**Solution-Processable Nanowire Field-Effect Transistors**

Maxim Shkunov, Grigorios Rigas and Marios Constantinou

Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/intechopen.68800

#### **Abstract**

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jp0757816

78 Nanowires - New Insights

nl303920b

between TiO2

doi/abs/10.1021/nn900863a

com/10.1002/adma.201204192

Solution-processable single-crystalline inorganic semiconducting nanowires are excellent building blocks for printable electronics requiring high performance of semiconducting components. Excellent charge carrier mobilities of crystalline nanowires combined with solvent-based nanowire processing open up possibilities for low-cost nanowire electronics targeting a variety of applications ranging from flexible circuits to chemical and biological sensors. Nanowire field-effect transistors are key devices for most of such applications. Recent developments in controllable nanowire positioning and orientation on the substrates and electrical property selection provide the necessary technological breakthroughs enabling the fabrications of reproducible nanowire transistors. In this chapter, we discuss the nanowire assembly methods and high-spatial-resolution scanning probe microscopy techniques towards scalable fabrication of high-performance printable nanowire field-effect transistors.

**Keywords:** inorganic semiconducting nanowires, printed electronics, field-effect transistors, solution processability

## **1. Introduction**

The growing interest for printed electronics using functional nanomaterials is due to a plethora of conventional and novel applications that can be generated at a fraction of the cost as compared to conventional microelectronic device fabrication involving multiple photolithographic and etching steps. These applications include flexible circuits [1], biological and chemical sensors [2–4], photovoltaic and piezo energy harvesting [5–7], low-dissipation power electronics [8], terahertz detectors [9, 10], memory storage devices [11], artificial e-skin sensors [12], flexible displays [13] and optoelectronic devices [14] including lasers [15, 16]. One-dimensional inorganic semiconductors in the form of single-crystalline nanowires

© 2017 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

(NWs) hold most of the promise to act as a backbone for these applications. This is due to nanowires' excellent charge transport properties, the availability of both direct and indirect bandgap semiconducting materials, high aspect ratios allowing nanowires to bridge typical device electrode gaps, solution processability, chemical stability, room temperature deposition capabilities and compatibility with a variety of substrates including both rigid and flexible substrates such as plastics and paper. Separation of nanowire growth from the device assembly allows to employ low-temperature, bottom-up device fabrication approach utilising solution processing of nanowire devices. General nanowire device fabrication process flow is illustrated in **Figure 1**, where synthesised nanowires are dispersed in organic solvents for form functional inks, and then solution-based deposition is used to assemble nanowires on substrates, ideally with a good degree of nanowire orientation and positioning in respect to device electrodes. Density of nanowires after solvent-based disposition is defined by the type of the device and can vary significantly from monolayer coverage for transistor devices to very dense layers intended as energy storage electrodes in, for example, Li-ion batteries [17]. The devices are then finished by depositing the required counter-electrodes, dielectric

**Figure 1.** A concept of printable nanowire electronics on flexible substrates, where NW powder (a) is dispersed to form semiconducting nanowire inks (b), followed by aligned deposition of nanowires between device electrodes (c), and finished device can be fabricated at low-temperature process compatible with plastic substrates (d). (b) shows example of ZnO NW ink on the left and Si NW ink on the right.

layers and conducting tracks and also encapsulation layers, if devices need protection from the environment.

Reproducible positioning and alignment of nanowires with respect to device electrodes have been one of the key challenges in solution-processed nanowire electronics and has attracted a significant research effort. Advances toward nanowire assembly from liquid-based 'inks' onto device substrates are discussed in Section 3, paying attention to positioning, alignment and orientation. Recent progress toward selective nanowire deposition using dielectrophoresis is discussed in relation to separation of nanowires with different physical dimensions, such as lengths, and also selection based on the their electrical properties and types of nanowires.

Nanowire surface states play an important role in the corresponding device electrical characteristics, and large surface-to-volume ratio of nanowires opens, on one hand, enormous opportunities for surface receptor functionalisation toward chemical and biological sensors and, on the other hand, can lead to undesirable electrical hysteresis effects due to the presence of surface trap states that need to be eliminated. Further discussion of nanowire surface functionalisation and passivation methods towards stable, hysteresis-free device operation is described in Section 4.

Multiple nanowire channel devices raise particular characterisation challenges associated with both good contact formation between the nanowires and electrodes and also the need to identify nanowires which fully connect the device electrodes and those that do not participate in the conduction mechanism. Characterisation methods based on conducting scanning probe microscopy techniques are discussed in Section 5 in relation to conducting and semiconducting nanowires to probe their positioning, morphology, conductivities and other physical parameters.

## **2. Nanowire transistor device structures**

(NWs) hold most of the promise to act as a backbone for these applications. This is due to nanowires' excellent charge transport properties, the availability of both direct and indirect bandgap semiconducting materials, high aspect ratios allowing nanowires to bridge typical device electrode gaps, solution processability, chemical stability, room temperature deposition capabilities and compatibility with a variety of substrates including both rigid and flexible substrates such as plastics and paper. Separation of nanowire growth from the device assembly allows to employ low-temperature, bottom-up device fabrication approach utilising solution processing of nanowire devices. General nanowire device fabrication process flow is illustrated in **Figure 1**, where synthesised nanowires are dispersed in organic solvents for form functional inks, and then solution-based deposition is used to assemble nanowires on substrates, ideally with a good degree of nanowire orientation and positioning in respect to device electrodes. Density of nanowires after solvent-based disposition is defined by the type of the device and can vary significantly from monolayer coverage for transistor devices to very dense layers intended as energy storage electrodes in, for example, Li-ion batteries [17]. The devices are then finished by depositing the required counter-electrodes, dielectric

80 Nanowires - New Insights

**Figure 1.** A concept of printable nanowire electronics on flexible substrates, where NW powder (a) is dispersed to form semiconducting nanowire inks (b), followed by aligned deposition of nanowires between device electrodes (c), and finished device can be fabricated at low-temperature process compatible with plastic substrates (d). (b) shows example

of ZnO NW ink on the left and Si NW ink on the right.

Field-effect transistors (FETs) are key building blocks for modern electronics as they provide a variety of functions essential for analogue and digital electronics. Printable electronic fabrication approach is highly beneficial for a variety of senor transistor applications, including chemical and biological sensing and tensile and optical sensing, where extremely dense transistor integration is not required, and in many cases, sensors need to be positioned some distance apart from each other to allow, for example, transistor functionalisation with chemical or biological receptors.

Traditional microelectronic fabrication involves mainly top-down processes, such as masking; etching; stripping; ion implantation, with multiple photolithographic steps; and hightemperature annealing (often around 900°C), resulting in high amount of chemical waste required for the processing and very significant amount of energy use.

Printable electronics is based around the concept of bottom-up fabrications with additive manufacturing steps aimed at building the devices by functional inks printing and deposition techniques involving consecutive printing of conducting, semiconducting, and dielectric layers and components. These functional inks thus need to contain nanoparticles and/or material providing the necessary properties. Examples include semiconducting nanowire inks, metal nanoparticle inks and polymer dielectric inks. Printable nanowire FETs can be fabricated by various deposition techniques, with specifics related to the particular conductor, semiconductor, or dielectric materials. Metal nanoparticle ink deposition for nanowire FET electrodes, for example, can be performed by ink-jet printing [18], whereas popular gate dielectric deposition for NW FETs is by spin-coating polymer insulator materials [19]. Semiconductor nanowire transistor channel plays a defining role in the FET operation, so more attention will be devoted to the NW assembly as discussed in the next section.

FET device structures that are fully compatible with solution-based printing fabrication belong to thin-film transistor family and are represented by bottom-gate FETs and top-gate FETs. **Figure 2** is showing schematics for both types of NW FETs.

Top- and bottom-gate NW FET structures each have particular advantages: Bottom-gate structure is ideal for sensing applications, where NW channel area is fully exposed on the top to chemical or biological analytes. Additionally, bottom-gate design offers straightforward device prototyping when using commercially available oxidised silicon (Si/SiO2 ) wafers, which can be directly used as the substrate, incorporating conducting common gate, highly doped Si and gate dielectric SiO2 . Such substrates are also highly amenable for ink-jet printing for electrode deposition.

Top-gate transistor architecture allows better gate control over nanowire channel due to wrap-around gate dielectric geometry, naturally occurring after the dielectric deposition. Importantly, top-gate FETs demonstrate improved environmental stability due to nanowire channel encapsulation provided by the gate dielectric together with metal gate electrode covering the channel, thus protecting nanowires from atmospheric exposure [20].

Main challenges in printable NW FET fabrication (Section 3) are due to deposition and controllable alignment of nanowires, which need to bridge the device electrodes; reproducible number of nanowires in FETs; and solvent-based deposition and alignment compatible with large-scale printing.

**Figure 2.** Schematics of bottom-gate (a) and top-gate (b) nanowire FETs.

Surface states are always present in nanomaterials due to their high surface area, and they play an important role in nanowire device performance. Thus, interface properties of nanowires need to be controlled to eliminate unwanted electrical hysteresis effects as discussed in Section 4.

## **3. Nanowire assembly**

ers and components. These functional inks thus need to contain nanoparticles and/or material providing the necessary properties. Examples include semiconducting nanowire inks, metal nanoparticle inks and polymer dielectric inks. Printable nanowire FETs can be fabricated by various deposition techniques, with specifics related to the particular conductor, semiconductor, or dielectric materials. Metal nanoparticle ink deposition for nanowire FET electrodes, for example, can be performed by ink-jet printing [18], whereas popular gate dielectric deposition for NW FETs is by spin-coating polymer insulator materials [19]. Semiconductor nanowire transistor channel plays a defining role in the FET operation, so more attention will be devoted

FET device structures that are fully compatible with solution-based printing fabrication belong to thin-film transistor family and are represented by bottom-gate FETs and top-gate

Top- and bottom-gate NW FET structures each have particular advantages: Bottom-gate structure is ideal for sensing applications, where NW channel area is fully exposed on the top to chemical or biological analytes. Additionally, bottom-gate design offers straightfor-

which can be directly used as the substrate, incorporating conducting common gate, highly

Top-gate transistor architecture allows better gate control over nanowire channel due to wrap-around gate dielectric geometry, naturally occurring after the dielectric deposition. Importantly, top-gate FETs demonstrate improved environmental stability due to nanowire channel encapsulation provided by the gate dielectric together with metal gate electrode cov-

Main challenges in printable NW FET fabrication (Section 3) are due to deposition and controllable alignment of nanowires, which need to bridge the device electrodes; reproducible number of nanowires in FETs; and solvent-based deposition and alignment compatible with

. Such substrates are also highly amenable for ink-jet printing

) wafers,

ward device prototyping when using commercially available oxidised silicon (Si/SiO2

ering the channel, thus protecting nanowires from atmospheric exposure [20].

**Figure 2.** Schematics of bottom-gate (a) and top-gate (b) nanowire FETs.

to the NW assembly as discussed in the next section.

doped Si and gate dielectric SiO2

for electrode deposition.

82 Nanowires - New Insights

large-scale printing.

FETs. **Figure 2** is showing schematics for both types of NW FETs.

The bottom-up fabrication approach for nanowire transistors relies on the availability of grown nanowire materials and also on the efficient assembly methods for nanowire solvent-based deposition. The NW synthesis has been demonstrated using various methods, including supercritical fluid-liquid-solid growth (SFLS) for Si and Ge NWs [21], vapour liquid solid (VLS) growth for Si nanowires and the laser ablation for SnO2 nanowires [22]. For the preparation of the NW formulations, the as-synthesised NWs are typically dispersed in various organic solvents using lowpower sonication process for short periods of time to gently remove nanowires from the growth substrates and to promote homogeneous distribution of nanowire materials in the solvent.

Nanowire deposition and alignment on device substrates represent the next fabrication step. Several self-assembly techniques have been developed in the past for transferring the NWs onto the microelectrode structures to form the conducting channels of the FET devices. The main challenges in self-assembly are the precise alignment and positioning of the nanowires on predefined electrode areas and the purification and selection of nanowires with desired electrical properties. Most of the reported assembly techniques, apart from dielectrophoresis (DEP) provide no or very limited control of NW lateral alignment and no electrical properties selection. In this section, various NW deposition methods are discussed, and more attention is paid to the DEP process enabling electrical and morphological properties' selectivity.

#### **3.1. Nanowire alignment techniques**

A number of techniques have been developed for the alignment and deposition of NWs on the substrates, including Langmuir-Blodgett (LB), blown-bubble films (BBF), flow-directed assembly, electrostatic interactions, mechanical shear forces and electric field-assisted assembly with dielectrophoresis.

The Langmuir-Blodgett deposition is a very powerful technique for the alignment of highdensity arrays of parallel nanostructures over large areas with a precise spacing between nanoparticles from μm down to nm scale. The method was first reported for barium chromate nanorods [23], with inspiration taken from centuries-old technique for timber-floating on rivers [24]. The technique has been adapted and developed to assemble a variety of nanowires from metallic silver NWs [25] to semiconducting nanowires, including silicon [26]. In the LB technique, the surfactant-wrapped NWs (e.g. 1-octadecylamine) are dispersed on the water surface of a Langmuir-Blodgett trough. Due to the impartial surfactant's solubility in water, the NWs are floating on the surface of the trough. Then, computer-controlled barriers, positioned at the edges of the LB trough, slowly compress the NWs to a higher density at the surface. The density of the monolayer, which depends on NW-to-NW stacking, is mainly limited by the amount of the suspended NWs, and their direction of alignment is dictated by the barrier orientation of the LB trough. Barrier compression causes NWs to reorient and to align parallel to the trough barrier edge, forming a highly dense monolayer. Then the NW layer can be transferred to a substrate, such as silicon wafer; however, some degree of misalignment can occur during the transfer of nanowire from the surface of the trough onto the solid substrate. This LB technique is compatible with large-area electronic fabrication; however, it is difficult to control the NW alignment yield and reproducibility of the alignment on top of the FET sourcedrain electrode structures [25, 26], and no lateral nanowire alignment is typically obtained.

The blown-bubble film assembly technique is able to provide uniformly aligned and controlled density of NW by utilising a bubble expansion process [27]. The surface of nanomaterials is chemically functionalised, and then, nanowires are mixed with epoxy resin. For example, Si NWs are modified using 5,6-epoxyhexyltriethoxysilane, dispersed into tetrahydrofuran and then homogenously mixed with a known mass of epoxy resin. Afterward, a bubble is expanded from the epoxy-nanomaterial viscous formulation at a controlled direction and speed, and then bubble surface is touched by a substrate to transfer the nanowires resulting in well-defined nanomaterial-incorporated thin films. The alignment of the nanomaterials is mainly attributed to the shear stress present in the epoxy fluid during the bubble expansion

**Figure 3.** (a) Schematic of the BBF technique. The nanomaterials are dispersed in polymer solution, the solution is expanded as a bubble using a die, and then the uniformly aligned nanomaterials are transferred to different substrates including plastics. (b) Optical image of 6 inch Si wafer with aligned Si NWs (scale bar, 10 μm). (c) Density vs. concentration curve, indicating the density can be controlled by loading a percentage of nanomaterials [27]. © The Royal Society of Chemistry 2008.

process (**Figure 3a**). The viscosity of the homogeneous solution is the key parameter for the uniform distribution of nanomaterials in the resulting bubble films (**Figure 3b**–**c**). This technique provides a dense and uniform NW distribution suitable for large-area applications, and it is applicable to both rigid and flexible substrates. Although, it requires a large sample volume of NWs, the residual epoxy resin needs to be removed in order to define electrical contacts for NW FET applications, and it is difficult to control the number of the aligned NWs across the source-drain FET electrodes [27]

surface. The density of the monolayer, which depends on NW-to-NW stacking, is mainly limited by the amount of the suspended NWs, and their direction of alignment is dictated by the barrier orientation of the LB trough. Barrier compression causes NWs to reorient and to align parallel to the trough barrier edge, forming a highly dense monolayer. Then the NW layer can be transferred to a substrate, such as silicon wafer; however, some degree of misalignment can occur during the transfer of nanowire from the surface of the trough onto the solid substrate. This LB technique is compatible with large-area electronic fabrication; however, it is difficult to control the NW alignment yield and reproducibility of the alignment on top of the FET sourcedrain electrode structures [25, 26], and no lateral nanowire alignment is typically obtained.

The blown-bubble film assembly technique is able to provide uniformly aligned and controlled density of NW by utilising a bubble expansion process [27]. The surface of nanomaterials is chemically functionalised, and then, nanowires are mixed with epoxy resin. For example, Si NWs are modified using 5,6-epoxyhexyltriethoxysilane, dispersed into tetrahydrofuran and then homogenously mixed with a known mass of epoxy resin. Afterward, a bubble is expanded from the epoxy-nanomaterial viscous formulation at a controlled direction and speed, and then bubble surface is touched by a substrate to transfer the nanowires resulting in well-defined nanomaterial-incorporated thin films. The alignment of the nanomaterials is mainly attributed to the shear stress present in the epoxy fluid during the bubble expansion

**Figure 3.** (a) Schematic of the BBF technique. The nanomaterials are dispersed in polymer solution, the solution is expanded as a bubble using a die, and then the uniformly aligned nanomaterials are transferred to different substrates including plastics. (b) Optical image of 6 inch Si wafer with aligned Si NWs (scale bar, 10 μm). (c) Density vs. concentration curve, indicating the density can be controlled by loading a percentage of nanomaterials [27]. © The Royal Society of

Chemistry 2008.

84 Nanowires - New Insights

Highly aligned and dense nanowire packing was demonstrated by flow-directed assembly of nanowires in a microfluidic channel structure formed between poly(dimethylsiloxane) (PDMS) mould and a flat substrate (Si/SiO<sup>2</sup> modified with amine functionality). Assembled arrays of NWs, formed by passing the suspended NWs through the microfluidic channels, were aligned along the flow direction. The shear flow near the surface of the substrate immobilised the NWs and aligned them along the flow. At high flow rates, larger shear forces were produced and led to better alignment. This technique provided a controlled NW density and a flexibility to meet complex device configurations. However, the alignment process was attainable only for NWs with diameter <15 nm, it required the fabrication of microfluidic channels, it was challenging to scale up the process to large wafers, it was difficult to control the number of the aligned NWs across the source-drain FET electrodes and no lateral nanowire alignment was achievable [28, 29].

The electrostatic interaction method for nanowire assembly was developed by Heo et al. [30], and it relied on the electrostatic interactions of the positively charged surfaces of the semiconducting nanomaterials with the negatively charged surface of the substrate. Si NWs were functionalised with amine-terminated aminopropyltriethoxysilane (APTS) self-assembled monolayer (SAM) and well dispersed in aqueous solution. Then Si NWs were deposited on negatively charged substrates (i.e. SiO2 ) with hydrophobic octadecyltrichlorosilane patterns. Therefore, the positively charged NWs were attracted and aligned by the negatively charged APTS surface regions of the substrate. This technique was able to prepare arbitrarily shaped patterns using conventional microfabrication facilities; nonetheless it required the removal of the APTS SAM on the Si NWs with buffer oxide etching process.

A nanowire contact printing method was developed by et al. [31] which utilises the shear forces generated by mechanically sliding two solid surfaces, giving a high degree of order of assembled NWs. In this method two substrates are needed, namely, the donor and the receiver substrate. The donor substrate is covered with a dense "lawn" of NWs, while the receiver is coated with lithographically patterned resist. The method is based on a contact printing process by sliding the surfaces of the two substrates against each other under gentle pressure (**Figure 4a**). Also, lubricant is used to minimise the NW-NW mechanical friction and their uncontrolled breakage during the sliding process. During printing, NWs are transferred from the donor substrate to the receiver substrate by the van der Waals interactions, resulting in the direct alignment of a dense monolayer array of NWs (**Figure 4b**–**e**). This technique offers the ability to transfer monolayer arrays of NWs on both rigid and flexible substrates with a controllable density. The disadvantage of this technique is the lack of control of the number of the aligned NWs across the source-drain FET electrodes, and NWs tend to break during the transfer process [29, 31].

**Figure 4.** (a) A schematic illustration of the contact printing method. (b) Optical image of the assembly of Ge NWs on a Si/SiO2 substrate. (c–d) Optical images of a cross assembly printing of Si NWs. (e) Printed Ge NWs on a 4 inch Si/SiO2 wafer, including an inset SEM image of the printed NWs [31]. © 2008 American Chemical Society.

The electric field-assisted assembly known as dielectrophoresis (DEP) is currently the most promising nanowire assembly technique for the self-alignment of nanomaterials. During a DEP process, a polarisable nanoparticle, suspended in a liquid, is subjected to a non-uniform alternating electric field (AC), and its charges separate and accumulate at the surface, forming a dipole, which experiences the force dependent on the gradient of the electric field resulting in NW self-assembly across the electrode gap [32, 33]. The working principle of DEP is based on the balancing of NW-NW interaction and dielectrophoretic and opposing hydrodynamic drag forces. When the NW "ink" (nanowire dispersion) flows over the electrode gap with applied AC electric field, it gets polarised and attracted to the regions with the strongest electric field gradient, resulting in nanowire deposition across the electrode gap by means of dielectrophoretic forces (FDEP), as illustrated in **Figure 5a**. The deposition of NWs across the FET source-drain electrodes mainly depends on the difference in the dielectric properties (ε) of the nanomaterial and the medium, based on the Clausius-Mossotti factor (CMF) and the electric field gradient. As opposed to previously mentioned nanowire assembly techniques, the DEP method requires very small volumes of NW dispersion (a few μL per DEP alignment), and it offers a precise, dense and controllable deposition of NW monolayer arrays on predefined electrode structures with a high degree of orientation control as shown in **Figure 5b**–**d**. The NW density can be controlled by tailoring the NW concentration in the formulation and the applied DEP signal voltage [33, 34].

#### **3.2. Self-assembly and purification of nanowires**

Some of the key challenges in solution-processed NW applications are the simultaneous purification, selection, and alignment of NWs on the desired substrate areas, which have attracted

**Figure 5.** (a) Graphical illustration of dielectrophoretic assembly [1]. © 2012 American Chemical Society. (b) Optical image of NW assembly on eight multi-finger electrode arrays of total 96 sites (scale bar, 200 μm). (c) Precision alignment of NWs on a single sense array (scale bar, 20 μm). (d) Deep ultraviolet image of a NW aligned on a single electrode (scale bar, 4 μm) [34]. © 2010 Macmillan Publishers Limited.

a significant research effort. Despite the substantial progress in NW assembly demonstrated with LB, BBF, flow-directed assembly, electrostatic interactions and mechanical shear forces, the simultaneous precise deposition of NWs with respect to device electrodes and the selective deposition of NWs based on morphological or electrical properties received little attention, and NWs were typically deposited as-synthesised, which affected device reproducibility, performance and reliability.

The electric field-assisted assembly known as dielectrophoresis (DEP) is currently the most promising nanowire assembly technique for the self-alignment of nanomaterials. During a DEP process, a polarisable nanoparticle, suspended in a liquid, is subjected to a non-uniform alternating electric field (AC), and its charges separate and accumulate at the surface, forming a dipole, which experiences the force dependent on the gradient of the electric field resulting in NW self-assembly across the electrode gap [32, 33]. The working principle of DEP is based on the balancing of NW-NW interaction and dielectrophoretic and opposing hydrodynamic drag forces. When the NW "ink" (nanowire dispersion) flows over the electrode gap with applied AC electric field, it gets polarised and attracted to the regions with the strongest electric field gradient, resulting in nanowire deposition across the electrode gap by means of dielectrophoretic forces (FDEP), as illustrated in **Figure 5a**. The deposition of NWs across the FET source-drain electrodes mainly depends on the difference in the dielectric properties (ε) of the nanomaterial and the medium, based on the Clausius-Mossotti factor (CMF) and the electric field gradient. As opposed to previously mentioned nanowire assembly techniques, the DEP method requires very small volumes of NW dispersion (a few μL per DEP alignment), and it offers a precise, dense and controllable deposition of NW monolayer arrays on predefined electrode structures with a high degree of orientation control as shown in **Figure 5b**–**d**. The NW density can be controlled by tailoring the NW concentration in the formulation and the applied DEP signal voltage [33, 34].

**Figure 4.** (a) A schematic illustration of the contact printing method. (b) Optical image of the assembly of Ge NWs on a

wafer, including an inset SEM image of the printed NWs [31]. © 2008 American Chemical Society.

substrate. (c–d) Optical images of a cross assembly printing of Si NWs. (e) Printed Ge NWs on a 4 inch Si/SiO2

Some of the key challenges in solution-processed NW applications are the simultaneous purification, selection, and alignment of NWs on the desired substrate areas, which have attracted

**3.2. Self-assembly and purification of nanowires**

Si/SiO2

86 Nanowires - New Insights

The first precise orientation positioning, selective deposition and separation of single Si NWs based on their electrical quality from a mixture of other types of nanowires were demonstrated using DEP with capillary assembly by Collet et al. [35]. The combination of both DEP and capillary assembly involved dragging the liquid meniscus of the NW solution on top of the substrate, with a controlled velocity and temperature which led to the trapping of single NWs by the DEP forces on predefined locations coupled with the capillary force acting to align the nanowires. The DEP force trapped the NWs and also adjusted their orientation at the surface of the electrodes followed by the liquid evaporation. A mixture of monodispersed Si, ZnO and InAs nanowires dispersed in isopropanol was used in this study.

The precise orientation of the NWs was achieved by employing stronger electronic polarisation along the long NW axis as compared to the short axis under the application of the AC electric field. In the case of Si NWs, the optimum capture frequency was obtained at 50 kHz and for InAs and ZnO were 500 kHz and 2 MHz, respectively. The authors argued that each NW exhibits its own specific signature based on their electrical properties, which leads to the assembly of different nanostructures at different frequencies. As a proof of concept, the authors provided separation and precise alignment of single Si and InAs nanowires from NW mixture containing both types of nanowires, into alternating columns on the substrate, by switching the applied frequency between 50 and 500 kHz in each column of DEP electrodes, once the meniscus of the NW solution reached the desired set of electrodes. This work has successfully demonstrated a separation of nanowires with different electrical conductivities by examining their optimum capture frequency, which is influenced by the conductivity and level of doping.

Key progress in DEP nanowire selection and purification was demonstrated by Constantinou et al. [33] by developing a scalable one-step solution process for the selection, collection and ordered assembly of Si NW arrays (**Figure 6a**) with desired electrical properties from a polydisperse as-synthesised NW dispersions. The method was applied to SFLS-grown Si NWs with various lengths, diameters and electrical conductivities. The technique utilised the fluidic shear forces coupled with DEP self-alignment to position high-quality NWs with the lowest level of traps across the electrode gap and to remove weakly interacting NWs and

**Figure 6.** (a) Graphical illustration of the fluidic shear force with DEP technique used for the NW deposition and DEP alignment. The substrate was tilted at approximately 30° angle (versus horizontal plane) to provide gravity-assisted flow of NW dispersion. (b) Length histogram of NWs collected by DEP across two different electrode gaps, 10 and 20 μm. Controllable DEP alignment of SFLS Si NWs across parallel electrode bas with 10 μm spacing at (c) 5 V, (d) 10 V, (e) 15 V and (f) 20 V. (g) Subthreshold swing (s-s) and NW trap density (Ntrap) data extracted from transfer characteristics of FETs for NWs collected from 100 kHz to 5 MHz [33]. © 2016 American Chemical Society.

impurities from the device channel region. The DEP assembly process employed a drop-cast method on an inclined substrate to provide a gravity-assisted slow flow of NW formulations perpendicular to the pre-patterned DEP electrode gap after the DEP sinusoidal signal was applied (**Figure 6c–f**). The DEP selectivity based on the NW electrical parameters was controlled by altering the frequency dependence of the DEP force. The DEP method coupled with fluidic shear forces offered a high degree of flexibility for NW positioning with NWs being oriented along the channel and perpendicular to the electrode edges. Importantly, the DEP also served as a nanowire length selection tool by providing the strongest interactions for the NWs with lengths at least the same size as the electrode gap or slightly longer opening the possibility for a sequential separation of NWs by length (**Figure 6b**). Main advancement of the method was in systematical examination of the electrical response of the Si NWs aligned at various DEP signal frequencies. It was highlighted that the FDEP is frequency dependent and the level of polarisability is related to the conductivity of the nanostructure, allowing the selection of highly conducting NWs by altering the applied DEP frequency. Thus, lower frequency range collects NWs with various qualities including poor quality that may contain defects and associated traps, while high frequencies induce the collection of only the highest quality, low-defect semiconducting Si NWs, with higher conductivity. The electrical properties of the NWs aligned at various frequencies were compared using FET devices by extracting both subthreshold swing (s-s) and trap density (Ntrap) data as shown in **Figure 6g** and via conducting atomic force microscopy analysis. As a proof of concept, high-performance Si NW FETs with excellent performance were demonstrated with high FET on-currents in the mA range and low subthreshold swing (s-s) and trap density.

The proposed methodology enables the effective selection and assembly of heterogeneous nanowires of any type and provides a printed electronic fabrication approach that can be scaled up for industrial applications.

## **4. Surface modification approaches for nanowire FETs**

switching the applied frequency between 50 and 500 kHz in each column of DEP electrodes, once the meniscus of the NW solution reached the desired set of electrodes. This work has successfully demonstrated a separation of nanowires with different electrical conductivities by examining their optimum capture frequency, which is influenced by the conductivity and

Key progress in DEP nanowire selection and purification was demonstrated by Constantinou et al. [33] by developing a scalable one-step solution process for the selection, collection and ordered assembly of Si NW arrays (**Figure 6a**) with desired electrical properties from a polydisperse as-synthesised NW dispersions. The method was applied to SFLS-grown Si NWs with various lengths, diameters and electrical conductivities. The technique utilised the fluidic shear forces coupled with DEP self-alignment to position high-quality NWs with the lowest level of traps across the electrode gap and to remove weakly interacting NWs and

**Figure 6.** (a) Graphical illustration of the fluidic shear force with DEP technique used for the NW deposition and DEP alignment. The substrate was tilted at approximately 30° angle (versus horizontal plane) to provide gravity-assisted flow of NW dispersion. (b) Length histogram of NWs collected by DEP across two different electrode gaps, 10 and 20 μm. Controllable DEP alignment of SFLS Si NWs across parallel electrode bas with 10 μm spacing at (c) 5 V, (d) 10 V, (e) 15 V and (f) 20 V. (g) Subthreshold swing (s-s) and NW trap density (Ntrap) data extracted from transfer characteristics of FETs

for NWs collected from 100 kHz to 5 MHz [33]. © 2016 American Chemical Society.

level of doping.

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The undesirable electrical hysteresis effect in NW FETs is one of the main sources for performance instabilities, which affects the reproducibility and potential applications of NW FETs such as sensors, circuits elements and logic gates, that causes a shift in the threshold voltage (VTH) during normal device operation under gate bias stress. In most FET applications, besides memory devices, even a small degree of hysteresis is unwanted.

The hysteresis behaviour mainly originates from electron or hole trapping/detrapping at the semiconductor/insulator interface due to dielectric surface functionalities and adsorbed small molecules (e.g. oxygen and water). Typically such interface trapping is very strongly pronounced in bottom-gate NW FETs with SiO<sup>2</sup> gate dielectric [36], where silanol groups trap charges at the interfacial layer between the semiconductor material and the gate dielectric [37]. In NW FETs, the hysteresis also originates from the NW surface traps, and it is observed in moisture-free environments and ambient air conditions, highlighting the demand for NW passivation. In this section, we describe NW surface passivation methods with an oxide shell for minimising hysteresis effects.

### **4.1. Silicon nanowire surface passivation methods**

The majority of the NW surface passivation methods include high-temperature annealing which is not suitable for plastic electronic applications. However, successful passivation results for Chemical Vapour Deposition grown Si NWs have been demonstrated by Kawashima et al. [38] and Wang et al. [39]. Both approaches focused on the synthesis of core-shell Si NWs with the core acting as a channel and the shell acting as a gate dielectric.

Kawashima et al. [38] investigated the growth of a 24-nm thermal oxide layer on the surface of Si NWs (forming a core-shell structure) using rapid thermal processing in an oxygen atmosphere at 1100°C for 2–6 min. The authors compared the I–V characteristics of bare and core-shell Si NW FETs, although hysteresis appeared in both cases with a much smaller effect on the core-shell Si NW FETs than the bare Si NW FETs. The results proved that the hysteresis is drastically reduced by the formation of the oxide shell around the Si NW core, effectively passivating the Si NW surface and preventing the adsorption of oxygen and moisture which cause hysteresis. In a similar approach by Wang et al. [39], a silicon nanowire core was covered with a 10-nm-thick SiO2 shell at lower annealing temperature (700°C) but for a much longer time duration (4 h), also resulting in near-zero hysteresis in devices.

A different approach [40] demonstrated thermal oxidation using ozone for forming a good quality 5-nm-thick SiO2 shell layer obtained at 600°C processing temperature. However, such high-temperature annealing is not fully suitable for printed electronic applications, and a low-temperature process is still required.

A very efficient method for nanowire passivation that results in a dramatic reduction of surface trap states on Si NWs was demonstrated by Constantinou et al. [41]. This method is ideally suited for nanomaterials intended for printed electronic applications, as it is quick, fully solution based and conducted at room temperature and normal pressure. The passivation phenomenon was directly linked to the interfacial mild oxidation effect induced by the processing solvent.

Dimethylformamide (DMF) solvent treatment was used to directly reduce the hysteresis effect in solution-processed SFLS-grown Si NW FET devices [41]. The choice of solvents for the NW dispersion had a dramatic impact on the NW surface trap density and on the hysteresis effect. The undoped Si NWs were dispersed in both anisole and DMF, with DMF solvent-processed FETs exhibiting significantly low hysteresis of ~3 V, with the lowest reported hysteresis value being 0.1 V (**Figure 7a**), whereas the average hysteresis values of FETs based on nanowires dispersed in anisole were 25–32 V. Thus, DMF passivation effect of the Si NW shell resulted in a drastically suppressed NW FET hysteresis with up to 300 times (from 32 to 0.1 V) reduction as compared to anisole dispersion solvent [41]. For the investigation of the NW surface passivation, high-resolution X-ray photoelectron spectroscopy (XPS) technique was used to analyse the surface of the DMF- and anisole-treated Si NWs. It was observed that DMF-treated Si NWs showed a significant 35% increase of SiO<sup>2</sup> composition of NW shell around the core compared to the reference sample (dry NWs) as shown in **Figure 7b**. The formation of a SiO2 -rich shell passivates the Si core channel area and provides stability against environmental ageing and prevents the adsorption of water molecules that are responsible for the hysteretic behaviour of the Si NW FETs (**Figure 7c**). As a further study, the DMF-treated devices were exposed to

**Figure 7.** (a) I–V characteristics of DMF-treated Si NW FET showing a very low hysteresis of 0.1 V. (b) XPS highresolution spectrum of the Si2p region of SFLS-grown Si NWs dispersed in anisole and DMF. (c) HRTEM image of Si NW dispersed in DMF showing a single crystal silicon core with 30 nm diameter and 5–8-nm-thick amorphous oxidised polyphenylsilane shell [41]. © 2015 American Chemical Society.

ambient conditions for 1000 h showing environmental stability, with a marginal increase of the hysteresis. In summary, the simplicity and effectiveness of solution-based mild oxidation methods offer fast passivation technological solution for printable nanowire-based electronics.

## **5. Scanning probe microscopy techniques for the characterisation of nanowires and devices**

## **5.1. Introduction to conducting atomic force microscopy**

**4.1. Silicon nanowire surface passivation methods**

ered with a 10-nm-thick SiO2

low-temperature process is still required.

showed a significant 35% increase of SiO<sup>2</sup>

quality 5-nm-thick SiO2

90 Nanowires - New Insights

the core acting as a channel and the shell acting as a gate dielectric.

longer time duration (4 h), also resulting in near-zero hysteresis in devices.

The majority of the NW surface passivation methods include high-temperature annealing which is not suitable for plastic electronic applications. However, successful passivation results for Chemical Vapour Deposition grown Si NWs have been demonstrated by Kawashima et al. [38] and Wang et al. [39]. Both approaches focused on the synthesis of core-shell Si NWs with

Kawashima et al. [38] investigated the growth of a 24-nm thermal oxide layer on the surface of Si NWs (forming a core-shell structure) using rapid thermal processing in an oxygen atmosphere at 1100°C for 2–6 min. The authors compared the I–V characteristics of bare and core-shell Si NW FETs, although hysteresis appeared in both cases with a much smaller effect on the core-shell Si NW FETs than the bare Si NW FETs. The results proved that the hysteresis is drastically reduced by the formation of the oxide shell around the Si NW core, effectively passivating the Si NW surface and preventing the adsorption of oxygen and moisture which cause hysteresis. In a similar approach by Wang et al. [39], a silicon nanowire core was cov-

A different approach [40] demonstrated thermal oxidation using ozone for forming a good

high-temperature annealing is not fully suitable for printed electronic applications, and a

A very efficient method for nanowire passivation that results in a dramatic reduction of surface trap states on Si NWs was demonstrated by Constantinou et al. [41]. This method is ideally suited for nanomaterials intended for printed electronic applications, as it is quick, fully solution based and conducted at room temperature and normal pressure. The passivation phenomenon was directly linked to the interfacial mild oxidation effect induced by the processing solvent.

Dimethylformamide (DMF) solvent treatment was used to directly reduce the hysteresis effect in solution-processed SFLS-grown Si NW FET devices [41]. The choice of solvents for the NW dispersion had a dramatic impact on the NW surface trap density and on the hysteresis effect. The undoped Si NWs were dispersed in both anisole and DMF, with DMF solvent-processed FETs exhibiting significantly low hysteresis of ~3 V, with the lowest reported hysteresis value being 0.1 V (**Figure 7a**), whereas the average hysteresis values of FETs based on nanowires dispersed in anisole were 25–32 V. Thus, DMF passivation effect of the Si NW shell resulted in a drastically suppressed NW FET hysteresis with up to 300 times (from 32 to 0.1 V) reduction as compared to anisole dispersion solvent [41]. For the investigation of the NW surface passivation, high-resolution X-ray photoelectron spectroscopy (XPS) technique was used to analyse the surface of the DMF- and anisole-treated Si NWs. It was observed that DMF-treated Si NWs

to the reference sample (dry NWs) as shown in **Figure 7b**. The formation of a SiO2 -rich shell passivates the Si core channel area and provides stability against environmental ageing and prevents the adsorption of water molecules that are responsible for the hysteretic behaviour of the Si NW FETs (**Figure 7c**). As a further study, the DMF-treated devices were exposed to

shell at lower annealing temperature (700°C) but for a much

composition of NW shell around the core compared

shell layer obtained at 600°C processing temperature. However, such

Scanning probe microscopy (SPM) techniques evolved quite rapidly over the last two decades for incorporating additional modes beyond conventional topography [42, 43] and were able to provide additional characterisation information in comparison with traditional nanomaterial electron microscopy techniques such scanning electron microscopy. Driven by the introduction of novel one-dimensional conducting and semiconducting nanomaterials, SPM coupled with electrical modes became an integral part for the development and further understanding of these materials due to the unique capability of extracting critical information about the electrical properties of nanoparticles with a spatial resolution comparable to their nanoscale size [44, 45]. By combining this new level of information with conventional topography data [46], a correlation between structural and electrical properties can be established, thus enabling further optimisation of nanoparticles' growth and device integration mechanisms. In this section, the discussion will focus on recent advances in the field of conductive atomic force microscopy (c-AFM) for nanowire characterisation.

c-AFM is a current-based sensing technique for mapping the conductivity variations in samples. It utilises a conductive AFM tip which is brought in contact with a biased sample. During the scan, any current flowing through the sample and into the tip is recorded, forming a current map of the scanned surface (**Figure 8**). c-AFM can simultaneously map the topography and current distribution of a sample (**Figure 9**), thus making it ideal for evaluating defects formed during the fabrication of functional devices made with conducting or semiconducting NW networks.

**Figure 8.** Schematic of c-AFM operating principle [33]. © 2016 American Chemical Society.

In the pursue of solution processed, high conductivity and transparent alternatives to the ITO electrodes, commonly used in optoelectronic devices, metallic NWs were extensively studied [47–49]. One of the main fabrication challenges was the ability of the entire NW network to conduct and thus to minimise the effective sheet resistivity. Bridging the naturally occurring gaps between isolated nanowires during deposition (**Figure 9**) was considered of high importance, and several optimisation approaches were suggested [48, 50, 51]. While conventional measurement techniques can be employed for evaluating the conductivity improvement of these methods on the macroscopic scale, nanoscopic evaluation of the nanowire-to-nanowire connections requires a special approach. One of recent examples was based on using reduced graphene oxide (rGO) as a way of connecting discontinuities in silver nanowire (AgNW) networks [51]. c-AFM was successfully used for imaging these junctions and for proving the bridging effect induced by rGO flakes.

Example of metallic NWs acting as the electrode layer represents one of the most straightforward systems to be examined with c-AFM. Solution-processed nanowire electronics relies heavily on the active layers of the devices consisting of semiconducting NWs. Thus, efficient characterisation of nanowires, including FET device components and any defects on nanowires or contact areas, is essential for the advancement of printed electronics.

#### **5.2. c-AFM characterisation of nanowires with high spatial resolution**

As discussed in Section 3, the purification of NWs based on their electrical properties is essential for their efficient incorporation in functional devices. Establishing a relation between the nanowire deposition methods and the properties of assembled nanowires, with very high spatial resolution, is key for high-performance printable nanowire-based FETs. Recently, c-AFM technique was employed for probing the electrical properties of polydispersed Si NWs, after selection processes using different dielectrophoretic signal frequencies [33]. In order to

In the pursue of solution processed, high conductivity and transparent alternatives to the ITO electrodes, commonly used in optoelectronic devices, metallic NWs were extensively studied [47–49]. One of the main fabrication challenges was the ability of the entire NW network to conduct and thus to minimise the effective sheet resistivity. Bridging the naturally occurring gaps between isolated nanowires during deposition (**Figure 9**) was considered of high importance, and several optimisation approaches were suggested [48, 50, 51]. While conventional measurement techniques can be employed for evaluating the conductivity improvement of these methods on the macroscopic scale, nanoscopic evaluation of the nanowire-to-nanowire connections requires a special approach. One of recent examples was based on using reduced graphene oxide (rGO) as a way of connecting discontinuities in silver nanowire (AgNW) networks [51]. c-AFM was successfully used for imaging these junctions and for proving the

**Figure 8.** Schematic of c-AFM operating principle [33]. © 2016 American Chemical Society.

Example of metallic NWs acting as the electrode layer represents one of the most straightforward systems to be examined with c-AFM. Solution-processed nanowire electronics relies heavily on the active layers of the devices consisting of semiconducting NWs. Thus, efficient characterisation of nanowires, including FET device components and any defects on nanow-

As discussed in Section 3, the purification of NWs based on their electrical properties is essential for their efficient incorporation in functional devices. Establishing a relation between the nanowire deposition methods and the properties of assembled nanowires, with very high spatial resolution, is key for high-performance printable nanowire-based FETs. Recently, c-AFM technique was employed for probing the electrical properties of polydispersed Si NWs, after selection processes using different dielectrophoretic signal frequencies [33]. In order to

ires or contact areas, is essential for the advancement of printed electronics.

**5.2. c-AFM characterisation of nanowires with high spatial resolution**

bridging effect induced by rGO flakes.

92 Nanowires - New Insights

**Figure 9.** (a–b) c-AFM images including topography (a) and current maps (b) obtained for an AgNW network at a tip bias of 1.6 V. As deposited NWs may result in discontinuities which affect the sheet resistance of the layer. (c–d) Topography (c) and current maps (d) of isolated AgNWs, electrically connected using rGO [51]. © 2016 AIP Publishing.

investigate the conductivity of the low- and high-DEP frequency-selected NWs, c-AFM measurements were conducted with Si NW channels in real FETs. The devices were prepared with Si NWs assembled at DEP frequencies of 220 kHz and 5 MHz. The samples were biased at the drain electrode of the structure, as shown in **Figure 8**, with the conductive platinum-silicide AFM tip being in contact with the Si NWs to act as a ground electrode. Such two-terminal current measurement allows probing the NW conductivity directly, as a function of position. The material for the tip was chosen in order to reduce the contact resistance with the underlying semiconducting nanostructures, without increasing the cantilever deflection and thus allowing soft contact with the sample. By keeping the bias constant at 0.5 V and maintaining constant force applied to the AFM tip, the current maps for NW samples deposited at various DEP signal frequencies were obtained by scanning the samples in contact mode in the direction perpendicular to the NWs. Both conducting AFM current data and AFM topological data were collected at the same time allowing to differentiate the NWs deposited in the channel, but not electrically connected to the contacts, from NWs that were fully electrically connected.

**Figure 10** demonstrates typical images obtained for both height (AFM mode) and current (conducting mode) measurements of Si NWs aligned at different DEP frequencies. During the measurement, a common trend was observed that NWs collected using a high, 5 MHz, DEP signal showed ∼14 times higher current than the ones collected at low, 220 kHz, frequency. Current levels up to 233 pA were obtained for the NWs aligned at 5 MHz (**Figure 10b**), while peak

**Figure 10.** c-AFM data. (a) Height map of Si NWs aligned at 5 MHz and (b) the corresponding current map. Only one straight, fully electrically connected NW is visible in the image. (c) Height map of a NW aligned at 220 kHz and (d) its current map. Scale bars are 1 μm. Conducting Si NWs have similar diameters, (a) 33 nm and (c) 34 nm. All the images were obtained in the trace mode with a pixel size of 5.9 nm. NWs aligned at higher frequency showed higher peak currents up to 233 pA (b), compared to the 16-pA peak current found in the lower frequency assembled NWs (d) [33]. © 2016 American Chemical Society.

current values of 16 pA were measured for the ones assembled at 220 kHz (**Figure 10d**). These current differences between the NWs collected at high and low DEP signal frequencies were fully consistent with the transistor measurements, demonstrating that selective nanoparticle assembly at various dielectrophoretic frequencies is directly correlated with the conductivity of the NWs.

**Figure 10** demonstrates typical images obtained for both height (AFM mode) and current (conducting mode) measurements of Si NWs aligned at different DEP frequencies. During the measurement, a common trend was observed that NWs collected using a high, 5 MHz, DEP signal showed ∼14 times higher current than the ones collected at low, 220 kHz, frequency. Current levels up to 233 pA were obtained for the NWs aligned at 5 MHz (**Figure 10b**), while peak

**Figure 10.** c-AFM data. (a) Height map of Si NWs aligned at 5 MHz and (b) the corresponding current map. Only one straight, fully electrically connected NW is visible in the image. (c) Height map of a NW aligned at 220 kHz and (d) its current map. Scale bars are 1 μm. Conducting Si NWs have similar diameters, (a) 33 nm and (c) 34 nm. All the images were obtained in the trace mode with a pixel size of 5.9 nm. NWs aligned at higher frequency showed higher peak currents up to 233 pA (b), compared to the 16-pA peak current found in the lower frequency assembled NWs (d) [33]. ©

2016 American Chemical Society.

94 Nanowires - New Insights

Incorporation of semiconducting NWs into functional devices requires to consider surface oxide properties as well, to enable the efficient coupling of these nanowires with the rest of the device components [52]. In Si NWs, for example, native or intentionally grown surface oxide can act as an insulator or as a poor charge transport medium with limited conduction [53]. In such cases, the uniformity of this oxide layer can be of fundamental importance for the overall functionality of the device. Conventional approaches for imaging any defects in the oxide shell, such as transmission electron microscopy, rely on the observed structural uniformity only and may lead to incorrect assumptions regarding its electrical characteristics.

In a work published in 2008, Stratakis et al. [54] compared the differences between oxide grown on planar Si and Si NWs, in an attempt to evaluate the reliability of these nanostructures for future applications. By examining several nanowires, it was found that the interface barrier for electron injection from silicon core into the oxide shell was similar to planar oxides. Trap density however was susceptible to the non-uniformities of the oxide shell, which, despite appearing to be planar under conventional topography or TEM, had localised weaknesses (**Figure 11**). These weakness areas did not appear to lower substantially the threshold for current leakage through the oxide, but they were potential reliability hazards in nanowire-based devices. This work demonstrated quite successfully that electrical characteristics in NWs may vary significantly depending on the growth conditions of the shell layer. It can also serve as an example of the level of information that can be extracted using advanced SPM techniques.

**Figure 11.** c-AFM current through NW oxide. (a) AFM topography image of part of a NW. Images b, c and d are current maps of the same part of the wire. At the pristine state of this wire, current was first detected at a bias of 13 V (b). Emission is inhomogeneous. Reduced average current in the second scan (c) is attributed to electron trapping in the oxide. At a higher voltage (16 V), increased current density appears from the entire surface of the nanowire (d) [54]. © 2008 American Chemical Society.

## **6. Conclusions**

Solution-processed nanowire field-effect transistors have reached the threshold of being commercially viable due to the developments in nanowires controllable assembly. The main criticism for nanowire-based electronics was linked in the past to the lack of control of a number of nanowires between the device electrodes, thus limiting the devices reproducibility. Recent developments in the field, focusing on solvent-based reproducible and controllable positioning, orientation and placement of nanowires on predefined substrate locations, also coupled with nanowires' purification and selection methods, have provided the necessary breakthroughs to enable scalable fabrication of nanowire devices, including FETs.

For some time, the main target in NW assembly was to reach a high deposition yield and well-aligned nanostructures over large areas as an attempt to achieve superior device performances and reproducibility. However, more precise control of nanowire properties in fabricated devices can only be achieved by full integration of separation and purification processes for nanomaterials, based on their electrical and morphological properties. Currently, the only assembly technique offering all of these features is electric-field–assisted dielectrophoresis. This method is scalable and can be applied in large-area device deposition. Scanning probe microscopy characterisation techniques, such as conductive AFM, capable of simultaneous topological and conductivity measurements of nanowire active channels in electronic devices with high special resolution, have helped to optimise the nanowire properties and the corresponding selection and deposition methods.

In summary, solution-processed nanowire field-effect transistors represent a powerful technological platform with high potential for low-cost large-area electronics with applications targeting chemical, biological and tensile sensing; flexible circuits; memory; displays; and photonic devices.

## **Author details**

Maxim Shkunov\*, Grigorios Rigas and Marios Constantinou

\*Address all correspondence to: m.shkunov@surrey.ac.uk

Advanced Technology Institute, Electrical and Electronic Engineering, University of Surrey, Guildford, UK

## **References**

[1] Liu X, Long Y-Z, Liao L, Duan X, Fan Z. Large-scale integration of semiconductor nano wires for high-performance flexible electronics. ACS Nano. 2012;**6**(3):1888-1900. DOI:10.1021/nn204848r

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**6. Conclusions**

96 Nanowires - New Insights

photonic devices.

**Author details**

Guildford, UK

**References**

DOI:10.1021/nn204848r

Solution-processed nanowire field-effect transistors have reached the threshold of being commercially viable due to the developments in nanowires controllable assembly. The main criticism for nanowire-based electronics was linked in the past to the lack of control of a number of nanowires between the device electrodes, thus limiting the devices reproducibility. Recent developments in the field, focusing on solvent-based reproducible and controllable positioning, orientation and placement of nanowires on predefined substrate locations, also coupled with nanowires' purification and selection methods, have provided the necessary break-

For some time, the main target in NW assembly was to reach a high deposition yield and well-aligned nanostructures over large areas as an attempt to achieve superior device performances and reproducibility. However, more precise control of nanowire properties in fabricated devices can only be achieved by full integration of separation and purification processes for nanomaterials, based on their electrical and morphological properties. Currently, the only assembly technique offering all of these features is electric-field–assisted dielectrophoresis. This method is scalable and can be applied in large-area device deposition. Scanning probe microscopy characterisation techniques, such as conductive AFM, capable of simultaneous topological and conductivity measurements of nanowire active channels in electronic devices with high special resolution, have helped to optimise the nanowire properties and the cor-

In summary, solution-processed nanowire field-effect transistors represent a powerful technological platform with high potential for low-cost large-area electronics with applications targeting chemical, biological and tensile sensing; flexible circuits; memory; displays; and

Advanced Technology Institute, Electrical and Electronic Engineering, University of Surrey,

[1] Liu X, Long Y-Z, Liao L, Duan X, Fan Z. Large-scale integration of semiconductor nano wires for high-performance flexible electronics. ACS Nano. 2012;**6**(3):1888-1900.

throughs to enable scalable fabrication of nanowire devices, including FETs.

responding selection and deposition methods.

Maxim Shkunov\*, Grigorios Rigas and Marios Constantinou

\*Address all correspondence to: m.shkunov@surrey.ac.uk


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CPEM.2014.6898335

100 Nanowires - New Insights

marc.200900220

Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/67446

#### **Abstract**

Semiconductor nanowires have aroused a lot of scientific interest and have been regarded as one of the most promising candidates that would make possible building blocks in future nanoscale devices and integrated circuits. Employing nanowire as metal‐oxide‐semicon‐ ductor field‐effect transistor (MOSFET) channel can enable a gate‐surrounding structure allowing an excellent electrostatic gate control over the channel for reducing the short‐ channel effects. This chapter introduces the basic physics of semiconductor nanowires and addresses the problem of how to synthesize semiconductor nanowires with low‐cost, high‐efficiency and bottom‐up approaches. Effective integration of nanowires in modern complementary metal‐oxide‐semiconductor (CMOS) technology, specifically in MOSFET devices, and non‐volatile memory applications is also reviewed. By extending the nanow‐ ire MOSFET structure into a universal device architecture, various novel semiconductor materials can be investigated. Semiconductor nanowire MOSFETs have been proved to be a strong and useful platform to study the physical and electrical properties of the novel material. In this chapter, we will also review the investigations on topological insulator materials by employing the nanowire field‐effect transistor (FET) device structure.

**Keywords:** semiconductor nanowire, gate‐surrounding, MOSFET, self‐assembly, flash‐like non‐volatile memory, topological insulator nanowire FETs

## **1. Introduction**

Since the invention of integrated circuit in the 1950s, the scaling of metal‐oxide‐semiconduc‐ tor field‐effect transistor (MOSFET) continues with the emergence of new technologies to extend complementary metal‐oxide‐semiconductor (CMOS) down to ever smaller technol‐ ogy node. However, the CMOS scaling has deviated from the trends predicted by Moore and the scaling rules set forth by Dennard et al. due to fundamental physical and technical limitations [1, 2]. Limitations such as heat dissipation, leakage current and channel length

© 2017 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

modulation have become a major concern that will inevitably lead to the slowing down in CMOS scaling when approaching atomic dimension. Thus, there is an urgent need to develop new semiconductor technology to solve the issues including cost, speed, density, reliability and power dissipation. A great deal of efforts has been made, and among all the candidates, nanoelectronics involved with replacing existing silicon‐based technology has risen to be one of the most promising solutions towards continuous CMOS scaling.

During the past decades, semiconductor nanowires synthesized by bottom‐up techniques and derived field‐effect transistor (FET) devices have been intensively studied as the funda‐ mental building blocks for nanoelectronic devices and circuit technologies [3–7]. Compared to planar devices based on bulk materials, the nanowires have a smaller channel and large surface‐to‐volume ratio. In addition, the gate‐surrounding or gate‐all‐around (GAA) struc‐ ture that can be formed in the nanowire FET allows excellent electrostatic gate control over the nanowire channel. Moreover, the GAA nanowire transistors enable ultimate CMOS device scaling with the best possible short‐channel control considering the quantum con‐ finement effects and the scattering at atomic dimensions. The GAA horizontal nanowire FET architecture exhibits high similarities to the FinFET, which is the predominant tech‐ nology in the current 10 nm or even 7 nm process node. Thus, GAA FETs are very promis‐ ing candidates in the sub‐7 nm nodes to extend the scalability beyond the limits imposed by the FinFET technology with much less complexity compared to the alternative scaling approaches [8].

Till date, nanowire FETs have mainly been fabricated using the "top‐down" approaches based on advanced lithography with nanowire prepared by dry/wet etching which usually yields well‐oriented nanowire arrays [9, 10]. However, it has been well recognized that nanowires synthesized by "bottom‐up" techniques such as chemical vapour deposition (CVD) can have lower cost and higher quality compared to the"top‐down" methods [11]. Thus, it would be very attractive to develop an approach to manufacture such nanowire FETs with an excellent performance. Nevertheless, the technique to fabricate FETs from CVD grown silicon nanow‐ ires remains a barrier to the development of devices with optimized performance. Current approaches are primarily based on the harvesting and positioning the as‐grown nanowires using aligning methods such as fluidic alignment, dielectrophoresis or nanoscale probe meth‐ ods [12–17]. Such methods will inevitably introduce contaminants to the nanowire surfaces, which will adversely influence the device interface state density and possibly the nanowire surface roughness, and the device performance will be deteriorated as a result.

In this chapter, we first review the fundamentals of semiconductor nanowires and synthetic strategies. Then we introduce a novel self‐alignment fabrication process for nanowire FET applications. The high‐quality self‐aligned nanowire channels possess clean surface and the fabricated FET devices exhibit excellent performance including large on/off ratio, small sub‐ threshold slope and small leakage current. Such an effective nanowire integration scenario is very attractive for different materials and device investigations. We focus on the flash memory based on the self‐aligned Si nanowire FETs and the study of topological insulator nanowire FETs using the self‐alignment techniques. The results demonstrate that by employing the one‐ dimensional nanowire as the active component in the electronic devices, the flash memory performance has been significantly improved such as lower operation voltage and better reliability, and the basic principles behind the topological insulators have been manifested strongly enabling more delicate characterizations to understand the physics of the specific material. We believe that nanowire MOSFETs will open up a suit of potential applications in future sub‐10 nm semiconductor technology as well as solutions towards emerging micro and nanoelectronic device challenges.

## **2. Review of physics of semiconductor nanowires**

The theory of nanowires will be briefly reviewed with a focus on silicon nanowires since the features discussed here can be extended to other types of semiconductor nanowires. The structural and mechanical properties of silicon nanowires will be reviewed first, and then the electronic properties will be discussed in which we will also consider the device‐related issues and limitations.

## **2.1. Structural and mechanical properties**

modulation have become a major concern that will inevitably lead to the slowing down in CMOS scaling when approaching atomic dimension. Thus, there is an urgent need to develop new semiconductor technology to solve the issues including cost, speed, density, reliability and power dissipation. A great deal of efforts has been made, and among all the candidates, nanoelectronics involved with replacing existing silicon‐based technology has risen to be one

During the past decades, semiconductor nanowires synthesized by bottom‐up techniques and derived field‐effect transistor (FET) devices have been intensively studied as the funda‐ mental building blocks for nanoelectronic devices and circuit technologies [3–7]. Compared to planar devices based on bulk materials, the nanowires have a smaller channel and large surface‐to‐volume ratio. In addition, the gate‐surrounding or gate‐all‐around (GAA) struc‐ ture that can be formed in the nanowire FET allows excellent electrostatic gate control over the nanowire channel. Moreover, the GAA nanowire transistors enable ultimate CMOS device scaling with the best possible short‐channel control considering the quantum con‐ finement effects and the scattering at atomic dimensions. The GAA horizontal nanowire FET architecture exhibits high similarities to the FinFET, which is the predominant tech‐ nology in the current 10 nm or even 7 nm process node. Thus, GAA FETs are very promis‐ ing candidates in the sub‐7 nm nodes to extend the scalability beyond the limits imposed by the FinFET technology with much less complexity compared to the alternative scaling

Till date, nanowire FETs have mainly been fabricated using the "top‐down" approaches based on advanced lithography with nanowire prepared by dry/wet etching which usually yields well‐oriented nanowire arrays [9, 10]. However, it has been well recognized that nanowires synthesized by "bottom‐up" techniques such as chemical vapour deposition (CVD) can have lower cost and higher quality compared to the"top‐down" methods [11]. Thus, it would be very attractive to develop an approach to manufacture such nanowire FETs with an excellent performance. Nevertheless, the technique to fabricate FETs from CVD grown silicon nanow‐ ires remains a barrier to the development of devices with optimized performance. Current approaches are primarily based on the harvesting and positioning the as‐grown nanowires using aligning methods such as fluidic alignment, dielectrophoresis or nanoscale probe meth‐ ods [12–17]. Such methods will inevitably introduce contaminants to the nanowire surfaces, which will adversely influence the device interface state density and possibly the nanowire

surface roughness, and the device performance will be deteriorated as a result.

In this chapter, we first review the fundamentals of semiconductor nanowires and synthetic strategies. Then we introduce a novel self‐alignment fabrication process for nanowire FET applications. The high‐quality self‐aligned nanowire channels possess clean surface and the fabricated FET devices exhibit excellent performance including large on/off ratio, small sub‐ threshold slope and small leakage current. Such an effective nanowire integration scenario is very attractive for different materials and device investigations. We focus on the flash memory based on the self‐aligned Si nanowire FETs and the study of topological insulator nanowire FETs using the self‐alignment techniques. The results demonstrate that by employing the one‐ dimensional nanowire as the active component in the electronic devices, the flash memory performance has been significantly improved such as lower operation voltage and better

of the most promising solutions towards continuous CMOS scaling.

approaches [8].

102 Nanowires - New Insights

The Si nanowires are intriguing mostly due to the extra high surface‐to‐volume ratio and the well‐defined single crystalline orientation. The nanowire growth direction has been widely studied, and the connection between the diameter and the favoured crystal direction has been established [18]. It has been reported both experimentally and theoretically that the catalyst‐ assisted Si nanowires with smallest diameter prefer the <110> direction, while the nanowires with larger diameter favours the <111> direction [19–21]. The growth direction determines the nanowire cross section to some extent. A pentagonal cross section has been observed from the ground‐state structure for Si nanowires up to 5 nm [22, 23]. This cross section due to the joint of five prisms cut of a Si (110) plane has rarely been reported. A more well‐known structure in good agreement with experimental work is the hexagonal cross section for <110> Si nanowires with a bulk core [18, 24].

Mechanical properties of Si become quite different when reaching nanoscale with lower dimen‐ sion. Due to the compressive surface stress, the Young's modulus of <100> Si nanowires softens as the surface‐to‐volume ratio increases and a steep decrease has been detected on shrinking of the nanowire diameter to 2–2.5 nm [25]. It was further discovered that the Young's modulus of Si nanowires is strongly anisotropic [26]. Different from the <100> nanowires, which exhibit lowest values, the wires grown along <110> direction give the highest values. These results are also in good agreement with the experimental work [27]. Currently, the mechanical proper‐ ties of nanowires have become a promising research direction. Static and dynamic nanowire bending with atomistic simulations, which relies on periodic boundary conditions, reveals the influence of surface stress more clearly and provides valuable information for nanowire‐based device designs.

## **2.2. Electronic properties**

It is widely recognized that bulk Si has an indirect band gap, with the valence band maxi‐ mum at the Γ point and the conduction minimum at about 85% along the Γ and Χ direction. However, Si nanowires grown along most orientations have a direct band gap, with the maxi‐ mum of the valence band and the minimum of the conduction band aligned at the same point in k‐space. As a result, such nanowire materials have become encouraging candidates in opto‐ electronics or photonics applications [28].

The electronic properties of nanowires depend on the nanowire growth direction, cross section and diameter. However, it is interesting to find that the band gap of Si nanowire is insensitive to the shape of cross section. The band gap of a 1 nm nanowire was found constant with change less than 0.09 eV by simulating cross sections that are even utterly different, as long as providing the same surface‐to‐volume ratio [29, 30].

Different types of Si nanowire based electronic devices have been fabricated and studied for a variety of application purposes. An important cause of electrical conductance deg‐ radation in such devices is the scattering occurring at the surface with the presence of surface defects or surface roughness [31, 32]. Generally, the surface roughness disorder induces irregularities in the density of states along the nanowire axis, resulting in the car‐ rier reflection and reduction in conductance. A more detailed study shows that the back‐ scattering due to the surface roughness strongly depends on the nanowire orientation, and the anisotropy comes from the difference in band structure [33, 34]. In particular, electrons are less sensitive to surface roughness in <110> nanowires, and the transfer of holes is more smooth in <111> nanowires. Other electronic transport parameters such as the mean free path, length and the localization length can be better explained with the above incorpo‐ rated differences.

Despite the defects or roughness from the nanowire surface, the existence of impurities is another major source of scattering, especially when the nanowire size is scaled down below 10 nm. Unlike the bulk in which the carriers are just slowed down by the impurities, the trajectories of the carriers in an extremely thin one‐dimensional medium can be entirely back‐ scattered because the scattering potential often extends throughout most of the cross sections of the thin wire [34]. Impurities can be originated from imperfect growth or intentional dop‐ ing for targeted electrical properties when referred to semiconductors. For the dopants in Si nanowires, impurities like donor impurities, either segregate to the surface forming electri‐ cally inactive components or stay in the wire producing a strong backscattering, both will lead to the decreased conductance.

## **3. Silicon nanowire synthesis and field‐effect transistors**

## **3.1. Silicon nanowire synthesis**

There has been a large number of reported works on the nanowire synthesis of a wide spectrum of semiconductor materials during the past decades. Both chemical and physical methods are intensively studied. Understanding the growth mechanism of these synthesis approaches is helpful in developing one‐dimensional nanostructures of the desired materials and derivative electrical devices.

Solution phase synthesis of nanowires is a low cost yet high yield method in which selec‐ tive capping agents are often employed, especially in an anisotropic growth, for the kinetic control of the evolving nanostructure to allow elongation along certain axis by preferentially adsorbing to specific crystal facets [35–37]. The major limitation of such solution phase syn‐ thesis lies in the empirical trial‐and‐error methodology for capping agents. Template‐assisted electrochemical synthesis is another popular approach to grow one‐dimensional nanostruc‐ tures. Synthesis of metals, semiconductors and conductive polymers and oxides has been reported by using templates such as anodic aluminium oxide (AAO) and polycarbonate membranes [38, 39]. This method shares the advantages such as low‐cost, well‐orientation, ambient temperature, pressure operation and feasibility of batch fabrication of nanowire array. However, complete template filling still remains a challenge for the nanowire synthesis through electrodeposition. Template‐assisted synthesis has been more utilized in the forma‐ tion of hollow nanotube and core‐shell nanowire structures in combination with atomic layer deposition (ALD) technique [40, 41].

However, Si nanowires grown along most orientations have a direct band gap, with the maxi‐ mum of the valence band and the minimum of the conduction band aligned at the same point in k‐space. As a result, such nanowire materials have become encouraging candidates in opto‐

The electronic properties of nanowires depend on the nanowire growth direction, cross section and diameter. However, it is interesting to find that the band gap of Si nanowire is insensitive to the shape of cross section. The band gap of a 1 nm nanowire was found constant with change less than 0.09 eV by simulating cross sections that are even utterly different,

Different types of Si nanowire based electronic devices have been fabricated and studied for a variety of application purposes. An important cause of electrical conductance deg‐ radation in such devices is the scattering occurring at the surface with the presence of surface defects or surface roughness [31, 32]. Generally, the surface roughness disorder induces irregularities in the density of states along the nanowire axis, resulting in the car‐ rier reflection and reduction in conductance. A more detailed study shows that the back‐ scattering due to the surface roughness strongly depends on the nanowire orientation, and the anisotropy comes from the difference in band structure [33, 34]. In particular, electrons are less sensitive to surface roughness in <110> nanowires, and the transfer of holes is more smooth in <111> nanowires. Other electronic transport parameters such as the mean free path, length and the localization length can be better explained with the above incorpo‐

Despite the defects or roughness from the nanowire surface, the existence of impurities is another major source of scattering, especially when the nanowire size is scaled down below 10 nm. Unlike the bulk in which the carriers are just slowed down by the impurities, the trajectories of the carriers in an extremely thin one‐dimensional medium can be entirely back‐ scattered because the scattering potential often extends throughout most of the cross sections of the thin wire [34]. Impurities can be originated from imperfect growth or intentional dop‐ ing for targeted electrical properties when referred to semiconductors. For the dopants in Si nanowires, impurities like donor impurities, either segregate to the surface forming electri‐ cally inactive components or stay in the wire producing a strong backscattering, both will lead

There has been a large number of reported works on the nanowire synthesis of a wide spectrum of semiconductor materials during the past decades. Both chemical and physical methods are intensively studied. Understanding the growth mechanism of these synthesis approaches is helpful in developing one‐dimensional nanostructures of the desired materials

**3. Silicon nanowire synthesis and field‐effect transistors**

electronics or photonics applications [28].

rated differences.

104 Nanowires - New Insights

to the decreased conductance.

**3.1. Silicon nanowire synthesis**

and derivative electrical devices.

as long as providing the same surface‐to‐volume ratio [29, 30].

Vapour phase synthesis of one‐dimensional nanostructure is probably the most extensively explored approach. Numerous techniques have been developed to grow nanowire from gas precursors. Among all the vapour phase methods, the most widely studied and success‐ ful approach in generating high‐quality single‐crystal nanowires in large quantities is the vapour‐liquid‐solid (VLS) mechanism [4]. We will be focusing on this method in this section, and the following contents reviewed in this chapter are based on the nanowires synthesized by using the VLS approach.

A typical VLS process starts from the dissolution of vapour reactants into a catalytic alloy phase, followed by the crystal nucleation at the liquid‐solid interface. As illustrated in **Figure 1**, gold nanoparticles are commonly used as catalyst for Si nanowire growth by the

**Figure 1.** Schematic illustration of the VLS mechanism for Si nanowire synthesis using Au nanoparticle as catalyst.

VLS mechanism. The Au particles catalyze the gas precursor (e.g. SiH<sup>4</sup> ) and reacts with the Si atoms from the vapour phase, forming Au‐Si eutectic droplets. Si was introduced from the vapour and adsorbed onto the liquid surface, then diffused into the droplet leading to a supersaturated state where the Si atoms precipitate and the nanowire starts nucleating. In the growth, the droplet serves as the "seeds" limiting the lateral growth of individual nanowires, and the droplet size remains unchanged during the growth which determines the diameter of the subsequent nanowires.

The VLS process has become a widely used growth method for one‐dimensional nanostruc‐ tures of a broad variety of materials. In addition to elemental semiconductors such as Si and Ge, binary compounds including III‐V semiconductors (e.g. GaN, GaAs and InAs), oxides (e.g. ZnO, SiO<sup>2</sup> and ITO) and chalcogenides (e.g. Bi<sup>2</sup> Se3 , In<sup>2</sup> Se3 and CdS) have also been fabricated and studied in nanowire morphology following the VLS mechanism.

## **3.2. Silicon nanowire field‐effect transistors**

In this section, we review the fabrication and characterization of Si nanowire FETs prepared by using a self‐alignment method based on VLS synthesis mechanism [42]. Unlike the tradi‐ tional nanowire harvesting and alignment methods, the self‐alignment approach not only enables simultaneous batch fabrication of reproducible and homogeneous nanowire devices of high quality, but also limits the contaminations of the nanowire during the fabrication process. The fabricated self‐aligned Si nanowire FETs exhibit excellent current‐voltage (I‐V) characteristics, high on/off current ratio and small subthreshold slope providing an excellent platform for other devices and material investigations and applications.

## *3.2.1. FET fabrication*

The Si nanowire FETs are fabricated using the directed self‐alignment process as shown in **Figure 2**. The main concept of this fabrication approach is that Si nanowires are synthesized from Au catalysts on predefined locations as on wafers and well aligned with the source/drain and gate electrodes by photolithographic processes without harvesting the nanowires. At the first step of the fabrication process, a thin layer of Au catalyst (∼1 nm) was deposited on the SiO<sup>2</sup> /Si substrate and patterned by photolithography and lift‐off processes. The Si nanowires were grown from the catalyst at the defined locations in a low‐pressure chemical vapour deposition (LPCVD) furnace at 440°C for 2 hours with an ambient SiH<sup>4</sup> stream under a pres‐ sure of 500 mTorr. The nanowires are typically 20 μm in length and 20 nm in diameter. Immediately after the VLS growth, the Si nanowires were loaded in a dry oxidation furnace and oxidized at 750°C for 30 minutes in O<sup>2</sup> to form a ≈ 3 nm thick SiO<sup>2</sup> which was expected to provide a good interface between the nanowire and the subsequent top gate dielectric stack [42]. Photolithographic and lift‐off processes were then performed to form the source and drain contacts. To facilitate proper contact formation, a 2% HF wet etch was applied to remove the oxides from the Si nanowires at the source/drain region before electrode metal (Al in this case) deposition. The next step is to deposit top gate dielectric (25 nm HfO<sup>2</sup> ) by ALD at 250°C, followed by a deposition of 5 nm of Al<sup>2</sup> O3 to improve the interface with the

**Figure 2.** Self‐alignment fabrication process: (a) patterned Au catalyst on SiO<sup>2</sup> ; (b) synthesis of Si nanowire from the Au catalyst, nanowire oxidation and alignment of source/drain contacts; (c) deposition of gate dielectric and pattern of top gate electrode [42].

Al top gate which was formed by the same lift‐off process as of the source/drain electrodes. The final devices were annealed in forming gas (5% H<sup>2</sup> in N<sup>2</sup> ) at 325°C for 5 minutes to reduce the interface trap density between the nanowire and dielectric layer, as well as to improve the contact between the Al metal to the Si nanowire and HfO<sup>2</sup> . **Figure 3** shows the top‐view scanning electron microscopy (SEM) image of a finished self‐aligned Si nanowire FET with gate length of 2 μm.

#### *3.2.2. Electrical characterizations*

VLS mechanism. The Au particles catalyze the gas precursor (e.g. SiH<sup>4</sup>

and ITO) and chalcogenides (e.g. Bi<sup>2</sup>

**3.2. Silicon nanowire field‐effect transistors**

and oxidized at 750°C for 30 minutes in O<sup>2</sup>

ALD at 250°C, followed by a deposition of 5 nm of Al<sup>2</sup>

and studied in nanowire morphology following the VLS mechanism.

platform for other devices and material investigations and applications.

deposition (LPCVD) furnace at 440°C for 2 hours with an ambient SiH<sup>4</sup>

the subsequent nanowires.

ZnO, SiO<sup>2</sup>

106 Nanowires - New Insights

*3.2.1. FET fabrication*

SiO<sup>2</sup>

Si atoms from the vapour phase, forming Au‐Si eutectic droplets. Si was introduced from the vapour and adsorbed onto the liquid surface, then diffused into the droplet leading to a supersaturated state where the Si atoms precipitate and the nanowire starts nucleating. In the growth, the droplet serves as the "seeds" limiting the lateral growth of individual nanowires, and the droplet size remains unchanged during the growth which determines the diameter of

The VLS process has become a widely used growth method for one‐dimensional nanostruc‐ tures of a broad variety of materials. In addition to elemental semiconductors such as Si and Ge, binary compounds including III‐V semiconductors (e.g. GaN, GaAs and InAs), oxides (e.g.

> Se3 , In<sup>2</sup> Se3

In this section, we review the fabrication and characterization of Si nanowire FETs prepared by using a self‐alignment method based on VLS synthesis mechanism [42]. Unlike the tradi‐ tional nanowire harvesting and alignment methods, the self‐alignment approach not only enables simultaneous batch fabrication of reproducible and homogeneous nanowire devices of high quality, but also limits the contaminations of the nanowire during the fabrication process. The fabricated self‐aligned Si nanowire FETs exhibit excellent current‐voltage (I‐V) characteristics, high on/off current ratio and small subthreshold slope providing an excellent

The Si nanowire FETs are fabricated using the directed self‐alignment process as shown in **Figure 2**. The main concept of this fabrication approach is that Si nanowires are synthesized from Au catalysts on predefined locations as on wafers and well aligned with the source/drain and gate electrodes by photolithographic processes without harvesting the nanowires. At the first step of the fabrication process, a thin layer of Au catalyst (∼1 nm) was deposited on the

/Si substrate and patterned by photolithography and lift‐off processes. The Si nanowires were grown from the catalyst at the defined locations in a low‐pressure chemical vapour

to form a ≈ 3 nm thick SiO<sup>2</sup>

O3

sure of 500 mTorr. The nanowires are typically 20 μm in length and 20 nm in diameter. Immediately after the VLS growth, the Si nanowires were loaded in a dry oxidation furnace

to provide a good interface between the nanowire and the subsequent top gate dielectric stack [42]. Photolithographic and lift‐off processes were then performed to form the source and drain contacts. To facilitate proper contact formation, a 2% HF wet etch was applied to remove the oxides from the Si nanowires at the source/drain region before electrode metal (Al in this case) deposition. The next step is to deposit top gate dielectric (25 nm HfO<sup>2</sup>

) and reacts with the

and CdS) have also been fabricated

stream under a pres‐

which was expected

to improve the interface with the

) by

Si nanowire FET with single or multiple nanowire channels is expected to exhibit better performance than planer bulk Si. The Gate‐surrounding structure can be enabled allow‐ ing excellent electrostatic gate control over the channel for reduced short‐channel effects.

**Figure 3.** Top‐view SEM image of a typical self‐aligned Si nanowire FET with gate length of 2 μm [42].

The following equations define the minimum gate length to avoid short‐channel effects for single‐gate, double‐gate and surrounding‐gate structures:

$$
\lambda\_{\text{stagke-gate}} = \sqrt{\frac{\varepsilon\_{\text{si}} t\_{\text{sr}} t\_{\text{st}}}{\varepsilon\_{\text{sr}}}} \tag{1}
$$

$$
\lambda\_{\text{double-gate}} = \sqrt{\frac{\varepsilon\_{Si} t\_{ox} t\_{Si}}{2}} \tag{2}
$$

$$
\lambda\_{\text{double-gate}} = \sqrt{\frac{\varepsilon\_{Si} l\_{sr} \varepsilon\_{Si}}{2}} \tag{2}
$$

$$
\lambda\_{\text{surrounding-gate}} = \sqrt{\frac{2 \varepsilon\_{Si} l\_{Si} ^{2} \ln \left( 1 + \frac{2 \cdot t\_{sr}}{t\_{sr}} \right) + \varepsilon\_{sr} t\_{sr} ^{2}}{16 \text{ } \varepsilon\_{sr}}} \tag{3}
$$

where *t*Si, *ε*Si, *t*ox and *ε*ox are the thickness and permittivity of Si and gate oxide, respectively [43]. The above equations demonstrate that the surrounding gate structure offers the best characteristics for controlling the short‐channel effects.

**Figure 4a** and **b** shows the output characteristics of a self‐aligned Si nanowire FET in both linear and logarithmic scale. From the drain current (*I* DS) versus drain voltage (*V*DS) curves, the leakage‐affected region, weak, moderate and strong inversion operation regions of the FET are clearly shown in **Figure 4b**. In the weak inversion region, *I* DS increases exponentially with gate voltage (*V*GS) due to the diffusion of carriers (holes) and is saturated at 3 φ<sup>t</sup> (∼78 mV at room temperature, φ<sup>t</sup> = kT/q is the thermal voltage). In moderate inversion region, *I*DS varies by a couple of orders of magnitude, changing gradually from one form of functional depen‐ dence to the other. In strong inversion region, *I* DS approximately follows the quadratic law and is proportional to (*V*GS – *V*TH)<sup>2</sup> with saturation at *V*DS = *V*GS − *V*TH. These curves demonstrate that the self‐aligned Si nanowire FET has similar electrical behaviours to those of conven‐ tional MOSFETs, even though it has much simpler device structure and no source/drain junc‐ tion doping. It should be noted that the *I* DS−*V*DS curves increase sharply in the linear region, indicating a small source and drain contact resistance.

Due to the Schottky contacts between the Al contacts and the intrinsic Si nanowire, Schottky‐ barrier pMOSFET characteristics are expected for these FETs. **Figure 5** shows typical transfer characteristics of self‐aligned Si nanowire FET with *V*DS of −50, −100 and −150 mV, respectively.

**Figure 4.** Output characteristics of the self‐aligned Si nanowire FET in (a) linear and (b) logarithmic scale [42].

The following equations define the minimum gate length to avoid short‐channel effects for

**Figure 3.** Top‐view SEM image of a typical self‐aligned Si nanowire FET with gate length of 2 μm [42].

2 *εSi t Si*

where *t*Si, *ε*Si, *t*ox and *ε*ox are the thickness and permittivity of Si and gate oxide, respectively [43]. The above equations demonstrate that the surrounding gate structure offers the best

**Figure 4a** and **b** shows the output characteristics of a self‐aligned Si nanowire FET in both

leakage‐affected region, weak, moderate and strong inversion operation regions of the FET

by a couple of orders of magnitude, changing gradually from one form of functional depen‐

gate voltage (*V*GS) due to the diffusion of carriers (holes) and is saturated at 3 φ<sup>t</sup>

\_\_\_\_\_\_ *εSi t ox <sup>t</sup>* \_\_\_\_\_\_*Si εox*

\_\_\_\_\_\_ *εSi t ox <sup>t</sup>* \_\_\_\_\_\_*Si* 2 *εox*

\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_

\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_\_ 16 *εox*

= kT/q is the thermal voltage). In moderate inversion region, *I*DS varies

<sup>2</sup> ln(1 + <sup>2</sup> *<sup>t</sup>* \_*ox t Si* ) + *εox t Si* 2

(1)

(2)

(3)

DS) versus drain voltage (*V*DS) curves, the

DS approximately follows the quadratic law

DS increases exponentially with

(∼78 mV at

single‐gate, double‐gate and surrounding‐gate structures:

*<sup>λ</sup>*single−gate <sup>=</sup> <sup>√</sup>

*<sup>λ</sup>*double−gate <sup>=</sup> <sup>√</sup>

characteristics for controlling the short‐channel effects.

linear and logarithmic scale. From the drain current (*I*

dence to the other. In strong inversion region, *I*

are clearly shown in **Figure 4b**. In the weak inversion region, *I*

*<sup>λ</sup>*surrounding−gate <sup>=</sup> <sup>√</sup>

room temperature, φ<sup>t</sup>

108 Nanowires - New Insights

**Figure 5.** Transfer characteristics of the Si nanowire FET, with *V*DS value of −50, −100 and −150 mV, respectively [42].

The on/off current ratio is ∼10<sup>8</sup> within a 1.2 V *V*GS window and no ambipolar behaviour is observed. The carrier mobility can be calculated from the linear region of the transconduc‐ tance when *V*DS = −50 mV with a presumed diameter of 20 nm for the nanowire channel. The calculated results show that the fabricated Si nanowire FETs have a relatively consistent hole mobility around 100 cm<sup>2</sup> /Vs. The subthreshold swing (SS) can be extracted from the subthresh‐ old region of *I* DS in the log‐scale *I* DS−*V*GS curves. The SS values of the Si nanowire FETs are as low as 75 mV/dec, which is quite small as compared to most reported results on nanowire FETs and poly‐Si thin‐film transistors [42].

The Si nanowire FETs fabricated through the self‐alignment approach exhibit excellent perfor‐ mance as indicated by a high on/off current ratio (∼10<sup>8</sup> ), small leakage current (<10−14 A), good carrier mobility (∼100 cm<sup>2</sup> /Vs) and small subthreshold slope (75 mV/dec). These excellent characteristics are due to the clean interfaces formed in the self‐alignment fabrication process, and such Si nanowire FETs are very attractive for future nanoelectronic device applications.

## **4. Silicon nanowire‐based flash‐like non‐volatile memory**

## **4.1. Introduction of flash‐like non‐volatile memory**

Today, computing architectures and electronic systems built on CMOS components are still pursuing without any sign of slowing down of requirements for low power, fast speed and high density alternatives. Up to now, electronic systems whose main function is to focus on date computing and storage take up more than half of the semiconductor market, and the demand is still growing explosively in areas such as portable electronic devices and systems. Solid‐state mass storage occupies a large portion of this market, due to their compatibility with CMOS scaling technology, suitability for harsh environment without mechanical parts and the fact that most types of memory are non‐volatile.

Non‐volatile memory is typically employed for the task of secondary storage or long‐term storage, which usually does not require fast operation speed or integration density. The cur‐ rent primary storage or on‐chip memory still relies upon volatile forms of random‐access memory. During the past decades, the size of cache memory in the central processing unit (CPU), which is also known as the static random‐access memory (SRAM) has been doubled several times as a feasible strategy to increase the CPU capability. However, increasing SRAM will decrease CPU net information throughput because it is volatile and occupies a large chip floor space. Thus, it will be a revolutionary breakthrough in microelectronics if a truly non‐volatile memory can be implemented as the on‐chip memory in CPUs replacing SRAM.

## *4.1.1. Basic memory concepts and scaling challenges*

Among all the non‐volatile memory candidates for primary storage applications, flash mem‐ ory is the most widely studied and electrically accessible form and is the most promising non‐volatile memory in the electronics market. Flash memory has fast read access times, good retention and reliability and CMOS compatible fabrication process [44–46].

Also known as the floating‐gate memory (shown in **Figure 6**), a flash memory device stores the trapped electrons in the floating gate until they are removed by another application of electrical field. Because the floating gate is insulated from the control gate and the MOSFET channel by a relatively thick blocking oxide and a thin tunnelling oxide, respectively, the trapped electrons can be retained for many years, and logical "0" and "1" states can be defined according to the presence or absence of electrons trapped in the floating gate. In the past years, the flash capacity, integrated density and performance have been continued to increase with lower manufactur‐ ing cost. Due to its compatibility with conventional CMOS process, it is easier and more reliable to integrate flash memory than other forms of non‐volatile memory in logic and analog devices with increasing embedded and stand‐alone memory to achieve higher chip performance.

The on/off current ratio is ∼10<sup>8</sup>

DS in the log‐scale *I*

mance as indicated by a high on/off current ratio (∼10<sup>8</sup>

**4.1. Introduction of flash‐like non‐volatile memory**

and the fact that most types of memory are non‐volatile.

*4.1.1. Basic memory concepts and scaling challenges*

FETs and poly‐Si thin‐film transistors [42].

mobility around 100 cm<sup>2</sup>

carrier mobility (∼100 cm<sup>2</sup>

old region of *I*

110 Nanowires - New Insights

within a 1.2 V *V*GS window and no ambipolar behaviour is

DS−*V*GS curves. The SS values of the Si nanowire FETs are as

), small leakage current (<10−14 A), good

/Vs. The subthreshold swing (SS) can be extracted from the subthresh‐

/Vs) and small subthreshold slope (75 mV/dec). These excellent

observed. The carrier mobility can be calculated from the linear region of the transconduc‐ tance when *V*DS = −50 mV with a presumed diameter of 20 nm for the nanowire channel. The calculated results show that the fabricated Si nanowire FETs have a relatively consistent hole

low as 75 mV/dec, which is quite small as compared to most reported results on nanowire

The Si nanowire FETs fabricated through the self‐alignment approach exhibit excellent perfor‐

characteristics are due to the clean interfaces formed in the self‐alignment fabrication process, and such Si nanowire FETs are very attractive for future nanoelectronic device applications.

Today, computing architectures and electronic systems built on CMOS components are still pursuing without any sign of slowing down of requirements for low power, fast speed and high density alternatives. Up to now, electronic systems whose main function is to focus on date computing and storage take up more than half of the semiconductor market, and the demand is still growing explosively in areas such as portable electronic devices and systems. Solid‐state mass storage occupies a large portion of this market, due to their compatibility with CMOS scaling technology, suitability for harsh environment without mechanical parts

Non‐volatile memory is typically employed for the task of secondary storage or long‐term storage, which usually does not require fast operation speed or integration density. The cur‐ rent primary storage or on‐chip memory still relies upon volatile forms of random‐access memory. During the past decades, the size of cache memory in the central processing unit (CPU), which is also known as the static random‐access memory (SRAM) has been doubled several times as a feasible strategy to increase the CPU capability. However, increasing SRAM will decrease CPU net information throughput because it is volatile and occupies a large chip floor space. Thus, it will be a revolutionary breakthrough in microelectronics if a truly non‐volatile memory can be implemented as the on‐chip memory in CPUs replacing SRAM.

Among all the non‐volatile memory candidates for primary storage applications, flash mem‐ ory is the most widely studied and electrically accessible form and is the most promising non‐volatile memory in the electronics market. Flash memory has fast read access times, good

retention and reliability and CMOS compatible fabrication process [44–46].

**4. Silicon nanowire‐based flash‐like non‐volatile memory**

However, current flash memory also exhibit disadvantages such as relatively slow write/erase speed and medium endurance, which make it far below the standards of on‐chip memory applications. In a conventional floating‐gate memory, the tunnelling oxide can hardly be scaled below 7 nm due to the requirement of data retention. Moreover, ultra‐thin tunnelling oxide will lead to severe stress‐induced leakage current (SILC) issue. On the other hand, the conventional floating‐gate materials, poly Si and oxynitride operate at large programming voltages and endure only 105 operation cycles. Even though some new flash technologies are promising for low‐voltage operations, the voltage supply is in excess of the working voltage standard of the advanced processes, and the gap between the operation voltage of memory device and CMOS logic continues to be broadened.

**Figure 6.** Schematic diagram of a floating‐gate flash memory.

#### *4.1.2. SONOS type charge‐trapping memory*

In recent decades, polysilicon‐oxide‐nitride‐oxide‐silicon (SONOS) type charge‐trapping non‐ volatile memory has attracted intensive attention to replace the conventional floating‐gate memory due to their advantages such as lower consumption, better reliability and scalability, and simpler structure and fabrication process [47–49]. **Figure 7** demonstrates the schematic structure of a SONOS charge‐trapping memory, in which the electrons tunnel through the tunnelling layer and stored in the nitride layer. However, the conventional charge‐trapping materials in SONOS memory are not compatible with the dimensional scaling and lead to poor performance in speed, retention and endurance. Furthermore, to achieve faster speed, the tunnelling oxide must be shrinking to enhance the electric field across it while the block‐ ing oxide should be thicker to suppress the leakage current. But thinner tunnelling layer may in turn cause poor stability and reliability, and thicker blocking layer requires larger working voltages. Great efforts have been made for good memory characteristics via various approaches to gain a trade‐off between speed and data retention. An effective strategy is to use non‐planar channel such as nanotubes and nanowires, to enhance the gate control over the channel. Compared to planar devices based on bulk materials, the nanowires have larger surface‐to‐volume ratio, therefore, it requires less stored charges to induce the same memory window for nanowire‐based flash memory.

**Figure 7.** Schematic diagram of a SONOS‐type charge‐trapping flash memory.

The following in this section reviews the work on the device engineering of flash memory with novel dielectric materials and redox molecules as charge trapping medium based on the Si nanowire FETs. As compared with planar structure memory devise, much better performances have been achieved by utilizing the one‐dimensional nanowire channel in the memory devices.

#### **4.2. Silicon nanowire‐based dielectric charge‐trapping memory**

## *4.2.1. History of one‐dimensional nanostructure based charge‐trapping memory*

The first non‐volatile memory cell was demonstrated in 2002 by Fuhrer et al. with one‐ dimensional nanostructure as the active channel component based on carbon nanotube [50]. Sufficient memory window was witnessed, and Fuhrer et al*.* predicted that the charge detec‐ tion of such narrow and high mobility nanotube FETs will outperform planar FET cells [50]. In 2003, Choi et al*.* reported a carbon nanotube based non‐volatile memory with oxide‐nitride‐ oxide (ONO) dielectric stack [51]. A high electric field was generated by 5 V top gate voltage surrounding the surface of 3 nm nanotube, which was sufficiently high to produce Fowler‐ Nordheim tunnelling.

In 2006, Cha et al*.* reported a non‐volatile flash memory having GaN nanowires with SiO<sup>2</sup> as a charge trapping material, and the operation mechanism was also investigated [52]. It was reported that the electric field distribution in the gate dielectric was different at the centre and the edge beneath the gate. The field is uniform under the centre of the gate across the oxide, and the field distribution at the edge changes along the distance. Non‐volatile memory cells based on Si nanowire with CMOS compatible gate dielectric were reported by Zhu et al*.* in 2011 [53]. HfO<sup>2</sup> was used for charge storage, the thickness of which does not affect the elec‐ tric field across the tunnelling oxide. The programming speed and retention time have been significantly improved through the surrounding gate structure.

Various high‐k materials such as Y<sup>2</sup> O3 , Gd<sup>2</sup> O3 and ZrO<sup>2</sup> have been proposed and studied as charge‐trapping layer for better reliability and speed [54–56]. Using thicker high‐k dielectric with relatively larger band gap as the blocking oxide can be expected to lower the electric field across the blocking layer. Integration of novel dielectric materials as the gate stack in the nanowire FET architecture is therefore very promising to realize practical applications of flash memory with faster speed, higher density, smaller size and better reliability.

#### *4.2.2. Device fabrication*

*4.1.2. SONOS type charge‐trapping memory*

112 Nanowires - New Insights

window for nanowire‐based flash memory.

**Figure 7.** Schematic diagram of a SONOS‐type charge‐trapping flash memory.

In recent decades, polysilicon‐oxide‐nitride‐oxide‐silicon (SONOS) type charge‐trapping non‐ volatile memory has attracted intensive attention to replace the conventional floating‐gate memory due to their advantages such as lower consumption, better reliability and scalability, and simpler structure and fabrication process [47–49]. **Figure 7** demonstrates the schematic structure of a SONOS charge‐trapping memory, in which the electrons tunnel through the tunnelling layer and stored in the nitride layer. However, the conventional charge‐trapping materials in SONOS memory are not compatible with the dimensional scaling and lead to poor performance in speed, retention and endurance. Furthermore, to achieve faster speed, the tunnelling oxide must be shrinking to enhance the electric field across it while the block‐ ing oxide should be thicker to suppress the leakage current. But thinner tunnelling layer may in turn cause poor stability and reliability, and thicker blocking layer requires larger working voltages. Great efforts have been made for good memory characteristics via various approaches to gain a trade‐off between speed and data retention. An effective strategy is to use non‐planar channel such as nanotubes and nanowires, to enhance the gate control over the channel. Compared to planar devices based on bulk materials, the nanowires have larger surface‐to‐volume ratio, therefore, it requires less stored charges to induce the same memory

> The Si nanowire FET based dielectric charge‐trapping flash memory is prepared by following the self‐alignment method [57]. Typically, a 300 nm SiO<sup>2</sup> was first grown on Si substrate by dry oxidation. Then a thin film of Au catalyst (1–3 nm) was deposited on patterned area pre‐defined by photolithography. Then the Si nanowires were grown from the catalyst following the VLS mechanism and were oxidized at 750°C for 30 minutes to form a ≈ 3 nm SiO<sup>2</sup> which will func‐ tion as the tunnelling layer. The 3/100 (unit: nm) Ti/Pt source and drain electrodes were then patterned with photolithography and deposited by e‐beam evaporation. The channel length

between the source/drain electrodes was controlled to be 5 μm. The following process is the deposition of charge‐trapping layer and blocking oxide dielectric. Different charge‐trapping layer and stacks were fabricated—Ta<sup>2</sup> O5 , Ta<sup>2</sup> O5 /Al<sup>2</sup> O3 /Ta<sup>2</sup> O5 (TAT) and a reference HfO<sup>2</sup> , with thickness of 20, 6/8/6, 20 nm, respectively [57]. The blocking oxide for all memory devices was selected to be 25 nm for Al<sup>2</sup> O3 . Ta<sup>2</sup> O5 was deposited by sputtering, whereas Al<sup>2</sup> O3 and HfO<sup>2</sup> layers were deposited by ALD with TMA and TEMAH as precursors, respectively. Finally, a 100 nm Pd top gate was formed by the same photolithographic and lift‐off processes as the source/drain electrodes.

#### *4.2.3. Characterization and performance discussion*

Three SONOS‐like charge‐trapping flash memory devices with structures of metal/Al<sup>2</sup> O3 / Ta<sup>2</sup> O5 /Al<sup>2</sup> O3 /Ta<sup>2</sup> O5 /SiO<sup>2</sup> /Si (MATATOS), metal/Al<sup>2</sup> O3 /Ta<sup>2</sup> O5 /SiO<sup>2</sup> /Si (MATOS) and metal/Al<sup>2</sup> O3 / HfO<sup>2</sup> /SiO<sup>2</sup> /Si (MAHOS) have been fabricated and electrically characterized [57]. **Figure 8** shows the schematic top view and a cross‐sectional transmission electron microscope (TEM) image of a MATATOS device.

Typical output characteristics (*I* DS−*V*DS) of the self‐aligned Si nanowire FET based flash mem‐ ory are shown in **Figure 9a** (MATATOS) with smooth and well‐saturated drain current curves and a small source and drain contact resistance. **Figure 9b**–**d** shows the transfer characteristics of the three memory devices with counterclockwise hysteresis loops suggesting the charging and discharging behaviour. By comparing the memory window, the MATATOS and MATOS devices show larger values than the MAHOS device [57].

The programming and erasing (P/E) operations on the MATATOS memory were measured by studying the threshold voltage shift (Δ*V*Th) under different P/E operations and were

**Figure 8.** (a) Schematic of top‐view of the dielectric charge‐trapping flash memory based on Si nanowire FET; (b) cross‐ sectional TEM image of the dielectric flash memory with TAT charge‐trapping layer [57].

between the source/drain electrodes was controlled to be 5 μm. The following process is the deposition of charge‐trapping layer and blocking oxide dielectric. Different charge‐trapping

thickness of 20, 6/8/6, 20 nm, respectively [57]. The blocking oxide for all memory devices was

layers were deposited by ALD with TMA and TEMAH as precursors, respectively. Finally, a 100 nm Pd top gate was formed by the same photolithographic and lift‐off processes as the

Three SONOS‐like charge‐trapping flash memory devices with structures of metal/Al<sup>2</sup>

shows the schematic top view and a cross‐sectional transmission electron microscope (TEM)

ory are shown in **Figure 9a** (MATATOS) with smooth and well‐saturated drain current curves and a small source and drain contact resistance. **Figure 9b**–**d** shows the transfer characteristics of the three memory devices with counterclockwise hysteresis loops suggesting the charging and discharging behaviour. By comparing the memory window, the MATATOS and MATOS

The programming and erasing (P/E) operations on the MATATOS memory were measured by studying the threshold voltage shift (Δ*V*Th) under different P/E operations and were

**Figure 8.** (a) Schematic of top‐view of the dielectric charge‐trapping flash memory based on Si nanowire FET; (b) cross‐

sectional TEM image of the dielectric flash memory with TAT charge‐trapping layer [57].

O3 /Ta<sup>2</sup> O5 /SiO<sup>2</sup>

/Si (MAHOS) have been fabricated and electrically characterized [57]. **Figure 8**

was deposited by sputtering, whereas Al<sup>2</sup>

DS−*V*DS) of the self‐aligned Si nanowire FET based flash mem‐

(TAT) and a reference HfO<sup>2</sup>

/Si (MATOS) and metal/Al<sup>2</sup>

O3

, with

O3 /

O3 /

and HfO<sup>2</sup>

O5 , Ta<sup>2</sup> O5 /Al<sup>2</sup> O3 /Ta<sup>2</sup> O5

/Si (MATATOS), metal/Al<sup>2</sup>

O3 . Ta<sup>2</sup> O5

devices show larger values than the MAHOS device [57].

layer and stacks were fabricated—Ta<sup>2</sup>

*4.2.3. Characterization and performance discussion*

selected to be 25 nm for Al<sup>2</sup>

image of a MATATOS device.

Typical output characteristics (*I*

source/drain electrodes.

Ta<sup>2</sup> O5 /Al<sup>2</sup> O3 /Ta<sup>2</sup> O5 /SiO<sup>2</sup>

HfO<sup>2</sup>

/SiO<sup>2</sup>

114 Nanowires - New Insights

**Figure 9.** (a) Output characteristics of MATATOS device for *V*GS from −4 to −1 V with 0.2 V step; transfer characteristics of (b) MATATOS, (c) MATOS, and (d) MAHOS devices, showing counterclockwise hysteresis loops under different *V*GS sweep ranges [57].

illustrated in **Figure 10**. The *I*DS−*V*GS curves show clear Δ*V*Th under accumulative rectan‐ gular gate voltage pulses but exhibiting same subthreshold slope (∼300 mV/dec) before and after the programming or erasing operations. This indicates that the Δ*V*Th is due to the fixed charges in the charge‐trapping layers instead of the interface states. By stress‐ ing a positive gate voltage, the electrons will tunnel through the tunnelling oxide from the Si nanowire and get trapped in the charge‐trapping layers. This corresponds to the programming operations, which will result into a *V*Th shift towards the positive direction. Negative gate voltage will reversely shift the *V*Th in the opposite direction by removing the pre‐trapped electrons from the charge‐trapping layer to the Si nanowire. This is defined as the erasing operations. By comparing the Δ*V*Th under different P/E gate voltages, it was found that both MATATOS and MATOS devices showed faster speed than the MAHOS device, and MATOS device showed a larger Δ*V*Th for a long P/E time due to the thicker charge‐trapping layer.

**Figure 11a** shows the charge retention properties of the devices. Less than 25% charge loss was observed for both MATATOS and MATOS devices. **Figure 11b** demonstrated the

**Figure 10.** (a) Programming and (b) erasing operations with accumulated P/E time at ±10 V gate voltage pulses on the MATATOS flash memory device [57].

**Figure 11.** (a) Retention and (b) endurance characteristics of three flash memory devices [57].

endurance properties of the three devices. Very small memory window degradations were observed for all the devices after 10<sup>7</sup> P/E cycles. Such good endurance behaviour arises from the good interface between the Si nanowire and the high‐k stacks formed in the self‐ alignment fabrication process.

The design of the TAT charging‐trapping stack with an Al<sup>2</sup> O3 layer sandwiched between two Ta<sup>2</sup> O5 layers is for the multiple charge storage, in which the Al<sup>2</sup> O3 layer functions as the blocking oxide for the first Ta<sup>2</sup> O5 layer and tunnelling oxide for the second Ta<sup>2</sup> O5 layer. As shown in **Figure 12**, clear two‐step charging behaviour is successfully observed in the MATATOS device. The first step around 10 V gate voltage is due to the charge storage in the first Ta<sup>2</sup> O5 layer, and the second step at around 20 V is observed indicating the charge‐trap‐ ping centres in both Ta<sup>2</sup> O5 layers have been filled with electrons. The charge density of the two Ta<sup>2</sup> O5 layers are calculated to be 1.75 × 1019 and 4.98 × 1019 cm−3, respectively.

**Figure 12.** Δ*V*Th as a function of programming voltage of the three devices. MATATOS device shows a two‐step charging storage behaviour. Inset: Δ*V*Th versus programming voltage of the MATATOS device under gate voltage pulse with different width [57].

By comparing the above results from the flash memory based on Si nanowire FET to the elec‐ trical performance of planar capacitor structure with same gate dielectric stack, the nanowire FET‐based flash memory exhibits faster speed, better endurance and more remarkable dis‐ crete multi‐bit memory storage at lower operation voltages [58]. The scaling from planar Si to nanoscale Si nanowire channel effectively enhance the gate electric field introduced by the gate‐surrounding structure, enabling faster speed and lower operation voltage. The device reliability is improved with the clean nanowire surface and dielectric interfaces formed by using the self‐alignment technique. Such a high‐performance and CMOS compatible flash memory is very attractive for future multi‐bit non‐volatile memory applications.

#### **4.3. Silicon nanowire‐based molecular charge‐trapping memory**

#### *4.3.1. Introduction of redox‐active molecules*

endurance properties of the three devices. Very small memory window degradations were

**Figure 10.** (a) Programming and (b) erasing operations with accumulated P/E time at ±10 V gate voltage pulses on the

from the good interface between the Si nanowire and the high‐k stacks formed in the self‐

As shown in **Figure 12**, clear two‐step charging behaviour is successfully observed in the MATATOS device. The first step around 10 V gate voltage is due to the charge storage in the

layers are calculated to be 1.75 × 1019 and 4.98 × 1019 cm−3, respectively.

layer, and the second step at around 20 V is observed indicating the charge‐trap‐

layers is for the multiple charge storage, in which the Al<sup>2</sup>

O5

**Figure 11.** (a) Retention and (b) endurance characteristics of three flash memory devices [57].

P/E cycles. Such good endurance behaviour arises

layer sandwiched between

layer functions as

O5 layer.

O3

O3

layer and tunnelling oxide for the second Ta<sup>2</sup>

layers have been filled with electrons. The charge density of the

observed for all the devices after 10<sup>7</sup>

The design of the TAT charging‐trapping stack with an Al<sup>2</sup>

O5

alignment fabrication process.

MATATOS flash memory device [57].

116 Nanowires - New Insights

the blocking oxide for the first Ta<sup>2</sup>

two Ta<sup>2</sup>

first Ta<sup>2</sup>

two Ta<sup>2</sup>

O5

O5

O5

ping centres in both Ta<sup>2</sup>

CMOS and semiconductor non‐volatile memory scaling have generated various approaches towards building memory devices with higher scalability and better performance. The hybrid silicon/molecular approach is very attractive as a technology that leverages advan‐ tages afforded by a molecule‐based active medium with the vast infrastructure of traditional MOS technology.

In reduction‐oxidation, redox‐active molecules can be attached on various surfaces such as Si and SiO<sup>2</sup> by forming a self‐assembled monolayer (SAM) or multiple layers with simple and low‐cost processes. Due to the inherent reduction and oxidation of the redox centres, such molecules can exhibit distinct charged and discharged states which can represent the logic on and off states. It has been demonstrated that the redox‐active molecules attached on Si structures are stable and can endure more than 1012 P/E cycles [59]. Such an excellent reli‐ ability is derived from the intrinsic properties of redox molecules. Thus, incorporating redox‐ active molecules as charge‐storage medium in a Si‐based flash memory is quite interesting. By taking advantage of the high‐quality thin oxide surrounding the Si nanowire, which is readily feasible in various chemical functionalizations, a molecular flash memory with redox molecules attached on the Si nanowire surface serving as the charge storage medium can have even better memory performance including lower operation voltage, faster speed, better device scalability and better reliability.

#### *4.3.2. Redox‐active molecules attachment and memory device fabrication*

Two redox‐active molecules were integrated and studied in the molecular flash memory: α‐ferrocenylethanol (referred as ferrocene) and Ru<sup>2</sup> (ap)<sup>4</sup> (C<sup>2</sup> C6 H4 P(O)(OH)<sup>2</sup> ) (referred as Ru<sup>2</sup> ), in which ap = 2‐anilinopyridinate, with the molecular structures shown in **Figure 13** [60].

The molecular flash memory device fabrication follows the self‐alignment Si nanowire FET process as well. After the catalyst patterning, nanowire growth and oxidation and source/ drain electrode formation, the molecules SAM attachment on the nanowire was performed by placing droplets of a solution of dichloromethane with 3‐mM ferrocene and 2 mM Ru<sup>2</sup> on the active areas separately [60]. Each drop was in place for 3–4 minutes and the samples were held at 100°C in an N<sup>2</sup> environment during the attachment. Saturated SAM will be formed after ∼30 minutes. After the self‐assembly process, dichloromethane was used to rinse the substrates to remove any residual molecules that are not bonded to the SiO<sup>2</sup> surface. Then, the samples were immediately loaded into the ALD chamber for a deposition of 25 nm Al<sup>2</sup> O3 with TMA and H<sup>2</sup> O as precursors at 100°C. Finally, a 100 nm Pd top gate was formed with photo‐ lithographic and lift‐off processes. A reference sample without molecules was fabricated for comparative study.

**Figure 13.** Molecular structure of (a) α‐ferrocenylethanol and (b) Ru<sup>2</sup> (ap)<sup>4</sup> (C<sup>2</sup> C6 H4 P(O)(OH)<sup>2</sup> ) [60].

#### *4.3.3. Electrical characterization and memory performance*

In reduction‐oxidation, redox‐active molecules can be attached on various surfaces such as

and low‐cost processes. Due to the inherent reduction and oxidation of the redox centres, such molecules can exhibit distinct charged and discharged states which can represent the logic on and off states. It has been demonstrated that the redox‐active molecules attached on Si structures are stable and can endure more than 1012 P/E cycles [59]. Such an excellent reli‐ ability is derived from the intrinsic properties of redox molecules. Thus, incorporating redox‐ active molecules as charge‐storage medium in a Si‐based flash memory is quite interesting. By taking advantage of the high‐quality thin oxide surrounding the Si nanowire, which is readily feasible in various chemical functionalizations, a molecular flash memory with redox molecules attached on the Si nanowire surface serving as the charge storage medium can have even better memory performance including lower operation voltage, faster speed, better

Two redox‐active molecules were integrated and studied in the molecular flash memory:

The molecular flash memory device fabrication follows the self‐alignment Si nanowire FET process as well. After the catalyst patterning, nanowire growth and oxidation and source/ drain electrode formation, the molecules SAM attachment on the nanowire was performed by placing droplets of a solution of dichloromethane with 3‐mM ferrocene and 2 mM Ru<sup>2</sup>

the active areas separately [60]. Each drop was in place for 3–4 minutes and the samples were

after ∼30 minutes. After the self‐assembly process, dichloromethane was used to rinse the

lithographic and lift‐off processes. A reference sample without molecules was fabricated for

samples were immediately loaded into the ALD chamber for a deposition of 25 nm Al<sup>2</sup>

substrates to remove any residual molecules that are not bonded to the SiO<sup>2</sup>

in which ap = 2‐anilinopyridinate, with the molecular structures shown in **Figure 13** [60].

(ap)<sup>4</sup> (C<sup>2</sup> C6 H4

environment during the attachment. Saturated SAM will be formed

O as precursors at 100°C. Finally, a 100 nm Pd top gate was formed with photo‐

(ap)<sup>4</sup> (C<sup>2</sup> C6 H4

P(O)(OH)<sup>2</sup>

) [60].

P(O)(OH)<sup>2</sup>

) (referred as Ru<sup>2</sup>

surface. Then, the

O3 with

),

on

by forming a self‐assembled monolayer (SAM) or multiple layers with simple

Si and SiO<sup>2</sup>

118 Nanowires - New Insights

device scalability and better reliability.

held at 100°C in an N<sup>2</sup>

TMA and H<sup>2</sup>

comparative study.

*4.3.2. Redox‐active molecules attachment and memory device fabrication*

α‐ferrocenylethanol (referred as ferrocene) and Ru<sup>2</sup>

**Figure 13.** Molecular structure of (a) α‐ferrocenylethanol and (b) Ru<sup>2</sup>

Schematic structure of a completed molecular flash memory device was shown in **Figure 14a**. **Figure 14b** shows the TEM image of the cross‐section of a ferrocene‐attached molecular flash memory. A clear gate surrounding structure has been obtained, with an "intermixed" region observed (indicated by the red dash line). Schottky‐barrier p‐type MOSFET characteristics have been observed for the Si nanowire based molecular flash memory cells as the source/ drain was engineered as Schottky junction. **Figure 15a** and **b** shows the output characteristics of a typical ferrocene molecular flash memory. Smooth and well saturated *I* DS−*V*DS curves have been observed with clear leakage‐affected region and the weak, moderate and strong inver‐ sion operation regions. From the *I* DS−*V*GS curves shown in **Figure 15c** and **d**, counterclockwise hysteresis loops were obtained for both devices, suggesting the charge trapping mechanism. The log‐scale transfer characteristics shown in the insets demonstrated an on/off ratio as high as ∼10<sup>7</sup> . The inset (ii) in **Figure 15c** shows the *I*DS−*V*GS curves of the reference sample (with‐ out molecules), and a negligible memory window was observed, ruling out the possibility of charge storage in the Al<sup>2</sup> O3 dielectric traps.

The P/E speed characterizations of the ferrocene flash memory were shown in **Figure 16a** and **b**. Threshold voltage shift towards the positive (negative) direction was observed during the programming (erasing) operations, indicating the electrons (holes) were injected from the Si nanowire through the SiO<sup>2</sup> and stored in the centres of the molecules. From **Figure 16c** and **d**, both molecular memory devices showed fast P/E speed, which arises from the intrinsic fast speed of the charging behaviour of the molecules and the strong electric field induced through the top gate control over the channel in the gate‐surrounding structure.

Similar to the multiple charging behaviour demonstrated in the previous dielectric flash memory, the Ru<sup>2</sup> molecular flash memory is also designed and expected for the application

**Figure 14.** (a) Schematic structure of a completed molecular flash memory device based on Si nanowire FET; (b) TEM image of the cross section of a ferrocene‐attached molecular flash memory. The red dashed line indicates the ferrocene‐ embedded Al<sup>2</sup> O3 region. Inset: Cross section of the nanowire channel, with SiO<sup>2</sup> layer indicated by the dashed line [60].

**Figure 15.** (a) Linear and (b) log‐scale output characteristics of ferrocene molecular flash memory; *I* DS−*<sup>V</sup>*GS of the (c) ferrocene and (d) Ru<sup>2</sup> molecular flash memory with the insets showing the log‐scale transfer curves. Inset (ii) in (c) shows the *I*DS−*V*GS curves of the reference sample with negligible hysteresis observed [60].

**Figure 16.** (a) Programming and (b) erasing operations of the ferrocene molecular memory under accumulative rectangular P/E gate voltage pulses. Speed characterizations of the (c) ferrocene and (d) Ru<sup>2</sup> molecular flash memory [60].

of multi‐bit memory storage due to the two redox centres, which can exhibit stable and dis‐ tinct charged states at different voltage levels [57, 60]. As shown in **Figure 17b**, two charged steps were observed at around 10 and 14 V, respectively. The overall charging density of the Ru<sup>2</sup> SAM was calculated to be 1.12 × 1013 cm⁻<sup>2</sup> , which is sufficiently high for discrete multi‐bit memory applications. One of the most intriguing features of a molecular flash memory is the reliability. **Figure 17c**–**f** shows the date retention and the endurance properties of the

**Figure 15.** (a) Linear and (b) log‐scale output characteristics of ferrocene molecular flash memory; *I*

**Figure 16.** (a) Programming and (b) erasing operations of the ferrocene molecular memory under accumulative

rectangular P/E gate voltage pulses. Speed characterizations of the (c) ferrocene and (d) Ru<sup>2</sup>

the *I*DS−*V*GS curves of the reference sample with negligible hysteresis observed [60].

molecular flash memory with the insets showing the log‐scale transfer curves. Inset (ii) in (c) shows

ferrocene and (d) Ru<sup>2</sup>

120 Nanowires - New Insights

DS−*<sup>V</sup>*GS of the (c)

molecular flash memory [60].

**Figure 17.** Δ*V*Th of (a) ferrocene and reference sample and (b) Ru<sup>2</sup> flash memory as a function of P/E voltage. Room temperature retention characteristics of (c) ferrocene and (d) Ru<sup>2</sup> flash memory. Endurance properties of (e) ferrocene and (f) Ru<sup>2</sup> flash memory [60].

ferrocene and Ru<sup>2</sup> flash memory devices, respectively. The projected 10 year memory window showed a charge loss of only 20%, and the excellent endurance characteristics were demon‐ strated by the negligible memory window degradation after 109 P/E cycles, which is about 10,000 times better than that of the conventional floating gate memory [60]. Such a good reli‐ ability is due to the intrinsic stable redox behaviour of the molecules and the high‐quality tunnelling oxide with clean solid/molecule and dielectric interfaces by using the self‐aligned nanowire FET fabrication process. The nanowire FET based molecular flash memory is thus very attractive for future fast speed, high‐endurance and high‐density on‐chip non‐volatile memory applications.

## **5. Nanowire field‐effect transistor as a platform for novel materials research**

Semiconductor nanowires have shown unique properties in the manner of both physics and technology. The significance of nanowires over planar materials has been more and more discovered and focussed through various interesting and fundamental phenomena, when nanowires have nanoscale diameter at or even below the characteristic length scale of such basic parameters as phonon mean free path, exciton Bohr radius, magnetic domain size, exci‐ ton diffusion length and so forth [61]. Many physical properties of semiconductor nanowire are utterly different from the planar bulk materials due to the confines of nanowire surface. Moreover, the large surface‐to‐volume ratio of nanowires allows for distinct structural, electrical and transport behaviours, as well as advanced technological applications.

This section focuses on the applications of nanowire MOSFETs as a platform for novel mate‐ rials research. Topological insulator materials and devices are discussed here as an example illustrating the significance of semiconductor with nanowire morphology in the understand‐ ing and implementation of fundamental physics and properties behind the materials.

## **5.1. Introduction to topological insulators**

Topological insulators are characterized as a new class of materials having insulating band gaps in the bulk but gapless surface states topologically protected by time‐reversal symmetry [62, 63]. Recently discovered three‐dimensional topological insulators such as Bi<sup>2</sup> Se3 , Bi<sup>2</sup> Te<sup>3</sup> and Sb<sup>2</sup> Te<sup>3</sup> have been intensively investigated both theoretically and experimentally [64, 65]. Most current experimental research focuses on the surface states of thin films grown by a molecular beam epitaxy (MBE) or mechanically exfoliated from bulk materials. For exam‐ ple, the gapless surface states featuring helical Dirac electrons have been observed by angle‐ resolved photoemission spectroscopy (ARPES) and scanning tunnelling microscopy (STEM) techniques. A few groups have reported the modification of surface conduction of such mate‐ rials by doping, electrical gating or polarized light [66–68]. But there has rarely been reported of high‐performance nanoelectronic devices based on topological insulators such as the ana‐ log of MOSFET. For conventional CMOS devices, the Si surface conduction is protected by thermal SiO<sup>2</sup> to optimize the inversion properties for good transistor performance. For topo‐ logical insulators, the gapless surface state is derived from the inherent material properties and maintains a robust surface conduction. Therefore, it will be very attractive to integrate the topological insulators as the active conducting channel in MOSFETs.

However, despite the significant efforts made in engineering of materials and devices based on bulk topological insulators, it is always a challenge to modulate the surface conduction due to the dominant contribution from bulk conduction. Topological insulator nanowires can be expected to greatly enhance the surface conduction due to their extra‐high surface‐to‐ volume ratio. Here, we will review the work on MOSFET devices based on topological insu‐ lator nanowires and the effective separation of surface conduction from the bulk conduction by an external electrical means [69].

#### **5.2. VLS nanowire synthesis of topological insulator Bi2 Se3 nanowires**

The Bi<sup>2</sup> Se3 topological insulator nanowire FETs were fabricated by following the self‐alignment process, similar to that of previous Si nanowire FETs [69]. The essential steps are as follows: the SiO<sup>2</sup> /Si substrates with patterned Au catalyst were loaded in the downstream end in a horizon‐ tal tube furnace while Bi<sup>2</sup> Se3 source powder was located at the heating centre. The furnace was heated to a temperature in a range of 500–550°C and kept for 2 hours with a 50 sccm flow of Ar gas as a carrier gas. The Bi<sup>2</sup> Se3 nanowires were grown following the VLS route at pre‐defined locations with typical length of 20 μm and 50 nm in diameter. Ti (3 nm)/Pt (100 nm) source/ drain electrodes were formed by photolithography. A layer of 30 nm HfO<sup>2</sup> was then deposited at 250°C by ALD covering the nanowire channel and also a part of source/drain electrodes. The final step is the formation of 100 nm Pd top gate electrode.

**Figure 18a** shows the SEM image of the as‐synthesized Bi<sup>2</sup> Se3 nanowires. Au nanoparticles were found at the top end of each wire, indicating the VLS mechanism. The high‐resolution TEM (HRTEM) image shown in **Figure 18** demonstrates that the Bi<sup>2</sup> Se3 nanowires are in a well‐defined single‐crystal rhombohedral phase with growth direction close to [11¯ 20]. From the cross‐sectional TEM image (**Figure 18d**); it is clear that the hexagonal nanowire core is surrounded by the insulating HfO<sup>2</sup> and the Omega‐shaped top gate [69].

#### **5.3. Characterizations of Bi2 Se3 nanowire FET**

ferrocene and Ru<sup>2</sup>

122 Nanowires - New Insights

memory applications.

flash memory devices, respectively. The projected 10 year memory window

P/E cycles, which is about

Se3 , Bi<sup>2</sup> Te<sup>3</sup>

showed a charge loss of only 20%, and the excellent endurance characteristics were demon‐

10,000 times better than that of the conventional floating gate memory [60]. Such a good reli‐ ability is due to the intrinsic stable redox behaviour of the molecules and the high‐quality tunnelling oxide with clean solid/molecule and dielectric interfaces by using the self‐aligned nanowire FET fabrication process. The nanowire FET based molecular flash memory is thus very attractive for future fast speed, high‐endurance and high‐density on‐chip non‐volatile

**5. Nanowire field‐effect transistor as a platform for novel materials research**

Semiconductor nanowires have shown unique properties in the manner of both physics and technology. The significance of nanowires over planar materials has been more and more discovered and focussed through various interesting and fundamental phenomena, when nanowires have nanoscale diameter at or even below the characteristic length scale of such basic parameters as phonon mean free path, exciton Bohr radius, magnetic domain size, exci‐ ton diffusion length and so forth [61]. Many physical properties of semiconductor nanowire are utterly different from the planar bulk materials due to the confines of nanowire surface. Moreover, the large surface‐to‐volume ratio of nanowires allows for distinct structural,

electrical and transport behaviours, as well as advanced technological applications.

ing and implementation of fundamental physics and properties behind the materials.

[62, 63]. Recently discovered three‐dimensional topological insulators such as Bi<sup>2</sup>

**5.1. Introduction to topological insulators**

and Sb<sup>2</sup>

thermal SiO<sup>2</sup>

Te<sup>3</sup>

This section focuses on the applications of nanowire MOSFETs as a platform for novel mate‐ rials research. Topological insulator materials and devices are discussed here as an example illustrating the significance of semiconductor with nanowire morphology in the understand‐

Topological insulators are characterized as a new class of materials having insulating band gaps in the bulk but gapless surface states topologically protected by time‐reversal symmetry

Most current experimental research focuses on the surface states of thin films grown by a molecular beam epitaxy (MBE) or mechanically exfoliated from bulk materials. For exam‐ ple, the gapless surface states featuring helical Dirac electrons have been observed by angle‐ resolved photoemission spectroscopy (ARPES) and scanning tunnelling microscopy (STEM) techniques. A few groups have reported the modification of surface conduction of such mate‐ rials by doping, electrical gating or polarized light [66–68]. But there has rarely been reported of high‐performance nanoelectronic devices based on topological insulators such as the ana‐ log of MOSFET. For conventional CMOS devices, the Si surface conduction is protected by

logical insulators, the gapless surface state is derived from the inherent material properties

have been intensively investigated both theoretically and experimentally [64, 65].

to optimize the inversion properties for good transistor performance. For topo‐

strated by the negligible memory window degradation after 109

The Bi<sup>2</sup> Se3 nanowire FET shows excellent transfer characteristics, as shown in **Figure 19**, such as close‐to‐zero cutoff current, strong‐inversion‐like on state current and over 10<sup>8</sup> on/off ratio within 1.0 V gate voltage. The nanowire FET has unipolar current dominated by electron conduction, which is similar to a conventional long‐channel Schottky‐barrier MOSFET with either electron or hole conduction determined by the unipolar Schottky junctions at the source and drain. **Figure 19b** and **c** shows well‐saturated and smooth *I* DS−*V*DS curves. *I* DS saturates roughly at *V*DS = *V*GS− *V*Th in the highly conductive region but does not saturate at *V*DS ≈ 3φ<sup>t</sup> in the weak/moderate conductive region. Instead, *I*DS keeps increasing significantly after 3φ<sup>t</sup> , suggesting the fact that the Bi<sup>2</sup> Se3 nanowire FET does not follow the diffusion current model as described for the conventional MOSFETs. It is believed that *I* DS in the weak/moderate con‐ ductive regions is also dominated by drift current [69].

**Figure 18.** (a) SEM image of Bi<sup>2</sup> Se3 nanowires synthesized by following the VLS mechanism; (b) HRTEM image of Bi<sup>2</sup> Se3 nanowire showing the [ <sup>11</sup>¯ 20] growth direction. Inset: Magnified region of the nanowire; (c) schematic structure of a Bi2 Se3 nanowire FET; (d) cross‐sectional TEM image of a Bi<sup>2</sup> Se3 nanowire FET [69].

Further characterizations at different temperatures confirm that the saturation of *I*DS is due to the electron velocity saturation at the source end instead of the pinch‐off at the drain end of the nanowire channel, because a linear relationship was observed between the saturation drain current and the over‐threshold voltage (*V*GS−*V*Th) as shown in **Figure 19**. By comparing the transfer characteristics at different temperatures (**Figure 20a**), it was found that *I* DS−*V*GS curves obtained at temperatures lower than 240 K show a clear cutoff region with higher on/off ratio. The off state current for temperatures greater than 240 K flattens and saturates at negative voltages much below *V*Th. Such temperature dependence indicates metallic con‐ duction in the on state and insulating behaviour in the off state. By fitting the strongly acti‐ vated temperature‐dependent current to *I* DS,Off = *I* <sup>0</sup> *<sup>e</sup>* <sup>−</sup>*E*<sup>a</sup> /*kT* where *E*<sup>a</sup> is the activation energy, *k* is

Boltzmann's constant and *I*<sup>0</sup> is a constant prefactor. *E*<sup>a</sup> value of about 0.33 eV was obtained which is very close to the reported band gap value of bulk Bi<sup>2</sup> Se3 [69].

**Figure 19.** (a) Transfer characteristics and (b and c) output characteristics of the Bi<sup>2</sup> Se3 nanowire FET at 77 K. (d) *I* DS as a function of over‐threshold voltage. Inset: Linear fit slope versus temperature [69].

Further characterizations at different temperatures confirm that the saturation of *I*DS is due to the electron velocity saturation at the source end instead of the pinch‐off at the drain end of the nanowire channel, because a linear relationship was observed between the saturation drain current and the over‐threshold voltage (*V*GS−*V*Th) as shown in **Figure 19**. By comparing the transfer characteristics at different temperatures (**Figure 20a**), it was found that *I*

Se3

curves obtained at temperatures lower than 240 K show a clear cutoff region with higher on/off ratio. The off state current for temperatures greater than 240 K flattens and saturates at negative voltages much below *V*Th. Such temperature dependence indicates metallic con‐ duction in the on state and insulating behaviour in the off state. By fitting the strongly acti‐

> DS,Off = *I* <sup>0</sup> *<sup>e</sup>* <sup>−</sup>*E*<sup>a</sup> /*kT*

where *E*<sup>a</sup>

nanowires synthesized by following the VLS mechanism; (b) HRTEM image of Bi<sup>2</sup>

20] growth direction. Inset: Magnified region of the nanowire; (c) schematic structure of a

nanowire FET [69].

vated temperature‐dependent current to *I*

Se3

nanowire FET; (d) cross‐sectional TEM image of a Bi<sup>2</sup>

**Figure 18.** (a) SEM image of Bi<sup>2</sup>

nanowire showing the [ <sup>11</sup>¯

124 Nanowires - New Insights

Bi2 Se3

DS−*V*GS

Se3

is the activation energy, *k* is

**Figure 20.** (a) *I*DS−*V*GS curves at different temperature; (b) ln(*I*DS) at off state versus 1/kT above 240 K and its fit to *I* DS, Off = *I* <sup>0</sup> *e* <sup>−</sup>*Ea* /*kT*. [69].

#### **5.4. Performance discussion**

In the off state, the gate voltage is large enough to fully deplete the electrons from the nanow‐ ire, and the small temperature‐dependent off‐state current is due to the thermal excitations across the energy band gap of the bulk of Bi<sup>2</sup> Se3 nanowire. This further indicates the fact that the electric field generated surround the gate by the gate voltage below the threshold is strong enough to modify the spectrum of the nanowire and destroy the surface conduction channels [69]. Different with the conventional semiconductor nanowires, the saturated current of the Bi2 Se3 nanowire FET in the on state is linear in gate voltage, indicating metallic conduction and is most likely flowing at the nanowire surface. Such interpretation also agrees with the temperature dependence shown in **Figure 20a**. The most significant achievement is that the surface metallic conduction and the insulating switch‐off can be controlled by a surprisingly small gate voltage, resulting from the excellent gate control by the surrounding gate nanowire FET structure.

The above electrical performance obtained from the Bi<sup>2</sup> Se3 topological insulator nanowire FET is very impressive by taking advantages of the nanowire surrounding gate structure, lead‐ ing to an enhanced gate control over the nanowire channel to realize electrical behaviour that have not been observed on planar counterparts. For example, the sharp switching from cutoff to surface conduction and saturation current by a gate voltage of a few volts is neither expected nor has been previously reported. Since the spin and momentum are locked in the surface states of topological insulators, possibilities of electric manipulation of spin current using gate voltage as well as novel circuit applications may be opened up using such one‐ dimensional topological insulator materials.

## **6. Conclusions**

The physics and operation principles of nanowire materials and device have been sys‐ tematically studied. Semiconductor nanowires enable the surrounding‐gate structures, which significantly enhance the gate control over the channel in the electrical devices, leading to quite distinct and interesting device behaviours compared with the planar or bulk materials. The "self‐alignment" approach enables simultaneous batch fabrication of large numbers of nanowire devices, while effectively reducing the processing steps in which nanowire surfaces might be contaminated. Si nanowire FETs with excellent elec‐ trical performances have been used as the platform to fabricate novel flash non‐volatile memory devices. Both high‐k dielectric and molecular charge‐trapping memory demon‐ strate excellent memory behaviour and are very interesting for future on‐chip non‐volatile memory applications. The "self‐alignment" method and the nanowire FET device archi‐ tecture have been proved to be an effective platform and approach to be implemented and study other novel materials. High‐performance topological insulator Bi<sup>2</sup> Se3 nanowire FET has been fabricated and investigated. The surface states are successfully separated from the bulk conduction within a small range of gate voltage due to the strong electric field induced through the surrounding‐gate structure formed in the self‐alignment fabrication process. Such a high‐performance nanoelectronic device and the analysis on surface con‐ duction have never been previously reported. Therefore, the nanowire MOSFETs not only exhibit their potential in future CMOS scaling at advanced technology nodes but also provide an excellent approach for novel materials research towards next‐generation micro and nanoelectronic devices.

## **Author details**

Hao Zhu

**5.4. Performance discussion**

126 Nanowires - New Insights

Bi2 Se3

FET structure.

**6. Conclusions**

across the energy band gap of the bulk of Bi<sup>2</sup>

The above electrical performance obtained from the Bi<sup>2</sup>

dimensional topological insulator materials.

In the off state, the gate voltage is large enough to fully deplete the electrons from the nanow‐ ire, and the small temperature‐dependent off‐state current is due to the thermal excitations

Se3

the electric field generated surround the gate by the gate voltage below the threshold is strong enough to modify the spectrum of the nanowire and destroy the surface conduction channels [69]. Different with the conventional semiconductor nanowires, the saturated current of the

is very impressive by taking advantages of the nanowire surrounding gate structure, lead‐ ing to an enhanced gate control over the nanowire channel to realize electrical behaviour that have not been observed on planar counterparts. For example, the sharp switching from cutoff to surface conduction and saturation current by a gate voltage of a few volts is neither expected nor has been previously reported. Since the spin and momentum are locked in the surface states of topological insulators, possibilities of electric manipulation of spin current using gate voltage as well as novel circuit applications may be opened up using such one‐

The physics and operation principles of nanowire materials and device have been sys‐ tematically studied. Semiconductor nanowires enable the surrounding‐gate structures, which significantly enhance the gate control over the channel in the electrical devices, leading to quite distinct and interesting device behaviours compared with the planar or bulk materials. The "self‐alignment" approach enables simultaneous batch fabrication of large numbers of nanowire devices, while effectively reducing the processing steps in which nanowire surfaces might be contaminated. Si nanowire FETs with excellent elec‐ trical performances have been used as the platform to fabricate novel flash non‐volatile memory devices. Both high‐k dielectric and molecular charge‐trapping memory demon‐ strate excellent memory behaviour and are very interesting for future on‐chip non‐volatile memory applications. The "self‐alignment" method and the nanowire FET device archi‐ tecture have been proved to be an effective platform and approach to be implemented and

has been fabricated and investigated. The surface states are successfully separated from the bulk conduction within a small range of gate voltage due to the strong electric field induced through the surrounding‐gate structure formed in the self‐alignment fabrication

study other novel materials. High‐performance topological insulator Bi<sup>2</sup>

 nanowire FET in the on state is linear in gate voltage, indicating metallic conduction and is most likely flowing at the nanowire surface. Such interpretation also agrees with the temperature dependence shown in **Figure 20a**. The most significant achievement is that the surface metallic conduction and the insulating switch‐off can be controlled by a surprisingly small gate voltage, resulting from the excellent gate control by the surrounding gate nanowire

Se3

nanowire. This further indicates the fact that

topological insulator nanowire FET

Se3

nanowire FET

Address all correspondence to: hao\_zhu@fudan.edu.cn

School of Microelectronics, Fudan University, Shanghai, P.R. China

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