Author details

Raffaele Giordano<sup>1</sup> \*, Vincenzo Izzo<sup>2</sup> and Alberto Aloisio<sup>1</sup>

\*Address all correspondence to: rgiordano@na.infn.it


### References


[4] CPRI Specification V4.1 (2009-02-18), 2009, pp. 21–22 [On-line]. Available: http://www. cpri.info/downloads/CPRI\_v\_4\_1\_2009-02-18.pdf

In this chapter, we have shown how to implement fixed-latency serial IO, essentially by opportunely configuring SerDeses (in particular, the SerDes devices embedded in commercially available Xilinx FPGAs) and by adequately adding a specific control logic to such devices. The proposed architecture is able to operate with fixed latency and it is capable to recover the clock from the serial stream with a predictable phase, which does not change after a power-cycle or a reset of the link. We presented a 2.5-Gbps 8B10B link which is able to serialize 8-bit words, as a detailed example of implementation. We also described the procedure for extending the example architecture in order to transfer packets made of several data words and to synchronously transfer data with an external clock. The presented architecture is also code-independent, i.e. it can be used with any data encoding, provided a special care to

This work is part of the ROAL project (CINECA Grant no. RBSI14JOUV) funded by the Scientific Independence of Young Researchers (SIR) 2014 program of the Italian Ministry of

1 Università Degli Studi Di Napoli "Federico II" and INFN Sezione Di Napoli, Napoli, Italy

[1] Jedec Solid State Technology Association, JEDEC Standard, "Serial Interface for Data

[2] IEEE Standard 1588, IEEE Standard for a Precision Clock Synchronization Protocol for

[3] M. Lipiński, T. Włostowski, J. Serrano and P. Alvarez, "White rabbit: a PTP application for robust sub-nanosecond synchronization," In: 2011 International IEEE Symposium on Precision Clock Synchronization for Measurement Control and Communication (ISPCS), Munich,

\*, Vincenzo Izzo<sup>2</sup> and Alberto Aloisio<sup>1</sup>

the various issues described.

266 Field - Programmable Gate Array

Acknowledgements

Author details

Raffaele Giordano<sup>1</sup>

References

Education, University and Research (MIUR).

\*Address all correspondence to: rgiordano@na.infn.it

Networked Measurement and Control Systems, 2008.

2011, pp. 25–30. doi:10.1109/ISPCS.2011.6070148

2 INFN Sezione di Napoli, Napoli, Italy

Converters," JESD204B.01


[19] InfiniBand Trade Association, "InfiniBand Architecture Specification Volume 2," Nov. 6,

[20] A. Aloisio and R. Giordano, "Testing radiation tolerance of SerDeses for serial links of the SuperB experiment," In: Proceedings of the 2011 IEEE Nuclear Science Symposium, Medical

[21] A. Aloisio and R. Giordano, "Testing radiation tolerance of electronics for the SuperB experiment," In: Proceedings of the 13th ICATPP Conference on Astroparticle, Particle, Space

[22] P. Branchini et al., "Intensive irradiation study on monitored drift tubes chambers," IEEE

[23] P. Branchini et al., "ATLAS MDT chamber behaviour after neutron irradiation and in a

2012 [On-line]. Available: https://cw.infinibandta.org/document/dl/7141

Physics and Detectors for Physics Applications, Como, Oct. 3–7, 2011

high rate background," Nucl. Instrum. Meth. A, 581, 2007, pp. 171–174

Trans. Nucl. Sci., vol. 54, no 3, Part 2, 2007, pp. 648–653

Imaging Conference, Valencia, Oct. 23–29, 2011

268 Field - Programmable Gate Array
