**3. Power consumption in SRAM‐based FPGAs**

The programmable term in FPGA only reflects that any new function can be implemented on the chip even after its fabrication. Programmability/reconfigurability of an FPGA is based on an underlying programming technology, which can cause a change in behavior of a prefab‐ ricated chip. The main programming technologies used in FPGAs are static random memory

The SRAM‐based FPGAs provide ideal prototyping medium and are widely used to inte‐ grate FPGAs in an embedded system [6–8] due to the use of standard CMOS technologies, higher performance, and reprogrammability. However, the larger static power consumption in SRAM cell limits the use of SRAM‐based FPGAs in portable embedded system compared to flash‐based FPGAs [9, 10]. The other concern related to SRAM‐based FPGA is its volatile nature. Although the dynamic power management and duty‐cycling techniques [11, 12] have been used to save static power during idle mode of FPGA, these techniques are not very effec‐ tive due to the energy consumption associated with the resulting reconfiguration process. Due to large load capacitance and high access rate, SRAM cells are responsible for consuming sig‐ nificant portion of the total power of the design. Thus, SRAM power consumption is an impor‐ tant consideration for designers to find the balance between the performance and the overall power consumption. The speed of the SRAM cell in FPGA is not a critical factor because it does not affect the operating speed of the circuit implemented in FPGA as mentioned in ref. [13].

In this chapter, we investigate the various factors responsible for power consumption in SRAM‐based FPGAs and review the different techniques proposed in the literature to save the power. We will also consider the static and dynamic power in the conventional 6T SRAM cell and its architecture. Various design techniques, presented in the literature, to reduce power consumption in SRAM cell will be reviewed in detail with their merits and demerits. A data‐ aware power‐efficient SRAM cell will be discussed to save power and to optimize the stability.

SRAM cells are the basic cells used for SRAM‐based FPGA. These cells are scattered through‐ out the design in form of an array and mainly used to program: (1) the routing interconnects of FPGAs and (2) configurable logic blocks (CLBs) that are used to implement logic func‐ tions. SRAM‐based programming technology has become the dominant approach for FPGAs because of its reprogrammability and the use of standard CMOS process technology, which results in larger package density and higher speed. Due to the volatile nature of SRAM tech‐ nology, SRAM‐based FPGAs lose their configured data whenever power supply is switched off and need to be reprogrammed every time when the power supply is turned on. Hence, almost every system using SRAM‐based FPGAs contains an additional nonvolatile memory such as flash programmable read only memory (PROM) or EEPROM to store the configura‐ tion data and load it into the SRAM‐based FPGA whenever power is on. In many applications, a complex programmable logic device (CPLD) is used in addition to the external configuration memory to perform the vital functions of the system necessary at power‐up. The first static memory‐based FPGA (commonly called an SRAM‐based FPGA) was proposed by Wahlstrom in 1967 [14]. This architecture is allowed for both logic and interconnection configuration using

(SRAM), flash memory, and antifuse [2–5].

222 Field - Programmable Gate Array

**2. SRAM‐based FPGAs**

In the recent years, the traditional FPGA research area has shifted from speed and area over‐ head issues to design of power‐efficient FPGAs due to increased applications of FPGA in por‐ table and nonportable devices. In portable devices power saving is required to enhance the battery life time, whereas in nonmobile devices power saving decides the cost, performance, and reliability of the device. The main sources of power consumption in FPGA are static and dynamic power [10, 12, 15, 16].

Static power is consumed when device/system is idle and leakage current flows in the sys‐ tem. The various leakage currents in OFF transistor are subthreshold leakage current, gate‐ induced drain leakage, junction leakage current, and direct tunneling current [17–19].

Dynamic power consumption is due to the switching activity of the transistors in normal oper‐ ational mode. The dynamic power consumption depends on the parasitic capacitance, power supply, switching activity, and frequency of operation and mathematically expressed as [20]:

$$P\_{dyn} = \eta \, \mathbb{C}\_{\mathbb{L}} V\_{dd}^2 f \tag{1}$$

where *CL* is the load capacitance, *Vdd* is the power supply, *f* is the frequency of operation, and *η* is the switching activity.

FPGA design consumes larger static power than the ASIC design due to excessive leakage currents [21–23], which is due to more number of transistors per logic. Other components, which are responsible for larger power consumption, are circuits used to provide flexibility to FPGA, number of configuration bits, lookup‐tables (LUTs), and presence of large number of programmable switches.
