**1. Introduction**

A drift chamber (DC) is a detector used in high energy physics experiments for determin‐ ing charged particle trajectories. It consists of a gas volume and of an array of thin wires at high voltages generating high electric fields. Charged particles passing through the gas ion‐ ize it creating electron/ion pairs along their path [1], which, accelerated by the electric fields, produce signal pulses on the wires. The signal pulses from all the wires are then collected and the particle trajectory is tracked assuming that the distances of closest approach (the impact parameter) between the particle trajectory and the wires coincide with the distance between the closest ion cluster and the corresponding nearest wire [1, 2]. The widespread use of light, helium‐based gas mixtures, aimed at minimizing the multiple scattering contribution to the momentum measurement for low momentum particles, produces, as a consequence, a low ionization clusters density (12 cluster/cm in a 90/10 helium/isobutane mixture) [3], thus

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introducing a sensible bias in the impact parameter assumption, particularly for short impact parameters and small drift cell [4]. Recently, it has been proposed an alternative track recon‐ struction (cluster counting/timing) technique, which consists in measuring the arrival times on the wires of each individual ionization cluster and combining these times to get a bias‐free estimate of the impact parameter [5, 6]. Typical time separations between consecutive ioniza‐ tion acts, in a helium‐based gas mixture, range from a few ns, at small impact parameters, to a few tens of ns, at large impact parameters [7, 8]. Therefore, in order to efficiently applying the cluster timing technique, it is necessary to have readout interfaces [9, 10] capable of processing high speed signals, in which one can easily isolate pulses due to different ionization cluster.

### **1.1. Hardware**

The wire signals generated by the drift chamber, before being processed, are converted from analog to digital with the use of an analog‐to‐digital converter (ADC). Requirements on drift chamber performance impose the conversions at sampling frequencies of at least 1 GS/s with at least 8‐bit resolution. These constraints, together with the maximum drift times, usually of the order of 1 microsecond, and with the large number of acquisition channels, typically of the order of tens of thousands, mandate some sizeable data reduction, which, however, must preserve all the relevant information. Identifying both the amplitude and the arrival time of each peak associated with each individual ionization cluster is the minimum requirement on the data transfer for storage [5, 6].

This chapter deals with the possibility of using FPGAs for the real‐time analysis of the data generated by a drift chamber [11] and successively converted by an ADC (**Figure 1**).

More specifically, a fast readout algorithm (CluTim [12]) for identifying, in the digitized drift chamber signals, the individual ionization pulse peaks and recording their time and ampli‐ tude has been developed as VHDL/Verilog code implemented on a Xilinx ML605 Evaluation board [13] shown in **Figure 2**, making use of a Virtex 6 FPGA.

In particular, the used device is a Virtex‐6 XC6VLX240T‐1 FFG1156 [14] that allows for a maxi‐ mum input/output clock switching frequency of 710 MHz. The hardware setup includes also an evaluation board AD9625‐2.0EBZ [15] shown in **Figure 3** with a pipeline ADC.

The analog‐to‐digital converter (ADC) used is an AD9625 [16], a 12‐bit monolithic sampling ADC that operates at conversion rates of up to 2.0 GSPS, with 3.48 W power dissipation.

**Figure 1.** Channel setup.

**Figure 2.** Xilinx ML605 Evaluation Board.

introducing a sensible bias in the impact parameter assumption, particularly for short impact parameters and small drift cell [4]. Recently, it has been proposed an alternative track recon‐ struction (cluster counting/timing) technique, which consists in measuring the arrival times on the wires of each individual ionization cluster and combining these times to get a bias‐free estimate of the impact parameter [5, 6]. Typical time separations between consecutive ioniza‐ tion acts, in a helium‐based gas mixture, range from a few ns, at small impact parameters, to a few tens of ns, at large impact parameters [7, 8]. Therefore, in order to efficiently applying the cluster timing technique, it is necessary to have readout interfaces [9, 10] capable of processing high speed signals, in which one can easily isolate pulses due to different ionization cluster.

The wire signals generated by the drift chamber, before being processed, are converted from analog to digital with the use of an analog‐to‐digital converter (ADC). Requirements on drift chamber performance impose the conversions at sampling frequencies of at least 1 GS/s with at least 8‐bit resolution. These constraints, together with the maximum drift times, usually of the order of 1 microsecond, and with the large number of acquisition channels, typically of the order of tens of thousands, mandate some sizeable data reduction, which, however, must preserve all the relevant information. Identifying both the amplitude and the arrival time of each peak associated with each individual ionization cluster is the minimum requirement on

This chapter deals with the possibility of using FPGAs for the real‐time analysis of the data

More specifically, a fast readout algorithm (CluTim [12]) for identifying, in the digitized drift chamber signals, the individual ionization pulse peaks and recording their time and ampli‐ tude has been developed as VHDL/Verilog code implemented on a Xilinx ML605 Evaluation

In particular, the used device is a Virtex‐6 XC6VLX240T‐1 FFG1156 [14] that allows for a maxi‐ mum input/output clock switching frequency of 710 MHz. The hardware setup includes also

The analog‐to‐digital converter (ADC) used is an AD9625 [16], a 12‐bit monolithic sampling ADC that operates at conversion rates of up to 2.0 GSPS, with 3.48 W power dissipation.

generated by a drift chamber [11] and successively converted by an ADC (**Figure 1**).

an evaluation board AD9625‐2.0EBZ [15] shown in **Figure 3** with a pipeline ADC.

board [13] shown in **Figure 2**, making use of a Virtex 6 FPGA.

**1.1. Hardware**

160 Field - Programmable Gate Array

the data transfer for storage [5, 6].

**Figure 1.** Channel setup.

This product is designed for sampling wide bandwidth analog signals up to the second Nyquist zone. The combination of wide input bandwidth, high sampling rate, and excellent linearity of the AD9625 is ideally suited for data acquisition systems, and for the purpose of the experiment.

The analog input clock signals are differential. The standard output used is JESD204B‐based high speed serialized output [17] that is configurable in a variety of one‐, two‐, four‐, six‐, or eight‐lane configurations.

The ADC configuration (sampling frequency, number output lines, power control, etc.) is set with three single‐ended lines (clock, date, and enable) that configure the internal register of an SPI. The signals on these lines are managed from the VIRTEX, where a VHDL script gen‐ erating the bits stream to configure the SPI register, the enable signal and the clock is imple‐ mented, and sent to the ADC.

The AD9625 digital output complies with the JEDEC Standard No. JESD204B, serial interface for data converters.

JESD204B is a protocol linking the AD9625 to a digital processing device over a serial inter‐ face up to link speeds in excess of 6.5 Gbps. The benefits of the JESD204B interface over LVDS include a reduction in the required board area for data interface routing and enabling smaller packages for converters and logic devices.

The JESD204B data transmit block assembles the parallel data from the ADC into frames and uses 8‐bit/10‐bit encoding as well as optional scrambling to form serial output data. Lane

**Figure 3.** AD9625‐2.0EBZ Evaluation Board.

 synchronization is supported using special characters during the initial establishment of the link. Additional data that are used to maintain synchronization are embedded in the data stream thereafter. A JESD204B receiver (the FPGA) is required to complete the serial link.

The AD9625 JESD204B transmits block maps to two digital down converters for the outputs of the ADC over a link.

A link can be configured to use up to eight JESD204B lanes. The JESD204B specification refers to a number of parameters to define the link, and these parameters must match between the JESD204B transmitter and receiver.

The JESD204B protocol stack consists of seven functional blocks in the transmit path and seven functional blocks in the receive path, as shown in **Figure 4**.

Xilinx offers a complete working solution that simplifies the adoption of JESD204B [17], includ‐ ing best‐in‐class serial transceivers, IP, design tools, reference designs, and ecosystem partners.


**Figure 4.** JESD204B protocol.

**Figure 3.** AD9625‐2.0EBZ Evaluation Board.

162 Field - Programmable Gate Array

The two evaluation boards are connected by a high‐speed VITA 57 Mezzanine Connector in order to limit parasitic effects due to pin couplings.

The FPGA Mezzanine Card (FMC) standard has proven to be highly popular with over 100 total FMC cards now available from a variety of partners. Over 30 of these FMCs specifi‐ cally support high‐speed data converters. The FMC provides a way for customers to quickly configure their standard Xilinx development boards with real‐world analog interfaces.

Xilinx partners have been providing many easy‐to‐use (and to re‐use) reference designs that save customers weeks or even months of development time. Building on this success are the first high‐speed analog FMC cards supporting JESD204B from industry‐leading analog pro‐ viders such as analog devices, IDT, 4DSP, NXP, and others.

## **1.2. Software**

The Xilinx ISE 14.5 software has been used to design, develop, and test the CluTim algorithm. It allows for the analysis and synthesis of source code written in a hardware description lan‐ guage (HDL) such as Verilog and VHDL, provides designs, and is also able:


The real data can be stored and visualized using the Chip Scope PRO software. It inserts logic analyzer, system analyzer, and virtual I/O low‐profile software cores directly into design, allowing them to view any internal signal or node, including embedded hard or soft proces‐ sors. Signals are captured in the system at the speed of operation and brought out through the programming interface, freeing up pins for the design. Captured signals are then displayed and analyzed using the ChipScope Pro analyzer tool. These signals can be also saved to be processed with other tools, i.e., MATLAB.
