**4. Experimental results of the modulation technique**

#### **4.1. Test chip description**

The results obtained are analogous to those of **Figure 8**. However, the values of *χ*p and *χ*<sup>n</sup> at 0.8 V are lower than at 1.2 V (note that the graphs in **Figures 8** and **9** are represented at the same scale). This means that reducing the supply voltage not only reduces the critical charge but also reduces the efficiency in terms of critical charge to make wider pMOS transistors.

Finally, **Figure 10** plots *χ*p as a function of the pulse width and supply voltage in a surface plot

The graph in **Figure 10** shows that reducing both the supply voltage and the pulse width decreases the efficiency, in terms of critical charge, of modulating the pMOS transistors channel

From all the results presented in this section, it can be deduced that if the SEU robustness of an SRAM cell is to be increased in a certain percentage, increasing the widths of only the pMOS and leaving the nMOS unmodified is more efficient than any other combination of transistor width modulation. Or, for a given percentage area budget, increasing only pMOS widths

**Table 1.** Critical charge and cell area increment for three different values of *r*p, and *r***n = 1 (***W*min = 0.15 μm). The supply

**Area increment with respect to minimum cell (%)**

**with respect to minimum cell (%)**

1.0 0.15 1.72 0 0 1.5 0.23 2.14 24 9 2.0 0.30 2.51 46 17

and as a family of curves generated by the supply voltage parameter.

**Figure 10.** Dependence of *χ*p,e with pulse width and supply voltage.

*r***<sup>p</sup>** *W***p (µm)** *Q***crit,e (fC)** *Q***crit,e increment**

width.

maximizes critical charge.

208 Field - Programmable Gate Array

voltage is nominal.

The transistor width modulation technique was implemented in a custom fabricated SRAM test chip in a 65‐nm CMOS commercial technology. Memory cells are six‐transistor (6T) cells and were implemented following regular layout design specifications to minimize parameter variations. The regular layout characteristics were described in Section 3, and include the use of straight diffusion regions and regular alignment of word line polysilicon lines.

**Figure 11.** Schematic representation of the five cell types implemented in the test chip.

From all the previously simulated cells, five of them were implemented in the test chip (five different combinations of transistors channel widths). All these combinations satisfy the restrictions imposed for a regular layout. The selected combinations (cell types) of *r*n and *r*p are schematized in **Figure 11** and detailed in **Table 2**. For each one of the five cell types, a total of


4096 cells were implemented. Finally, the test chip was irradiated following the procedure detailed in Section 4.2 to experimentally test the modulation technique.

**Table 2.** Main geometric features of the five cell types implemented in the test chip.

#### **4.2. Experimental irradiation procedure**

The objective of the experiment is to obtain the soft error rate (SER) of each one of the five cell types, that is, the number of soft errors (SEUs) for time unit.

The 65‐nm CMOS test chip was mounted on a specifically designed PCB and controlled by an FPGA to drive and capture data.

As a radiation source, it was used an Am‐241 alpha source with a 5 kBq activity providing alpha particles of 5.5 MeV. The source active area was 7 mm in diameter and was placed atop the unencapsulated chip, and all five cell types were irradiated at the same time. The control FPGA was not irradiated because the objective of the experiment was only to study the behavior of the test chip SRAM cells under radiation conditions.

The test procedure was performed following the subsequent steps:


Steps 4–5 were cycled until the experiment was finished. The overall number of SEUs, *N*TOT, is given by the addition of the number of SEUs recorded at each sampling period (*Ni* ), i.e.

$$N\_{\text{torr}} = \sum\_{i=1}^{n} N\_i \tag{4}$$

with *n* being the number of times that the memory is read. The overall time experiment (*t*exp) is given by exp <sup>=</sup> s . The SER at each sampling time period (SER*<sup>i</sup>* ) is given by SER <sup>=</sup> /s , while the mean SER of the overall experiment is given by

$$\text{SER} = \frac{\sum\_{i=1}^{n} \text{SER}\_i}{n} = \frac{\sum\_{i=1}^{n} N\_i}{n \cdot T\_s} = \frac{N\_{\text{TOT}}}{t\_{\text{exp}}} \tag{5}$$

The determination of the sampling period *T*s is important, since it must guarantee that the probability of a given cell to experience two or more flips within the same sampling period is negligible, while keeping the overall read time small with respect to the overall hold time (we are interested in computing the memory SER when the memory is not being accessed) [16]. We ran an initial experiment using a small one‐minute *T*<sup>s</sup> value and determined an SER order of magnitude of 1 SEU/minute. Based on this, we set a *T*<sup>s</sup> value of 30 min to not increase the memory read rate. The mean estimated SEU error using this *T*s value is 1‰.

#### **4.3. Experimental results**

4096 cells were implemented. Finally, the test chip was irradiated following the procedure

The objective of the experiment is to obtain the soft error rate (SER) of each one of the five cell

The 65‐nm CMOS test chip was mounted on a specifically designed PCB and controlled by an

As a radiation source, it was used an Am‐241 alpha source with a 5 kBq activity providing alpha particles of 5.5 MeV. The source active area was 7 mm in diameter and was placed atop the unencapsulated chip, and all five cell types were irradiated at the same time. The control FPGA was not irradiated because the objective of the experiment was only to study the

**5.** Read the whole memory and determine the number of cells whose state changed. Go to

Steps 4–5 were cycled until the experiment was finished. The overall number of SEUs, *N*TOT, is

*i=1 <sup>i</sup> N N* (4)

given by the addition of the number of SEUs recorded at each sampling period (*Ni*

TOT <sup>=</sup>å*<sup>n</sup>*

**Cell width (µm)**

**Cell area (µm2 )**

**Cell area increment with respect to A (%)**

), i.e.

**Cell height (µm)**

detailed in Section 4.2 to experimentally test the modulation technique.

**A** 0.15 0.15 0.58 1.75 1.01 0 **B** 0.23 0.15 0.58 1.91 1.10 9 **C** 0.30 0.15 0.58 2.05 1.18 17 **D** 0.23 0.23 0.58 2.07 1.19 18 **E** 0.15 0.30 0.58 2.05 1.18 17

**nMOS width,**  *W***n (µm)**

**Table 2.** Main geometric features of the five cell types implemented in the test chip.

types, that is, the number of soft errors (SEUs) for time unit.

behavior of the test chip SRAM cells under radiation conditions.

**2.** Read all memory cells, and compare to the written values.

**1.** Write all memory cells to a known value.

**3.** Initiate the memory radiation.

**4.** Wait for a sampling time *T*s.

Step 4.

The test procedure was performed following the subsequent steps:

**4.2. Experimental irradiation procedure**

FPGA to drive and capture data.

**Cell type pMOS width,**  *W***p (µm)**

210 Field - Programmable Gate Array

The experiment was conducted under the conditions and procedure described in Section 4.2 for a total time of 72 h to accumulate enough SEUs as to obtain a reliable SER result.

The SEU count evolution is shown in **Figure 12**. As expected, results show that the accumulated SEU count with time is linear. An alternative way to calculate SER is by obtaining the slope of the plot of accumulated number of SEU as a function of time.

**Figure 12.** Accumulated SEUs in a 72 h period irradiation for the five cell types.

The first important result from **Figure 12** is that different memory cell types have different SER values (i.e., different slopes). If each SER is computed and represented in a bar plot, **Figure 13** is obtained.

**Figure 13.** SER of 4096 cells for each one of the five cell types.

In addition, SER values are tabulated in **Table 3** along with critical charge results. Keep in mind that a more robust cell means more critical charge but less SER.


**Table 3.** SER and critical charge values for the five different cell types (sorted by SER value).

From **Figure 13** and **Table 3**, it is observed that the stronger cell—from a SER point of view is the C, followed by B, and that the less robust is E. In addition, if critical charge is also taken into account, the following can be observed:


In short, increasing the pMOS transistors channel width improves critical charge and SER. However, increasing the nMOS transistors channel width improves critical charge, but worsens SER. The reason for this nonsymmetrical behavior must be sought in the fact that increasing critical charge by widening the channel of the transistors has a dual effect on SER:


The key point is that the relative contribution of these two factors (critical charge and area increase) is not the same in the case of widening nMOS and pMOS transistors. Increasing the channel size of pMOS implies an area increase inside the well, while increasing the channel size of nMOS increases the area directly on the substrate. The different ability to collect charge of pMOS (in the well) or nMOS (on the substrate) is the qualitative explanation of the observed relation between SER and critical charge for nMOS and pMOS width modulation. This behavior is quantitatively explained in the following section.
