**3. FPGA PCIe integration into the real‐time Linux system**

The evaluation of the SHWFS is only one part of the AO system since the partial derivatives of the wavefront must be either used for reconstruction of the wavefront and/or used for controlling a deformable mirror (DM) in closed‐loop operation. A simple, basic AO concept is used for the work presented in this text, see **Figure 11**. In the experimental setup, the FPGA, besides the evaluation of the SHWFS, is also used for interfacing the digital‐to‐analog converter (DAC) card. The benefit is that the FPGA can easily guarantee a true parallel output (same guaranteed phase) for all analog outputs even if multiple DACs have to be used.

**Figure 11.** Overview over the basic AO concept; for the detailed concept see [21].

The subsequent processing of the SHWFS data is carried out by a performance computer using state‐of‐the‐art hardware. On this performance computer, the control algorithm is running on a hard real‐time Linux operating system (OS). This OS in combination with the performance computer offers rapid‐control prototyping (RCP) capabilities in view of the direct MATLAB/ Simulink interface. Such an RCP system reduces the implementation effort drastically when different control schemes and approaches need to be tested or compared with each other.

The PCIe FPGA card, see **Figure 12**, is a self‐developed card based on the Xilinx Kintex‐7 FPGA module TE0741 from Trenz Electronics. The PCIe FPGA card offers more connectivity than only the CameraLink interface. Nevertheless, in this context, only CameraLink, PCIe, and the Serial Peripheral Interface (SPI) are used. The other interfaces are neglected in this context but are presented in detail in Refs. [9, 21].

which corresponds to 1111 ms. Thus, the proposed method has a delay equal or less than one

The evaluation of the SHWFS is only one part of the AO system since the partial derivatives of the wavefront must be either used for reconstruction of the wavefront and/or used for controlling a deformable mirror (DM) in closed‐loop operation. A simple, basic AO concept is used for the work presented in this text, see **Figure 11**. In the experimental setup, the FPGA, besides the evaluation of the SHWFS, is also used for interfacing the digital‐to‐analog converter (DAC) card. The benefit is that the FPGA can easily guarantee a true parallel output (same

The subsequent processing of the SHWFS data is carried out by a performance computer using state‐of‐the‐art hardware. On this performance computer, the control algorithm is running on a hard real‐time Linux operating system (OS). This OS in combination with the performance computer offers rapid‐control prototyping (RCP) capabilities in view of the direct MATLAB/ Simulink interface. Such an RCP system reduces the implementation effort drastically when different control schemes and approaches need to be tested or compared with each other.

The PCIe FPGA card, see **Figure 12**, is a self‐developed card based on the Xilinx Kintex‐7 FPGA module TE0741 from Trenz Electronics. The PCIe FPGA card offers more connectivity than only the CameraLink interface. Nevertheless, in this context, only CameraLink, PCIe, and the Serial Peripheral Interface (SPI) are used. The other interfaces are neglected in this context but

**3. FPGA PCIe integration into the real‐time Linux system**

guaranteed phase) for all analog outputs even if multiple DACs have to be used.

**Figure 11.** Overview over the basic AO concept; for the detailed concept see [21].

are presented in detail in Refs. [9, 21].

single frame.

186 Field - Programmable Gate Array

**Figure 12.** Developed PCIe FPGA board based on a TE0741 (Xilinx Kintex‐7) module from Trenz Electronics.

The integration of the FPGA card is realized via the PCIe interface. Thus, almost any modern computer can be used for interfacing the PCIe FPGA card. The SHWFS, more exactly the CCD camera, is connected with the CameraLink interface to the card. Additionally, two separate DAC boards are installed where each DAC board offers 32 analog channels.

The outputs of the DAC cards are fed into an amplifier which amplifies the small signals to drive, for example, the piezoelectric actuators that are part of the DM. In the setup, two DMs have been applied. This circumstance allows the feature that one DM may be used for an artificial, but realistic disturbance generation, whereas the other compensates for such disturbance. In principle, the disturbance may also be virtually induced by adding some signal to the output of the SHWFS; however, a meaningful emulation can be rather involved. This may limit the performance of the system. For this reason, a real disturbance has been incor‐ porated. The amplifier offers the feature to switch between regular and symmetric voltage by modifying the reference ground. Here, the benefit of the symmetric voltage is that the stroke is symmetric as well. Due to the creeping behavior of the piezoelectric actuators, simply applying an offset of [+150] V is not the same as symmetric operation.

For integrating the PCIe FPGA card into the Linux kernel, a kernel driver has to be developed. So as to integrate data acquisition cards, Linux offers a special interface called comedi (control and measurement device interface). Using this interface is very comfortable because the core functionality is already implemented and only low‐level driver modules have to be developed for supporting a new data acquisition card. In addition, a user‐space library called "comedilib" is available which allows the utilization of user‐space to access the functionality of the data acquisition card (**Figure 14**).

**Figure 13.** RTAI principle for RTAI‐core active or inactive [21].


**Figure 14.** Block diagram of the different abstraction layers used in RTAI/LXRT [9].

The Linux kernel is patched with the RTAI (real‐time application interface) [22] patch which itself is based on Adeos. The purpose of the Adeos project is to offer an environment so as to allow sharing of hardware resources among multiple operating systems. RTAI uses that approach (shown in **Figure 13**) for scheduling Linux in the hard real‐time support. If RTAI is loaded then case B is active, otherwise case A.

Furthermore, RTAI supports comedi without disturbing the hard real‐time behavior. RTAI has the LXRT extension that offers the feature to run real‐time applications as user‐space pro‐ grams, see **Figure 14**. Additionally, a MATLAB/Simulink target is available which uses the Simulink Coder for C/C++ code generation [23]. Based on these prerequisites it is easy to extend the given code generation to support more comedi implemented features such as block memory reads or trigger commands.

The PCIe implementation is based on the Xilinx 7 Series Gen2 Integrated Block for PCI Express IP‐core which has been extended to support Direct Memory Access (DMA). This way, the FPGA may write the assigned centroids into the main memory of the computer without involving the CPU, see **Figure 15**. PCIe is based on sending and receiving Transaction Layer Packets (TLPs). The block "COMEDI\_SHWFS\_READ," see **Figure 16**, performs a blocking read request on the memory destination also being used for the DMA transfer. Behind these Simulink blocks, we have predefined *s*‐functions which are based on the functionality provided by comedi. The "COMEDI\_SHWFS\_TRIGGER" triggers the start of the frame capture; thus, the image acquisition is synchronous to the real‐time application which is essential for guaran‐ teeing a deterministic behavior. As shown in the timeline in **Figure 10**, after approximately 1050 µs the data is transferred via DMA to the main memory of the computer.

**Figure 15.** Communication using PCIe interface between FPGA and computer.

**Figure 13.** RTAI principle for RTAI‐core active or inactive [21].

188 Field - Programmable Gate Array

**Figure 14.** Block diagram of the different abstraction layers used in RTAI/LXRT [9].

loaded then case B is active, otherwise case A.

memory reads or trigger commands.

The Linux kernel is patched with the RTAI (real‐time application interface) [22] patch which itself is based on Adeos. The purpose of the Adeos project is to offer an environment so as to allow sharing of hardware resources among multiple operating systems. RTAI uses that approach (shown in **Figure 13**) for scheduling Linux in the hard real‐time support. If RTAI is

Furthermore, RTAI supports comedi without disturbing the hard real‐time behavior. RTAI has the LXRT extension that offers the feature to run real‐time applications as user‐space pro‐ grams, see **Figure 14**. Additionally, a MATLAB/Simulink target is available which uses the Simulink Coder for C/C++ code generation [23]. Based on these prerequisites it is easy to extend the given code generation to support more comedi implemented features such as block

The PCIe implementation is based on the Xilinx 7 Series Gen2 Integrated Block for PCI Express IP‐core which has been extended to support Direct Memory Access (DMA). This way, the FPGA may write the assigned centroids into the main memory of the computer without involving the CPU, see **Figure 15**. PCIe is based on sending and receiving Transaction Layer Packets

**Figure 16.** Simulink model used for code‐generation and based on Simulink Coder.

The captured data, e.g., from the SHWFS as well as the control output and error values are fed into the "RTAI\_LOG" block. This module creates an interface with which another user‐space program may record the data and write it either to the main memory or the hard disk.
