**4.4. Analysis of the results**

The first important result from **Figure 12** is that different memory cell types have different SER values (i.e., different slopes). If each SER is computed and represented in a bar plot, **Figure 13**

In addition, SER values are tabulated in **Table 3** along with critical charge results. Keep in mind

From **Figure 13** and **Table 3**, it is observed that the stronger cell—from a SER point of view is the C, followed by B, and that the less robust is E. In addition, if critical charge is also taken

**•** The best cell is C; note that this occurs from both critical charge and SER points of view. **•** Increasing the pMOS transistors channel widths (cells A, B, and C) causes an increase in critical charge, which directly results into a decrease in SER. That is, cell C is more robust than B, and B more robust than A, from both from critical charge and SER point of view.

is obtained.

212 Field - Programmable Gate Array

**Figure 13.** SER of 4096 cells for each one of the five cell types.

into account, the following can be observed:

that a more robust cell means more critical charge but less SER.

**Cell type SER (s−1 × 10−3)** *Q***crit,e (fC) C** 3.87 2.51 **B** 4.60 2.14 **D** 5.24 2.44 **A** 5.68 1.72 **E** 8.30 2.26

**Table 3.** SER and critical charge values for the five different cell types (sorted by SER value).

Experimental data show that maintaining minimum nMOS transistors width (*r*n = 1) while increasing pMOS transistor channel widths improves both critical charge and SER for a 6T memory cell. However, increasing nMOS transistor channel width improves memory cell critical charge, but worsens SER. As it has been mentioned before, this can be qualitatively explained as follows: Increasing transistor width has two competing effects on SER. On the one hand, SEUs are more difficult to occur, because *Q*crit is raised due to the increase of both the drain capacity and the transistor width, which enhances transistor strength. On the other hand, widening a transistor increases its sensitive area, raising the probability of the cell to collect charge and thus be flipped by the effect of an energetic particle. The relative contribution of these two opposite effects on SER depends on the transistor type (nMOS or pMOS), especially for CMOS bulk technologies with well areas for pMOS transistors [17].

To model these two effects, it is necessary to use an expression that relates SER and critical charge. The following expression [18] will be used:

$$\text{SER} = \kappa \left( A\_{\text{diff},u} \cdot e^{\frac{-Q\_{\text{att},s}}{\eta\_u}} + A\_{\text{diff},p} \cdot e^{\frac{-Q\_{\text{att},s}}{\eta\_u}} \right) \tag{6}$$

where *A*diff,n and *A*diff,p are the nMOS and pMOS sensitive drain area. *Q*crit,e and *Q*crit,h are respectively the critical charges due to the collection of electrons and holes, and *κ* is a parameter that depends on the radiation flux. Parameters *η*e and *η*h represent electron and hole charge collection efficiency. To compute SER, parameters *κ*, *η*e, and *η*h need to be experimentally obtained, as they depend on the environment and on the device precise characteristics. Note that the model includes both critical charges (*Q*crit,e and *Q*crit,h) introduced in Section 3.1.

**Figure 14.** SER (experimental and modeled) of 4096 cells for each one of the five cell types.

In our case, since we obtained SER and critical charge for different cell types, we can fit SER experimental data to the calculated critical charge values and obtain the unknown parameters *<sup>κ</sup>*, *η*e, and *η*h. Diffusion areas can be expressed as diff,n = · n, and diff,p = p · <sup>p</sup>, being *H*n and *H*p the diffusion lengths of the drains of the nMOS and pMOS transistors. The design rules restrictions for symmetrical and regular cell layout impose *H*n to be slightly longer than *H*p (in fact we used the minimum possible diffusion length in the pMOS transistor, p = min, while n = diff · min with *K*diff = 1.1 for the five different cells). Introducing again *r*n and *r*p coefficients defined in Eq. (2) we obtain:

$$\begin{aligned} A\_{\text{diff},n} &= r\_{\text{n}} \cdot W\_{\text{min}} \cdot K\_{\text{diff}} \cdot H\_{\text{min}} = r\_{\text{n}} \cdot K\_{\text{diff}} \cdot A\_{\text{min,diff}}\\ A\_{\text{diff,p}} &= r\_{\text{p}} \cdot W\_{\text{min}} \cdot H\_{\text{min}} = r\_{\text{p}} \cdot A\_{\text{min,diff}} \end{aligned} \tag{7}$$

where min, diff = min · min. Therefore, Eq. (7) becomes:

$$SER = \overbrace{\kappa \cdot A\_{m\ln, altff}}^{K\_A} \left( K\_{dfff} \cdot r\_n \cdot e^{-\frac{Q\_{crit, e}}{\eta\_\varepsilon}} + r\_p \cdot e^{-\frac{Q\_{crit, h}}{\eta\_h}} \right) \tag{8}$$

The values of *SER*, *Q*crit,e, *Q*crit,h, *r*n, *r*p, and *K*diff in Eq. (8) are known and, therefore, *K*A, *η*e and *η*<sup>h</sup> remain as fitting parameters, being *K*A the product of *κ* and *A*min, diff. The obtained values after the fitting for these parameters are: *K*A = 3.13 × 10−6 s−1, *η*e = 2.02 fC, and *η*h = 0.79 fC.

**Figure 14** compares the experimental and fitted SER. As it can be seen, Eq. (8) accurately describes the experimental SER as a function of critical charge and geometrical parameters. In addition, the model properly describes quantitatively the asymmetrical influence of nMOS and pMOS transistor width in terms of SER, which was previously interpreted qualitatively.

The experimentally fitted parameters and the resulting critical charge values from Eq. (8) allow to plot SER as a function of *r*n and *r*p. The resulting surface is shown in **Figure 15**.

**Figure 15.** SER as a function of *r*n and *r*p.

crit ,e crit ,h

*n p κA e A e* (6)

*Q Q η η*


where *A*diff,n and *A*diff,p are the nMOS and pMOS sensitive drain area. *Q*crit,e and *Q*crit,h are respectively the critical charges due to the collection of electrons and holes, and *κ* is a parameter that depends on the radiation flux. Parameters *η*e and *η*h represent electron and hole charge collection efficiency. To compute SER, parameters *κ*, *η*e, and *η*h need to be experimentally obtained, as they depend on the environment and on the device precise characteristics. Note that the model includes both critical charges (*Q*crit,e and *Q*crit,h) introduced in Section 3.1.

<sup>e</sup> <sup>h</sup> SER · diff , diff , ·

**Figure 14.** SER (experimental and modeled) of 4096 cells for each one of the five cell types.

*<sup>κ</sup>*, *η*e, and *η*h. Diffusion areas can be expressed as diff,n = ·

again *r*n and *r*p coefficients defined in Eq. (2) we obtain:

where min, diff = min · min. Therefore, Eq. (7) becomes:

 p

214 Field - Programmable Gate Array

In our case, since we obtained SER and critical charge for different cell types, we can fit SER experimental data to the calculated critical charge values and obtain the unknown parameters

*H*n and *H*p the diffusion lengths of the drains of the nMOS and pMOS transistors. The design rules restrictions for symmetrical and regular cell layout impose *H*n to be slightly longer than *H*p (in fact we used the minimum possible diffusion length in the pMOS transistor,

= min, while n = diff · min with *K*diff = 1.1 for the five different cells). Introducing

*A rW H r A* (7)

diff ,n n min diff min n diff min,diff diff ,p p min min p min,diff ··· ·· ·· ·

= = = = *A rW K H rK A* n, and diff,p = p ·

<sup>p</sup>, being

Results of **Figure 15** confirm that increasing *r*<sup>p</sup> leads to a SER reduction, whereas increasing *r*<sup>n</sup> produces an undesired SER increment. This SER surface can be compared to the critical charge surface of **Figure 6**, where critical charge was improved as both *r*n and *r*p were increased.

If the charge collection efficiency values obtained as fitting parameters are analyzed, it is confirmed that charge collection efficiency for electrons (*η*e) is higher than for holes (*η*h) [19]. In addition, critical charge for electrons (*Q*crit,e) is smaller than for holes (*Q*crit,h). This electron and hole asymmetry in terms of charge collection efficiency and in terms of critical charge is the root cause of the observed differences of SER dependency with *r*n and *r*p.

Usual 6T‐cells are designed with minimum sized access transistors (acc <sup>=</sup> min), minimum sized pMOS (p <sup>=</sup> min), and non‐minimum‐sized nMOS (n = CR · min). The CR parameter is called cell ratio and is usually greater than 1, being the most frequent values between 1.5 and 2.5 as a trade‐off to assure cell stability during write and read operations [3]. Note that this cell with this transistor dimensions does not have straight diffusions. In addition, also note that this cell has the internal latch (cross coupled inverters) equal to the ones in E cell.

From the irradiation experiments, it has been obtained that the C cell shows an SER that is a 46% of the E cell SER, that is, C cell receives less than half the number of SEUs per time unit than E cell. Note that this improvement is achieved only by adequate transistor sizing, because both cells (C and E) have the same area. If instead of considering this two cells, we compare the C cell with respect to a usual cell with CR = 2, then the SER of the C cell is a 57% the SER of the CR = 2 cell.

The effects of the transistor width modulation technique on power consumption and access time are summarized in **Table 4**. For example, it can be observed that C and E cells show similar access times and power consumption levels (although there is an increase of the energy needed to change the logic state of the C cell, it presents lower leakage current than the E cell).


**Table 4.** Summary of different power, speed and stability figures of the fife different cell types.

Finally, it was also analyzed how the modulation technique affects read and write stability, by computing two well‐known parameters: read static noise margin (RSNM) and write static noise margin (WSNM). As it can be seen in **Table 4**, RSNM is not very affected. Despite that, in [20], a technique to recover the RSNM of a 6T cell is analyzed. In addition, WSNM is degraded in some cell types (the ones in which pMOS transistors are increased in size). To overcome that, if needed, there are write assist techniques that could be suitable to improve WSNM [21, 22]. However, all tested cells types are experimentally writable with no write assist technique applied.
