**3. SRAM cell transistors channel width modulation technique**

Memories are usually structures in which the maximum density of integration is requested. Therefore, the transistors forming memory cells are usually close to the minimum dimensions enabled by technology. Nevertheless, this section describes how it is possible to achieve more robust SRAM cells by varying the channel width of some of the cell transistors. This technique has a clear impact on the area occupied by each cell and, therefore, in the total memory area. For this reason, we will study how to use the area increase in the most efficient way, that is, how to get some gain in critical charge with minimum additional area. Moreover, the impact of this technique in terms of power consumption, stability, and access time is characterized in Section. 4.4.

Designing SRAMs is a challenge as technology scales down mainly due to parameter varia‐ tions. There are two main causes of mismatch between the cell cross‐coupled inverters: polysilicon and diffusion critical dimensions, as well as implant variations [12]. The use of subwavelength lithography and reactive ion etching are two of the main causes that converts the drawn polygon corners on the layout mask into rounded shapes on the manufactured circuits. Although proper optical proximity corrections can minimize those distortions, these techniques alone cannot compensate all the distortions, especially as the lithography gap is increasing with each successive technology node [12]. As a result, traditional cell designs are very sensitive to misalignment because they include transistor diffusion width changes. These changes in width produce bends and steps in the diffusion regions, which in turn, cause small variations of the poly placement that lead to significant poly‐diffusion overlay misalignment. This variability impacts directly on transistor matching, which can compromise cell stability and functionality.

The so‐called regular cell layouts (**Figure 4**) have shown to be more tolerant to parameter variations due to several factors: all poly lines are drawn in the same direction, poly lines are aligned facilitating better polysilicon critical dimension control, and helping phase shift masking techniques [13]. In addition, when a cell is inside the SRAM array, all transistors see the same polysilicon patterns, thus minimizing poly proximity issues [12]. Finally, regular cells have straight diffusions and, therefore, are much less sensitive to misalignments [14, 15].

**Figure 4.** 6‐T SRAM regular layout.

**Figure 3.** 6T‐SRAM cell schematics for simulating a 1 to 0 SEU (left) and a 0 to 1 SEU (right).

**3. SRAM cell transistors channel width modulation technique**

Memories are usually structures in which the maximum density of integration is requested. Therefore, the transistors forming memory cells are usually close to the minimum dimensions enabled by technology. Nevertheless, this section describes how it is possible to achieve more robust SRAM cells by varying the channel width of some of the cell transistors. This technique has a clear impact on the area occupied by each cell and, therefore, in the total memory area. For this reason, we will study how to use the area increase in the most efficient way, that is, how to get some gain in critical charge with minimum additional area. Moreover, the impact of this technique in terms of power consumption, stability, and access time is characterized in

Designing SRAMs is a challenge as technology scales down mainly due to parameter varia‐ tions. There are two main causes of mismatch between the cell cross‐coupled inverters: polysilicon and diffusion critical dimensions, as well as implant variations [12]. The use of subwavelength lithography and reactive ion etching are two of the main causes that converts the drawn polygon corners on the layout mask into rounded shapes on the manufactured circuits. Although proper optical proximity corrections can minimize those distortions, these techniques alone cannot compensate all the distortions, especially as the lithography gap is

power consumption and long‐term reliability.

202 Field - Programmable Gate Array

Section. 4.4.

This chapter deals only with 6T SRAM cells, although there are other SRAM which are specially designed to deal with radiation issues. In general, they are hardened SRAM cells that maintain their stored data even if the electrical state of some of their nodes is flipped by a particle strike, some of them are described in [10, 11]. The main drawbacks of them are the increase in cell transistor count with the consequent area increase. In addition, in these cells, it is difficult to implement regular cell layouts, which, as it will be described in Section 3, is a useful method for parameter variation minimization. Furthermore, nonstandard cells complicate the possi‐ bility to include them in current SRAM and FPGA design flows. Conversely, the technique that will be described in Section 3 is fully compatible with SRAM memory compilers and easily adaptable to current FPGA designs. Other mitigation techniques, such as supply voltage increase [9], are not suitable to be implemented in many applications due to their impact on

> Parameter variation has become a key factor in SRAM memory design. For this reason, the regular layout is the one that is considered in this chapter. Using regular layouts imposes geometrical restrictions, for example, as previously mentioned, it is necessary to orientate all polysilicon lines in the same direction and keep them aligned. However, the determining factor that mainly affects the transistor channel width modulation technique is the impossibility to introduce steps and bends in the diffusion areas. This means that the designer will be unable to freely change SRAM transistors channel widths.

> The formation of bends in the diffusion regions of a cell, like the one considered in **Figure 4**, can be avoided if all nMOS transistors channel width (*W*n) is the same, as well as all pMOS transistors channel width (*W*p) is also the same. In **Figure 4**, it can be seen that this way the diffusion areas (colored in green) remain straight. If we consider as a reference a cell where channel width of all transistors is the minimum (*W*min), the restriction is expressed as

$$\begin{aligned} W\_n &= r\_n \cdot W\_{\text{min}} \\ W\_p &= r\_p \cdot W\_{\text{min}} \end{aligned} \tag{2}$$

With these two restrictions, the nMOS channel width can vary independently from the pMOS channel width. This implies that the designer has two degrees of freedom.

#### **3.1. Critical charge results**

As it was mentioned before, the behavior of the cell undergoing a current injection due to an energetic particle impact depends on the duration of the pulse (pulse width); for this reason, it is interesting to use it as a parameter to explore.

Pulse widths of current transients are highly variable and depend on multiple parameters, but several studies show that they are between a few picoseconds and hundreds of picoseconds [6]. 3D simulations also show that short pulses correspond to ionization events whose track crosses the drain of a cut‐off transistor, while long ones are the result of events whose track does not pass through the drain [9]. It is necessary to consider both cases, since the location of the trace ionization with respect to drain is a random parameter. For this reason, to characterize the behavior of the cell, simulations with pulse widths ranging between 20 and 200 ps have been performed.

In addition, there are two different critical charges depending on which node (the one at 0 or the one at 1) receives the collected charge modeled by the current injection. The collection of electrons by the drain junction of an nMOS in OFF state results in a current pulse that upsets the affected node from 1 to 0, so this critical charge is named *Q*crit,e. Similarly, the collection of holes by a pMOS drain junction upsets the affected node from 0 to 1, so this critical charge is called *Q*crit,h. If both critical charges are represented as a function of pulse width, **Figure 5** is obtained.

**Figure 5.** Critical charge for electrons and holes of a minimum‐sized 6T‐SRAM (*r*n = *r*p = 1) as a function of pulse width.

It can be observed that *Q*crit,e is lower than *Q*crit,h. Therefore, it is normally considered that the cell‐flip process is dominated by *Q*crit,e, and sometimes *Q*crit,h is neglected. However, accurate models need to include both critical charges, as it will be shown in Section 4.4.

n n min p p min · · = = *W r W*

channel width. This implies that the designer has two degrees of freedom.

**3.1. Critical charge results**

204 Field - Programmable Gate Array

been performed.

obtained.

it is interesting to use it as a parameter to explore.

With these two restrictions, the nMOS channel width can vary independently from the pMOS

As it was mentioned before, the behavior of the cell undergoing a current injection due to an energetic particle impact depends on the duration of the pulse (pulse width); for this reason,

Pulse widths of current transients are highly variable and depend on multiple parameters, but several studies show that they are between a few picoseconds and hundreds of picoseconds [6]. 3D simulations also show that short pulses correspond to ionization events whose track crosses the drain of a cut‐off transistor, while long ones are the result of events whose track does not pass through the drain [9]. It is necessary to consider both cases, since the location of the trace ionization with respect to drain is a random parameter. For this reason, to characterize the behavior of the cell, simulations with pulse widths ranging between 20 and 200 ps have

In addition, there are two different critical charges depending on which node (the one at 0 or the one at 1) receives the collected charge modeled by the current injection. The collection of electrons by the drain junction of an nMOS in OFF state results in a current pulse that upsets the affected node from 1 to 0, so this critical charge is named *Q*crit,e. Similarly, the collection of holes by a pMOS drain junction upsets the affected node from 0 to 1, so this critical charge is called *Q*crit,h. If both critical charges are represented as a function of pulse width, **Figure 5** is

**Figure 5.** Critical charge for electrons and holes of a minimum‐sized 6T‐SRAM (*r*n = *r*p = 1) as a function of pulse width.

*W r <sup>W</sup>* (2)

In addition, critical charges for a 6T cell for various combinations of *W*p, *W*n were calculated. **Figure 6** shows the results in a graph where the independent variables are *r*p, *r*n. Results are shown for two different pulse widths and only for *Q*crit,e, since *Q*crit,h show similar results.

**Figure 6.** Critical charge (*Q*crit,e) as a function of *r*n and *r*p and for two different pulse widths.

**Figure 6** shows how the cell is more robust as the transistors channel width is increased. However, increasing the channel width of transistors produces a clear and undesired impact on the area of each cell and, therefore, on the total memory area. For this reason, it is necessary to establish a trade‐off between the increased radiation robustness and the additional area used. Moreover, it is convenient to use the additional area in the most efficient possible way. This is discussed in the following subsection.

It has also been studied how the supply voltage affects cell robustness. **Figure 7** shows the results of critical charge for a typical alpha‐particle pulse width of 30 ps [6] as a function of *r*p, rn for two different supply voltages.

**Figure 7.** Critical charge (*Q*crit,e) as a function of *r*n and *r*p and for two different supply voltages and for a 30 ps pulse width.

As it can be observed, a decrease in the supply voltage causes a reduction in the critical charge for all combinations of transistors channel widths. This result is in line with the previously mentioned fact that a cell with reduced voltage supply uses less charge to store data and, therefore, it is easier to change its stored value.

#### **3.2. Additional area optimization to harden the SRAM cell**

Due to the almost linear behavior of the graph in **Figure 6**, the following coefficients can be defined and are virtually independent of *W*p and *W*n:

$$\chi\_{\text{p}} = \frac{\partial \underline{Q}\_{\text{crit}}}{\partial W\_{\text{p}}} \chi\_{\text{n}} = \frac{\partial \underline{Q}\_{\text{crit}}}{\partial W\_{\text{n}}} \tag{3}$$

These two coefficients represent the efficiency, in terms of critical charge, of a certain increase in the transistors channel width (pMOS in the case of *χ*p, and nMOS in the case of *χ*n).Geo‐ metrically, these coefficients represent the slopes in the two horizontal directions of the planes of **Figure 6**. These slopes vary as a function of the different pulse widths; therefore, coefficients are a function of the considered pulse width. If this dependence is plotted, **Figure 8** is obtained.

**Figure 8.** Dependence of *χ*p,e and *χ*n,e with pulse width for nominal supply voltage (1.2 V).

**Figure 7.** Critical charge (*Q*crit,e) as a function of *r*n and *r*p and for two different supply voltages and for a 30 ps pulse

As it can be observed, a decrease in the supply voltage causes a reduction in the critical charge for all combinations of transistors channel widths. This result is in line with the previously mentioned fact that a cell with reduced voltage supply uses less charge to store data and,

Due to the almost linear behavior of the graph in **Figure 6**, the following coefficients can be

crit crit

*Q Q χ χ W W* (3)

p n ¶ ¶ = = ¶ ¶

These two coefficients represent the efficiency, in terms of critical charge, of a certain increase in the transistors channel width (pMOS in the case of *χ*p, and nMOS in the case of *χ*n).Geo‐ metrically, these coefficients represent the slopes in the two horizontal directions of the planes of **Figure 6**. These slopes vary as a function of the different pulse widths; therefore, coefficients are a function of the considered pulse width. If this dependence is plotted, **Figure 8** is obtained.

p n

width.

206 Field - Programmable Gate Array

therefore, it is easier to change its stored value.

**3.2. Additional area optimization to harden the SRAM cell**

defined and are virtually independent of *W*p and *W*n:

**Figure 8** shows that, in general, *χ*p is larger than *χ*n, only for very short pulses *χ*n tends to equal or even exceed the value of *χ*p. This means that for pulses longer than about 10 ps, increasing only pMOS transistors width (*W*p) is more efficient than increasing nMOS transistors (*W*n). As it has been mentioned before, the widths of the current pulses generated by SEU vary. However, for alpha particles, a typical pulse width is about 30 ps [6]. For this typical pulse width, increasing *W*p is more efficient than increasing *W*n.

Same simulations were repeated for 0.8 V supply voltage, the results are shown in **Figure 9**.

**Figure 9.** Dependence of *χ*p,e and *χ*n,e with pulse width for 0.8 V supply voltage.

The results obtained are analogous to those of **Figure 8**. However, the values of *χ*p and *χ*<sup>n</sup> at 0.8 V are lower than at 1.2 V (note that the graphs in **Figures 8** and **9** are represented at the same scale). This means that reducing the supply voltage not only reduces the critical charge but also reduces the efficiency in terms of critical charge to make wider pMOS transistors.

Finally, **Figure 10** plots *χ*p as a function of the pulse width and supply voltage in a surface plot and as a family of curves generated by the supply voltage parameter.

**Figure 10.** Dependence of *χ*p,e with pulse width and supply voltage.

The graph in **Figure 10** shows that reducing both the supply voltage and the pulse width decreases the efficiency, in terms of critical charge, of modulating the pMOS transistors channel width.

From all the results presented in this section, it can be deduced that if the SEU robustness of an SRAM cell is to be increased in a certain percentage, increasing the widths of only the pMOS and leaving the nMOS unmodified is more efficient than any other combination of transistor width modulation. Or, for a given percentage area budget, increasing only pMOS widths maximizes critical charge.


**Table 1.** Critical charge and cell area increment for three different values of *r*p, and *r***n = 1 (***W*min = 0.15 μm). The supply voltage is nominal.

**Table 1** shows the critical charges for a pulse of 30 ps for three values *r*p (and *r*n = 1) at nominal voltage. In addition, it shows the increased area with respect to the minimum sized cell (*r*p =  1, *r*n = 1). Areas are obtained by designing cells with the regular layout features and restrictions described earlier.

**Table 1** shows that, for example, for an area increase of 17%, an increment 46% in critical charge is achieved.

To sum up, the transistors channel width modulation technique has shown by simulation to be effective in terms of improving critical charge. For this reason, it was decided to implement and test this technique in a real memory prototype (test chip) described in Section 4.1.
