Author details

check matrix have the same absolute value, equal to the minimum of the α messages connected to the corresponding check node unit, while the dc-th check node message absolute value is equal to the second minimum. Therefore, a compressed check node message can be used, consisting of the signs, first minimum, second minimum, and the index of the first minimum. Regarding the FPGA implementation, the compressed form is suitable for shift register-based implementation in conventional CLB logic, while the uncompressed form is suitable for BRAM implementation. However, in BRAM-based implementation of the check node message, memory in compressed form is proposed for layered decoder with serial processing at processing node level. Routing from the BRAM blocks containing the check node messages to the processing units is achieved using large

3. Routing network: Routing network is implemented using barrel shifters. The number of barrel shifters is dependent on the degree of parallelism in the processing unit. For each AP-LLR input of the processing unit, a pair of barrel shifters—one for routing read mes-

4. Control unit: The control unit is responsible for the generation of read/write addresses for the two memories, the shift amounts for the barrel shifter, as well as the control signals corresponding to the processing units. As in the case of the flooded decoders, ROM type of memories is used to embed the LDPC code information, from which are computed the

A major issue in the layer architecture is represented by the data hazards. Depending on the LDPC code, read-after-write (RAW) data hazards may affect the AP-LLR update: the updated value of the AP-LLR has not been written into the memory, before it is read for a new layer processing [35]. The problem of data hazards is aggravated by the usage of pipeline stages,

This book chapter presents an overview of the main design trade-offs in the implementation of LDPC decoders on FPGA devices. We detail how the main architectural choices for both flooded and layered scheduling strategies map on the built-in resources of modern FPGA

1. The degree of parallelism at processing node level has a major influence in the resource consumption of the LDPC decoder: it gives the number of barrel shifters used for routing, as well as the number of memory ports or memory banks used for message storage.

2. Routing represents an important factor in the cost/performance of the LDPC decoder; highperformance pipelined barrel shifter-based routing can be advantageously implemented in

3. Memories for message storage in partial parallel flooded LDPC decoder or layered decoders can be implemented using embedded BRAM blocks; the main problem is

devices. The main conclusions which can be drawn from this survey are as follows:

modern FPGA devices using conventional CLB resources.

represented by the low usage of the memory bits within the BRAM.

sages and one for routing the update message required for write—is required.

memory addresses, as well as the shift amounts.

both in the barrel shifters and in the processing units.

shift registers.

118 Field - Programmable Gate Array

6. Conclusions

Alexandru Amaricai\* and Oana Boncalo

\*Address all correspondence to: alexandru.amaricai@cs.upt.ro

Computer and Information Technology Department, University Politehnica Timisoara, Timisoara, Romania
