**Power Efficient Data-Aware SRAM Cell for SRAM-Based FPGA Architecture**

Ajay Kumar Singh

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Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/67257

#### **Abstract**

The design of low‐power SRAM cell becomes a necessity in today's FPGAs, because SRAM is a critical component in FPGA design and consumes a large fraction of the total power. The present chapter provides an overview of various factors responsible for power consumption in FPGA and discusses the design techniques of low‐power SRAM‐ based FPGA at system level, device level, and architecture levels. Finally, the chapter proposes a data‐aware dynamic SRAM cell to control the power consumption in the cell. Stack effect has been adopted in the design to reduce the leakage current. The various peripheral circuits like address decoder circuit, write/read enable circuits, and sense amplifier have been modified to implement a power‐efficient SRAM‐based FPGA.

**Keywords:** FPGA, ASIC, static power, dynamic power, leakage current, SRAM cell, subthreshold cell, data‐aware SRAM cell
