Preface

Chapter 7 **The Use of FPGA in Drift Chambers for High Energy Physics**

Gianluigi Chiarello, Claudio Chiri, Giuseppe Cocciolo, Alessandro Corvaglia, Francesco Grancagnolo, Marco Panareo, Aurora Pepino

**Experiments 159**

**VI** Contents

Gabriel Torrens

**Architecture 221** Ajay Kumar Singh

and Giovanni Francesco Tassielli

Steffen Mauch and Johann Reger

Chapter 8 **Real‐Time Adaptive Optic System Using FPGAs 177**

Chapter 9 **FPGA‐SRAM Soft Error Radiation Hardening 197**

Chapter 11 **High‐Speed Deterministic‐Latency Serial IO 249**

Chapter 10 **Power Efficient Data-Aware SRAM Cell for SRAM-Based FPGA**

Raffaele Giordano, Vincenzo Izzo and Alberto Aloisio

This edited volume is a collection of reviewed and relevant research chapters, concerning the developments within the "Field-Programmable Gate Array" field of study. The book in‐ cludes scholarly contributions by various authors and edited by a group of experts pertinent to semiconductors. Each contribution comes as a separate chapter completed within itself but directly related to the book's topics and objectives.

The book has 11 chapters.

The target audience comprises scholars and specialists in the field.

**InTechOpen**

### **Efficient Hardware Architecture for Correlation-Based Spike Detection and Unsupervised Clustering Efficient Hardware Architecture for Correlation-Based Spike Detection and Unsupervised Clustering**

Chien-Min Ou and Wen-Jyi Hwang Chien-Min Ou and Wen-Jyi Hwang

Additional information is available at the end of the chapter Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/66105

#### **Abstract**

This chapter presents a novel hardware architecture for correlation-based spike detection and unsupervised clustering. The architecture is able to utilize the information extracted from the results of spike clustering for efficient spike detection. The architecture supports the fast computation for the normalized correlation and OSORT operations. The normalized correlation is used for template matching for accurate spike detection. The OSORT algorithm is adopted for unsupervised classification of the detected spikes. The mean of spikes of each cluster produced by the OSORT algorithm is used as the templates for subsequent detection. The architecture adopts postnormalization technique for reducing the area costs. Modified OSORT operations are also proposed for facilitating unsupervised clustering by hardware. The proposed architecture is implemented by field programmable gate array (FPGA) for performance evaluation. In addition to attaining high detection and classification accuracy for spike sorting, experimental results reveal that the proposed architecture is an efficient design providing low area cost and high throughput for real-time offline spike sorting applications.

**Keywords:** spike sorting, spike detection, spike clustering, field programmable gate array, brain machine interface
