**Efficient FPGA Implementation of a CTC Turbo Decoder for WiMAX/LTE Mobile Systems**

Cristian Anghel, Cristian Stanciu and

Constantin Paleologu

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2015).

24 Field - Programmable Gate Array

Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/67017

#### Abstract

This chapter describes the implementation on field programmable gate array (FPGA) of a turbo decoder for 3GPP long-term evolution (LTE) standard, respectively, for IEEE 802.16-based WiMAX systems. We initially present the serial decoding architectures for the two systems. The same approach is used; although for WiMAX the scheme implements a duo-binary code, while for LTE a binary code is included. The proposed LTE serial decoding scheme is adapted for parallel transformation. Then, considering the LTE high throughput requirements, a parallel decoding solution is proposed. Considering a parallelization with N = 2<sup>p</sup> levels, the parallel approach reduces the decoding latency N times versus the serial decoding one. For parallel approach the decoding performance suffers a small degradation, but we propose a solution that almost eliminates this degradation, by performing an overlapped data block split. Moreover, considering the native properties of the LTE quadratic permutation polynomial (QPP) interleaver, we propose a simplified parallel decoder architecture. The novelty of this scheme is that only one interleaver module is used, no matter the value of N, by introducing an even-odd merge sorting network. We propose for it a recursive approach that uses only comparators and subtractors.

Keywords: LTE, WiMAX, turbo decoder, single interleaver, Max LOG MAP, parallel architecture, FPGA
