**1. Introduction**

Field programmable gate array (FPGA) is prefabricated integrated circuit (IC), which contains programmable gate matrix to implement logic functions and interconnect resources to connect the logic functions and I/O blocks. These interconnect resources can be electrically programmed by the user to implement any digital circuits and systems. Due to faster time to market, lower cost, and flexibility, FPGA prefers over ASIC (application‐specific IC) design although it has disadvantages like larger size, slower speed, and larger power consumption. Due to the flex‐ ibility of FPGA, it is possible to partially program any portion of the FPGA depending on the requirement even when the rest of an FPGA is still running. Computer‐aided design (CAD) tools and architecture are the two important technologies, which differentiate FPGAs. First memory‐based programming FPGAs were introduced in 1986 by Xilinx Inc., San Jose, CA [1].

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The programmable term in FPGA only reflects that any new function can be implemented on the chip even after its fabrication. Programmability/reconfigurability of an FPGA is based on an underlying programming technology, which can cause a change in behavior of a prefab‐ ricated chip. The main programming technologies used in FPGAs are static random memory (SRAM), flash memory, and antifuse [2–5].

The SRAM‐based FPGAs provide ideal prototyping medium and are widely used to inte‐ grate FPGAs in an embedded system [6–8] due to the use of standard CMOS technologies, higher performance, and reprogrammability. However, the larger static power consumption in SRAM cell limits the use of SRAM‐based FPGAs in portable embedded system compared to flash‐based FPGAs [9, 10]. The other concern related to SRAM‐based FPGA is its volatile nature. Although the dynamic power management and duty‐cycling techniques [11, 12] have been used to save static power during idle mode of FPGA, these techniques are not very effec‐ tive due to the energy consumption associated with the resulting reconfiguration process. Due to large load capacitance and high access rate, SRAM cells are responsible for consuming sig‐ nificant portion of the total power of the design. Thus, SRAM power consumption is an impor‐ tant consideration for designers to find the balance between the performance and the overall power consumption. The speed of the SRAM cell in FPGA is not a critical factor because it does not affect the operating speed of the circuit implemented in FPGA as mentioned in ref. [13].

In this chapter, we investigate the various factors responsible for power consumption in SRAM‐based FPGAs and review the different techniques proposed in the literature to save the power. We will also consider the static and dynamic power in the conventional 6T SRAM cell and its architecture. Various design techniques, presented in the literature, to reduce power consumption in SRAM cell will be reviewed in detail with their merits and demerits. A data‐ aware power‐efficient SRAM cell will be discussed to save power and to optimize the stability.
