*1.4.1. Digital hardware*

There exists a range of solutions to the digital-processing problem for a software-defined radio, each with its own characteristics and application areas. The digital-processing area is, in many respects, as challenging as the analogue processing described in detail in this book and the intention of this section is merely to highlight the options and their main characteristics. The two biggest issues at present are the power consumption and cost of the various options. In a base-station application, these are less of an issue (but are still a significant challenge); however, they are perhaps the main inhibitor to the widespread use of software-defined radio in handsets and other portable devices:

**1.** The use of reconfigurability as a method of providing upgrading, improvement or backwards compatibility (i.e., a smooth transition from a legacy system) is, however, a strong argument for flexible processing and SDR concepts. It is in this context that the processing options outlined in the following will be discussed.

Cost is also a multi-faceted issue. Most designs judge cost based almost exclusively on the cost of the target device used for the code (be it a processor or an FPGA). In the case of a very highvolume application (e.g., a handset), this might be a reasonable approach, although even here it could be somewhat short-sighted. In the case of a base-station design, however, there are many other considerations that will determine the overall cost of a design (particularly if lifetime cost is considered and not just purchase cost). As a summary, the factors that influence the cost of the digital elements of an SDR BTS include


reused between evolutionary models in a range (as well as across models in a given range), are clearly attractive, even if the devices upon which they are based are not the lowestcost components available.

**g.** Flexibility. This is a benefit in terms of time to market for new products and hence a benefit in terms of opportunity cost. If full flexibility could be provided for the same cost as a fixed solution (e.g., a single-application ASIC), then it would be a simple decision to adopt a flexible approach. This is almost never true and hence a full business case must be developed for flexibility, in a given marketplace and each opportunity judged on its merits.

## *1.4.1.1. Digital signal processors*

they are perhaps the main inhibitor to the widespread use of software-defined radio in

**1.** The use of reconfigurability as a method of providing upgrading, improvement or backwards compatibility (i.e., a smooth transition from a legacy system) is, however, a strong argument for flexible processing and SDR concepts. It is in this context that the

Cost is also a multi-faceted issue. Most designs judge cost based almost exclusively on the cost of the target device used for the code (be it a processor or an FPGA). In the case of a very highvolume application (e.g., a handset), this might be a reasonable approach, although even here it could be somewhat short-sighted. In the case of a base-station design, however, there are many other considerations that will determine the overall cost of a design (particularly if lifetime cost is considered and not just purchase cost). As a summary, the factors that influence

**b.** Costs involved in the associated ancillary and interfacing devices (e.g., memory, clock

**c.** Non-recurring expense (NRE). This is most obviously associated with application-specific integrated circuit (ASIC) or application-specific signal processor (ASSP) designs and includes mask-set costs, fabrication and so forth. These costs are rising dramatically as feature sizes reduce and are therefore making the break-even volume (compared to, say,

**d.** Tools/training investment. Changing from one digital technology to another (e.g., from DSPs to FPGAs) may well involve a significant change of design personnel, or at the very least a degree of retraining. This will have an associated cost and also an opportunity cost as the time to market will be increased (see the following). Even changing from one manufacturer's processors to another may involve a loss of productivity while the development team familiarizes itself with a new feature set and the new tricks required

**e.** Cooling. The cost of cooling can undergo step changes as the form of cooling required changes. The most obvious example is in going from convection cooling to forced-air cooling, with the cost of the fans now needing to be added to the bill of materials. Additional power consumption will also add to the cost of the power supply, although with modern switched-mode designs, this is usually small. It is, however, a much bigger issue in handset designs due to the increased requirements it places upon the battery and

**f.** Development time/resource. This is becoming an increasingly important aspect of cost, as product life cycles, even of base-station designs, reduce as each new design appears. The volume of units sold of a particular design is then lower and the cost of producing that design becomes an ever-larger proportion of its selling price. Techniques or architectures, which allow these designs to be generated quickly, or significant portions of designs to be

the user-acceptance issues of large batteries or reduced talk times.

processing options outlined in the following will be discussed.

the cost of the digital elements of an SDR BTS include

**a.** Direct cost of the processing device itself.

FPGAs) much higher as time progresses.

to get the best out of a particular device.

circuitry and so forth).

handsets and other portable devices:

88 Field - Programmable Gate Array

DSPs were arguably the original enabling technology for software-defined radio (other than perhaps in military circles where cost is less important). They have the advantage of complete flexibility, wide applicability and a wide availability of skilled practitioners in their software. They are also high-volume devices and hence the benefits of economies of scale may be realized across a large number of applications in a wide range of industries (not just wireless communications). This, in general, makes up for their lack of optimization for a given specific project or niche application area and allows them to be a realistic option for early prototyping and initial production volumes of a new design, as well as for the final volume product, in some cases.

They are best suited to the less computationally intensive forms of signal processing, rather than very high-speed front-end applications. They are often utilized for involved, off-line processing of data which has been acquired and undergone initial processing/storage by a different type of device (e.g., an FPGA or an ASIC) [16]. They are, however, well supported and also tend to come in backwards-compatible families, which allow development to take place on a state-of-the-art (SOTA) device, with the final application device being lower cost. This generally occurs for two reasons:


### *1.4.1.2. Field-programmable gate arrays*

FPGAs have undergone a revolution in recent years, both in performance and in cost. From humble beginnings as simple, flexible glue logic in complex digital designs, they are now a credible processing platform in their own right and able to rival ASIC solutions in many areas (and act as a low-cost prototyping mechanism for ASIC designs). They have also undergone a revolution in volume pricing, which means that they are no longer consigned to the prototype and initial volume parts of the product life cycle, but can now be used throughout volume production, in some applications [17]. It is also possible to convert from an FPGA to a quasi-ASIC, with a highdegree of confidence of success and a relatively low NRE (and hence break-even volume). FPGAs are therefore challenging and displacing ASICs in traditional ASIC application areas.

Furthermore, they provide much more flexibility than can be cost-effectively built into an ASIC, thereby fitting with the requirements of SDR very well. In common with DSPs, they also tend to come in families, thereby, again, allowing an initial design to take place on a large (potentially over specified) device with the final device being chosen to just fit the processing requirement. It is also possible (but not necessarily economic) to add IP processor cores into an FPGA (or an FPGA-derived ASIC). This makes possible a single-chip solution in some applications and this may be important for size or reliability reasons (with the improved reliability coming from the reduction in devices and soldered joints).

#### *1.4.1.3. ASICs*

The main issue with utilizing ASICs (or, more correctly, application-specific signal processors) within an SDR system lies in their lack of flexibility (or conversely the cost of adding flexibility). There are many methods by which flexibility may be introduced within an ASSP and these include the following:


#### **1.5. About NI-USRP**

The NI USRP-2922 can be used for various communication applications, including

**a.** WiFi

(and act as a low-cost prototyping mechanism for ASIC designs). They have also undergone a revolution in volume pricing, which means that they are no longer consigned to the prototype and initial volume parts of the product life cycle, but can now be used throughout volume production, in some applications [17]. It is also possible to convert from an FPGA to a quasi-ASIC, with a highdegree of confidence of success and a relatively low NRE (and hence break-even volume). FPGAs are therefore challenging and displacing ASICs in traditional

Furthermore, they provide much more flexibility than can be cost-effectively built into an ASIC, thereby fitting with the requirements of SDR very well. In common with DSPs, they also tend to come in families, thereby, again, allowing an initial design to take place on a large (potentially over specified) device with the final device being chosen to just fit the processing requirement. It is also possible (but not necessarily economic) to add IP processor cores into an FPGA (or an FPGA-derived ASIC). This makes possible a single-chip solution in some applications and this may be important for size or reliability reasons (with the improved reliability coming from

The main issue with utilizing ASICs (or, more correctly, application-specific signal processors) within an SDR system lies in their lack of flexibility (or conversely the cost of adding flexibility). There are many methods by which flexibility may be introduced within an ASSP and these

**a.** Provision of multiple toolbox functions with flexible input parameters. An example would be a QAM modulator that had an input variable to configure it from 16 to 256 QAM, for

**b.** Provision of hardware for all current modulation formats, coding schemes and so forth in a single (large!) ASSP, with the ability to select between the different paths. This is not strictly flexible in the generic sense; however, it is flexible in its range of functionality the user will not care how he is provided with service over a range of standards, just that he obtains service at a low cost. The major disadvantage with this option is that it is not really future-proof, unless the system designer has an extraordinary insight into the future trend in mobile communications (and can convince his or her management that he or she

**c.** A combination of one or both of the above with some programmable DSP functionality (e.g., using an embedded DSP core). The key here is in providing enough DSP power to be useful and provide a degree of future-proofing, without designing essentially a DSP device—it would almost certainly be lower cost to buy an off-the-shelf DSP device from

The NI USRP-2922 can be used for various communication applications, including

ASIC application areas.

90 Field - Programmable Gate Array

*1.4.1.3. ASICs*

include the following:

example [18].

is right).

a volume vendor.

**1.5. About NI-USRP**

the reduction in devices and soldered joints).


The NI USRP-2922 as shown in **Figure 1** has the following basic characteristics:


**Figure 1.** Block diagram of NI USRP-2922.

The RF switch allows transmit and receive operations to occur on the same shared antenna. On the NI USRP-2922, one antenna is designated receive-only.The NI USRP is also capable of receiving the signal, where the received signal is mixed down from RF using a directconversion receiver to baseband I/Q components. The digitized I/Q data follows parallel paths through a digital down-conversion (DDC) method that mixes, filters and decimates the input signal to a user-specified rate. Gigabit Ethernet connection is used to pass the down-converted samples to the host computer.

#### *1.5.1. Receive trail*


#### *1.5.2. Transmit trail*


#### **1.6. Design of a generic transceiver for FPGA-based SDR**

In this section, the building blocks of a generic transceiver for FPGA-based SDR modem system built in LabVIEW have been explained. The designed system consists of two parts: the transmitter section and the receiver section. The transmitter section consists of four modules which are a message source module, pulse-shaped filter module, QAM modulator module and Gaussian noise module. The receiver has been designed using an adaptive filter module, QAM demodulator module, sync and tracking module. A brief description of each block follows. The front panel of generic transceiver for SDR modem system is shown in **Figure 2**.

FPGA-Based Software-Defined Radio and Its Real-Time Implementation Using NI-USRP http://dx.doi.org/10.5772/66272 93


**Figure 2.** Front panel of transmitter, Tx parameter.

*1.5.1. Receive trail*

92 Field - Programmable Gate Array

amplify.

used.

*1.5.2. Transmit trail*

specified rate.

to a reference signal.

**1.6. Design of a generic transceiver for FPGA-based SDR**

antenna.

reference signal.

phase (Q) components.

**i.** The received signal is amplified using the low-noise amplifier and drive amplifier

**ii.** The voltage-controlled oscillator (VCO) is controlled by the phase-locked loop (PLL)

**iii.** The mixer down-converts the signals to the baseband in-phase (I) and quadrature-

**iv.** To reduce the noise and high-frequency components in the signal, low-pass filter is

**vi.** The digital down-converter (DDC) mixes, filters and decimates the signal to a user-

**vii.** A standard gigabit Ethernet connection is used to pass the down-converted samples.

**i.** The host computer synthesizes baseband I/Q signals and transmits the signals to the

**ii.** The digital up converter (DUC) mixes, filters and interpolates the signal to 400 MS/s.

**v.** The mixer is used to up-convert the received signals to a user-specified RF frequency.

**vi.** The PLL controls the VCO so that the device clocks and LO can be frequency-locked

**vii.** The transmit amplifier amplifies the signal, which is then transmitted through the

In this section, the building blocks of a generic transceiver for FPGA-based SDR modem system built in LabVIEW have been explained. The designed system consists of two parts: the transmitter section and the receiver section. The transmitter section consists of four modules which are a message source module, pulse-shaped filter module, QAM modulator module and Gaussian noise module. The receiver has been designed using an adaptive filter module, QAM demodulator module, sync and tracking module. A brief description of each block follows.

The front panel of generic transceiver for SDR modem system is shown in **Figure 2**.

**iv.** The low-pass filter reduces noise and high-frequency components in the signal.

**v.** The analogue-to-digital converter digitizes the I and Q data.

device over a standard gigabit Ethernet connection.

**iii.** The digital-to-analogue converter converts the signal to analogue.

so that the device clocks and local oscillator (LO) can be frequency-locked to a

In **Figure 2**, under Tx parameter is used to select the parameters such as IQ sampling rate, Tx frequency, Tx gain and so on of the transmitter. In the **USRP, IP address one s**elects the IP address of the transmitter device such as 192.168.10.2. In the **Tx IQ sampling rate [s/s] field, we must s**et the sampling rate to 500 k for text, random data and 2M for image transmission. **Tx frequency [Hz] is used to s**et the frequency to 2.5 G (the user can use any frequency from 400 MHz to 4.4 GHz for USRP2922). In the **Tx gain [dB]** field, we enter Tx gain 12 and we can take upto 31. Now, one need to select the Tx antenna as Tx1. In the specify message window in the transmitter front panel, we can select the type of the file to be transmitted;it consists of three files: random data, text and image as shown in **Figure 3**.

**Figure 3.** Specify message/random data window.

Random data can be transmitted by selecting the random data field. The message field is set to set the data to be transmitted. Transmitted bits indicate the bits which have to be transmitted. Encode button is meant to encode the transmitted data. Type of encoding is used to select the type of encoding required either convolution viterbi or turbo coding. Similar to the random data, one can select text or image window in order to transmit text or image, respectively. **Figures 3** and **4** show text and image window, respectively.


**Figure 4.** Specify message/text window.

**Figure 5.** Specify message/image window.

We can write the text to be transmitted in the input window as shown in **Figure 4**. Encode button is used to provide encoding scheme. One needs to press the encode button to encode the transmitted data. The type of encoding field is used to select the type of encoding required either convolution viterbi or turbo coding as shown in **Figure 4**. Similarly, one can transmit the image as shown in **Figure 5**. We need to select the path or browse the path of the image and the selected picture is indicated in the front panel.

Pulse-shaping filter parameters field is used to set the system filter parameters as shown in **Figure 5**:

**a. Tx filter:** Used to select the type of filter required raised cosine filter or root raised cosine or none.

**b. Alpha**: Set the alpha to 0.50.

Random data can be transmitted by selecting the random data field. The message field is set to set the data to be transmitted. Transmitted bits indicate the bits which have to be transmitted. Encode button is meant to encode the transmitted data. Type of encoding is used to select the type of encoding required either convolution viterbi or turbo coding. Similar to the random data, one can select text or image window in order to transmit text or image, respectively.

**Figures 3** and **4** show text and image window, respectively.

**Figure 4.** Specify message/text window.

94 Field - Programmable Gate Array

**Figure 5.** Specify message/image window.

**c. Filter length:** Set filter length to 6.

**Samples per symbol:** Set samples per symbol to 8.

**Symbol rate [symbols/s]:** It indicates the symbol rate **M-FSK:** Set the FSK parameters as shown in **Figure 5**.

**a. M-FSK:** Set M-FSK to 4 (can be changed).

**b. FSK deviation [Hz]:** Set FSK deviation to 25.00 k.

**c. Symbol phase continuity:** Select symbol phase continuity to continuous.

**M-PSK:** Set M-PSK to 4. **M-QAM:** Set M-QAM to 8. Now, select the specific packets window from the transmitter front panel to set the message bits as shown in **Figure 6**.


**Figure 6.** Specify modulation window.

Specify packet window is used to set the packet parameters such as guard bits, sync bits, message bits and packed pad (samples). Message bits need to be set 128 bits for random data, text and 4096 bits for image. The PN sequence order for sync bits is also to be specified in the window as shown in **Figure 7**.


**Figure 7.** Specify packet window.

Now at the receiver end we need to receive the sent message for that the receiver must be set to certain parameters as shown in **Figure 8**. The front panel of the receiver looks as shown in **Figure 8**; select Rx parameter window, specify the IP address, Rx parameter sand acquisition duration [s].

**Figure 8.** Front panel of USRP receiver/Rx parameter.

Rx parameter is used to select receiver Rx parameter. USRPIP address for the receiver is specified in the IP address of the receiver device. Rx IQ sampling rate [s/s] is set to 500k to provide the required sampling rate. Rx frequency [Hz] is used to set the frequency to2.5G. Rx gain [dB] is set to12, same as gain for the Tx. Rx antenna field is used to select the Rx antenna as Rx1. In the field acquisition duration [s], set duration 40 m for random data and text, 56 m for image. Now one must select Rx display as per selected specify message in the transmitter. If text is selected at transmitter, then text should be selected at receiver similar to random data and image as shown in **Figures 9**–**11**.

**Figure 9.** Rx display/random data Rx.

Specify packet window is used to set the packet parameters such as guard bits, sync bits, message bits and packed pad (samples). Message bits need to be set 128 bits for random data, text and 4096 bits for image. The PN sequence order for sync bits is also to be specified in the

Now at the receiver end we need to receive the sent message for that the receiver must be set to certain parameters as shown in **Figure 8**. The front panel of the receiver looks as shown in **Figure 8**; select Rx parameter window, specify the IP address, Rx parameter sand acquisition

window as shown in **Figure 7**.

96 Field - Programmable Gate Array

**Figure 7.** Specify packet window.

**Figure 8.** Front panel of USRP receiver/Rx parameter.

duration [s].

**Figure 10.** Rx display/text Rx.

**Figure 11.** Rx display/image.

Random data: Click on random data in order to receive random data. Encoded bits in this window indicate the bits which are encoded. Decoded bits indicate the bits that are decoded from the transmitted data. Decode button is used to decode the received data. Type of decoding field is used to select the type of decoding required either convolution viterbi or turbo coding which is selected at the transmitter.

For receiving the text, we need to select the text field. Encoded text field indicates the encoded text. Decoded text field indicates the decoded text.


**Figure 12.** Specify demodulation window.

For receiving the image, we need to select the image field. Encoded image field indicates the encoded image. Decoded image field indicates the decoded image. Decode button is used to decode the received data. Type of decoding needs to be set to either convolution viterbi or turbo coding which is selected at the transmitter. Now, select the specify demodulation window, as shown in **Figure 12**, all the parameters to be set exactly the same as transmitter modulation.

**Matching filter parameters:** Set the matching filter parameters as shown in **Figure 12**:


**Figure 11.** Rx display/image.

98 Field - Programmable Gate Array

which is selected at the transmitter.

**Figure 12.** Specify demodulation window.

text. Decoded text field indicates the decoded text.

Random data: Click on random data in order to receive random data. Encoded bits in this window indicate the bits which are encoded. Decoded bits indicate the bits that are decoded from the transmitted data. Decode button is used to decode the received data. Type of decoding field is used to select the type of decoding required either convolution viterbi or turbo coding

For receiving the text, we need to select the text field. Encoded text field indicates the encoded

**c. Filter length:** Set filter length to 6.

**Samples per symbol:** Set samples per symbol to 8. **Symbol rate [symbols/s]. M-FSK:** Set the FSK parameters as shown in **Figure 13**:


**Figure 13.** Receiver/specify packet window.


**e.** Symbol phase continuity: Select symbol phase continuity to continuous.

Now, select the specify packet window from the receiver front panel, as shown in **Figure 13**.

Specify packet specifies the packet same as transmitter, that is, 128 for random data and text, for image 4096. Message bits field holds the number of bits, same as in the transmitter. Number of packets to be expected must be entered in this window which is the same as in the transmitter. Now, select output parameters window, which shows the constellation diagram, eye diagram and BER Vs Eb/No with respective received data as shown in **Figure 14**.

**Figure 14.** Output parameters.

Constellation graph is used to indicate the constellation of the received bits with respect to data. Eye diagram indicates the eye diagram of the received bits with respect to data. BER Vs Eb/No indicates the BER Vs Eb/No of the received bits with respect to data. BER Data Export to Excel: Click on BER Data Export to Excel Button it will export BER Vs Eb/No data to Excel sheet. Decode: Press the decode button to decode the received data. Type of decoding: Select the type of decoding required either convolution viterbi or turbo coding which is selected at the transmitter.
