**5. Conclusions**

If the charge collection efficiency values obtained as fitting parameters are analyzed, it is confirmed that charge collection efficiency for electrons (*η*e) is higher than for holes (*η*h) [19]. In addition, critical charge for electrons (*Q*crit,e) is smaller than for holes (*Q*crit,h). This electron and hole asymmetry in terms of charge collection efficiency and in terms of critical charge is

Usual 6T‐cells are designed with minimum sized access transistors (acc <sup>=</sup> min), minimum sized pMOS (p <sup>=</sup> min), and non‐minimum‐sized nMOS (n = CR · min). The CR parameter is called cell ratio and is usually greater than 1, being the most frequent values between 1.5 and 2.5 as a trade‐off to assure cell stability during write and read operations [3]. Note that this cell with this transistor dimensions does not have straight diffusions. In addition, also note that this cell has the internal latch (cross coupled inverters) equal to the ones in E cell.

From the irradiation experiments, it has been obtained that the C cell shows an SER that is a 46% of the E cell SER, that is, C cell receives less than half the number of SEUs per time unit than E cell. Note that this improvement is achieved only by adequate transistor sizing, because both cells (C and E) have the same area. If instead of considering this two cells, we compare the C cell with respect to a usual cell with CR = 2, then the SER of the C cell is a 57% the SER

The effects of the transistor width modulation technique on power consumption and access time are summarized in **Table 4**. For example, it can be observed that C and E cells show similar access times and power consumption levels (although there is an increase of the energy needed to change the logic state of the C cell, it presents lower leakage current than the E cell).

**A** 125.5 4.65 0.32 0.28 168 468 **B** 134.2 5.93 0.33 0.28 178 429 **C** 144.1 7.10 0.35 0.28 184 346 **D** 163.8 6.45 0.36 0.27 165 468 **E** 180.6 5.59 0.36 0.26 149 517

Finally, it was also analyzed how the modulation technique affects read and write stability, by computing two well‐known parameters: read static noise margin (RSNM) and write static noise margin (WSNM). As it can be seen in **Table 4**, RSNM is not very affected. Despite that, in [20], a technique to recover the RSNM of a 6T cell is analyzed. In addition, WSNM is degraded in some cell types (the ones in which pMOS transistors are increased in size). To overcome that, if needed, there are write assist techniques that could be suitable to improve WSNM [21, 22]. However, all tested cells types are experimentally writable with no write assist

**Table 4.** Summary of different power, speed and stability figures of the fife different cell types.

**Write time (ns) Read time (ns) RSNM (mV) WSNM (mV)**

the root cause of the observed differences of SER dependency with *r*n and *r*p.

of the CR = 2 cell.

216 Field - Programmable Gate Array

technique applied.

**Cell type Leakage (pW/cell) Write energy**

**(fJ/cell)** 

Due to technology scaling, radiation effects have become a major concern for modern inte‐ grated circuits even at ground level. FPGA SRAMS are not an exception, and radiation effects are even maximized, because these circuits are usually designed with transistors sizes close to the minimum allowed by technology. The so‐called SEUs are the main radiation issue for SRAMs. SEUs are capable of altering the memory content of SRAM cells without permanently damaging the circuit.

A technique based on transistor width modulation was developed and tested. The technique consists in modifying the cell transistors channel width in a way that is compatible with the so‐called regular layouts (i.e. avoiding the formation of bends in the diffusion regions). The main advantage of this layout scheme is that it reduces parameter variation. Nevertheless, it imposes some geometrical restrictions over transistor sizes, so that the modulation technique has to be designed to meet those constraints.

The technique was implemented and tested using two approaches: critical charge and experimental SER. Critical charge is a parameter cheap and easy to obtain, because it can be calculated using electrical simulations. However, as it was shown, it does not give a directly accurate measurement of the robustness of an SRAM cell if transistor areas are modified. Conversely, SER is a better parameter to assess cell robustness. The main drawback of SER is that it can only be directly obtained with experimental measurements, which are expensive and time consuming. After a preliminary analysis, the most interesting transistor size combi‐ nations where selected and implemented in a custom‐fabricated test chip. The test chip has 4096 cells of each one of the five selected cells types, and all of them where irradiated with alpha particles to experimentally obtain SER.

Results show that some of the cell types are much more robust to radiation than others. In addition, results also reveal that, while a larger critical charge can lead to a better SER, some memory cells with higher critical charge also exhibit worst SER. This behavior was found when increasing nMOS channel widths. This suggests that special care must be taken when com‐ paring SRAM cells with different transistor areas using critical charge as a figure of merit. Despite that, results indicate that SER can be estimated from critical charge with a model if some cell intrinsic cell parameters are known.

Results also show that SER is improved by increasing the pMOS transistors channel width (*W*p), and worsened when the nMOS transistors channel width is increased (*W*n). For this reason, the best way to design a hardened 6T SRAM cell is by minimizing the nMOS transistors channel width and dedicating all additional area to increase pMOS transistor channel width. In addition, for a 65‐nm CMOS commercial technology, SER was reduced to a 57% of the value that conventional nonstructured layout cells exhibit. Due to careful transistor sizing, this radiation robustness improvement was achieved with minor area penalty. However, this hardened cells with wider pMOS transistors, also show a reduction in cell writability. To overcome this issue, write assist techniques can be implemented. Nevertheless, if a trade‐off between writability, area, and radiation robustness is achieved by proper transistor sizing, hardened cells remain writable without any further action. Finally, with the modulation technique presented in this chapter, the achieved cell radiation robustness gain is fundamen‐ tally an area trade‐off, provided that the cell remains writable. For this reason, at design level, radiation robustness can be set as an adjustable parameter in memory compilers.
