**2. Radiation impact on SRAMs**

The analysis of radiation impact on integrated circuits is difficult and is typically performed by experimental tests or using device‐level simulations. However, the critical charge (*Q*crit) is a parameter usually used as a standardized methodology to analyze the circuit‐level impact of radiation on SRAMs [6, 7]. One of the main advantages of this parameter is that it can be obtained by electrical simulations, which are cheaper than experimentation and less time consuming than device‐level simulations. In addition, it helps to understand how SEUs are produced.

**Figure 1.** Example of a double exponential current pulse.

When an energetic particle impacts a CMOS circuit substrate, it induces a charge track due to electron‐hole pair generation. This deposited charge can be collected by a sensitive node typically the drain of an off transistor—which is near to the ionization track [4]. This results in a transient current pulse at the node. A sufficiently strong current pulse will modify data stored in the cell (cell flip). If this occurs, an SEU is produced. The word "Single" means that the cell upset is caused by a single energetic particle. The parameter used to quantify the minimum amount of charge collected by a memory element node that changes its state is the critical charge. Typically, *Q*crit is determined by electrical simulation analyzing how a given memory cell flips under current pulses having different shapes and intensities. It has been reported that energetic particle strikes lead to current transients with varying pulse durations (pulse width), and that the *Q*crit value of a node is a function of the waveform shape [8, 9]. For this reason, a proper choice of current waveforms to estimate the critical charge is important. In this chapter, we will use the well‐known double‐exponential current source model given by

#### FPGA‐SRAM Soft Error Radiation Hardening http://dx.doi.org/10.5772/66195 201

$$\dot{\mathbf{u}}(t) = \dot{\mathbf{u}}\_0 \left( e^{-\frac{t-t\_0}{t\_1}} - e^{-\frac{t-t\_0}{t\_2}} \right) \tag{1}$$

where *i*(*t*) is the current intensity at time *t*, *i*0 is a parameter that scales the current intensity, *τ*<sup>1</sup> determines the current fall‐time, *τ*2 its rise time, and *t*0 is the time at which the current peak is initiated. The total charge injected in the node is the area under the *i*(*t*) curve. The shape of one of these curves is represented in **Figure 1**.

**Figure 2** depicts a 6‐transistor SRAM (6T‐SRAM) cell configuration. It has two cross‐coupled inverters which form the two internal cell nodes (LN and RN). In addition, it has two access transistors, which are used to reach the internal nodes from outside the cell in the read and write operations.

**Figure 2.** 6T‐SRAM cell schematic.

**2. Radiation impact on SRAMs**

200 Field - Programmable Gate Array

**Figure 1.** Example of a double exponential current pulse.

produced.

The analysis of radiation impact on integrated circuits is difficult and is typically performed by experimental tests or using device‐level simulations. However, the critical charge (*Q*crit) is a parameter usually used as a standardized methodology to analyze the circuit‐level impact of radiation on SRAMs [6, 7]. One of the main advantages of this parameter is that it can be obtained by electrical simulations, which are cheaper than experimentation and less time consuming than device‐level simulations. In addition, it helps to understand how SEUs are

When an energetic particle impacts a CMOS circuit substrate, it induces a charge track due to electron‐hole pair generation. This deposited charge can be collected by a sensitive node typically the drain of an off transistor—which is near to the ionization track [4]. This results in a transient current pulse at the node. A sufficiently strong current pulse will modify data stored in the cell (cell flip). If this occurs, an SEU is produced. The word "Single" means that the cell upset is caused by a single energetic particle. The parameter used to quantify the minimum amount of charge collected by a memory element node that changes its state is the critical charge. Typically, *Q*crit is determined by electrical simulation analyzing how a given memory cell flips under current pulses having different shapes and intensities. It has been reported that energetic particle strikes lead to current transients with varying pulse durations (pulse width), and that the *Q*crit value of a node is a function of the waveform shape [8, 9]. For this reason, a proper choice of current waveforms to estimate the critical charge is important. In this chapter,

we will use the well‐known double‐exponential current source model given by

**Figure 3** shows the current sources scheme used to simulate SEUs. In particular, it is necessary to investigate two types of SEUs: a 0‐to‐1 SEU, where the impacted node is at 0 level, and a 1‐ to‐0 SEU, where the impacted node is at 1 level. Due to cell symmetry, only two configurations cover all possibilities of memory cell perturbation. **Figure 3** also shows that a charge injection on a node which is at 0 requires the nMOS transistor to drain the collected charge due to the particle hit. Conversely, when a particle hits a node which is at 1, the pMOS transistor maintains the stored value by providing the current needed to hold the node electrical value.

**Figure 3.** 6T‐SRAM cell schematics for simulating a 1 to 0 SEU (left) and a 0 to 1 SEU (right).

This chapter deals only with 6T SRAM cells, although there are other SRAM which are specially designed to deal with radiation issues. In general, they are hardened SRAM cells that maintain their stored data even if the electrical state of some of their nodes is flipped by a particle strike, some of them are described in [10, 11]. The main drawbacks of them are the increase in cell transistor count with the consequent area increase. In addition, in these cells, it is difficult to implement regular cell layouts, which, as it will be described in Section 3, is a useful method for parameter variation minimization. Furthermore, nonstandard cells complicate the possi‐ bility to include them in current SRAM and FPGA design flows. Conversely, the technique that will be described in Section 3 is fully compatible with SRAM memory compilers and easily adaptable to current FPGA designs. Other mitigation techniques, such as supply voltage increase [9], are not suitable to be implemented in many applications due to their impact on power consumption and long‐term reliability.
