**7. Concluding remarks**

are separated into five types: the number of adders, multipliers, dividers, comparators, and registers. **Tables 3** and **4** show the area complexities of the normalized correlator and OSORT modules, respectively. It can be observed from **Table 3** that, in the normalized correlator module, the correlator unit and switch buffer have larger area complexities. The number of adders, multipliers, and registers grows with the block dimension *N* and the number of templates *c* in the correlator unit. Let *L* be the capacity (i.e., the maximum number of spikes) of each buffer in the switch buffer. The number of registers in the switch buffer therefore is dependent on *L* and *N*, as shown in **Table 3**. The area complexities of the other types are of *O*(1). Therefore, the proposed circuit has low consumption of dividers and comparators. From **Table 4**, we observe that only the area complexities of the buffers in the OSORT module grow

**Correlator Thresholding unit Switch buffer Subtotal**

**Mean updating unit** **Subtotal**

with *N*. The other parts of the OSORT module have fixed area complexities.

Adders *O*(1) *O*(1) *O*(*cN*) *O*(1) 0 *O*(*cN*) Multipliers *O*(1) *O*(1) *O*(*cN*) *O*(1) 0 *O*(*cN*) Dividers 0 0 1 0 0 1 Comparators 0 0 0 *O*(1) 0 *O*(1) Registers *O*(1) *O*(*N*) *O*(*cN*) *O*(1) *O*(*LN*) *O*(*cN* + *LN*)

Adders 0 *O*(1) *O*(1) *O*(1) Multipliers 0 *O*(1) *O*(1) *O*(1) Dividers 0 0 *O*(1) *O*(1) Comparators 0 *O*(1) 0 *O*(1) Registers *O*(*cN*) *O*(1) *O*(1) *O*(*cN*)

The proposed architecture has been implemented by FPGA for performance measurement. The target FPGA device for the hardware implementation is Altera STRATIX IV EP4SGX230. The design platform for the experiments is the Altera QUARTUS II with QSYS. **Table 5** shows the hardware utilization of the proposed architecture. There are four different FPGA hardware resources considered: adaptive look-up tables (ALUTs), dedicated logic registers, block memory bits, and DSP blocks. The DSP blocks are dedicated to the implementations of adders, multipliers, dividers, and comparators. The ALUTs, dedicated logic registers, and block memory bits can be used for the implementation of registers, as well as adders, multipliers, dividers, and comparators. It can be observed from **Table 5** that the consumption of DSP blocks of normalized correlator is higher than that of the OSORT module. This is because the

**Filter unit Block energy**

20 Field - Programmable Gate Array

**Table 3.** Area complexities of the normalized correlator module.

**Table 4.** Area complexities of the OSORT module.

**Buffer Distance computation unit**

**computation**

The proposed architecture has been found to be effective for real-time spike sorting. It features high accuracy, low hardware resource consumption, and high throughput. The combination of the normalized correlation and OSORT algorithm is beneficial for accurate spike detection with high TPR and low FAR even for low SNR values. The postnormalization approach adopted by the normalized correlator circuit is also able to reduce the area costs for the normalization operations. In addition, the switch buffer in the correlation circuit can effectively coordinate the operations of spike detection and classification for achieving high throughput. Experimental results reveal that the proposed architecture achieves TPR = 82.71% and FAR = 1.06% for SNR = −3 dB. The ALUT consumption is only 21.57% for the FPGA device STRUTIX IV EP4SGX230. The throughput is 25.04 Msamples/sec for the clock rate 100 MHz. All these facts demonstrate the effectiveness of the proposed architecture.
