**3. Electron beam lithography**

The fundamental limit of optical lithography is not determined by the optical system alone but rather by an overall contribution from the optics, resist and subsequent process steps. As depicted in **Figure 3**, there exist in general two kinds of resolution, one which is linked to feature size and the other to pitch. While the feature size determines the critical dimension that can be obtained (e.g., size of the transistor), the pitch determines its density on the wafer (e.g.,

**Figure 3.** Example of pattern to be exposed showing a hole diameter as smallest feature and related pitch.

1

*n*

*R k*

For clarity, we will focus only on projection systems in this paragraph. The pitch resolution (R) of these systems is usually expressed in terms of source wavelength *λ* and numerical aperture

sin

where *k1* a process-dependent constant with values in 0.5–1 range, *n* is the refractive index of the media between the mask and the wafer, and *θ* is half acceptance angle of the lens (see

To improve the pitch resolution, it is necessary to decrease (*λ, k*1) and to enhance the numerical aperture. Historically, this improvement was driven by decrease in wavelength *λ* of the source. From mercury lamps at 365nm–435nm wavelength, to excimer laser sources with Krypton Fluoride (248 nm), Argon Fluoride (193 nm), and molecular Fluorine (157 nm) [9]. Furthermore, optical resolution limit has been pushed toward sub-100 nm features using resolution enhancement techniques (RET) such as optical proximity correction, high numerical aperture, and phase-shift masks; 65 nm device geometry (nodes) was indeed achieved using wavelength as large as 193 nm [10, 11]. While numerical aperture higher than 1 is not possible in conventional air-media imaging, using water between the last imaging lens and the wafer has pushed down the limit to sub-45 nm [12]. This technique, known as immersion lithography, is a potential candidate to take over the actual 193 nm technology in the industry. To complete the picture, extreme UV (EUV) is another immerging technique on which relies the future of next

generation of circuit components to push further resolution down to sub-20 nm [13].

q

<sup>=</sup> (1)

l

number of transistors per wafer).

46 Modern Technologies for Creating the Thin-film Systems and Coatings

( = ()) as

**Figure 2**).

Electron beam lithography has been generally accepted as a valuable tool in research and technology development because of its high degree of flexibility and its outstanding resolution capability. There are many versions of electron lithography systems starting from modified scanning electron microscope (SEM) to mask-writers, shaped-spot systems, and electron-beam projection machines.

Converted SEM systems are best adapted for research where the throughput is not a critical issue. They are useful for applications involving small devices such as metallic junctions, few transistors, lines, dots, and small gratings. The pattern data are transferred to the controlling computer, which then directs a tiny focused electron beam (ebeam) to desired locations on the resist by deflecting and turning the beam on and off. The area of an individual chip is selected, and the beam draws out the features in that area pixel-by-pixel with a predefined dose. The scan rate is adjusted to deliver a "desired dose" of electrons to a selected area of the resist.

A crucial factor for electron beam lithography in the industry is the throughput performance. Scaling down features increases pattern density and hence exposure time. Throughput rate can be increased by projecting large complex patterns at one shot onto a resist-coated wafer. In this case, electron beam passes through apertures and masks on which shaped geometries like square or rectangle are fabricated. Electron projection lithography is one of the nextgeneration lithography techniques that could be used for printing sub-70 nm structures on a wafer. Well-known and promising projection systems are scattering with angular limitation projection electron-beam lithography (SCALPEL) developed at Lucent Technologies [14] and IBM prototype called projection reduction exposure with variable axis immersion lenses (PREVAIL) [15].

**Figure 4.** A schematic illustration of proximity effects where red rectangles represent original exposed area. The beam energy was 20 keV and the exposing current is 15 pA.

The resolution of ebeamlithographydepends strongly onthe interaction which occurs between the electron and the resist/substrate layer. Considerable efforts have been made to understand the resolution limits in ebeam lithography [16, 17]. The size ofthe beam is notthe limiting factor because sizes of nearly 2 nm are routinely reached and the diffraction effects are negligible. As the primary electrons hit the resist, part of their energy is dissipated in form of secondary electrons and backscattered electrons. Secondary electrons with energy lying between 2 and 50 eV and of few nanometer range contribute to the major resist exposure. Backscattered electrons experience instead a wide scattering angle into the resist and the substrate which dramatically broadens the exposure area [18, 19]. At 20 keV, for example, the range of backscattered electrons is about 5 µm meaning that patterns of less than that range will experience cumulative exposure. As a consequence, proximity effects, sample charging, and placement accuracy are major factors affecting electron beam lithography systems. **Figure 4** is an example showing proximity effects on 200-nm-thick HSQ negative resist on silicon substrate. As a result, the corners of the big rectangles are not developed to desired size and also overlap between the small rectangle and the big ones is over exposed.

Fortunately, correction techniques exist to circumvent and attenuate effects of these limiting factors. This topic will not be completely addressed in this chapter, but we will instead present few ways used to correct for proximity effects. On way to perform this correction is to change the initial pattern and assign a proper dose to each element as illustrated in **Figure 5**.

**Figure 5.** A schematic illustration of proximity effects correction made by changing the shape of the design and by assigning a dose to each element.

**Figure 6.** A schematic illustration showing the extent of exposed regions in thick (left) and thin (right) substrate for two subsequent point exposures.

From a practical point of view, using thin resist layer and substrates with low atomic mass helps to decrease proximity effects by lowering the backscattered coefficient. As sketched in **Figure 6**, an incident electron beam "forward-scatters" hits the resist. Consequently, strong scattering in the thick substrate layer results in broadly distributed "back-scattered" electrons, which expose a wide region of the resist. This broadening is less pronounced for thin substrate. As demonstrated in Ref. [20], metallic nanogaps of sub-5 nm opening were successfully transferred to 100 nm thick using a thin silicon nitride substrate. In Ref. [20], the resist was 100 nm-thick PMMA exposed with 30 keV beam energy.

### **4. Pattern transfer**

the primary electrons hit the resist, part of their energy is dissipated in form of secondary electrons and backscattered electrons. Secondary electrons with energy lying between 2 and 50 eV and of few nanometer range contribute to the major resist exposure. Backscattered electrons experience instead a wide scattering angle into the resist and the substrate which dramatically broadens the exposure area [18, 19]. At 20 keV, for example, the range of backscattered electrons is about 5 µm meaning that patterns of less than that range will experience cumulative exposure. As a consequence, proximity effects, sample charging, and placement accuracy are major factors affecting electron beam lithography systems. **Figure 4** is an example showing proximity effects on 200-nm-thick HSQ negative resist on silicon substrate. As a result, the corners of the big rectangles are not developed to desired size and

Fortunately, correction techniques exist to circumvent and attenuate effects of these limiting factors. This topic will not be completely addressed in this chapter, but we will instead present few ways used to correct for proximity effects. On way to perform this correction is to change

**Figure 5.** A schematic illustration of proximity effects correction made by changing the shape of the design and by

**Figure 6.** A schematic illustration showing the extent of exposed regions in thick (left) and thin (right) substrate for two

From a practical point of view, using thin resist layer and substrates with low atomic mass helps to decrease proximity effects by lowering the backscattered coefficient. As sketched in **Figure 6**, an incident electron beam "forward-scatters" hits the resist. Consequently, strong

the initial pattern and assign a proper dose to each element as illustrated in **Figure 5**.

also overlap between the small rectangle and the big ones is over exposed.

48 Modern Technologies for Creating the Thin-film Systems and Coatings

assigning a dose to each element.

subsequent point exposures.

We had so far introduced lithography techniques widely used to expose appropriate resists. This lithography step is principally devoted to create a resist image and precisely define appropriate areas (pattern) on the substrate. After resist development, the pattern is transferred with micrometric or nanometric scale to the substrate after subsequent process steps such as liftoff or etching (see **Figure 7**).

**Figure 7.** Exposed resist pattern transferred to the substrate by liftoff (top) and by etching (bottom).

Two major factors impact dramatically the fidelity of pattern transfer to the wafer, namely resist profile and overlay. Resist shape, that is, resist profile, requirement is generally dictated by post-lithography process steps. The profile is governed by exposure dose, the developer, as well as resist properties such as sensitivity and contrast. Let's consider the case of liftoff process which is a widely used technique for fabricating micro- and nanodevices that combines lithography and thin film deposition. The resist under the deposited film is removed with a solvent leaving only the film on required locations of the substrate. The main conditions for a proper liftoff are the formation of an undercut in the resist after development and the perpendicular incidence of the film particle beam onto the substrate (**Figure 8a**). The undercut ensures that the evaporated metal, deposited on the patterned resist, is discontinuous, thereby enabling the working metal liftoff. As illustrated in **Figure 8c**, a successful lift-off could be obtained with resist profile having an "undercut" shape. In fact, wings at the edges of structure appear when the profile is not favorable like in the bowel shape case (**Figure 8b**, **d**).

**Figure 8.** Scanning electron microscope images of resist profile (a,b) and line metallic structure (c,d). Images (a) and (b) were obtained using a trilayer of SML/ZEP520A/PMMA electron beam resists. Images (c) and (d) correspond to liftoff process of 100-nm-thick gold using SML electron beam resist. Raith 150 ebeam system was used to expose resists.

Overlay comes into play when several fabrication levels are needed to fabricate a given structure. Overlay error determines the precision at which a pattern is placed accurately in wanted position on the chip. Mostly, placement accuracies of sub-30 nm up to 1 µm are required to connect micrometric or nanometric scale elements to the pads or between other elements of the structure. Alignment marks are usually used to achieve such precisions, and the patternplacement accuracy increases when the marks are as close as possible to the critical areas. Alignment system consists generally of a detector, which detects a given mark, and a software that analyzes and determines the center of the mark relatively to a reference. The accuracy depends not only on the detector signal but also on the quality of the marks. Depending on subsequent process requirements, these marks can be made from resist, metal or being etched. **Figure 9** illustrates transferred ellipsoidal on silicon waveguide gold obtained by liftoff of 30 nm-thick gold. An alignment of <30 nm was required to properly align gold nanostructure on the waveguide [21].

**Figure 9.** Scanning electron image of 11 ellipsoidal gold on Si waveguide for guided plasmonic applications.
