**6. Results and discussion**

The proposed resistive threshold logic and FFT computing architecture have been tested and compared with corresponding CMOS [14], dynamic MOS and pseudo‐NMOS circuits. Propagation delay, total harmonic distortion, area, power dissipation and leakage power were compared. For the fairness in comparison the technology, sizes of all components in the circuit are kept same.

Comparisons of the memristor‐based resistive threshold logic with other logic families were carried out. **Tables 2** and **3** give the comparison results of propagation delay of NAND and NOR gates, respectively, implemented using various logic families. Comparison of resistive threshold logic with CMOS, pseudo‐NMOS and dynamic‐MOS logic families was carried out. The experiment was carried out for various numbers of inputs. The general trend in the existing logic family is that the propagation delay of a gate increases as the number of inputs increases. This is due to the fact that the increase in the number of inputs means the increase in the number of input transistors. More transistors in the path lead to increase in the propa‐ gation delay of the gate.

But in the case of resistive threshold logic, this problem can be avoided. This is due to the fact that when the number of inputs increases, the number of memristors increases, but in a paral‐ lel fashion. This does not increase the path between input and output. Thus, the increase in the number of inputs does not affect the propagation delay of the overall circuit. This leads to lower propagation delay in the resistive threshold logic compared to other logic families, as the number of inputs increases. Comparison of propagation delay is shown for both NAND and NOR gates (see **Tables 2** and **3**).


**Table 2.** Comparison of propagation delay of NAND gate various logic families.


**Table 3.** Comparison of propagation delay of NOR gate various logic families.

**6. Results and discussion**

circuit are kept same.

The proposed resistive threshold logic and FFT computing architecture have been tested and compared with corresponding CMOS [14], dynamic MOS and pseudo‐NMOS circuits. Propagation delay, total harmonic distortion, area, power dissipation and leakage power were compared. For the fairness in comparison the technology, sizes of all components in the

**Figure 18.** Circuit diagram of XOR gate using memristor‐based resistive threshold logic.

**Figure 17.** Circuit diagram of AND gate using memristor‐based resistive threshold logic.

112 Fourier Transforms - High-tech Application and Current Trends

Comparisons of the memristor‐based resistive threshold logic with other logic families were carried out. **Tables 2** and **3** give the comparison results of propagation delay of NAND and NOR gates, respectively, implemented using various logic families. Comparison of resistive threshold logic with CMOS, pseudo‐NMOS and dynamic‐MOS logic families was carried out. The experiment was carried out for various numbers of inputs. The general trend in the Another comparison that shows the advantage of the proposed logic family is that of total harmonic distortion (THD). The total harmonic distortion gives the measure of harmonic dis‐ tortion present in a circuit. Consider a signal of frequency *x*, the harmonics of the signals are signals containing frequencies 2*x*, 3*x*, 4*x* and so on. These harmonics cause distortion in the output of the circuit. The total amount of distortion caused by the harmonics is measured as total harmonic distortion. It can be defined as the ratio of powers of all harmonics to the power of the fundamental frequency.

Let the power of the fundamental frequency signal be *P*<sup>1</sup> . Let the powers of the harmonics be *P*2 , *P*3 , *P*4 , …*P*<sup>∞</sup> . Then the total harmonic distortion can be expressed as Eq. (8).

$$\text{THD} = \frac{\sum\_{i=2}^{n} P\_i}{P\_i} \tag{8}$$

So higher the THD value means higher the distortion caused by the harmonics. When com‐ paring the values in **Table 4**, it can be seen that the total harmonic distortion of the proposed memristor‐based resistive threshold logic is less when compared to other existing logic fami‐ lies. Thus, it can be seen that the proposed logic family has several advantages when com‐ pared to the existing logic families. Various comparisons were carried out for the fast Fourier transform circuits of **Figure 13**. **Table 5** gives the comparison of area of the FFT circuit imple‐ mented using different logic families.


**Table 4.** Comparison of total harmonic distortion of NOR and NAND gate various logic families.


**Table 5.** Comparison of the total area of FFT circuits using various logic families.

The area comparison clearly shows that the circuit implements using the proposed logic fam‐ ily require less area compared to most of the other existing logic families. Another comparison was carried out regarding the power dissipation of the circuit, the results of which are shown in **Table 6**.


**Table 6.** Comparison of thetotal power dissipation of FFT circuits using various logic families.

The proposed logic family consumes less power when compared to other logic families. In **Table 6**, the power dissipation of the circuit using dynamic MOS is much less compared to other logic families owing to the fact that the dynamic MOS is a clocked logic family.

Now, **Table 7** shows the comparison of the FFT circuit implemented using various logic gates, in respect of their leakage power. The slight increase in the leakage power of the circuit using proposed logic family is due to the presence of op‐amp in the circuit.


**Table 7.** Comparison of leakage power of FFT circuits using various logic families.

memristor‐based resistive threshold logic is less when compared to other existing logic fami‐ lies. Thus, it can be seen that the proposed logic family has several advantages when com‐ pared to the existing logic families. Various comparisons were carried out for the fast Fourier transform circuits of **Figure 13**. **Table 5** gives the comparison of area of the FFT circuit imple‐

**Logic family THD of NAND (%) THD of NOR(%)**

**Table 4.** Comparison of total harmonic distortion of NOR and NAND gate various logic families.

CMOS logic 71.2091 107.4098 Pseudo NMOS 76.2288 97.9864 Dynamic MOS 51.0608 146.7818 Resistive threshold logic 61.7043 85.2743

**Logic family Area (µm2**

**Table 5.** Comparison of the total area of FFT circuits using various logic families.

CMOS logic 83.5200 Pseudo NMOS 53.0496 Dynamic MOS 58.4852 Resistive threshold logic 58.1292

**Logic family Power** CMOS logic 19.3842 µW Pseudo NMOS 14.6467 µW Dynamic MOS 03.9515 nW Resistive threshold logic 13.7932 µW

The area comparison clearly shows that the circuit implements using the proposed logic fam‐ ily require less area compared to most of the other existing logic families. Another comparison was carried out regarding the power dissipation of the circuit, the results of which are shown

**)**

The proposed logic family consumes less power when compared to other logic families. In **Table 6**, the power dissipation of the circuit using dynamic MOS is much less compared to

Now, **Table 7** shows the comparison of the FFT circuit implemented using various logic gates, in respect of their leakage power. The slight increase in the leakage power of the circuit using

other logic families owing to the fact that the dynamic MOS is a clocked logic family.

proposed logic family is due to the presence of op‐amp in the circuit.

**Table 6.** Comparison of thetotal power dissipation of FFT circuits using various logic families.

mented using different logic families.

114 Fourier Transforms - High-tech Application and Current Trends

in **Table 6**.

As mentioned earlier, each of the FFT unit takes in four inputs, each of which is 8‐bit long. **Figure 19** shows the 8th bit of the four inputs to a single FFT unit. The outputs of each FFT unit will be 10‐bit long. **Figure 20** shows the LSB of the outputs of FFT unit for inputs shown in **Figure 19**.

**Figure 19.** Eighth bit of the four inputs to a FFT unit.

**Figure 20.** LSB of the output of the FFT unit is shown as sum. Carry and Cout of the LSB are also shown.

### **7. Discussion**

In order to maintain practical relevance of the approach, all the results mentioned in the pre‐ vious section are based on device parameters from 90 nm TSMC process. HP memristor mod‐ els with *R* ON = 100 Ω and *R* OFF = 100 k Ω were used and all the simulations were carried out using LTSpice VI.

From the results shown in the previous section, it can be seen that the proposed logic family is clearly of advantage when we are trying to implement large input circuits. The comparison of propagation delay of the logic gates showed that the memristor‐based resis‐ tive threshold logic family can be used to implement brain‐like large input logic functions. Moreover, it gives a clear advantage in terms of the total harmonic distortion also. After the successful implementation of the new logic family, it was used to implement a circuit that could compute the fast Fourier transform of the given set of inputs. A four‐point FFT circuit was implemented. It can take in four inputs at a time and give four FFT outputs. The circuit can handle complex numbers and the complex inputs were separated into real and imaginary part for the easy computation. All the inputs considered in this project were 8‐bit long.

All the circuits and gates involved in the FFT circuit were implemented using the proposed memristor‐based resistive threshold logic family. The speed of operation of the circuit can be further increased and the area can be further reduced if low power and high speed op‐amp designs are developed, or an alternative thresholding circuit needs to be developed. If a bet‐ ter op‐amp can be developed, then the leakage power can also be reduced to a great extent. Moreover, in the proposed logic, we are not concentrating on the memory power of memristor. If we can use that property of memristor in our architecture to save the data, then we can imple‐ ment a memory unit also.

As a future work, the memory property of the memristor can be made use of using this prop‐ erty, a very efficient memory unit can be implemented. Since the area required for the mem‐ ristor is very small, a very compact and area‐efficient memory cell can be developed which can be used as an alternative for the existing memory cells. Also, only two‐state logic gates are considered in this project. But in the future, by making use of the memory property of the memristor, multi‐state logic functions can also be implemented. The op‐amps used in this project can be replaced by more efficient and smaller op‐amps, thereby, further reducing the area and leakage power and also increase the speed of operation of the circuit.
