4. PWM for multilevel inverters

In this section, the following MLI topologies are presented: diode-clamped (DC) MLI, cascade H-bridge (CHB) MLI, and capacitor-clamped (CC) MLI. The three-level diode-clamped inverter, which is also called the neutral-point-clamped inverter, was initially introduced by Nabae et al. [8] in 1981. Thereafter, diode-clamped, cascade H-bridge, and flying capacitor MLIs with higher number of DC voltage levels have been developed [9–11].

### 4.1. Diode-clamped MLI

from −Vdc to Vdc when x ¼ −πM cos y, from Vdc to −Vdc when x ¼ πM cos y.

3.1.2.2. Symmetrically regularly sampled PWM

124 Fourier Transforms - High-tech Application and Current Trends

in terms of continuous variables x and y is given by

from <sup>−</sup>Vdc to Vdc when <sup>x</sup> <sup>¼</sup> <sup>−</sup>π<sup>M</sup> cos <sup>y</sup>′

from Vdc to <sup>−</sup>Vdc when <sup>x</sup> <sup>¼</sup> <sup>π</sup><sup>M</sup> cos <sup>y</sup>′

3.1.2.3. Asymmetrically regularly sampled PWM

yi ′ <sup>¼</sup> <sup>ω</sup><sup>0</sup> ωc

yi ′ <sup>¼</sup> <sup>y</sup><sup>−</sup> ω0 ωc

which can be expressed in terms of continuous variables x and y as

changes

staircase variables

Switching instances for SR PWM can be determined by the intersection between the sampled sinusoid waveform and the solution trajectory line <sup>y</sup> <sup>¼</sup> <sup>y</sup>′ þ ðω0=ωcÞx. The same switching instances can be determined as the intersection between the continuous sinusoid waveform and a staircase variable y′ which has a constant value within each carrier interval [4]. In

where p represents the pth carrier interval within a fundamental cycle. The staircase variable y′

The double Fourier series coefficients for the case of SR PWM with a triangle carrier can be found analogously to NS PWM with variable y substituted by variable y′ found from Eq. (6).

Considering the previous example with the one-phase two-level inverter leg shown in Figure 1, switching time instances for the SR double-edge modulation are defined such that fðx, yÞ

Switching time instances for AR PWM are determined similarly to SR PWM. Unlike SR PWM, switching occurs twice within each carrier interval for AR PWM. The switching time instances can be determined as the intersection between the continuous sinusoid waveform and two

> i π 2

> > i π 2

2pπ þ ð−1Þ

x−2pπ−ð−1Þ

To write the double Fourier series integral for AR PWM, the switched waveform in each carrier interval must be split into two sections for analysis, and with the results added by

2pπ, p ¼ 0, 1, 2, … (5)

ðx−2pπÞ, p ¼ 0, 1, 2, …: (6)

, i ¼ 1, 2, (7)

, i ¼ 1, 2: (8)

general, the value of y′ within each carrier interval can be expressed as

<sup>y</sup>′ <sup>¼</sup> <sup>ω</sup><sup>0</sup> ωc

> ω0 ωc

> > ,

.

<sup>y</sup>′ <sup>¼</sup> <sup>y</sup><sup>−</sup>

### 4.1.1. DCMLI circuit topology

A three-level diode-clamped inverter is shown in Figure 4a. In this circuit, the DC bus voltage is split into three levels by two series-connected bulk capacitors, C<sup>1</sup> and C2. The middle point of the two capacitors n can be defined as a neutral point. The inverter has two complementary switch pairs: ðS1, S3Þ and ðS2, S4Þ; the complementary switches cannot be turned on simultaneously. The output voltage va has three states: −Vdc=2, 0, and Vdc=2. For voltage level Vdc=2, switches S<sup>1</sup> and S<sup>2</sup> should be turned on; for −Vdc=2, switches S<sup>3</sup> and S<sup>4</sup> should be turned on; and for the 0 level, switches S<sup>2</sup> and S<sup>3</sup> should be turned on.

Figure 4b shows a five-level diode-clamped converter whose DC bus consists of four capacitors: C1, C2, C3, and C4. Here, the output voltage va has five levels: −Vdc=2, −Vdc=4, 0, Vdc=4, and Vdc=2. In this example, four complementary switches are ðS1, S5Þ, ðS2, S6Þ, ðS3, S7Þ, and ðS4, S8Þ. For voltage level Vdc=2, all upper switches S<sup>1</sup> and S<sup>4</sup> should be turned on; for voltage level Vdc=4, three upper switches S<sup>2</sup> and S<sup>4</sup> and one lower switch should be turned on; for voltage level 0, two upper switches S<sup>3</sup> and S<sup>4</sup> and two lower switches S<sup>5</sup> and S<sup>6</sup> should be turned on; for voltage level −Vdc=4, one upper switch S<sup>4</sup> and three lower switches S<sup>5</sup> and S<sup>7</sup> should be turned on; and for voltage level −Vdc=2, all lower switches S<sup>5</sup> and S<sup>8</sup> should be turned on.

Figure 4. DCMLI circuit topologies: (a) three-level; (b) five-level.

Development of DCMLI of a higher level is constrained by diodes rating for reverse voltage blocking. The number of diodes increases quadratic in the level of inverter; therefore, construction of DCMLI beyond certain level will be impractical. Moreover, the diode recovery time is the major challenge in high-voltage high-power applications [12].

### 4.1.2. Carrier-based PWM schemes for DCMLIs

For DCMLIs, two or more carrier waveforms are used to modulate the target waveform. The number of waveforms depends on the level of the converter. Usually, the level of an inverter is an odd number, and if L is the level of the converter, then the number of carrier waveforms is L−1.

Carrier waveforms can be shifted with respect to each other. Based on the shift between the carrier waveforms, following modulation schemes are identified:


Figure 5. POD PWM scheme for a five-level inverter with the sinusoid reference waveform.

Figure 6. APOD PWM scheme for a five-level inverter with the sinusoid reference waveform.

Figure 7. PD PWM scheme for a five-level inverter with the sinusoid reference waveform.

An example of each PWM scheme for a five-level inverter is shown in Figures 5–7. Apparently, there is no difference between POD and APOD for three-level inverters.

### 4.1.3. Contour plots for DCMLIs

Development of DCMLI of a higher level is constrained by diodes rating for reverse voltage blocking. The number of diodes increases quadratic in the level of inverter; therefore, construction of DCMLI beyond certain level will be impractical. Moreover, the diode recovery time is

For DCMLIs, two or more carrier waveforms are used to modulate the target waveform. The number of waveforms depends on the level of the converter. Usually, the level of an inverter is an odd number, and if L is the level of the converter, then the number of carrier waveforms is

Carrier waveforms can be shifted with respect to each other. Based on the shift between the

• phase opposition disposition (POD): all carrier waveforms above zero are in phase and

• alternative phase opposition disposition (APOD): every carrier waveform is 180° out of

the major challenge in high-voltage high-power applications [12].

carrier waveforms, following modulation schemes are identified:

• phase disposition (PD): all carrier waveforms are in phase.

4.1.2. Carrier-based PWM schemes for DCMLIs

Figure 4. DCMLI circuit topologies: (a) three-level; (b) five-level.

126 Fourier Transforms - High-tech Application and Current Trends

180° out of phase with those below zero;

phase with its neighbors;

L−1.

If L is the level of the inverter, it denotes N ¼ ðL−1Þ=2. Then, function fðx, yÞ of voltage level assumes one of the values: −NVdc=ðL−1Þ, −ðN−1ÞVdc=ðL−1Þ, …, 0, …, NVdc=ðL−1Þ. Let us denote carrier waveforms as xc <sup>1</sup>ðtÞ, xc <sup>2</sup>ðtÞ, …, xc <sup>L</sup>−1ðtÞ beginning from the lowest one. If the reference waveform is less than xc <sup>1</sup>ðtÞ, then fðx, yÞ ¼ −NVdc=ðL−1Þ; if the reference waveform is greater than xc <sup>i</sup>−1ðt<sup>Þ</sup> and less than xc <sup>i</sup>ðtÞ, i ¼ 2, …, L−1, then fðx, yÞ ¼ −ðN−i þ 1ÞVdc=ðL−1Þ; and, finally, <sup>f</sup>ðx, <sup>y</sup>Þ ¼ NVdc=ðL−1<sup>Þ</sup> if the reference waveform is greater than xc <sup>L</sup>−1ðtÞ.

To determine the corresponding contour plot, interval ½−π; π� of the y-axis should be divided in 2N−1 intervals with limits defined by M cos y ¼ m=N, m ¼ −N, −ðN−1Þ, …, N. One also needs to consider separately "rising" and "falling" edges of each carrier waveform corresponding to two intervals of variable x: −π ≤ x ≤ 0 and 0 ≤ x ≤ π. Then, the condition that the reference waveform is greater than the carrier waveform xc <sup>i</sup>ðtÞ for "rising" and "falling" edges becomes, respectively:

$$\text{NM}\cos y > \frac{\mathfrak{x}\_i^{\varepsilon}}{\pi} \text{ if } 0 \le \mathfrak{x} \le \pi,\tag{9}$$

$$NM\cos y > -\frac{\mathcal{X}\_i^\varepsilon}{\pi} \text{ if } -\pi \le x \le 0. \tag{10}$$

Similarly, the opposite conditions can be defined. Solving in Eqs. (9) and (10) for all values of fðx, yÞ, one can find the contour plot of a particular PWM scheme, accounting for the voltage level in each domain. Examples of different PWM schemes for three- and five-level diodeclamped inverter are given in Figures 8–12.

Figure 8. PD PWM scheme for a three-level diode-clamped inverter.

Figure 9. POD PWM scheme for a three-level diode-clamped inverter.

To determine the corresponding contour plot, interval ½−π; π� of the y-axis should be divided in 2N−1 intervals with limits defined by M cos y ¼ m=N, m ¼ −N, −ðN−1Þ, …, N. One also needs to consider separately "rising" and "falling" edges of each carrier waveform corresponding to two intervals of variable x: −π ≤ x ≤ 0 and 0 ≤ x ≤ π. Then, the condition that

> xc i π

> > xc i π

Similarly, the opposite conditions can be defined. Solving in Eqs. (9) and (10) for all values of fðx, yÞ, one can find the contour plot of a particular PWM scheme, accounting for the voltage level in each domain. Examples of different PWM schemes for three- and five-level diode-

<sup>i</sup>ðtÞ for "rising" and "falling"

if 0 ≤ x ≤ π, (9)

if −π ≤ x ≤ 0: (10)

the reference waveform is greater than the carrier waveform xc

NM cos y >

NM cos y > −

edges becomes, respectively:

clamped inverter are given in Figures 8–12.

128 Fourier Transforms - High-tech Application and Current Trends

Figure 9. POD PWM scheme for a three-level diode-clamped inverter.

Figure 8. PD PWM scheme for a three-level diode-clamped inverter.

Figure 10. PD PWM scheme for a five-level diode-clamped inverter (here <sup>φ</sup><sup>2</sup> <sup>¼</sup> <sup>π</sup>−φ<sup>1</sup> and <sup>φ</sup><sup>1</sup> <sup>¼</sup> cos <sup>−</sup><sup>1</sup>ð1=2MÞ).

Figure 11. POD PWM scheme for a five-level diode-clamped inverter (here <sup>φ</sup><sup>2</sup> <sup>¼</sup> <sup>π</sup>−φ<sup>1</sup> and <sup>φ</sup><sup>1</sup> <sup>¼</sup> cos <sup>−</sup><sup>1</sup>ð1=2MÞ).

Figure 12. APOD PWM scheme for a five-level diode-clamped inverter (here <sup>φ</sup><sup>2</sup> <sup>¼</sup> <sup>π</sup>−φ<sup>1</sup> and <sup>φ</sup><sup>1</sup> <sup>¼</sup> cos <sup>−</sup><sup>1</sup>ð1=2MÞ).

### 4.1.4. Harmonic spectra of DCMLIs

Once the unit cell with contour plots of voltage level domains for a particular PWM is obtained, harmonic components of the PWM can be found using Eq. (2) with the help of equations given in Section 2.2. Output voltage waveforms and their Fourier transforms are given below for three- and five-level diode-clamped inverters using different modulation strategies. Harmonic components magnitudes are plotted for first harmonic numbers assuming M ¼ 0:8 and ωc=ω<sup>0</sup> ¼ 40.

The output voltage of a three-level diode-clamped inverter modulated by NS POD/APOD PWM is given by

$$w\_a(t) = V\_{dc}M\cos\left(\omega\_0 t\right) + \frac{2V\_{dc}}{\pi} \sum\_{m=1}^{\circ} \frac{1}{m} \sum\_{p=-\infty}^{\circ} (-1)^p I\_{2p+1}(m\pi M)\cos\left(m\omega\_c t + (2p+1)\omega\_0 t\right) \tag{11}$$

and its harmonic components are plotted in Figure 13.

Figure 13. Theoretical harmonic spectrum of a three-level diode-clamped inverter modulated using NS POD/APOD PWM.

The output voltage of a three-level diode-clamped inverter modulated using NS PD PWM can be calculated as

$$\begin{split} v(t)a &= V\_{dc}M\cos\left(\omega\_{0}t\right) + \frac{2V\_{dc}}{\pi} \sum\_{q=1}^{\infty} \frac{1}{2q} \sum\_{p=-\infty}^{\infty} \frac{I\_{2p+1}(2q\pi M)(-1)^{p}}{2s+1} \cos\left(2q\omega\_{c}t + (2p+1)a\omega\_{0}t\right) + \\ &+ \frac{4V\_{dc}}{\pi^{2}} \sum\_{q=1}^{\infty} \frac{1}{2q-1} \sum\_{p=-\infty}^{\infty} \sum\_{s=-\infty}^{\infty} \frac{I\_{2s+1}((2q-1)\pi M)(-1)^{p}}{2p+2s+1} \cos\left((2q-1)a\omega\_{c}t + 2p\omega\_{0}t\right) \end{split} \tag{12}$$

and its theoretical harmonic spectrum is shown in Figure 14.

The output voltage of a five-level diode-clamped inverter obtained by NS POD PWM can be found as follows:

Figure 14. Theoretical harmonic spectrum of a three-level diode-clamped inverter modulated using NS PD PWM.

$$\begin{split} v\_{a}(t) &= 2V\_{dc}M\cos\left(\omega\_{0}t\right) + \frac{2V\_{dc}}{\pi} \sum\_{q=1}^{\infty} \frac{1}{2q\_{p}} \sum\_{s=-\infty}^{\infty} (-1)^{p} I\_{2p+1}(4\eta\pi M) \cos\left(2q\omega\_{c}t + (2p+1)a\_{0}t\right) + \\ &+ \frac{4V\_{dc}}{\pi^{2}} \sum\_{q=1}^{\infty} \frac{1}{2q-1} \sum\_{p=-\infty}^{\infty} \left[ \begin{matrix} (-1)^{p} I\_{2p+1}(2(2q-1)\pi M) \left(\frac{\pi}{2} - 2\phi\right) \\ + \sum\_{s=-\infty}^{\infty} (-1)^{s+1} I\_{2s+1}(2(2q-1)\pi M) \frac{\sin\left(2(p+s+1)\phi\right)}{p+s+1} \end{matrix} \right], \end{split} \tag{13}$$

where <sup>φ</sup> <sup>¼</sup> cos <sup>−</sup><sup>1</sup>ð1=2M<sup>Þ</sup> and its harmonic spectrum is plotted in Figure 15.

The output voltage of a five-level diode-clamped inverter modulated by NS APOD PWM is given by

$$\upsilon\_a(t) = 2V\_{dc}M\cos\left(\omega\_0 t\right) + \frac{2V\_{dc}}{\pi} \sum\_{m=1}^{\infty} \frac{1}{m} \sum\_{p=-m}^{\infty} (-1)^{m+p} f\_{2p+1}(2m\pi M) \cos\left(m\omega\_c t + (2p+1)\omega\_0 t\right) \tag{14}$$

and its harmonics are plotted in Figure 16.

4.1.4. Harmonic spectra of DCMLIs

130 Fourier Transforms - High-tech Application and Current Trends

ing M ¼ 0:8 and ωc=ω<sup>0</sup> ¼ 40.

vaðtÞ ¼ VdcM cos <sup>ð</sup>ω0tÞ þ <sup>2</sup>Vdc

π ∑ ∞ m¼1

and its harmonic components are plotted in Figure 13.

1 m ∑ ∞ p¼−∞ ð−1Þ p

PWM is given by

be calculated as

PWM.

þ 4Vdc <sup>π</sup><sup>2</sup> <sup>∑</sup> ∞ q¼1

found as follows:

<sup>v</sup>ðtÞ<sup>a</sup> <sup>¼</sup> VdcM cos <sup>ð</sup>ω0tÞ þ <sup>2</sup>Vdc

1 <sup>2</sup>q−<sup>1</sup> <sup>∑</sup> ∞ p¼−∞

π ∑ ∞ q¼1

and its theoretical harmonic spectrum is shown in Figure 14.

∑ ∞ s¼−∞

1 2q ∑ ∞ p¼−∞

Once the unit cell with contour plots of voltage level domains for a particular PWM is obtained, harmonic components of the PWM can be found using Eq. (2) with the help of equations given in Section 2.2. Output voltage waveforms and their Fourier transforms are given below for three- and five-level diode-clamped inverters using different modulation strategies. Harmonic components magnitudes are plotted for first harmonic numbers assum-

The output voltage of a three-level diode-clamped inverter modulated by NS POD/APOD

The output voltage of a three-level diode-clamped inverter modulated using NS PD PWM can

Figure 13. Theoretical harmonic spectrum of a three-level diode-clamped inverter modulated using NS POD/APOD

<sup>J</sup>2sþ<sup>1</sup>ðð2q−1ÞπMÞð−1<sup>Þ</sup>

The output voltage of a five-level diode-clamped inverter obtained by NS POD PWM can be

<sup>J</sup>2pþ<sup>1</sup>ð2qπMÞð−1<sup>Þ</sup>

p

p

<sup>2</sup><sup>p</sup> <sup>þ</sup> <sup>2</sup><sup>s</sup> <sup>þ</sup> <sup>1</sup> cos ðð2q−1Þωct <sup>þ</sup> <sup>2</sup>pω0t<sup>Þ</sup>

<sup>2</sup><sup>s</sup> <sup>þ</sup> <sup>1</sup> cos <sup>ð</sup>2qωct þ ð2<sup>p</sup> <sup>þ</sup> <sup>1</sup>Þω0tÞþ

(12)

J2pþ<sup>1</sup>ðmπMÞ cos ðmωct þ ð2p þ 1Þω0tÞ (11)

Figure 15. Theoretical harmonics spectrum of a five-level diode-clamped inverter modulated using NS POD PWM.

Figure 16. Theoretical harmonic spectrum of a five-level diode-clamped inverter modulated using NS APOD PWM.

The output voltage of a five-level diode-clamped inverter modulated using NS PD PWM is given by

$$\begin{split} \upsilon\_{a}(t) &= 2V\_{dc}M\cos\left(\omega\_{0}t\right) + \frac{2V\_{dc}}{\pi} \sum\_{q=1}^{\infty} \frac{1}{2q} \sum\_{p=-\infty}^{\infty} (-1)^{p} I\_{2p+1}(4q\pi M) \cos\left(2q\omega\_{c}t + (2p+1)\omega\_{0}t\right) + \\ &+ \frac{4V\_{dc}}{\pi^{2}} \sum\_{q=1}^{\infty} \frac{1}{2q-1} \sum\_{p=-\infty}^{\infty} \sum\_{\substack{q=-\infty \\ 2p+2s+1}}^{\infty} (-1)^{s} I\_{2s+1}(2(2q-1)\pi M) \frac{\cos\left(\pi(p+s)\right) - 2\sin\left(\phi(2p+2s+1)\right)}{2p+2s+1} \\ &\times \cos\left((2q-1)\omega\_{c}t + 2p\omega\_{0}t\right) \end{split} \tag{15}$$

where <sup>φ</sup> <sup>¼</sup> cos <sup>−</sup><sup>1</sup>ð1=2M<sup>Þ</sup> and the theoretical harmonics spectrum is shown in Figure 17.

Figure 17. Theoretical harmonic spectrum of a five-level diode-clamped inverter modulated using NS PD PWM.

Below theoretical harmonic contents for SR and AR PWM are presented for a three-level diode-clamped inverter. The output voltage of a three-level diode-clamped inverter modulated with SR POD PWM can be found using

Application of Fourier Series Expansion to Electrical Power Conversion http://dx.doi.org/10.5772/66581 133

$$\mathbb{C}\_{m,2n+1} = \frac{2V\_{dc}}{q\pi}(-1)^n l\_{2n+1}(q\pi M) \tag{16}$$

where q ¼ m þ nω0=ωc. Its harmonics content is shown in Figure 18.

The harmonic spectrum of a three-level diode-clamped inverter modulated with SR PD PWM can be determined by equations

$$\mathcal{C}\_{m,2p} = \frac{2V\_{dc}}{\pi^2} \frac{1 - e^{i\eta \pi}}{\eta} \sum\_{k=-\infty}^{\infty} (-1)^p \frac{I\_{2k+1}(q\pi M)}{2p + 2k + 1} \tag{17}$$

$$\mathbf{C}\_{m,2p+1} = \frac{V\_{dc}}{\pi} \frac{1 + e^{i\eta n}}{q} (-1)^p I\_{2p+1}(q\pi M) \tag{18}$$

where q ¼ m þ nω0=ωc. First harmonics are plotted in Figure 19.

The output voltage of a five-level diode-clamped inverter modulated using NS PD PWM is

Figure 16. Theoretical harmonic spectrum of a five-level diode-clamped inverter modulated using NS APOD PWM.

<sup>J</sup>2sþ<sup>1</sup>ð2ð2q−1ÞπM<sup>Þ</sup>

where <sup>φ</sup> <sup>¼</sup> cos <sup>−</sup><sup>1</sup>ð1=2M<sup>Þ</sup> and the theoretical harmonics spectrum is shown in Figure 17.

Below theoretical harmonic contents for SR and AR PWM are presented for a three-level diode-clamped inverter. The output voltage of a three-level diode-clamped inverter modulated

Figure 17. Theoretical harmonic spectrum of a five-level diode-clamped inverter modulated using NS PD PWM.

cos 

· cos ðð2q−1Þωct þ 2pω0tÞ (15)

J2pþ<sup>1</sup>ð4qπMÞ cos ð2qωct þ ð2p þ 1Þω0tÞþ

2p þ 2s þ 1

−2 sin ðφð2p þ 2s þ 1ÞÞ

πðp þ sÞ

given by

þ 4Vdc <sup>π</sup><sup>2</sup> <sup>∑</sup> ∞ q¼1

vaðtÞ ¼ <sup>2</sup>VdcM cos <sup>ð</sup>ω0tÞ þ <sup>2</sup>Vdc

132 Fourier Transforms - High-tech Application and Current Trends

1 <sup>2</sup>q−<sup>1</sup> <sup>∑</sup> ∞ p¼−∞

with SR POD PWM can be found using

π ∑ ∞ q¼1

> ð−1Þ s

∑ ∞

<sup>s</sup> <sup>¼</sup> <sup>−</sup><sup>∞</sup> <sup>2</sup>pþ2s≠−<sup>1</sup>

1 2q ∑ ∞ p¼−∞ ð−1Þ p

Figure 18. Theoretical harmonic spectrum of a three-level diode-clamped inverter modulated using SR POD PWM.

Figure 19. Theoretical harmonic spectrum of a three-level diode-clamped inverter modulated using SR PD PWM.

The harmonic spectrum of a three-level diode-clamped inverter modulated with AR POD PWM can be determined by equations

$$\mathbf{C}\_{\text{mu}} = \frac{2V\_{dc}(1 - e^{j\pi\eta})}{\pi^2 \eta} \begin{bmatrix} \frac{1}{n} \sin\left(n \frac{\pi a\_0}{2\alpha\_c}\right) \sin\left(n \frac{\pi}{2}\right) + \frac{\pi}{2}I\_n(q\pi M)\sin\left(n \frac{\pi}{2} \left[1 - \frac{a\nu\_0}{\omega\_c}\right]\right) + \\\ + \sum\_{\substack{k = -\alpha \\ n + k \neq 0}} \frac{1}{n+k}I\_k(q\pi M)\sin\left(\frac{\pi}{2} \left[k \cdot n \frac{\omega\_0}{\omega\_c}\right]\right) \sin\left((n+k)\frac{\pi}{2}\right) \end{bmatrix} \tag{19}$$

where q ¼ m þ nω0=ω<sup>c</sup> and n is odd. A series of lower order harmonics are shown in Figure 20.

Figure 20. Theoretical harmonic spectrum of a three-level diode-clamped inverter modulated using AR POD PWM.

The harmonic spectrum of a three-level diode-clamped inverter modulated with AR PD PWM can be found using equations

$$\mathbb{C}\_{m0} = \frac{2V\_{dc}}{\pi^2 q} \sum\_{s=-\infty}^{\infty} \frac{I\_{2s+1}(q\pi M)}{2s+1} \binom{\pi\nu M}{1-e^{i(q+2s)\pi}} \tag{20}$$

$$\mathbb{C}\_{\text{unu}} = \frac{2V\_{dc}(1+e^{i\eta\pi})}{\pi^2 q} \left[ \frac{1}{n} \sin\left(n\frac{\pi}{2}\frac{a\_0}{\omega\_c}\right) \sin\left(n\frac{\pi}{2}\right) + (-1)^{n+1} \frac{\pi}{2} I\_n(q\pi M) \sin\left(n\frac{\pi}{2}\left[1+\frac{a\_0}{a\_c}\right]\right) \right]$$

$$+ \sum\_{k=-\infty}^{\infty} \frac{(-1)^{k+1}}{n+k} J\_k(q\pi M) \sin\left([n+k]\frac{\pi}{2}\right) \sin\left(\frac{\pi}{2}\left[k+n\frac{a\_0}{\omega\_c}\right]\right) \tag{21}$$

where q ¼ m þ nω0=ω<sup>c</sup> and n is odd in Eq. (21). A series of lower order harmonics are shown in Figure 21.

### 4.2. Cascaded H-Bridge MLI

### 4.2.1. CHBMLI circuit topology

A single-phase H-bridge inverter is shown in Figure 22. It is made up of two single-phase inverter legs (Figure 1) connected to a common DC bus. Each phase is modulated in complementary pattern by a carrier/reference waveform comparison when the switching occurs as it is described above. A single-phase full-bridge inverter generates voltage of three levels: −Vdc, 0, and Vdc:

Figure 21. Theoretical harmonic spectrum of a three-level diode-clamped inverter modulated using AR PD PWM.

Figure 22. A single-phase H-bridge (full-bridge) inverter.

The harmonic spectrum of a three-level diode-clamped inverter modulated with AR POD

JkðqπM<sup>Þ</sup> sin <sup>π</sup>

where q ¼ m þ nω0=ω<sup>c</sup> and n is odd. A series of lower order harmonics are shown in Figure 20.

The harmonic spectrum of a three-level diode-clamped inverter modulated with AR PD PWM

Figure 20. Theoretical harmonic spectrum of a three-level diode-clamped inverter modulated using AR POD PWM.

J2sþ<sup>1</sup>ðqπMÞ 2s þ 1

<sup>n</sup> <sup>þ</sup> <sup>k</sup> JkðqπM<sup>Þ</sup> sin <sup>½</sup><sup>n</sup> <sup>þ</sup> <sup>k</sup>�

where q ¼ m þ nω0=ω<sup>c</sup> and n is odd in Eq. (21). A series of lower order harmonics are shown in

A single-phase H-bridge inverter is shown in Figure 22. It is made up of two single-phase inverter legs (Figure 1) connected to a common DC bus. Each phase is modulated in complementary

sin n π 2 � � � 1−e jðqþ2sÞπ �

<sup>n</sup>þ<sup>1</sup> π

π 2 � �

<sup>2</sup> JnðqπM<sup>Þ</sup> sin <sup>n</sup>

sin <sup>π</sup>

π <sup>2</sup> <sup>1</sup> <sup>þ</sup>

� � � �

<sup>2</sup> <sup>k</sup> <sup>þ</sup> <sup>n</sup>

ω0 ωc

� � � �

ω0 ωc

þ ð−1Þ

<sup>2</sup> JnðqπM<sup>Þ</sup> sin <sup>n</sup>

ω0 ωc � � � �

<sup>2</sup> <sup>k</sup>−<sup>n</sup>

π <sup>2</sup> <sup>1</sup><sup>−</sup> ω0 ωc � � � �

sin ðn þ kÞ

þ

(19)

(20)

(21)

π 2 � �

sin n π 2 � � þ π

PWM can be determined by equations

134 Fourier Transforms - High-tech Application and Current Trends

1 n sin n

þ ∑ ∞

<sup>k</sup>¼−<sup>∞</sup> <sup>n</sup>þk≠<sup>0</sup>

Cm<sup>0</sup> <sup>¼</sup> <sup>2</sup>Vdc π<sup>2</sup>q ∑ ∞ s¼−∞

> ð−1Þ kþ1

1 n sin n π 2 ω0 ωc � �

þ ∑ ∞ k¼−∞ k≠−n

πω<sup>0</sup> 2ω<sup>c</sup> � �

> 1 n þ k

Cmn <sup>¼</sup> <sup>2</sup>Vdcð1−ejn<sup>π</sup><sup>Þ</sup> π<sup>2</sup>q

can be found using equations

Cmn <sup>¼</sup> <sup>2</sup>Vdcð<sup>1</sup> <sup>þ</sup> ejq<sup>π</sup><sup>Þ</sup> π<sup>2</sup>q

4.2. Cascaded H-Bridge MLI 4.2.1. CHBMLI circuit topology

Figure 21.

A cascaded H-bridge multilevel inverter, also called cascaded multicell inverters [12], consists of a number of series-connected single-phase H-bridge inverters connected to separate dc voltage sources. The resulting phase voltage is synthesized by addition of the voltages generated by different cells and is nearly sinusoidal even without filtering. An example of a fivelevel cascaded H-bridge inverter is shown in Figure 23.

Cascaded MLI topology has several advantages: each cell can be controlled independently from the others. Although communication between cells is required to achieve synchronized reference and carrier waveforms, controllers can be distributed. The control scheme is significantly easier than the ones for other topologies. However, it has not been used in practice in low power applications because a separate isolated dc voltage supply is needed for each full H-bridge [4].

Figure 23. A five-level cascaded H-bridge inverter topology.

### 4.2.2. Carrier-based PWM schemes for CBHMLIs

Three-level modulation of a single-phase full-bridge inverter can be obtained via combination of voltage modulations of two phase legs a and b. The phase legs are modulated with 180 opposed reference waveforms given by

$$v\_a^{id}(t) = \frac{V\_{dc}}{2} M \cos y,\tag{22}$$

$$v\_b^{id}(t) = \frac{V\_{dc}}{2} M \cos\left(y \cdot \pi\right). \tag{23}$$

The fundamental line-to-line (l-l) output reference voltage for the inverter is the difference between two phase reference voltages and is equal to

$$
\upsilon\_{ab}^{id}(t) = \upsilon\_a^{id}(t) \neg \upsilon\_b^{id}(t) = V\_{dc}M \cos y. \tag{24}
$$

Then, the l-l output voltage harmonic components for the inverter are given by

$$
\upsilon\_{ab}(t) = \upsilon\_a(t) \neg \upsilon\_b(t). \tag{25}
$$

Applying different PWM schemes to a single-phase half-bridge inverter, one can obtain various modulations for the full-bridge inverter: NS, SR, and AR.

### 4.2.3. Harmonic spectra of CHBMLIs

The harmonic solution for NS PWM of a phase leg is given by

$$v\_a(t) = \frac{V\_{dc}}{2} + \frac{V\_{dc}}{2}M\cos\left(\omega\_0 t\right) + \frac{2V\_{dc}}{\pi} \sum\_{m=1}^{\infty} \frac{1}{m} \sum\_{n=-\infty}^{\infty} J\_n\left(m\frac{\pi}{2}M\right) \sin\left([m+n]\frac{\pi}{2}\right) \cos\left(m\omega\_c t + n\omega\_0 t\right). \tag{26}$$

Eq. (26) can be applied for each phase leg accounting for 180° phase shift of the reference waveforms resulting in the following harmonic spectrum for NS PWM of a full-bridge inverter:

$$\left(\upsilon\_{ab}^{NS}(t) = V\_{dc}M\cos\left(\omega\_0 t\right) + \frac{4V\_{dc}}{\pi} \sum\_{m=1}^{\bullet} \frac{1}{2m} \sum\_{n=-\bullet}^{\bullet} I\_{2n+1}(2m\pi M)\cos\left([m+n]\pi\right)\cos\left(2m\omega\_{\ell}t + [2n+1]\omega\_0 t\right). \tag{27}$$

The harmonic spectrum of the output voltage of a full-bridge inverter modulated using SR PWM is equal to

$$\begin{split} \upsilon\_{ab}^{SR} (t) &= \frac{4V\_{dc}}{\pi} \left[ \sum\_{n=1}^{\infty} \frac{I\_n \left( n \frac{\omega\_0}{\omega\_c} \frac{\pi}{2} M \right)}{n \frac{\omega\_0}{\omega\_c}} \sin \left( n \left[ 1 + \frac{\omega\_0}{\omega\_c} \right] \frac{\pi}{2} \right) |\sin n\frac{\pi}{2}| \cos \left( n\omega\_0 t \right) \\ &+ \sum\_{m=1}^{\infty} \sum\_{n=-m}^{\infty} \frac{I\_n \left( \left[ m + n \frac{\omega\_0}{\omega\_c} \right] \frac{\pi}{2} M \right)}{m + n \frac{\omega\_0}{\omega\_c}} \sin \left( \left[ m + n + n \frac{\omega\_0}{\omega\_c} \right] \frac{\pi}{2} \right) |\sin n\frac{\pi}{2}| \cos \left( m\omega\_c t + m\omega\_0 t \right) \right] \end{split} \tag{28}$$

and using AR PWM it is given by

4.2.2. Carrier-based PWM schemes for CBHMLIs

Figure 23. A five-level cascaded H-bridge inverter topology.

136 Fourier Transforms - High-tech Application and Current Trends

between two phase reference voltages and is equal to

vid abðtÞ ¼ vid

opposed reference waveforms given by

Three-level modulation of a single-phase full-bridge inverter can be obtained via combination of voltage modulations of two phase legs a and b. The phase legs are modulated with 180

The fundamental line-to-line (l-l) output reference voltage for the inverter is the difference

<sup>2</sup> <sup>M</sup> cos <sup>y</sup>, (22)

<sup>2</sup> <sup>M</sup> cos <sup>ð</sup>y−πÞ: (23)

<sup>b</sup> ðtÞ ¼ VdcM cos y: (24)

vid

vid

<sup>a</sup> <sup>ð</sup>tÞ ¼ Vdc

<sup>a</sup> <sup>ð</sup>tÞ−vid

Then, the l-l output voltage harmonic components for the inverter are given by

<sup>b</sup> <sup>ð</sup>tÞ ¼ Vdc

$$v\_{ab}^{AR}(t) = \frac{4V\_{dc}}{\pi} \left[ \sum\_{n=1}^{\infty} \frac{J\_n\left(n\frac{a\upsilon}{\omega\_c}\frac{\pi}{2}M\right)}{n\frac{a\upsilon}{\omega\_c}} \sin\left(n\frac{\pi}{2}\right) \cos\left(n\omega\_0 t\right) \right. $$

$$+ \sum\_{m=1}^{\infty} \sum\_{n=-\infty}^{\infty} \frac{J\_{2n-1}\left(\left[m + n\frac{a\upsilon}{\omega\_c}\right]\frac{\pi}{2}M\right)}{m + n\frac{a\upsilon}{\omega\_c}} \sin\left(\left[m + n\right]\frac{\pi}{2}\right) |\sin n\frac{\pi}{2}| \cos\left(m\omega\_c t + n\omega\_0 t\right) \right]. \tag{29}$$

It can be seen that all odd carrier and associated sideband harmonics as well as even sideband harmonics are cancelled out from the l-l output voltage. A further cancellation can be obtained by appropriately phase shifting the remaining harmonics of several seriesconnected single-phase H-bridges. This process is called phase-shifted cascaded (PSC) PWM. The major principle is that the phase shift between two phases of each H-bridge cell is kept 180°, and then, carriers of each H-bridge are shifted with respect to each other. Optimum harmonic cancellation is achieved via phase shifting each carrier by ði−1Þπ=N, where i is the ith converter, N is the number of series-connected single-phase inverter legs, and N ¼ ðL−1Þ=2 and L is the number of voltage levels that can be achieved. This modulation is also called phase shift (PS) PWM. The overall cascaded inverter phase leg to dc link midpoint voltage can be obtained by adding up the l-l output reference voltages of each cell:

$$
\sigma(t) = \sum\_{i=1}^{N} \sigma\_{ab}^{i}(t). \tag{30}
$$

One can see in Figures 24–32 that carrier harmonics of odd order and even order sideband harmonics are cancelled out in the three-level CHB inverter for all presented topologies, and increasing the level of the inverter is leading to cancelling out other carrier harmonics of order m≠kN, k ¼ 1, 2, 3, :::

Figure 24. Theoretical harmonic spectrum of a single-phase half-bridge inverter modulated using NS PS PWM.

Figure 25. Theoretical harmonic spectrum of a single-phase full-bridge inverter modulated using NS PS PWM.

cell is kept 180°, and then, carriers of each H-bridge are shifted with respect to each other. Optimum harmonic cancellation is achieved via phase shifting each carrier by ði−1Þπ=N, where i is the ith converter, N is the number of series-connected single-phase inverter legs, and N ¼ ðL−1Þ=2 and L is the number of voltage levels that can be achieved. This modulation is also called phase shift (PS) PWM. The overall cascaded inverter phase leg to dc link midpoint voltage can be obtained by adding up the l-l output reference voltages of

> vðtÞ ¼ ∑ N i¼1 vi

Figure 24. Theoretical harmonic spectrum of a single-phase half-bridge inverter modulated using NS PS PWM.

Figure 25. Theoretical harmonic spectrum of a single-phase full-bridge inverter modulated using NS PS PWM.

One can see in Figures 24–32 that carrier harmonics of odd order and even order sideband harmonics are cancelled out in the three-level CHB inverter for all presented topologies, and increasing the level of the inverter is leading to cancelling out other carrier harmonics of order

abðtÞ: (30)

each cell:

138 Fourier Transforms - High-tech Application and Current Trends

m≠kN, k ¼ 1, 2, 3, :::

Figure 26. Theoretical harmonic spectrum of a single-phase cascaded H-bridge inverter modulated using NS PS PWM.

Figure 27. Theoretical harmonic spectrum of a single-phase half-bridge inverter modulated using SR PS PWM.

Figure 28. Theoretical harmonic spectrum of a single-phase full-bridge inverter modulated using SR PS PWM.

Figure 29. Theoretical harmonic spectrum of a single-phase cascaded H-bridge inverter modulated using SR PS PWM.

Figure 30. Theoretical harmonic spectrum of a single-phase half-bridge inverter modulated using AR PS PWM.

Figure 31. Theoretical harmonic spectrum of a single-phase full-bridge inverter modulated using AR PS PWM.

Figure 32. Theoretical harmonic spectrum of a single-phase half-bridge inverter modulated using AR PS PWM.

### 5. Harmonic distortion

Figure 29. Theoretical harmonic spectrum of a single-phase cascaded H-bridge inverter modulated using SR PS PWM.

140 Fourier Transforms - High-tech Application and Current Trends

Figure 30. Theoretical harmonic spectrum of a single-phase half-bridge inverter modulated using AR PS PWM.

Figure 31. Theoretical harmonic spectrum of a single-phase full-bridge inverter modulated using AR PS PWM.

Modern power electronic equipment operates in different discrete modes which causes a deviation of the output waveform from the desirable sine waveform due to insertion of undesirable harmonics. The rate of the deviation is presented by a number of basic indices characterizing the harmonic distortion. In particular, these indices enable us to compare the effectiveness of various inverter modulation algorithms. The indices are introduced in this section, and different inverter topologies are compared in their terms.

### 5.1. Harmonic distortion indices

Given that the output voltage vðtÞ of a power converter is a periodic function with period T, the root-mean-square (RMS) value of the function is defined by

$$V\_{rms} = \sqrt{\frac{1}{T} \int\_0^T v(t)^2 \, dt}. \tag{31}$$

Since <sup>v</sup>ðt<sup>Þ</sup> is periodic with the Fourier series <sup>v</sup>ðtÞ ¼ <sup>V</sup><sup>0</sup> <sup>þ</sup> <sup>∑</sup><sup>∞</sup> <sup>n</sup>¼<sup>1</sup>Vn cos <sup>ð</sup>nω<sup>t</sup> <sup>þ</sup> <sup>ϕ</sup>nÞ, the Parseval'<sup>s</sup> theorem can be used to find the RMS voltage of vðtÞ:

$$V\_{rms} = \sqrt{V\_0^2 + \sum\_{n=1}^{\infty} \frac{V\_n^2}{2}}.\tag{32}$$

In most of the practical cases, the fundamental harmonic V<sup>1</sup> can be considered as the desired output voltage. The reminder of this expression is then considered as a "distortion" to the output. Factoring out V<sup>1</sup> gives us

$$V\_{rms} = V\_{1,rms}\sqrt{1 + \frac{2V\_0^2}{V\_1^2} + \sum\_{n=2}^{\infty} \left(\frac{V\_n}{V\_1}\right)^2},\tag{33}$$

where <sup>V</sup>1,rms <sup>¼</sup> <sup>V</sup>1<sup>=</sup> ffiffiffi 2 <sup>p</sup> . The total harmonic distortion (THD) of the voltage is defined as

$$THD = \sqrt{\frac{2V\_0^2}{V\_1^2} + \sum\_{n=2}^{\circ} \left(\frac{V\_n}{V\_1}\right)^2} \tag{34}$$

and the RMS voltage becomes

$$V\_{rms} = V\_{1,rms}\sqrt{1 + THD^2}.\tag{35}$$

For the purpose of comparing various switching strategies, the weighted total harmonic distortion (WTHD) is used:

$$WTHD = \frac{1}{V\_1} \sqrt{\sum\_{n=2}^{\infty} \left(\frac{V\_n}{n}\right)^2} \tag{36}$$

In the case of pulse-width-modulated inverters, the DC voltage remains constant, while the fundamental component varies. On the other hand, for the same ratio of switching to output frequency, the harmonic components vary relatively little, resulting in a large variation of THD and WTHD. Therefore, a normalized WTHD can be used. For the case of half-bridge inverter, the normalization factor is chosen to be the value of the fundamental ac voltage when the modulation index M equals 1, that is, Vdc. Thus, the normalized WTHD, WTHD0, becomes

$$WTHD0 = \sqrt{\sum\_{n=2}^{n} \frac{1}{n^2} \left(\frac{V\_n}{V\_{dc}}\right)^2} = WTHD\frac{V\_1}{V\_{dc}} = WTHD \cdot M. \tag{37}$$

### 5.2. Harmonic distortion indices for a DCMLI

Harmonic distortion indices for all presented inverter topologies and PWMs are provided in Table 1. Spectra are evaluated for M ¼ 0:8 and ωc=ω<sup>0</sup> ¼ 40. It can be noted that a half-bridge inverters and full-bridge inverters demonstrate similar waveform quality regardless the PWM strategy applied. Cascaded H-bridge inverters show improvement in performance with increase in number of levels, which appears due to extensive harmonics cancelations up to harmonics of a high order. Performance of diode-clamped inverters also improves with increasing number of levels; however, the improvement is significantly lower than for the cascaded H-bridge inverters.

There is a substantial difference between different modulations used for the same converter. For example, AR PD is showing the worst performance among all other carrier-based


modulations of a three-level DC inverter which can be explained by the fact that very few harmonics are cancelled unlike the other modulations.

Table 1. Harmonic distortion factors for MLI.

## 6. Conclusion

Vrms ¼ V1,rms

THD ¼

Vrms ¼ V1,rms

WTHD <sup>¼</sup> <sup>1</sup>

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

Vn Vdc � �<sup>2</sup>

Harmonic distortion indices for all presented inverter topologies and PWMs are provided in Table 1. Spectra are evaluated for M ¼ 0:8 and ωc=ω<sup>0</sup> ¼ 40. It can be noted that a half-bridge inverters and full-bridge inverters demonstrate similar waveform quality regardless the PWM strategy applied. Cascaded H-bridge inverters show improvement in performance with increase in number of levels, which appears due to extensive harmonics cancelations up to harmonics of a high order. Performance of diode-clamped inverters also improves with increasing number of levels; however, the improvement is significantly lower than for the

There is a substantial difference between different modulations used for the same converter. For example, AR PD is showing the worst performance among all other carrier-based

1 n2

∑ ∞ n¼2

s

where <sup>V</sup>1,rms <sup>¼</sup> <sup>V</sup>1<sup>=</sup> ffiffiffi

(WTHD) is used:

becomes

and the RMS voltage becomes

2

142 Fourier Transforms - High-tech Application and Current Trends

WTHD0 ¼

5.2. Harmonic distortion indices for a DCMLI

cascaded H-bridge inverters.

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

� �<sup>2</sup> <sup>s</sup>

<sup>p</sup> . The total harmonic distortion (THD) of the voltage is defined as

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi

� �<sup>2</sup> <sup>s</sup>

Vn V1

ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi <sup>1</sup> <sup>þ</sup> THD<sup>2</sup> <sup>p</sup>

> ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi ∑ ∞ n¼2

<sup>¼</sup> WTHD <sup>V</sup><sup>1</sup>

Vdc

Vn n � �<sup>2</sup>

Vn V1

, (33)

: (35)

¼ WTHD � M: (37)

(34)

(36)

1 þ 2V<sup>2</sup> 0 V2 1 þ ∑ ∞ n¼2

2V<sup>2</sup> 0 V2 1 þ ∑ ∞ n¼2

For the purpose of comparing various switching strategies, the weighted total harmonic distortion

s

V1

In the case of pulse-width-modulated inverters, the DC voltage remains constant, while the fundamental component varies. On the other hand, for the same ratio of switching to output frequency, the harmonic components vary relatively little, resulting in a large variation of THD and WTHD. Therefore, a normalized WTHD can be used. For the case of half-bridge inverter, the normalization factor is chosen to be the value of the fundamental ac voltage when the modulation index M equals 1, that is, Vdc. Thus, the normalized WTHD, WTHD0,

> In this chapter, an application of double Fourier series to analytical analysis of power width modulation of power electronic converters was presented. The pulse width modulation concept was given, and different pulse width modulation schemes were described. Harmonic spectra and various distortion factors were calculated for various inverter topologies, namely three- and five-level diode-clamped inverters, three- and five-level cascaded H-bridge inverters, and modulated using different PWM schemes. PWM schemes performance varied for different converter topologies; therefore, the preferable PWM strategy is usually determined by a specific converter topology.

Comparing different topologies, the cascaded H-bridge topology contains the least number of sideband harmonics, and they can be further eliminated by increasing the number of levels of the inverter. DCMLIs and CCMLIs are constrained in the number of levels due to diodes physical properties.
