**5. Summary and conclusion**

In this chapter, high‐tech 1024‐point Radix II FFT processor was implemented. The design was launched with introducing 32‐bit data single precision floating‐point parallel pipeline architecture. Then, it was followed by implementing the subcomponents such as Radix II butterfly and smart controller. The implementation result of high‐tech 1024‐point Radix II FPP FFT processor was provided accordingly. Designing high speed floating‐point arith‐ metic unit such as adder/subtraction (278 MHz), multiplier (322 MHz), implementing smart controller to save area and increase system efficiency, design processor as single chip by implementing complex dual memory, and providing pipeline and parallel architecture lead to present a high‐tech 1024‐point Radix II FPP FFT processor. In addition, the proces‐ sor was synthesized using the Xilinx ISE platform. From synthesis report, it was found that the FPP FFT processor shows the maximum clock frequency of 227 MHz. The latency for calculating 1024‐point FFT is 22 µs. After FPGA implementation, the proposed proces‐ sor was optimized in ASIC under Silterra 0.18 µm and Mimos 0.35 µm technology librar‐ ies. The estimation power consumption was reported 640 mW in Silterra and 1.198 W in Mimos technology library with sample rate of 25 ms/s. The procedure was followed by defining the constraints and the netlist (gate level) to produce the ASIC layout. The design compiler result shows the die size of 2.32 × 2.32 mm2 in Silterra 0.18 µm technology and 4.256 × 4.256 mm2 in Mimos 0.35 µm technology. From the given specification, it was found that the high‐tech 1024‐point Radix II FPP FFT processor is suitable for high performance DSP application.
