**4. Resistive threshold logic**

We can see from *i* = *v*/*M*(*q* ) that when there is no voltage difference across the memristor, there is no current through the memristor. When the potential applied is reversed, the width of the undoped region increases resulting in an increase in effective resistance. The high resistance blocks any reverse leakage current and adding more inputs, the collective current does not

The *V*‐*I* characteristics of the memristor are shown in **Figure 7**. Generally, indicative of a pinched hysteresis effect [3, 4, 6], the changes in the slope indicate the switching behaviour, with each of the switch having at least two resistance states. With change in operating fre‐ quencies, the resistance values of the state become equal at high frequencies. The frequency

increase significantly as the effective resistance remains constant.

dependence of memristor is shown in **Figure 7**.

102 Fourier Transforms - High-tech Application and Current Trends

**Figure 7.** The V‐I characteristics of the memristor device.

Resistive threshold logic [11, 12] is a new logic family based on a resistive voltage divider and threshold logic, which is the hardware implementation of the neuron cell by configur‐ ing the cognitive memory network [13]. This circuit is capable of doing all Boolean logic [14, 15].

Two‐input basic resistive threshold logic cells are shown in **Figure 8**. For a straight forward approach, we started by using semiconductor resistors for the resistive divider. The input to the resistive divider is voltage levels that can be equated to the logic inputs [10] of a digital logic gate. Based on the logic functionality required, predefined threshold levels will be used in the thresholding part.

**Figure 8.** Two‐input basic resistive threshold logic cell.

An *N*‐input resistance divider circuit consist of *N* input resistors *Ri* and one reference resistor *R*0 . The output voltage *V*<sup>0</sup> for *N*‐input voltages *Vi* is shown in Eq. (1),

$$V\_o = \frac{\sum\_{i=1}^{N} \frac{V\_i}{R\_\gamma}}{\left(\frac{1}{R\_o} + \sum\_{i=1}^{N} \frac{1}{R\_\gamma}\right)}\tag{1}$$

We keep equal values to *Ri* 's and *R*<sup>0</sup> <sup>=</sup> *<sup>m</sup> Ri* , which results in:

$$V\_0 = \frac{\sum\_{i=1}^{N} V\_i}{\frac{1}{m} + N} \tag{2}$$

The inverter with a threshold *<sup>V</sup>* th and a two‐input resistive divider is used to implements the NAND and NOR gates shown in **Table 1**. Given that, *<sup>V</sup>* dd <sup>=</sup> <sup>1</sup>*V*, *<sup>V</sup>* <sup>H</sup> <sup>=</sup> <sup>1</sup>*V*, *<sup>V</sup>* <sup>L</sup> <sup>=</sup> <sup>0</sup>*V*, (see **Table 1**), when the threshold voltage of the inverter is set between 0 and 1/3 V, the cell functions as NOR logic, while between 1/3 and 2/3 V the cell functions as NAND logic. This implies that varying the threshold voltage of the inverter a single cell structure can be used to implement NAND and NOR logic.

In general, the range of threshold voltage, *V*th of NOR gate is *Nm <sup>V</sup>* \_\_\_\_\_\_*<sup>L</sup>* 1 + *Nm* ≤ *V*th ≤  (*VH* + (*<sup>N</sup>* <sup>−</sup> 1)*VL* ) *<sup>m</sup>* \_\_\_\_\_\_\_\_\_\_\_\_\_ *Nm* + 1 and NAND gate is,*<sup>m</sup>*(*VL* + (*<sup>N</sup>* <sup>−</sup> 1)*VH* ) \_\_\_\_\_\_\_\_\_\_\_\_\_ *Nm* + 1  ≤ *V*th ≤  *mN <sup>V</sup>* \_\_\_\_\_\_*<sup>H</sup> Nm* + 1.

To find the *m* value in Eq. (2), the lower limit of NAND gate threshold range *<sup>m</sup>*(*VL* + (*<sup>N</sup>* <sup>−</sup> 1)*VH* ) \_\_\_\_\_\_\_\_\_\_\_\_\_ *Nm* + 1 is equated to *VH* + *<sup>V</sup>* \_\_\_\_\_\_*<sup>L</sup>* <sup>2</sup> . And to solve the equation *VL* is taken as 0 V. So we get the *m* value as \_\_\_\_ <sup>1</sup> *<sup>N</sup>* <sup>−</sup> 2. Now we can say that the threshold voltage of NAND gate must be between *VH* + *<sup>V</sup>* \_\_\_\_\_\_*<sup>L</sup>* <sup>2</sup> and *mN <sup>V</sup>* \_\_\_\_\_\_*<sup>H</sup> Nm* + 1.

But there are certain drawbacks in using semiconductor resistors for building the voltage divider. One of the most important factors is the large leakage current of the semiconduc‐ tor resistors. When the number of inputs increases the problem of leakage current becomes prohibitively high. Another drawback of using semiconductor resistor is that a change in the resistance value of the resistor due to second‐order implementation effects, such as improper junctions and defects. This change in the resistance value is generally termed as the tolerance


**Table 1.** Truth table of two‐input resistive divider for NAND and NOR gates.

value of a resistors, which is usually ∓ 10% . This change in the resistance value may not cre‐ ate any problem when we are considering two‐input or three‐input circuits. But in practical implementations having a large number of inputs, these changes in the resistance value will have an adverse effect on the output of the circuit.

To overcome these drawbacks, semiconductor resistors were replaced with memristors developed by HP, which had negligible leakage current. Thus, the logic gate was modified as shown in **Figure 9**. The advantage of using op‐amp in the circuit is that it can act as a buffer and isolates the inputs from output of the circuit thus enabling realistic implementations of a large number of inputs per gate. As the number of inputs shown in **Figure 8** increases, the threshold voltage will change. This change can affect the functionality of the gate. This prob‐ lem can also be avoided by using the circuit shown in **Figure 9**. Here, the op‐amp will boost the signal before applying it to the inverter. Thus, it offers the advantage of scalability over the number of inputs.

The op‐amp reference voltage for NOR logic, *V*REF is fixed as *VL*+*<sup>Δ</sup>* and for NAND logic, *V*REF is fixed as *VH*−*<sup>Δ</sup>* , where *Δ* is a small voltage defined to ensure the bounds of *V*th. The op‐amp shifts the voltage to a high value or low value depending on the input voltage, *V*<sup>0</sup> .

**Figure 9.** Resistive threshold logic.

An *N*‐input resistance divider circuit consist of *N* input resistors *Ri*

's and *R*<sup>0</sup> <sup>=</sup> *<sup>m</sup> Ri*

In general, the range of threshold voltage, *V*th of NOR gate is

<sup>2</sup> . And to solve the equation *VL*

*mN <sup>V</sup>* \_\_\_\_\_\_*<sup>H</sup> Nm* + 1.

To find the *m* value in Eq. (2), the lower limit of NAND gate threshold range *<sup>m</sup>*(*VL*

Now we can say that the threshold voltage of NAND gate must be between *VH* + *<sup>V</sup>* \_\_\_\_\_\_*<sup>L</sup>*

But there are certain drawbacks in using semiconductor resistors for building the voltage divider. One of the most important factors is the large leakage current of the semiconduc‐ tor resistors. When the number of inputs increases the problem of leakage current becomes prohibitively high. Another drawback of using semiconductor resistor is that a change in the resistance value of the resistor due to second‐order implementation effects, such as improper junctions and defects. This change in the resistance value is generally termed as the tolerance

**) Output voltage NAND NOR**

2 *V*\_\_\_*L* 3 

*VL* <sup>+</sup>*<sup>V</sup>* \_\_\_\_\_\_*<sup>H</sup>* 3 

*VL* <sup>+</sup>*<sup>V</sup>* \_\_\_\_\_\_*<sup>H</sup>* 3 

<sup>2</sup> *<sup>V</sup>*\_\_\_\_*<sup>H</sup>* 3 

**Table 1.** Truth table of two‐input resistive divider for NAND and NOR gates.

*VL* <sup>+</sup>*<sup>V</sup>* \_\_\_\_\_\_*<sup>H</sup>* 3 <sup>&</sup>lt; *Vth* <sup>&</sup>lt;

for *N*‐input voltages *Vi*

is shown in Eq. (1),

∑*<sup>i</sup>*=1 *N V*\_\_\_*i Ri* \_\_\_\_\_\_\_\_\_\_

, which results in:

*<sup>N</sup> V* \_\_\_\_\_\_*<sup>i</sup>* \_\_1 *<sup>m</sup>* + *N*

The inverter with a threshold *<sup>V</sup>* th and a two‐input resistive divider is used to implements the NAND and NOR gates shown in **Table 1**. Given that, *<sup>V</sup>* dd <sup>=</sup> <sup>1</sup>*V*, *<sup>V</sup>* <sup>H</sup> <sup>=</sup> <sup>1</sup>*V*, *<sup>V</sup>* <sup>L</sup> <sup>=</sup> <sup>0</sup>*V*, (see **Table 1**), when the threshold voltage of the inverter is set between 0 and 1/3 V, the cell functions as NOR logic, while between 1/3 and 2/3 V the cell functions as NAND logic. This implies that varying the threshold voltage of the inverter a single cell structure can be used to implement

( \_\_1 *R*0 + ∑*<sup>i</sup>*=1 *<sup>N</sup>* \_\_1 *Ri* )

*R*0

. The output voltage *V*<sup>0</sup>

We keep equal values to *Ri*

NAND and NOR logic.

NAND gate is,*<sup>m</sup>*(*VL*

equated to *VH* + *<sup>V</sup>* \_\_\_\_\_\_*<sup>L</sup>*

**Input voltage (** *V i*

*VL VL*

*VL VH*

*VH VL*

*VH VH*

*V*<sup>0</sup> =

104 Fourier Transforms - High-tech Application and Current Trends

*<sup>V</sup>*<sup>0</sup> <sup>=</sup> <sup>∑</sup>*<sup>i</sup>*=1

 + (*<sup>N</sup>* <sup>−</sup> 1)*VH* ) \_\_\_\_\_\_\_\_\_\_\_\_\_

*<sup>V</sup>*<sup>1</sup> *<sup>V</sup>*<sup>2</sup> *<sup>V</sup>*<sup>0</sup>

*Nm* + 1  ≤ *V*th ≤ 

and one reference resistor

(*VH* + (*<sup>N</sup>* <sup>−</sup> 1)*VL* ) *<sup>m</sup>* \_\_\_\_\_\_\_\_\_\_\_\_\_ *Nm* + 1 and

<sup>2</sup> and

 + (*<sup>N</sup>* <sup>−</sup> 1)*VH* ) \_\_\_\_\_\_\_\_\_\_\_\_\_ *Nm* + 1 is

*<sup>N</sup>* <sup>−</sup> 2.

*mN <sup>V</sup>* \_\_\_\_\_\_*<sup>H</sup> Nm* + 1.

(1)

(2)

*Nm <sup>V</sup>* \_\_\_\_\_\_*<sup>L</sup>* 1 + *Nm* ≤ *V*th ≤ 

is taken as 0 V. So we get the *m* value as \_\_\_\_ <sup>1</sup>

<sup>2</sup> *<sup>V</sup>*\_\_\_\_*<sup>H</sup>* 3 

*VH VH*

*VH VL*

*VH VL*

*VL VL*

2 *V*\_\_\_*L* 3 <sup>&</sup>lt; *Vth* <sup>&</sup>lt; *VL* <sup>+</sup>*<sup>V</sup>* \_\_\_\_\_\_*<sup>H</sup>* 3 

> The universal gate circuit using resistive threshold logic is shown in **Figure 10**. For the cell to work as a NAND logic, the switches S1 and S4 are closed and the output is taken from *V*out. To implement AND logic, the switches S1 and S3 are closed and the output is taken from *V*out. If the switches S2 and S4 are closed, we get a NOR logic from *V*out. If both S2 and S3 are closed, OR logic can be implemented.

> **Figure 11** shows the circuit diagram of an *N*‐input resistive threshold logic gate. Here { *V* <sup>1</sup> , *V* <sup>2</sup> , *V* <sup>3</sup> , …,*<sup>V</sup>* <sup>N</sup>} represents the inputs to the cell.{ *<sup>M</sup>* <sup>1</sup> , *M* <sup>2</sup> , *M* <sup>3</sup> , ….*<sup>M</sup> <sup>N</sup>*} represents the input memristors. Depending on the values of the inputs, a potential *<sup>V</sup>* A is generated which is given

**Figure 10.** The universal gate structure that implements NAND, NOR, AND, OR and NOT logic functions.

**Figure 11.** N‐input resistive threshold logic gate.

to the non‐inverting terminal of the op‐amp. To the inverting terminal of the op‐amp, a *<sup>V</sup>* REF is given depending upon which the cell acts as either *N*‐input NOR gate or *N*‐input NAND gate. If the *<sup>V</sup>* REF is fixed at *<sup>V</sup> <sup>L</sup>* <sup>+</sup>*Δ* then the circuits acts as NOR gate and for NAND logic,*<sup>V</sup>* REF is fixed as *<sup>V</sup> <sup>H</sup>* <sup>−</sup> *<sup>Δ</sup>*, where *Δ* is a small voltage defined to ensure the bounds of *<sup>V</sup>* th. Thus, an *N*‐input logic gate can be implemented using memristor‐based resistive threshold logic. Here, as the number of inputs increase, only the number of memristors increases. The area consumed by a memristor is very small. Hence, even a very large input logic gate can be implemented in a very small area using the proposed resistive threshold logic.

## **5. Fast Fourier transform circuits**

The chapter summaries our previous work on the use of threshold logic in developing a hard‐ ware implementation of Fast Fourier transform [16]. Fast Fourier transform/inverse fast Fourier transform (FFT/IFFT) is widely used algorithm to compute the discrete Fourier transform and its inverse of a given set of inputs. FFT/IFFT is mainly used in digital signal processing applica‐ tions such as communication systems including orthogonal frequency division multiplexing (OFDM), spectrum analysis, DSL modems, speech coding, HDTV etc. Due to the large number of applications, it is important to design a FFT circuit which can handle large number of inputs and at the same time it should be small in area and should not become too complex.

The basic equation of four‐point DFT is

**Figure 11.** N‐input resistive threshold logic gate.

**Figure 10.** The universal gate structure that implements NAND, NOR, AND, OR and NOT logic functions.

106 Fourier Transforms - High-tech Application and Current Trends

$$X(k) = \sum\_{j=0}^{3} x(n) e^{\frac{-j2\pi k}{4}}, \ k = 0, 1, 2, 3 \tag{3}$$

Eq. (3) can be rewritten as an N‐by‐N multiplication as

$$\mathbf{X} = \mathbf{W}\mathbf{x}\tag{4}$$

Eq. (4) can be expanded in matrix form as given below.

$$
\begin{bmatrix} X(0) \\ X(1) \\ X(2) \\ X(3) \end{bmatrix} = \begin{bmatrix} 1 & 1 & 1 & 1 \\ 1 & -j & -1 & j \\ 1 & -1 & 1 & 1 \\ 1 & j & -1 & j \end{bmatrix} \begin{bmatrix} x(0) \\ x(1) \\ x(2) \\ x(3) \end{bmatrix} \tag{5}
$$

In the above matrix multiplication, *X*(*k*), *<sup>k</sup>* <sup>=</sup> 0, 1, 2, 3are the DFT outputs whereas *x*(*k*), *<sup>k</sup>* <sup>=</sup> 0, 1, 2, <sup>3</sup> are the inputs. Using this matrix equation, we can represent the signal flow graph of four‐point DFT, as shown in **Figure 12**. The exponential term *e* −*j*2*πnk* \_\_\_\_\_\_ <sup>4</sup> = ±1 or ± *j*. Since multiplications with ±1and ±*j* are trivial, no multipliers are needed to implement them, i.e. they can be simply realized with bypass, inversion, and/or swap for 2's complement numbers. Hence, it does not require any multiplier to construct a butterfly element for a four‐point DFT (radix‐4 butterfly). From **Figure 12**, it can be seen that we can implement the processor using adders and inverters.

**Figure 12.** Signal flow graph of a four‐point FFT.

Implementation of the FFT processor can be done, as shown in **Figure 13** where *x*(0), *x*(1), *x*(2) and *x*(3) are the inputs and *X*(0), *X*(1)*, X*(2) and *X*(3) are the outputs of the FFT circuits. The circuits are capable of handling complex numbers and the complex numbers are separated into real and imaginary part and are given into the circuit. All the inputs to the circuit are 8 bits long.

All the FFT units take in four inputs and give the corresponding FFT output. Inputs are given to the FFT units according to **Figure 12**. From the signal flow graph of the four‐point FFT, we can see that FFT outputs are obtained by equations of the form

$$X(k) = a + b + c + d\tag{6}$$

or

$$X(k) = a + b - c - d\tag{7}$$

So it is understood that certain inputs need to be subtracted in order to get the Fourier transform output. In digital circuits, subtraction is carried out by taking the 2's complement of the subtra‐ hend and then adding it to the minuend to get the difference. For obtaining 2's complement of a number, first of all, 1's compliment of the number has to be found out and then add one to it.

From **Figure 12**, it can be seen that the real and the imaginary part of the first output, i.e. *X*(0), in four‐point FFT is obtained by computations of the form Eq. (6). So it requires addition operations only. Hence, the inputs to the first two FFT units are not complimented, as shown in **Figure 13**.

**Figure 13.** General block diagram of a four‐point FFT circuit.

require any multiplier to construct a butterfly element for a four‐point DFT (radix‐4 butterfly). From **Figure 12**, it can be seen that we can implement the processor using adders and inverters.

Implementation of the FFT processor can be done, as shown in **Figure 13** where *x*(0), *x*(1), *x*(2) and *x*(3) are the inputs and *X*(0), *X*(1)*, X*(2) and *X*(3) are the outputs of the FFT circuits. The circuits are capable of handling complex numbers and the complex numbers are separated into real and imaginary part and are given into the circuit. All the inputs to the circuit are 8 bits long. All the FFT units take in four inputs and give the corresponding FFT output. Inputs are given to the FFT units according to **Figure 12**. From the signal flow graph of the four‐point FFT, we

*X*(*k*) = *a* + *b* + *c* + *d* (6)

*X*(*k*) = *a* + *b* − *c* − *d* (7)

So it is understood that certain inputs need to be subtracted in order to get the Fourier transform output. In digital circuits, subtraction is carried out by taking the 2's complement of the subtra‐ hend and then adding it to the minuend to get the difference. For obtaining 2's complement of a number, first of all, 1's compliment of the number has to be found out and then add one to it.

From **Figure 12**, it can be seen that the real and the imaginary part of the first output, i.e. *X*(0), in four‐point FFT is obtained by computations of the form Eq. (6). So it requires addition operations only. Hence, the inputs to the first two FFT units are not complimented, as shown in **Figure 13**.

can see that FFT outputs are obtained by equations of the form

**Figure 12.** Signal flow graph of a four‐point FFT.

108 Fourier Transforms - High-tech Application and Current Trends

or

However, all other outputs of the four‐point FFT are obtained by computations of the form Eq. (7), see **Figure 12**. So it consists of addition as well as subtractions. In order to implement subtraction, two's complement of the inputs is taken and is added. For taking 2's complement, first of all, the signals need to be inverted. This is obtained by the inverters shown in **Figure 13**. Since all the inputs are of 8‐bit length, 8‐bit inverters are used in the circuit. The output of these inverters will be the 1's compliment of the input signals. To get 2's complement one must be added to the 1's compliment. Since two signals are to be complimented according to Eq. (7), two must be added to their sum. It is equivalent to adding one be the (LSB + 1)th place of their sum. This is done inside their corresponding FFT units, see **Figure 14**.

**Figure 14.** General block diagram of a FFT unit.

Let the four inputs to an FFT unit be denoted as *w*, *x*, *y* and *z*. All these inputs are 8‐bit long. So the input *w* can be represented as *<sup>w</sup>* <sup>8</sup> *<sup>w</sup>* <sup>7</sup> *<sup>w</sup>* <sup>6</sup> *<sup>w</sup>* <sup>5</sup> *<sup>w</sup>* <sup>4</sup> *<sup>w</sup>* <sup>3</sup> *<sup>w</sup>* <sup>2</sup> *<sup>w</sup>* <sup>1</sup> . Similarly, *x*, *y* and *z* can be represented as *<sup>x</sup>* <sup>8</sup> *<sup>x</sup>* <sup>7</sup> *<sup>x</sup>* <sup>6</sup> *<sup>x</sup>* <sup>5</sup> *<sup>x</sup>* <sup>4</sup> *<sup>x</sup>* <sup>3</sup> *<sup>x</sup>* <sup>2</sup> *<sup>x</sup>* <sup>1</sup> , *<sup>y</sup>* <sup>8</sup> *<sup>y</sup>* <sup>7</sup> *<sup>y</sup>* <sup>6</sup> *<sup>y</sup>* <sup>5</sup> *<sup>y</sup>* <sup>4</sup> *<sup>y</sup>* <sup>3</sup> *<sup>y</sup>* <sup>2</sup> *<sup>y</sup>* <sup>1</sup> and *<sup>z</sup>* <sup>8</sup> *<sup>z</sup>* <sup>7</sup> *<sup>z</sup>* <sup>6</sup> *<sup>z</sup>* <sup>5</sup> *<sup>z</sup>* <sup>4</sup> *<sup>z</sup>* <sup>3</sup> *<sup>z</sup>* <sup>2</sup> *<sup>z</sup>* <sup>1</sup> , respectively. For the FFT units that are computing real and imaginary parts of *X*(0 ) , namely *<sup>X</sup>* re(0 )and *<sup>X</sup>* im(0 ) , only additions are involved. Hence w, x, y and z need to be added to get *X*(0 ) . Addition of four binary num‐ bers can be done using (4, 2)‐counters or (4, 2)‐compressors. So in order to implement a FFT unit, eight (4, 2)‐counters are required.

The basic block diagram of a (4, 2)‐counter is as shown in **Figure 15**. This circuit takes in four inputs and gives 3 outputs ‐ sum, carry and carry out. A parallel arrangement of eight such (4, 2)‐counters are needed to implement a single FFT unit. As seen from **Figure 15**, these (4, 2)‐ counters are implemented using the basic logic gates. All these logic gates are implemented using the proposed memristor‐based resistive threshold logic.

The OR gate presented in **Figure 15** is implemented as shown in **Figure 16**, where A and B repre‐ sent the inputs, *VL* <sup>+</sup>*Δ*V represent the reference voltage and *V*OUT represents the output of the gate.

AND gate can be obtained either from inverting the output of the NAND gate or by giving inverted inputs to the NOR gate. **Figure 17** shows the AND gate, used in **Figure 15** which is obtained by giving inverted inputs to the resistive threshold NOR gate.

XOR logic gate is implemented as shown in the circuit diagram of **Figure 18**. It is imple‐ mented using NOR logic. Thus, by using the circuits of **Figures 16**–**18**, a (4, 2)‐counter can be implemented. By using a parallel implementation of eight such (4, 2)‐counters, a single FFT unit can be implemented. For implementing a full FFT circuit, we require eight FFT units, four for the real parts and four for the imaginary parts of the outputs.

**Figure 15.** Block diagram of a single (4, 2)‐counter.

Since all the inputs are of 8‐bit length, 8‐bit inverters are used in the circuit. The output of these inverters will be the 1's compliment of the input signals. To get 2's complement one must be added to the 1's compliment. Since two signals are to be complimented according to Eq. (7), two must be added to their sum. It is equivalent to adding one be the (LSB + 1)th place of their

Let the four inputs to an FFT unit be denoted as *w*, *x*, *y* and *z*. All these inputs are 8‐bit long. So

that are computing real and imaginary parts of *X*(0 ) , namely *<sup>X</sup>* re(0 )and *<sup>X</sup>* im(0 ) , only additions are involved. Hence w, x, y and z need to be added to get *X*(0 ) . Addition of four binary num‐ bers can be done using (4, 2)‐counters or (4, 2)‐compressors. So in order to implement a FFT

The basic block diagram of a (4, 2)‐counter is as shown in **Figure 15**. This circuit takes in four inputs and gives 3 outputs ‐ sum, carry and carry out. A parallel arrangement of eight such (4, 2)‐counters are needed to implement a single FFT unit. As seen from **Figure 15**, these (4, 2)‐ counters are implemented using the basic logic gates. All these logic gates are implemented

The OR gate presented in **Figure 15** is implemented as shown in **Figure 16**, where A and B repre‐

AND gate can be obtained either from inverting the output of the NAND gate or by giving inverted inputs to the NOR gate. **Figure 17** shows the AND gate, used in **Figure 15** which is

XOR logic gate is implemented as shown in the circuit diagram of **Figure 18**. It is imple‐ mented using NOR logic. Thus, by using the circuits of **Figures 16**–**18**, a (4, 2)‐counter can be implemented. By using a parallel implementation of eight such (4, 2)‐counters, a single FFT unit can be implemented. For implementing a full FFT circuit, we require eight FFT units, four

<sup>+</sup>*Δ*V represent the reference voltage and *V*OUT represents the output of the gate.

and *<sup>z</sup>* <sup>8</sup> *<sup>z</sup>* <sup>7</sup> *<sup>z</sup>* <sup>6</sup> *<sup>z</sup>* <sup>5</sup> *<sup>z</sup>* <sup>4</sup> *<sup>z</sup>* <sup>3</sup> *<sup>z</sup>* <sup>2</sup> *<sup>z</sup>* <sup>1</sup>

. Similarly, *x*, *y* and *z* can be represented

, respectively. For the FFT units

sum. This is done inside their corresponding FFT units, see **Figure 14**.

the input *w* can be represented as *<sup>w</sup>* <sup>8</sup> *<sup>w</sup>* <sup>7</sup> *<sup>w</sup>* <sup>6</sup> *<sup>w</sup>* <sup>5</sup> *<sup>w</sup>* <sup>4</sup> *<sup>w</sup>* <sup>3</sup> *<sup>w</sup>* <sup>2</sup> *<sup>w</sup>* <sup>1</sup>

unit, eight (4, 2)‐counters are required.

**Figure 14.** General block diagram of a FFT unit.

110 Fourier Transforms - High-tech Application and Current Trends

, *<sup>y</sup>* <sup>8</sup> *<sup>y</sup>* <sup>7</sup> *<sup>y</sup>* <sup>6</sup> *<sup>y</sup>* <sup>5</sup> *<sup>y</sup>* <sup>4</sup> *<sup>y</sup>* <sup>3</sup> *<sup>y</sup>* <sup>2</sup> *<sup>y</sup>* <sup>1</sup>

using the proposed memristor‐based resistive threshold logic.

obtained by giving inverted inputs to the resistive threshold NOR gate.

for the real parts and four for the imaginary parts of the outputs.

as *<sup>x</sup>* <sup>8</sup> *<sup>x</sup>* <sup>7</sup> *<sup>x</sup>* <sup>6</sup> *<sup>x</sup>* <sup>5</sup> *<sup>x</sup>* <sup>4</sup> *<sup>x</sup>* <sup>3</sup> *<sup>x</sup>* <sup>2</sup> *<sup>x</sup>* <sup>1</sup>

sent the inputs, *VL*

**Figure 16.** Circuit diagram of OR gate using memristor‐based resistive threshold logic.

But while implementing the FFT units for real and imaginary parts of outputs *X*(*1*), *X*(*2*) and *X*(3), the implementations involve subtraction. For subtractions, 2's complement of the subtrahend is taken and added. For taking 2's complement, first of all, the signal is inverted and then one is added. Inversion of the signal is carried out using an 8‐bit inverter, as shown in **Figure 13**. The addition of one is done inside the FFT unit. Since two signals are to be subtracted per FFT unit, one has to be added twice which is equivalent to adding two or in binary terms, adding one to the (LSB+1)th position. This addition is shown in **Figure 14**.

**Figure 17.** Circuit diagram of AND gate using memristor‐based resistive threshold logic.

**Figure 18.** Circuit diagram of XOR gate using memristor‐based resistive threshold logic.
