**1. Introduction**

The prevalent subject of Fourier analysis encompasses a vast spectrum of mathematics where parts may appear quite different at first glance. In Fourier analysis, the term Fourier transform often refers to the process that decomposes a given function into the harmonics domain. This process results in another function that describes what frequencies are in the original function.

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© 2016 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, © 2017 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Meanwhile, the transformation is often given a more specific name depending upon the domain and other properties of the function being transformed.

### **2. Fourier transform fundamental**

Fourier transform was introduced with the main concepts of discrete Fourier transform (DFT) [1] in the heart of most DSP processor. The DFT is a Fourier representation of a finite‐length sequence which is the most important fundamental operation in digital signal processing and communication system [2, 3]. However, the computation complexity of the direct evaluation of an *N*‐point DFT involves a long phase computational time and large power consumption [4]. As a result of these problems, it is important to develop a fast algorithm. There are numerous viewpoints that can be taken toward the derivation and interpretation of the DFT representation of a finite‐duration sequence. The sequence of *x*̃(*n* )that is periodic with period *N* so that *x*̃(*n* ) = *x*̃(*n* + *kN* )functions for any integer value of *k*. It is possible to represent *x*̃(*n* )in terms of Fourier series that is represented by the sum of sine and cosine values or equivalently complex exponential sequences with frequen‐ cies that are integer multiplies of the fundamental frequencies 2*π*/*N* associated with the periodic sequence. The same representation can be applied to finite‐duration sequence. The resulting Fourier representation for finite duration sequences will be referred to as the DFT. Sequence of length *N* by a periodic sequence can be represented by a periodic sequence with period *N*, one period of which is identical to the finite‐duration sequence. The sampled sequence signal in frequency is defined as

$$X(\omega) = \sum\_{n=-\omega}^{\omega} \mathbf{x}(n) e^{-\omega n} \tag{1}$$

The DFT *X*(*ω*) is a function of continuous‐frequency variable *ω*, and the summation in Eq. (1) extends toward positive and negative infinitively. Therefore, the DFT is a theoretical Fourier transform of a digital signal. However, it cannot be implemented for real applications. It is the sample of the signal in time domain at a particular time and can be expressed as:

$$\mathbf{x}(n) = \underset{\mathbf{t}}{\stackrel{\ast}{\underset{\mathbf{0}}{\rightleftharpoons}}} \mathbf{x}(t)\boldsymbol{\delta}\left(t - t\_n\right) \tag{2}$$

The frequency analysis of a finite‐length sequence is equal to the sample of continuous fre‐ quency variable *ω* at *N* equally spaced frequencies *ωk* = 2*πk*/*N* for *k* = 0, 1, 2, …, *N* ‐ 1 on the unit circle. These frequency samples are expressed as:

eqequency samples are expressed as: 
$$\begin{array}{l} \text{X(k)} = \text{ X(\omega)} \; , \; \omega\_{k} = \frac{2\pi k}{N} \\ \text{X(k)} = \sum\_{n=0}^{N-1} \text{x}(n)e^{-\frac{j2\pi k}{N}} = \sum\_{n=0}^{N-1} \text{x}(n)W\_{N}^{kn} \; , \; k = 0 \; 1 \; \dots \; N-1 \end{array} \tag{3}$$

where the twiddle factors are defined as:

where the twiddle factors are defined as: 
$$W\_N^{\rm tr} = \ \ c^{-\left(\frac{2\pi}{N}\right)n} = \cos\left(\frac{2\pi kn}{N}\right) - j\sin\left(\frac{2\pi kn}{N}\right) \tag{4}$$

The DFT is based on the assumption that the signal **x(n )** is periodic. Therefore, *X*(*k*) for *k* = 0, 1, …, *N* ‐ 1 can uniquely represent a periodic sequence *x*(*n*) of period *N*. The inverse DFT is the reversed process of the DFT. It converts the frequency spectrum *X*(*k*) back to the time domain signal *x*(*n*) [5]:

$$\mathbf{x}(n) = \ \ \ \frac{1}{N} \sum\_{k=0}^{N-1} \mathbf{X}(k) e^{\frac{(2\pi kn)}{N}} = \ \frac{1}{N} \sum\_{k=0}^{N-1} \mathbf{X}(k) \mathbf{W}\_N^{-k\*}, n = 0, \ 1, \ldots, N-1 \tag{5}$$

Direct computation of an *N*‐point DFT according to Equation Eq. (5) requires *N*(*N*‐ **1**) complex additions and *N*(*N*‐ **1**) complex multiplications. The complexity for computing an N‐point DFT is therefore *O*(*N***2**). High computation complexity in DFT algorithm and need for having efficient Fourier processor leads for introduction of a fast Fourier transform (FFT) processor.

### **2.1. Fast Fourier transform (FFT) algorithm**

Meanwhile, the transformation is often given a more specific name depending upon the domain

Fourier transform was introduced with the main concepts of discrete Fourier transform (DFT) [1] in the heart of most DSP processor. The DFT is a Fourier representation of a finite‐length sequence which is the most important fundamental operation in digital signal processing and communication system [2, 3]. However, the computation complexity of the direct evaluation of an *N*‐point DFT involves a long phase computational time and large power consumption [4]. As a result of these problems, it is important to develop a fast algorithm. There are numerous viewpoints that can be taken toward the derivation and interpretation of the DFT representation of a finite‐duration sequence. The sequence of *x*̃(*n* )that is periodic with period *N* so that *x*̃(*n* ) = *x*̃(*n* + *kN* )functions for any integer value of *k*. It is possible to represent *x*̃(*n* )in terms of Fourier series that is represented by the sum of sine and cosine values or equivalently complex exponential sequences with frequen‐ cies that are integer multiplies of the fundamental frequencies 2*π*/*N* associated with the periodic sequence. The same representation can be applied to finite‐duration sequence. The resulting Fourier representation for finite duration sequences will be referred to as the DFT. Sequence of length *N* by a periodic sequence can be represented by a periodic sequence with period *N*, one period of which is identical to the finite‐duration sequence.

> *n*= −∞ ∞

The DFT *X*(*ω*) is a function of continuous‐frequency variable *ω*, and the summation in Eq. (1) extends toward positive and negative infinitively. Therefore, the DFT is a theoretical Fourier transform of a digital signal. However, it cannot be implemented for real applications. It is the

> 0 ∞

The frequency analysis of a finite‐length sequence is equal to the sample of continuous fre‐ quency variable *ω* at *N* equally spaced frequencies *ωk* = 2*πk*/*N* for *k* = 0, 1, 2, …, *N* ‐ 1 on the

*<sup>X</sup>*(*k*) <sup>=</sup> *<sup>X</sup>*(*ωk*) , *<sup>ω</sup><sup>k</sup>* <sup>=</sup> \_\_\_\_ <sup>2</sup>*π<sup>k</sup>*

The DFT is based on the assumption that the signal **x(n )** is periodic. Therefore, *X*(*k*) for *k* = 0, 1, …, *N* ‐ 1 can uniquely represent a periodic sequence *x*(*n*) of period *N*. The inverse DFT is the

*x*(*n*)*WN*

\_2*πkn*

*x*(*t*)*δ*(*t* − *t*

*N*

*<sup>N</sup>* ) − *j* sin (

*kn* , *k* = 0, 1, …,*N* − 1

\_2*πkn*

sample of the signal in time domain at a particular time and can be expressed as:

*<sup>X</sup>*(*k*) <sup>=</sup> <sup>∑</sup>

*<sup>N</sup>* )*kn* = cos (

*x*(*n*)*e* <sup>−</sup>*jω<sup>n</sup>* (1)

*<sup>n</sup>*) (2)

*<sup>N</sup>* ) (4)

(3)

and other properties of the function being transformed.

The sampled sequence signal in frequency is defined as

*X*(*ω*) = ∑

*x*(*n*) = ∫

where the twiddle factors are defined as:

*WN*

unit circle. These frequency samples are expressed as:

*n*=0 *N*−1 *x*(*n*)*e* <sup>−</sup> *j*2*πkn* \_\_\_\_\_ *<sup>N</sup>* = ∑ *n*=0 *N*−1

*kn* = *e* <sup>−</sup>*j*(

\_2*π*

**2. Fourier transform fundamental**

68 Fourier Transforms - High-tech Application and Current Trends

In 1965 Cooley and Tukey [6] developed the use of FFT in order to save time and avoid unnec‐ essary complex calculations. FFT algorithm computes an *N*‐point forward DFT or inverse DFT (IDFT) where *N* is 2 power of *M*. FFT algorithm divides *N*‐point data into two *N*/2‐point series and performs the DFT on series individually results in the order of *O*(*N*/2 ) 2 complex‐ ity as compared with the original *N*<sup>2</sup> operations in an *N*‐point DFT. The process of dividing can be continued until a 2‐point DFT is reached. FFT algorithm computes an *N*‐point forward DFT or inverse DFT (IDFT) where *N* is 2 power of *m*. The FFT is a family of algorithms that efficiently implements the DFT. **Table 1** shows the comparison between the calculation of direct DFT and FFT when a different number of *N* is applied.


**Table 1.** Computation complexity of DFT and FFT algorithm.

To calculate FFT algorithm, there are two well‐known methods identified as DIT‐FFT and DIF‐FFT calculations [7–9]. In general, FFT processor has many types in terms of Fourier cal‐ culation. Taking into account different types of FFT algorithms are:


Here, further detail is provided for DIT and DIF processor.

### *2.1.1. DIT Radix II butterfly FFT processor*

The FFT structure divides input series into odd and even sequences. The number of stream in FFT is *N* = 2*<sup>m</sup>* when *m* is a positive integer:

\*\*1 \*\*1\*\*: \_positive\_mode\_ mean\_ decreases.\*\* The number of alternate \_and\_ be positive integer:

$$\text{xe(n)} = \text{x}(2m), \ m = 0, \ 1, \ \dots, \left(\frac{N}{2}\right) - 1$$

$$\text{xo(n)} = \text{x}(2m+1), \ m = 0, \ 1, \ \dots, \left(\frac{N}{2}\right) - 1$$

Based on the DFT definition and combination of the FFT concept, *X*(*k*) can be written as:

$$X(k) = \sum\_{n=0}^{N-1} x(n)W\_N^{kn} = \sum\_{n=0}^{\binom{N}{2}-1} x(2m)W\_N^{2nk} + \sum\_{n=0}^{\binom{N}{2}-1} x(2m+1) \, W\_N^{(2m+1)k} \tag{7}$$

Since *WN* <sup>2</sup>*mk* <sup>=</sup> *WN*/2 *mk* , the equation will be simplified as:

$$X(k) = \sum\_{m=0}^{\binom{N}{2}-1} \mathbf{x}\_{\epsilon}(m) W\_{\frac{N}{2}}^{\#} + W\_N^k \sum\_{m=0}^{\binom{N}{2}-1} \mathbf{x}\_{\epsilon}(m) W\_{\frac{N}{2}}^{\#} k = 0, 1, \dots, N-1 \tag{8}$$

where *WN k* is complex twiddle factor with unit amplitude and different phase angles. The 8‐point FFT utilizes the twiddle factors from *WN* 0 to *WN* 7 . The first twiddle factor *WN* <sup>0</sup> = 1 . All twiddle factors are distributed around the unit circle. **Figure 1** shows the twiddle factor for 8‐point Fourier transform. The twiddle factor *WN k* repeats itself after every multiple of *N*. The twiddle factors are periodic and for 8‐point FFT twiddle factor 0 and 8 are equal.

**Figure 1.** 8‐point FFT twiddle factor.

By assuming *Xe* (*k*) = ∑ *m*=0 ( \_ *N* <sup>2</sup> )−1 *xe* (*m* ) *WN*/2 *mk* and *X<sup>o</sup>* (*k*) = ∑ *m*=0 ( \_ *N* <sup>2</sup> )−1 *xo* (*m*)*W*\_\_ *N* 2 *mk* , this symmetric property provides a reduction in calculations as:

By assuming  $\mathbf{x}\_{i}(k) = \sum\_{\mathbf{m}} \mathbf{x}\_{i}(m)W\_{\mathbf{m}}$  and  $\mathbf{x}\_{o}(k) = \sum\_{\mathbf{m}} \mathbf{x}\_{o}(m)W\_{\frac{\mathbf{m}}{2}}^{\*}$ , thus summing  $\mathbf{m}$  and 
$$\mathbf{X}(k) = \begin{cases} X\_{i}(k) + W\_{\mathbf{N}}^{k}X\_{o}(k), \ k = 0, 1, \ldots, \left(\frac{N}{2}\right) - 1\\\ X\_{i}(k) - W\_{\mathbf{N}}^{k}X\_{o}(k), \ k = \left(\frac{N}{2}\right), \ldots, N - 1 \end{cases} \tag{9}$$

Butterfly calculation is the fundamental concept of the FFT algorithm and 8‐point butterfly structure is shown in **Figure 2**.

**Figure 2.** Decomposition of 8‐point DIT FFT structure.

*2.1.1. DIT Radix II butterfly FFT processor*

70 Fourier Transforms - High-tech Application and Current Trends

FFT is *N* = 2*<sup>m</sup>* when *m* is a positive integer:

*n*=0 *N*−1

> *m*=0 ( \_ *N* 2 )−1 *xe* (*m*)*W*\_\_ *N* 2 *mk* + *WN k* ∑ *m*=0 ( \_ *N* 2 )−1 *xo* (*m*)*W*\_\_ *N* 2

*x*(*n*)*WN*

*mk* , the equation will be simplified as:

*k*

periodic and for 8‐point FFT twiddle factor 0 and 8 are equal.

*kn* = ∑ *m*=0 ( \_ *N* 2 )−1

> 0 to *WN* 7

*X*(*k*) = ∑

*X*(*k*) = ∑

FFT utilizes the twiddle factors from *WN*

transform. The twiddle factor *WN*

**Figure 1.** 8‐point FFT twiddle factor.

<sup>2</sup>*mk* <sup>=</sup> *WN*/2

Since *WN*

where *WN k*

The FFT structure divides input series into odd and even sequences. The number of stream in

\_ *N*2 )– 1 

\_ *N* 2 )– 1

*x*(2*m* + 1 ) *WN*

(6)

(2*m*+1 )*<sup>k</sup>* (7)

<sup>0</sup> = 1 . All twiddle factors

*mk k* = 0, 1, …,*N* − 1 (8)

*xe*(*n*) = *x*(2*m*), *m* = 0, 1, …., (

*xo*(*n*) = *x*(2*m* + 1 ), *m* = 0, 1, …., (

Based on the DFT definition and combination of the FFT concept, *X*(*k*) can be written as:

*x*(2*m*)*WN*

are distributed around the unit circle. **Figure 1** shows the twiddle factor for 8‐point Fourier

<sup>2</sup>*mk* + ∑ *m*=0 ( \_ *N* 2 )−1

is complex twiddle factor with unit amplitude and different phase angles. The 8‐point

. The first twiddle factor *WN*

repeats itself after every multiple of *N*. The twiddle factors are

Radix II butterfly FFT is decomposed into *M* stages, where *<sup>M</sup>* <sup>=</sup> log2 *<sup>N</sup>*. In each stage, *N*/2 complexes are multiplied by the twiddle factors where *N* complex additions are required. Therefore, the total computational requirement is (*<sup>N</sup>* log2 *<sup>N</sup>* ) /2 complex multiplications and *<sup>N</sup>* log2 *<sup>N</sup>* complex addi‐ tions. Consequently, expanding Radix II butterfly calculation into 8 data is shown in **Figure 3**.

### *2.1.2. DIF Radix II butterfly FFT processor*

DIF‐FFT calculation is similar to the DIT‐FFT algorithm. As far as FFT calculation is involved, the time domain sequence is divided into two subsequences with *N/2 samples: The DFT concept of x(n )* expressed as:

$$\mathbf{X}(\mathbf{k}) = \sum\_{n=0}^{\binom{N}{2}-1} \mathbf{x}(n)\mathbf{W}\_{N}^{nk} + \sum\_{n=\frac{N}{2}}^{N-1} \mathbf{x}(n)\mathbf{W}\_{N}^{nk} = \sum\_{n=0}^{\binom{N}{2}-1} \mathbf{x}(n)\mathbf{W}\_{N}^{nk} + \sum\_{n=0}^{\{N/2\}-1} \mathbf{x}(n+N/2)\mathbf{W}\_{N}^{nk} \ \mathbf{W}\_{N}^{(\frac{N}{2})k} \tag{10}$$

**Figure 3.** Decomposition of 8‐point DIT‐FFT.

Given that *WN* ( \_ *N*<sup>2</sup> )*<sup>k</sup>* = (− 1 ) *<sup>k</sup>* , Eq. (10) can be simplified to:

$$X(k) = \sum\_{n=0}^{\binom{N}{2}-1} \left[ \mathbf{x}(n) + (-1)^k \mathbf{x}(n + N/2) \right] W\_N^{nk} \tag{11}$$

Later, Eq. (11) is expanded into two parts including even *X*(2*k* )and odd *X*(2*k* + 1 )sam\twid‐ dle factor characteristic, Eq. (11) is simplified to:

$$\begin{aligned} W\_n^{\text{V2a}} &= W\_{N/2}^{\text{inh}} W\_n^{(12\lambda+1)a} = W\_N^{\text{v2}} W\_{N/2}^{\text{v2a}}\\ X\left(2\lambda\right) &= \sum\_{n=0}^{\left(\frac{N}{2}\right)-1} \left[ \mathbf{x}\left(n\right) + \mathbf{x}\left(n + \frac{N}{2}\right) \right] W\_{N/2}^{\text{vak}} = \sum\_{n=0}^{\left(\frac{N}{2}\right)-1} \mathbf{x}\_1\left(n\right) W\_{N/2}^{\text{vak}}\\ X\left(2\lambda+1\right) &= \sum\_{n=0}^{\left(\frac{N}{2}\right)-1} \left[ \mathbf{x}\left(n\right) - \mathbf{x}\left(n + \frac{N}{2}\right) \right] W\_{N}^{\text{vak}} W\_{N/2}^{\text{vak}} = \sum\_{n=0}^{\left(\frac{N}{2}\right)-1} \mathbf{x}\_2\left(n\right) W\_{N}^{\text{vak}} W\_{N/2}^{\text{vak}} k = 0, 1, ..., \left(\frac{N}{2}\right) - 1 \end{aligned} \tag{12}$$

Similarly, 8‐point DIF FFT structure is shown in **Figure 4** with detail complex calculation in three stages. The output sequence *X*(*k* )of the DIF‐FFT is bit‐reversed, while the input sequence *x*(*n* ) of the DIT‐FFT is bit‐reversed. In addition, there is a slight difference in the calculation of butterfly architecture. As shown in **Figure 4**, the complex multiplication is performed before the complex addition or subtraction in the DIT‐FFT processor. In contrast, the complex subtraction is performed before the complex multiplication in the DIF‐FFT. The process of decomposition is continued until the last stage is reduced to the 2‐point DFT. Since the fre‐ quency samples in the DIF‐FFT are bit‐reversed, it is required to apply bit‐reversal algorithm to the frequency samples. Likewise, the DIF‐FFT algorithm also uses in‐place computation.

**Figure 4.** Internal calculation of 8‐point DIF‐FFT processor.

Unlike the DIF structure, input data in DIT‐FFT is in bit‐reverse format while the output is sorted. On the other hand, both the DIT and DIF can go from normal to shuffled data or vice versa. In order to apply Radix II FFT structures, DIT and DIF algorithms require the same number of operations and bit‐reversal to compute the FFT calculation. The overall performance of the FFT processor is dependent on the application, hardware implementation, and conve‐ nience. If the design is focused on high speed structure, the processor has to take the most efficient approach and algorithm to perform the FFT calculation accordingly. In this chapter DIT‐FFT architecture is considered for floating‐point implementation.

### **2.2. Floating point FFT algorithm**

Given that *WN*

( \_ *N*<sup>2</sup> )*<sup>k</sup>* = (− 1 ) *k*

*X*(*k*) = ∑

**Figure 3.** Decomposition of 8‐point DIT‐FFT.

72 Fourier Transforms - High-tech Application and Current Trends

dle factor characteristic, Eq. (11) is simplified to:

/ 2 / 2

( ) ( ) ( )

= ++ =

*<sup>N</sup> X k x n x n W x nW*

*n n*

*N N*

− −

1 1 2 2

0 0

= =

∑ ∑

( ) ( ) ( )

2

1 1 2 2

*N N*

− −

*n n*

0 0

= =

∑ ∑

( )

+

*kn kn k n n kn n Nn N N*

2 2 1

2

,

*W W W WW*

= =

, Eq. (10) can be simplified to:

*n*=0 ( \_ *N*2 )−1

[*x*(*n*) + (− 1 ) *<sup>k</sup> x*(*n* + *N*/2 )]*WN*

Later, Eq. (11) is expanded into two parts including even *X*(2*k* )and odd *X*(2*k* + 1 )sam\twid‐

/ 2 1 /2

*nk nk N N*

2 1 0,1, , 1 2 2

Similarly, 8‐point DIF FFT structure is shown in **Figure 4** with detail complex calculation in three stages. The output sequence *X*(*k* )of the DIF‐FFT is bit‐reversed, while the input sequence *x*(*n* ) of the DIT‐FFT is bit‐reversed. In addition, there is a slight difference in the calculation of butterfly architecture. As shown in **Figure 4**, the complex multiplication is performed before the complex addition or subtraction in the DIT‐FFT processor. In contrast, the complex subtraction is performed before the complex multiplication in the DIF‐FFT. The process of decomposition is continued until the last stage is reduced to the 2‐point DFT. Since the fre‐ quency samples in the DIF‐FFT are bit‐reversed, it is required to apply bit‐reversal algorithm to the frequency samples. Likewise, the DIF‐FFT algorithm also uses in‐place computation.

+= − + = =… −

*N N X k x n x n W W x nWW k*

/ 2 2 / 2

*nk nk n nk N N N N*

*nk* (11)

(12)

Measured frequency by FFT will be subjected to quantization noise error with respect to the real frequency. This is caused by the fact that the FFT only computes the spectrum at dis‐ crete frequencies. This error is said to affect the accuracy. In addition, spectral leakage effect becomes very significant when small amplitude harmonics are close to large amplitude ones since they become hidden by the energy distribution of the larger harmonics. Furthermore, the fixed internal arithmetic calculation generates white noise in frequency domain. To reduce the generated noise effect and enhance signal strength, floating‐point technique is designed and implemented. The floating‐point technique allows numbers to be represented with a large dynamic range. Therefore, floating‐point arithmetic enables the reduction of overflow problems that occur in fixed‐point arithmetic. Although it is at the expense of throughput and chip area size, the new architecture is designed and investigated to avoid undesired effects in floating‐point FFT algorithm. Floating‐point arithmetic provides higher precision and a much larger dynamic range under IEEE 754 standard [10]. Therefore, floating‐point operations sup‐ port more accurate DSP operations. **Table 2** compares the efficiency between fixed‐point and the floating‐point FFT processor.


**Table 2.** Fixed‐point and floating‐point FFT processor properties.

In floating‐point format, the data are translated based on power and mantissa in the decimal system. This notation can be expanded into the binary system. Representing the data in power and mantissa system gives the data the capability of storing a much greater range of numbers than if the binary points were fixed. Floating point refers to the "truth" of the Radix point, which refers to the decimal point or in computers it is known as the binary point that has the capabil‐ ity to float. This entails the event to occur anywhere that is relative to the significant digit of the number. Thus, a floating‐point representation, with its position indicated separately in the internal representation, is a computer's recognition of a scientific concept. Although the benefit of floating‐point representation over fixed‐point (and integer) representation is much wider in range of values, but the floating‐point format needs more storage. Hence, the implementation of high performance system requires applying efficient and fast floating‐point processor, which is competitive with the fixed‐point processor. Various types of floating‐point representation have been used in computers in the past. However, in the last decade, the IEEE 754 standard [10] has defined the representation. According to the IEEE 754 standard [10], the single precision is cho‐ sen to represent the floating‐point data. The IEEE standard specifies a way in which the three values described can be represented in a 32‐bit or a 64‐bit binary number, referred to single and double precision, respectively [11, 12]. In this project, single precision is selected to function. For the 32‐bit numbers, the first bit (MSB) specifies the sign, followed by 8 bits for the exponent, and the remaining 23 bits are used for the mantissa. This arrangement is illustrated in **Figure 5**. The sign bit is set to zero if the number is positive, and the bit is set to 1 if the number is negative. The mantissa bits are set to the fractional part of the mantissa in the original number in bits 22 to 0.


**Figure 5.** Floating‐point structure in IEEE 754 standard [10].

Floating‐point algorithm finds huge demand in industry. To conclude this section, **Table 3** summarizes the FFT algorithm application in fixed‐point and floating‐point architectures.


**Table 3.** Fixed and floating‐point FFT application.

### **2.3. Pipeline/parallel FFT algorithm**

In floating‐point format, the data are translated based on power and mantissa in the decimal system. This notation can be expanded into the binary system. Representing the data in power and mantissa system gives the data the capability of storing a much greater range of numbers than if the binary points were fixed. Floating point refers to the "truth" of the Radix point, which refers to the decimal point or in computers it is known as the binary point that has the capabil‐ ity to float. This entails the event to occur anywhere that is relative to the significant digit of the number. Thus, a floating‐point representation, with its position indicated separately in the internal representation, is a computer's recognition of a scientific concept. Although the benefit of floating‐point representation over fixed‐point (and integer) representation is much wider in range of values, but the floating‐point format needs more storage. Hence, the implementation of high performance system requires applying efficient and fast floating‐point processor, which is competitive with the fixed‐point processor. Various types of floating‐point representation have been used in computers in the past. However, in the last decade, the IEEE 754 standard [10] has defined the representation. According to the IEEE 754 standard [10], the single precision is cho‐ sen to represent the floating‐point data. The IEEE standard specifies a way in which the three values described can be represented in a 32‐bit or a 64‐bit binary number, referred to single and double precision, respectively [11, 12]. In this project, single precision is selected to function. For the 32‐bit numbers, the first bit (MSB) specifies the sign, followed by 8 bits for the exponent, and the remaining 23 bits are used for the mantissa. This arrangement is illustrated in **Figure 5**. The sign bit is set to zero if the number is positive, and the bit is set to 1 if the number is negative. The mantissa bits are set to the fractional part of the mantissa in the original number in bits 22 to 0.

Low power consumption High power consumption

**Fixed‐point FFT Floating‐point FFT**

Limited dynamic range Large dynamic range

16‐bit or 24‐bit 32‐bit

**Table 2.** Fixed‐point and floating‐point FFT processor properties.

74 Fourier Transforms - High-tech Application and Current Trends

Overflow and quantization errors Less error Higher frequency Low frequency Less silicon area More silicon area Cheaper More expensive

Floating‐point algorithm finds huge demand in industry. To conclude this section, **Table 3** summarizes the FFT algorithm application in fixed‐point and floating‐point architectures.

**Figure 5.** Floating‐point structure in IEEE 754 standard [10].

In 2009, Xilinx Logic core [13] introduced the FFT processor using the Radix structure on a chip. The introduced FFT processors were designed to offer a trade‐off between core sizes and transform time. These architectures are classified below:


The pipeline serial I/O allows to continue data processing, whereas the burst parallel I/O loads and processes data separately by using the iterative approach. It is smaller in size than the parallel but has a longer transform time. In the case of Radix II algorithm, it uses the same iterative approach as Radix IV with the difference of smaller butterfly size that differentiates it. Yet, the transformation time is longer. Finally, for the last category, based on Radix II archi‐ tecture, this variant uses a time multiplexed approach to the butterfly for an even smaller core, at the expense of longer transformation time. **Figure 6** shows the throughput versus resource among the four architectures.

### *2.3.1. FFT processor with Radix II pipelined, serial I/O*

In this design, *n*‐stage of Radix II butterfly is connected as a serial structure. Each unit of Radix II butterfly has its own RAM memory to upload and download data. The input data are stored in the RAM while the processor simultaneously performs transform calculations on the current frame of data and loads input data for the next frame of data and unloads the result of the previous frame of data. Input data are presented in sorted order. The unloaded output data can either be in bit‐reversed order or in sorted order. When sorted output data are selected, an additional memory resource is utilized. **Figure 7** illustrates the architecture of the pipeline serial I/O with individual memory bank, which connects in a serial structure.

**Figure 6.** FFT architecture resources vs. throughput.

**Figure 7.** FFT processor with Radix II pipelined, serial I/O [13].

### *2.3.2. FFT processor with Radix IV, burst I/O*

Radix IV structure accepts 4 input data simultaneously whereas Radix II takes only 2 input data at the time to perform FFT calculation. Radix IV input data uploaded into the FFT processor, cannot be uploaded while the calculation is underway. When the FFT is started, the data are loaded. After a full frame has been loaded, the core computes the transformation. The result can be downloaded after the full process is over. The data loading and unloading processes can be overlapped if the data are unloaded in digit‐reversed order. **Figure 8** shows the Radix IV structure when 4 input data are loaded for FFT calculation.

High Resolution Single-Chip Radix II FFT Processor for High-Tech Application http://dx.doi.org/10.5772/66745 77

**Figure 8.** FFT processor with Radix IV architecture [13].

### *2.3.3. FFT processor with Radix II, burst I/O*

FFT processor with burst I/O architecture utilizes Radix II butterfly calculation to execute the arithmetic structure. In spite of Radix IV with burst I/O processor, which the input data cannot be loaded and unloaded simultaneously, the Radix II processor accepts the input data during the FFT processor and data can be used concurrently when the output samples are in bit‐reversed order. The twiddle factors are stored in the ROM blocks while the output and input data are stored in a separate or mixed RAM blocks. **Figure 9** shows the Radix II struc‐ ture when 2 input data are loaded for FFT calculation.

### *2.3.4. FFT processor with Radix II lite, burst I/O*

*2.3.2. FFT processor with Radix IV, burst I/O*

**Figure 7.** FFT processor with Radix II pipelined, serial I/O [13].

**Figure 6.** FFT architecture resources vs. throughput.

76 Fourier Transforms - High-tech Application and Current Trends

structure when 4 input data are loaded for FFT calculation.

Radix IV structure accepts 4 input data simultaneously whereas Radix II takes only 2 input data at the time to perform FFT calculation. Radix IV input data uploaded into the FFT processor, cannot be uploaded while the calculation is underway. When the FFT is started, the data are loaded. After a full frame has been loaded, the core computes the transformation. The result can be downloaded after the full process is over. The data loading and unloading processes can be overlapped if the data are unloaded in digit‐reversed order. **Figure 8** shows the Radix IV FFT processor with Radix II lite architecture uses one shared RAM, hence reducing resources at the expense of an additional delay per butterfly calculation. The multiplier in this structure multiplies the real part of complex number in one clock cycle and the imaginary in the next. In this architecture, the data can be simultaneously loaded and unloaded if the output samples are in bit‐reversed order. In this architecture, sine and cosine twiddle factor coefficient will be saved in the ROM and the output data will be saved in a single RAM. Although this proposed architecture saves the resources, the throughput is significantly limited by the FFT structure due to the sequence calculations. **Figure 10** shows the Radix II lite structure when 2 input data are loaded for FFT calculations.

**Figure 9.** FFT processor with Radix II burst I/O architecture [13].

**Figure 10.** FFT processor with Radix II lite burst I/O architecture [13].
