**2. Operating principle of a front junction** *n***‐type silicon solar cell**

The operating principle of a front junction *n*‐type silicon solar cell is described in **Figure 1** via the band diagram. The *p+* emitter region is formed by 'doping' the front side of a *n*‐type silicon wafer with boron dopants in high concentration, and the conjunction of the *p+* region and the *n* substrate forms the *pn*‐junction. Due to the doping concentration gradient across the *pn*‐ junction, electrons flow by diffusion from the *n* region into the *p+* region, and holes flow from the *p+* region to the *n* region [3]. This leaves behind exposed charges on ionized boron and phosphorus doping atoms at lattice sites, which form the space charge region. These exposed charges build up an electric field that opposes the natural flow of electrons and holes until and equilibrium scenario is reached with a fixed space charge width and electric field [4]. This built‐in electric field also causes a bending of the conduction band (*EC*) and the valence band (*EV*) (**Figure 1**). When the solar cell is illuminated, photons with energy greater than the silicon band gap energy (*Eg*) are absorbed to excite electrons from the valence band to the conduction band, which generates an electron‐hole pair. The generated electrons and holes can diffuse within the bulk of the solar cell until they reach the space charge region, if they avoid recombination or trapping by defects. Then, the electric field at the *pn*‐junction separate these carriers by sweeping electrons to the *n* region and holes to the *p+* region. In the case of illumination, quasi‐Fermi levels (*EFn* for electrons and *EFp* for holes) are used to analyse the solar cell in non‐equilibrium (**Figure 1**). The electrical contact to the front *p+* emitter region is described as an ohmic contact while the metal contact to *n* region, without any heavy doping, is generally a Schottky‐type because the metal contact to *n* silicon induces a barrier to majority carrier (electrons) [3]. In order to obtain high cell efficiency, proper doping profiles in both the *p+* and the *n* regions are necessary to reduce the contact resistance and the metal‐induced recombination.

#### **2.1. Solar cell parameters**

generating electron‐hole pairs that are separated by a *pn*‐junction and then flow to electrical contacts on the front and back sides to perform work in external circuit, as shown in the **Figure 1**.In addition, due to several advantages of *n*‐type (typically phosphorus‐doped) silicon wafers over *p*‐type (typically boron‐doped), including better tolerance to common impurities (e.g. iron) [1], higher bulk lifetime and no light‐induced degradation (LID) [2], *n*‐type silicon solar cells with high efficiency can be potentially more cost‐effective than *p*‐type silicon solar cells. Hence, the focus in this chapter will be on high‐efficiency front junction *n*‐type crystalline silicon solar cell with both sides passivated and contacted, including their operating principle,

**Figure 1.** Schematic energy band diagram of a front junction *n*‐type silicon solar cell in a non‐equilibrium (with illumi‐

The operating principle of a front junction *n*‐type silicon solar cell is described in **Figure 1** via the band diagram. The *p+* emitter region is formed by 'doping' the front side of a *n*‐type silicon

*n* substrate forms the *pn*‐junction. Due to the doping concentration gradient across the *pn*‐ junction, electrons flow by diffusion from the *n* region into the *p+* region, and holes flow

and phosphorus doping atoms at lattice sites, which form the space charge region. These exposed charges build up an electric field that opposes the natural flow of electrons and holes until and equilibrium scenario is reached with a fixed space charge width and electric field [4]. This built‐in electric field also causes a bending of the conduction band (*EC*) and the valence band (*EV*) (**Figure 1**). When the solar cell is illuminated, photons with energy greater than the silicon band gap energy (*Eg*) are absorbed to excite electrons from the valence band to the conduction band, which generates an electron‐hole pair. The generated electrons and holes can diffuse within the bulk of the solar cell until they reach the space charge region, if they avoid recombination or trapping by defects. Then, the electric field at the *pn*‐junction separate

region to the *n* region [3]. This leaves behind exposed charges on ionized boron

region and the

**2. Operating principle of a front junction** *n***‐type silicon solar cell**

wafer with boron dopants in high concentration, and the conjunction of the *p+*

advanced cell structures, surface passivation and fabrication schemes.

nation), including photon absorption, carrier generation and separation.

from the *p+*

94 Nanostructured Solar Cells

According to the *ideal diode law* (one diode model), an actual silicon solar cell with parasitic series resistance (*Rs*) and shunt resistance (*R*sh) can be described by an equivalent circuit containing one diode as shown in **Figure 2** and is often expressed as [3, 4]

**Figure 2.** Equivalent circuit of a front junction *n*‐type silicon solar cell with parasitic series resistance (*Rs*) and shunt resistance (*R*sh) [3, 4].

$$I = I\_L - I\_0 \left\{ \exp\left[\frac{V + IR\_s}{\left(\frac{nkT}{q}\right)}\right] - 1 \right\} - \frac{V + IR\_s}{R\_{sh}} \tag{1}$$

where *I* is the terminal current, *IL* is the light‐generated current with illumination, *I0* is the saturation current (the solar cell leakage current in the dark), *V* is the terminal voltage, *q* is the electronic charge, *k* is the Boltzmann's constant, *T* is the absolute temperature and *n* is the ideality factor that is typically in the range of 1 and 2.

The resulting *I‐V* curve with illumination is often plotted as output power, as shown in **Figure 3**. The maximum power point (MPP) is also indicated at (*V*mp, *I*mp). The fill factor (*FF*) is another important parameter determining cell performance, and it is a metric of the *pn*‐ junction quality and the parasitic resistance of a finished silicon solar cell [3]. *FF* is a measure of the squareness of the *I‐V* curve and defined as

**Figure 3.** A typical representation of an illuminated *I‐V* curve as well as output power curve as a function of voltage, including indication of short circuit current (*I*sc), open circuit voltage (*V*oc) and the maximum power point (*V*oc and *I*sc) [3, 4].

$$FF = \frac{I\_{\rm mp} V\_{\rm mp}}{I\_{\rm sc} V\_{\rm oc}} \tag{2}$$

where *I*mp and *V*mp are the corresponding current and voltage at the maximum power point, *I*sc is the current at short circuit condition ( = 0) and *V*oc is the voltage at open circuit condition ( = 0) [3, 4]. Finally, the most important metric of solar cell performance is the energy conversion efficiency and is defined as

$$
\eta = \frac{I\_{\text{sc}} V\_{\text{oc}} FF}{P\_{\text{in}}} \tag{3}
$$

where *P*in is the total incident light power striking the solar cell [3]. According to the detailed balance limit of efficiency, the maximum efficiency of an ideal single‐junction crystalline silicon solar cell with *Eg* of 1.12 eV at 25°C is about 30% [5]. Its major fundamental mechanisms of power loss include (1) photons with energy less than 1.12 eV (<*Eg*) cannot be absorbed and directly transmitted through the cell, (2) the excessive energy in photons with high energy (>*Eg*) is wasted via thermallization as the generated electron‐hole pair relax back to the edges of carrier band, (3) each absorbed photon creates only one electron‐hole pair regardless of its energy, and (4) as shown in **Figure 1**, quasi‐Fermi levels (*EFn* and *EFp*) stay within energy gap ( − <sup>&</sup>lt; ), hence *pn*‐junction silicon solar cells are inherently capable of giving voltage output smaller than the potential corresponding to its band gap energy [3, 5].

#### **2.2.** *pn***‐junction formation**

junction quality and the parasitic resistance of a finished silicon solar cell [3]. *FF* is a measure

**Figure 3.** A typical representation of an illuminated *I‐V* curve as well as output power curve as a function of voltage, including indication of short circuit current (*I*sc), open circuit voltage (*V*oc) and the maximum power point (*V*oc and *I*sc)

> mp mp sc oc *I V*

where *I*mp and *V*mp are the corresponding current and voltage at the maximum power point, *I*sc is the current at short circuit condition ( = 0) and *V*oc is the voltage at open circuit condition ( = 0) [3, 4]. Finally, the most important metric of solar cell performance is the energy

> sc oc in *I V FF P*

voltage output smaller than the potential corresponding to its band gap energy [3, 5].

where *P*in is the total incident light power striking the solar cell [3]. According to the detailed balance limit of efficiency, the maximum efficiency of an ideal single‐junction crystalline silicon solar cell with *Eg* of 1.12 eV at 25°C is about 30% [5]. Its major fundamental mechanisms of power loss include (1) photons with energy less than 1.12 eV (<*Eg*) cannot be absorbed and directly transmitted through the cell, (2) the excessive energy in photons with high energy (>*Eg*) is wasted via thermallization as the generated electron‐hole pair relax back to the edges of carrier band, (3) each absorbed photon creates only one electron‐hole pair regardless of its energy, and (4) as shown in **Figure 1**, quasi‐Fermi levels (*EFn* and *EFp*) stay within energy gap

), hence *pn*‐junction silicon solar cells are inherently capable of giving

h

*I V* <sup>=</sup> (2)

= (3)

*FF*

of the squareness of the *I‐V* curve and defined as

conversion efficiency and is defined as

( − <sup>&</sup>lt;

[3, 4].

96 Nanostructured Solar Cells

To form the *pn*‐junction on *n*‐type crystalline silicon wafers, a typical approach is to diffuse boron atoms into the silicon substrates at high temperature. This can be accomplished by several techniques including depositing boron‐doped silicon oxide via atmospheric pressure chemical vapour deposition (APCVD) and then thermal annealing at high temperature [6]. The boron emitter can be also formed by spinning‐on orthoboric acid (H3BO3) solutions [7, 8], which is considered to be a hydrate of boric trioxide (B2O3). During the subsequent thermal annealing, the boron oxide reacts with silicon to form SiO2 and B, which diffuses into silicon at high temperature, as described by

$$\text{2B}\_2\text{O}\_3 + \text{3Si} \rightarrow \text{3SiO}\_2 + \text{4B} \tag{4}$$

Screen‐printed boron emitters have also been explored by printing proper boron‐containing paste followed by a thermal drive‐in diffusion [9]. Another promising and widely used technology is called 'BBr3 diffusion' that involves a direct thermal diffusion of boron atom from a liquid boron tribromide (BBr3) source [10]. In this process, pure nitrogen (N2) carrier gas flows into a bubbler containing liquid BBr3, which creates and transports gaseous BBr3 into the quartz tube and deposits on the surface of silicon wafers loaded in a quartz boat [11]. During this deposition stage, a boron oxide layer is formed on the silicon wafer surface in the oxygen (O2) ambient according to

$$\text{4BBr}\_3 + \text{3O}\_2 \rightarrow \text{2B}\_2\text{O}\_3 + \text{6Br}\_2\tag{5}$$

This thin boron oxide layer contains very high concentration of inactive boron element on the silicon surface. So, a high temperature anneal (typically ≥950°C) is necessary to activate boron atoms and diffuse them into silicon bulk to form the *p+* region through the reaction (4) [11]. During this process, a SiO2/B2O3 stack or the borosilicate glass (BSG) layer is formed on the surface that has to be removed to achieve better dielectric surface passivation quality. By controlling gas flow rate, diffusion temperature and duration, proper boron dopant profiles can be engineered [12].

Because all of these junction formation technologies suffer from wrap‐around or naturally double‐sided diffusion process, etching off one side or depositing a mask layer on one side is needed to prevent junction shunting. Therefore, ion implantation has been investigated and implemented as a promising alternative technology that has a unique characteristic to provide single‐sided diffusion and facilitates the development of next‐generation cells [13]. It can simplify the junction formation process by eliminating the extra processes of masking and etching. In addition, ion implantation offers other technical advantages, including (1) high junction uniformity, (2) flexibly and precisely controlled dopant profiles, (3) elimination of the edge isolation process, (4) capability of patterned doping for selective doping and (5) elimi‐ nation of the dopant glass (i.e. BSG layer) removal process [14]. It is important to note that ion implantation forms an amorphous layer on the surface [15], therefore, a very high temperature (≥1000°C) is needed to recover lattice damage and activate dopants [16, 17]. In addition, proper ion dose, implant energy and anneal conditions are essential to obtain desired dopant profiles [18, 19]. Current ion implantation tools have throughput of more than 2000 wafers per h but the capex and maintenance is much higher than the traditional diffusion tubes [13]. **Figure 4** shows two examples of boron emitter profiles measured by electrochemical capacitance‐ voltage (ECV) profiling technique, revealing that the boron concentration decreases towards the silicon wafer surface due to the higher solubility of boron in the SiO2 layer than in silicon bulk [20].

**Figure 4.** Two measured ECV profiles of ion‐implanted boron emitters with sheet resistance of 80 and 200 Ω/□ [16, 20].

#### **2.3. Metallization**

In order to extract electrical power from a silicon solar cell, metal contacts have to be applied to the front emitter and the rear base to collect the generated electron‐hole pairs. The collected electrons flow through the *n+* regions into the external circuit to power the load and then recombine with the generated holes. In order to minimize the power loss, the electrical contact needs to have low contact resistance with doped silicon regions, low metallic resistance in the formed structure, good adhesion to silicon and reliable solderability for cell interconnection for module production [21]. There are several metallization technologies that are typically used in photovoltaic industry for research and production. First, the screen printing of metal pastes to form electrical contact is the most widely applied technology to manufacture silicon solar cells in photovoltaic industry today because it is very robust, simple, high‐throughput, low‐ cost and reliable method [21]. Its first application dates back to 1970s. In this metallization process, a metal paste is printed through a patterned screen with well‐designed openings onto a wafer lying under the screen. This screen acts as a mask, consisting of a mesh of wires partially covered with an emulsion. By properly optimizing some key process parameters, including the snap‐off distance between screen and wafer, the printing pressure (pressing the screen against the wafer surface and pushing the metal paste onto wafer surface) and the printing speed, printed gridline with high aspect ratio can be obtained today with line width of ≤60 µm and height of ∼25 µm (**Figure 5(A)**) [16]. Then, the contact formation is realized by a firing process in a conveyor belt furnace that fires the metal pastes through the passivation layer and anti‐reflection coating (typically silicon nitride SiNx) on the front. During this firing process, hydrogen (H) is released from the hydrogen‐rich SiNx layer into the crystalline silicon to passivate bulk and interface defects to increase the cell performance [23, 24].

(≥1000°C) is needed to recover lattice damage and activate dopants [16, 17]. In addition, proper ion dose, implant energy and anneal conditions are essential to obtain desired dopant profiles [18, 19]. Current ion implantation tools have throughput of more than 2000 wafers per h but the capex and maintenance is much higher than the traditional diffusion tubes [13]. **Figure 4** shows two examples of boron emitter profiles measured by electrochemical capacitance‐ voltage (ECV) profiling technique, revealing that the boron concentration decreases towards the silicon wafer surface due to the higher solubility of boron in the SiO2 layer than in silicon

**Figure 4.** Two measured ECV profiles of ion‐implanted boron emitters with sheet resistance of 80 and 200 Ω/□ [16, 20].

In order to extract electrical power from a silicon solar cell, metal contacts have to be applied to the front emitter and the rear base to collect the generated electron‐hole pairs. The collected

recombine with the generated holes. In order to minimize the power loss, the electrical contact needs to have low contact resistance with doped silicon regions, low metallic resistance in the formed structure, good adhesion to silicon and reliable solderability for cell interconnection for module production [21]. There are several metallization technologies that are typically used in photovoltaic industry for research and production. First, the screen printing of metal pastes to form electrical contact is the most widely applied technology to manufacture silicon solar cells in photovoltaic industry today because it is very robust, simple, high‐throughput, low‐ cost and reliable method [21]. Its first application dates back to 1970s. In this metallization process, a metal paste is printed through a patterned screen with well‐designed openings onto a wafer lying under the screen. This screen acts as a mask, consisting of a mesh of wires partially covered with an emulsion. By properly optimizing some key process parameters, including the snap‐off distance between screen and wafer, the printing pressure (pressing the screen against the wafer surface and pushing the metal paste onto wafer surface) and the printing

regions into the external circuit to power the load and then

bulk [20].

98 Nanostructured Solar Cells

**2.3. Metallization**

electrons flow through the *n+*

**Figure 5.** (A) Optical scope image of screen‐printed gridline. (B) Scanning electron microscope image of photolitho‐ graphically defined and plated gridline. (C) Optical scope image of laser‐opened point contact pattern for physical va‐ pour deposited metallization [16, 22].

Second contact technology involves metal plating approach that offers low contact resistivity, good gridline conductivity and narrow gridline width (low metal shading). Thus, it is a promising alternative to the screen‐printing technology but metal plating typically requires an initial patterning step to create openings in a dielectric masking layer for the subsequent self‐aligned metallization [21]. The openings can be defined by photolithography [10] or laser ablation, and then the contacts are applied by electroless plating [25] or a combination of light‐ induced plating (LIP) and electroplating in an inline plating machine [26]. For industrially feasible plated metallization, nickel (Ni) layer is typically used, first to obtain low contact resistivity and prevent copper (Cu) diffusion followed by copper plating to provide excellent line conductivity and low material cost (compared to silver) [27]. The gridline width after plating is typically around 30 µm, with height of ∼15 µm, as shown in **Figure 5(B)**.

Third contact technology involves physical vapour deposition (PVD) that is attractive because of its potential advantages of lower specific contact resistance [28], reduced wafer breakage and processing of thinner wafers due to non‐contacting process. In addition, a thin (1∼2 µm) PVD aluminium (Al) on the entire rear area is sufficient to meet the required electrical conductance for large area silicon solar cells, which can lead to less wafer bow and less metal material consumption [22]. In order to form the contact between silicon and PVD metal, patterned openings through a dielectric masking layer are needed for the subsequent PVD metallization, which is typically created by laser ablation. **Figure 5(C)** shows an example of rear point contact pattern (300 × 300 µm2 ) after laser ablation, with the opening diameter of ≤40 µm and metal coverage of ≤1.4% [22]. To obtain a good solder contact to the PVD Al side, deposition of a double layer of Ni:V/Ag on top of PVD Al layer is often implemented to provide an excellent solderability and long‐term stability for module manufacturing [29].
