**5. Simulation results on various circuits**

Four typical simulation cases are presented in this section to validate the proposed model and its computational implementation. All examples have been derived from the same generic 65 nm CMOS technology. In the first example, the RWDD transient response of an isolated transistor subjected to an alpha particle has been compared to TCAD simulation. In the second example, a CMOS inverter has been considered to the effect of the feedback of the node voltage on the modulation of the space charge region related to the impacted junction. The two last examples concern a SRAM cell and a master-slave D flip-flop, with an isolated output, illustrating the internal/external solutions for circuit solving and charge-sharing effects at the level of circuit sensitive nodes.

#### **5.1. Model validation—isolated NMOS**

(19)

Eqs. (10)–(19) constitute the core model implemented in the code RWDDCPP for CMOS inverter and SRAM cell solving. In Eq. (9), NMOS and PMOS source-to-drain currents are analytically modeled using the EPFL-EKV model 2.6 [20, 21], here implemented in C++ as numerical functions (IDN and IDP) having two arguments (see **Figure 5**). The EKV 2.6 MOSFET model is a predictive (scalable) compact model for the simulation of submicron CMOS technologies. It was built taking into account fundamental physical characteristics of the MOS structure. The model offers a continuous modeling of the different regimes of the transistor operation (weak, moderate and strong inversion), which is mandatory for circuit modeling. The version 2.6 takes into account numerous essential issues for the transistor modeling such as the effects of the doping profile, substrate effects, process-related aspects (oxide thickness, effective channel length and width and junction depth), mobility effects due to vertical and lateral electric fields, the velocity saturation, short-channel effects, etc. Section 5 details several

For more complex circuit architectures than a single inverter or a SRAM cell, an external SPICE circuit simulator can be otherwise used in the place of the internal subroutine for circuit solving. In this case, the circuit simulator is instantiated in interactive mode by the executable code with a circuit netlist corresponding to the simulated structure. Current source(s) emu‐ lating the transient collected current(s) at the different circuit nodes is (are) automatically added to the netlist by the RWDDCPP program. At each time step of the simulation, the magnitude of each current source is updated as a function of the number of charge packets collected by the corresponding biased junction, following Eq. (5). Then, the SPICE simulator computes the new voltages on the circuit nodes and finally, from Eqs. (6) and (7), the width of the space charge region(s) and the distribution of the electrical field can be updated, time step by time step. The whole circuit counteraction to the radiation transient can then be taken into account. This approach has been successfully implemented in this work using both NGSPICE

Four typical simulation cases are presented in this section to validate the proposed model and its computational implementation. All examples have been derived from the same generic 65 nm CMOS technology. In the first example, the RWDD transient response of an isolated transistor subjected to an alpha particle has been compared to TCAD simulation. In the second example, a CMOS inverter has been considered to the effect of the feedback of the node voltage on the modulation of the space charge region related to the impacted junction. The two last examples concern a SRAM cell and a master-slave D flip-flop, with an isolated output,

examples of simulations using this code RWDDCPP.

**4.2. SPICE simulator**

126 Modeling and Simulation in Engineering Sciences

[22] and ELDO [23] simulators.

**5. Simulation results on various circuits**

This simplest case corresponds to an isolated transistor subjected to single event irradiation. The radiation-induced collected current and charge have been separately computed using the RWDDCPP code and the commercial Synopsys TCAD simulation platform [24]. **Figure 6** (top) shows the 3D structure of a single NMOS transistor implanted in a Pwell region (delimited in depth by a deep N-well) built in Synopsys Sentaurus using geometrical and technological parameters corresponding to the considered 65 nm CMOS technology.

**Figure 6.** *Top*: 3D electron density distribution obtained by TCAD simulation at 2 ps after an alpha particle strikes the drain of an OFF-state isolated NMOS transistor (designed in 65 nm CMOS technology). To facilitate the picture analy‐ sis, spacers, gate material and isolation oxide are not shown here. The long arrow indicates the location and direction of the ionizing particle strike. *Bottom*: Current and charge collected by an isolated OFF-state NMOS transistor after the alpha particle strike computed by TCAD and by the RWDD model. (Reprinted with permission from Autran et al. [10], © 2014, Elsevier).

**Figure 6** also shows the electron density 2 ps after the passage of an alpha particle (incident energy of 5 MeV) at the level of the drain of the transistor maintained in the OFF-state. A similar structure has been built and simulated with the RWDDCPP program; the main simulation parameters and options in both approaches have been forced to the same values: drift-diffusion model, constant carrier mobility for electrons (400 cm2 /V/s) and holes (200 cm2 /V/s), identical minority carrier lifetime (10−8 s), etc. **Figure 6** (bottom) shows the transient current and the corresponding charge collected by the drain of the NMOS transistor subjected to a 5 MeV alpha particle striking the center of the drain perpendicularly to the device. A good agreement between results obtained with RWDD and TCAD are shown in this graph. One can observe a few differences between the two curves, especially in the early stages of the transient, mainly due to: (i) the arrival of discrete charge packets at the level of the collecting drain contact in the RWDD approach which induces inherent granularities; and (ii) the characteristic time (2 ps) of the Gaussian time distribution used in the TCAD simulation. Values of the collected charges obtained from TCAD and RWDD are very close at the end of the transient event, with a difference limited to a maximum of 15%, indicating that both modeling approaches have very similar charge collection efficiencies. We confirmed this point by comparing the results given by RWDD and TCAD concerning the space charge region width and the electric field: a very good agreement between the two series of results was obtained and then reiterated for different bias conditions. This shows that both transport and charge collection processes of the RWDD model provide results very similar to those of TCAD simulations without employing any fitting or unphysical parameter. This is a significant advantage of the RWDD approach over other previously developed methods (see [25] for example).

#### **5.2. Transient simulation of a CMOS inverter**

We explored next the case of the same NMOS transistor but embedded in a CMOS inverter, as shown in **Figure 7**. In the present case, the voltage node V2 is not fixed, as was the case for the study of a NMOS transistor standalone; the operation of the second transistor of the CMOS inverter (see **Figure 7**) leads to the variation of the voltage V2 during the transient process. These node bias changes may modify the charge collection efficiency at the drain of the NMOS transistor, through the variation of both E and WSCR by a feedback process. In the following,

**Figure 7.** Schematics illustrating the differences in the charge collection process between an isolated NMOS and the same structure embedded in a CMOS inverter (OFF-state). The drain junction is biased at fixed VDD in the transistor alone, whereas it is subjected to the node potential V2 in the inverter. This voltage is susceptible to vary during the transient event due to circuit retroaction. (Reprinted with permission from Autran et al. [10], © 2014, Elsevier).

this case is called "with SCR feedback." By opposition, we name "without SCR feedback" the case when the same (fixed) SCR parameters are maintained during the entire transient simulation. With respect to the charge collection process, this last case is equivalent to that of considering a standalone NMOS transistor. Simulated transients of the CMOS inverter (under the initial conditions V1 = 0 and V2 = VDD) obtained with the RWDD model when a 5 MeV alpha particle passes across the NMOS drain are shown in **Figure 8**. These results reveal the influence of the circuit feedback on the SCR characteristics, through the time changes of V2. Without the circuit feedback on the SCR, the radiation effect is to turn V2 to negative values for a period of time equal to about 30 ps. This obviously evidences a hazardous condition for a cross-coupled inverter in the case of an SRAM cell (somewhat reduced by the gate capacitance in the case where the second inverter is coupled). **Figure 8** illustrates an important issue concerning the inverter operation: the hazardous condition described above persists 2× as long when SCR feedback is activated.

particle striking the center of the drain perpendicularly to the device. A good agreement between results obtained with RWDD and TCAD are shown in this graph. One can observe a few differences between the two curves, especially in the early stages of the transient, mainly due to: (i) the arrival of discrete charge packets at the level of the collecting drain contact in the RWDD approach which induces inherent granularities; and (ii) the characteristic time (2 ps) of the Gaussian time distribution used in the TCAD simulation. Values of the collected charges obtained from TCAD and RWDD are very close at the end of the transient event, with a difference limited to a maximum of 15%, indicating that both modeling approaches have very similar charge collection efficiencies. We confirmed this point by comparing the results given by RWDD and TCAD concerning the space charge region width and the electric field: a very good agreement between the two series of results was obtained and then reiterated for different bias conditions. This shows that both transport and charge collection processes of the RWDD model provide results very similar to those of TCAD simulations without employing any fitting or unphysical parameter. This is a significant advantage of the RWDD approach over

We explored next the case of the same NMOS transistor but embedded in a CMOS inverter, as shown in **Figure 7**. In the present case, the voltage node V2 is not fixed, as was the case for the study of a NMOS transistor standalone; the operation of the second transistor of the CMOS inverter (see **Figure 7**) leads to the variation of the voltage V2 during the transient process. These node bias changes may modify the charge collection efficiency at the drain of the NMOS transistor, through the variation of both E and WSCR by a feedback process. In the following,

**Figure 7.** Schematics illustrating the differences in the charge collection process between an isolated NMOS and the same structure embedded in a CMOS inverter (OFF-state). The drain junction is biased at fixed VDD in the transistor alone, whereas it is subjected to the node potential V2 in the inverter. This voltage is susceptible to vary during the transient event due to circuit retroaction. (Reprinted with permission from Autran et al. [10], © 2014, Elsevier).

other previously developed methods (see [25] for example).

**5.2. Transient simulation of a CMOS inverter**

128 Modeling and Simulation in Engineering Sciences

**Figure 8.** RWDD simulation of the impact of an ionizing particle on an off-state NMOS transistor embedded in a CMOS inverter with and without the feedback effect of the space charge region (width and electric field dependence on V2) on the collected current (top) and on the voltage on the struck node (bottom). (Reprinted from Autran et al. [10], © 2014, Elsevier).

**Figure 8** also shows that the shape of the transient current is essentially modified when the "SCR feedback" is taken into account. The results show a plateau on the collected current curve, in good accordance with TCAD simulations published in [2]. In the case "without feedback," the transient current shows a classical shape (being composed from a fast drift component and a slower decay) because the SCR of the struck NMOS is maintained constant without feedback. When the "SCR feedback" is considered, the SCR of the struck NMOS can vary when V2 changes. As explained by Ferlet-Cavrois et al. [2], when the NMOS is disturbed by a single event, it momentarily biases the on-state load PMOS transistor in a condition for drain current to flow. After a short-duration current peak corresponding to the output capacitance support of the drain voltage at its pre-strike value, the drain voltage collapses, which causes a reduction of both the electric field and the extension of the space charge region; as a consequence, the NMOS single event current becomes governed by the depressed drain voltage (that impacts the collection efficiency of the junction) and the compensating PMOS transistor drive current. The result of this dynamic interaction of the node voltage and the PMOS transient current is a characteristic current equilibrium or "plateau," as shown in **Figure 8**. The amplitude of this current plateau is linked to the PMOS drive, and the duration of the plateau is synchronous with the depressed drain voltage. As soon as most of the deposited charge flows out of the struck transistor, the current flow cannot be maintained, the equilibrium conditions relax, the drain voltage recovers and the current pulse again decreases toward zero [2, 26]. This second example illustrates the importance of device coupling effects at circuit-level and its conse‐ quences on the charge collection dynamics in the impacted device. The soft-error rate conse‐ quence of such effects has to be investigated in future works, notably in SRAM cells composed of two cross-coupled inverters for which a very similar behavior as highlighted in **Figure 8** is expected at the level of the impacted OFF-state transistor.

#### **5.3. Alpha-particle SEU in SRAM**

In this third example, the single-event upset alpha particle cross-section of a 65 nm SRAM cell has been simulated using the RWDD approach and compared with experiments. The alpha cross-section experimental measurement was performed using an Americium 241 source (3.7 MBq), at room temperature and under nominal voltage 1.2 V), following all the recom‐ mendations of the JESD98A test standard [27]. Since the alpha source has a high activity, several thousand errors are measured and cross-section uncertainties are very low.

For the RWDD simulation, several additional assumptions have been introduced to estimate the electrical response of the 65 nm bit cell: (i) all of the electron-hole pairs generated inside or below the deep N-well (see the structure of the transistor in **Figure 6** top) are not taken into account; (ii) minorities charge carriers that reach well limits are considered as recombined and are eliminated from the simulation. **Figure 9** (top) shows the 65 nm bit cell composed of a centered Nwell and two Pwells. The four drains of the transistors constituting the two inverters have been placed in structure and connected to the corresponding nodes in the circuit netlist. The total simulation area is larger than the bit cell area to take into account an alpha particle with a high tilt angle, which strikes around the bit cell. The maximum tilt angle has been calculated using the range of the alpha particle and the thickness of the back-end layer. We computed a simulated cross-section by performing simulations for several thousand impacts of alpha particles, considering random impact locations and particles with random directions; the number of upsets was divided by the simulated fluency.

Charge Collection Physical Modeling for Soft Error Rate Computational Simulation in Digital Circuits http://dx.doi.org/10.5772/64277 131

**Figure 9.** *Top*: Schematic representation of the 65 nm bit cell with the charge deposited by an alpha particle and com‐ puted by the RWDD model. The figure shows that in the impacted drain area, the electric field has extracted most of the deposited charge. *Bottom*: Corresponding bit cell alpha-simulated cross section compared with the experimental value (Reprinted With permission from Glorieux et al. [12], © 2014, IEEE).

The measured alpha particle cross-section of the 65 nm bit cell is compared with their simulated counterparts in **Figure 9** (bottom). Three different voltages from 1.08 to 1.32 V have been considered in simulation. This figure illustrates the nice agreement between the results obtained with the RWDD model and experimental measurements. **Figure 9** also demonstrates that this model is able to take into account the supply voltage dependence for the evaluation of the bit cell cross-section. Unfortunately, the comparison between experiment and simulation was not possible for this bit cell at both 1.1 and 1.3 V because experimental data were not available.

#### **5.4. Flip-flop circuit**

a slower decay) because the SCR of the struck NMOS is maintained constant without feedback. When the "SCR feedback" is considered, the SCR of the struck NMOS can vary when V2 changes. As explained by Ferlet-Cavrois et al. [2], when the NMOS is disturbed by a single event, it momentarily biases the on-state load PMOS transistor in a condition for drain current to flow. After a short-duration current peak corresponding to the output capacitance support of the drain voltage at its pre-strike value, the drain voltage collapses, which causes a reduction of both the electric field and the extension of the space charge region; as a consequence, the NMOS single event current becomes governed by the depressed drain voltage (that impacts the collection efficiency of the junction) and the compensating PMOS transistor drive current. The result of this dynamic interaction of the node voltage and the PMOS transient current is a characteristic current equilibrium or "plateau," as shown in **Figure 8**. The amplitude of this current plateau is linked to the PMOS drive, and the duration of the plateau is synchronous with the depressed drain voltage. As soon as most of the deposited charge flows out of the struck transistor, the current flow cannot be maintained, the equilibrium conditions relax, the drain voltage recovers and the current pulse again decreases toward zero [2, 26]. This second example illustrates the importance of device coupling effects at circuit-level and its conse‐ quences on the charge collection dynamics in the impacted device. The soft-error rate conse‐ quence of such effects has to be investigated in future works, notably in SRAM cells composed of two cross-coupled inverters for which a very similar behavior as highlighted in **Figure 8** is

In this third example, the single-event upset alpha particle cross-section of a 65 nm SRAM cell has been simulated using the RWDD approach and compared with experiments. The alpha cross-section experimental measurement was performed using an Americium 241 source (3.7 MBq), at room temperature and under nominal voltage 1.2 V), following all the recom‐ mendations of the JESD98A test standard [27]. Since the alpha source has a high activity,

For the RWDD simulation, several additional assumptions have been introduced to estimate the electrical response of the 65 nm bit cell: (i) all of the electron-hole pairs generated inside or below the deep N-well (see the structure of the transistor in **Figure 6** top) are not taken into account; (ii) minorities charge carriers that reach well limits are considered as recombined and are eliminated from the simulation. **Figure 9** (top) shows the 65 nm bit cell composed of a centered Nwell and two Pwells. The four drains of the transistors constituting the two inverters have been placed in structure and connected to the corresponding nodes in the circuit netlist. The total simulation area is larger than the bit cell area to take into account an alpha particle with a high tilt angle, which strikes around the bit cell. The maximum tilt angle has been calculated using the range of the alpha particle and the thickness of the back-end layer. We computed a simulated cross-section by performing simulations for several thousand impacts of alpha particles, considering random impact locations and particles with random directions;

several thousand errors are measured and cross-section uncertainties are very low.

expected at the level of the impacted OFF-state transistor.

the number of upsets was divided by the simulated fluency.

**5.3. Alpha-particle SEU in SRAM**

130 Modeling and Simulation in Engineering Sciences

The final step was to confirm the ability of the RWDD model to simulate more complex circuit architectures and considering a large LET range. For this purpose, we simulated the heavy ion cross-section of a 65 nm flip-flop and we compared the simulation results with experimental measurements. To model the geometrical structure of the flip-flop, we took into account simulation hypothesis identical to those considered for the SRAM. Heavy ion measurements have been performed on a 65 nm test-chip, at nominal supply voltage and room temperature. The measurements have been performed at the RADEF facility, Jyväskylä University (Finland), with a fluency of 106 heavy ions per square centimeter for five different ion LETs.

The functional schematic of the considered flip-flop (classical, unhardened master slave Dflip-flops) is shown in **Figure 10** (top). Data are transmitted between the master and slave latch using a pass gate. In this study, we include in the modeled structure all drains of all the transistors present in the flip-flop, unlike to our previous simulation works that only consid‐ ered the bistable transistors [6, 28]. In this way, all of the possible upset mechanisms can be taken into account. This is specifically the case when an ionizing particle strikes a clock network transistor that can involve the latching of new data, these mechanisms being particularly important for high LET ions.

**Figure 10.** *Top*: Schematic of the modeled 65 nm flip-flop that corresponds to master-slave D flip-flop, with an isolated output. *Bottom*: Comparison of simulated and measured heavy-ion cross-sections of the 65 nm flip-flop. (Adapted with permission from Glorieux et al. [12]).

**Figure 10** (bottom) shows the measured and simulated heavy ion cross-section of the flip-flop. This graph shows the excellent correlation of the simulated cross-section with the measure‐ ments for low LET ions. For higher LET impacts, the non-modeled multi-cell upsets induces a difference between measured and simulated data. Several reasons can explain these differ‐ ences:

**-** The main reason for the lack of accuracy is the contribution of non-modeled multi-cell upset (MCU) in the measured data: indeed, flip-flop cross-sections have been measured in a shift register structure where flip-flops are next to each other. Thus, a single ionizing particle can upset several flip-flops. Experimentally, this phenomenon has been verified (some MCUs have been recorded) but it was not possible to precisely quantify it since the number of stages in the shifter structure is not constant between the physical neighbor's cells, and the test has been performed dynamically.

The measurements have been performed at the RADEF facility, Jyväskylä University (Finland),

The functional schematic of the considered flip-flop (classical, unhardened master slave Dflip-flops) is shown in **Figure 10** (top). Data are transmitted between the master and slave latch using a pass gate. In this study, we include in the modeled structure all drains of all the transistors present in the flip-flop, unlike to our previous simulation works that only consid‐ ered the bistable transistors [6, 28]. In this way, all of the possible upset mechanisms can be taken into account. This is specifically the case when an ionizing particle strikes a clock network transistor that can involve the latching of new data, these mechanisms being particularly

**Figure 10.** *Top*: Schematic of the modeled 65 nm flip-flop that corresponds to master-slave D flip-flop, with an isolated output. *Bottom*: Comparison of simulated and measured heavy-ion cross-sections of the 65 nm flip-flop. (Adapted with

**Figure 10** (bottom) shows the measured and simulated heavy ion cross-section of the flip-flop. This graph shows the excellent correlation of the simulated cross-section with the measure‐ ments for low LET ions. For higher LET impacts, the non-modeled multi-cell upsets induces a difference between measured and simulated data. Several reasons can explain these differ‐

**-** The main reason for the lack of accuracy is the contribution of non-modeled multi-cell upset (MCU) in the measured data: indeed, flip-flop cross-sections have been measured in a shift register structure where flip-flops are next to each other. Thus, a single ionizing

heavy ions per square centimeter for five different ion LETs.

with a fluency of 106

132 Modeling and Simulation in Engineering Sciences

important for high LET ions.

permission from Glorieux et al. [12]).

ences:

**-** A second reason that can explain the differences in the cross-section at high LET energies concerns modeling of the charge carrier reaching the good limits and more specifically the approximation used to calculate this charge. Charge packets that reach the good interface are considered in the charge transport model as recombined and are then removed from the simulation. Another limitation concerns the impact location of the ionizing particle: the current implementation of our model is not totally adequate for an impact close to the good interface. Owing to the punctual character of the track profile, all charge packets are generated on the impacted well since, if taking into account the particle track radius, a non-negligible part of these packets should be considered in the adjacent well(s).

The SEU sensitive areas for each simulated LET can be identified on the flip-flop layout using the RWDD model, as in the case for other Monte Carlo simulation methods [29, 30]. The map of the simulated impacts inducing an upset for each ion LET is illustrated in **Figure 11**. This map has been generated on the slave latch of the flip-flop, with a high logic state stored in the latch. This figure indicates that, as the LET of the ionizing particles increases, the sensitive transistors are more abundant. The explanation is that upsets are uniquely produced on bistable transistors for ions with low LET, while for higher ion LET, other transistors (clock and pass gate transistors) become sensitive to SEU, in addition to those impacted at low LET.

**Figure 11.** Mapping of the upsets in the slave latch, for different ion LET. The number of SEU-sensitive transistors in‐ creases with the LET of the incident heavy ions. The location labeled "detailed impact" has been considered for chargesharing analysis discussed in the text. (Adapted with permission from Glorieux et al. [12]).

Finally, in order to evaluate the capability of the RWDD model to simulate charge-sharing mechanisms, a dedicated study has been performed. The SEU impact map of **Figure 11** shows that the top part of the bottom right drain of the flip-flop (labeled node "SL") is not sensitive to SEU. A detailed study of the collected currents in this area has then been conducted. For this purpose, a specific ion impact location (shown in **Figure 11**, labeled "detailed impact" in the top left corner of node SL) has been fixed and the collected current waveform following the ion impact at this location has been systematically analyzed, as well as the voltage waveform of the two bistable nodes. As expected, this node SL collects most of the charge as it corresponds to the stricken drain. However, the fine analysis (not shown) of the different transient currents indicates that the nodes SLN, N1 and N2 collect later, by a diffusion mechanism, a small quantity of charge, which is high enough to keep the voltage of the SLN node at the low logic state and to prevent a latch upset. In order to validate this affirmation, we removed from the circuit netlist in a separate simulation batch the drains corresponding to nodes SLN, N1 and N2. In this case, since no charge is collected on the NMOS of the SLN node to counter-balance the feedback loop of the latch, the electrical potential of the SLN node increases and an upset occurs.

To conclude, this particular charge-sharing mechanism in the area of the top left corner of collecting node SL has been observed whatever the value of the LET in the range 1.8–60 MeV cm2 /mg, demonstrating the capability of the RWDD approach to treat such complex circuit response to single events.
