**Theoretical Derivation of Junction Temperature of Package Chip**

Professor Wei-Keng Lin

Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/62570

#### **Abstract**

Junction temperature is the highest operating temperature of the actual semiconductor in an electronic device. In operation, junction temperature is higher than the case temperature and the temperature of the part's exterior. The difference is equal to the amount of heat transferred from the junction to case multiplied by the junction-to-case thermal resistance. When designing integrated circuits, predicting and calculating the chip junction temperature is a very important task. This chapter describes how to derive the junction temperature from the thermal transport model.

**Keywords:** junction temperature, thermal resistance, thermal conduction, thermal convection, thermal radiation

#### **1. Introduction**

From the small integrated circuits in 1960 to the development of today's large and ultra-highspeed integrated circuits, the package density has increased from only several electronic components to billions of electronic components per chip. Because of this high package density, the combination directly causes a serious designing problem, and it will also increase the heat dissipation of the chip per unit volume or area. If the cooling method is not properly de‐ signed, this overheated high-density package chip will result in a high junction temperature. As a result, it will have a negative effect on the functions, the reliabilities, and the life of the electronic chip. Usually, a high-speed integrated circuit is the most expensive element of the whole package. If the chip continues to suffer from the effect of high heat, it will cause the speed to slow down or be damaged; therefore, the solution of the heat-dissipated problem should not be underestimated. In electronics manufacturing, integrated circuit packaging is the final stage

© 2016 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

of semiconductor device fabrication, in which the tiny block of semiconducting material is encased in a supporting case that prevents physical damage and corrosion. The case, known as a "package," supports the electrical contacts that connect the device to a circuit board. The junctions of the chip are used by wire connecting on the package housing. These wires are then connected to other components through the wire on the printed circuit board (PCB). There‐ fore,formanyintegratedcircuitproducts,packagingtechnologyisaveryimportantstage.Using chip as the main product such as random access memory (RAM) or dynamic RAM (DRAM), packaging technology not only can guarantee the separation ofthe chip andthe outer worldbut also can prevent chip circuit from losing its function caused by the corrosion of the impurities in the air; also, the wellness of the packaging technology directly concerns the designing and producing of the PCB connected with the chip. This leads to the deeply influential of the chip's performance. However, if the thermal impedance of the package is too high, the junction temperature will also be raised to a high level. According to the report, once the junction temperature is raised to approximately 10°C, half of the component life will be reduced [1]. if the average life span is 30,000 to 50,000 hours, it is also implied that 15,000 to 25,000 hours of usage time will be decreased and result in the chip efficiency's sharp decline. This chapter is mainly focused on the theoretically export system manufacturers' topmost concern, junction temperature (*T* <sup>J</sup> ). Sometime in 1980, PC is still in 386 and 486, and the CPUs' permitted temperature could be up to 90°C; until the 21st century, all the semiconductor chip junction temperature (including LED) has been asked not to surpass 70°C. Some of them are not even allowed to exceed 50°C. Therefore, the purpose of this chapter is how to simply use a theoreti‐ cal calculation to derive the chip junction temperature (*T* <sup>J</sup> ) without using software package (Code).

## **2. Theoretical derivation of the junction temperature**

The following are the logical ways to think of the solutions to counter heat-dissipated prob‐ lems.

#### **2.1. Questions in Table 1**



**Table 1.** Steps of finding the solutions of heat-dissipated problems.

At this step, readers should have a good physical explanation for solving the questions. From steps A to G, we can be closer and see clearly the answer to the question.

#### **2.2. Quantization and removal of unimportant parameters**

The goal of this step is to think about every item of the question (or concept) to gain a deeper understanding. For example, *Q*=*hA*(*T*s-*T*<sup>f</sup> ); in this phase, notice the correct use of the unit (usually in SI unit). Make sure not to compare apple and orange, making correct assumptions necessary. Thus, when making any item negligible, we need to provide a scientific proof. We cannot directly ignore an item because it is small. Take the temperature, for example, when finding the answer to the question on temperature. We need to ask if we are looking for the temperature distribution or the end point. What is the accuracy? Is there anything else that can be simplified?

#### **2.3. Establishment of the governing equation**

The definition of the governing equation is using other variables to define an unknown item. If we only consider the heat transfer mechanics of the single chip on the PWB, take **Figures 1** and **2**, for example, during the heat transfer mechanism. The chip and the board both have thermal conductance, thermal convection, and thermal radiation. At this point, we can notice some of the characteristics of the heat transfer processes: (A) Multiple heat transfer processes, a high level of thermal coupling (heat source and sink). (B) Large-scale thermal spreading effect. If we consider all the heat transfer mechanism between each PWB, such as in **Figure 3**, then we need to also consider the thermal conductance coupling problem from the PCB. Among thermal convection, they include (i) material on the board, (ii) thermal convection and thermal radiation between each adjacent boards, and (iii) thermal coupling between the main board and the daughter card. Among radiation coupling, they include (a) material on the board and (b) adjacent boards. What needs to be paid attention of is when there is thermal coupling between the outer heat source and the chip heat itself. The heat received from the critical chip is not less than the heat source chip itself. **Figure 4** presents a schematic diagram between the heat source chip and the critical chip of the motherboard and the outer heat source. Thus, to solve the heat-dissipated problem, we should not only pay attention to the temperature on the heat source of chip itself but also need to know problems such as the heat accumulation locations and the other chip influences.

**Figure 1.** Heat transfer mechanism process of the chip for the upper part.

**Figure 2.** Heat transfer mechanism process of the chip for the lower portion.

**Figure 3.** Heat transfer mechanism between each PWB.

**Figure 4.** Schematic diagram between the heat source chip and the critical chip of the motherboard and the outer heat source.

#### **2.4. How to analyze the influences of the thermal coupling**

Thermal coupling makes it hard to analyze, if we do not include the thermal coupling in the calculation, and the results will not be accurate. Because of the thermal coupling natural properties, we need to consider the environment, chassis, PWB, component (module), chip, and parts (diodes, transistor) etc., when analyzing conducting a solution that can explain the thermal effect. Usually, there are three ways to solve either the key component or the heat source chip's heat-dissipated problem (see **Figure 5**). One of them is using the integral method, that is, a closed-form solution. However, this method can necessarily not be used on every energy conservation. The second method is using the differential method, the so-called numerical analysis. Numerical analysis needs a special mathematical skills technique. It needs someone who has studied numerical analysis to write a program that includes grids definition, module establish, numerical analysis model, converging problem, boundary condition definition, etc. This needs to educate talented people, and most of the companies are unwilling to invest in here. But on the other hand, usually there are also software packages in the market, such as ice pack, fluent, ANSYS, and Flotherm. However, all these software packages cost more than USD 30,000 or 40,000. Not everyone can afford it, and most companies cannot even buy it—these are some of the difficulties what companies are facing. The third solution is measure it by experiment. The experiment is then separated into two kinds. One is the actual measure‐ ment that uses the real system with the samples attached to it to measure the data such as temperature. Although this is a very reliable way, it spends a lot of manpower and time, and the cost is expensive. Cooler manufacturers commonly do not use this solution. For example, Intel published the next-generation CPU, but there are supplier problems on these equipment, such as power supply, main board, south bridge, north bridge, hard disk, and DRAM. Cooler manufacturers can only solve the CPU's heat-dissipated problems, and they really cannot wait until all these peripheral accessory devices are ready because it will take too much time and cost too much. Therefore, the actual measurement is only used in system manufacture, such as in HP, DELL, ASUS, ACER, and Lenovo. The second way of the experiment is the Dummy experiment, also known as Dummy heater. It is commonly used by the industry. For example, because we wanted to know what the thermal resistance of the cooler is, we only have to place the cooler on the heating copper block with which it has the same area and then measure the difference temperature between the heat copper block and ambient temperature then divide by the input power to get the thermal resistance of the cooler. The experiment does not have any complex problems. The only thing that we need to be aware of is the sensors' correction, measuring the position and boundary condition.

**Figure 5.** Three methods for solving heat-dissipated problems.

#### **2.5. Theoretical derivation of the junction temperature (***T* **J)**

*2.5.1. Consider a control volume around the outside of the component and lead pin*

Take the control volume on the external chip and wire as in **Figure 6**.

**Figure 6.** Heat transfer diagram outside the chip.

Let us apply the energy balance equation to the body of the component and device power dissipation is "*P*tot,

$$\begin{aligned} P\_{\text{nor}} &= \underline{Q}\_{C,R} + \underline{Q}\_{C,h} + \underline{Q}\_{L,h} + \underline{Q}\_{C,C} \\ &= \underline{Q}\_{C,R} + \underline{Q}\_{C,h} + \underline{Q}\_{L,h} + \underline{Q}\_{L,C} + \underline{Q}\_{A,C} \end{aligned} \tag{1}$$

where *Q*C,R=radiation heat transfer from component (W), *Q*C,H=convection heat transfer from component (W), *Q*L,h=convection heat transfer from lead (W), *Q*C,C=conduction heat transfer through component (W), *Q*L,C=conduction heat transfer through lead (W), and *Q*A,C=conduction heat transfer through air gap under the component (W).

Converting all the *Q*'s in Eq. (1) in terms of the temperature definitions, we have

*2.5.1.1. Using Stefan-Boltzmann's law to change the thermal radiation of the chip into temperature*

$$
\mathcal{Q}\_{C,\mathcal{R}} = \sigma \in\_{\subset\_{\subset}} \mathcal{f}\_{C,\nu\rho'} A\_{C,\mathcal{C}} \left( T\_C^4 - T\_{\nu\rho'}^4 \right) = \left( \frac{1}{R\_{ab,\mathcal{CR}}} \right) \left( T\_C^4 - T\_{\nu\rho'}^4 \right)
$$

$$
= \sigma \in\_{\subset} \mathcal{f}\_{C,\nu\rho'} A\_{C,\mathcal{C}} \left( T\_C^4 - T\_{\ a}^{-4} \right) = \left( \frac{1}{R\_{ab,\mathcal{CR}}} \right) \left( T\_C^4 - T\_{\ a}^{-4} \right) \tag{2}
$$

where σ=Stefan-Boltzmann's constant=5.669×10−8 W/m2 K4 ,*ε*=material emissivity, *f*c,ref=shape factor for component, *A*C,C=upper surface area of the chip=bottom surface area of the chip (m2 ), *T*C=upper surface temperature of the chip (K), *h*C=heat transfer coefficient of the chip (W/m2 K), and *T*ref=reference temperature where the component radiates to generally can be assumed to be *T*a (K).

$$\mathcal{Q}\_{C,h} = h\_C A\_{C,C} \left( T\_C - T\_a \right) \tag{3}$$

$$R\_{th,Ch} = \frac{1}{h\_C A\_{C,C}} = \frac{T\_C - T\_a}{Q\_{C,h}} \tag{4}$$

#### *2.5.1.2. Using Newton's cooling law to change the thermal convection of the chip into temperature*

$$Q\_{L,h} = h\_L A\_{L,S} \left( T\_L - T\_a \right)$$

$$R\_{ih,Lh} = \frac{1}{h\_L A\_{L,S}} = \frac{T\_L - T\_a}{\mathcal{Q}\_{L,h}} \tag{5}$$

where *h*L=heat transfer coefficient of the wire (W/m2 K) and *A*L,S=surface area of the wire (m2 ). *2.5.1.3. Using Newton's cooling law to change the thermal convection of the lead into temperature*

$$
\underline{\mathcal{Q}}\_{L,\mathcal{C}} = \frac{k\_L A\_{L,\mathcal{C}}}{L\_L} \left( T\_L - T\_b \right)
$$

$$
\underline{\mathcal{R}}\_{lb,LC} = \frac{1}{k\_L A\_{L,\mathcal{S}}} = \frac{T\_L - T\_b}{\underline{\mathcal{Q}}\_{L,\mathcal{C}}} \tag{6}
$$

where *A*L,C=cross-sectional area of the lead (m2 ), *k*L=lead thermal conductivity (W/m K), *L*L=length of the lead outside of the component (m), and *T*L=lead average temperature (K).

*2.5.1.4. Using Fourier's cooling law to change the thermal conduction of the chip into temperature through air gap between chip and board*

$$
\underline{\mathcal{Q}}\_{A,C} = \frac{k\_A A\_{C,C}}{t\_A} \left( T\_c - T\_b \right)
$$

$$
\underline{\mathcal{R}}\_{h,CA} = \frac{1}{k\_A A\_{C,C}} = \frac{T\_c - T\_b}{\underline{\mathcal{Q}}\_{A,C}} \tag{7}
$$

where *k*A=air thermal conductivity (W/m K), *t*A=thickness of the layer of air underneath the component (m), *T*b=board temperature (K), and *A*C,C=assumed component top surface is the cross-sectional area of the air gap (m2 ).

Substitute the above into Eq. (1):

$$\begin{aligned} P\_{\text{nor}} &= \underline{Q}\_{C,R} + \underline{Q}\_{C,h} + \underline{Q}\_{L,h} + \underline{Q}\_{C,C} \\ &= \underline{Q}\_{C,R} + \underline{Q}\_{C,h} + \underline{Q}\_{L,h} + \underline{Q}\_{C,C} + \underline{Q}\_{L,C} + \underline{Q}\_{A,C} \end{aligned}$$

$$\begin{aligned} &= \sigma \in\_{\mathcal{C}} f\_{\mathcal{C}, n\mathcal{y}} A\_{\mathcal{C}, \mathcal{C}} \left( T\_{\mathcal{C}}^{4} - T\_{n\mathcal{y}}^{4} \right) + h\_{\mathcal{C}} A\_{\mathcal{C}, \mathcal{C}} \left( T\_{\mathcal{C}} - T\_{a} \right) \\ &+ h\_{L} A\_{L, \mathcal{S}} \left( T\_{L} - T\_{a} \right) + \frac{k\_{L} A\_{L, \mathcal{C}}}{L\_{L}} \left( T\_{L} - T\_{b} \right) + \frac{k\_{A} A\_{\mathcal{C}, \mathcal{C}}}{t\_{A}} \left( T\_{\mathcal{C}} - T\_{b} \right) \end{aligned} \tag{8}$$

In Eq. (8), *T*L, *T*b, and *T*<sup>C</sup> are unknown, but we do not know the junction temperature (*T*<sup>J</sup> ) yet. Therefore, we need seek another control volume to get *T*<sup>J</sup> .

#### *2.5.2. Consider a control volume around the inside of the component*

Assume a chip inside as shown in **Figure 7**, according to energy conservation

$$P\_{\rm nu} = \underline{Q}\_{C,\aleph} + \underline{Q}\_{C,h} + \underline{Q}\_{C,J} + \underline{Q}\_{A,C} \tag{9}$$

**Figure 7.** Case temperature and heat transfer diagram inside the chip.

*2.5.2.1. Using Fourier's cooling law to change the inner thermal conduction of the chip into temperature*

$$\underline{Q}\_{C,J} = (-\frac{k\_L A\_{L,C}}{L\_L})\_{\text{eff}} \left( T\_C - T\_J \right) = \left( \frac{k\_L A\_{L,C}}{L\_L} \right)\_{\text{eff}} \left( T\_J - T\_C \right) \tag{10}$$

where *Q*C,J=conduction heat transfer within the body of the component (W), *A*L,C=effective lead cross-sectional area inside the component (m2 ), *L*L,eff=effective lead length inside the component (m), *k*L,eff=effective thermal conductivity of the lead (W/m K).

*2.5.2.2. Using Fourier's cooling law and Newton's cooling law to change the thermal conduction and thermal convection of the chip and lead into temperature*

Compare Eq. (1) with Eq. (9).

$$P\_{\rm nu} = \underline{Q}\_{C,R} + \underline{Q}\_{C,h} + \underline{Q}\_{L,h} + \underline{Q}\_{L,C} + \underline{Q}\_{A,C} \tag{1}$$

$$P\_{\rm nu} = \underline{Q}\_{C,R} + \underline{Q}\_{C,h} + \underline{Q}\_{C,J} + \underline{Q}\_{A,C} \tag{9}$$

As shown in **Figure 8**, the conduction heat transfer within the body of the component *Q*C,J is the sum of the thermal convection from lead to ambient *Q*L,h and lead thermal conductance to board *Q*L,C:

$$\mathcal{Q}\_{\mathcal{C},J} = \mathcal{Q}\_{\mathcal{L},b} + \mathcal{Q}\_{\mathcal{L},\mathcal{C}}$$

Plugging all the thermal conduction equation and thermal convection into above equation, we obtain:

$$(\frac{k\_L A\_{L, \text{C}}}{L\_L})\_{\text{eff}} \left( T\_J - T\_{\text{C}} \right) = h\_L A\_{L, \text{S}} \left( T\_L - T\_a \right) + \frac{k\_L A\_{L, \text{C}}}{L\_L} \left( T\_L - T\_b \right) \tag{11}$$

Plug Eq. (11) into Eq. (8):

$$\begin{aligned} P\_{\text{tot}} &= \sigma \in\_{\mathcal{C}} \, \_{C}F\_{\text{C},ref} \, A\_{\text{C},\text{C}} \left( T\_{\text{C}}^{4} - T\_{\text{ref}}^{4} \right) + h\_{\text{C}} A\_{\text{C},\text{C}} \left( T\_{\text{C}} - T\_{\text{o}} \right) \\ &+ h\_{L} A\_{L,\text{S}} \left( T\_{L} - T\_{\text{o}} \right) + \frac{k\_{L} A\_{L,\text{C}}}{L\_{L}} \left( T\_{L} - T\_{\text{o}} \right) + \frac{k\_{A} A\_{\text{C},\text{C}}}{t\_{A}} \left( T\_{\text{C}} - T\_{\text{o}} \right) \end{aligned}$$

$$\begin{aligned} \sigma &= \sigma \in\_{\mathcal{C}} f\_{\mathcal{C}, \nu \circ f} A\_{\mathcal{C}, \mathcal{C}} \left( T\_{\mathcal{C}}^{4} - T\_{\nu \circ}^{4} \right) + h\_{\mathcal{C}} A\_{\mathcal{C}, \mathcal{C}} \left( T\_{\mathcal{C}} - T\_{a} \right) \\ &+ \left( \frac{k\_{L} A\_{L, \mathcal{C}}}{L\_{L}} \right)\_{\text{eff}} \left( T\_{J} - T\_{\mathcal{C}} \right) + \frac{k\_{A} A\_{\mathcal{C}, \mathcal{C}}}{t\_{A}} \left( T\_{\mathcal{C}} - T\_{b} \right) \end{aligned} \tag{12}$$

Solve for *T*<sup>J</sup> from Eq. (12):

$$T\_J = T\_c + \left(\frac{k\_L A\_{L,C}}{L\_L}\right)\_{\text{eff}}^{-1} \left\{ P\_{\text{av}} - \begin{bmatrix} \sigma \in\_{\subset} f\_{\subset, \text{ref}} A\_{\subset, \text{C}} \left(T\_C^4 - T\_{\text{ref}}^4\right) \\\\ + h\_C A\_{\subset, \text{C}} \left(T\_C - T\_a\right) + \frac{k\_A A\_{\subset, \text{C}}}{t\_A} \left(T\_C - T\_b\right) \end{bmatrix} \right\} \tag{13}$$

In Eq. (13), the junction temperature is what we need, but there are two unknown temperatures, such as *T*b and *T*C. Therefore we must seek another two equations to obtain *T*b and *T*C.

**Figure 8.** Junction temperature and heat transfer diagram inside the chip.

#### *2.5.3. Consider a control volume around the air flow channel without considering adjacent heat source*

Consider a control volume around the air flow channel as shown in **Figure 9**. The conduction heat transfer from component to board *Q*C,C is the sum of *Q*L,C, *Q*A,C, and *Q*N,C, where *Q*L,C=conduction heat transfer through lead, *Q*A,C=conduction heat transfer through air gap under the component, and *Q*N,C=adjacent heat input.

$$\mathcal{Q}\_{\mathcal{C},\mathcal{C}} = \mathcal{Q}\_{\mathcal{L},\mathcal{C}} + \mathcal{Q}\_{\mathcal{A},\mathcal{C}} + \mathcal{Q}\_{\mathcal{N},\mathcal{C}}$$

Neglect *Q*N,C heat conduction from neighbor and consider a control volume shown as in **Figure 9**. Chip heat conductance power *Q*C,C is then the sum of *Q*b,h, *Q*bb,h, *Q*b,R, and *Q*bb,R, where *Q*b,h=convection heat transfer from board top surface, *Q*bb,h=convection heat transfer from board bottom surface, *Q*b,R=radiation heat transfer from board top surface, and *Q*bb,R=radiation heat transfer from board bottom surface.

$$\underline{Q}\_{C,C} = \left(\underline{Q}\_{b,h} + \underline{Q}\_{bb,h}\right) + \left(\underline{Q}\_{b,R} + \underline{Q}\_{bb,R}\right) \tag{14}$$

From Eq.(1), with energy conservation of airflow channel:

……With energy conservation of air flow channel:

$$
\underline{Q}\_{b,h} + \underline{Q}\_{b,R} + \underline{Q}\_{C,R} + \underline{Q}\_{C,h} + \underline{Q}\_{L,h} = m\_{a\bar{\nu}} C\_{\rho, a\bar{\nu}} \left( T\_o - T\_i \right) \tag{15}
$$

Plug Eq. (15) into Eq. (1) and obtain Eq. (16):

$$\begin{split} P\_{\text{tot}} &= \underline{Q}\_{C,R} + \left( \underline{Q}\_{C,h} + \underline{Q}\_{L,h} \right) + \left( \underline{Q}\_{L,C} + \underline{Q}\_{A,C} \right) \\ &= \underline{Q}\_{C,R} + \left[ m\_{\text{air}} C\_{p,\text{air}} \left( T\_o - T\_i \right) - \underline{Q}\_{b,h} - \underline{Q}\_{b,R} - \underline{Q}\_{C,R} \right] + \left( \underline{Q}\_{L,C} + \underline{Q}\_{A,C} \right) \\ &= \left[ m\_{\text{air}} C\_{p,\text{air}} \left( T\_o - T\_i \right) - \underline{Q}\_{b,h} - \underline{Q}\_{b,R} + \left( \underline{Q}\_{L,C} + \underline{Q}\_{A,C} \right) \right] \end{split} \tag{16}$$

$$\text{Scicence } \underline{Q}\_{C,C} = \underline{Q}\_{L,C} + \underline{Q}\_{A,C} = \left(\underline{Q}\_{b,h} + \underline{Q}\_{bb,h}\right) + \left(\underline{Q}\_{b,R} + \underline{Q}\_{bb,R}\right) \tag{14}$$

Plug Eq.(14) into Eq.(16), and solve for it, i.e.,

$$P\_{\rm tot} = m\_{\rm air} C\_{p,\rm air} \Delta T + Q\_{\rm bb,h} + Q\_{\rm bb,R} \tag{17}$$

Assuming *Q*bb,h and *Q*bb,R can be ignored, Eq. (17) turns out to be:

$$P\_{\text{tot}} = m\_{\text{air}} C\_{\rho, \text{air}} \left( T\_o - T\_i \right) \tag{18}$$

It is reasonable that all the power generation from the component should be carried away by the air flow. If not, the board temperature, the case temperature, and the junction temperature will be increased. However, Eq. (18) cannot help to solve the board temperature; therefore, we need to seek another control volume to solve *T* b.

**Figure 9.** Schematic diagram for airflow channel.

#### *2.5.4. Consider a control volume around the board*

Consider a control volume around the board as in **Figure 10**, where *T*b=board temperature (K), *Q*C,C=conduction heat transfer from component to board (W), *Q*b,h=convection heat transfer from board top surface (W), *Q*bb,h=convection heat transfer from board bottom surface (W), *Q*b,R=radiation heat transfer from board top surface (W), *Q*bb,R=radiation heat transfer from board bottom surface (W), and *Q*N,C=conduction heat transfer from neighboring component (W).

**Figure 10.** Schematic of chip on board.

Energy balance for the steady-state condition:

$$
\mathcal{Q}\_{\boldsymbol{\alpha}} = \mathcal{Q}\_{\boldsymbol{\alpha}\boldsymbol{\alpha}}
$$

$$
\mathcal{Q}\_{\boldsymbol{C},\boldsymbol{C}} + \mathcal{Q}\_{\mathcal{N},\boldsymbol{C}} = \mathcal{Q}\_{b,h} + \mathcal{Q}\_{bb,h} + \mathcal{Q}\_{b,\boldsymbol{R}} + \mathcal{Q}\_{bb,\boldsymbol{R}}\tag{19}
$$

If neglect the bottom back board thermal convection and radiation effects, then *Qbb*,*<sup>h</sup>* = *Qb*,*<sup>R</sup>* = 0. Assume *Q*N,C=0 and simplify Eq. (19) to be Eq. (20):

$$Q\_{\mathcal{C},\mathcal{C}} = Q\_{\mathcal{L},\mathcal{C}} + Q\_{\mathcal{A},\mathcal{C}} = Q\_{b,h} + Q\_{b,\mathcal{R}} \tag{20}$$

where *Q* L,C=conductance heat transfer from lead (W) and *Q* A,C=conduction heat transfer through air gap under the component (W).

**Figure 11.** Schematic of heat transfer from lead to board.

In **Figure 11**, the conduction heat transfer from component to board *Q*C,C is the sum of the conductance heat transfer from lead *Q*L,C and the conduction heat transfer through air gap under the component *Q*A,C. If we neglect the convection heat transfer from board bottom surface *Q*bb,h and the radiation heat transfer from board bottom surface, then the power *Q*C,C should also equal to the sum of convection heat transfer from board top surface *Q*b,h and radiation heat transfer from board top surface *Q*b,R. Therefore,

$$
\boldsymbol{P}\_{\text{av,board}} = \boldsymbol{Q}\_{C,C} = \boldsymbol{Q}\_{L,C} + \boldsymbol{Q}\_{A,C} = \boldsymbol{Q}\_{b,b} + \boldsymbol{Q}\_{b,R}
$$

$$
= \boldsymbol{h}\_b \left( \boldsymbol{A}\_b - \boldsymbol{A}\_{C,C} \right) \left( \boldsymbol{T}\_b - \boldsymbol{T}\_a \right) + \sigma \boldsymbol{\Theta}\_b \boldsymbol{f}\_{b,ref} \left( \boldsymbol{A}\_{b,-} \boldsymbol{A}\_{C,C} \right) \left( \boldsymbol{T}\_b^4 - \boldsymbol{T}\_a^4 \right) \tag{21}
$$

where *h*b=heat transfer coefficient of air flow associated with the board, *A*b=board upper surface area, and *A*C,C=component top surface area=bottom surface area.

After obtaining a first estimate of the board temperature and assuming that the heat is uniformly distributed over the board, neglect *Q*b,R and thus obtain an initial average board temperature:

$$P\_{\text{tot,baud}} = h\_b \left( A\_b - A\_{C,C} \right) \left( T\_b - T\_a \right) \tag{22}$$

Solve *T* b from Eq. (22):

$$T\_b = \frac{P\_{\text{av,board}}}{h\_b \left(A\_b - A\_{C,C}\right)} + T\_a \tag{23}$$

Hence, we have a first estimate of Tb.

where *P*tot=total power generation from chip and *P*tot,board=total power conduction to the board.

Remember, *P*tot is different from *P*tot,board. In general, under the forced convection condition, the heat conductance into the board is around 20–30%, *P*tot,board=0.2*P*tot ~ 0.3*P*tot whereas, under the natural convection condition, the heat conductance into the board is only 70–80%, *P*tot,board=0.2*P*tot ~ 0.3*P*tot

*2.5.5. Solve for T C, T b, and T J*

*2.5.5.1. Method 1*

*2.5.5.1.1. If Rth,JC can be obtained from the vendor:*

$$R\_{th, \mathcal{K}} = \frac{T\_J - T\_{\mathcal{C}}}{P\_{\nu \nu}} \tag{24}$$

Combining Eqs. (13), (23), and (24), *T*<sup>J</sup> , *T*b, and *T*C can be solved.

#### Theoretical Derivation of Junction Temperature of Package Chip http://dx.doi.org/10.5772/62570 165

$$T\_J = T\_C + \left(\frac{k\_L A\_{L,C}}{L\_L}\right)^{-1}\_{\mathcal{A}\mathcal{Y}} \left\{ P\_{\rm{tot}} - \begin{bmatrix} \sigma \in\_{\mathcal{C}} f\_{c,\nu\mathcal{Y}} A\_{c,\mathcal{C}} \left(T\_c^4 - T\_{\nu\mathcal{Y}}^4\right) + \\\\ h\_c A\_{c,\mathcal{C}} \left(T\_c - T\_s\right) + \frac{k\_A A\_{\mathcal{C},\mathcal{C}}}{t\_A} \left(T\_c - T\_b\right) \end{bmatrix} \right\} \tag{13}$$

$$T\_b = \frac{P\_{\text{nor,bound}}}{h\_b \left(A\_b - A\_{C,C}\right)} + T\_a \tag{23}$$

#### *2.5.5.1.2. If Rth,JC is unknown*

Assume that *P*up is uniformly spread over the entire upper surface of the component. Therefore,

$$P\_{up} = h\_c A\_{c,c} \left( T\_c - T\_a \right) \tag{25}$$

$$
\dot{P}\_{\text{tot}} - P\_{\text{tot,bawdl}} = P\_{\text{tot}} - h\_b \left( A\_b - A\_{C,C} \right) \left( T\_b - T\_a \right)
$$

$$
T\_C = \frac{P\_{\text{up}}}{h\_C A\_{C,C}} + T\_a
\tag{26}
$$

From Eqs.(13), (23), and (26), solve for *TJ* , *Tb* and *Tc*.

$$T\_J = T\_C + \left(\frac{k\_L A\_{L,C}}{L\_L}\right)^{-1}\_{\text{eff}} \left\{ P\_{\text{tot}} - \left[ \frac{\sigma \in\_C f\_{C, \text{ref}} A\_{C,C} \left( T\_C^4 - T\_{\text{ref}}^4 \right) + \right.}{k\_C A\_{C,C} \left( T\_C - T\_a \right) + \frac{k\_A A\_{C,C}}{t\_A} \left( T\_C - T\_b \right)} \right] \right\} \tag{13}$$

$$T\_b = \frac{P\_{\text{net,bowd}}}{h\_b \left(A\_b - A\_{C,C}\right)} + T\_a \tag{23}$$

In the case of duct flow, from Eq. (26), we need to obtain *T*a. Let us reconsider the airflow over the component in a channel. If we neglect the radiation effect, the heat transported by the air is obtained from

$$T\_C = \frac{P\_{up}}{h\_C A\_{C,C}} + T\_a \tag{26}$$

$$\mathcal{Q}\_{up,C} = \dot{m} C\_{p,a\dot{m}} \left( T\_o - T\_i \right) \tag{27}$$

*T*o is air exit temperature of the flow channel, whereas *T*<sup>i</sup> is the air inlet temperature of the flow channel. *T*o can be obtained from Eq. (28):

$$T\_o = \frac{\mathcal{Q}\_{up,C}}{\dot{m}C\_{p,air}} + T\_i \tag{28}$$

In duct flow, the ambient temperature is the average temperature of the air inlet temperature and air exit temperature:

$$\begin{split} T\_a &= \frac{\left(T\_o + T\_i\right)}{2} = \frac{1}{2} \left(\frac{\underline{Q}\_{ap,C}}{\dot{m}C\_{p,a\nu}} + 2T\_i\right) \\ &= \frac{\underline{Q}\_{ap,C}}{2\dot{m}C\_{p,a\nu}} + T\_i = \frac{P\_{ap}}{2\dot{m}C\_{p,a\nu}} + T\_i \end{split} \tag{29}$$

Plug Eq. (29) into Eq. (26) and then obtain chip case temperature *T*C:

$$T\_c = \frac{P\_{up}}{h\_C A\_{c,C}} + T\_a = P\_{up} \left( \frac{1}{h\_C A\_{c,C}} + \frac{1}{2 \dot{m} C\_{p,a\nu}} \right) + T\_i \tag{30}$$

However, in Eq. (30), the heat transfer coefficient *h*C is still needs to be obtained.

#### *2.5.5.2. Method 2*

If *h*C is not readily available, let us use the junction-to-ambient and junction-to-case thermal resistance for the component as shown in **Figure 12**, the schematic diagram of thermal re‐ sistance in flow channel.

**Figure 12.** Schematic diagram of thermal resistance in flow channel.

The definition of thermal resistance *R*th,JC is the junction temperature (*T*<sup>J</sup> ) minus the chip case temperature *T*C divided by power input as shown in Eq. (31):

$$R\_{th,JC} = \frac{T\_f - T\_C}{P\_{wp}} \tag{31}$$

The thermal convection resistance from chip surface to ambient *R*th,Ca is shown in Eq. (32):

$$R\_{th,Ca} = \frac{1}{h\_C A\_{C,C}}\tag{32}$$

Therefore, the total thermal resistance *R*th,Ja is the sum of *R*th,JC and *R*th,Ca, shown as in Eq. (33):

$$R\_{\rm th,JC} + R\_{\rm th,Cu} = R\_{\rm th,La} \tag{33}$$

The thermal resistance *R*th,Ch (or *R*th,Ca) can be represented by Eq. (34):

$$R\_{ib,Ch} = R\_{ib,Ca} = \frac{T\_c - T\_a}{P\_{up}} = \frac{T\_c - \frac{P\_{up}}{2\dot{m}C\_{p,air}} - T\_i}{P\_{up}}$$

$$= \frac{T\_c}{P\_{up}} - \frac{1}{2\dot{m}C\_{p,air}} - \frac{T\_i}{P\_{up}}\tag{34}$$

The case temperature *T*C can be represented by Eq. (35):

$$T\_c = P\_{up} \left( R\_{ub,Ca} + \frac{1}{2\dot{m}C\_{p,air}} \right) + T\_i \tag{35}$$

$$R\_{th,Ch} = R\_{th,Ca} = \frac{1}{h\_C A\_{C,C}} = \frac{T\_c - T\_a}{\mathcal{Q}\_{C,b}} \tag{4}$$

Plug Eq. (4) into Eq. (35) and obtain Eq. (36):

$$T\_c = P\_{up} \left( \frac{1}{h\_c A\_{c,C}} + \frac{1}{2C\_p \left( \rho\_{air} V\_{air} A\_{channel} \right)} \right) + T\_i \tag{36}$$

Eqs. (36) and (30) are the same.

$$T\_c = P\_{up} \left( \frac{1}{h\_C A\_{C,C}} + \frac{1}{2 \dot{m} C\_{p,air}} \right) + T\_i \tag{30}$$

Basically, we can solve for *T*<sup>J</sup> , *T*b, and *T*C from Eqs. (13), (23), and (26).

#### *2.5.6. Consider a control volume around the air flow channel with adjacent heat source*

Now, if we want get a more accurate expression for the board temperature *T* b, then we can reconsider the energy balance for the board, as shown in **Figure 13**. Because the value for *T*<sup>C</sup> is known from Eqs. (26) and Eq. (30) from Eq. (17):

$$P\_{\rm av} = m\_{\rm air} C\_{p,\rm air} \Delta T + Q\_{\rm bb,h} + Q\_{\rm bb,R} \tag{17}$$

**Figure 13.** Schematic of chip thermal resistance and thermal resistance from adjacent heat source in the flow channel.

Total power *P*tot thus can be represented in terms of temperature:

$$\begin{split} P\_{\text{tot}} &= \dot{m}C\_{p,air} \left( T\_o - T\_i \right) + h\_{bb} A\_{bb} \left( T\_b - T\_{amb,bb} \right) \\ &+ \left( \frac{1}{R\_{th,bbR}} \right) \left( T\_b^4 - T\_{N,bb}^4 \right) \end{split} \tag{37}$$

where *T*N,b=neighboring board temperature where the component top surface sees for radiation exchange (K),*h*bb=heat transfer coefficient from the backside of the board (W/m K), *A*bb=back surface area associated with above convection loss (m2 ), *R*th,b,R=radiation heat transfer resist‐ ance with respect to the board (K/W), *R*th,bb,R=radiation heat transfer resistance with respect to the back of the board (K/W), and *T*N,bb=board temperature of the neighboring board where the radiation exchange takes place with back of the board where the component of interest resides.

Solve for *T*<sup>b</sup> in Eq. (37); theoretically, we need more accuracy equation such as Eq. (38). In fact, it is not easy to solve for Eq. (38); sometimes, we need numerical analysis. In addition, there are some variables that could affect its accuracy, such as *h*bb and *T*N,b.

$$\left(\frac{1}{\mathcal{R}\_{h,b\&R}}\right)T\_b^4 + h\_{b\flat}A\_{b\flat}T\_{b\flat}$$

$$\dot{\lambda}\_s = P\_{\text{tot}} + \left(\frac{1}{R\_{th,bbR}}\right) T\_{N,b}^4 + h\_{bb} A\_{bb} T\_{amb,b} - \dot{m} C\_p \left(T\_o - T\_i\right) \tag{38}$$

Because we have *T*b, *T*C, and *T*a, *T*<sup>J</sup> can be calculated from Eq. (13).

$$T\_J = T\_C + \left(\frac{k\_L A\_{L,C}}{L\_L}\right)\_{\text{eff}}^{-1} \left\{ P\_{\text{av}} - \begin{bmatrix} \sigma \mathbf{\dot{\sigma}}\_C f\_{C, \text{ref}} A\_{C,C} \left(T\_C^4 - T\_{\text{ref}}^4\right) + \\\\ h\_C A\_{C,C} \left(T\_C - T\_a\right) + \frac{k\_A A\_{C,C}}{t\_A} \left(T\_C - T\_b\right) \end{bmatrix} \right\} \tag{13}$$

**Figure 14** shows the flow chart solution for *T*<sup>J</sup> . (i) Consider a control volume around the outside of the component and lead pin for the first. Get a chip power *P*tot as a function of (*T*L, *T*b, *T*C, *T*a). (ii) Consider a control volume around the inside of the component and get junction temperature (*T*<sup>J</sup> ) as the function of (*T*b, *T*C, *T*a). (iii) Consider a control volume around the air flow channel, and the total power *P*tot is equal to *mC*p(*T*o−*T*<sup>i</sup> ). (iv) Consider a control volume around the board and assume that the power input to the board *P*tot,board is *n* times of the total power *P*tot, *P*tot,board=*nP*tot. The average board temperature *T*b obtained at this time is the function of *P*tot,board and *T*a. (v) If the vendor can provide *R*th,JC data, then *T*<sup>J</sup> , *T*b, *T*C, and *T*<sup>a</sup> can be calculated. (vi) Calculate *Q*L,C and *Q*A,C. Calculate *P*tot,board=*Q*L,C+*Q*A,C, and (*P*tot,board/*P*tot)=*n*′; if (*n*′-*n*)/*n*>5%, take new *n* for *n*=(*n*′+*n*)/2, back to (iv) using iterative method, and recalculate until (*n*′-*n*)/*n*<5%. Remember, the goal is to solve for TJ ,Therefore, to ensure *<sup>η</sup>* <sup>=</sup> <sup>∆</sup> *<sup>T</sup> <sup>J</sup>* ,*calc* <sup>∆</sup> *<sup>T</sup> <sup>J</sup>* ,*spec* <sup>=</sup> *<sup>T</sup> <sup>J</sup>* ,*calc* - *<sup>T</sup>* <sup>∞</sup> *<sup>T</sup> <sup>J</sup>* ,*spec* - *<sup>T</sup>* <sup>∞</sup> <sup>≤</sup>0.9.

**Figure 14.** Flow chart of junction temperature calculation using the iterative method.

#### **3. Summary**

The goal of the thermal designer is to minimize the thermal resistance of the chip. Equations and analysis procedures are provided in this chapter to assist the designer in understanding the thermal characteristics of chip devices and the thermal performance of related materials. The methods are useful for the approximations of the chip junction temperature. In the meantime, the permissible dissipated powers of chip can be estimated as well.

## **Author details**

Professor Wei-Keng Lin

Address all correspondence to: wklin@es.nthu.edu.tw

Engineering & System Science Department, National Tsing-Hua University, Hsinchu, Taiwan

#### **References**

