**1. Introduction**

The creation of graphene, a monolayer of carbon atoms forming a regular hexagonal lattice [1–3], has stimulated extensive experimental and theoretical studies along various lines of research. Graphene's unique properties make it a promising material for a new generation of carbon-based nanoelectronic devices. In particular, carrier mobility in graphene amounts to 2 · <sup>10</sup><sup>5</sup> cm2/(V s), and ballistic transport is possible on a submicrometer scale [4, 5].

Over a few past years, numerous theoretical and experimental results have been reported on electronic properties of nanometer-wide ribbons of graphene (nanoribbons). Among the first were studies of electronic states of graphene nanoribbons using the Dirac equation under appropriate boundary conditions [6, 7]. The electronic properties of a graphene nanoribbon strongly depend on its size and edge geometry [8]. In terms of transport properties, graphene nanoribbons are highly reminiscent of carbon nanotubes [9, 10] since free carrier motion inside them is also one-dimensional.

A field-effect transistor (FET) based on a 2 nm wide, 236 nm long graphene nanoribbon was fabricated in a recent study [11] (nanoribbons of widths between 10 and 60 nm were

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also studied). The graphene nanoribbon was made narrow enough to open a gap of width required for room-temperature transistor operation. However, it is less compact than the graphene quantum-dot transistor 30 nm in diameter discussed in [12].

The results of paper [13] confirm that graphene devices exhibit very high electronic mobility *µ* on a hexagonal boron nitride (h-BN) substrates, graphene devices on WS2 substrates (G/WS2) are equally promising for high quality electronic transport *<sup>µ</sup>* <sup>∼</sup> 3.8 <sup>×</sup> <sup>10</sup><sup>4</sup> cm2/(V s) at room temperature, followed by G/MoS2 *<sup>µ</sup>* <sup>∼</sup> 104 cm2/(V s) and G/GaSe *<sup>µ</sup>* <sup>∼</sup> 2.2 <sup>×</sup> <sup>10</sup><sup>3</sup> cm2/(V s). However, authors of [13] observed a significant asymmetry in electron and hole conduction in G/WS2 and G/MoS2 heterostructures, most likely due to the presence of sulphur vacancies in the substrate crystals.

Heterogeneous engineering of two-dimensional layered materials, including metallic graphene and semiconducting transition metal dichalcogenides, presents an exciting opportunity to produce highly tunable electronic and optoelectronic systems. In order to engineer pristine layers and their interfaces, epitaxial growth of such heterostructures is required. We report the direct growth of crystalline, monolayer tungsten diselenide (WSe2) on epitaxial graphene (EG) grown from silicon carbide. Vertical transport measurements across the WSe2/EG heterostructure provides evidence that an additional barrier to carrier transport beyond the expected WSe2/EG band offset exists due to the interlayer gap [14].

The integration of graphene and other atomically flat, two-dimensional materials has attracted much interest and been materialized very recently. An in-depth understanding of transport mechanisms in such heterostructures is essential. The vertically stacked graphene-based heterostructure transistors were manufactured to elucidate the mechanism of electron injection at the interface [15]. In a careful analysis of current-voltage characteristics, an unusual decrease in the effective Schottky barrier height and increase in the ideality factor were observed with decreasing temperature. A model of thermionic emission with a Gaussian distribution of barriers was able to precisely interpret the conduction mechanism.

The intrinsic performance of vertical and lateral graphene-based heterostructure FETs have been theoretically investigated in [16]. Authors focused on three recently proposed graphene-based transistors, that in experiments have exhibited large current modulation. The analysis is based on device simulations including the self-consistent solution of the electrostatic and transport equations within the non-equilibrium Green's function formalism. It was shown that the lateral heterostructure transistor has the potential to outperform the graphene-based technology and to meet the requirements for the next generation of semiconductor integrated circuits. On the other hand, it was found that vertical heterostructure transistors miss these performance targets by several orders of magnitude, both in terms of switching frequency and delay time, due to large intrinsic capacitances, and unavoidable current/capacitance tradeoffs.

In this chapter, we focus on the theoretical aspects of the planar technology of the graphene-based heterostructures. We will consider three types of these heterostructures: the single heterojunction, the quantum well, and the superlattice. Our analysis of the electronic properties of such heterostructures is based on the envelope wave function approach. In the first instance, this rather simple method gives an information about an energy spectrum of charge carriers. Then we can obtain a knowledge about optical and transport properties.

Here, we suggest to widely use the gap modifications of graphene in the planar heterostructures. We believe that the planar heterostructures made of gapless and gapped graphene are as prospective building blocks in future carbon-based nanoelectronics. The use of only gapless graphene reduces the diverse opportunities offered by bandgap engineering in gapped graphene.
