**2. Theoretical basis**

also studied). The graphene nanoribbon was made narrow enough to open a gap of width required for room-temperature transistor operation. However, it is less compact than the

The results of paper [13] confirm that graphene devices exhibit very high electronic mobility *µ* on a hexagonal boron nitride (h-BN) substrates, graphene devices on WS2 substrates (G/WS2) are equally promising for high quality electronic transport *<sup>µ</sup>* <sup>∼</sup> 3.8 <sup>×</sup> <sup>10</sup><sup>4</sup> cm2/(V s) at room temperature, followed by G/MoS2 *<sup>µ</sup>* <sup>∼</sup> 104 cm2/(V s) and G/GaSe *<sup>µ</sup>* <sup>∼</sup> 2.2 <sup>×</sup> <sup>10</sup><sup>3</sup> cm2/(V s). However, authors of [13] observed a significant asymmetry in electron and hole conduction in G/WS2 and G/MoS2 heterostructures, most likely due to the presence of

Heterogeneous engineering of two-dimensional layered materials, including metallic graphene and semiconducting transition metal dichalcogenides, presents an exciting opportunity to produce highly tunable electronic and optoelectronic systems. In order to engineer pristine layers and their interfaces, epitaxial growth of such heterostructures is required. We report the direct growth of crystalline, monolayer tungsten diselenide (WSe2) on epitaxial graphene (EG) grown from silicon carbide. Vertical transport measurements across the WSe2/EG heterostructure provides evidence that an additional barrier to carrier transport beyond the expected WSe2/EG band offset exists due to the interlayer gap [14]. The integration of graphene and other atomically flat, two-dimensional materials has attracted much interest and been materialized very recently. An in-depth understanding of transport mechanisms in such heterostructures is essential. The vertically stacked graphene-based heterostructure transistors were manufactured to elucidate the mechanism of electron injection at the interface [15]. In a careful analysis of current-voltage characteristics, an unusual decrease in the effective Schottky barrier height and increase in the ideality factor were observed with decreasing temperature. A model of thermionic emission with a Gaussian distribution of barriers was able to precisely interpret the conduction

The intrinsic performance of vertical and lateral graphene-based heterostructure FETs have been theoretically investigated in [16]. Authors focused on three recently proposed graphene-based transistors, that in experiments have exhibited large current modulation. The analysis is based on device simulations including the self-consistent solution of the electrostatic and transport equations within the non-equilibrium Green's function formalism. It was shown that the lateral heterostructure transistor has the potential to outperform the graphene-based technology and to meet the requirements for the next generation of semiconductor integrated circuits. On the other hand, it was found that vertical heterostructure transistors miss these performance targets by several orders of magnitude, both in terms of switching frequency and delay time, due to large intrinsic capacitances, and

In this chapter, we focus on the theoretical aspects of the planar technology of the graphene-based heterostructures. We will consider three types of these heterostructures: the single heterojunction, the quantum well, and the superlattice. Our analysis of the electronic properties of such heterostructures is based on the envelope wave function approach. In the first instance, this rather simple method gives an information about an energy spectrum of charge carriers. Then we can obtain a knowledge about optical and transport properties.

graphene quantum-dot transistor 30 nm in diameter discussed in [12].

sulphur vacancies in the substrate crystals.

180 Graphene - New Trends and Developments

unavoidable current/capacitance tradeoffs.

mechanism.
