**4.4. FET design and gate coupling**

contamination and scattering sites, while the hot electron and barrier lowering effects affect graphene due to the pinchoff formation needed to have the large Ion/Ioff ratio required for typical electronics applications and to create large enough voltage and power gains for RF

Graphene is a self-contained electronic sheet showing no classical band bending interactions when coupled to a metallic contact as shown in Figure 18. This creates an abrupt transition in the vacuum level, creating a barrier that any carrier would have to tunnel through, creating

**Figure 18.** Classical band diagrams for a metal-silicon interface, a metal-metal interface, and a metal graphene inter‐

In conjunction to this challenge is the relative inertness of a graphene sheet, making good electrical contacts difficult to realize and mainly occurring at grain edges. [56] This creates a situation where the bulk of the contact sits over the graphene electrostatically doping it, while also trying to realize good adhesion creating a search for a metals with good adhesion to graphene along with the correct Fermi level. [56] To achieve this goal, a double or triple metal stack is commonly used with an oxygen scavenger interfacing the graphene (normally Ti), followed by one or a couple of Fermi level contacts (Au, Pd, Ni). [56] The metallic doping effect, however, can be utilized for some interesting devices such as one using asymmetric contacts to create an internal electric field making an IR detector through the photothermoelectric effect, or using large gap superconducting contacts to confine electrons and holes in a graphene sheet

As stated in Section 1 and Section 3, graphene is a self-contained layer without any dangling bonds, thus adhesion and interfaces with graphene are a challenge. Multiple groups have been

**4.2. Metallic doping by source drain contacts in graphene**

charge buildup at the band edges and large contact resistances. [56]

applications.

74 Graphene - New Trends and Developments

face.

to enhance bolometric response. [45, 57]

**4.3. Dielectric deposition and trap states**

To overcome some of the short channel issues and problems with graphene integration into common process flows, a wafer bonding type of integration has been suggested as shown in Figure 19. [59] This allows for the separation of the drain and gate contacts, which reduces coupling and alleviates some of the issues with drain induced barrier lowering. [60]

**Figure 19.** Wafer bonding with subsequent source drain contact deposition [59].

Gate coupling is a significant issue with graphene FETs due to the large gate voltages needed to create sufficient barriers for high Ion/Ioff ratios, the metallic characteristic of the graphene layer, the thin gate oxide needed to ensure good gate control and reduced gate potential for smaller electrical field propagation, and finally the dielectric breakdown strength. [60] All of these needs show that a thin high-k gate with opposing gate and source drain contact geometry is desired as shown in Figure 19.

Graphene devices have a very thin cross section where the active electric field can affect one another. It has been shown that by using tapered contacts as shown in Figure 20, the amount of source drain coupling is reduced due to electric field reduction. [60] This is especially effective if utilizing a back gate design as shown later in Figure 21, or a large gate that could overlap the source and drain contacts on the opposing side of the devices channel. [55, 60]

**Figure 20.** Tapered contacts used on opposing sides of the gate to reduce [60].
