**4.5. Graphene FET and RF electronic performance**

In order to create a device that allows for the opening of a band gap required for current saturation and appropriate voltage and current gains, several device geometries have been proposed. [16, 55] The main mechanisms for increasing graphene performance in FETs is to increase gate coupling with graphene layer and to optimize the graphene dielectric interface to reduce scattering and make the conduction and valence states continuous. [16]

One possible device geometry shown in Figure 21 utilizes a bilayer graphene channel with a large backgate voltage to induce an electric field of 1.7 V/nm that opens a band gap in bilayer graphene of 80 meV with the Mexican hat shape shown in Figure 2iv. [16, 55] The band gap creates a saturation current due to pinchoff at the drain contact resulting in a voltage gain of 35, which is relevant for RF electronics.

**Figure 21.** Diagram of a B-bilayer graphene FET with back contact to create a pinchoff region and voltage gain [55].

This mechanism works much better for bilayer graphene than monolayer graphene as bilayer graphene more easily forms a pinchoff region. To demonstrate this, the amount of voltage gain in such a graphene FET is graphed as contour plots with voltage gain axis on the right hand side of the graph as shown in Figure 22. [55]

**Figure 22.** Contour maps of voltage gain in a single layer and bilayer graphene channel with modification of back gate voltage [55].

Current designs for graphene FETs are shown in Figure 23, with the back gated design commonly used to overcome any doping in the graphene channel due to substrate, atmos‐ pheric, or dielectric effects. [16] The back gate and top gate design are the most common since these allow for the shifting of the Dirac point to zero through an induced electric field and proper gate modulation. [16]

**Figure 23.** Image showing the most common designs for GFETs [16]

**Figure 20.** Tapered contacts used on opposing sides of the gate to reduce [60].

In order to create a device that allows for the opening of a band gap required for current saturation and appropriate voltage and current gains, several device geometries have been proposed. [16, 55] The main mechanisms for increasing graphene performance in FETs is to increase gate coupling with graphene layer and to optimize the graphene dielectric interface

One possible device geometry shown in Figure 21 utilizes a bilayer graphene channel with a large backgate voltage to induce an electric field of 1.7 V/nm that opens a band gap in bilayer graphene of 80 meV with the Mexican hat shape shown in Figure 2iv. [16, 55] The band gap creates a saturation current due to pinchoff at the drain contact resulting in a voltage gain of

**Figure 21.** Diagram of a B-bilayer graphene FET with back contact to create a pinchoff region and voltage gain [55].

This mechanism works much better for bilayer graphene than monolayer graphene as bilayer graphene more easily forms a pinchoff region. To demonstrate this, the amount of voltage gain in such a graphene FET is graphed as contour plots with voltage gain axis on the right hand

to reduce scattering and make the conduction and valence states continuous. [16]

**4.5. Graphene FET and RF electronic performance**

76 Graphene - New Trends and Developments

35, which is relevant for RF electronics.

side of the graph as shown in Figure 22. [55]

Utilizing a three-terminal top gate design of CVD graphene grown on a SiC substrate, one group was able to achieve a 350 GHz cutoff frequency, utilizing a channel length of 40 nm as shown in Figure 24. [61]

Figure 24.<sup>61</sup>

Utilizing a three-terminal top gate design of CVD graphene grown on a SiC substrate, one group

 Figure 24. Image showing the threshold frequency versus gate length for the device **Figure 24.** Image showing the threshold frequency versus gate length for the device architectures shown on the left, the epitaxial graphene is on the SiC substrate, and the frequency shows a 1/L dependence [61].

architectures shown on the left, the epitaxial graphene is on the SiC substrate, and the frequency shows a 1/L dependence [61]. This group showed that the threshold frequency has a 1/L dependence, where L is the channel length of the graphene FET. This has been modeled and pushed to the limit with an understanding that graphene might be able to break the 1THz limit that InGaAs and SiGe HEMTs can't break.<sup>62</sup> One group theoretically tuned all of the parasitic capacitances that would limit the graphene channel mobility; this includes removing Schottky interactions at the source This group showed that the threshold frequency has a 1/L dependence, where L is the channel length of the graphene FET. This has been modeled and pushed to the limit with an under‐ standing that graphene might be able to break the 1THz limit that InGaAs and SiGe HEMTs can't break. [62] One group theoretically tuned all of the parasitic capacitances that would limit the graphene channel mobility; this includes removing Schottky interactions at the source and drain contacts, removal of any trapped states in the oxide, ignoring any electron/hole pooling effects, and having the gate voltage perfectly coupled to channel potential, allowing for a GFET that operates at 1.5 THz. [62] This GFET is optimized to have zero gain due to the current saturation in the 50 nm channel. [62] By allowing for current saturation in the GFET, a voltage gain can be engineered in the graphene channel; however, this would deteriorate the operating frequency of the GFET as shown in Figure 25. [62]

**Figure 25.** An image showing the threshold frequency for each possible gain in a GFET for systems with different amounts of tuning of parasitic resistance; the blue line has no parasitic resistance [62].
