**Meet the editors**

Stephen E. Saddow is a Professor of Electrical Engineering and member of the Biomedical Engineering Faculty, College of Engineering, at the University of South Florida, Tampa, FL USA. He has been an active researcher in the field of SiC Technology since 1992, when he pioneered the use of 6H-SiC for high-power optical switching. Since this early work, he has specialized in

the development of various SiC processing methods, most notably CVD of 3C-SiC on Si. In the last decade he has focused on the use of 3C-SiC for biomedical applications and has been developing SiC-based continuous glucose monitoring systems and neural implants. He has over 150 published papers, 3 books, several book chapters and has several patents, awarded or pending, on the use of SiC for biomedical applications. He has held several visiting researcher/professor positions in Italy, Germany, France, and more recently Brazil.

Francesco La Via was born in Catania, Italy, in September 1961. He received the M.S. degree in physics from Catania University, Italy, in 1985. From 1985 to 1990 he had a fellowship at STMicroelectronics, Catania and was a Visiting Scientist at Philips National Laboratory, Eindhoven, Netherlands. In 1990 he joined the CNR Institute for Microelectronic, Catania as a researcher. In

2001 he became senior researcher and from 2003 he has been responsible of the division of CNR-IMM that develops new processes for silicon carbide epitaxy and hetero-epitaxy. From 2013 he has been in the International Steering Committee of the ICSCRM conference. In 2015 he became co-Chair of the ICSCRM 2015 and Chair of the Technical Program Committee. In this period he published more than 300 papers on JCR journals, one e-book, a focus issue of JMR and three book chapters. He has presented nine invited contributions to international conferences. He has 10 patents on SiC processing.

## Contents

**Preface XI**



#### **Section 3 Novel SiC Devices 197**


## Preface

**Section 3 Novel SiC Devices 197**

**VI** Contents

**Al2O3 Films 199** Feng Zhang

Chapter 7 **High-responsivity SiC Ultraviolet Photodetectors with SiO2 and**

Chapter 8 **Silicon Carbide for Novel Quantum Technology Devices 221** Stefania Castelletto, Lorenzo Rosa and Brett C. Johnson

> The field of Silicon Carbide has seen steady growth since pioneering work by Nishino and Powell in 1983 when they demonstrated the large-area growth of silicon carbide (SiC) on silicon (Si) substrates. This was the first time that a cost-effect method for producing highquality SiC material was demonstrated with the possibility of scaling up the technology for industrial applications. While the growth of hexagonal crystals of SiC had been demonstrat‐ ed by Lely and others as early as the 1950s, it was the possibility of producing scalable sub‐ strates of SiC, in this case the cubic polytype known as 3C-SiC, that led to a renaissance in SiC technology. One could argue that this event stimulated renewed efforts to develop highquality hexagonal substrates of SiC which would allow for the homo-epitaxy of device lay‐ ers leading to such technologically important devices as blue LEDs. The group of Bob Davis at NC State was able to develop cost-effect methods to grow high-quality bulk crystals of 6H-SiC which led to the founding of Cree Research (now Cree Inc.) and the first commer‐ cially available blue LED in the late 1980s. As they say 'the rest is history' and the story of how Cree and other companies globally led us to the current state of SiC technology is well known, resulting in a billion-dollar industry world-wide in the area of solid-state lighting and power electronics. With this in mind, we organized this book to bring to the attention of those well versed in SiC technology some new developments in the field with a particular emphasis on particularly promising technologies such as SiC-based solar cells and optoelec‐ tronics. We have attempted to balance this with the more traditional subjects such as power electronics (DC to DC converters, for example), and some new developments in the im‐ provement of the MOS system for SiC MOSFETS. Staying true to the original stimulation of the last quarter century of SiC activity, we also included a review on 3C-SiC for both micro‐ system and electronic applications. We sincerely hope that this somewhat eclectic mix of topics will be both highly interesting to the reader while helping those who wish to develop SiC materials for use in areas other than main-stream power electronics. It was our distinct pleasure and honor to edit this impressive collection of works from around the world and we wish you an enjoyable experience as you read the book, as we believe it will result in further developments in the field of SiC which continues to grow exponentially world-wide.

> > **Stephen E. Saddow, PhD** Professor of Electrical Engineering, University of South Florida, Tampa, FL USA

**Francesco La Via, PhD** Italian National Research Council, Catania, Sicily, Italy

**Section 1**

## **SiC Device Processing**

## **Silicon Carbide in Microsystem Technology — Thin Film Versus Bulk Material**

Mariana Amorim Fraga, Matteo Bosi and Marco Negri

Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/60970

#### **Abstract**

This chapter looks at the role of silicon carbide (SiC) in microsystem technology. It starts with an introduction into the wide bandgap (WBG) materials and the properties that make them potential candidates to enable the development of harsh environment microsystems. The future commercial success of WBG microsystems depends mainly on the availability of high-quality materials, well-established microfabrication processes, and economic viability. In such aspects SiC platform, in relation to other WBG materials, provides a clear and competitive advantage. The reasons for this will be detailed. Furthermore, the current status of the SiC thin film and bulk material technologies will also be discussed. Both SiC material forms have played important roles in different microsystem types.

**Keywords:** silicon carbide, thin film, bulk material, microsystem technology, harsh environment

#### **1. Introduction**

As the most popular microelectronic material, silicon (Si) has established itself as the main material for microsystem technology (MST) or micro-electro-mechanical systems (MEMS). This occurred for a number of reasons, including the mechanical properties of silicon (in single crystal form, it is almost a perfect Hookean material and hence no energy dissipation occurs) and economic issues (ready availability of low-cost high-quality materials) [1].

© 2015 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Advances in microsystem technology have frequently been linked to innovations in the development of advanced materials that can outperform conventional semiconductors: not only Si, but also germanium (Ge) and gallium arsenide (GaAs) [2, 3].

In order to enable wide applications in harsh environments, the goal is to develop microsys‐ tems able to go beyond the limits of those of conventional semiconductors. In the search for advanced materials to be used in MEMS devices, the wide bandgap (WBG) semiconductors are recognized as the most promising. These semiconductors possess remarkable electronic properties that Si and other conventional materials lack. WBG semiconductors have a high bandgap, more than 2.0 eV, whereas the conventional semiconductors have a small bandgap (around 1.0 eV). One impact of this is that the WBG semiconductor devices can be employed at elevated temperatures [4].

Besides the excellent electronic properties, WBG semiconductors exhibit superior physical properties, as well as chemical inertness, overcoming the limitations of traditional siliconbased platforms in harsh conditions. Thus, WBG MEMS sensing element can be directly exposed to harsh environment media, which may reduce the cost of packaging [5].

**Figure 1.** Wide bandgap semiconductor materials with potential for use in microsystem technology

Other important properties of WBG semiconductors are high Young's modulus, hardness, and fracture toughness. Such characteristics are also potentially interesting for microsystem applications given that the Si has relatively low values [6].


**Table 1.** Properties of SiC, diamond, and GaN

Advances in microsystem technology have frequently been linked to innovations in the development of advanced materials that can outperform conventional semiconductors: not

In order to enable wide applications in harsh environments, the goal is to develop microsys‐ tems able to go beyond the limits of those of conventional semiconductors. In the search for advanced materials to be used in MEMS devices, the wide bandgap (WBG) semiconductors are recognized as the most promising. These semiconductors possess remarkable electronic properties that Si and other conventional materials lack. WBG semiconductors have a high bandgap, more than 2.0 eV, whereas the conventional semiconductors have a small bandgap (around 1.0 eV). One impact of this is that the WBG semiconductor devices can be employed

Besides the excellent electronic properties, WBG semiconductors exhibit superior physical properties, as well as chemical inertness, overcoming the limitations of traditional siliconbased platforms in harsh conditions. Thus, WBG MEMS sensing element can be directly

exposed to harsh environment media, which may reduce the cost of packaging [5].

**Figure 1.** Wide bandgap semiconductor materials with potential for use in microsystem technology

only Si, but also germanium (Ge) and gallium arsenide (GaAs) [2, 3].

at elevated temperatures [4].

4 Advanced Silicon Carbide Devices and Processing

**Figure 2.** Recent evolution of the diameter of commercially available SiC wafer

WBG semiconductors can be grouped into three main categories: (i) carbon-based materi‐ als, (ii) nitride-based materials, and (iii) oxide-based materials. Among them, Figure 1 highlights some examples of WBG semiconductors that are being successful employed in MEMS sensors: diamond [6], diamond like-carbon (DLC) [7], metal-containing DLC (Me-DLC) [8], silicon carbide (SiC) [3], gallium nitride (GaN) [2], aluminum nitride (AlN) [9], and zinc oxide (ZnO) [10].

There is a consensus that the WBG semiconductors are the materials for harsh environment microdevices*.* However, there are differences and particularities among the different WBG semiconductor types. This leads us to ask which would be the best WBG semiconductors for use in microsystems. SiC, GaN, and diamond are considered with greatest potential due to their outstanding properties (see Table 1) and commercial availability of wafers [11-13]. From a material properties perspective, diamond has superior properties to SiC and GaN, except for its easy oxidation at high temperatures [5].

The technological development of SiC, diamond, and GaN material-based platforms are maturing in three directions: (i) production of wafers, (ii) techniques for micromachining, and (iii) materials integration. These platforms compete with each other*.* Currently, among them, SiC platform is the most established for harsh environment device applications.

Much progress in terms of quality and dimensions has been made in SiC wafer production. The 4" SiC wafers are the mainstream product on the market and recently 6" wafers were introduced, although the supply is still limited. Figure 2 shows the evolution SiC wafer size in the last years [14]. This diameter increase is crucial for reducing the cost of microdevices through scale economies and the use of Si device fabrication equipment.

In Figure 3, the price per area of SiC substrate wafer is compared with those of Si, diamond, and GaN. SiC substrate is cheaper than other WBG semiconductors [15]. However, the quality is not as good as Si wafers and the cost is significantly higher.

Silicon Carbide in Microsystem Technology — Thin Film Versus Bulk Material http://dx.doi.org/10.5772/60970 7

**Figure 3.** Comparison among the price of wafers of silicon, sapphire, silicon carbide, and gallium nitride (adapted from [15])

WBG semiconductors can be grouped into three main categories: (i) carbon-based materi‐ als, (ii) nitride-based materials, and (iii) oxide-based materials. Among them, Figure 1 highlights some examples of WBG semiconductors that are being successful employed in MEMS sensors: diamond [6], diamond like-carbon (DLC) [7], metal-containing DLC (Me-DLC) [8], silicon carbide (SiC) [3], gallium nitride (GaN) [2], aluminum nitride (AlN) [9],

**Figure 2.** Recent evolution of the diameter of commercially available SiC wafer

There is a consensus that the WBG semiconductors are the materials for harsh environment microdevices*.* However, there are differences and particularities among the different WBG semiconductor types. This leads us to ask which would be the best WBG semiconductors for use in microsystems. SiC, GaN, and diamond are considered with greatest potential due to their outstanding properties (see Table 1) and commercial availability of wafers [11-13]. From a material properties perspective, diamond has superior properties to SiC and GaN, except for

The technological development of SiC, diamond, and GaN material-based platforms are maturing in three directions: (i) production of wafers, (ii) techniques for micromachining, and (iii) materials integration. These platforms compete with each other*.* Currently, among them,

Much progress in terms of quality and dimensions has been made in SiC wafer production. The 4" SiC wafers are the mainstream product on the market and recently 6" wafers were introduced, although the supply is still limited. Figure 2 shows the evolution SiC wafer size in the last years [14]. This diameter increase is crucial for reducing the cost of microdevices

In Figure 3, the price per area of SiC substrate wafer is compared with those of Si, diamond, and GaN. SiC substrate is cheaper than other WBG semiconductors [15]. However, the quality

SiC platform is the most established for harsh environment device applications.

through scale economies and the use of Si device fabrication equipment.

is not as good as Si wafers and the cost is significantly higher.

and zinc oxide (ZnO) [10].

6 Advanced Silicon Carbide Devices and Processing

its easy oxidation at high temperatures [5].

Another point related to SiC platform for developing MEMS devices is to establish a fabrication technology comparable to its silicon technology counterpart. One obstacle is the strong chemical stability of high quality SiC bulk, which makes its etching difficult for the fabrication of SiC MEMS structures. To overcome this drawback, the integration of SiC film with Si or SOI (silicon-on-insulator) substrates is a good alternative because it allows the fabrication of SiCbased MEMS through common Si micromachining processes.

Discussion and questions about applications of SiC thin film versus bulk material are opened. There are differences among material properties of each form. However, recent literature has shown that SiC in both forms, thin film and bulk material, play important roles in microsystem technology but each settle into its own role. There are interesting sensing devices that can be produced using both material forms.

SiC thin film has been used in different microsystem devices in different functions such as sensing layer (transduction element), buffer layer, and biocompatible coating. SiC bulk material allows the fabrication of all-SiC microsystem device (structural and sensing elements), which increase its performance especially in harsh environments. According to D. G. Jones's PhD thesis: "One vision of the future is an all-SiC sensor chip composed of crystalline SiC substrate, doped polycrystalline SiC structures, and sputtered amorphous SiC sealing layers" [16].

There is optimism about the feasibility of SiC thin film technology in microsystem applications, but the film growth on large area substrate without loss of uniformity or quality is still a challenge.

The purpose of this chapter is to give an outline of the current landscape of SiC key technologies for microsystem applications. The following SiC technologies are described addressing the bulk material and thin film: synthesis, material properties (quality), material processing, and microsystem device development.

#### **2. SiC material issues for microsystem technology applications**

Although there are over 200 known polytypes of SiC, only a few are grown with good reproducibility and attractive properties for microelectronics applications [17]. The polytypes of SiC commonly used in such applications are 3C-SiC, 4H-SiC, and 6H-SiC, which can be synthesized in thin film or wafer forms using different methods. The growth of SiC involves challenges related to the control of (i) polytype formation, (ii) defects, and (iii) doping.

The availability of high-quality SiC material with lower defect density and controlled doping is very important to ensure high fabrication yields and good device performance. For the last couple of decades, the quality of SiC wafer has been significantly improved. Likewise, the growth of high-quality SiC film on Si large wafers is becoming more mature. Unfortunately, thin-film growth methods still seek to obtain 3C-SiC films with properties comparable to those of hexagonal SiC bulk material.

Aside from material growth issues, micromachining of SiC has been the subject of intensive research in recent years for its application in MEMS devices. Several bulk and surface micro‐ machining techniques have been studied for the fabrication of three-dimensional SiC MEMS structures. Nevertheless, despite the advances in deep dry etching methods for SiC bulk micromachining, the process is still complex. On the other hand, SiC-on-Si substrates are attractive for implementing MEMS devices because they combine the well-established Si wet bulk micromachining process with the outstanding sensing properties of SiC thin film.

In the next sections, the issues of growth and micromachining of SiC bulk and thin film will be reviewed.

#### **2.1. Bulk (or substrate)**

#### *2.1.1. Bulk crystal growth and material quality*

The crystal ingot of conventional semiconductors as Si, Ge, and GaAs are grown by melt methods, which are not suitable for SiC crystal growth because its stoichiometric melting only occurs at pressures above 10 GPa and temperatures higher than 3200 °C [18]. In addition, SiC bulk crystal growth involves challenges attributed to the physical-chemical nature of SiC such as polytypism and extreme thermodynamic properties (noncongruent melting at high temperatures) making difficult the production of semiconductor grade SiC ingots. Figure 4 compares the production of SiC wafers per ingot with ones of Si, sap‐ phire (Al2O3), and GaN [19].

Thus as SiC and GaN, sapphire has high melting point and chemical inertness. However, few micromachining processes exist making fabrication of MEMS type structures difficult [20]. So, although sapphire is a promising high temperature material with lower cost, it does not compete with SiC in microsystem applications.

As illustrated in Figure 5, SiC substrates can be grown by methods based on vapor phase or solution phase. The vapor phase growth processes are the most common and are divided in Silicon Carbide in Microsystem Technology — Thin Film Versus Bulk Material http://dx.doi.org/10.5772/60970 9

**Figure 4.** Comparison among production and price of SiC wafers with ones of Si, Al2O3, and GaN

**Figure 5.** Main methods used for SiC substrate growth

**2. SiC material issues for microsystem technology applications**

of hexagonal SiC bulk material.

8 Advanced Silicon Carbide Devices and Processing

be reviewed.

**2.1. Bulk (or substrate)**

phire (Al2O3), and GaN [19].

*2.1.1. Bulk crystal growth and material quality*

compete with SiC in microsystem applications.

Although there are over 200 known polytypes of SiC, only a few are grown with good reproducibility and attractive properties for microelectronics applications [17]. The polytypes of SiC commonly used in such applications are 3C-SiC, 4H-SiC, and 6H-SiC, which can be synthesized in thin film or wafer forms using different methods. The growth of SiC involves challenges related to the control of (i) polytype formation, (ii) defects, and (iii) doping.

The availability of high-quality SiC material with lower defect density and controlled doping is very important to ensure high fabrication yields and good device performance. For the last couple of decades, the quality of SiC wafer has been significantly improved. Likewise, the growth of high-quality SiC film on Si large wafers is becoming more mature. Unfortunately, thin-film growth methods still seek to obtain 3C-SiC films with properties comparable to those

Aside from material growth issues, micromachining of SiC has been the subject of intensive research in recent years for its application in MEMS devices. Several bulk and surface micro‐ machining techniques have been studied for the fabrication of three-dimensional SiC MEMS structures. Nevertheless, despite the advances in deep dry etching methods for SiC bulk micromachining, the process is still complex. On the other hand, SiC-on-Si substrates are attractive for implementing MEMS devices because they combine the well-established Si wet bulk micromachining process with the outstanding sensing properties of SiC thin film.

In the next sections, the issues of growth and micromachining of SiC bulk and thin film will

The crystal ingot of conventional semiconductors as Si, Ge, and GaAs are grown by melt methods, which are not suitable for SiC crystal growth because its stoichiometric melting only occurs at pressures above 10 GPa and temperatures higher than 3200 °C [18]. In addition, SiC bulk crystal growth involves challenges attributed to the physical-chemical nature of SiC such as polytypism and extreme thermodynamic properties (noncongruent melting at high temperatures) making difficult the production of semiconductor grade SiC ingots. Figure 4 compares the production of SiC wafers per ingot with ones of Si, sap‐

Thus as SiC and GaN, sapphire has high melting point and chemical inertness. However, few micromachining processes exist making fabrication of MEMS type structures difficult [20]. So, although sapphire is a promising high temperature material with lower cost, it does not

As illustrated in Figure 5, SiC substrates can be grown by methods based on vapor phase or solution phase. The vapor phase growth processes are the most common and are divided in two main types: (i) physical vapor transport (PVT) also called as seeded sublimation method or modified Lely and (ii) high temperature chemical vapor deposition (CVD). With the evolution of these processes, new techniques have emerged, namely, modified PVT method, continuous feed PVT (CF-PVT), and halide CVD [21].

Table 2 summarizes the main vapor phase processes for SiC crystal growth. The first process for growth of high-purity SiC crystal was reported by Lely in 1955. This process allowed the


**Table 2.** Description and drawbacks of vapor phase methods for SiC crystal growth

synthesis of SiC with suitable quality for use in electronic devices, which was not possible using the previous method demonstrated by Acheson in 1892. One limitation of the Lely method is the growth of small SiC substrates only up to 10 mm in diameter.

In 1978, Tairov and Tsvetkov modified the Lely method allowing the production of large dimension SiC wafer with good quality. The modified Lely process became the main industrial method for fabrication of SiC wafer substrates of polytypes 4H-SiC and 6H-SiC with different thicknesses and doping (n-type, p-type, and semi-insulating). Regarding the 3C-SiC polytype, the CVD methods have been most used to grow it heteroepitaxially on different substrates, especially silicon. Large monocrystal 3C-SiC substrates with at least 200 micrometers thickness after removing the Si base layer are being produced [22].

Although the thermodynamic properties of SiC do not allow the solution phase bulk growth of SiC from a stoichiometric melt, it is possible to grow SiC from non-stoichiometric solutions containing Si and C. These solution growth processes have been developed based on the solubility of SiC and C in Si melt [21]. A problem is the very low carbon solubility in liquid silicon below 1800°C. It has been shown that the use of Si-metal growth flux is a good alter‐ native to increase the carbon solubility [23]. Despite significant recent progress in solution phase growth, this method is still not well-established to the production of substrates like the PVT and CVD methods.

As pointed out in the previous sections, the wide use of SiC in semiconductor and MEMS devices is limited by high price of high-quality wafers. Controlling different types of defects has been a critical challenge for SiC wafer technology [24].

In general, defects may compromise the structural integrity of the crystal, or alter its electrical, chemical, and thermal properties. A number of defects in SiC crystals have been reported, including different types of dislocations (mainly open-core screw dislocations called micro‐ pipes), low-angle boundaries, macro-inclusions, chemical impurities, and inhomogeneity in either dopant or polytype [25]. Among them, the micropipes are the most common obstacle to the production of high quality SiC devices. The origins of the formation of micropipes during crystal growth are not entirely known, but it seems to involve the propagations of dislocations in the nucleation phase or contaminant particles present upon crystallization [25].

With the continuous improving of wafer manufacturing processes, a significant reduction of micropipe densities has been achieved. Nowadays, there are commercial 2" and 3" SiC wafers with micropipe density less than 1/cm2 and 4" diameter with less than 10/cm2 [14]. However, it has been observed that the quality of new larger wafers is relatively lower compared to prior generations [24]. The challenge of SiC wafer technology is increasing the wafer diameter keeping low levels of defects.

#### *2.1.2. Bulk micromachining*

synthesis of SiC with suitable quality for use in electronic devices, which was not possible using the previous method demonstrated by Acheson in 1892. One limitation of the Lely

**Method Description Drawback Year**

In general, the SiC grown by this method is contaminated and not suitable for electronic devices.

The control of polytype, size, and doping of the crystal is very limited. SiC crystals only up to 10 mm in

The control of polytype and doping

Technological challenges harder than for PVT control of the thermodynamic

concentrations is difficult.

diameter.

conditions.

1892

1955

1978

1996

The process is based on reduction of silica (SiO2) and carbon at temperatures above

Sublimation of SiC at elevated temperatures (2550–2600ºC) and normal pressure. It was the first method developed for high purity

Polycrystalline SiC at the source sublimes at a high temperature (1800–2600ºC) and low pressure. It is the most mature growth process and allows the production large dimension SiC wafer with good quality.

SiC growth is carried out using conventional silicon and carbon gas precursors. It is

**Table 2.** Description and drawbacks of vapor phase methods for SiC crystal growth

possible to grow long ingots.

2000ºC.

10 Advanced Silicon Carbide Devices and Processing

SiC crystal growth.

In 1978, Tairov and Tsvetkov modified the Lely method allowing the production of large dimension SiC wafer with good quality. The modified Lely process became the main industrial method for fabrication of SiC wafer substrates of polytypes 4H-SiC and 6H-SiC with different thicknesses and doping (n-type, p-type, and semi-insulating). Regarding the 3C-SiC polytype, the CVD methods have been most used to grow it heteroepitaxially on different substrates, especially silicon. Large monocrystal 3C-SiC substrates with at least 200 micrometers thickness

Although the thermodynamic properties of SiC do not allow the solution phase bulk growth of SiC from a stoichiometric melt, it is possible to grow SiC from non-stoichiometric solutions containing Si and C. These solution growth processes have been developed based on the solubility of SiC and C in Si melt [21]. A problem is the very low carbon solubility in liquid silicon below 1800°C. It has been shown that the use of Si-metal growth flux is a good alter‐ native to increase the carbon solubility [23]. Despite significant recent progress in solution phase growth, this method is still not well-established to the production of substrates like the

As pointed out in the previous sections, the wide use of SiC in semiconductor and MEMS devices is limited by high price of high-quality wafers. Controlling different types of defects

method is the growth of small SiC substrates only up to 10 mm in diameter.

after removing the Si base layer are being produced [22].

has been a critical challenge for SiC wafer technology [24].

PVT and CVD methods.

Acheson

Lely

Modified Lely (seeded sublimation or PVT process)

HTCVD

Fabrication of MEMS using SiC substrate is still immature when compared to those on silicon substrates or with the SiC power devices. The high thermal and chemical stability of SiC make certain fabrication steps difficult. Etching has required particular attention because etch depths of at least 200 *μ*m are required for bulk micromachined SiC structures [26].

Wet etching in potassium hydroxide (KOH) solution at temperatures between 70ºC and 90ºC is the most used method to fabricate Si MEMS structures due to its advantages like low cost and simple experimental procedure [27]. However, this process is not practical for SiC.

There are no simple wet-chemical etchants for SiC available suitable for device fabrication. Chemical etching is only possible under rather extreme conditions, for example, in molten KOH, NaOH, or Na2O2 at 450–600ºC. This process usually creates defects on the surface besides severe contamination from K or Na [28, 29].

The plasma-based dry etching has been shown as a practical way to deep etch SiC for the fabrication of MEMS. Fluorine-based plasmas have the most effective etch rate. An advantage is that the fluorinated etch products (SiF, and CF, species) are relatively volatile, and their removal from the surface is generally not the rate-limiting step [30]. Most commonly plasma sources employed in SiC etching are reactive ion etching (RIE), electron cyclotron resonance (ECR), and inductively coupled plasma (ICP). Much effort has been devoted to understanding the etch mechanisms in these processes in order optimize etching conditions such as pressure, gas flow rate, power, time, etc.

The SiC RIE process has been investigated in fluorinated gases (mainly CF4, SF6, and NF3), usually mixed with oxygen using standard silicon RIE hardware [31]. Generally, SiC RIE process is highly anisotropic with little undercutting of the etch mask, leaving smooth surfaces. Typical RIE etch rate for 4H- and 6H-SiC are in the order of hundreds of angstroms per minute. In this range, the etch rates are sufficient for the fabrication of many electronic devices, but not for MEMS sensors and some very high voltage power device structures. In such applications, SiC etch rates on the order of tens to hundreds of micrometers deep are required [31].

High density plasma dry etching techniques, such as ECR and ICP, are very promising for deep etching of SiC. The ECR process allows producing very smooth etched surfaces and the control of the degree of anisotropy by the substrate bias. ICP because of high flux with lowerion energy enables the achievement of excellent anisotropy, low surface damage, smooth morphology, and high etch rate for SiC even at relatively low-bias voltages [32].

A challenge of dry etching processes is the mask. The dry-etch contrast ratio between SiC and typical mask materials as photoresist is low. Thereby deep dry etching requires a hard mask, typically metal such as aluminum (Al), nickel (Ni), or chromium (Cr), to obtain a high etch selectivity [33]. However, many plasma etch systems cannot tolerate the contamination caused by metal etching as a degradation in the health of internal components and electrical shorting occurs [34]. In addition, the presence of a fast-diffusing metal such as Ni within the silicon CMOS fab requires special contamination control precautions [33]. Apart from contamination, during high rate etching, micromasking defects on the etch surface often occurs causing undesirable roughening [34].

Some studies have been conducted to enable the use of non-metallic masks in SiC dry etching, for example, (i) replacing the fluorine-based plasmas by HBr/Cl2, which allows the use of SiO2 as etch mask, and (ii) using the AlN as mask material in etching with SF6/O2 plasmas [34]. Although both approaches have resulted in etch rate and selectivity lower than those reported to metal masks, a further characterization and optimization of the etch systems can make them promising in SiC MEMS fabrication.

#### **2.2. Thin film**

#### *2.2.1. Growth*

#### *2.2.1.1. Growth of hexagonal polytypes*

The main motivation for the homoepitaxial growth of 4H-SiC is to obtain thick and high quality layers to be used as active regions of power devices and switches with lower losses than conventional silicon-based devices. The 10-kV class SiC P-i-N diodes and insulated gate bipolar transistors (IGBTs) have been fabricated. Furthermore, SiC power Schottky barrier diodes (SBDs), metal-oxide-semiconductor field effect transistors (MOSFETs), and junction fieldeffect transistors (JFETs) have been already commercialized.

High-quality 4H-SiC epilayers with low defects density are required to fulfill the high performance of SiC power devices. The technology for the realization of bulk 4H-SiC substrates is nowadays well developed but their quality and the possibility to control doping is inferior to the one permitted by epitaxial techniques. Moreover, to realize complex devices, precise control of doping, stacking layers with controlled doping and realization of p-n junction is mandatory. The necessity of very thick epitaxial layers (up to 100 µm) comes from the high bandgap of the material: the breakdown voltage is limited by the depletion region width, which depends on the doping level. In order to realize diodes and switches for high-voltage and high power applications, it is necessary to have a material with very low doping concen‐ tration, which leads to a very wide depletion layer inside the junction. For this reason, a lot of efforts have been made to develop epitaxial techniques that permit the growth of very thick layers in a reasonable time, maintaining a high material quality.

for MEMS sensors and some very high voltage power device structures. In such applications,

High density plasma dry etching techniques, such as ECR and ICP, are very promising for deep etching of SiC. The ECR process allows producing very smooth etched surfaces and the control of the degree of anisotropy by the substrate bias. ICP because of high flux with lowerion energy enables the achievement of excellent anisotropy, low surface damage, smooth

A challenge of dry etching processes is the mask. The dry-etch contrast ratio between SiC and typical mask materials as photoresist is low. Thereby deep dry etching requires a hard mask, typically metal such as aluminum (Al), nickel (Ni), or chromium (Cr), to obtain a high etch selectivity [33]. However, many plasma etch systems cannot tolerate the contamination caused by metal etching as a degradation in the health of internal components and electrical shorting occurs [34]. In addition, the presence of a fast-diffusing metal such as Ni within the silicon CMOS fab requires special contamination control precautions [33]. Apart from contamination, during high rate etching, micromasking defects on the etch surface often occurs causing

Some studies have been conducted to enable the use of non-metallic masks in SiC dry etching, for example, (i) replacing the fluorine-based plasmas by HBr/Cl2, which allows the use of SiO2 as etch mask, and (ii) using the AlN as mask material in etching with SF6/O2 plasmas [34]. Although both approaches have resulted in etch rate and selectivity lower than those reported to metal masks, a further characterization and optimization of the etch systems can make them

The main motivation for the homoepitaxial growth of 4H-SiC is to obtain thick and high quality layers to be used as active regions of power devices and switches with lower losses than conventional silicon-based devices. The 10-kV class SiC P-i-N diodes and insulated gate bipolar transistors (IGBTs) have been fabricated. Furthermore, SiC power Schottky barrier diodes (SBDs), metal-oxide-semiconductor field effect transistors (MOSFETs), and junction field-

High-quality 4H-SiC epilayers with low defects density are required to fulfill the high performance of SiC power devices. The technology for the realization of bulk 4H-SiC substrates is nowadays well developed but their quality and the possibility to control doping is inferior to the one permitted by epitaxial techniques. Moreover, to realize complex devices, precise control of doping, stacking layers with controlled doping and realization of p-n junction is mandatory. The necessity of very thick epitaxial layers (up to 100 µm) comes from the high bandgap of the material: the breakdown voltage is limited by the depletion region width,

SiC etch rates on the order of tens to hundreds of micrometers deep are required [31].

morphology, and high etch rate for SiC even at relatively low-bias voltages [32].

undesirable roughening [34].

12 Advanced Silicon Carbide Devices and Processing

promising in SiC MEMS fabrication.

*2.2.1.1. Growth of hexagonal polytypes*

effect transistors (JFETs) have been already commercialized.

**2.2. Thin film**

*2.2.1. Growth*

The 4H-SiC homoepitaxy permits to obtain a material with far superior crystalline quality and lower defect density with respect of 3C-SiC/Si, due to the absence of lattice and thermal mismatch, far superior device performances could be obtained and the adoption of singlecrystalline 4H-SiC can significantly extend the range of applicability of MEMS devices in harsh environments. The recent development of photo-electrochemical etching [35] to fabricate MEMS in 4H-SiC increased even more the interest for 4H-SiC homoepitaxy, as will be discussed in the following sections.

The 4H-SiC substrates for SiC homoepitaxy are nowadays commercially available. Due to stacking of Si and C atoms, SiC is a polar material so the substrate surface can actually end with a Si plane or a C plane depending on the crystalline orientation. Si-face substrates are more commonly used because permit to lower the residual nitrogen incorporation with respect of C-face substrates.

Usually, the homoepitaxial 4H-SiC growth is carried out on off-axis substrates, the most common misorientation being about 4° off. It has been found that (0001) vicinal surfaces, due to the presence of surface steps on the growth surface, are able to suppress unwanted polytype formation, thus increasing the crystalline quality. It has also been found that the penetration of basal plane dislocations is effectively hindered in lower off-axis substrates. However, the epilayers grown on these substrates are more prone to form step-bunching and triangular extended defects, due to the presence of terraces [36].

Most of the defects found in the epitaxial layers propagate from the substrate or originate where substrate defects emerge at the surface. It is thus mandatory to deposit SiC onto a substrate with very low defect density, and a lot of effort is thus put in decreasing the substrates defect density, while increasing its size to reduce cost per area.

The most common defects found in the epilayers are: (i) downfalls [37], usually particles formed in the gas phase then precipitated on film surface, (ii) carrots [38, 39], comets [40], or triangular defects [41], elongated defects along the step-flow growth direction, which usually indicate disturbance in the step flow growth. All these defects are known to be device killers and a great effort has been put to optimize the epitaxial growth in order to limit their propa‐ gation.

Standard SiC epitaxy is usually carried out in vapor phase epitaxy (VPE) reactors at temper‐ atures between 1500°C and 1700°C, using silane and propane as precursor and hydrogen as carrier gas. The deposition process usually begins with an in situ H2 etching, in order to improve the substrate surface before the deposition of the epitaxial layer [42]. Depending on reactor configuration and process parameters, etching in H2+C3H8, H2+SiH4 or H2+HCl were also proposed. [43]. Typical C/Si ratios are between 1 and 2, while growth rates for epilayers are usually in the range 5–10 µm/h. However, in order to realize p-i-n junctions and devices able to block voltages of more than 4 kV, SiC thickness up to 50–100 µm are needed. With such low growth rates the epitaxial deposition needs a very long time and becomes unpractical and expensive. The main problem is that the increase of precursors flow to obtain a faster growth rate results in the formation of silicon droplets in the gas phase, which tends to deplete the nutrient phase and to precipitate on the substrate, thus reducing the epilayer quality. For this reason, the introduction of chlorinated species in the gas phase, such as HCl, methyltrichlor‐ osilane (CH3SiCl3, or MTS), trichlorosilane (SiHCl3, TCS), and SiCl4 was investigated. The chlorinated species bind with silicon species in the gas phase because the Cl-Si bond has a lower energy with respect to the Si-Si bond. This permit to avoid the formation and precipi‐ tation of Si aggregates and to maintain a mass-transport limited regime where the growth rate is usually linearly dependent on the silane flow. TCS is a precursor of choice of several research groups, since it is safer and more stable that SiH4 [44]. It brings to the gas mixture both Si and Cl so very high growth rate were achieved using this compound up to 100µm/h without silicon precipitates. Moreover, the use of this precursor has been shown to reduce defects such as basal plane dislocations, point defects, and single Shockley faults. Also, a smoother surface, with root means square roughness as low as 0.18 nm, was demonstrated. Another method to overcome Si reactions in the gas phase is to lower the reactor pressure up to 20–40 mbar but it is not as effective as the chlorine addition.

In order to realize SiC power device, an accurate control and optimization of doped layers is necessary. Doping concentration and uniformity over the substrate area and on all the substrate in a planetary reactor are key-issues for the performance of the devices. The N-type doping is usually carried out with nitrogen.

Nitrogen incorporation has been found to be enhanced by Si-rich gas phase, because N atoms substitute C sites in SiC lattice. P-type doping is less common in literature but is nevertheless very important for devices such as pin diodes and IGBTs. The most common dopant for the growth of p-type layers is aluminum, usually in the form of trimethyl aluminum (TMA). Aluminum tends to substitute Si in the lattice, and it was generally found to depend on the C/ Si ratio: at higher values the p-type doping was found to increase. Also, it was found to decrease with the Cl/Si ratio [45].

#### *2.2.1.2. Growth of 3C-SiC films*

Cubic silicon carbide (also called 3C or β) shows similar interesting features as the other polytypes, such as wide bandgap (2.39 eV), high breakdown field (2.2 x 106 V/cm), high thermal stability and conductivity, mechanical strength, Mohs hardness of roughly 9, and a Young's modulus that ranges between 330 GPa and 700 GPa depending on the polytype and measure‐ ment technique used to acquire the data. In addition to that, 3C-SiC has some peculiar features that fostered the attention of researchers. Among the three most common polytypes (3C, 6H, 4H), the cubic one has the highest saturated drift velocity (2.5 x 107 cm/s), which allows to obtain high channel currents in microwave devices [46] and it is helpful for high gain solid state devices. Owing to the higher symmetry and consequently a reduced phonon scattering, 3C-SiC has also the highest electron mobility (≈1000 cm2 /V.s) compared to the other polytypes. The mobility is directly linked to the conductivity of a semiconductor and having a high mobility means to be able to obtain a higher current. This will lead to faster capacitance charge. In general, a device built with a high mobility material has a better high frequency response. A high maximum current density is fundamental to increase the number of components per integrated circuit chip, to target large-scale integration. The thermal conductivity of cubic SiC is significant (3.2 W cm−1 K−1 (poly-3C)) even if compared to those of the most common metals, although slightly lower than other polytypes (3.6 W cm−1 K−1 for 6H–SiC and 3.7 W cm−1 K −1 for 4H–SiC). Additionally, cubic SiC is more and more used as a substrate for the epitaxial deposition of other materials such as gallium nitride [47] or boron nitride [48].

able to block voltages of more than 4 kV, SiC thickness up to 50–100 µm are needed. With such low growth rates the epitaxial deposition needs a very long time and becomes unpractical and expensive. The main problem is that the increase of precursors flow to obtain a faster growth rate results in the formation of silicon droplets in the gas phase, which tends to deplete the nutrient phase and to precipitate on the substrate, thus reducing the epilayer quality. For this reason, the introduction of chlorinated species in the gas phase, such as HCl, methyltrichlor‐ osilane (CH3SiCl3, or MTS), trichlorosilane (SiHCl3, TCS), and SiCl4 was investigated. The chlorinated species bind with silicon species in the gas phase because the Cl-Si bond has a lower energy with respect to the Si-Si bond. This permit to avoid the formation and precipi‐ tation of Si aggregates and to maintain a mass-transport limited regime where the growth rate is usually linearly dependent on the silane flow. TCS is a precursor of choice of several research groups, since it is safer and more stable that SiH4 [44]. It brings to the gas mixture both Si and Cl so very high growth rate were achieved using this compound up to 100µm/h without silicon precipitates. Moreover, the use of this precursor has been shown to reduce defects such as basal plane dislocations, point defects, and single Shockley faults. Also, a smoother surface, with root means square roughness as low as 0.18 nm, was demonstrated. Another method to overcome Si reactions in the gas phase is to lower the reactor pressure up to 20–40 mbar but it

In order to realize SiC power device, an accurate control and optimization of doped layers is necessary. Doping concentration and uniformity over the substrate area and on all the substrate in a planetary reactor are key-issues for the performance of the devices. The N-type

Nitrogen incorporation has been found to be enhanced by Si-rich gas phase, because N atoms substitute C sites in SiC lattice. P-type doping is less common in literature but is nevertheless very important for devices such as pin diodes and IGBTs. The most common dopant for the growth of p-type layers is aluminum, usually in the form of trimethyl aluminum (TMA). Aluminum tends to substitute Si in the lattice, and it was generally found to depend on the C/ Si ratio: at higher values the p-type doping was found to increase. Also, it was found to decrease

Cubic silicon carbide (also called 3C or β) shows similar interesting features as the other polytypes, such as wide bandgap (2.39 eV), high breakdown field (2.2 x 106 V/cm), high thermal stability and conductivity, mechanical strength, Mohs hardness of roughly 9, and a Young's modulus that ranges between 330 GPa and 700 GPa depending on the polytype and measure‐ ment technique used to acquire the data. In addition to that, 3C-SiC has some peculiar features that fostered the attention of researchers. Among the three most common polytypes (3C, 6H,

high channel currents in microwave devices [46] and it is helpful for high gain solid state devices. Owing to the higher symmetry and consequently a reduced phonon scattering, 3C-

The mobility is directly linked to the conductivity of a semiconductor and having a high

cm/s), which allows to obtain

/V.s) compared to the other polytypes.

4H), the cubic one has the highest saturated drift velocity (2.5 x 107

SiC has also the highest electron mobility (≈1000 cm2

is not as effective as the chlorine addition.

14 Advanced Silicon Carbide Devices and Processing

doping is usually carried out with nitrogen.

with the Cl/Si ratio [45].

*2.2.1.2. Growth of 3C-SiC films*

The feature that most determines the success of the applied research on cubic SiC is the possibility of epitaxial growth on silicon, which also has a cubic lattice, but with different constant (≈20% lattice mismatch) [49]. Cubic SiC may also be heteroepitaxially grown on 6H-SiC [50] and on TiC [51]. In addition to that, the bulk SiC contains screw dislocations that can propagate into the epitaxial layer, as in the case of 4H-SiC [52], while it is possible to find nearly defect-free silicon wafers. The availability of silicon wafers with diameter up to 17.7 inches compared to the smaller diameters of commercially available SiC, together with the extreme difficulties to obtain single crystal, large area bulk 3C-SiC crystals, pushed toward silicon the choice for the preferred substrate for 3C-SiC epitaxy. Moreover, the lowering cost of silicon wafers, even for high quality substrates, may help to bring the benefits of SiC technology to consumer devices.

There are many technological advantages using SiC on Si, like the easy integration in silicon electronics, which is already extremely developed and almost ubiquitous. Silicon and silicon carbide have also the same native insulating oxide that might be exploited for the processing and fabrication of Si-SiC-based electronic devices.

The silicon lattice constant is 5.43 Å, while in 3C-SiC it is 4.36 Å, which results in a lattice mismatch of approximately 20% and it can lead to a highly defective epitaxial film, which can be detrimental for electronic devices. The substrate thickness is much higher than the epilayer in the first stages of the growth and this leads the strain to be positioned almost completely in the deposited layer. The effect is the presence of shear stresses in crystal planes that may cause defects formation when a critical thickness of the epilayer is reached. In addition to that, the different thermal expansion (≈8% difference between Si and SiC) fosters the formation of defects during the cooling stage after the growth [53]. A brief review on the defects generated in the SiC layer and strictly correlated to the heteroepitaxy on silicon such as misfit dislocations, twins, stacking faults, threading dislocations, antiphase (or inversion) domain boundaries (APBs on Si (100)), and double positioning boundaries (DPBs on Si (111)) is presented in the next section.

In order to try to reduce the effect of the different lattice parameters between Si and SiC, a carbonization process is often used in the first stages of the epitaxial synthesis. Flowing carbon precursors as propane, methane, or ethane at high temperature over the silicon substrate is a well-known technique [54] to create a thin layer of SiC on the surface of the silicon substrate. Since the SiC lattice parameter is lower than the one of Si, in many cases atoms with bigger size like germanium [55] are added during this process.

Frequently the terms "carbonization" and "buffer layer" are mixed up in literature, but in this work we will refer to carbonization as the process performed only with the carbon precursor turning the outer layers of the silicon substrate into silicon carbide. Other precursors may be added, but not the one for silicon, as it happens in the "buffer layer" process, as reported hereafter. Another technique to ensure the relaxation of elastic energy at the interface between the substrate and the epilayer and to help to stop the propagation of the defects generated at Si-SiC interface is the introduction of a buffer layer prior to the growth. This can be made of silicon and carbon or other materials with less difference in lattice parameters. Typically, the gradual matching between the substrate and final overlayer is ensured via a continuous composition gradient of the buffer layer. A common way to reduce the strain is to pattern the silicon substrate in order to grow SiC crystal with a finite size. The first material used and the most common one to manufacture the mask is silicon oxide [56, 57], but other materials like silicon nitride or aluminum nitride also proved to be effective [58].

The difference in lattice parameter between Si substrate and SiC epilayer causes an "island" growth mode in the very first stages and then may originate many defects in the epitaxial layer, the most common being misfit dislocations, stacking faults and antiphase boundaries.

Misfit dislocations are generated at the interface between the substrate and epilayer, in order to allow the minimization of the lattice strain. The misfit dislocation leaves dangling bonds at the interface and it may propagate as a threading dislocation in the epitaxial layer often causing high leakage currents in a Si/3C-SiC device. TEM images help in understanding the phenom‐ enon (see Figure 6 from [59]): five (111) SiC lattice planes match with four (111) silicon planes, which correspond to a 20% lattice mismatch. In the case of silicon carbide grown over silicon, the difference in the two thermal expansion coefficients contributes to create additional misfit dislocation during the cooling stage after the growth, in order to relieve the stress created at the interface between the two crystals. The voids are another typical defect at the SiC/Si interface that are formed due to outdiffusion of Si during the heating process. If the carboni‐ zation is not properly optimized and if a continuous, thick SiC layer is not formed after the low temperature carbonization, during the second heating up to the growth temperature Si outdiffusion from the substrate may occur, leaving voids of the dimension of some µm2 at the interface [60]. These defects may degrade the electrical properties in vertical devices, where current flows in the Si substrate. Also, the presence of voids may disturb the SiC lattice arrangement above them, thus increasing the concentration of extended defects.

A two-dimensional deviation of the position of the atoms from their corresponding lattice site is called generically "planar defect." The most common types found in heteroepitaxial silicon carbide are stacking faults (SF), twins, and antiphase boundaries (APB).

Stacking faults are an anomaly in the stacking sequence of the different layers (ABCABCABC for 3C, ABABAB for 2H,...) of the crystal. This can be also considered as a local occurrence of another polytype**.** The energy associated with this kind of defects is very low, if compared to other planar defects, because this does not affect the near neighbor bonding; therefore, it is very common to observe stacking faults in cubic silicon carbide along the stacking of {111} planes. It is appropriate to remember that there is almost the same interface spacing between hexagonal and cubic planes [61].

**Figure 6.** Lattice arrangements at the SiC/Si interface [59]

Frequently the terms "carbonization" and "buffer layer" are mixed up in literature, but in this work we will refer to carbonization as the process performed only with the carbon precursor turning the outer layers of the silicon substrate into silicon carbide. Other precursors may be added, but not the one for silicon, as it happens in the "buffer layer" process, as reported hereafter. Another technique to ensure the relaxation of elastic energy at the interface between the substrate and the epilayer and to help to stop the propagation of the defects generated at Si-SiC interface is the introduction of a buffer layer prior to the growth. This can be made of silicon and carbon or other materials with less difference in lattice parameters. Typically, the gradual matching between the substrate and final overlayer is ensured via a continuous composition gradient of the buffer layer. A common way to reduce the strain is to pattern the silicon substrate in order to grow SiC crystal with a finite size. The first material used and the most common one to manufacture the mask is silicon oxide [56, 57], but other materials like

The difference in lattice parameter between Si substrate and SiC epilayer causes an "island" growth mode in the very first stages and then may originate many defects in the epitaxial layer, the most common being misfit dislocations, stacking faults and antiphase boundaries.

Misfit dislocations are generated at the interface between the substrate and epilayer, in order to allow the minimization of the lattice strain. The misfit dislocation leaves dangling bonds at the interface and it may propagate as a threading dislocation in the epitaxial layer often causing high leakage currents in a Si/3C-SiC device. TEM images help in understanding the phenom‐ enon (see Figure 6 from [59]): five (111) SiC lattice planes match with four (111) silicon planes, which correspond to a 20% lattice mismatch. In the case of silicon carbide grown over silicon, the difference in the two thermal expansion coefficients contributes to create additional misfit dislocation during the cooling stage after the growth, in order to relieve the stress created at the interface between the two crystals. The voids are another typical defect at the SiC/Si interface that are formed due to outdiffusion of Si during the heating process. If the carboni‐ zation is not properly optimized and if a continuous, thick SiC layer is not formed after the low temperature carbonization, during the second heating up to the growth temperature Si outdiffusion from the substrate may occur, leaving voids of the dimension of some µm2

interface [60]. These defects may degrade the electrical properties in vertical devices, where current flows in the Si substrate. Also, the presence of voids may disturb the SiC lattice

A two-dimensional deviation of the position of the atoms from their corresponding lattice site is called generically "planar defect." The most common types found in heteroepitaxial silicon

Stacking faults are an anomaly in the stacking sequence of the different layers (ABCABCABC for 3C, ABABAB for 2H,...) of the crystal. This can be also considered as a local occurrence of another polytype**.** The energy associated with this kind of defects is very low, if compared to other planar defects, because this does not affect the near neighbor bonding; therefore, it is very common to observe stacking faults in cubic silicon carbide along the stacking of {111} planes. It is appropriate to remember that there is almost the same interface spacing between

arrangement above them, thus increasing the concentration of extended defects.

carbide are stacking faults (SF), twins, and antiphase boundaries (APB).

hexagonal and cubic planes [61].

at the

silicon nitride or aluminum nitride also proved to be effective [58].

16 Advanced Silicon Carbide Devices and Processing

A twin is a particular defect in the stacking sequence of the planes in which the sequence at the opposite side of the defect plane is mirror images of each other. For example, in the cubic polytype, where the stacking sequence is ABCABCABCABC..., a twin may occur like this: ABCABCBACBACBA. This corresponds to a change in the crystal orientation.

As said previously, the lattice mismatch between the substrate and the epilayer causes the growth of three-dimensional islands in the first stages of the synthesis process known as "island growth mode." The genesis of antiphase boundary domains (APB) is linked to the nonperfect planarity of the substrate. In addition to the initial roughness of the silicon, which todate can be significantly reduced, the carbonization process introduces many irregularities. During the island growth mode, islands generated in different sites of the substrate may be at different levels owing to the presence of surface steps on the substrate. During the growth and coalescence of the islands, a Si outer layer of an island may bond with a Si layer of another island, thus forming Si-Si bonds. The same phenomenon may occur with C layers of two different islands generating C-C bonds. These boundaries usually propagate along (111) planes, and when two boundaries with opposite orientation combine, they annihilate them‐ selves and the result is the disappearance of the island (and of the APB).

It is possible to generate double position boundaries (DPB) on SiC grown on a (111) surface. This kind of defect is the result of twins that start from the epilayer-substrate interface. The epilayer may orient with respect to the substrate in two ways that are crystallographically equivalent but are rotated 60° relative to each other. When two growth nuclei with different orientations coalesce, a DPB is formed.

#### *2.2.2. Epitaxial SiC quality*

Epitaxial 3C-, 4H-, and 6H-SiC have very different properties and characteristics, mainly because of the hetero or homo-epitaxial processes necessary for their deposition. The main issues affecting SiC material quality are due to the substrate used and the growth process. The quality of grown material can be measured mainly in terms of lattice perfection (e.g., from XRD measurements), point defects, extended defects, and residual strain. Usually, the presence of crystalline defects does not hinder the performances of MEMS devices or their capabilities to work in harsh environments.

Due to the ease of fabrication on Si substrate, the polytype of choice for the realization of SiC MEMS is still 3C, and in this case there are still more variables to be considered because this polytype can be deposited in different forms such as crystalline, polycrystalline, or amorphous. These lattice structures have different mechanical properties, such as Young's modulus, which may affect MEMS fabrication.

The mechanical properties of polycrystalline 3C-SiC depend on its characteristics such as preferred orientation, stoichiometry, grain size and shape, and defect. Polycrystalline SiC films have a lower Young's modulus with respect to single crystalline SiC [62], and amorphous films growth at lower temperatures may have even lower Young's modulus values [63]. The Young's modulus of high crystalline quality of 3C-SiC/Si was found to depend on thickness [64] ranging from 1.5x1011 to 3.75x1011 Pa for thickness between 2 and 3 µm. Considering that the epitaxial quality of SiC increases with thickness due to progressive annihilation of defects and lowering of (002) XRD peak FWHM, the increase in Young's modulus with thickness could be related to lattice quality and defect density. This is one of the most important characteristics to be considered when designing MEMS and still hinder the development of microfabrication. Different growth processes may lead to completely different microstructure properties due to the presence of different type and density of lattice defects and strain content.

In the case of most common MEMS devices, the main requirements of the material are related to mechanical strength and hardness. The presence of residual stress or stress gradients inside the epitaxial layer can also hinder the process of microfabrication in different ways. The stress, originating either from lattice and thermal mismatch in 3C-SiC/Si heteroepitaxy, may cause severe macroscopic bending of the substrate, and may make photolithographic processing impossible or very difficult. At the microscopic level, stress and stress gradients may bend the microstructures or introduce unwanted and unpredictable forces to the system that may alter the behavior of the device or change the predicted resonant frequencies. Different strategies may be adopted to minimize the strain content of 3C-SiC/Si, from the carbonization process optimization or to the deposition of special buffer layers to reduce the lattice mismatch strain [60]. However, the presence of thermal mismatch cannot be avoided and could be limited only by reducing the growth temperature.

Reducing the deposition temperature has a tremendous effect on 3C-SiC. High quality crystalline material, with XRD FWHM peak as low 200 arcsec, is usually grown at temperatures higher than 1250–1300°C, with temperatures in the range 1350–1400°C being most commonly used. Precursors of choice are silane and propane, in hot wall VPE reactors. Lowering the growth temperature usually means to significantly degrade the surface morphology and to increase the roughness. In order to maintain a high material quality even at lower deposition temperatures, several alternative precursors have been studied and plasma enhanced techni‐ ques have been used. Most of alternative precursors include a Si-C bond in the molecule, such as tetramethylsilane, methyltrichlorosilane, monomethylsilane, hexamethyldisilane, and have lower cracking temperature. However, since for standard MEMS processes the suitable surface termination or the high crystal quality are not mandatory requirements, a trade-off between process conditions and 3C-SiC characteristic may be found. Different deposition techniques such as chemical vapor deposition (CVD), plasma enhanced CVD or sputtering are normally used to deposit polycrystalline or amorphous 3C-SiC at low temperature. Doping of poly or amorphous remains an issue because grain boundaries inhibit dopant incorporation and carrier transport. Moreover, dopant species must crack at low temperature so normally NH3 (which is toxic) is normally used instead of N2.

Doping can also influence important properties like crystal quality and strain. The increased doping concentration results in a slightly decreased or increased lattice constant, because N substitute C in the SiC lattice and Al substitute Si for p-type doping. Doping affects thus not only the electrical properties but also the mechanical properties, such as elastic modulus and hardness, so that it can influence the resonance frequency of microstructures. Elastic modulus and hardness of the 3C-SiC thin film may decrease from 350–400 GPa to 150–200 GPa and from 35 GPa to 20 GPa, respectively, with an increase in the nitrogen concentration [65].

#### *2.2.3. Surface micromachining*

It is possible to generate double position boundaries (DPB) on SiC grown on a (111) surface. This kind of defect is the result of twins that start from the epilayer-substrate interface. The epilayer may orient with respect to the substrate in two ways that are crystallographically equivalent but are rotated 60° relative to each other. When two growth nuclei with different

Epitaxial 3C-, 4H-, and 6H-SiC have very different properties and characteristics, mainly because of the hetero or homo-epitaxial processes necessary for their deposition. The main issues affecting SiC material quality are due to the substrate used and the growth process. The quality of grown material can be measured mainly in terms of lattice perfection (e.g., from XRD measurements), point defects, extended defects, and residual strain. Usually, the presence of crystalline defects does not hinder the performances of MEMS devices or their capabilities

Due to the ease of fabrication on Si substrate, the polytype of choice for the realization of SiC MEMS is still 3C, and in this case there are still more variables to be considered because this polytype can be deposited in different forms such as crystalline, polycrystalline, or amorphous. These lattice structures have different mechanical properties, such as Young's modulus, which

The mechanical properties of polycrystalline 3C-SiC depend on its characteristics such as preferred orientation, stoichiometry, grain size and shape, and defect. Polycrystalline SiC films have a lower Young's modulus with respect to single crystalline SiC [62], and amorphous films growth at lower temperatures may have even lower Young's modulus values [63]. The Young's modulus of high crystalline quality of 3C-SiC/Si was found to depend on thickness [64] ranging from 1.5x1011 to 3.75x1011 Pa for thickness between 2 and 3 µm. Considering that the epitaxial quality of SiC increases with thickness due to progressive annihilation of defects and lowering of (002) XRD peak FWHM, the increase in Young's modulus with thickness could be related to lattice quality and defect density. This is one of the most important characteristics to be considered when designing MEMS and still hinder the development of microfabrication. Different growth processes may lead to completely different microstructure properties due to

In the case of most common MEMS devices, the main requirements of the material are related to mechanical strength and hardness. The presence of residual stress or stress gradients inside the epitaxial layer can also hinder the process of microfabrication in different ways. The stress, originating either from lattice and thermal mismatch in 3C-SiC/Si heteroepitaxy, may cause severe macroscopic bending of the substrate, and may make photolithographic processing impossible or very difficult. At the microscopic level, stress and stress gradients may bend the microstructures or introduce unwanted and unpredictable forces to the system that may alter the behavior of the device or change the predicted resonant frequencies. Different strategies may be adopted to minimize the strain content of 3C-SiC/Si, from the carbonization process optimization or to the deposition of special buffer layers to reduce the lattice mismatch strain

the presence of different type and density of lattice defects and strain content.

orientations coalesce, a DPB is formed.

18 Advanced Silicon Carbide Devices and Processing

*2.2.2. Epitaxial SiC quality*

to work in harsh environments.

may affect MEMS fabrication.

As it was discussed previously, SiC MEMS has a tremendous potential for the realization of devices operating in harsh, biological environments and high temperatures, exceeding the capabilities of current silicon technology. The polytype of choice for the realization of SiC MEMS is still 3C, either polycrystalline or heteroepitaxial deposited on Si, SOI, or on a sacrificial layer such as SiO2 or poly-Si. Its main limitations are still due to the low material quality (low crystallinity, high concentration of lattice defects) and the high amount of residual strain due to the heteroepitaxy. However, advances in 3C-SiC epitaxial techniques and the possibility to use well-developed silicon wet-etch techniques to realize SiC MEMS provided a convenient way to fabricate even complex devices. Suspended 3C-SiC structures are released by surface machining using both the wet and dry etching process.

Microfabrication technology on 4H-SiC is much more complicated than the 3C-SiC/Si system because of the lack of a wet etchant for 4H-SiC: conventional wet chemical etching of SiC is not possible at a practical temperature and with suitable etch rates. 4H or 6H-SiC MEMS were fabricated by expensive and complex techniques such as wafer bonding or smart-cut technique [66], anisotropic electron cyclotron resonance (ECR) etching technique [67], or bulk microma‐ chining [68] from the backside of the wafer. However, the possibility to combine active electronics and microsystems in a single device that could withstand extreme environments and high power is very promising.

#### *2.2.3.1. Processing techniques*

SiC can be processed with many of the techniques used also for silicon, while, owing to its mechanical hardness and chemical inertness, not all of the silicon etching techniques can be used for silicon carbide.

#### **Oxidation**

It is possible to grow stable thermal oxide layers on all SiC polytypes, as it is commonly done for silicon, but the oxidation rate is much lower. Owing its chemical stability SiC is less likely than silicon to dissociate and react with oxygen to form silicon oxide. Furthermore, CO, one of the reaction products, must diffuse out of the oxide layer for the reaction to proceed. Even if the presence of hydrogen or water vapor increases the oxidation rate, frequently, a thick oxide is required for MEMS fabrication; for this reason the deposition of polycrystalline silicon and following oxidation [69] or the direct deposition of silicon oxide is generally chosen.

#### **Metallization**

The deposition of different metallic species to achieve good ohmic or rectifying contacts on SiC has been widely investigated. Depending on the deposition parameters, but mostly on the annealing temperature, different contact behavior can be obtained ceteris paribus.

Annealed Ni for n-type SiC or Al for p-type have been extensively used to obtain ohmic contacts with low contact resistivity [70, 71], while Au [71], Ti [71], Pt [72], or Al [73] have been studied to obtain Schottky barriers. Nevertheless, using some metal that prevents the exploi‐ tation of silicon technology, as gold, the metallization should be performed outside of IC fabrication facilities because gold shows electromigration at relatively low temperatures.

#### **SiC-coated MEMS**

One can exploit the well-developed state-of-the art of silicon micromachining techniques to obtain devices with complicated design using well-known silicon etchings and covering them with monocrystalline or polycrystalline silicon carbide after the MEMS is released. It has been shown that depositing a thin SiC film over a silicon MEMS improves significantly the wear resistance, decreases the static friction, thus enhancing the device lifetime [74]. The erosion resistance typical of silicon carbide is exploited for SiC-coated MEMS operating in chemically harsh environments [75]. In prospect, the direction of MEMS development will be toward an additional size reduction. For this reason, another feature that is gathering interest is the reduction of adhesion of SiC-coated MEMS [75] thanks to the reduction of surface forces owing probably to topographical surface properties and slower oxidation rates.

#### **SiC on insulator substrates**

fabricated by expensive and complex techniques such as wafer bonding or smart-cut technique [66], anisotropic electron cyclotron resonance (ECR) etching technique [67], or bulk microma‐ chining [68] from the backside of the wafer. However, the possibility to combine active electronics and microsystems in a single device that could withstand extreme environments

SiC can be processed with many of the techniques used also for silicon, while, owing to its mechanical hardness and chemical inertness, not all of the silicon etching techniques can be

It is possible to grow stable thermal oxide layers on all SiC polytypes, as it is commonly done for silicon, but the oxidation rate is much lower. Owing its chemical stability SiC is less likely than silicon to dissociate and react with oxygen to form silicon oxide. Furthermore, CO, one of the reaction products, must diffuse out of the oxide layer for the reaction to proceed. Even if the presence of hydrogen or water vapor increases the oxidation rate, frequently, a thick oxide is required for MEMS fabrication; for this reason the deposition of polycrystalline silicon and following oxidation [69] or the direct deposition of silicon oxide is generally chosen.

The deposition of different metallic species to achieve good ohmic or rectifying contacts on SiC has been widely investigated. Depending on the deposition parameters, but mostly on the

Annealed Ni for n-type SiC or Al for p-type have been extensively used to obtain ohmic contacts with low contact resistivity [70, 71], while Au [71], Ti [71], Pt [72], or Al [73] have been studied to obtain Schottky barriers. Nevertheless, using some metal that prevents the exploi‐ tation of silicon technology, as gold, the metallization should be performed outside of IC fabrication facilities because gold shows electromigration at relatively low temperatures.

One can exploit the well-developed state-of-the art of silicon micromachining techniques to obtain devices with complicated design using well-known silicon etchings and covering them with monocrystalline or polycrystalline silicon carbide after the MEMS is released. It has been shown that depositing a thin SiC film over a silicon MEMS improves significantly the wear resistance, decreases the static friction, thus enhancing the device lifetime [74]. The erosion resistance typical of silicon carbide is exploited for SiC-coated MEMS operating in chemically harsh environments [75]. In prospect, the direction of MEMS development will be toward an additional size reduction. For this reason, another feature that is gathering interest is the reduction of adhesion of SiC-coated MEMS [75] thanks to the reduction of surface forces owing

probably to topographical surface properties and slower oxidation rates.

annealing temperature, different contact behavior can be obtained ceteris paribus.

and high power is very promising.

20 Advanced Silicon Carbide Devices and Processing

*2.2.3.1. Processing techniques*

used for silicon carbide.

**Oxidation**

**Metallization**

**SiC-coated MEMS**

There is a great interest in obtaining SiC-on-insulator (SiCOI) substrates for micromachining both for obtaining electrical insulation of the SiC layer from substrate and to use oxide as a sacrificial layer or etch stop.

Silicon-on-insulator (SOI) substrates are obtained by ion implantation of O into the subsurface region of Si wafers, or, more frequently, bonding two silicon wafers covered by oxide. The first attempts to achieve a 3C-SiC layer over silicon oxide starting from a SOI were reported by Reichert et al. [76]. This method has some challenges: the buried oxide quality must be high to withstand the elevated temperatures needed for growing monocrystalline SiC (typically high T, near silicon melting point, 1414°C, ensure better quality epitaxial SiC, but for MEMS a lower crystalline quality may be acceptable). When silicon oxide reaches high temperatures, it undergoes glass transitions [76] and starts to degrade leaving a holey structure (outdiffusion of oxygen [76]) and worsening the electrical characteristics. Another important challenge is the complete conversion of the silicon overlayer into silicon carbide, if not, an undesirable 3C-SiC-on-Si-on-SiO structure is obtained. The carbonization step, as explained in the epitaxial growth part of this chapter, may help in obtaining that, but the method is limited because the diffusion process can reach a limited thickness (around 200 nm in the Si layer). Finely tuning the growth parameters, the production of SiCOI without significant degradation of the buried layers was demonstrated [77].

The "smart cut" process was already developed for obtaining SOI [78, 79]. The process starts with two oxidized silicon substrates, called handle wafer and implant wafer. Hydrogen ions are implanted into the implant wafer under the oxide layer and buried in the silicon bulk at a low depth. After the bonding of the two wafers, an annealing is performed and the implanted hydrogen forms a void layer inside the silicon. After that it is possible to break the implant wafer along these voids leaving the thin silicon layer still bonded to the handle wafer. The same process was successfully used using 6H-SiC substrates with 1-µm-thick deposited oxide layer as implant wafer and 6H-SiC, polycrystalline SiC, and Si layers as handle wafer [77] thus obtaining SiCOI.

As for SOI, wafer bonding is also used to obtain SiCOI [77]; in this case the handle wafer is thermally oxidized silicon. A film of cubic silicon carbide is epitaxially grown on a silicon wafer, and silicon oxide is deposited on this SiC layer. The two wafer oxide surfaces are treated and bonded together, then the handle wafer is protected and the silicon is removed from the second wafer generally using wet etching techniques. The result is a 3C-SiC-on-insulator-onsilicon structure. In literature it is possible to find other wafer bonding processes to obtain SiCOI, such the polysilicon-polysilicon bonding technique [80].

#### **3. A brief overview of the most common SiC microsystem devices**

Silicon carbide exhibits piezoresistive and piezoelectric properties as well as superior ther‐ momechanical properties at higher temperatures (>300° C) [81]. Thus, there is a growing interest in its use as an electromechanical material to replace the silicon in a variety of potential harsh environment applications. Microsystems have become an important direction for SiC technology development. Currently, SiC is the wide bandgap semiconductor material with most potential for MEMS sensors and actuators.

The resonators are one of the most investigated SiC MEMS. SiC resonant structures can present much higher resonant frequencies compared to the same dimensioned Si or GaAs structures due to its high Young's modulus and the relatively low mass density [82]. SiC MEMS resona‐ tors have been fabricated with higher power handling capabilities and operating frequencies, compared to those of similar polysilicon-based resonators [81]. Two types of SiC-based resonators have been reported, which use: (i) SiC grown on Si (or SOI) substrates and (ii) homoepitaxial layer grown on single-crystalline 4H- or 6H-SiC substrates.

SiC resonators can be easily fabricated on Si substrates using surface micromachining fabri‐ cation technology. This fabrication process is attractive because of integration compatibility with CMOS processes, low-cost film deposition, and minimal compromises between the electrical and mechanical performances of the fabricated structures [81]. Wang et al. reported the fabrication of MEMS resonators based on SiC thin film deposited by low temperature PECVD [82]. These resonators were tested and showed a good performance for harsh envi‐ ronment, such as, high temperature, erosion, and high pressure. The use of mono- and polycrystalline 3C-SiC grown on Si wafers by CVD in resonators able to work at high frequencies with high quality factors has also been reported. The structure of the 3C-SiC resonator is schematized in Figure 7(a) [83].

Regarding the resonant structures made of homoepitaxial layers grown on single-crystalline 4H- or 6H-SiC substrates, their fabrication process is more difficult than that of SiC/Si MEMS. However, high resonant frequency makes 4H-SiC MEMS very attractive for high-sensitivity sensors. Adachi et al. compared the resonance characteristics of 4H-SiC cantilevers on 4H-SiC substrate with the same dimensions of 3C-SiC cantilevers fabricated on Si substrate. It was observed that the resonant frequency of the 4H-SiC cantilevers was 10 times that of 3C-SiC cantilevers [84]. The 4H-SiC cantilevers were fabricated by doping-type selective electrochem‐ ical etching of 4H-SiC and their structure is shown in Figure 7(b).

Recently, Yang et al. reported high frequency torsional resonators based on a single-crystal 6H-SiC thin layer on top of a SiO2-on-Si wafer by using a "smart-cut" process. 6H-SiC smart technology is an alternative process to micromachining of 6H-SiC, which is not only very time consuming but also requires deposited metal masks and still lacks precision when thin films and small dimensions are required for devices [85].

Another important type of SiC MEMS is the piezoresistive sensors for harsh environment applications. In the 1990s, the first piezoresistive pressure sensors developed on 6H-SiC substrates were reported for applications up to 500ºC [86, 87]. These sensors were batchmicrofabricated using a combination of photo and dark etching methods to create the dia‐ phragm. In 2004, Ned et al. reported the fabrication of 6H-SiC pressure sensors, with optimized sensing diaphragms containing "bossed" areas, using a combination of deep reactive ion etching (DRIE) and electrochemical etching [88]. The reports on 4H-SiC pressure sensors are

**Figure 7.** (a) 3C-SiC resonator structure [83] and (b) 4H-SiC micro cantilever [84]

more recent than those of 6H-SiC. In 2011, Akiyama et al. introduced a new approach for the fabrication of 4H-SiC bulk sensors using a mechanical milling (drilling) to form the membrane of the sensor. The detailed milling process done by Tecnisco (Japan) was not disclosed [89]. Earlier this year, Okojie et al. investigated 4H-SiC piezoresistive pressure sensors when operated up to 800ºC. This is the first experimental work published under piezoresistance versus temperature for 4H-SiC [90].

On the other hand, the piezoresistive properties of 3C-SiC and a-SiC films and the influence of the temperature on them have been reported by different authors as reviewed in [91]. The first studies were focused on polycrystalline 3C-SiC films. However, recent publications have demonstrated that a p-type single crystalline 3C-SiC film is a valuable material for MEMS sensors [92, 93].

The potential of SiC for gas sensors in a range of environments has also been reported [94, 95]. These sensors exhibit a simple sensing element based on metal-insulator-semiconductor (MIS) structure, typically a capacitor or a Schottky diode. The use of an insulating layer separating the metal from the SiC allows these devices to operate at temperatures in excess of 900°C [94].

#### **4. Summary**

interest in its use as an electromechanical material to replace the silicon in a variety of potential harsh environment applications. Microsystems have become an important direction for SiC technology development. Currently, SiC is the wide bandgap semiconductor material with

The resonators are one of the most investigated SiC MEMS. SiC resonant structures can present much higher resonant frequencies compared to the same dimensioned Si or GaAs structures due to its high Young's modulus and the relatively low mass density [82]. SiC MEMS resona‐ tors have been fabricated with higher power handling capabilities and operating frequencies, compared to those of similar polysilicon-based resonators [81]. Two types of SiC-based resonators have been reported, which use: (i) SiC grown on Si (or SOI) substrates and (ii)

SiC resonators can be easily fabricated on Si substrates using surface micromachining fabri‐ cation technology. This fabrication process is attractive because of integration compatibility with CMOS processes, low-cost film deposition, and minimal compromises between the electrical and mechanical performances of the fabricated structures [81]. Wang et al. reported the fabrication of MEMS resonators based on SiC thin film deposited by low temperature PECVD [82]. These resonators were tested and showed a good performance for harsh envi‐ ronment, such as, high temperature, erosion, and high pressure. The use of mono- and polycrystalline 3C-SiC grown on Si wafers by CVD in resonators able to work at high frequencies with high quality factors has also been reported. The structure of the 3C-SiC resonator is

Regarding the resonant structures made of homoepitaxial layers grown on single-crystalline 4H- or 6H-SiC substrates, their fabrication process is more difficult than that of SiC/Si MEMS. However, high resonant frequency makes 4H-SiC MEMS very attractive for high-sensitivity sensors. Adachi et al. compared the resonance characteristics of 4H-SiC cantilevers on 4H-SiC substrate with the same dimensions of 3C-SiC cantilevers fabricated on Si substrate. It was observed that the resonant frequency of the 4H-SiC cantilevers was 10 times that of 3C-SiC cantilevers [84]. The 4H-SiC cantilevers were fabricated by doping-type selective electrochem‐

Recently, Yang et al. reported high frequency torsional resonators based on a single-crystal 6H-SiC thin layer on top of a SiO2-on-Si wafer by using a "smart-cut" process. 6H-SiC smart technology is an alternative process to micromachining of 6H-SiC, which is not only very time consuming but also requires deposited metal masks and still lacks precision when thin films

Another important type of SiC MEMS is the piezoresistive sensors for harsh environment applications. In the 1990s, the first piezoresistive pressure sensors developed on 6H-SiC substrates were reported for applications up to 500ºC [86, 87]. These sensors were batchmicrofabricated using a combination of photo and dark etching methods to create the dia‐ phragm. In 2004, Ned et al. reported the fabrication of 6H-SiC pressure sensors, with optimized sensing diaphragms containing "bossed" areas, using a combination of deep reactive ion etching (DRIE) and electrochemical etching [88]. The reports on 4H-SiC pressure sensors are

homoepitaxial layer grown on single-crystalline 4H- or 6H-SiC substrates.

ical etching of 4H-SiC and their structure is shown in Figure 7(b).

and small dimensions are required for devices [85].

most potential for MEMS sensors and actuators.

22 Advanced Silicon Carbide Devices and Processing

schematized in Figure 7(a) [83].

The wide bandgap semiconductor technologies are the key to enable the development of MEMS devices for harsh environment applications. Among them, SiC technology is the most mature from the viewpoint of material quality, manufacturing, and device performance. High quality single crystal wafers are commercially available; wafer size and substrate qualities are increasing whereas wafer cost is decreasing. In the same way, thin film growth techniques have been optimized to accurately synthesize SiC with the necessary properties for its device applications such as material composition, crystal structure, suitable electrical conductivity, morphology, and mechanical characteristics. Despite these advancements in the manufactur‐ ing of SiC wafers, thick films, and thin films, there are still processing challenges especially related to doping and micromachining. SiC bulk etching techniques have been developed seeking high throughput to realize patterned, high-aspect ratio features, such as preservation of sidewall smoothness and etching profile at high etch rates, and high selectivity. In parallel, the progresses on the growth of 3C-SiC on silicon substrates and in surface micromachining techniques have enabled the fabrication of interesting MEMS devices.

#### **Acknowledgements**

The author M. A. Fraga acknowledges the FAPESP (Process 2014/18139-8) and CNPq (Process 442133/2014-6) for financial support.

#### **Author details**

Mariana Amorim Fraga1\*, Matteo Bosi2 and Marco Negri2

\*Address all correspondence to: mafraga@ita.br

1 National Institute for Space Research, Associated Laboratory of Sensors and Materials, Brazil

2 IMEM-CNR Institute, Italy

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The author M. A. Fraga acknowledges the FAPESP (Process 2014/18139-8) and CNPq (Process

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#### **Chapter 2**

## **3C-SiC — From Electronic to MEMS Devices**

Jean-François Michaud, Marc Portail and Daniel Alquier

Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/61020

#### **Abstract**

Since decades, silicon carbide (SiC) has been avowed as an interesting material for highpower and high-temperature applications because of its significant properties including its wide bandgap energy and high temperature stability. SiC is also professed as an ideal candidate for microsystem applications due to its excellent mechanical properties and chemical inertia, making it suitable for harsh environments. Among the 250 different SiC polytypes, only 4H, 6H and 3C-SiC are commercially available. The cubic structure, 3C-SiC, is the only one that can be grown on cheap silicon substrates. Hence, 3C-SiC is more interesting than any other polytype for reducing fabrication costs and increasing wafer diameter. This huge property has been evidenced for more than 30 years using chemical vapor deposition. Despite this key achievement and the growing interest for silicon carbide, no 3C-SiC-based devices can be found on the market whereas 4H-SiCbased devices are more and more largely commercialized. Even so, important headways have been reached for electrical and microelectromechanical systems (MEMS) applica‐ tions. Therefore, the purpose of this chapter is to address concerns related to electronic applications and MEMS fabrication of 3C-SiC-based devices, trying to give a broad overview on specific issues and challenging solutions.

**Keywords:** Doping, Defects, Implantation, Etching, MEMS

#### **1. Introduction**

Silicon carbide (SiC) is a material presenting different crystalline structures called polytypes. Indeed, more than 250 structures are referenced in the literature [1]. Each polytype is charac‐ terized by its own atomic stacking sequence, which can result in cubic, hexagonal or rhombo‐

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hedral structures, but each structure consists of 50% carbon atoms bonded with 50% silicon atoms. However, among the different polytypes, only two hexagonal structures (4H-SiC and 6H-SiC) and the cubic one (3C-SiC) are commercially available. As the properties are closely related to the crystalline arrangement, they differ from one polytype to another but the tendencies are similar. Silicon carbide presents a high breakdown field (2-4 MV/cm) and a high energy bandgap (2.3-3.2 eV), largely higher than for silicon. As a result, silicon carbide is commonly referred to as a wide bandgap material. The combination of these two properties is a great advantage for the design of electrical devices presenting a low on-state resistance and a low leakage current. In addition, SiC also presents a high saturated electron velocity, which is a crucial parameter for high-frequency applications. Moreover, the silicon carbide thermal conductivity is around three times higher than that observed for silicon. Then, SiC is a material presenting high thermal capability. This property can be very helpful for devices subjected to high temperature and compares favorably to challenging wide bandgap materials such as gallium nitride. Furthermore, SiC is also known as a biocompatible material [2], which is deeply valued for biologic applications [3], and is resistant to high-radiative environments [4]. Within this frame, the cubic polytype of SiC (3C-SiC) is the only one that can be grown on a host substrate with the huge opportunity to grow only the silicon carbide thickness required for the targeted application. The possible growth on silicon substrate has long remained a real advantage in terms of scalability regarding the reduced diameter of commercially available hexagonal SiC. To date, the growth of 3C-SiC on silicon has been demonstrated on 150 mm Si wafers [5]. Since the pioneering works of Nishino *et al.* in the early 1980s, who demonstrated an efficient method to grow 3C-SiC on silicon [6], a large amount of data concerning growth mechanisms has been established by many groups and paved the route for the large dissem‐ ination of this material [6-11]. However, despite the fact that the realization of 3C-SiC/Si epilayers appears very promising for taking benefit of outstanding properties of SiC at a low cost, the low crystalline quality of these epilayers in comparison to what is obtained on hexagonal bulk SiC wafers have hampered their use for device fabrication. Nevertheless, the positive trade-off between the cost advantage and a real opportunity for scalability versus reduced quality compared to hexagonal polytypes maintains interest in 3C-SiC for diverse applications.

To summarize, silicon carbide is a promising material with high potential for designing high-power and high-temperature electrical devices, as clearly described in some review papers [12-15].

#### **2. 3C-SiC for electronic applications**

#### **2.1. Doping**

#### *2.1.1. In situ doping*

As explained previously, the great advantage of the cubic polytype is the possibility to grow 3C-SiC films on cheap silicon substrates. Then, in order to consider the elaboration of any 3C-SiC-based device, it is necessary to master its growth. For more than 30 years, this theme has been deeply investigated and will not be detailed here. For more detailed information, one could consult some papers as the idea of this contribution is rather to discuss the important progresses accomplished for electrical applications [16, 17].

hedral structures, but each structure consists of 50% carbon atoms bonded with 50% silicon atoms. However, among the different polytypes, only two hexagonal structures (4H-SiC and 6H-SiC) and the cubic one (3C-SiC) are commercially available. As the properties are closely related to the crystalline arrangement, they differ from one polytype to another but the tendencies are similar. Silicon carbide presents a high breakdown field (2-4 MV/cm) and a high energy bandgap (2.3-3.2 eV), largely higher than for silicon. As a result, silicon carbide is commonly referred to as a wide bandgap material. The combination of these two properties is a great advantage for the design of electrical devices presenting a low on-state resistance and a low leakage current. In addition, SiC also presents a high saturated electron velocity, which is a crucial parameter for high-frequency applications. Moreover, the silicon carbide thermal conductivity is around three times higher than that observed for silicon. Then, SiC is a material presenting high thermal capability. This property can be very helpful for devices subjected to high temperature and compares favorably to challenging wide bandgap materials such as gallium nitride. Furthermore, SiC is also known as a biocompatible material [2], which is deeply valued for biologic applications [3], and is resistant to high-radiative environments [4]. Within this frame, the cubic polytype of SiC (3C-SiC) is the only one that can be grown on a host substrate with the huge opportunity to grow only the silicon carbide thickness required for the targeted application. The possible growth on silicon substrate has long remained a real advantage in terms of scalability regarding the reduced diameter of commercially available hexagonal SiC. To date, the growth of 3C-SiC on silicon has been demonstrated on 150 mm Si wafers [5]. Since the pioneering works of Nishino *et al.* in the early 1980s, who demonstrated an efficient method to grow 3C-SiC on silicon [6], a large amount of data concerning growth mechanisms has been established by many groups and paved the route for the large dissem‐ ination of this material [6-11]. However, despite the fact that the realization of 3C-SiC/Si epilayers appears very promising for taking benefit of outstanding properties of SiC at a low cost, the low crystalline quality of these epilayers in comparison to what is obtained on hexagonal bulk SiC wafers have hampered their use for device fabrication. Nevertheless, the positive trade-off between the cost advantage and a real opportunity for scalability versus reduced quality compared to hexagonal polytypes maintains interest in 3C-SiC for diverse

To summarize, silicon carbide is a promising material with high potential for designing high-power and high-temperature electrical devices, as clearly described in some review

As explained previously, the great advantage of the cubic polytype is the possibility to grow 3C-SiC films on cheap silicon substrates. Then, in order to consider the elaboration of any 3C-SiC-based device, it is necessary to master its growth. For more than 30 years,

applications.

papers [12-15].

**2.1. Doping**

*2.1.1. In situ doping*

**2. 3C-SiC for electronic applications**

34 Advanced Silicon Carbide Devices and Processing

In order to consider the elaboration of electrical devices, it is necessary to master some technological steps. Among them, doping is probably the most important. Doped layers can be obtained directly during the epitaxial growth of silicon or silicon carbide films. This *in situ* doping presents a major advantage for providing, in a single process, a finalized hetero‐ structure.

The doping-related issues of SiC epilayers have been addressed in the literature in the same time as growth developments because doping incorporation can have a strong impact on growth conditions. For SiC, different dopants can be used, such as nitrogen or phosphorus for n-type doping and boron or aluminum for p-type doping. The choice of dopant is motivated by their low dopant ionization energy. For nitrogen and phosphorus, these energies are around 50 meV, which is in the same order of magnitude as the one observed for donor dopants classically used with silicon, phosphorus and arsenic. However, p-type doping is much more complicated in SiC in comparison with Si. Usually, silicon p-type doping is obtained using boron, which presents an ionization energy around 45 meV. This value is around 6 times lower than the shallowest acceptor dopants observed in SiC using aluminum. As a consequence, SiC p-type doping is a permanent challenge.

In case of nitrogen doping, a quite largely accepted scheme exists and is relevant for many cases (different SiC polytype, SiC polarity (for hexagonal polytypes), or SiC crystalline orientation). It is well known that nitrogen incorporates SiC by substituting with carbon atoms, leading to a N/C site competition effect [18]. A direct consequence is the possibility to tune, to a large extent, the dopant concentration. It can be noticed that most of the published works deal with the incorporation of nitrogen within hexagonal SiC polytypes. For them, the SiC polarity is shown to play an important role [19, 20]. Nitrogen is preferentially incorporated onto a carbon face and can be reduced by increasing the C/Si ratio regarding the site compe‐ tition effect. In case of the 3C-SiC epilayer, the incorporation of dopant has been less discussed. The presence of extended defects within the epilayer makes the interpretation in the sole term of site competition effect more complicated but some similarities with hexagonal polytypes exist. Regarding the impact of crystalline orientation of the epilayer, it has been shown that both (100) and (111) oriented epilayers present a similar level of nitrogen incorporation, but a different incorporation behavior when C/Si ratio is modified during growth. If (100) oriented epilayers do not present a modification of the incorporation with a C/Si increase, this one is reduced on (111) epilayers with C/Si increase, highlighting a possible influence of the reactor environment in which growth is done as well as a different surface atomic structure between the two crystalline orientations. It is also of interest to point out that doping level acts on the residual stress within 3C-SiC/Si epilayer. Compressive to tensile residual strain states have been reported in accordance to the nitrogen concentration and must be considered when these epilayers are expected to be used for the design of MEMS where stress is an important parameter to take into account [21]. This highlights the special care we must take when considering doping issues in 3C-SiC. It is also important to mention that nitrogen doping does not imply any memory effect during the growth, allowing the formation of abrupt highly/low doped 3C-SiC heteroepilayers, relevant for the design of devices such as Schottky diodes. In addition, different mechanisms governing the aluminum doping remain a matter of debate. If it is expected that aluminum incorporates in place of silicon atoms, a large dispersion of the experimental results obtained by various groups attests either to some misunderstanding of the mechanism or highlights the influence of the specificity of each growth reactor [19, 22-24]. For instance, Forsberg *et al.* have shown that, regarding the specific attachment of one alumi‐ num atom to one carbon atom via a single bond, the dependence of aluminum incorporation differs from Si to C polarity for hexagonal polytypes. They also report on a constant incorpo‐ ration on C face and an increasing incorporation with C/Si increase [22]. Other groups have communicated their own results on the topic but often with more or less pronounced dissim‐ ilarities [19, 23, 24]. We can highlight that, in most cases, the role of uncontrolled flux of carbon in the reactor, due to graphite surfaces of the vessel, can have a nonnegligible impact on growth and could be partly responsible for the discrepancies reported in results. However, this parameter is inherent to a given growth reactor, making a direct comparison between different groups difficult. To our knowledge, very few groups have reported on Al incorporation into 3C-SiC epilayers [25]. A last point to mention is the fact that chemical precursors used for p doping induce a large memory effect in the growth chamber, which makes it difficult to realize abrupt p/n junctions in a single growth process. The addition of chloride-based gases has been recently proposed to circumvent this drawback and could be helpful for the realization of highquality bipolar devices [26]. Finally, it is important to mention that using this method, it is not possible to obtain dissimilar planar doping levels. To localize the doping regions, other methods are required.

#### *2.1.2. Implantation*

In silicon technology, localized doping can be achieved by means of ion implantation or diffusion processes. In contrast, in silicon carbide technology, due to the extremely low dopant diffusion, ion implantation is the only method available. In order to get n-type highly doped regions, both nitrogen (N) and phosphorus (P) implantations were studied in the literature [27-29].

By means of ion implantation, «impurities» can be selectively introduced into the silicon carbide layer at a thickness depending on the energy. Then, due to the lack of diffusion, obtaining a deep abrupt junction requires multiple-step implantation known as a «box-like» profile, as illustrated in Fig. 1.

The other significant implantation parameter is the dose as it induces the doping level of the implanted material. However, due to the collisions between incorporated ions and the silicon carbide crystal lattice, the implantation step leads to the generation of point and extended defects. In addition, the implanted species are classically in interstitial sites in the crystal lattice. As a consequence, the implanted ions cannot bond with the SiC atoms and thus they cannot participate in the electrical conduction. For both reasons, it is mandatory to provide energy to the targeted material, aiming to recover the crystal lattice (if possible) and to allow the implanted species to locally diffuse for occupying a substitutional site. This energy is provided

not imply any memory effect during the growth, allowing the formation of abrupt highly/low doped 3C-SiC heteroepilayers, relevant for the design of devices such as Schottky diodes. In addition, different mechanisms governing the aluminum doping remain a matter of debate. If it is expected that aluminum incorporates in place of silicon atoms, a large dispersion of the experimental results obtained by various groups attests either to some misunderstanding of the mechanism or highlights the influence of the specificity of each growth reactor [19, 22-24]. For instance, Forsberg *et al.* have shown that, regarding the specific attachment of one alumi‐ num atom to one carbon atom via a single bond, the dependence of aluminum incorporation differs from Si to C polarity for hexagonal polytypes. They also report on a constant incorpo‐ ration on C face and an increasing incorporation with C/Si increase [22]. Other groups have communicated their own results on the topic but often with more or less pronounced dissim‐ ilarities [19, 23, 24]. We can highlight that, in most cases, the role of uncontrolled flux of carbon in the reactor, due to graphite surfaces of the vessel, can have a nonnegligible impact on growth and could be partly responsible for the discrepancies reported in results. However, this parameter is inherent to a given growth reactor, making a direct comparison between different groups difficult. To our knowledge, very few groups have reported on Al incorporation into 3C-SiC epilayers [25]. A last point to mention is the fact that chemical precursors used for p doping induce a large memory effect in the growth chamber, which makes it difficult to realize abrupt p/n junctions in a single growth process. The addition of chloride-based gases has been recently proposed to circumvent this drawback and could be helpful for the realization of highquality bipolar devices [26]. Finally, it is important to mention that using this method, it is not possible to obtain dissimilar planar doping levels. To localize the doping regions, other

In silicon technology, localized doping can be achieved by means of ion implantation or diffusion processes. In contrast, in silicon carbide technology, due to the extremely low dopant diffusion, ion implantation is the only method available. In order to get n-type highly doped regions, both nitrogen (N) and phosphorus (P) implantations were studied in the literature

By means of ion implantation, «impurities» can be selectively introduced into the silicon carbide layer at a thickness depending on the energy. Then, due to the lack of diffusion, obtaining a deep abrupt junction requires multiple-step implantation known as a «box-like»

The other significant implantation parameter is the dose as it induces the doping level of the implanted material. However, due to the collisions between incorporated ions and the silicon carbide crystal lattice, the implantation step leads to the generation of point and extended defects. In addition, the implanted species are classically in interstitial sites in the crystal lattice. As a consequence, the implanted ions cannot bond with the SiC atoms and thus they cannot participate in the electrical conduction. For both reasons, it is mandatory to provide energy to the targeted material, aiming to recover the crystal lattice (if possible) and to allow the implanted species to locally diffuse for occupying a substitutional site. This energy is provided

methods are required.

36 Advanced Silicon Carbide Devices and Processing

profile, as illustrated in Fig. 1.

*2.1.2. Implantation*

[27-29].

**Figure 1.** Example of a multienergies implantation required obtaining a nitrogen box-like profile in 3C-SiC with a 5 × 1019 cm-3 concentration doping level, simulated by SRIM.

by means of an annealing. However, as 3C-SiC is grown on silicon substrates, the postimplantation annealing temperature is limited by the melting point of silicon (around 1410°C). Then, the feasibility of obtaining SiC on cheap Si substrates, which is a huge advantage to elaborate cost-effective devices, is also a «bonus» challenging parameter, in comparison with the 4H and 6H-SiC polytypes, which have to be considered. In fact, this parameter has to take into account the dose calculation as, in some cases, a high dose that is expected to lead to a high doping level could induce an amorphization of the implanted region. In such conditions, even a post-implantation annealing for several hours at 1350°C is not sufficient to entirely recover the crystal lattice [30]. To circumvent this problem, two tracks have been explored, essentially on 4H-SiC. The first one consists of performing the implantation in temperature [31, 32]. This leads to a notable constraint of the defects induced by the implantation step but it involves the use of «original» implanters. The other track was based on a statement considering the size of the species: in the periodic table referencing the chemical elements, nitrogen (N) and carbon are neighbors. The same observation can be made with phosphorus (P) and silicon. As a consequence, it is generally admit that after implantation, N atoms occupy preferentially the SiC carbon sites and P atoms occupy the silicon sites. Based on this statement, co-implan‐ tation of both species has been investigated in 4H-SiC and the results were promising [33, 34]. To our knowledge, such a study has never been experimentally completed in 3C-SiC except by our groups [35]. Actually, in 2011, we investigated 3C-SiC doping using nitrogen, phos‐ phorus implantations or their co-implantation. As expected from a physical point of view, crystal damages increased when increasing the atomic mass of the implanted species. How‐ ever, surprisingly, co-implantation did not demonstrate any interest in comparison with single nitrogen implantation. The defects induced by the higher mass of phosphorus were probably not entirely recovered consecutively to the post-implantation annealing.

Anyway, whatever the implantation conditions, defects are still induced. Then, this step is always associated with a post-implantation annealing. As previously mentioned, due to the

**Figure 2.** Energy band diagram for a metal and an n-type semiconductor, in the case *ϕ*m < *ϕ*s, before contact (a) and after contact (b).

presence of the silicon substrate, the temperature is limited to 1400°C, which is several hundred degrees below the temperature commonly used for post-implantation annealing on 4H-SiC substrates. However, even if the temperature is lower, a degradation of the surface can be observed according to the post-implantation annealing temperature. Due to that, as on 4H-SiC polytypes, samples can be annealed with a carbon-cap layer based on pyrolized photoresist [36-39]. This layer is then removed by annealing under oxygen, typically at 800°C. Using this method, it is possible to anneal 3C-SiC samples without any degradation of the surface [35], whereas such a degradation was observed with no capping layer [30]. Another method has been also investigated, using a silane overpressure during the annealing in order to prevent desorption of silicon atoms from the silicon carbide film [40, 41]. Nevertheless, the appropriate gas parameters are strictly related to the design of the furnace then it is very difficult to transpose them from a study to another one. Thus, to our knowledge, this method has been deserted to the detriment of the carbon cap layer process.

#### **2.2. Metal-semiconductor contacts**

The wide bandgap of 3C-SiC is a huge benefit for the achievement of electronic devices but the use of an electrical device requires the ability to control current flow, which is closely related to the electrical contacts. When a semiconductor material and a metal are brought into contact, an ohmic or a rectifying contact can be formed. For an ohmic contact, a linear and symmetric current-voltage characteristic is observed for negative and positive applied voltages, which allows current flow through the electrical device. The resistance for such a contact is negligible in comparison to the bulk one. In contrast, a rectifying contact allows the current to flow for only one voltage regime (negative or positive). The formation of an ohmic contact needs the injection of electrons from the metal to the semiconductor material. As a consequence, the metal work function *ϕ*m has to be lower than the one for the semiconductor material *ϕ*s, as illustrated in Fig. 2 for an n-type semiconductor.

The work function of most metals used in microelectronics field is about 4.5-5 eV, whereas the 3C-SiC electron affinity χ<sup>s</sup> is 4 eV. As a consequence, the condition *ϕ*s > *ϕ*<sup>m</sup> is difficult to attain and, hence, the contacts on 3C-SiC are «naturally» rectifying after the metal deposition. To circumvent this problem, the common method considered for wide bandgap material is to get a highly doped epilayer beneath the contact. According to the process flow, the high doping level can be obtained directly on *in situ* heavily doped material or on implanted layers but, in both cases, the common idea is to favor the current flow by tunneling through the thin barrier.

For a more detailed explanation, a complete description of the metal-semiconductor contacts can be found in the literature, for example, see [42].

#### **Contact annealing and specific contact resistance**

As explained previously, the contacts on highly doped material can present an ohmic behavior as-deposited. However, in most cases, the resistivity of the contact and therefore the specific contact resistance (SCR), is not appropriate to consider electrical applications. As a conse‐ quence, the metals are generally annealed posteriorly to the deposition. The aim of annealing is to induce a reaction between the metal and the semiconductor material. For example, titanium reacts with SiC in order to form silicide or carbide phases, presenting suitable electrical characteristics. The annealing itself can be very different from one study to another according to temperature, duration, atmosphere (argon, nitrogen, vacuum), heating ramp, and so on.

SCR values are widely used to characterize a contact. This parameter, which can be obtained by means of transfer length method (TLM) [43] or circular-TLM [44], is preferred over the contact resistance that is closely linked to the surface of the contact. Obtaining ohmic contacts on 3C-SiC with a SCR value as low as possible has been the holy grail of numerous studies for the past two decades [45, 46]. Indeed, it is commonly admitted that a specific contact resistance around 10-6 Ω cm2 is targeted for the elaboration of electrical devices. To obtain ohmic contacts on 3C-SiC, different metals have been considered: Al, Ni, Cr, Pt, Mo, Ti... as well as metal association: Ti/Al, Al/Au, Ti/Ni... essentially on n-type 3C-SiC materials. SCR is also commonly considered to compare different post-implantation annealing conditions, as it is an indirect gauge of the electrical activation.

Nowadays, thanks to the large efforts achieved on this concern, a contact with a 10-6 Ω cm2 SCR value can be «easily» obtained on 3C-SiC material with a high doping level (>1019 cm-3). However, until now, no 3C-SiC-based electrical devices can be found on the market. This suggests that the achievement of an ohmic contact, which has long been considered as the main issue to overcome before considering the elaboration of an electrical device, is not the only locking parameter. Actually, this absence can be explained by the high density of defects.

As explained previously, obtaining Schottky contacts is less challenging as the contacts are naturally rectifying on SiC. Metals usually involved for such contacts on 3C-SiC are gold, nickel, aluminum and platinum, in most cases without annealing. However, special care is needed concerning the temperature behavior of as-deposited contacts, as SiC-based electronic devices are generally considered capable of working in these temperatures.

#### **2.3. Role of defects**

presence of the silicon substrate, the temperature is limited to 1400°C, which is several hundred degrees below the temperature commonly used for post-implantation annealing on 4H-SiC substrates. However, even if the temperature is lower, a degradation of the surface can be observed according to the post-implantation annealing temperature. Due to that, as on 4H-SiC polytypes, samples can be annealed with a carbon-cap layer based on pyrolized photoresist [36-39]. This layer is then removed by annealing under oxygen, typically at 800°C. Using this method, it is possible to anneal 3C-SiC samples without any degradation of the surface [35], whereas such a degradation was observed with no capping layer [30]. Another method has been also investigated, using a silane overpressure during the annealing in order to prevent desorption of silicon atoms from the silicon carbide film [40, 41]. Nevertheless, the appropriate gas parameters are strictly related to the design of the furnace then it is very difficult to transpose them from a study to another one. Thus, to our knowledge, this method has been

**Figure 2.** Energy band diagram for a metal and an n-type semiconductor, in the case *ϕ*m < *ϕ*s, before contact (a) and

The wide bandgap of 3C-SiC is a huge benefit for the achievement of electronic devices but the use of an electrical device requires the ability to control current flow, which is closely related to the electrical contacts. When a semiconductor material and a metal are brought into contact, an ohmic or a rectifying contact can be formed. For an ohmic contact, a linear and symmetric current-voltage characteristic is observed for negative and positive applied voltages, which allows current flow through the electrical device. The resistance for such a contact is negligible in comparison to the bulk one. In contrast, a rectifying contact allows the current to flow for only one voltage regime (negative or positive). The formation of an ohmic contact needs the injection of electrons from the metal to the semiconductor material. As a consequence, the metal work function *ϕ*m has to be lower than the one for the semiconductor material *ϕ*s, as

The work function of most metals used in microelectronics field is about 4.5-5 eV, whereas the 3C-SiC electron affinity χ<sup>s</sup> is 4 eV. As a consequence, the condition *ϕ*s > *ϕ*<sup>m</sup> is difficult to attain and, hence, the contacts on 3C-SiC are «naturally» rectifying after the metal deposition. To circumvent this problem, the common method considered for wide bandgap material is to get

deserted to the detriment of the carbon cap layer process.

illustrated in Fig. 2 for an n-type semiconductor.

**2.2. Metal-semiconductor contacts**

38 Advanced Silicon Carbide Devices and Processing

after contact (b).

Since decades, many efforts have been done to improve the crystalline quality of 3C-SiC grown on Si substrate using CVD, but defects are still present. Indeed, intrinsic stress is created during the deposition process due to the lattice mismatch between 3C-SiC (4.36 Å) and Si (5.43 Å). In addition, thermoelastic stress is introduced during the post-deposition growth, due to the 8% difference in the thermal expansion coefficients of both materials. The resulting stress, which induces the formation of different planar or extended defects in 3C-SiC, is a major parameter leading to a noticeable degradation of the final crystalline quality of the epilayer. Furthermore, the specific nucleation stage adopted to grow SiC on Si, namely, the carburization stage, induces the formation of interfacial voids between SiC and Si, which could limit the interest of this system for the fabrication of devices that require interface abruptness or vertical transport. Finally, the residual stress state of the epilayer must be taken into consideration.

Hereafter, we will give a brief overview on the different kinds of defects encountered in 3C-SiC/Si epilayers grown by chemical vapor deposition. Many published works provide further details. We will also discuss the influence each defect can have on the potential development of electronic and mechanical devices.

**Figure 3.** (a) Plane view SEM image of 1-µm-thick 3C-SiC(100) epilayers; dark lines are antiphase boundaries; (b) crosssection TEM of 3C-SiC(100) epilayer where antiphase boundary (denoted APB) and stacking faults (denoted SF) are visible; and (c) cross-section SEM of 3C-SiC(100) evidencing the presence of voids at the SiC/Si interface.

Two kinds of defects within epitaxial 3C-SiC films, as illustrated in Fig. 3 (a, b), are widely documented. Antiphase boundaries are the first kind of defects encountered in 3C-SiC(100) epitaxial layers. They are planar defects formed at the geometrical separation of two 3C-SiC grains differing from each other by a 90° rotation in the Si(100) growth plane [47]. These antiphased domains (APDs) being formed by the presence of steps on the Si surface, these steps being constituted by an odd number of Si atomic steps. The nucleation of 3C-SiC on two different Si terraces leads to the formation of two SiC grains growing along the (100) direction but presenting an opposite atomic stacking arrangement along a <111> direction [47]. These two grains coalesce by forming a defective plane called antiphase boundary (APB). Different authors have studied the mechanisms of propagation and annihilation of these defects. It is admitted that when APBs are propagating along a {111} plane, a «natural» annihilation of APBs by mutual intersection occurs when the 3C-SiC is thickened [48, 49]. Nevertheless, it has also been mentioned that some APBs can propagate vertically along the (100) growth direction [50]. In that case, the thickening of the epilayer does not allow the reduction of their density [51]. The influence of APBs on the electrical properties of 3C-SiC epilayers is poorly documented but they are supposed to be electrically active, as demonstrated by Song *et al.,* who have reported their electrical activity [52] (Some details about these measures will be given in the following section). Furthermore, they constitute preferential etching sites when 3C-SiC surfaces are exposed to hydrogen [53]. A second kind of defect of importance is linked to the formation of stacking faults along the <111> planes. Indeed, the formation of two grains of 3C-SiC, differing from one another by a 60° in-plane rotation, is energetically identical but leads to the formation of twinned domains (also called double positioning domains) [54]. In 3C-SiC(100) oriented epilayers, twins are visible as inclined domains respectively to the (100) growth direction. They annihilate mutually by increasing the film thickness. Twins are also present in 3C-SiC(111) oriented layers where they can also be observed parallel to the growth direction (basal double positioning domains) [55]. It is important to notice that most of the published works dealing with 3C-SiC growth on silicon substrates highlight the intrinsic character of such defects and point out the fact that, except by increasing the film thickness, a drastic reduction of their density by only changing growth parameters is not possible. Some authors have proposed different extrinsic routes for effectively reducing the defect densities. In most cases, they require either the suppression of the silicon substrate or the use of specif‐ ically patterned Si substrates (undulant substrates) or both (switchback epitaxy) [56-58]. They appear very efficient in solving, to a large extent, the presence of extended defects in 3C-SiC(100) oriented epilayers.

the deposition process due to the lattice mismatch between 3C-SiC (4.36 Å) and Si (5.43 Å). In addition, thermoelastic stress is introduced during the post-deposition growth, due to the 8% difference in the thermal expansion coefficients of both materials. The resulting stress, which induces the formation of different planar or extended defects in 3C-SiC, is a major parameter leading to a noticeable degradation of the final crystalline quality of the epilayer. Furthermore, the specific nucleation stage adopted to grow SiC on Si, namely, the carburization stage, induces the formation of interfacial voids between SiC and Si, which could limit the interest of this system for the fabrication of devices that require interface abruptness or vertical transport. Finally, the residual stress state of the epilayer must be taken into consideration.

Hereafter, we will give a brief overview on the different kinds of defects encountered in 3C-SiC/Si epilayers grown by chemical vapor deposition. Many published works provide further details. We will also discuss the influence each defect can have on the potential development

**Figure 3.** (a) Plane view SEM image of 1-µm-thick 3C-SiC(100) epilayers; dark lines are antiphase boundaries; (b) crosssection TEM of 3C-SiC(100) epilayer where antiphase boundary (denoted APB) and stacking faults (denoted SF) are

Two kinds of defects within epitaxial 3C-SiC films, as illustrated in Fig. 3 (a, b), are widely documented. Antiphase boundaries are the first kind of defects encountered in 3C-SiC(100) epitaxial layers. They are planar defects formed at the geometrical separation of two 3C-SiC grains differing from each other by a 90° rotation in the Si(100) growth plane [47]. These antiphased domains (APDs) being formed by the presence of steps on the Si surface, these steps being constituted by an odd number of Si atomic steps. The nucleation of 3C-SiC on two different Si terraces leads to the formation of two SiC grains growing along the (100) direction but presenting an opposite atomic stacking arrangement along a <111> direction [47]. These two grains coalesce by forming a defective plane called antiphase boundary (APB). Different authors have studied the mechanisms of propagation and annihilation of these defects. It is admitted that when APBs are propagating along a {111} plane, a «natural» annihilation of APBs by mutual intersection occurs when the 3C-SiC is thickened [48, 49]. Nevertheless, it has also been mentioned that some APBs can propagate vertically along the (100) growth direction [50]. In that case, the thickening of the epilayer does not allow the reduction of their density [51]. The influence of APBs on the electrical properties of 3C-SiC epilayers is poorly documented but they are supposed to be electrically active, as demonstrated by Song *et al.,* who have

visible; and (c) cross-section SEM of 3C-SiC(100) evidencing the presence of voids at the SiC/Si interface.

of electronic and mechanical devices.

40 Advanced Silicon Carbide Devices and Processing

The formation of interfacial voids between the silicon substrate and the 3C-SiC epilayer is another kind of defect, which has a potential impact for the design of 3C-SiC/Si epilayer-based electrical or mechanical devices. Indeed, the formation of 3C-SiC on silicon substrates requires the realization of a first carbonization stage that forms a buffer 3C-SiC layer serving as a seed for the further growth of the epilayer. In most cases, this carbonization stage is performed using a carbon-containing precursor and during this stage some of the silicon substrate is consumed to form the SiC seed [59-62]. This consumption leads to the formation of more or less large cavities (voids) developing at the SiC/Si interface, as can be seen on Fig. 3(c) with noticeable densities (106 /108 cm-2). The direct consequence is that SiC/Si is never totally abrupt and can be a real concern for electric vertical transport. Thus, the reduction of the void densities remains a key issue especially for the achievement of electronic devices. This requires extended investigations for identifying the experimental key parameters that govern their formation. Some of them have already been discussed but are not totally efficient for the complete removal of the voids [63-66]. However, Bosi *et al.* have recently underlined the great impact of the thermal ramp used between carbonization and growth stages. They have demonstrated the fabrication of void-free epilayers by playing on that parameter [67]. This could be of great impact for solving the interface issue.

Finally, the residual stress in 3C-SiC/Si epilayers must be addressed. The residual stress comes from the opposite or additive effect of the intrinsic stress, arising during the growth of the epilayer, and the thermal stress induced during the cooling down process and regarding the large thermal expansion coefficient mismatch between SiC and Si. The residual stress is strongly dependent on the surface orientation as well as the growth parameter. In case of 3C-SiC(100) growth, the residual stress can be either compressive or tensile whereas it has always been observed tensile in case of 3C-SiC(111) epilayers. This has a direct consequence on when such epilayers can be used to fabricate mechanical devices. Our groups have illustrated this issue by reporting on the opposite deflections of cantilevers made from either 3C-SiC(100) or 3C-SiC(111) epilayers [68], as presented in Fig. 4. Our groups have illustrated this issue by reporting on the opposite deflections of cantilevers

made from either 3C-SiC(100) or 3C-SiC(111) epilayers [68], as presented in Fig. 4.

**Fig. 4.** Typical SEM images of 3C-SiC cantilevers formed on the basis of (a) (100) oriented and (b) (111) oriented films. **Figure 4.** Typical SEM images of 3C-SiC cantilevers formed on the basis of (a) (100) oriented and (b) (111) oriented films.

We will conclude this part by mentioning that grown epilayers present a quite important roughness (*R*q roughness in the range of some nm), which is not well suited for additional technological processes such as contacting. In order to achieve sufficient low surface roughness, 3C-SiC epilayers require additional chemical mechanical polishing (CMP), which allows us to significantly reduce the *R*q roughness in typical ranges below 0.5 nm [69]. We will conclude this part by mentioning that grown epilayers present a quite important roughness (*R*q roughness in the range of some nm), which is not well suited for additional technological processes such as contacting. In order to achieve sufficient low surface rough‐ ness, 3C-SiC epilayers require additional chemical mechanical polishing (CMP), which allows us to significantly reduce the *R*q roughness in typical ranges below 0.5 nm [69].

From the abovementioned developments, one can say that a broad knowledge of the different kinds of defects in 3C-SiC epilayers exist but, in comparison, few works have been reported on their influence on the electrical degradation they imply. In 2009, Eriksson *et al.* investigated the electrical characteristics of Au/3C-SiC Schottky diodes as a function of the contact area (Fig. 5) [70]. They observed that the Schottky barrier height increased upon reducing the contact area and, for the smallest diodes, the value approached the ideal barrier height value. As the defect density is deeply related to the size of the 3C-SiC Schottky diodes, this behavior clearly highlights the influence of the defect towards the electrical characteristics of power devices. However, the electrical influence of the extended defects in 3C-SiC was imprecise. From the abovementioned developments, one can say that a broad knowledge of the different kinds of defects in 3C-SiC epilayers exist but, in comparison, few works have been reported on their influence on the electrical degradation they imply. In 2009, Eriksson *et al.* investigated the electrical characteristics of Au/3C-SiC Schottky diodes as a function of the contact area (Fig. 5) [70]. They observed that the Schottky barrier height increased upon reducing the contact area and, for the smallest diodes, the value approached the ideal barrier height value. As the defect density is deeply related to the size of the 3C-SiC Schottky diodes, this behavior clearly highlights the influence of the defect towards the electrical characteristics of power devices. However, the electrical influence of the extended defects in 3C-SiC was imprecise.

In order to highlight the role of the defects from an electrical point of view, a 3C-SiC sample presenting different doping level was investigated by means of scanning spreading resistance microscopy (SSRM) [52]. The sample presented successive 1-µm-thick layers with a nitrogen doping level ranging from 1017 cm-3 to 5 × 1018 cm-3, separated by nonintentionally doped layers. As illustrated in Fig. 6(a), the defects are not present in atomic force microscopy (AFM) topography, whereas these are clearly evidenced on the SSRM cartography in Fig. 6(b). This result evidenced, for the first time, the electrical activity of the extended defects in 3C-SiC. Moreover, the inset in Fig. 6(a) highlighted the defect activity is higher than the electrical activity of a 5 × 1018 cm-3 nitrogen-doped 3C-SiC epilayer.

The electrical activity of extended defects in 3C-SiC is a major concern for electronic device functioning. Indeed, due to the fact that the current flows preferentially through these defects,

such epilayers can be used to fabricate mechanical devices. Our groups have illustrated this issue by reporting on the opposite deflections of cantilevers made from either 3C-SiC(100) or 3C-SiC(111) epilayers [68], as presented in Fig. 4. Our groups have illustrated this issue by reporting on the opposite deflections of cantilevers made from either 3C-SiC(100) or 3C-SiC(111) epilayers [68], as presented in Fig. 4.

(a) (b)

**Fig. 4.** Typical SEM images of 3C-SiC cantilevers formed on the basis of (a) (100) oriented

**Figure 4.** Typical SEM images of 3C-SiC cantilevers formed on the basis of (a) (100) oriented and (b) (111) oriented

We will conclude this part by mentioning that grown epilayers present a quite important roughness (*R*q roughness in the range of some nm), which is not well suited for additional technological processes such as contacting. In order to achieve sufficient low surface rough‐ ness, 3C-SiC epilayers require additional chemical mechanical polishing (CMP), which allows

us to significantly reduce the *R*q roughness in typical ranges below 0.5 nm [69].

We will conclude this part by mentioning that grown epilayers present a quite important roughness (*R*q roughness in the range of some nm), which is not well suited for additional technological processes such as contacting. In order to achieve sufficient low surface roughness, 3C-SiC epilayers require additional chemical mechanical polishing (CMP), which allows us to significantly reduce the *R*q roughness in typical ranges below 0.5 nm [69].

From the abovementioned developments, one can say that a broad knowledge of the different kinds of defects in 3C-SiC epilayers exist but, in comparison, few works have been reported on their influence on the electrical degradation they imply. In 2009, Eriksson *et al.* investigated the electrical characteristics of Au/3C-SiC Schottky diodes as a function of the contact area (Fig. 5) [70]. They observed that the Schottky barrier height increased upon reducing the contact area and, for the smallest diodes, the value approached the ideal barrier height value. As the defect density is deeply related to the size of the 3C-SiC Schottky diodes, this behavior clearly highlights the influence of the defect towards the electrical characteristics of power devices. However, the electrical influence of the extended

From the abovementioned developments, one can say that a broad knowledge of the different kinds of defects in 3C-SiC epilayers exist but, in comparison, few works have been reported on their influence on the electrical degradation they imply. In 2009, Eriksson *et al.* investigated the electrical characteristics of Au/3C-SiC Schottky diodes as a function of the contact area (Fig. 5) [70]. They observed that the Schottky barrier height increased upon reducing the contact area and, for the smallest diodes, the value approached the ideal barrier height value. As the defect density is deeply related to the size of the 3C-SiC Schottky diodes, this behavior clearly highlights the influence of the defect towards the electrical characteristics of power devices. However, the electrical influence of the extended defects in 3C-SiC was imprecise.

In order to highlight the role of the defects from an electrical point of view, a 3C-SiC sample presenting different doping level was investigated by means of scanning spreading resistance microscopy (SSRM) [52]. The sample presented successive 1-µm-thick layers with a nitrogen doping level ranging from 1017 cm-3 to 5 × 1018 cm-3, separated by nonintentionally doped layers. As illustrated in Fig. 6(a), the defects are not present in atomic force microscopy (AFM) topography, whereas these are clearly evidenced on the SSRM cartography in Fig. 6(b). This result evidenced, for the first time, the electrical activity of the extended defects in 3C-SiC. Moreover, the inset in Fig. 6(a) highlighted the defect activity is higher than the electrical

The electrical activity of extended defects in 3C-SiC is a major concern for electronic device functioning. Indeed, due to the fact that the current flows preferentially through these defects,

and (b) (111) oriented films.

42 Advanced Silicon Carbide Devices and Processing

films.

defects in 3C-SiC was imprecise.

activity of a 5 × 1018 cm-3 nitrogen-doped 3C-SiC epilayer.

**Figure 5.** Experimental Schottky barrier height values extracted from I-V measurements as a function of the contact radius of Au/3C-SiC Schottky diodes. The results show that the Schottky barrier height increases upon reducing the contact area and, for the smallest diodes, the value approaches the ideal barrier height value. This result was explained by the defects in 3C-SiC, from [70].

**Figure 6.** Atomic force microscopy topography (a) and scanning spreading resistance microscopy (b) of a 3C-SiC sam‐ ple presenting a nitrogen doping level from 1017 cm-3 to 5 × 1018 cm-3. The inset corresponds to the SSRM signal of the white rectangular area, from [52].

the electrical performances are severely degraded, leading in particular to high leakage currents and low breakdown voltages. As a consequence, even if some major progresses have been completed on 3C-SiC in the field of electronic device elaboration, this kind of application remains too challenging. To address electrical applications using 3C-SiC, a drastic reduction of the defects or of their electrical activity is compulsory.

#### **3. MEMS fabrication: A new challenge for 3C-SiC?**

As explained previously, due to the electrical activity of the extended defects in 3C-SiC, this silicon carbide polytype is not yet suitable for the elaboration of electronic devices. However, for microelectromechanical systems (MEMS) applications, silicon carbide presents very attractive physical and chemical properties (hardness, inertness, melting point, operative temperature, etc.) which open a large field of applications [71-75]. These unique properties are particularly adapted to elaborate microsystems with full satisfactory characteristics and offer the possibility of overcoming those observed on devices using silicon or silicon-based material, which are widely used materials in this field. For example, among the notable properties, silicon carbide biocompatibility is particularly suitable for medical applications [3].

#### **3.1. Silicon carbide etching**

The elaboration of MEMS devices requires the mastery of some technological steps. For example, in most cases, an etching stage is required. As shown previously, silicon carbide is a material presenting many properties. Nonetheless, some of them are also drawbacks to elaborate microsystems. This is particularly the case for its chemical inertness. Actually, due to this feature, wet etching of crystalline silicon carbide is extremely difficult as SiC is totally inert to all aqueous etching solutions at room temperature [76]. To our knowledge, the lowest etching temperature referenced in the literature was mentioned by Chu and Campbell in 1965 [77]. They succeeded in etching SiC at 180°C by means of H3PO4. The use of other solutions like KOH is also feasible but it requires higher temperatures [78]. In addition, wet etching is often isotropic and, due to the severe conditions required for silicon carbide etching, difficult to localize. Consequently, due to the huge difficulties of wet silicon carbide etching, many efforts were enforced to develop a more user-friendly method. This is the case for plasma etching, which has since been the subject of intense research for decades.

Historically, reactive ion etching (RIE) using a capacitively coupled plasma (CCP) reactor was massively investigated during the 1980s-1990s. In this configuration (usually just called RIE), a RF electromagnetic field is applied between the two electrodes located on both sides of the reactor. Then electrons are accelerated by the high-frequency electric field and ionize the molecules of the gas, leading to a plasma. Consequently, the ions produced can react with the material to etch. For that matter, this behavior is the source of the RIE appellation. Typically, this chemical reaction is isotropic, leading to sloped sidewall profiles. In contrast, according to ion energy, a sputtering effect of the material can also be observed, which mainly results in an anisotropic etching, then to vertical sidewalls. The two effects coexist and the predominance of one effect compared with the other depends on the etching parameters (power, pressure, etc.). As a consequence, in a «simple» RIE reactor, the ion energy is closely linked to their density [79]. Therefore, in the 1990s, another configuration was developed with the emergence of inductively coupled plasma (ICP) reactors. In such a reactor, the plasma, generated by a RF magnetic field as previously shown (RIE power), is also contained inside the chamber, which is encircled by an inductive coil (ICP power). The great advantage of this configuration, in comparison with a RIE reactor, is the possibility to independently control the ion energy (with the RIE power) and their densities (with the ICP power). It enables a wide process flexibility varying from a «pure» RIE plasma to a «pure» ICP plasma.

Silicon carbide plasma etching has been largely investigated. However, as previously men‐ tioned, silicon carbide is a material that is difficult to etch. This is also the case using plasma etching. Then, the success of SiC plasma etching involves the use of severe conditions, which are rarely compatible with the masking materials. For example, photoresist, which is a classical masking material for plasma etching, only operates for thin SiC layers according to the etching selectivity, classically around 1. Silicon dioxide films have also been investigated to act as a mask for plasma etching but it requires thick layers, typically several microns [80, 81]. As a consequence, due to the poor selectivity of these materials, a metallic mask is usually preferred. Among them, aluminum has been largely investigated and results to a selectivity at least one order of magnitude higher than the one observed with photoresist [82, 83]. Unfortunately, the use of an aluminum mask induces a micromasking effect [84]. This phenomenon, which can lead to a grass-like surface of the SiC film, is explained by the formation of Al2O3, which is a nonvolatile species [82]. Thus, nickel is widely used as a hard mask instead of aluminum as it presents the interesting detail of being chemically inert towards the chemical species of the plasma. Then, as nickel is only etched by ion bombardment, no micromasking effect is observed using such a metal, except if the mask design is not spaced out enough, which prevents the evacuation of nonvolatile species, as explained in [85].

In terms of chemistry, silicon carbide plasma etching has been largely investigated using fluorinated gases as it is generally admitted that fluor atoms react with both silicon and carbon to form, respectively, SiF*x* and CF*y* species [86]. These volatile species are then eliminated by pumping. In some studies, an additional gas, which could be argon or oxygen, is added to the fluorinated gas. Argon is attributed to promoting physical sputtering and also to increasing the dissociation of the plasma gas into reactive species, which therefore increase the etch rate [87]. In contrast, the role of oxygen is controversial. Some authors suggest that oxygen atoms participate directly in the etching of the SiC film by the formation of CO and CO2 species [88]. Other authors suggest that oxygen, for a typical fraction of 20%, helps to dissociate the fluorinated gas then produces more fluor atoms [71]. However, for higher fractions, it leads to a dilution of the fluorinated gas and then to a decrease of the etching rate [89]. This behavior was also observed by Jiang *et al.* [90]. Beheim *et al.* also observed an increase of the micro‐ trenching effect in all processes where O2 was incorporated [91]. This behavior was hypothe‐ sized by the formation of a SiF*x*O*<sup>y</sup>* layer that could have a greater tendency to charge than SiC. As a consequence, the charges on the sidewalls lead to the deflection of the incident ions, resulting in a microtrenching phenomenon. This same behavior has been observed by other groups [92, 93]. In addition, a small amount of oxygen, typically less than 10%, can be also added to the SF6 gas in order to react with a nickel mask. The aim is to promote the formation of a nickel oxide, which is more resistant to the plasma treatment [68]. It can be helpful for the plasma etching of thick silicon carbide layers as it increases selectivity. In conclusion, the benefit of using oxygen for silicon carbide plasma etching is still debated. Nevertheless, even if the full mechanisms involved in SiC plasma etching are not perfectly identified, this step, compulsory to consider the elaboration of MEMS devices, is now mastered with typical etching rate at around 1 µm/min.

#### **3.2. MEMS devices and mechanical properties**

attractive physical and chemical properties (hardness, inertness, melting point, operative temperature, etc.) which open a large field of applications [71-75]. These unique properties are particularly adapted to elaborate microsystems with full satisfactory characteristics and offer the possibility of overcoming those observed on devices using silicon or silicon-based material, which are widely used materials in this field. For example, among the notable properties,

The elaboration of MEMS devices requires the mastery of some technological steps. For example, in most cases, an etching stage is required. As shown previously, silicon carbide is a material presenting many properties. Nonetheless, some of them are also drawbacks to elaborate microsystems. This is particularly the case for its chemical inertness. Actually, due to this feature, wet etching of crystalline silicon carbide is extremely difficult as SiC is totally inert to all aqueous etching solutions at room temperature [76]. To our knowledge, the lowest etching temperature referenced in the literature was mentioned by Chu and Campbell in 1965 [77]. They succeeded in etching SiC at 180°C by means of H3PO4. The use of other solutions like KOH is also feasible but it requires higher temperatures [78]. In addition, wet etching is often isotropic and, due to the severe conditions required for silicon carbide etching, difficult to localize. Consequently, due to the huge difficulties of wet silicon carbide etching, many efforts were enforced to develop a more user-friendly method. This is the case for plasma

Historically, reactive ion etching (RIE) using a capacitively coupled plasma (CCP) reactor was massively investigated during the 1980s-1990s. In this configuration (usually just called RIE), a RF electromagnetic field is applied between the two electrodes located on both sides of the reactor. Then electrons are accelerated by the high-frequency electric field and ionize the molecules of the gas, leading to a plasma. Consequently, the ions produced can react with the material to etch. For that matter, this behavior is the source of the RIE appellation. Typically, this chemical reaction is isotropic, leading to sloped sidewall profiles. In contrast, according to ion energy, a sputtering effect of the material can also be observed, which mainly results in an anisotropic etching, then to vertical sidewalls. The two effects coexist and the predominance of one effect compared with the other depends on the etching parameters (power, pressure, etc.). As a consequence, in a «simple» RIE reactor, the ion energy is closely linked to their density [79]. Therefore, in the 1990s, another configuration was developed with the emergence of inductively coupled plasma (ICP) reactors. In such a reactor, the plasma, generated by a RF magnetic field as previously shown (RIE power), is also contained inside the chamber, which is encircled by an inductive coil (ICP power). The great advantage of this configuration, in comparison with a RIE reactor, is the possibility to independently control the ion energy (with the RIE power) and their densities (with the ICP power). It enables a wide process flexibility

Silicon carbide plasma etching has been largely investigated. However, as previously men‐ tioned, silicon carbide is a material that is difficult to etch. This is also the case using plasma etching. Then, the success of SiC plasma etching involves the use of severe conditions, which are rarely compatible with the masking materials. For example, photoresist, which is a classical

silicon carbide biocompatibility is particularly suitable for medical applications [3].

etching, which has since been the subject of intense research for decades.

varying from a «pure» RIE plasma to a «pure» ICP plasma.

**3.1. Silicon carbide etching**

44 Advanced Silicon Carbide Devices and Processing

As already discussed, due to its physical and chemical properties, 3C-SiC is a very promising material to elaborate MEMS devices. Some examples of already completed 3C-SiC-based microsystems are presented in Fig. 7.

SiC-based microsystems are presented in Fig. 7.

promising material to elaborate MEMS devices. Some examples of already completed 3C-

Lateral resonator [94] Vertical resonator [83] Nanocantilever [95]

**Fig. 7.** Examples of 3C-SiC MEMS devices, from the literature. **Figure 7.** Examples of 3C-SiC MEMS devices, from the literature.

For most applications, the idea is to take advantage of the SiC physical properties. For example, the resonant frequencies of the vertical resonators presented in Fig. 7 were around 40% higher than those obtained with an equivalent Si device and the quality factor was twice higher [83]. In addition, using 3C-SiC allows to achieve MEMS devices easier. Indeed, state of the art silicon-based technology is not compatible with conditions encountered by most devices. To become sufficient, some silicon-based devices require the use of cooling system or radiation shielding. These extra items add volume and weight to the initial MEMS devices which is in contradiction with the miniaturization targeted using MEMS devices. Moreover, for specific applications in the field of spatial or aeronautics, an increase of the weight leads to a severe rise of the cost [96]. Considering the silicon carbide physical properties, these problematics should be bypassed using 3C-SiC-based MEMS devices. For most applications, the idea is to take advantage of the SiC physical properties. For example, the resonant frequencies of the vertical resonators presented in Fig. 7 were around 40% higher than those obtained with an equivalent Si device and the quality factor was twice higher [83]. In addition, using 3C-SiC allows to achieve MEMS devices easier. Indeed, state of the art silicon-based technology is not compatible with conditions encountered by most devices. To become sufficient, some silicon-based devices require the use of cooling system or radiation shielding. These extra items add volume and weight to the initial MEMS devices which is in contradiction with the miniaturization targeted using MEMS devices. Moreover, for specific applications in the field of spatial or aeronautics, an increase of the weight leads to a severe rise of the cost [96]. Considering the silicon carbide physical properties, these problematics should be bypassed using 3C-SiC-based MEMS devices.

As 3C-SiC is grown on silicon, MEMS elaboration generally requires partial etching of the substrate. To do that, two ways are possible as, as opposed to silicon carbide, silicon can be easily etched by means of wet etching. Indeed, different wet-etching solutions have been used such as potassium hydroxide (KOH) mixtures [97,98] or HF:HNO3/H2O combination with [99] and without the adjunction of acetic acid [83]. This feasibility fully benefits from SiC's chemical inertia. However, it is also possible to directly etch the silicon substrate by means of plasma etching [80]. Indeed, according to the design of the microsystem, this step can even be completed in the same run that the plasma etching of the SiC film as both materials require fluorinated gases to be etched. It must also be noted that a modification of the plasma parameters can be helpful to favor the isotropic etching of the silicon substrate, in order to liberate the microsystems, as presented in Fig. 4. For each vibrating system, the Young's modulus is a key parameter. As a consequence, As 3C-SiC is grown on silicon, MEMS elaboration generally requires partial etching of the substrate. To do that, two ways are possible as, as opposed to silicon carbide, silicon can be easily etched by means of wet etching. Indeed, different wet-etching solutions have been used such as potassium hydroxide (KOH) mixtures [97, 98] or HF:HNO3/H2O combination with [99] and without the adjunction of acetic acid [83]. This feasibility fully benefits from SiC's chemical inertia. However, it is also possible to directly etch the silicon substrate by means of plasma etching [80]. Indeed, according to the design of the microsystem, this step can even be completed in the same run that the plasma etching of the SiC film as both materials require fluorinated gases to be etched. It must also be noted that a modification of the plasma param‐ eters can be helpful to favor the isotropic etching of the silicon substrate, in order to liberate the microsystems, as presented in Fig. 4.

many research works were focused on this mechanical property. To determine the Young's For each vibrating system, the Young's modulus is a key parameter. As a consequence, many research works were focused on this mechanical property. To determine the Young's modulus, two main methods are used, nanoindentation [100-102] and the resonant frequency measure‐ ment of clamped-free cantilevers. The first method consists of penetrating the SiC material by using a hard tip whose mechanical properties are known. Usually, the geometry of the indenter is known with high precision, which is the case for the Berkovic tip presenting a three-sided pyramid geometry. The indenter tip progressively penetrates the investigated material with the applications of increasing load. During the indentation process, depth penetration is

recorded as a function of the applied load, resulting in a load vs. displacement curve [103]. As this method cannot be used to provide an elastic modulus value in a particular direction, nanoindentation is more fitting for polycrystalline materials [104]. The second method, mainly used for the determination of 3C-SiC mechanical properties, consists of determining the resonance frequency of clamped-free cantilevers, as illustrated in Fig. 8. resulting in a load vs. displacement curve [103]. As this method cannot be used to provide an elastic modulus value in a particular direction, nanoindentation is more fitting for polycrystalline materials [104]. The second method, mainly used for the determination of 3C-SiC mechanical properties, consists of determining the resonance frequency of clampedfree cantilevers, as illustrated in Fig. 8.

As already discussed, due to its physical and chemical properties, 3C-SiC is a very promising material to elaborate MEMS devices. Some examples of already completed 3C-

 Lateral resonator [94] Vertical resonator [83] Nanocantilever [95]

For most applications, the idea is to take advantage of the SiC physical properties. For example, the resonant frequencies of the vertical resonators presented in Fig. 7 were around 40% higher than those obtained with an equivalent Si device and the quality factor was twice higher [83]. In addition, using 3C-SiC allows to achieve MEMS devices easier. Indeed, state of the art silicon-based technology is not compatible with conditions encountered by most devices. To become sufficient, some silicon-based devices require the use of cooling system or radiation shielding. These extra items add volume and weight to the initial MEMS devices which is in contradiction with the miniaturization targeted using MEMS devices. Moreover, for specific applications in the field of spatial or aeronautics, an increase of the weight leads to a severe rise of the cost [96]. Considering the silicon carbide physical properties, these problematics should be bypassed using 3C-SiC-based MEMS devices.

For most applications, the idea is to take advantage of the SiC physical properties. For example, the resonant frequencies of the vertical resonators presented in Fig. 7 were around 40% higher than those obtained with an equivalent Si device and the quality factor was twice higher [83]. In addition, using 3C-SiC allows to achieve MEMS devices easier. Indeed, state of the art silicon-based technology is not compatible with conditions encountered by most devices. To become sufficient, some silicon-based devices require the use of cooling system or radiation shielding. These extra items add volume and weight to the initial MEMS devices which is in contradiction with the miniaturization targeted using MEMS devices. Moreover, for specific applications in the field of spatial or aeronautics, an increase of the weight leads to a severe rise of the cost [96]. Considering the silicon carbide physical properties, these problematics

As 3C-SiC is grown on silicon, MEMS elaboration generally requires partial etching of the substrate. To do that, two ways are possible as, as opposed to silicon carbide, silicon can be easily etched by means of wet etching. Indeed, different wet-etching solutions have been used such as potassium hydroxide (KOH) mixtures [97,98] or HF:HNO3/H2O combination with [99] and without the adjunction of acetic acid [83]. This feasibility fully benefits from SiC's chemical inertia. However, it is also possible to directly etch the silicon substrate by means of plasma etching [80]. Indeed, according to the design of the microsystem, this step can even be completed in the same run that the plasma etching of the SiC film as both materials require fluorinated gases to be etched. It must also be noted that a modification of the plasma parameters can be helpful to favor the isotropic etching of the silicon substrate,

As 3C-SiC is grown on silicon, MEMS elaboration generally requires partial etching of the substrate. To do that, two ways are possible as, as opposed to silicon carbide, silicon can be easily etched by means of wet etching. Indeed, different wet-etching solutions have been used such as potassium hydroxide (KOH) mixtures [97, 98] or HF:HNO3/H2O combination with [99] and without the adjunction of acetic acid [83]. This feasibility fully benefits from SiC's chemical inertia. However, it is also possible to directly etch the silicon substrate by means of plasma etching [80]. Indeed, according to the design of the microsystem, this step can even be completed in the same run that the plasma etching of the SiC film as both materials require fluorinated gases to be etched. It must also be noted that a modification of the plasma param‐ eters can be helpful to favor the isotropic etching of the silicon substrate, in order to liberate

For each vibrating system, the Young's modulus is a key parameter. As a consequence, many research works were focused on this mechanical property. To determine the Young's

For each vibrating system, the Young's modulus is a key parameter. As a consequence, many research works were focused on this mechanical property. To determine the Young's modulus, two main methods are used, nanoindentation [100-102] and the resonant frequency measure‐ ment of clamped-free cantilevers. The first method consists of penetrating the SiC material by using a hard tip whose mechanical properties are known. Usually, the geometry of the indenter is known with high precision, which is the case for the Berkovic tip presenting a three-sided pyramid geometry. The indenter tip progressively penetrates the investigated material with the applications of increasing load. During the indentation process, depth penetration is

SiC-based microsystems are presented in Fig. 7.

46 Advanced Silicon Carbide Devices and Processing

**Fig. 7.** Examples of 3C-SiC MEMS devices, from the literature.

**Figure 7.** Examples of 3C-SiC MEMS devices, from the literature.

in order to liberate the microsystems, as presented in Fig. 4.

the microsystems, as presented in Fig. 4.

should be bypassed using 3C-SiC-based MEMS devices.

**Fig. 8.** (a) Multiple size cantilevers enabling Young's modulus extraction (b) 'Sun' cantilevers and associated vibration (c) measured by Polytec MSA 500 Laser Doppler Vibrometer (vibration mode 2). **Figure 8.** (a) Multiple size cantilevers enabling Young's modulus extraction (b) 'Sun' cantilevers and associated vibra‐ tion (c) measured by Polytec MSA 500 Laser Doppler Vibrometer (vibration mode 2).

This parameter, which can be directly determined using optical vibrometers, is used to calculate the Young's modulus as the resonance frequency of a clamped-free beam; the mode *n* is a function of device geometry and material properties as presented in the This parameter, which can be directly determined using optical vibrometers, is used to calculate the Young's modulus as the resonance frequency of a clamped-free beam, for the mode *n*, is a function of device geometry and material properties as presented in the following equation [105]:

following equation [105]:

$$f\_n = \frac{\left(\lambda\_n\right)^2}{2\pi\sqrt{12}} \frac{h}{L^2} \sqrt{\frac{E}{\rho}}\tag{1}$$

where *λn* is a constant depending of the mode (1 = 1.875, 2 = 4.694), *h* and *L* are, respectively, the thickness and the length of the beam, *E* the Young's modulus and *ρ* the cantilever material density (3.2 gcm3 for SiC). Indeed, as mentioned previously, the use of this method has highlighted the fact that 3C-SiC (100) cantilevers are bended downwards whereas 3C-SiC (111) cantilevers are bended upwards, which is clearly visible on submicron-thick cantilevers, and reveal opposite residual stress effects [68,106]. where *λ<sup>n</sup>* is a constant depending of the mode (*λ*<sup>1</sup> = 1.875, *λ*<sup>2</sup> = 4.694), *h* and *L* are, respectively, the thickness and the length of the beam, *E* the Young's modulus and *ρ* the cantilever material density (3.2 g cm-3 for SiC). Indeed, as mentioned previously, the use of this method has highlighted the fact that 3C-SiC (100) cantilevers are bended downwards whereas 3C-SiC (111) cantilevers are bended upwards, which is clearly visible on submicron-thick cantilevers, and reveal opposite residual stress effects [68, 106].

*L*

 Equation (1) assumes that the cantilever is free at one end and fixed to the bulk material at the other. Nonetheless, consecutive to the etching of the silicon substrate used to release the beams, an undercutting of the attachment region can be obtained. Consequently, the anchorage point is not totally fixed. As an example, for cantilevers presenting a 20-µm width, an over-etching of more than 10 µm can be observed. The consequence is an increase of the cantilever effective length [107], lowering the vibration frequency and leading to an underestimation of the Young's modulus. Then, in order to prevent a mistaken value of the Young's modulus, only «long» cantilevers should be considered, that means cantilevers presenting a length of around one order of magnitude higher than the over-etch value, as presented in Fig. 9.

**Figure 9.** Calculated values of the Young's modulus as a function of the cantilever length for a 0.5-µm-thick (111) 3C-SiC sample. The results are presented for vibration modes 1 and 2, on 10-µm-wide cantilevers.

In the literature, the values presented for the 3C-SiC Young's modulus are quite dispersed; however, a 450 GPa value for the 100 orientation, is usually acknowledged. However, since 1992, Tong *et al.* [108] have suggested that defect density could play a role in Young's modulus. As the crystalline quality is closely dependent of the 3C-SiC deposition method, the dispersion could be explained by the defect density. In 2009, Mastropaolo *et al.* investigated single crystal and polycrystalline 3C-SiC for MEMS applications [81]. In their work, cantilever resonators were fabricated from the two types of materials using films deposited by CVD. Experimental resonance frequencies were used to calculate the Young's modulus. Based on this method, they determined a Young's modulus of 446 and 246 GPa for a 2.3-µm-thick single crystalline (100) 3C-SiC epilayer and for a 1.4-µm-thick polycrystalline material, respectively. That same year, Locke *et al.* also investigated the Young's modulus of 3C-SiC by means of nanoindentation [102]. For a 2.3-µm-thick (100) 3C-SiC single crystalline material, they obtained a Young's modulus of 433 GPa, which was in good agreement with the results obtained by Mastropaolo *et al.* They also studied this parameter for (111) 3C-SiC films and obtained a value higher than 500 GPa. However, the Young's modulus determined on a polycrystalline material, evaluated to 457 GPa, was quite different from the one observed by Mastropaolo *et al*., whereas, in both cases, the thickness of the 3C-SiC layers was similar. Based on these studies, it was then difficult to clearly determine the influence of the defects towards the mechanical properties of 3C-SiC films.

In 2010, our groups also investigated the Young's modulus of 3C-SiC films by means of the resonance frequencies of clamped-free cantilevers, but for thin 3C-SiC epilayers (<550 nm) as submicron 3C-SiC layers are required for specific applications, for example, in the field of atomic force microscopy, as presented in Fig. 7(c) [95]. For (100) and (111) 3C-SiC oriented films, the Young's modulus has been evaluated to 350 GPa [68]. This result was in contradiction with the literature data obtained on thicker 3C-SiC materials. As a consequence, complemen‐ tary analyses of Young's modulus on thicker layers (then on less defective material), and on polycrystalline material (highly defective) were performed. The same experimental protocol lead to a Young's modulus evaluation of 450 GPa for a 2-µm-thick (100) 3C-SiC layer and close to 500 GPa for a 1-µm-thick (111) layer. For polycrystalline material, the Young's modulus was evaluated to 100-150 GPa. This behavior was attributed to the defect density and the evidence that the mechanical properties of 3C-SiC films were severely affected by the defect density, which has been suggested since 1992, was finally highlighted.

More recently, Anzalone *et al.* also studied the defect influence on heteroepitaxial 3C-SiC Young's modulus [109]. They found Young's modulus values from 217 to 425 GPa for (100) 3C-SiC films with a thickness ranging from 2.04 to 3.13 µm, confirming that Young's modulus is strictly related to the defect density and, therefore, to the film's thickness. In 2012, the same group also investigated the dependence of mechanical properties of 3C-SiC film with defect densities artificially induced by ion implantation [110]. The main conclusion of this paper was the correlation between the Young's modulus and the defects induced by the implantation step.

To conclude on this part, even if the defect density is not deeply detrimental for the functioning of MEMS devices, as defects can affect the 3C-SiC mechanical properties, their influence has to be taken into account.

#### **3.3. What's next for 3C-SiC-based MEMS?**

Equation (1) assumes that the cantilever is free at one end and fixed to the bulk material at the other. Nonetheless, consecutive to the etching of the silicon substrate used to release the beams, an undercutting of the attachment region can be obtained. Consequently, the anchorage point is not totally fixed. As an example, for cantilevers presenting a 20-µm width, an over-etching of more than 10 µm can be observed. The consequence is an increase of the cantilever effective length [107], lowering the vibration frequency and leading to an underestimation of the Young's modulus. Then, in order to prevent a mistaken value of the Young's modulus, only «long» cantilevers should be considered, that means cantilevers presenting a length of around

**Figure 9.** Calculated values of the Young's modulus as a function of the cantilever length for a 0.5-µm-thick (111) 3C-

In the literature, the values presented for the 3C-SiC Young's modulus are quite dispersed; however, a 450 GPa value for the 100 orientation, is usually acknowledged. However, since 1992, Tong *et al.* [108] have suggested that defect density could play a role in Young's modulus. As the crystalline quality is closely dependent of the 3C-SiC deposition method, the dispersion could be explained by the defect density. In 2009, Mastropaolo *et al.* investigated single crystal and polycrystalline 3C-SiC for MEMS applications [81]. In their work, cantilever resonators were fabricated from the two types of materials using films deposited by CVD. Experimental resonance frequencies were used to calculate the Young's modulus. Based on this method, they determined a Young's modulus of 446 and 246 GPa for a 2.3-µm-thick single crystalline (100) 3C-SiC epilayer and for a 1.4-µm-thick polycrystalline material, respectively. That same year, Locke *et al.* also investigated the Young's modulus of 3C-SiC by means of nanoindentation [102]. For a 2.3-µm-thick (100) 3C-SiC single crystalline material, they obtained a Young's modulus of 433 GPa, which was in good agreement with the results obtained by Mastropaolo *et al.* They also studied this parameter for (111) 3C-SiC films and obtained a value higher than 500 GPa. However, the Young's modulus determined on a polycrystalline material, evaluated to 457 GPa, was quite different from the one observed by Mastropaolo *et al*., whereas, in both

SiC sample. The results are presented for vibration modes 1 and 2, on 10-µm-wide cantilevers.

one order of magnitude higher than the over-etch value, as presented in Fig. 9.

48 Advanced Silicon Carbide Devices and Processing

The high 3C-SiC Young's modulus is not the only interesting property for MEMS applications. The chemical inertia and the temperature resistance of this material are also huge benefits to achieve microsystems that can operate in harsh environments.

In 2013, Michaud *et al.* succeeded in achieving a single crystalline 3C-SiC membrane on a 3C-SiC pseudo-substrate [111], using an original 3C-SiC/Si/3C-SiC stack grown on a 100 silicon substrate, as presented in Fig. 10. The process was based on the use of the sandwiched silicon film acting as a sacrificial layer. Such a structure could be the starting point for the achievement of complete SiC-based MEMS devices. Indeed, this result seems promising as, in 2014, Anzalone *et al.* also investigated the use of a Si/3C-SiC/Si heterostructure [112]. For example, using a thick 3C-SiC epilayer, the silicon substrate could be completely etched in order to obtain a self-supporting monocrystalline 3C-SiC structure. Such a feasibility could be very helpful for medical applications or for devices functioning in harsh environments for which the presence to be taken into account.

induced by the implantation step.

highlighted.

huge benefits to achieve microsystems that can operate in harsh environments.

**2.3. What's next for 3C-SiC-based MEMS?** 

contradiction with the literature data obtained on thicker 3C-SiC materials. As a consequence, complementary analyses of Young's modulus on thicker layers (then on less defective material), and on polycrystalline material (highly defective) were performed. The same experimental protocol lead to a Young's modulus evaluation of 450 GPa for a 2-µmthick (100) 3C-SiC layer and close to 500 GPa for a 1-µm-thick (111) layer. For polycrystalline material, the Young's modulus was evaluated to 100–150 GPa. This behavior was attributed to the defect density and the evidence that the mechanical properties of 3C-SiC films were severely affected by the defect density, which has been suggested since 1992, was finally

More recently, Anzalone *et al.* also studied the defect influence on heteroepitaxial 3C-SiC Young's modulus [109]. They found Young's modulus values from 217 to 425 GPa for (100) 3C-SiC films with a thickness ranging from 2.04 to 3.13 µm, confirming that Young's modulus is strictly related to the defect density and, therefore, to the film's thickness. In 2012, the same group also investigated the dependence of mechanical properties of 3C-SiC film with defect densities artificially induced by ion implantation [110]. The main conclusion of this paper was that the correlation between the Young's modulus and the defects were

To conclude on this part, even if the defect density is not deeply detrimental for the function of MEMS devices, as defects can affect the 3C-SiC mechanical properties, their influence has

The high 3C-SiC Young's modulus is not the only interesting property for MEMS

**Fig. 10.** Single crystalline 3C-SiC membrane on a 3C-SiC pseudo-membrane, from [111]. **Figure 10.** Single crystalline 3C-SiC membrane on a 3C-SiC pseudo-substrate, from [111].

of a silicon substrate is restraining. In addition, thanks in large part to the efforts engaged in controlling the doping level of 3C-SiC films, new MEMS devices could be achievable with, for example, the use of a highly doped layer acting as an electrode. In 2013, Michaud *et al.* succeeded in achieving a single crystalline 3C-SiC membrane on a 3C-SiC pseudo-membrane [111], using an original 3C-SiC/Si/3C-SiC stack grown on a 100

silicon substrate, as presented in Fig. 10. The process was based on the use of the

#### **4. Conclusion**

For decades, silicon carbide has been the subject of intensive research activities. This material exists in more than 250 identified structures called polytypes, but only 4H, 6H and 3C-SiC are commercially available. Among these polytypes, only the cubic one, 3C-SiC, can be grown on silicon substrates. This feasibility is a huge benefit to reducing the cost of the devices but, whereas SiC-based devices are more and more present in the market, 3C-SiC-based ones are lacking. However, important headways have been reached for electrical and MEMS applica‐ tions using this material. Then, the purpose of this chapter was to summarize the noticeable results obtained on this material.

For electrical considerations, large efforts have been done to control the doping level by means of ion implantation, which is a crucial issue to consider in the achievement of any electrical device. Indeed, beyond the necessity to get localized doped layer for electrical applications, doping is also mandatory to obtain ohmic contacts on 3C-SiC. This was probably the most significant issue investigated in the literature last two decades. Fortunately, due to the large efforts engaged for this problematic, specific contact resistance around 10-6 Ω cm2 are now «easily» obtained on 3C-SiC, which is a suitable value to consider the elaboration of electrical devices. However, for the moment, 3C-SiC-based electrical devices are still absent from the market, whereas the success of a fit ohmic contact and SiC local doping have long been considered as the main issues to overcome. Actually, this absence is explained by the high defect density, which has been proved quite recently by means of spreading scanning resist‐ ance microscopy. As a consequence, a drastic reduction of the defects or of their electrical activity is mandatory to expect elaborating noteworthy electronic devices.

In contrast, for microsystem applications, the high defect density combined with its electrical activity does not seem to be a challenging issue. Actually, some examples of microsystems like nanocantilevers or resonators have been already obtained using 3C-SiC. For such applications, the physical and mechanical properties are very motivating as they outshine those of silicon or silicon-based materials typically involved in the field of MEMS devices. These achievements have been accessible at the cost of large efforts on plasma etching. Indeed, this problem has been largely investigated in the last few decades, with probably the same interest as that of obtaining an ohmic contact for electrical applications. Even if a comprehension of the plasma etching mechanisms is not fully acquired, inductively coupled plasma etching is now a wellmastered technology. In addition, the feasibility to grow 3C-SiC/Si/3C-SiC stack on 100 silicon substrates, demonstrated recently, could open the way for the achievement of new MEMS devices, operating, for example, in harsh environments. As a consequence, for this application field, 3C-SiC is still a promising material with a huge potential remaining to be explored.

#### **Acknowledgements**

of a silicon substrate is restraining. In addition, thanks in large part to the efforts engaged in controlling the doping level of 3C-SiC films, new MEMS devices could be achievable with, for

**Fig. 10.** Single crystalline 3C-SiC membrane on a 3C-SiC pseudo-membrane, from [111].

In 2013, Michaud *et al.* succeeded in achieving a single crystalline 3C-SiC membrane on a 3C-SiC pseudo-membrane [111], using an original 3C-SiC/Si/3C-SiC stack grown on a 100 silicon substrate, as presented in Fig. 10. The process was based on the use of the

contradiction with the literature data obtained on thicker 3C-SiC materials. As a consequence, complementary analyses of Young's modulus on thicker layers (then on less defective material), and on polycrystalline material (highly defective) were performed. The same experimental protocol lead to a Young's modulus evaluation of 450 GPa for a 2-µmthick (100) 3C-SiC layer and close to 500 GPa for a 1-µm-thick (111) layer. For polycrystalline material, the Young's modulus was evaluated to 100–150 GPa. This behavior was attributed to the defect density and the evidence that the mechanical properties of 3C-SiC films were severely affected by the defect density, which has been suggested since 1992, was finally

More recently, Anzalone *et al.* also studied the defect influence on heteroepitaxial 3C-SiC Young's modulus [109]. They found Young's modulus values from 217 to 425 GPa for (100) 3C-SiC films with a thickness ranging from 2.04 to 3.13 µm, confirming that Young's modulus is strictly related to the defect density and, therefore, to the film's thickness. In 2012, the same group also investigated the dependence of mechanical properties of 3C-SiC film with defect densities artificially induced by ion implantation [110]. The main conclusion of this paper was that the correlation between the Young's modulus and the defects were

To conclude on this part, even if the defect density is not deeply detrimental for the function of MEMS devices, as defects can affect the 3C-SiC mechanical properties, their influence has

The high 3C-SiC Young's modulus is not the only interesting property for MEMS applications. The chemical inertia and the temperature resistance of this material are also

**2.3. What's next for 3C-SiC-based MEMS?** 

huge benefits to achieve microsystems that can operate in harsh environments.

For decades, silicon carbide has been the subject of intensive research activities. This material exists in more than 250 identified structures called polytypes, but only 4H, 6H and 3C-SiC are commercially available. Among these polytypes, only the cubic one, 3C-SiC, can be grown on silicon substrates. This feasibility is a huge benefit to reducing the cost of the devices but, whereas SiC-based devices are more and more present in the market, 3C-SiC-based ones are lacking. However, important headways have been reached for electrical and MEMS applica‐ tions using this material. Then, the purpose of this chapter was to summarize the noticeable

For electrical considerations, large efforts have been done to control the doping level by means of ion implantation, which is a crucial issue to consider in the achievement of any electrical device. Indeed, beyond the necessity to get localized doped layer for electrical applications, doping is also mandatory to obtain ohmic contacts on 3C-SiC. This was probably the most significant issue investigated in the literature last two decades. Fortunately, due to the large

«easily» obtained on 3C-SiC, which is a suitable value to consider the elaboration of electrical devices. However, for the moment, 3C-SiC-based electrical devices are still absent from the market, whereas the success of a fit ohmic contact and SiC local doping have long been considered as the main issues to overcome. Actually, this absence is explained by the high defect density, which has been proved quite recently by means of spreading scanning resist‐ ance microscopy. As a consequence, a drastic reduction of the defects or of their electrical

efforts engaged for this problematic, specific contact resistance around 10-6 Ω cm2

activity is mandatory to expect elaborating noteworthy electronic devices.

example, the use of a highly doped layer acting as an electrode.

**Figure 10.** Single crystalline 3C-SiC membrane on a 3C-SiC pseudo-substrate, from [111].

**4. Conclusion**

highlighted.

induced by the implantation step.

to be taken into account.

50 Advanced Silicon Carbide Devices and Processing

results obtained on this material.

The authors are thankful to past and present PhD students involved in 3C-SiC in GREMAN and CRHEA laboratories (Dr. A.E. Bazin, Dr. X. Song, Dr. S. Jiao, Dr. J. Biscarrat and R. Khazaka). We also would like to acknowledge colleagues from our laboratories and collabo‐ rators from NOVASiC (Dr. M. Zielinski and Dr. T. Chassagne).

#### **Author details**

Jean-François Michaud1\*, Marc Portail2 and Daniel Alquier1

\*Address all correspondence to: jean-francois.michaud@univ-tours.fr

1 University Francois Rabelais of Tours, GREMAN, BP, Tours Cedex 2, France

2 CRHEA CNRS-UPR10, Valbonne, France

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## **Impact of Dielectric Formation and Processing Techniques on the Operation of 4H-SiC MOSFETs**

Lucy Martin, Hua-Khee Chan, Ming-Hung Weng and Alton Horsfall

Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/61067

#### **Abstract**

[112] R. Anzalone, M. Camarda, A. Severino, N. Piluso and F. La Via. Curvature evalua‐ tion of Si/3C-SiC/Si hetero-structure grown by chemical vapor deposition. Materials

Science Forum 778-780 (2014) 255.

60 Advanced Silicon Carbide Devices and Processing

The mobility of carriers in the channel of silicon carbide is significantly lower than in equivalent silicon devices. This results in a significant increase in on-state resistance in comparison to theoretical predictions and is hindering the uptake of silicon carbide technology in commercial circuits. The density of interface traps at the interface be‐ tween silicon carbide and the dielectric film is higher and this is often considered to be the primary reason for the low mobility. In this work, we show that the mobility is dominated by the surface roughness of the silicon carbide, especially when the tran‐ sistor is operating in the strong inversion regime, by careful examination of the char‐ acteristics of lateral transistors designed to form complimentary MOS functions.

**Keywords:** Surface roughness, mobility, complementary metal–oxide semiconductor, flat band, 1/*f* noise

#### **1. Introduction**

The main objective of this study is to aid in the advancement and commercialisation of a CMOS process to enable the production of signal-level 4H-SiC MOSFETs for high-temperature digital and analog applications. Therefore, we report on the electrical characterisation and perform‐ ance of 4H-SiC n- and p-channel MOSFETs that have been fabricated using different, com‐ mercially relevant dielectric process treatments. The samples labelled as HV06, CR25 and CR27 were fabricated using the process conditions detailed in Table 1. The aim of this work is to establish which oxidation process technique provides the best characteristics for a comple‐ mentary CMOS process.

© 2015 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

#### **2. Overview of the theoretical MOSFET**

The metal–oxide semiconductor field-effect transistor (MOSFET) is one of the most important devices for integrated circuits in microprocessors and semiconductor memories, as well as being a very important power device. Due to this, it is becoming increasingly important to understand and advance the characteristics of 4H-SiC MOSFETs for both power device applications and signal-level devices. MOSFETs have several attractive features, which make them ideal for use in analog switching, high-input-impedance amplifiers, microwave ampli‐ fiers and digital integrated circuits.

The features include the following:


The MOSFET is usually referred to as a majority carrier or unipolar device because the current in a MOSFET is predominantly transported by carriers of one polarity. As shown in Figure 1, a MOSFET is a four-terminal device made up of a source, drain, gate and substrate or body. Figure 1 shows an n-channel MOSFET, which is made up of a p-type substrate into which two n+ regions are formed, the source and drain and a gate electrode which is usually made of doped polysilicon or metal and is separated from the substrate by a thin insulating film known as the gate dielectric.

**Figure 1.** Schematic representation of a simple n-MOSFET

When a low voltage is applied to the gate electrode that is insufficient to form an inversion layer at the surface, there is no conduction in the channel, which corresponds to two p–n junctions situated back to back. This results in a high resistance and electrical isolation between the source and drain contacts. If a sufficiently large bias is applied to the gate electrode, a surface inversion layer will be formed between the source and drain, which will form a conductive channel through which a current can flow. The conductance of the channel can be modulated by varying the voltage applied to the gate electrode. Conduction in n-channel devices is based on the flow of electrons, and the channel becomes more conductive with increasing positive bias on the gate, whilst p-channel devices are controlled by hole conduction and are more conductive with a more negative gate bias. Enhancement-mode (or normally off) devices have a low transconductance at zero gate bias and require an applied gate voltage to form a conductive channel. Their counterpart, depletion-mode (or normally on) devices, are conductive when a zero bias is applied to the gate of the device, and a gate voltage must be applied to turn the channel off. Devices can either have a surface inversion channel or a buried channel. Buried channel devices are based on bulk conduction and are, therefore, free of surface effects such as scattering and surface defects resulting in better carrier mobility. The physical distance between the gate and the channel is larger and also dependent on gate bias, leading to lower and variable transconductance.

In a long-channel MOSFET, at low drain voltage and for a given gate voltage, the drain current is given by

$$I\_{DS} = \frac{W}{L} q \mu\_{inv} \left| \mathbf{Q}\_{inv} \right| V\_{DS} \tag{1}$$

where *W* and *L* are the gate width and length, *q* is the electron charge, *μinv* the average mobility of the carriers in the inversion layer, *VDS* the drain voltage and *Qinv* the average charge in the inversion layer.

The field effect mobility *μFE* is defined as

**2. Overview of the theoretical MOSFET**

fiers and digital integrated circuits.

62 Advanced Silicon Carbide Devices and Processing

The features include the following:

are connected in parallel.

**Figure 1.** Schematic representation of a simple n-MOSFET

as the gate dielectric.

The metal–oxide semiconductor field-effect transistor (MOSFET) is one of the most important devices for integrated circuits in microprocessors and semiconductor memories, as well as being a very important power device. Due to this, it is becoming increasingly important to understand and advance the characteristics of 4H-SiC MOSFETs for both power device applications and signal-level devices. MOSFETs have several attractive features, which make them ideal for use in analog switching, high-input-impedance amplifiers, microwave ampli‐

**1.** Higher input impedance than bipolar transistors, which allows the input impedance to

**2.** Negative temperature coefficient at high current levels – more uniform temperature distribution over the device area and prevents the FET from thermal runaway or second

**3.** The device is thermally stable, even when the active area is large or when many devices

**4.** FETs do not suffer from minority carrier storage as there is no forward-biased p–n junction

The MOSFET is usually referred to as a majority carrier or unipolar device because the current in a MOSFET is predominantly transported by carriers of one polarity. As shown in Figure 1, a MOSFET is a four-terminal device made up of a source, drain, gate and substrate or body. Figure 1 shows an n-channel MOSFET, which is made up of a p-type substrate into which two n+ regions are formed, the source and drain and a gate electrode which is usually made of doped polysilicon or metal and is separated from the substrate by a thin insulating film known

When a low voltage is applied to the gate electrode that is insufficient to form an inversion layer at the surface, there is no conduction in the channel, which corresponds to two p–n

be more readily matched to the standard microwave system.

and consequently have higher large-signal switching speeds.

breakdown that can occur in the bipolar transistors.

$$
\mu\_{\rm FE} = \frac{L}{\rm WC\_{\cdot}V\_{DS}} \left(\frac{\delta I\_{\rm DS}}{\delta V\_{\rm GS}}\right) \tag{2}
$$

where *Ci* is the insulator capacitance per unit area and *VGS* is the gate voltage.

In 4H-SiC MOSFETs, the values of the field effect mobility extracted from the *VGS –IDS* characteristics will not correspond to the true inversion mobility due to the large density of interface charge. A knowledge of *Qinv* as a function of *VGS,* which can be extracted from the measured *VGS –IDS* characteristics, can allow the immobile interface charge to be calculated, which includes contributions from both *Qf* and *Qit*. A change in gate voltage *δVGS* results in a change in *Qit* and a change in *δQinv* in the inversion layer as the surface Fermi level moves away from the intrinsic level towards the conduction band edge [1]. This can be summarised through the use of equation 3:

$$
\delta \mathcal{S} V\_{GS} = -\frac{q}{\mathcal{C}\_i} \left( \delta \mathcal{Q}\_{it} + \delta \mathcal{Q}\_{inv} \right) \tag{3}
$$

By combining equations 2 and 3, an expression that relates the experimental field effect mobility and the inversion carrier mobility can be derived [2]:

$$
\mu\_{\rm FE} = \mu\_{\rm FE} \frac{\left[1 + \frac{\mathbf{Q}\_{\rm inv}}{\mu\_{\rm inv}} \frac{\delta \mu\_{\rm inv}}{\delta \mathbf{Q}\_{\rm inv}}\right]}{1 + \frac{\delta \mathbf{Q}\_{\rm int}}{\delta \mathbf{Q}\_{\rm inv}}} \tag{4}
$$

#### **3. Carrier mobility and scattering mechanisms in 4H-SiC**

The conductivity (*σ*) of a semiconductor can be varied by the introduction of n- or p-type dopants and can be represented by equation 5:

$$
\sigma = qn\mu\tag{5}
$$

where *μ* is the carrier mobility, *q* the charge of an electron and *n* the number of carriers in the material.

The carrier mobility is principally how quickly an electron or hole can move through a semiconductor under the influence of an applied electric field and is affected by the frequency of collisions with lattice defects and impurities. The probability of scattering is inversely proportional to the carrier mean free time and the mobility. A carrier moving through a semiconductor crystal can be scattered by a vibration of the lattice, which increases for high temperatures when the thermal agitation of the lattice becomes higher. Scattering can also be due to lattice defects (e.g. ionised impurities) and is prominent at low temperatures since atoms are less thermally agitated and the thermal motion of the carriers is also slower. Higher scattering arises because a slow moving carrier is likely to be scattered more significantly by an interaction with a charged ion than a carrier with a larger velocity. If the carrier mobility in a material is reduced, the conductivity of the material will reduce and hence the resistivity will increase and channel current will reduce. As it is widely known that 4H-SiC MOSFETs exhibit low channel mobility and hence low current, it is of great importance to analyse the mecha‐ nisms that are contributing to the reduced channel mobility.

As previously reported [3-5], the total inversion carrier mobility in 4H-SiC MOSFETs can be described by the sum of four mobility terms using Matthiessen's rule which is often incorporated in simulation tools, such as the Synopsys suite by means of the Lombardi mobility model [6,7]:

Impact of Dielectric Formation and Processing Techniques on the Operation of 4H-SiC MOSFETs http://dx.doi.org/10.5772/61067 65

$$
\mu\_{inv} = \left[\frac{1}{\mu\_{\rm B}} + \frac{1}{\mu\_{\rm AC}} + \frac{1}{\mu\_{\rm SR}} + \frac{1}{\mu\_{\rm C}}\right]^{-1} \tag{6}
$$

As previously stated, the measured field effect mobility will not correspond to the true inversion mobility due to the presence of interface trapped charges. However, the main interest in silicon carbide technology is in the development of devices with higher functionality, and so the experimental device characteristics of the modelled mobility mechanisms will be equated to the field effect mobility using equation 7. Therefore, each of the scattering mecha‐ nisms considered here (*μAC, μSR* and *μC)* will result in a mobility which is lower than the value of each that would combine to form the true inversion mobility:

*GS* ( *it inv* ) *i <sup>q</sup> V QQ <sup>C</sup>*

By combining equations 2 and 3, an expression that relates the experimental field effect

*inv inv inv inv*

dm

*it inv*

d

é ù ê ú + ë û <sup>=</sup> +

d

The conductivity (*σ*) of a semiconductor can be varied by the introduction of n- or p-type

 m

where *μ* is the carrier mobility, *q* the charge of an electron and *n* the number of carriers in the

The carrier mobility is principally how quickly an electron or hole can move through a semiconductor under the influence of an applied electric field and is affected by the frequency of collisions with lattice defects and impurities. The probability of scattering is inversely proportional to the carrier mean free time and the mobility. A carrier moving through a semiconductor crystal can be scattered by a vibration of the lattice, which increases for high temperatures when the thermal agitation of the lattice becomes higher. Scattering can also be due to lattice defects (e.g. ionised impurities) and is prominent at low temperatures since atoms are less thermally agitated and the thermal motion of the carriers is also slower. Higher scattering arises because a slow moving carrier is likely to be scattered more significantly by an interaction with a charged ion than a carrier with a larger velocity. If the carrier mobility in a material is reduced, the conductivity of the material will reduce and hence the resistivity will increase and channel current will reduce. As it is widely known that 4H-SiC MOSFETs exhibit low channel mobility and hence low current, it is of great importance to analyse the mecha‐

As previously reported [3-5], the total inversion carrier mobility in 4H-SiC MOSFETs can be described by the sum of four mobility terms using Matthiessen's rule which is often incorporated in simulation tools, such as the Synopsys suite by means of the Lombardi

*Q Q Q*

=- + (3)

= *qn* (5)

(4)

 dd

1

*FE FE*

**3. Carrier mobility and scattering mechanisms in 4H-SiC**

s

 m

1

*Q*

m d

d

64 Advanced Silicon Carbide Devices and Processing

mobility and the inversion carrier mobility can be derived [2]:

m

dopants and can be represented by equation 5:

nisms that are contributing to the reduced channel mobility.

material.

mobility model [6,7]:

$$
\mu\_{\rm FE} \propto \left[ \frac{1}{\mu\_{\rm B}} + \frac{1}{\mu\_{\rm AC}} + \frac{1}{\mu\_{\rm SR}} + \frac{1}{\mu\_{\rm C}} \right] \tag{7}
$$

where*μB* is the carrier mobility in the bulk semiconductor, *μAC* the acoustic phonon mobility, *μSR* the surface roughness mobility and *μC* the mobility related to carrier scattering at trapped charge at the silicon carbide–oxide interface.

At low electric fields, the carrier mobility in a semiconductor is a function of the temperature and the total doping concentration, which is referred to as the bulk or low-field mobility, *μB*. To represent this phenomena, an empirical model was developed by Caughey and Thomas which is described through the use of equation 8 [8, 9]:

$$\mu\_{\rm B} = \frac{\mu\_{\rm max} \left(\frac{300}{T}\right)^{\alpha} - \mu\_{\rm min}}{1 + \left(\frac{D}{N\_{\rm ref}}\right)^{\rho}} \tag{8}$$

where *Nref*, *μmin*, *μmax*, *α* and *β* are fitting parameters, *T* the temperature and *D* the total doping concentration.

The second term in equation 7 is the acoustic phonon mobility, *μAC.* Both surface phonon and bulk phonon scattering have been modelled previously [10-12]. Each shows a temperature dependence and both surface and bulk phonon scatterings increase with an increase in temperature. Previous research has indicated that phonon scattering has a strong effect on surface mobility in SiC MOSFETs at high gate biases and high temperatures [13], and Potbhare et al. showed that surface phonon mobility does not play an important role at temperatures below 200°C [14]. The carrier mobility related to phonon scattering can be determined using equation 9:

$$
\mu\_{AC} = \frac{\mathcal{B}}{E} + \frac{\text{CN}\_A^{\alpha 1}}{TE^{\frac{1}{3}}} \tag{9}
$$

where *B* and *C* are fitting parameters, *E* the perpendicular electric field, *NA* the total doping concentration, *T* the temperature and *α*1 a factor that indicates the dependency of the mobility term *μAC* on the impurity concentration.

Surface roughness scattering is due to the scattering of mobile carriers by imperfections in the SiC surface and is known to cause severe degradation of the surface mobility at high electric fields [8, 15, 16]. The carrier mobility determined from surface roughness scattering may be calculated using equation 10:

$$
\mu\_{\rm SR} = \frac{D\_1}{E^{\gamma 1}} \tag{10}
$$

wher*e E* is the perpendicular electric field an*d D1* and *γ*1 are fitting parameters.

Coulomb scattering is a result of carrier interactions with ionised impurities, which are most commonly a product of interface traps at the semiconductor–dielectric interface. Coulomb scattering is believed to dominate carrier mobility at low electric fields and is calculated using equation 11 [4]:

$$
\mu\_{\mathbb{C}} = \mathrm{NT}^{a2} \frac{\mathbb{Q}\_{\mathrm{uv}}^{\rho\_2}}{\mathbb{Q}\_{\mathrm{trap}}} \tag{11}
$$

where *Qinv* is the inversion charge per unit area, *β*2 a fitting parameter, *Qtrap* the trapped charge per unit area at the silicon carbide–oxide interface and *T* the temperature. For the analysis reported here, the exact values of *Qtrap* and *β*2 were unknown, and so a simplified formula was derived that has the same functional form but could be fitted to the measure MOSFET field effect mobility characteristics [17], which is given in equation 12:

$$
\mu\_{\mathbb{C}} = \left(E - \mathbb{Z}\right)^{\Phi} \tag{12}
$$

wher*e E* is the perpendicular electric field, *λ* the electric field offset at which the mobility becomes nonzero and Φ a fitting parameter which describes the gradient of the increasing mobility.

Figure 2 shows a schematic plot of the contributions of the three scattering mechanisms that have been discussed here:*μAC, μSR* and *μC.* For MOSFETs fabricated using 4H-SiC, the bulk mobility contribution to equation 7 term (*μB*) is far higher than the other scattering mechanisms, resulting in a negligible impact on the field effect mobility characteristics of the devices. For this reason, *μB*is omitted from further analysis and is not included in Figure 2. As shown in Figure 2, Coulomb scattering dominates the field effect mobility under low electric fields, with surface roughness scattering dominating under high electric fields as carriers are strongly attracted to the semiconductor surface under high applied biases and therefore have more interactions with the surface.

**Figure 2.** Schematic representation of the field effect mobility in an n-type MOSFET channel

#### **4. Current status of the technology**

= + (9)

= (10)

= (11)

= - *E* (12)

a

*B CN <sup>E</sup> TE*

where *B* and *C* are fitting parameters, *E* the perpendicular electric field, *NA* the total doping concentration, *T* the temperature and *α*1 a factor that indicates the dependency of the mobility

Surface roughness scattering is due to the scattering of mobile carriers by imperfections in the SiC surface and is known to cause severe degradation of the surface mobility at high electric fields [8, 15, 16]. The carrier mobility determined from surface roughness scattering may be

> 1 *SR* 1 *D E*g

Coulomb scattering is a result of carrier interactions with ionised impurities, which are most commonly a product of interface traps at the semiconductor–dielectric interface. Coulomb scattering is believed to dominate carrier mobility at low electric fields and is calculated using

> 2 2 *inv*

> > *trap*

where *Qinv* is the inversion charge per unit area, *β*2 a fitting parameter, *Qtrap* the trapped charge per unit area at the silicon carbide–oxide interface and *T* the temperature. For the analysis reported here, the exact values of *Qtrap* and *β*2 were unknown, and so a simplified formula was derived that has the same functional form but could be fitted to the measure MOSFET field

( )<sup>Φ</sup>

 l

wher*e E* is the perpendicular electric field, *λ* the electric field offset at which the mobility becomes nonzero and Φ a fitting parameter which describes the gradient of the increasing

Figure 2 shows a schematic plot of the contributions of the three scattering mechanisms that have been discussed here:*μAC, μSR* and *μC.* For MOSFETs fabricated using 4H-SiC, the bulk mobility contribution to equation 7 term (*μB*) is far higher than the other scattering mechanisms,

*C* m

*<sup>Q</sup> NT Q* b

a

m

wher*e E* is the perpendicular electric field an*d D1* and *γ*1 are fitting parameters.

*C*

m

effect mobility characteristics [17], which is given in equation 12:

*AC*

m

term *μAC* on the impurity concentration.

66 Advanced Silicon Carbide Devices and Processing

calculated using equation 10:

equation 11 [4]:

mobility.

The current status of MOSFET technology is still plagued by low channel mobility and oxide reliability issues due to issues with the 4H-SiC/dielectric interface, which is believed to be due to an unoptimised dielectric formation and post-oxidation anneal procedure. There has been a significant amount of research into the effects of varying the post-oxidation anneal condi‐ tions, including the use of hydrogen, oxygen, nitrogen and phosphorus anneal environments, which have previously been used to passivate interface traps in silicon technology. This has led to advances in the capabilities of the technology, and MOSFET field effect mobilities of over 100 *cm*<sup>2</sup> ⋅*V* <sup>−</sup><sup>1</sup> ⋅ *s* <sup>−</sup><sup>1</sup> have been reported in n-channel MOSFETs formed in Al-implanted regions, after performing a post deposition anneal in POCl3 [18].

#### **5. Fabrication techniques and process variations**

Complementary metal–oxide semiconductor (CMOS) devices fabricated using the three gate dielectrics summarised in Table 1 were examined using electrical characterisation techniques. The remaining process steps utilised in their fabrication were identical. The main aim of this investigation is to highlight the benefits and potential issues of each processing technique on the electrical performance of the devices under test.

The CMOS test structures reported here were fabricated on a 100 mm, Si face, 4° off axis, 4H SiC n+ wafer with a doped epitaxial layer. N- and p-type regions and the source and drain regions were formed by ion implantation. The implants were annealed at high temperature with the surface protected by a carbon cap. A thick field oxide and a thin gate dielectric region were then formed and doped polysilicon gate electrodes. Nickel-based contacts were then formed on the doped regions and a refractory metal interconnect was deposited and patterned. Next, a thin nickel top layer was applied to protect the pads from oxidation during probe testing at elevated temperatures. Finally, an oxide layer was deposited for final passivation and scratch protection, and openings were made for bond pads. A schematic of the device cross section is shown in Figure 3.


**Table 1.** Summary of the dielectric process conditions

**Figure 3.** Schematic cross section of the completed transistor structures

#### **6. Temperature-dependent electrical characteristics of 4H-SiC MOSFETs**

The remaining process steps utilised in their fabrication were identical. The main aim of this investigation is to highlight the benefits and potential issues of each processing technique on

The CMOS test structures reported here were fabricated on a 100 mm, Si face, 4° off axis, 4H

**Sample Initial process Dielectric Post-oxidation anneal**

Deposited phosphorous doped

O2 950 C N2 1200 C

H2O 875 C N2 1100 C

Steam 950 C

HV06 Dry oxidation at 1200 C

CR27 Dry oxidation stub oxide

phosphorous anneal and strip Deposited undoped oxide

 wafer with a doped epitaxial layer. N- and p-type regions and the source and drain regions were formed by ion implantation. The implants were annealed at high temperature with the surface protected by a carbon cap. A thick field oxide and a thin gate dielectric region were then formed and doped polysilicon gate electrodes. Nickel-based contacts were then formed on the doped regions and a refractory metal interconnect was deposited and patterned. Next, a thin nickel top layer was applied to protect the pads from oxidation during probe testing at elevated temperatures. Finally, an oxide layer was deposited for final passivation and scratch protection, and openings were made for bond pads. A schematic of the device

the electrical performance of the devices under test.

cross section is shown in Figure 3.

68 Advanced Silicon Carbide Devices and Processing

CR25 Dry oxidation at 1200C with

**Table 1.** Summary of the dielectric process conditions

**Figure 3.** Schematic cross section of the completed transistor structures

SiC n+

In the following subsections, the current-voltage characteristics are extracted and explored for the three different dielectric samples (HV06, CR25 and CR27) on both n-channel and p-channel 4H-SiC MOSFETs. This involved the extraction of the field effect mobility *μFE,* subthreshold slope (*SS*) and threshold voltage *VTH* from the measured *VGS –IDS* characteristics across a temperature range of 298 K to 498 K with 50 K increments in order to understand the effect of the dielectric processing treatment on the MOSFET characteristics. The extracted field effect mobility for each of the samples is also fitted to the theoretical model for mobility using equation 6 in order to predict the mobility-limiting mechanisms for each of the MOSFETs and the impact of temperature on the mobility-limiting mechanisms involved. All of the electrical characteristics discussed in this chapter were extracted using a Keithley 4200 SCS Parameter Analyser.

### **7. Temperature-dependent electrical characteristics of n-channel 4H-SiC MOSFETs**

The data shown in Figures 4, 5 and 6 show the *VGS –IDS* and *VGS -log(IDS)* characteristics for a typical 400x1.5 *μm* n-channel MOSFET for HV06, CR25 and CR27, respectively, measured from 298 K to 498 K. The drain bias in each of the measurements was 500 mV. Each of the samples shows a similar trend and there is an increase in drain current, a reduction in threshold voltage and a change in the subthreshold slope with increasing temperature. The data for HV06 in Figure 4 shows a much higher off-state leakage current, with subthreshold drain currents consistently around 0.1 nA, whereas the data for both CR25 (Figure 5) and CR27 (Figure 6) show reverse leakage current of approximately 1 pA. The off-state conduction could be due to counter doping in the channel region, which could be a product of the threshold-adjust implant [19]. This counter doping could have also been increased as an unwanted effect during the 1200 C to the N2O post-oxidation anneal that was performed on the dielectric as described in Table 1.

The increase in current with temperature observed in Figures 4.a, 5.a and 6.a for the three samples is due to the decrease of occupied interface traps with an increasing temperature, which is an agreement with the density of interface traps data extracted from capacitor test structures fabricated monolithically with the MOSFETs. As the density of interface traps decreases with increasing temperature, at a given gate voltage, more carriers are available for conduction in the channel. This finding also supports previous work conducted in the field [14].

The observed reduction in threshold voltage with temperature is also evident for each of the transistors across the temperature range and values extracted using linear interpolation of the *IDS –VGS* characteristics are summarised in Figure 7. The threshold voltage can be calculated using equation 13:

process HV06

process CR27

process CR25

TH FB B

TH FB B

qN V V

qN V V

7. The threshold voltage can be calculated using equation 13:

2 2 <sup>2</sup> εε φ =++ φ os A B

2 2 <sup>2</sup> εε φ =++ φ os A B

7. The threshold voltage can be calculated using equation 13:

increase in temperature as described previously [20].

increase in temperature as described previously [20].

Figure 7. Variation of MOSFET threshold voltage with temperature

Figure 7. Variation of MOSFET threshold voltage with temperature

i

i

C (13)

C (13)

Figure 3. Schematic cross section of the completed transistor structures

6. Temperature-dependent electrical characteristics of 4H-SiC MOSFETs

7. Temperature-dependent electrical characteristics of n-channel 4H-SiC MOSFETs

N2O post-oxidation anneal that was performed on the dielectric as described in Table 1.

channel. This finding also supports previous work conducted in the field [14].

In the following subsections, the current-voltage characteristics are extracted and explored for the three different dielectric samples (HV06, CR25 and CR27) on both n-channel and p-channel 4H-SiC MOSFETs. This involved the extraction of the field effect mobility µFE, subthreshold slope (SS) and threshold voltage VTH from the measured VGS–IDS characteristics across a temperature range of 298 K to 498 K with 50 K increments in order to understand the effect of the dielectric processing treatment on the MOSFET characteristics. The extracted field effect mobility for each of the samples is also fitted to the theoretical model for mobility using equation 6 in order to predict the mobility-limiting mechanisms for each of the MOSFETs and the impact of temperature on the mobility-limiting mechanisms involved. All of the electrical characteristics discussed in this chapter were extracted using a Keithley 4200 SCS Parameter Analyser.

The data shown in Figures 4, 5 and 6 show the VGS–IDS and VGS-log(IDS) characteristics for a typical 400x1.5 µm n-channel MOSFET for HV06, CR25 and CR27, respectively, measured from 298 K to 498 K. The drain bias in each of the measurements was 500 mV. Each of the samples shows a similar trend and there is an increase in drain current, a reduction in threshold voltage and a change in the subthreshold slope with increasing temperature. The data for HV06 in Figure 4 shows a much higher off-state leakage current, with subthreshold drain currents consistently around 0.1 nA, whereas the data for both CR25 (Figure 5) and CR27 (Figure 6) show reverse leakage current of approximately 1 pA. The off-state conduction could be due to counter doping in the channel region, which could be a product of the thresholdadjust implant [19]. This counter doping could have also been increased as an unwanted effect during the 1200 C to the

The increase in current with temperature observed in Figures 4.a, 5.a and 6.a for the three samples is due to the decrease

traps decreases with increasing temperature, at a given gate voltage, more carriers are available for conduction in the

**Figure 4.** (a) *VGS* –*IDS* and (b) *VGS* -log(*IDS*) characteristics of a 400x1.5 µm n-channel MOSFET as a function of tempera‐ ture for dielectric process HV06 Figure 4. (a) VGS–IDS and (b) VGS-log(IDS) characteristics of a 400x1.5 µm n-channel MOSFET as a function of temperature for dielectric

Figure 5. (a) VGS–IDS and (b) VGS-log(IDS) characteristics of a 400x1.5 µm n-channel MOSFET as a function of temperature for dielectric process CR25 **Figure 5.** (a) *VGS* –*IDS* and (b) *VGS* -log(*IDS*) characteristics of a 400x1.5 µm n-channel MOSFET as a function of tempera‐ ture for dielectric process CR25 Figure 5. (a) VGS–IDS and (b) VGS-log(IDS) characteristics of a 400x1.5 µm n-channel MOSFET as a function of temperature for dielectric

The observed reduction in threshold voltage with temperature is also evident for each of the transistors across the temperature range and values extracted using linear interpolation of the IDS–VGS characteristics are summarised in Figure Figure 6. (a) VGS–IDS and (b) VGS-log(IDS) characteristics of a 400x1.5 µm n-channel MOSFET as a function of temperature for dielectric process CR27 **Figure 6.** (a) *VGS* –*IDS* and (b) *VGS* -log(*IDS*) characteristics of a 400x1.5 µm n-channel MOSFET as a function of tempera‐ ture for dielectric process CR27

The observed reduction in threshold voltage with temperature is also evident for each of the transistors across the temperature range and values extracted using linear interpolation of the IDS–VGS characteristics are summarised in Figure

The observed shift in threshold voltage with temperature is due to the reduction in the surface band bending required for inversion, which is due to the increase in intrinsic carrier concentration and the decrease in band gap energy with an

The observed shift in threshold voltage with temperature is due to the reduction in the surface band bending required for inversion, which is due to the increase in intrinsic carrier concentration and the decrease in band gap energy with an Impact of Dielectric Formation and Processing Techniques on the Operation of 4H-SiC MOSFETs http://dx.doi.org/10.5772/61067 71

$$V\_{TH} = V\_{FB} + 2\phi\_{\text{B}} + \frac{\sqrt{2\varepsilon\_o \varepsilon\_s q N\_A \mathcal{Q} \phi\_{\text{B}}}}{\mathcal{C}\_i} \tag{13}$$

The observed shift in threshold voltage with temperature is due to the reduction in the surface band bending required for inversion, which is due to the increase in intrinsic carrier concen‐ tration and the decrease in band gap energy with an increase in temperature as described previously [20].

**Figure 7.** Variation of MOSFET threshold voltage with temperature

Figure 3. Schematic cross section of the completed transistor structures

6. Temperature-dependent electrical characteristics of 4H-SiC MOSFETs

7. Temperature-dependent electrical characteristics of n-channel 4H-SiC MOSFETs

N2O post-oxidation anneal that was performed on the dielectric as described in Table 1.

channel. This finding also supports previous work conducted in the field [14].

70 Advanced Silicon Carbide Devices and Processing

process HV06

process HV06

process CR25

process CR25

ture for dielectric process CR25

process CR27

process CR27

TH FB B

TH FB B

qN V V

ture for dielectric process CR27

qN V V

7. The threshold voltage can be calculated using equation 13:

2 2 <sup>2</sup> εε φ =++ φ os A B

2 2 <sup>2</sup> εε φ =++ φ os A B

7. The threshold voltage can be calculated using equation 13:

increase in temperature as described previously [20].

increase in temperature as described previously [20].

Figure 7. Variation of MOSFET threshold voltage with temperature

Figure 7. Variation of MOSFET threshold voltage with temperature

i

i

C (13)

C (13)

In the following subsections, the current-voltage characteristics are extracted and explored for the three different dielectric samples (HV06, CR25 and CR27) on both n-channel and p-channel 4H-SiC MOSFETs. This involved the extraction of the field effect mobility µFE, subthreshold slope (SS) and threshold voltage VTH from the measured VGS–IDS characteristics across a temperature range of 298 K to 498 K with 50 K increments in order to understand the effect of the dielectric processing treatment on the MOSFET characteristics. The extracted field effect mobility for each of the samples is also fitted to the theoretical model for mobility using equation 6 in order to predict the mobility-limiting mechanisms for each of the MOSFETs and the impact of temperature on the mobility-limiting mechanisms involved. All of the electrical characteristics discussed in this chapter were extracted using a Keithley 4200 SCS Parameter Analyser.

The data shown in Figures 4, 5 and 6 show the VGS–IDS and VGS-log(IDS) characteristics for a typical 400x1.5 µm n-channel MOSFET for HV06, CR25 and CR27, respectively, measured from 298 K to 498 K. The drain bias in each of the measurements was 500 mV. Each of the samples shows a similar trend and there is an increase in drain current, a reduction in threshold voltage and a change in the subthreshold slope with increasing temperature. The data for HV06 in Figure 4 shows a much higher off-state leakage current, with subthreshold drain currents consistently around 0.1 nA, whereas the data for both CR25 (Figure 5) and CR27 (Figure 6) show reverse leakage current of approximately 1 pA. The off-state conduction could be due to counter doping in the channel region, which could be a product of the thresholdadjust implant [19]. This counter doping could have also been increased as an unwanted effect during the 1200 C to the

The increase in current with temperature observed in Figures 4.a, 5.a and 6.a for the three samples is due to the decrease of occupied interface traps with an increasing temperature, which is an agreement with the density of interface traps data extracted from capacitor test structures fabricated monolithically with the MOSFETs. As the density of interface traps decreases with increasing temperature, at a given gate voltage, more carriers are available for conduction in the

**Figure 4.** (a) *VGS* –*IDS* and (b) *VGS* -log(*IDS*) characteristics of a 400x1.5 µm n-channel MOSFET as a function of tempera‐ ture for dielectric process HV06 Figure 4. (a) VGS–IDS and (b) VGS-log(IDS) characteristics of a 400x1.5 µm n-channel MOSFET as a function of temperature for dielectric

Figure 4. (a) VGS–IDS and (b) VGS-log(IDS) characteristics of a 400x1.5 µm n-channel MOSFET as a function of temperature for dielectric

Figure 5. (a) VGS–IDS and (b) VGS-log(IDS) characteristics of a 400x1.5 µm n-channel MOSFET as a function of temperature for dielectric

Figure 5. (a) VGS–IDS and (b) VGS-log(IDS) characteristics of a 400x1.5 µm n-channel MOSFET as a function of temperature for dielectric

**Figure 5.** (a) *VGS* –*IDS* and (b) *VGS* -log(*IDS*) characteristics of a 400x1.5 µm n-channel MOSFET as a function of tempera‐

Figure 6. (a) VGS–IDS and (b) VGS-log(IDS) characteristics of a 400x1.5 µm n-channel MOSFET as a function of temperature for dielectric

Figure 6. (a) VGS–IDS and (b) VGS-log(IDS) characteristics of a 400x1.5 µm n-channel MOSFET as a function of temperature for dielectric

**Figure 6.** (a) *VGS* –*IDS* and (b) *VGS* -log(*IDS*) characteristics of a 400x1.5 µm n-channel MOSFET as a function of tempera‐

The observed reduction in threshold voltage with temperature is also evident for each of the transistors across the temperature range and values extracted using linear interpolation of the IDS–VGS characteristics are summarised in Figure

The observed reduction in threshold voltage with temperature is also evident for each of the transistors across the temperature range and values extracted using linear interpolation of the IDS–VGS characteristics are summarised in Figure

The observed shift in threshold voltage with temperature is due to the reduction in the surface band bending required for inversion, which is due to the increase in intrinsic carrier concentration and the decrease in band gap energy with an

The observed shift in threshold voltage with temperature is due to the reduction in the surface band bending required for inversion, which is due to the increase in intrinsic carrier concentration and the decrease in band gap energy with an However, a change at the interface and within the depletion layer can also act to modify the gate voltage as *VFB* is dependent on the amount of charge trapped at the silicon carbide–oxide interface, as shown by equation 14:

$$\mathcal{V}\_{FB} = \phi\_{ms} - \frac{\mathcal{Q}\_f + \mathcal{Q}\_m + \mathcal{Q}\_{it}}{\mathcal{C}\_i} \tag{14}$$

where *ϕms* is the metal–semiconductor work function difference.

The data in Figure 8 shows the variation in subthreshold slope (*SS*) as a function of temperature for each of the dielectrics studies. As shown by the data, both HV06 and CR27 show an increase in *SS* with temperature, whereas CR25 shows a decrease in *SS*. An increase in the subthreshold slope with increasing temperature is expected, as *SS* is proportional to *kT* / *q*. The decrease of *SS* with temperature that is witnessed for CR25 suggests that there is a change in the interface trapped charge at the semiconductor dielectric interface as subthreshold slope is also depend‐ ent on the interface trap capacitance (*Cit*) as detailed in equation 15:

$$SS = \ln\left(10\left(\frac{kT}{q}\right)\left(\frac{\mathcal{C}\_i + \mathcal{C}\_D + \mathcal{C}\_{it}}{\mathcal{C}\_i}\right)\right) \tag{15}$$

where *CD* is equal to the capacitance of the depletion region in the semiconductor formed under the oxide layer [21].

**Figure 8.** Variation of extracted subthreshold slope with temperature, for 400x1.5 µm n-channel MOSFETs

This observed in subthreshold slope with temperature is in agreement with the change in interface trap density with temperature that was witnessed in capacitor test structures for both the CR25 n-type and p-type MIS capacitors that were analysed using Terman analysis. This change is most likely due to the change in *Dit* with temperature, which was observed at both the conduction band and valence band edges in the semiconductor for both the n-type and ptype CR25 MIS capacitors, respectively. The data in Figure 9 shows a plot of *Dit* as a function of temperature as extracted from the subthreshold slope of each of the MOSFET devices using equation 15. As can be observed from the data, the change in *Dit* for CR25 is significantly higher than that observed in either HV06 or CR27, decreasing from 3×1012 to 1.5×1012 cm-2 eV-1 between 298 and 498 K.

The data in Figures 10(a), 11(a) and 12(a) show the variation in field effect mobility with electric field *(μFE -E)* for a 400×1.5µm n-channel MOSFET measured between 298 and 498 K taken from samples HV06, CR25 and CR27, respectively. The field effect mobility was extracted from the *VGS –IDS* data sets shown in Figures 4(a), 5(a) and 6(a) by means of equation 2. All data sets exhibit a similar trend, with increasing maximum field effect mobility with increasing Impact of Dielectric Formation and Processing Techniques on the Operation of 4H-SiC MOSFETs http://dx.doi.org/10.5772/61067 73

trapped charge at the semiconductor dielectric interface as subthreshold slope is also depend‐

(10) *i D it*

*q C* æ öæ ö + + <sup>=</sup> ç ÷ç ÷ ç ÷

where *CD* is equal to the capacitance of the depletion region in the semiconductor formed under

è øè ø

*kT CC C SS ln*

**Figure 8.** Variation of extracted subthreshold slope with temperature, for 400x1.5 µm n-channel MOSFETs

This observed in subthreshold slope with temperature is in agreement with the change in interface trap density with temperature that was witnessed in capacitor test structures for both the CR25 n-type and p-type MIS capacitors that were analysed using Terman analysis. This change is most likely due to the change in *Dit* with temperature, which was observed at both the conduction band and valence band edges in the semiconductor for both the n-type and ptype CR25 MIS capacitors, respectively. The data in Figure 9 shows a plot of *Dit* as a function of temperature as extracted from the subthreshold slope of each of the MOSFET devices using equation 15. As can be observed from the data, the change in *Dit* for CR25 is significantly higher than that observed in either HV06 or CR27, decreasing from 3×1012 to 1.5×1012 cm-2 eV-1 between

The data in Figures 10(a), 11(a) and 12(a) show the variation in field effect mobility with electric field *(μFE -E)* for a 400×1.5µm n-channel MOSFET measured between 298 and 498 K taken from samples HV06, CR25 and CR27, respectively. The field effect mobility was extracted from the *VGS –IDS* data sets shown in Figures 4(a), 5(a) and 6(a) by means of equation 2. All data sets exhibit a similar trend, with increasing maximum field effect mobility with increasing

*i*

(15)

ent on the interface trap capacitance (*Cit*) as detailed in equation 15:

the oxide layer [21].

72 Advanced Silicon Carbide Devices and Processing

298 and 498 K.

Figure 9. Variation of extracted interface trap density (Dit) from the subthreshold slope of 400x1.5 µm n-channel MOSFETs The data in Figures 10(a), 11(a) and 12(a) show the variation in field effect mobility with electric field (µFE-E) for a **Figure 9.** Variation of extracted interface trap density (*Dit*) from the subthreshold slope of 400x1.5 µm n-channel MOS‐ FETs

temperature. The data in Figure 12(a) for sample CR27 shows the highest field effect mobility across the temperature range out of the three samples as supported by the data in Figure 16, which shows the peak field effect mobility of each device against temperature. 400×1.5µm n-channel MOSFET measured between 298 and 498 K taken from samples HV06, CR25 and CR27, respectively. The field effect mobility was extracted from the VGS–IDS data sets shown in Figures 4(a), 5(a) and 6(a) by means of equation 2. All data sets exhibit a similar trend, with increasing maximum field effect mobility with increasing temperature. The data in Figure 12(a) for sample CR27 shows the highest field effect mobility across the temperature range out of the three samples as supported by the data in Figure 16, which shows the peak field effect mobility of each

device against temperature.

does, especially for the HV06 data.

Figure 10. (a) µFE-E and (b)µ C-E characteristics of 400x1.5 µm HV06 n-channel MOSFET at different temperatures **Figure 10.** (a) *μFE* -E and (b)*μC*-E characteristics of 400x1.5 µm HV06 n-channel MOSFET at different temperatures

Figures 10(b),11(b) and 12(b) show the Coulomb mobility values that were fitted to the measured characteristics using equation 11. As shown by the data, all of the devices show an increase in Coulomb mobility with increasing temperature, which suggests that the effect of Coulomb scattering reduces with an increase in temperature. The data sets also show that the electric field at which the mobility increases from zero (the λ parameter in equation 12) does not show a significant variation with temperature; however, the Φ term used to describe the change in mobility with electric field does, especially for the HV06 data.

Figure 11. (a) µFE-E and (b) µC-E characteristics of 400x1.5 µm CR25 n-channel MOSFET at different temperatures

Figure 12. (a) µFE-E and (b)µ C-E characteristics of 400x1.5 µm CR27 n-channel MOSFET at different temperatures

Figures 10(b), 11(b) and 12(b) show the Coulomb mobility values that were fitted to the measured characteristics using equation 11. As shown by the data, all of the devices show an increase in Coulomb mobility with increasing temperature, which suggests that the effect of Coulomb scattering reduces with an increase in temperature. The data sets also show that the electric field at which the mobility increases from zero (the λ parameter in equation 12) does not show a significant variation with temperature; however, the Φ term used to describe the change in mobility with electric field device against temperature.

device against temperature.

Figure 10. (a) µFE-E and (b)µ C-E characteristics of 400x1.5 µm HV06 n-channel MOSFET at different temperatures

Figure 9. Variation of extracted interface trap density (Dit) from the subthreshold slope of 400x1.5 µm n-channel MOSFETs

Figure 9. Variation of extracted interface trap density (Dit) from the subthreshold slope of 400x1.5 µm n-channel MOSFETs

The data in Figures 10(a), 11(a) and 12(a) show the variation in field effect mobility with electric field (µFE-E) for a 400×1.5µm n-channel MOSFET measured between 298 and 498 K taken from samples HV06, CR25 and CR27, respectively. The field effect mobility was extracted from the VGS–IDS data sets shown in Figures 4(a), 5(a) and 6(a) by means of equation 2. All data sets exhibit a similar trend, with increasing maximum field effect mobility with increasing temperature. The data in Figure 12(a) for sample CR27 shows the highest field effect mobility across the temperature range out of the three samples as supported by the data in Figure 16, which shows the peak field effect mobility of each

The data in Figures 10(a), 11(a) and 12(a) show the variation in field effect mobility with electric field (µFE-E) for a 400×1.5µm n-channel MOSFET measured between 298 and 498 K taken from samples HV06, CR25 and CR27, respectively. The field effect mobility was extracted from the VGS–IDS data sets shown in Figures 4(a), 5(a) and 6(a) by means of equation 2. All data sets exhibit a similar trend, with increasing maximum field effect mobility with increasing temperature. The data in Figure 12(a) for sample CR27 shows the highest field effect mobility across the temperature range out of the three samples as supported by the data in Figure 16, which shows the peak field effect mobility of each

Figure 11. (a) µFE-E and (b) µC-E characteristics of 400x1.5 µm CR25 n-channel MOSFET at different temperatures **Figure 11.** (a) *μFE* -E and (b) *μC* -E characteristics of 400x1.5 µm CR25 n-channel MOSFET at different temperatures

Figure 11. (a) µFE-E and (b) µC-E characteristics of 400x1.5 µm CR25 n-channel MOSFET at different temperatures

Figures 10(b), 11(b) and 12(b) show the Coulomb mobility values that were fitted to the measured characteristics using Figure 12. (a) µFE-E and (b)µ C-E characteristics of 400x1.5 µm CR27 n-channel MOSFET at different temperatures **Figure 12.** (a) *μFE* -E and (b)µ C-E characteristics of 400x1.5 µm CR27 n-channel MOSFET at different temperatures

equation 11. As shown by the data, all of the devices show an increase in Coulomb mobility with increasing temperature, which suggests that the effect of Coulomb scattering reduces with an increase in temperature. The data sets also show

Figures 10(b), 11(b) and 12(b) show the Coulomb mobility values that were fitted to the measured characteristics using

**Figure 13.** Surface roughness mobility (*μSR*) as a function of electric field for 400×1.5 µm n-channel MOSFETs at 298 K

At high electric fields, the extracted values of *μFE* for each of the devices is severely limited by surface roughness scattering as shown by the data in Figures 10(a), 11(a) and 12(a). The data in Figure 13 shows the extracted *μSR* as a function of electric field for each of the samples at 298 K. This clearly identifies that the observed surface roughness mobility varies dependent on the dielectric under investigation. HV06 and CR27 show the lowest surface roughness mobility, which suggests that surface roughness scattering is higher within those devices. CR25 shows the highest surface roughness mobility, which suggests that the process techniques used in the fabrication of this sample produce the highest quality dielectric-semiconductor interface out of the 3 samples investigated. The data in Figures 14(a), 14(b) and 14(c) show the values of *μSR* fitted to each of the extracted MOSFET *μFE* characteristics between 298 and 498 K. The negligible temperature dependence observed in the high field regime for all three of the devices supports previously reported observations on 4H-SiC MOSFETs and shows that the experi‐ mental *μSR* has the same functional form as equation 10. Figure 13. Surface roughness mobility (µSR) as a function of electric field for 400×1.5 µm n-channel MOSFETs at 298 K At high electric fields, the extracted values of µFE for each of the devices is severely limited by surface roughness scattering as shown by the data in Figures 10(a), 11(a) and 12(a). The data in Figure 13 shows the extracted µSR as a function of electric field for each of the samples at 298 K. This clearly identifies that the observed surface roughness mobility varies dependent on the dielectric under investigation. HV06 and CR27 show the lowest surface roughness mobility, which suggests that surface roughness scattering is higher within those devices. CR25 shows the highest surface roughness mobility, which suggests that the process techniques used in the fabrication of this sample produce the highest quality dielectric-semiconductor interface out of the 3 samples investigated. The data in Figures 14(a), 14(b) and 14(c) show the values of µSR fitted to each of the extracted MOSFET µFE characteristics between 298 and 498 K. The negligible temperature dependence observed in the high field regime for all three of the devices supports previously reported observations on 4H-SiC MOSFETs and shows that the experimental µSR has the same functional form as

equation 10.

Figure 14. µSR-E characteristics of a 400×1.5 µm n-channel MOSFET from (a) HV06, (b) CR25 and (c) CR27 samples **Figure 14.** *μSR* -E characteristics of a 400×1.5 µm n-channel MOSFET from (a) HV06, (b) CR25 and (c) CR27 samples

The data shown in Figure 15 shows the theoretical acoustic phonon mobility (µAC) fitted to each sample using equation 9.

The values of the fitting parameters were identical for each of the samples studied, for both n-channel and p-channel devices, and were based on values reported in the literature [5, 8]. The value of B is 1.0×10<sup>6</sup>cm⋅s-1, C is 3.23×10<sup>6</sup>K⋅cm⋅s-1 and α is 0.0284. As shown by the data in Figure 15, the modelled acoustic phonon mobility is consistently above 150 cm<sup>2</sup>⋅V-1⋅s-1 across the entire investigated electric field and temperature range. As this is significantly higher than both µSR and µC, it has a negligible effect on the experimentally measured field effect mobility in each of the devices. The experimentally determined characteristics are consistently dominated at low and high electric fields by Coulomb and surface roughness scattering, respectively, as shown by the data in Figures 10(a), 11(a), 12(a) and 14. The data shown in Figure 15 shows the theoretical acoustic phonon mobility *(μAC)* fitted to each sample using equation 9. The values of the fitting parameters were identical for each of the samples studied, for both n-channel and p-channel devices, and were based on values reported in the literature [5, 8]. The value of *B* is 1.0×106 cm s-1, C is 3.23×106 K cm s-1 and α is 0.0284. As shown by the data in Figure 15, the modelled acoustic phonon mobility is consistently above 150 cm2 V-1 s-1 across the entire investigated electric field and temperature range. As this is significantly higher than both *μSR* and *μC,* it has a negligible effect on the experimentally measured field effect mobility in each of the devices. The experimentally determined charac‐ teristics are consistently dominated at low and high electric fields by Coulomb and surface roughness scattering, respectively, as shown by the data in Figures 10(a), 11(a), 12(a) and 14.

Figure 15. Predicted µAC-E characteristics of a 400×1.5 µm n-channel MOSFET The data in Figure 16 shows the variation in the peak field effect mobility with temperature for the three dielectrics studies. It is apparent that sample HV06 consistently shows the lowest channel mobility, whilst CR27 shows the most significant variation with temperature, giving the highest mobility at temperatures above 350 K. The main limiting factor that is witnessed across all of the samples is that of severely low surface roughness mobility, which acts to dominate the device mobility characteristics from electric fields above 1 MV cm-1. The extracted surface roughness mobility reported here for all three dielectric processes is approximately an order of magnitude lower than other 4H-SiC MOSFETs that have previously been reported,

**Figure 13.** Surface roughness mobility (*μSR*) as a function of electric field for 400×1.5 µm n-channel MOSFETs at 298 K

Figure 9. Variation of extracted interface trap density (Dit) from the subthreshold slope of 400x1.5 µm n-channel MOSFETs

Figure 9. Variation of extracted interface trap density (Dit) from the subthreshold slope of 400x1.5 µm n-channel MOSFETs

Figure 10. (a) µFE-E and (b)µ C-E characteristics of 400x1.5 µm HV06 n-channel MOSFET at different temperatures

Figure 10. (a) µFE-E and (b)µ C-E characteristics of 400x1.5 µm HV06 n-channel MOSFET at different temperatures

Figure 11. (a) µFE-E and (b) µC-E characteristics of 400x1.5 µm CR25 n-channel MOSFET at different temperatures

Figure 11. (a) µFE-E and (b) µC-E characteristics of 400x1.5 µm CR25 n-channel MOSFET at different temperatures

**Figure 11.** (a) *μFE* -E and (b) *μC* -E characteristics of 400x1.5 µm CR25 n-channel MOSFET at different temperatures

Figure 12. (a) µFE-E and (b)µ C-E characteristics of 400x1.5 µm CR27 n-channel MOSFET at different temperatures

Figure 12. (a) µFE-E and (b)µ C-E characteristics of 400x1.5 µm CR27 n-channel MOSFET at different temperatures

Figures 10(b), 11(b) and 12(b) show the Coulomb mobility values that were fitted to the measured characteristics using equation 11. As shown by the data, all of the devices show an increase in Coulomb mobility with increasing temperature, which suggests that the effect of Coulomb scattering reduces with an increase in temperature. The data sets also show that the electric field at which the mobility increases from zero (the λ parameter in equation 12) does not show a significant variation with temperature; however, the Φ term used to describe the change in mobility with electric field

**Figure 12.** (a) *μFE* -E and (b)µ C-E characteristics of 400x1.5 µm CR27 n-channel MOSFET at different temperatures

Figures 10(b), 11(b) and 12(b) show the Coulomb mobility values that were fitted to the measured characteristics using equation 11. As shown by the data, all of the devices show an increase in Coulomb mobility with increasing temperature, which suggests that the effect of Coulomb scattering reduces with an increase in temperature. The data sets also show that the electric field at which the mobility increases from zero (the λ parameter in equation 12) does not show a significant variation with temperature; however, the Φ term used to describe the change in mobility with electric field

device against temperature.

74 Advanced Silicon Carbide Devices and Processing

device against temperature.

does, especially for the HV06 data.

does, especially for the HV06 data.

The data in Figures 10(a), 11(a) and 12(a) show the variation in field effect mobility with electric field (µFE-E) for a 400×1.5µm n-channel MOSFET measured between 298 and 498 K taken from samples HV06, CR25 and CR27, respectively. The field effect mobility was extracted from the VGS–IDS data sets shown in Figures 4(a), 5(a) and 6(a) by means of equation 2. All data sets exhibit a similar trend, with increasing maximum field effect mobility with increasing temperature. The data in Figure 12(a) for sample CR27 shows the highest field effect mobility across the temperature range out of the three samples as supported by the data in Figure 16, which shows the peak field effect mobility of each

The data in Figures 10(a), 11(a) and 12(a) show the variation in field effect mobility with electric field (µFE-E) for a 400×1.5µm n-channel MOSFET measured between 298 and 498 K taken from samples HV06, CR25 and CR27, respectively. The field effect mobility was extracted from the VGS–IDS data sets shown in Figures 4(a), 5(a) and 6(a) by means of equation 2. All data sets exhibit a similar trend, with increasing maximum field effect mobility with increasing temperature. The data in Figure 12(a) for sample CR27 shows the highest field effect mobility across the temperature range out of the three samples as supported by the data in Figure 16, which shows the peak field effect mobility of each

**Figure 15.** Predicted *μAC* -E characteristics of a 400×1.5 µm n-channel MOSFET

which showed field effect mobility of consistently over 20 cm2 V-1 s-1 at high electric fields [8, 22-25].

**Figure 16.** Variation of peak field effect mobility (*μFE*) with temperature for a 400×1.5 µm n-channel MOSFET

The data in Table 2 shows the fitting parameters used to generate the mobility plots for the nchannel FETs reported here.

Impact of Dielectric Formation and Processing Techniques on the Operation of 4H-SiC MOSFETs http://dx.doi.org/10.5772/61067 77


which showed field effect mobility of consistently over 20 cm2

**Figure 15.** Predicted *μAC* -E characteristics of a 400×1.5 µm n-channel MOSFET

76 Advanced Silicon Carbide Devices and Processing

**Figure 16.** Variation of peak field effect mobility (*μFE*) with temperature for a 400×1.5 µm n-channel MOSFET

The data in Table 2 shows the fitting parameters used to generate the mobility plots for the n-

22-25].

channel FETs reported here.

V-1 s-1 at high electric fields [8,

**Table 2.** Fitting parameters to the mobility models used to describe the behaviour of n-channel MOSFET structures

### **8. Temperature-dependent electrical characteristics of p-channel 4H-SiC MOSFETs**

The data in Figures 17, 18 and 19 show the *VGS –IDS* and *VGS -log(IDS)* characteristics for a 1600×1.5 µm p-channel MOSFET from the HV06 sample and an 8000×1.5 µm CR25 and CR27 p-channel MOSFET, respectively, measured from 298 to 498 K. The drain bias in each of the measurements was 500 mV. The data for each of the samples exhibits a similar trend, showing an increase in drain current with increasing temperature, a change in threshold voltage and a change in the subthreshold slope across the measured temperature range. In contrast to the n-channel data shown in Figures 4(b), 5(b) and 6(b), all p-channel samples exhibit a very low reverse leakage current of below 1 pA as shown in Figures 17(b), 18(b) and 19(b).

charge present within the dielectric.

charge present within the dielectric.

charge present within the dielectric.

Figure 17. (a) VGS–IDS and (b) VGS-log(IDS) characteristics of a 1600×1.5 µm p-channel MOSFET from sample HV06 **Figure 17.** (a) *VGS* –*IDS* and (b) *VGS* -log(*IDS*) characteristics of a 1600×1.5 µm p-channel MOSFET from sample HV06

Figure 17. (a) VGS–IDS and (b) VGS-log(IDS) characteristics of a 1600×1.5 µm p-channel MOSFET from sample HV06

Figure 18. (a) VGS–IDS and (b) VGS-log(IDS) characteristics of an 8000×1.5 µm p-channel MOSFET from sample CR25 **Figure 18.** (a) *VGS* –*IDS* and (b) *VGS* -log(*IDS*) characteristics of an 8000×1.5 µm p-channel MOSFET from sample CR25

Figure 18. (a) VGS–IDS and (b) VGS-log(IDS) characteristics of an 8000×1.5 µm p-channel MOSFET from sample CR25

channel devices, CR27 shows a reduction (i.e. becoming closer to zero) in VTH with increasing temperature due to the reduction in the surface band bending required for inversion. This observation is identical to that observed in the nby the data in Figure 20. The threshold voltage of a MOSFET can be calculated using equation 13 [21], and as with the n-Figure 19. (a) VGS–IDS and (b) VGS-log(IDS) characteristics of an 8000×1.5 µm p-channel MOSFET from sample CR27 **Figure 19.** (a) *VGS* –*IDS* and (b) *VGS* -log(*IDS*) characteristics of an 8000×1.5 µm p-channel MOSFET from sample CR27

channel data and is due to the increase in intrinsic carrier concentration and the decrease in band gap energy with increasing temperature. The data for HV06 shows a minimal change in VTH with increasing temperature. However, in contrast, the data for CR25 shows an increase in VTH with temperature. This could be due to a change in the interfacial charge or a change in the charge within the depletion layer, which can also act to modify the gate voltage as VFB is dependent on the charge trapped at the silicon carbide–oxide interface. This is likely to be due to the increase in Dit with reduction in the surface band bending required for inversion. This observation is identical to that observed in the nchannel data and is due to the increase in intrinsic carrier concentration and the decrease in band gap energy with increasing temperature. The data for HV06 shows a minimal change in VTH with increasing temperature. However, in contrast, the data for CR25 shows an increase in VTH with temperature. This could be due to a change in the interfacial charge or a change in the charge within the depletion layer, which can also act to modify the gate voltage as VFB is The change in threshold voltage with temperature is also shown for each of the transistors across the temperature range by the data in Figure 20. The threshold voltage of a MOSFET can be calculated using equation 13 [21], and as with the nchannel devices, CR27 shows a reduction (i.e. becoming closer to zero) in VTH with increasing temperature due to the reduction in the surface band bending required for inversion. This observation is identical to that observed in the nchannel data and is due to the increase in intrinsic carrier concentration and the decrease in band gap energy with increasing temperature. The data for HV06 shows a minimal change in VTH with increasing temperature. However, in The change in threshold voltage with temperature is also shown for each of the transistors across the temperature range by the data in Figure 20. The threshold voltage of a MOSFET can be calculated using equation 13 [21], and as with the n-channel devices, CR27 shows a reduction (i.e. becoming closer to zero) in *VTH* with increasing temperature due to the reduction

temperature that was witnessed in monolithically fabricated MOS capacitor structures and the effects of mobile oxide

contrast, the data for CR25 shows an increase in VTH with temperature. This could be due to a change in the interfacial charge or a change in the charge within the depletion layer, which can also act to modify the gate voltage as VFB is dependent on the charge trapped at the silicon carbide–oxide interface. This is likely to be due to the increase in Dit with temperature that was witnessed in monolithically fabricated MOS capacitor structures and the effects of mobile oxide

dependent on the charge trapped at the silicon carbide–oxide interface. This is likely to be due to the increase in Dit with temperature that was witnessed in monolithically fabricated MOS capacitor structures and the effects of mobile oxide

by the data in Figure 20. The threshold voltage of a MOSFET can be calculated using equation 13 [21], and as with the n-

The change in threshold voltage with temperature is also shown for each of the transistors across the temperature range

channel devices, CR27 shows a reduction (i.e. becoming closer to zero) in VTH with increasing temperature due to the

in the surface band bending required for inversion. This observation is identical to that observed in the n-channel data and is due to the increase in intrinsic carrier concentration and the decrease in band gap energy with increasing temperature. The data for HV06 shows a minimal change in *VTH* with increasing temperature. However, in contrast, the data for CR25 shows an increase in *VTH* with temperature. This could be due to a change in the interfacial charge or a change in the charge within the depletion layer, which can also act to modify the gate voltage as *VFB* is dependent on the charge trapped at the silicon carbide–oxide interface. This is likely to be due to the increase in *Dit* with temperature that was witnessed in mono‐ lithically fabricated MOS capacitor structures and the effects of mobile oxide charge present within the dielectric.

**Figure 20.** Threshold voltage as a function of temperature for 1.5 µm gate length p-channel MOSFETs

Figure 17. (a) VGS–IDS and (b) VGS-log(IDS) characteristics of a 1600×1.5 µm p-channel MOSFET from sample HV06

Figure 17. (a) VGS–IDS and (b) VGS-log(IDS) characteristics of a 1600×1.5 µm p-channel MOSFET from sample HV06

Figure 17. (a) VGS–IDS and (b) VGS-log(IDS) characteristics of a 1600×1.5 µm p-channel MOSFET from sample HV06

**Figure 17.** (a) *VGS* –*IDS* and (b) *VGS* -log(*IDS*) characteristics of a 1600×1.5 µm p-channel MOSFET from sample HV06

Figure 18. (a) VGS–IDS and (b) VGS-log(IDS) characteristics of an 8000×1.5 µm p-channel MOSFET from sample CR25

Figure 18. (a) VGS–IDS and (b) VGS-log(IDS) characteristics of an 8000×1.5 µm p-channel MOSFET from sample CR25

Figure 18. (a) VGS–IDS and (b) VGS-log(IDS) characteristics of an 8000×1.5 µm p-channel MOSFET from sample CR25

**Figure 18.** (a) *VGS* –*IDS* and (b) *VGS* -log(*IDS*) characteristics of an 8000×1.5 µm p-channel MOSFET from sample CR25

Figure 19. (a) VGS–IDS and (b) VGS-log(IDS) characteristics of an 8000×1.5 µm p-channel MOSFET from sample CR27

Figure 19. (a) VGS–IDS and (b) VGS-log(IDS) characteristics of an 8000×1.5 µm p-channel MOSFET from sample CR27

Figure 19. (a) VGS–IDS and (b) VGS-log(IDS) characteristics of an 8000×1.5 µm p-channel MOSFET from sample CR27

**Figure 19.** (a) *VGS* –*IDS* and (b) *VGS* -log(*IDS*) characteristics of an 8000×1.5 µm p-channel MOSFET from sample CR27

The change in threshold voltage with temperature is also shown for each of the transistors across the temperature range by the data in Figure 20. The threshold voltage of a MOSFET can be calculated using equation 13 [21], and as with the n-channel devices, CR27 shows a reduction (i.e. becoming closer to zero) in *VTH* with increasing temperature due to the reduction

charge present within the dielectric.

78 Advanced Silicon Carbide Devices and Processing

charge present within the dielectric.

charge present within the dielectric.

The change in threshold voltage with temperature is also shown for each of the transistors across the temperature range by the data in Figure 20. The threshold voltage of a MOSFET can be calculated using equation 13 [21], and as with the nchannel devices, CR27 shows a reduction (i.e. becoming closer to zero) in VTH with increasing temperature due to the reduction in the surface band bending required for inversion. This observation is identical to that observed in the nchannel data and is due to the increase in intrinsic carrier concentration and the decrease in band gap energy with increasing temperature. The data for HV06 shows a minimal change in VTH with increasing temperature. However, in contrast, the data for CR25 shows an increase in VTH with temperature. This could be due to a change in the interfacial charge or a change in the charge within the depletion layer, which can also act to modify the gate voltage as VFB is dependent on the charge trapped at the silicon carbide–oxide interface. This is likely to be due to the increase in Dit with temperature that was witnessed in monolithically fabricated MOS capacitor structures and the effects of mobile oxide

The change in threshold voltage with temperature is also shown for each of the transistors across the temperature range by the data in Figure 20. The threshold voltage of a MOSFET can be calculated using equation 13 [21], and as with the nchannel devices, CR27 shows a reduction (i.e. becoming closer to zero) in VTH with increasing temperature due to the reduction in the surface band bending required for inversion. This observation is identical to that observed in the nchannel data and is due to the increase in intrinsic carrier concentration and the decrease in band gap energy with increasing temperature. The data for HV06 shows a minimal change in VTH with increasing temperature. However, in contrast, the data for CR25 shows an increase in VTH with temperature. This could be due to a change in the interfacial charge or a change in the charge within the depletion layer, which can also act to modify the gate voltage as VFB is dependent on the charge trapped at the silicon carbide–oxide interface. This is likely to be due to the increase in Dit with temperature that was witnessed in monolithically fabricated MOS capacitor structures and the effects of mobile oxide

The change in threshold voltage with temperature is also shown for each of the transistors across the temperature range by the data in Figure 20. The threshold voltage of a MOSFET can be calculated using equation 13 [21], and as with the nchannel devices, CR27 shows a reduction (i.e. becoming closer to zero) in VTH with increasing temperature due to the reduction in the surface band bending required for inversion. This observation is identical to that observed in the nchannel data and is due to the increase in intrinsic carrier concentration and the decrease in band gap energy with increasing temperature. The data for HV06 shows a minimal change in VTH with increasing temperature. However, in contrast, the data for CR25 shows an increase in VTH with temperature. This could be due to a change in the interfacial charge or a change in the charge within the depletion layer, which can also act to modify the gate voltage as VFB is dependent on the charge trapped at the silicon carbide–oxide interface. This is likely to be due to the increase in Dit with temperature that was witnessed in monolithically fabricated MOS capacitor structures and the effects of mobile oxide The increase in current with temperature that can be observed from the data shown in Figures 17(a), 18(a) and 19(a) for the three dielectrics studied is due to the decrease of occupied interface traps with an increase in temperature, which is an agreement with *Dit* values extracted from capacitor-based test structures fabricated monolithically with the MOSFETs. As the density of interface traps *(Dit)* decreases with increasing temperature, at a given gate voltage, more carriers are available for conduction in the MOSFET channel, as observed in previous reports in the literature [14].

The data in Figure 21 shows the variation in subthreshold slope (*SS*) with temperature for each of the samples. As shown, all three samples show an increase in *SS* with temperature. An increase in *SS* with temperature is expected, since *SS* is proportional to *kT* / *q*. The variation in *SS* with temperature is also influenced by the density of interface trapped charge *(Dit)* at the silicon carbide–oxide interface as *SS* is also dependent on the interface trap capacitance *(Cit)* as outlined in equation 14. This is in agreement with the trend witnessed for the equivalent nchannel MOSFET samples with the exception of sample CR25. The n-channel equivalent sample for CR25 showed a decrease in *SS* with temperature, whereas the p-channel device exhibits an increase in *SS* for increasing temperature, and the observed change is much smaller than that of the n-channel device. This is related to the experimentally measured variation in *Dit* over the measured temperature range on monolithically fabricated capacitor test structures.

**Figure 21.** Subthreshold slope as a function of temperature for 1.5 µm gate length p-channel MOSFETs

The data shown in Figures 22, 23 and 24 show the variation of *μFE -E* and the *μC -E* characteristics for the 1.5 µm gate length p-channel MOSFETs on HV06 and CR25 and CR27, respectively, measured from 298 to 498 K. The data sets for all three dielectrics show evidence of an increase in field effect mobility with increasing temperature, and the data for CR27 in Figure 24 shows the highest field effect mobility out of the three samples across the temperature range studied.

**Figure 22.** (a) *μFE* -E and (b) *μC* -E characteristics of a 1600×1.5 µm p-channel MOSFET from sample HV06

Figure 22. (a) µFE-E and (b) µC-E characteristics of a 1600×1.5 µm p-channel MOSFET from sample HV06

Figure 23. (a) µFE-E and (b) µC-E characteristics of an 8000×1.5 µm p-channel MOSFET from sample CR25

Figure 24. (a) µFE-E and (b) µC-E characteristics of an 8000×1.5 µm p-channel MOSFET from sample CR27

Figure 25, which shows the peak field effect mobility of each device against temperature.

The data in Figures 22, 23 and 24 show the µFE-E and µC-E characteristics for 1.5 µm p-channel MOSFETs on HV06, CR25 and CR27 extracted from experimental VGS–IDS measurements taken at temperatures between 298 and 498 K that are shown in Figures 17, 18 and 19 using equation 2. All devices studied exhibit a similar trend and show an increase in field effect mobility with increasing temperature. The field effect mobility data for CR27 shown in Figure 24 demonstrates the highest field effect mobility across the temperature range out of the three samples, as supported by the data shown in

Impact of Dielectric Formation and Processing Techniques on the Operation of 4H-SiC MOSFETs http://dx.doi.org/10.5772/61067 81

Figure 23. (a) µFE-E and (b) µC-E characteristics of an 8000×1.5 µm p-channel MOSFET from sample CR25 **Figure 23.** (a) *μFE* -E and (b) *μC* -E characteristics of an 8000×1.5 µm p-channel MOSFET from sample CR25

Figure 23. (a) µFE-E and (b) µC-E characteristics of an 8000×1.5 µm p-channel MOSFET from sample CR25

Figure 22. (a) µFE-E and (b) µC-E characteristics of a 1600×1.5 µm p-channel MOSFET from sample HV06

sample for CR25 showed a decrease in *SS* with temperature, whereas the p-channel device exhibits an increase in *SS* for increasing temperature, and the observed change is much smaller than that of the n-channel device. This is related to the experimentally measured variation in *Dit* over the measured temperature range on monolithically fabricated capacitor test structures.

80 Advanced Silicon Carbide Devices and Processing

**Figure 21.** Subthreshold slope as a function of temperature for 1.5 µm gate length p-channel MOSFETs

Figure 22. (a) µFE-E and (b) µC-E characteristics of a 1600×1.5 µm p-channel MOSFET from sample HV06

**Figure 22.** (a) *μFE* -E and (b) *μC* -E characteristics of a 1600×1.5 µm p-channel MOSFET from sample HV06

Figure 23. (a) µFE-E and (b) µC-E characteristics of an 8000×1.5 µm p-channel MOSFET from sample CR25

Figure 24. (a) µFE-E and (b) µC-E characteristics of an 8000×1.5 µm p-channel MOSFET from sample CR27

Figure 25, which shows the peak field effect mobility of each device against temperature.

The data in Figures 22, 23 and 24 show the µFE-E and µC-E characteristics for 1.5 µm p-channel MOSFETs on HV06, CR25 and CR27 extracted from experimental VGS–IDS measurements taken at temperatures between 298 and 498 K that are shown in Figures 17, 18 and 19 using equation 2. All devices studied exhibit a similar trend and show an increase in field effect mobility with increasing temperature. The field effect mobility data for CR27 shown in Figure 24 demonstrates the highest field effect mobility across the temperature range out of the three samples, as supported by the data shown in

The data shown in Figures 22, 23 and 24 show the variation of *μFE -E* and the *μC -E* characteristics for the 1.5 µm gate length p-channel MOSFETs on HV06 and CR25 and CR27, respectively, measured from 298 to 498 K. The data sets for all three dielectrics show evidence of an increase in field effect mobility with increasing temperature, and the data for CR27 in Figure 24 shows the highest field effect mobility out of the three samples across the temperature range studied.

The data in Figures 22, 23 and 24 show the µFE-E and µC-E characteristics for 1.5 µm p-channel MOSFETs on HV06, CR25

shown in Figures 17, 18 and 19 using equation 2. All devices studied exhibit a similar trend and show an increase in field

The data in Figures 22, 23 and 24 show the µFE-E and µC-E characteristics for 1.5 µm p-channel MOSFETs on HV06, CR25

and CR27 extracted from experimental VGS–IDS measurements taken at temperatures between 298 and 498 K that are Figure 24. (a) µFE-E and (b) µC-E characteristics of an 8000×1.5 µm p-channel MOSFET from sample CR27 **Figure 24.** (a) *μFE* -E and (b) *μC* -E characteristics of an 8000×1.5 µm p-channel MOSFET from sample CR27

effect mobility with increasing temperature. The field effect mobility data for CR27 shown in Figure 24 demonstrates the highest field effect mobility across the temperature range out of the three samples, as supported by the data shown in Figure 25, which shows the peak field effect mobility of each device against temperature. and CR27 extracted from experimental VGS–IDS measurements taken at temperatures between 298 and 498 K that are shown in Figures 17, 18 and 19 using equation 2. All devices studied exhibit a similar trend and show an increase in field effect mobility with increasing temperature. The field effect mobility data for CR27 shown in Figure 24 demonstrates the highest field effect mobility across the temperature range out of the three samples, as supported by the data shown in Figure 25, which shows the peak field effect mobility of each device against temperature. The data in Figures 22, 23 and 24 show the *μFE -E* and *μC* -E characteristics for 1.5 µm p-channel MOSFETs on HV06, CR25 and CR27 extracted from experimental *VGS –IDS* measurements taken at temperatures between 298 and 498 K that are shown in Figures 17, 18 and 19 using equation 2. All devices studied exhibit a similar trend and show an increase in field effect mobility with increasing temperature. The field effect mobility data for CR27 shown in Figure 24 demon‐ strates the highest field effect mobility across the temperature range out of the three samples, as supported by the data shown in Figure 25, which shows the peak field effect mobility of each device against temperature.

The data in Figures 22(b), 23(b) and 24(b) show the Coulomb mobility mechanism that was fitted to the measured characteristics using equation 11. As shown by the data in the figures, all of the devices (HV06, CR25 and CR27) show an increase in mobility with increasing temperature, which suggests that the effect of Coulomb scattering reduces with increasing temperature due to the reduction of interface trapping effects with increasing temperature. The same phenomenon was also witnessed in the equivalent n-channel MOSFETs, which suggest that the dominant mobility mechanisms are dominated by the processing of the gate dielectric for both the n- and p-channel devices.

**Figure 25.** Peak field effect mobility (*μFE)* as a function of temperature for 1.5 µm gate length p-channel MOSFETs

**Figure 26.** *μSR* -E characteristics of a 1600 x 1.5 µm HV06 and an 8000 x 1.5 µm CR25 and CR27 p-channel MOSFET at 298 K

At high electric fields, the extracted *μFE* for each of the devices is limited by surface roughness scattering as shown by the data in Figures 26 and 27, where the predicted *μSR* mobility fits to each of the extracted MOSFET *μFE* characteristics between 298 and 498 K. A negligible tem‐ perature dependence is exhibited by all three devices, which supports previous analysis performed on 4H-SiC MOSFETs and shows that the experimentally extracted *μSR* characteris‐ tics have the same functional form as expressed in equation 10 [5]. The data in Figure 26 shows the variation of the fitted surface roughness *(μSR)* as a function of electric field for each of the samples as 298 K. The data clearly identifies that the surface roughness mobility is different for each of the dielectrics under investigation. HV06 shows the highest surface roughness mobility, which suggests that surface roughness scattering is lower within the device and produces the highest quality dielectric–semiconductor interface out of the three samples investigated. The data for samples CR25 and CR27 show an almost identical surface roughness mobility across the measured electric field range, which suggests that the process techniques used in the fabrication of those samples produce a very similar quality of interface. However, all of the devices show very low field effect mobility at high electric fields, which is lower than recently reported values for 4H-SiC devices, such as those summarised in Table 4.

**Figure 27.** *μSR* -E characteristics of a 1600 x 1.5 µm (a) HV06 and an 8000 x 1.5 µm (b) CR25 and (c) CR27 p-channel MOSFET from 298 to 498 K

The data in Table 3 shows the fitting parameters used to generate the mobility plots for the pchannel FETs reported here.

This indicates that there is something common to all three dielectric processes that consistently act to reduce the surface roughness mobility. This could be due to the topography of the 4H-SiC epitaxial layer that was used for the fabrication of the devices or could potentially be a contribution of surface damage due to the ion implantation doping or the post-implantation anneal process that was used to form the n-type regions that are employed across all of the pchannel devices. In order to establish if this is the true cause, an investigation of the surface morphology using a technique such as atomic force microscopy is required, with measure‐ ments performed after the implantation and anneal process to measure the surface roughness, which could then be correlated to the measured electrical characteristics of the devices. A limited amount of data is available from a similar study conducted on n-channel 4H-SiC MOSFETs to establish the impact of the morphological and electrical properties of the SiO2– 4H-SiC interface on the mobility behaviour of 4H-SiC MOSFETs. The results indicated that a higher mobility can be observed in devices with a larger root-mean-square (RMS) roughness of the channel surface, possibly due to lower values of *Dit* associated to faceted surface morphologies [26]. However, this limited data contradicts observations made on other semiconductor systems, such as silicon and silicon-germanium. However, in the case of silicon carbide, evidence indicates a strong dependence between carrier mobility and the crystal surface from which the device is fabricated [27].

**Figure 26.** *μSR* -E characteristics of a 1600 x 1.5 µm HV06 and an 8000 x 1.5 µm CR25 and CR27 p-channel MOSFET at

**Figure 25.** Peak field effect mobility (*μFE)* as a function of temperature for 1.5 µm gate length p-channel MOSFETs

At high electric fields, the extracted *μFE* for each of the devices is limited by surface roughness scattering as shown by the data in Figures 26 and 27, where the predicted *μSR* mobility fits to each of the extracted MOSFET *μFE* characteristics between 298 and 498 K. A negligible tem‐ perature dependence is exhibited by all three devices, which supports previous analysis performed on 4H-SiC MOSFETs and shows that the experimentally extracted *μSR* characteris‐ tics have the same functional form as expressed in equation 10 [5]. The data in Figure 26 shows the variation of the fitted surface roughness *(μSR)* as a function of electric field for each of the

298 K

82 Advanced Silicon Carbide Devices and Processing


**Table 3.** Fitting parameters to the mobility models used to describe the behaviour of p-channel MOSFET structures

The data in Figure 28 shows the predicted values for the mobility limited by acoustic phonon scattering *(μAC)* based on equation 9. The parameters used to generate the values for *μAC* are identical to those used in the n-channel devices reported in a previous section and have been taken from the literature [5,8]; B is 1.0×106 cm s-1, C is 3.23×106 K cm s-1 and α is 0.0284. As shown by the data in Figure 28, the modelled acoustic phonon mobility is consistently above 150 cm2 V-1 s-1 for electric fields below 3.5MV cm-1 for the temperature range studied. Because the predicted mobility is significantly higher than both *μSR* and *μC,* the field effect mobility of a pchannel MOSFET is not determined by a contribution from acoustic phonon scattering. As observed with the n-channel data, the characteristics are consistently dominated at low and high electric fields by Coulomb and surface roughness scattering as shown by the data in Figures 22(b), 23(b), 24(b) and 27.

Impact of Dielectric Formation and Processing Techniques on the Operation of 4H-SiC MOSFETs http://dx.doi.org/10.5772/61067 85


**Table 4.** Comparison of 4H-SiC MOSFET characteristics

**HV06 Acoustic phonon Surface roughness Coulomb Temp B C D1 γ1 θ** 1 ×106 3.2 ×106 3.7×1034 5.9 5.0 1 ×106 3.2 ×106 7.2×1028 5.0 3.7 1 ×106 3.2 ×106 6.2×1027 4.8 2.6 1 ×106 3.2 ×106 1.5×1027 4.7 3.3 1 ×106 3.2 ×106 2.5×1023 4.0 4.1 **CR25 Acoustic phonon Surface roughness Coulomb Temp B C D1 γ1 θ** 1 ×106 3.2 ×106 1.2×1019 3.6 2.7 1 ×106 3.2 ×106 8.3×1015 3.0 2.1 1 ×106 3.2 ×106 3.2×1011 2.2 2.0 1 ×106 3.2 ×106 1.1×1015 2.8 2.1 1 ×106 3.2 ×106 2.4×1013 2.5 3.4 **CR27 Acoustic phonon Surface roughness Coulomb Temp B C D1 γ1 θ** 1 ×106 3.2 ×106 10.0×1021 4.1 9.1 1 ×106 3.2 ×106 1.2×1019 3.6 6.4 1 ×106 3.2 ×106 2.2×1018 3.4 6.0 1 ×106 3.2 ×106 1.4×1018 3.4 6.2 1 ×106 3.2 ×106 1.9×1014 2.7 4.1

**Table 3.** Fitting parameters to the mobility models used to describe the behaviour of p-channel MOSFET structures

taken from the literature [5,8]; B is 1.0×106

84 Advanced Silicon Carbide Devices and Processing

Figures 22(b), 23(b), 24(b) and 27.

cm2

The data in Figure 28 shows the predicted values for the mobility limited by acoustic phonon scattering *(μAC)* based on equation 9. The parameters used to generate the values for *μAC* are identical to those used in the n-channel devices reported in a previous section and have been

by the data in Figure 28, the modelled acoustic phonon mobility is consistently above 150

 V-1 s-1 for electric fields below 3.5MV cm-1 for the temperature range studied. Because the predicted mobility is significantly higher than both *μSR* and *μC,* the field effect mobility of a pchannel MOSFET is not determined by a contribution from acoustic phonon scattering. As observed with the n-channel data, the characteristics are consistently dominated at low and high electric fields by Coulomb and surface roughness scattering as shown by the data in

cm s-1, C is 3.23×106

K cm s-1 and α is 0.0284. As shown

**Figure 28.** *μAC* -E characteristics for a 1.5 µm gate length p-channel MOSFET

### **9. Impact of gate dielectric on the 1/***f* **noise characteristics of 4H-SiC MOSFETs**

Low-frequency noise (1/*f* noise) measurements are used to study impurities and defects in semiconductor devices. The technique is useful to investigate device quality and reliability issues as well as the examination of the density of interface states in MOS devices. Whilst 1/*f* noise dominates the low frequency region (up to 100 kHz), it can be up converted into a highfrequency component affecting the phase noise characteristics of devices used for RF applica‐ tions [43] as well as degrading the signal-to-noise ratio in analog circuitry. Very few studies of the 1/*f* noise in 4H-SiC have been explored to date [44 - 46]. Here, low-frequency noise is used to investigate how the gate dielectric influences the interface trap density and hence the characteristics of the 4H-SiC MOSFETs. The aim is to determine the impact of the interface quality and resulting noise characteristics on the device performance.

**Figure 29.** Schematic diagram of the low-frequency noise measurement set-up

The low-frequency noise measurements were conducted using a Stanford Research 760 FFT at 298 K, and the current-voltage characteristics that were used to normalise the characteristics were conducted on a Keithley 4200 SCS semiconductor analyser. A schematic of the measure‐ ment set-up is shown in Figure 29.

The normalised 1/*f* noise characteristics and the normalised noise power spectral density (NNPSD) for each of the dielectrics on the n-channel MOSFETs are shown in Figures 30, 31 and 32 for HV06, CR25 and CR27, respectively. The data in Figures 30(a), 31(a) and 32(a) show a plot of the NNPSD against frequency for varying *VGS* for each of the n-channel MOSFETs studied. The data shows that each of the devices shows a similar trend, with the NNPSD decreasing with increasing gate bias, and this indicates that 1/*f* noise is higher at low gate biases (during weak inversion) and reduces at higher gate biases (at strong inversion).

Figures 30(b), 31(b) and 32(b) show the variation of normalised noise power spectrum (NNPSD) at 10 Hz as a function of *VGS* and *IDS* for each of the devices studied here. The trends observed in the data for each of the devices suggest that mobility fluctuations are the main contributor to the noise characteristics [47]. During weak inversion, the *IDS* –*NNPSD* charac‐ teristics show a linear trend as shown by the data in Figure 30 (a), which suggests that carrier mobility fluctuations dominate the noise spectra, whereas during strong inversion and increased current levels, the dependency exhibits a different trend. This suggests that during weak inversion, the noise characteristics are dominated by carrier mobility fluctuations as a consequence or charge trapping at the interface due to Coulomb scattering as discussed in a previous section, which can be described by the McWhorter model [48]. During strong inversion, the noise characteristics reduce significantly due to the reduction in the effect of Coulomb scattering. The trends are also consistent with those reported by Rumyantsev et al. who examined the low-frequency noise characteristics of n-channel 4H-SiC with varying annealing treatments in NO [46]. with increasing gate bias, and this indicates that 1/f noise is higher at low gate biases (during weak inversion) and reduces at higher gate biases (at strong inversion). Figures 30(b), 31(b) and 32(b) show the variation of normalised noise power spectrum (NNPSD) at 10 Hz as a function of VGS and IDS for each of the devices studied here. The trends observed in the data for each of the devices suggest that mobility fluctuations are the main contributor to the noise characteristics [47]. During weak inversion, the IDS–NNPSD characteristics show a linear trend as shown by the data in Figure 30 (a), which suggests that carrier mobility fluctuations dominate the noise spectra, whereas during strong inversion and increased current levels, the dependency exhibits a different trend. This suggests that during weak inversion, the noise characteristics are dominated by carrier mobility fluctuations as a consequence or charge trapping at the interface due to Coulomb scattering as discussed in a previous section, which can be described by the McWhorter model [48]. During strong inversion, the noise characteristics reduce significantly due to the reduction in the effect of Coulomb scattering. The trends are also consistent with those reported

The low-frequency noise measurements were conducted using a Stanford Research 760 FFT at 298 K, and the currentvoltage characteristics that were used to normalise the characteristics were conducted on a Keithley 4200 SCS

channel MOSFETs studied. The data shows that each of the devices shows a similar trend, with the NNPSD decreasing

Figure 29. Schematic diagram of the low-frequency noise measurement set-up

semiconductor analyser. A schematic of the measurement set-up is shown in Figure 29.

**9. Impact of gate dielectric on the 1/***f* **noise characteristics of 4H-SiC**

quality and resulting noise characteristics on the device performance.

**Figure 29.** Schematic diagram of the low-frequency noise measurement set-up

ment set-up is shown in Figure 29.

Low-frequency noise (1/*f* noise) measurements are used to study impurities and defects in semiconductor devices. The technique is useful to investigate device quality and reliability issues as well as the examination of the density of interface states in MOS devices. Whilst 1/*f* noise dominates the low frequency region (up to 100 kHz), it can be up converted into a highfrequency component affecting the phase noise characteristics of devices used for RF applica‐ tions [43] as well as degrading the signal-to-noise ratio in analog circuitry. Very few studies of the 1/*f* noise in 4H-SiC have been explored to date [44 - 46]. Here, low-frequency noise is used to investigate how the gate dielectric influences the interface trap density and hence the characteristics of the 4H-SiC MOSFETs. The aim is to determine the impact of the interface

The low-frequency noise measurements were conducted using a Stanford Research 760 FFT at 298 K, and the current-voltage characteristics that were used to normalise the characteristics were conducted on a Keithley 4200 SCS semiconductor analyser. A schematic of the measure‐

The normalised 1/*f* noise characteristics and the normalised noise power spectral density (NNPSD) for each of the dielectrics on the n-channel MOSFETs are shown in Figures 30, 31 and 32 for HV06, CR25 and CR27, respectively. The data in Figures 30(a), 31(a) and 32(a) show a plot of the NNPSD against frequency for varying *VGS* for each of the n-channel MOSFETs studied. The data shows that each of the devices shows a similar trend, with the NNPSD decreasing with increasing gate bias, and this indicates that 1/*f* noise is higher at low gate biases

Figures 30(b), 31(b) and 32(b) show the variation of normalised noise power spectrum (NNPSD) at 10 Hz as a function of *VGS* and *IDS* for each of the devices studied here. The trends observed in the data for each of the devices suggest that mobility fluctuations are the main contributor to the noise characteristics [47]. During weak inversion, the *IDS* –*NNPSD* charac‐ teristics show a linear trend as shown by the data in Figure 30 (a), which suggests that carrier

(during weak inversion) and reduces at higher gate biases (at strong inversion).

**MOSFETs**

86 Advanced Silicon Carbide Devices and Processing

CR27 exhibits the lowest noise characteristics of the three samples, which suggests that CR27 has the highest quality interface as there is a very low noise contribution from carrier mobility fluctuations at the interface, which suggests that the oxide also has the lowest trap density in the oxide out of the three dielectric samples. This is also in agreement with the findings of the *Dit* values extracted from the subthreshold slope data for CR27 that was presented in Figure 9. by Rumyantsev et al. who examined the low-frequency noise characteristics of n-channel 4H-SiC with varying annealing treatments in NO [46]. CR27 exhibits the lowest noise characteristics of the three samples, which suggests that CR27 has the highest quality interface as there is a very low noise contribution from carrier mobility fluctuations at the interface, which suggests that the oxide also has the lowest trap density in the oxide out of the three dielectric samples. This is also in agreement with the findings of the Dit values extracted from the subthreshold slope data for CR27 that was presented in Figure 9.

Figure 30. (a) NNPSD–f characteristics and (b) NNPSD at 10 Hz as a function of VGS and IDS for 400×1.5 µm n-channel MOSFET with HV06 dielectric **Figure 30.** (a) NNPSD–f characteristics and (b) NNPSD at 10 Hz as a function of *VGS* and *IDS* for 400×1.5 µm n-channel MOSFET with HV06 dielectric

In general, the frequency dependence of the NNPSD is described by equation 16:

$$\text{NNPSD} = \frac{\beta}{f^a} \tag{16}$$

Figure 31. (a) NNPSD–f characteristics and (b) NNPSD at 10 Hz as a function of VGS and IDS for 400×1.5 µm n-channel MOSFET with CR25 dielectric where*α* and *β* are fitting parameters. The frequency exponent (α) describes how much the trend deviates from a pure *f* <sup>−</sup><sup>1</sup> behaviour. The data in Figure 33 shows the variation of this frequency exponent, *α*, as a function of gate overdrive (*VGS -VTH*) for each of the n-channel MOSFETs, HV06, CR25 and CR27, respectively. As shown by the data, all three devices have consistently deviated from the common low-frequency noise exponent (*α*=1), and *α* values of between 0.5 and 1 have been extracted across the measured voltage range. According to theory, the frequency exponent deviates from 1 if the trap density is not uniform in depth, and because the extracted values of *α*<1, this suggests that the trap density is higher close to the silicon carbide–oxide interface and reduces further into the oxide [49].

HV06 dielectric

35(b) and 36(b).

treatments in NO [46].

Figure 29. Schematic diagram of the low-frequency noise measurement set-up

reduces at higher gate biases (at strong inversion).

semiconductor analyser. A schematic of the measurement set-up is shown in Figure 29.

The low-frequency noise measurements were conducted using a Stanford Research 760 FFT at 298 K, and the currentvoltage characteristics that were used to normalise the characteristics were conducted on a Keithley 4200 SCS

The normalised 1/f noise characteristics and the normalised noise power spectral density (NNPSD) for each of the dielectrics on the n-channel MOSFETs are shown in Figures 30, 31 and 32 for HV06, CR25 and CR27, respectively. The data in Figures 30(a), 31(a) and 32(a) show a plot of the NNPSD against frequency for varying VGS for each of the nchannel MOSFETs studied. The data shows that each of the devices shows a similar trend, with the NNPSD decreasing with increasing gate bias, and this indicates that 1/f noise is higher at low gate biases (during weak inversion) and

Figures 30(b), 31(b) and 32(b) show the variation of normalised noise power spectrum (NNPSD) at 10 Hz as a function of VGS and IDS for each of the devices studied here. The trends observed in the data for each of the devices suggest that mobility fluctuations are the main contributor to the noise characteristics [47]. During weak inversion, the IDS–NNPSD characteristics show a linear trend as shown by the data in Figure 30 (a), which suggests that carrier mobility fluctuations dominate the noise spectra, whereas during strong inversion and increased current levels, the dependency exhibits a different trend. This suggests that during weak inversion, the noise characteristics are dominated by carrier mobility fluctuations as a consequence or charge trapping at the interface due to Coulomb scattering as discussed in a previous section, which can be described by the McWhorter model [48]. During strong inversion, the noise characteristics reduce significantly due to the reduction in the effect of Coulomb scattering. The trends are also consistent with those reported by Rumyantsev et al. who examined the low-frequency noise characteristics of n-channel 4H-SiC with varying annealing

CR27 exhibits the lowest noise characteristics of the three samples, which suggests that CR27 has the highest quality interface as there is a very low noise contribution from carrier mobility fluctuations at the interface, which suggests that the oxide also has the lowest trap density in the oxide out of the three dielectric samples. This is also in agreement with the findings of the Dit values extracted from the subthreshold slope data for CR27 that was presented in Figure 9.

Figure 30. (a) NNPSD–f characteristics and (b) NNPSD at 10 Hz as a function of VGS and IDS for 400×1.5 µm n-channel MOSFET with

Figure 31. (a) NNPSD–f characteristics and (b) NNPSD at 10 Hz as a function of VGS and IDS for 400×1.5 µm n-channel MOSFET with CR25 dielectric **Figure 31.** (a) NNPSD–f characteristics and (b) NNPSD at 10 Hz as a function of *VGS* and *IDS* for 400×1.5 µm n-channel MOSFET with CR25 dielectric

Figure 32. (a) NNPSD–f characteristics and (b) NNPSD at 10 Hz as a function of VGS and IDS for 400×1.5 µm n-channel MOSFET with CR27 dielectric **Figure 32.** (a) NNPSD–f characteristics and (b) NNPSD at 10 Hz as a function of *VGS* and *IDS* for 400×1.5 µm n-channel MOSFET with CR27 dielectric

In general, the frequency dependence of the NNPSD is described by equation 16:

α <sup>β</sup> NNPSD <sup>=</sup> f (16) whereα and β are fitting parameters. The frequency exponent (α) describes how much the trend deviates from a pure <sup>−</sup><sup>1</sup> f behaviour. The data in Figure 33 shows the variation of this frequency exponent, α, as a function of gate overdrive (VGS-VTH) for each of the n-channel MOSFETs, HV06, CR25 and CR27, respectively. As shown by the data, all three devices have consistently deviated from the common low-frequency noise exponent (α=1), and α values of between 0.5 and 1 have been extracted across the measured voltage range. According to theory, the frequency exponent deviates from 1 if the trap density is not uniform in depth, and because the extracted values of α<1, this suggests that the trap density is higher close to the silicon carbide–oxide interface and reduces further into the oxide [49]. The 1/*f* noise characteristics for each of the dielectrics on the p-channel MOSFETs are shown in Figures 34, 35 and 36 for HV06, CR25 and CR27, respectively. The data in Figures 34(a), 35(a) and 36(a) show a plot of the NNSPD against frequency for varying (*VGS)* for each of the pchannel MOSFETs, HV06, CR25 and CR27, respectively. Both HV06 and CR25 exhibit a similar characteristic and suggest that 1/*f* noise is higher at low gate biases (during weak inversion) and reduces at higher gate biases (at strong inversion) as shown by the data in Figures 34(a) and 35(a). However, the data for sample CR27 shown in Figure 36(a) shows that NNSPD increases slightly with increasing gate bias for sample CR27; however, the noise level is substantially lower than the noise level in both HV06 and CR25. A plot of the normalised noise spectrum power density (NNSPD) at 10 Hz against *VGS* and *IDS* is shown for each of the devices in Figures 34(b), 35(b) and 36(b).

As with the n-channel devices, CR27 exhibits the lowest noise characteristics of the three pchannel samples, supporting the hypothesis that the quality of the silicon carbide–oxide interface is highest in this sample.

The 1/f noise characteristics for each of the dielectrics on the p-channel MOSFETs are shown in Figures 34, 35 and 36 for HV06, CR25 and CR27, respectively. The data in Figures 34(a), 35(a) and 36(a) show a plot of the NNSPD against frequency for varying (VGS) for each of the p-channel MOSFETs, HV06, CR25 and CR27, respectively. Both HV06 and CR25 exhibit a similar characteristic and suggest that 1/f noise is higher at low gate biases (during weak inversion) and reduces at higher gate biases (at strong inversion) as shown by the data in Figures 34(a) and 35(a). However, the data for sample CR27 shown in Figure 36(a) shows that NNSPD increases slightly with increasing gate bias for sample CR27; however, the noise level is substantially lower than the noise level in both HV06 and CR25. A plot of the normalised noise spectrum power density (NNSPD) at 10 Hz against VGS and IDS is shown for each of the devices in Figures 34(b),

Figure 33. Variation of the frequency exponent as a function of gate overdrive for 400×1.5 µm n-channel MOSFETs

Impact of Dielectric Formation and Processing Techniques on the Operation of 4H-SiC MOSFETs http://dx.doi.org/10.5772/61067 89

Figure 29. Schematic diagram of the low-frequency noise measurement set-up

reduces at higher gate biases (at strong inversion).

treatments in NO [46].

HV06 dielectric

88 Advanced Silicon Carbide Devices and Processing

MOSFET with CR25 dielectric

CR27 dielectric

35(b) and 36(b).

α <sup>β</sup> NNPSD <sup>=</sup> f (16)

in Figures 34(b), 35(b) and 36(b).

interface is highest in this sample.

MOSFET with CR27 dielectric

semiconductor analyser. A schematic of the measurement set-up is shown in Figure 29.

The low-frequency noise measurements were conducted using a Stanford Research 760 FFT at 298 K, and the currentvoltage characteristics that were used to normalise the characteristics were conducted on a Keithley 4200 SCS

The normalised 1/f noise characteristics and the normalised noise power spectral density (NNPSD) for each of the dielectrics on the n-channel MOSFETs are shown in Figures 30, 31 and 32 for HV06, CR25 and CR27, respectively. The data in Figures 30(a), 31(a) and 32(a) show a plot of the NNPSD against frequency for varying VGS for each of the nchannel MOSFETs studied. The data shows that each of the devices shows a similar trend, with the NNPSD decreasing with increasing gate bias, and this indicates that 1/f noise is higher at low gate biases (during weak inversion) and

Figures 30(b), 31(b) and 32(b) show the variation of normalised noise power spectrum (NNPSD) at 10 Hz as a function of VGS and IDS for each of the devices studied here. The trends observed in the data for each of the devices suggest that mobility fluctuations are the main contributor to the noise characteristics [47]. During weak inversion, the IDS–NNPSD characteristics show a linear trend as shown by the data in Figure 30 (a), which suggests that carrier mobility fluctuations dominate the noise spectra, whereas during strong inversion and increased current levels, the dependency exhibits a different trend. This suggests that during weak inversion, the noise characteristics are dominated by carrier mobility fluctuations as a consequence or charge trapping at the interface due to Coulomb scattering as discussed in a previous section, which can be described by the McWhorter model [48]. During strong inversion, the noise characteristics reduce significantly due to the reduction in the effect of Coulomb scattering. The trends are also consistent with those reported by Rumyantsev et al. who examined the low-frequency noise characteristics of n-channel 4H-SiC with varying annealing

CR27 exhibits the lowest noise characteristics of the three samples, which suggests that CR27 has the highest quality interface as there is a very low noise contribution from carrier mobility fluctuations at the interface, which suggests that the oxide also has the lowest trap density in the oxide out of the three dielectric samples. This is also in agreement with the findings of the Dit values extracted from the subthreshold slope data for CR27 that was presented in Figure 9.

Figure 30. (a) NNPSD–f characteristics and (b) NNPSD at 10 Hz as a function of VGS and IDS for 400×1.5 µm n-channel MOSFET with

Figure 31. (a) NNPSD–f characteristics and (b) NNPSD at 10 Hz as a function of VGS and IDS for 400×1.5 µm n-channel MOSFET with CR25 dielectric **Figure 31.** (a) NNPSD–f characteristics and (b) NNPSD at 10 Hz as a function of *VGS* and *IDS* for 400×1.5 µm n-channel

Figure 32. (a) NNPSD–f characteristics and (b) NNPSD at 10 Hz as a function of VGS and IDS for 400×1.5 µm n-channel MOSFET with

**Figure 32.** (a) NNPSD–f characteristics and (b) NNPSD at 10 Hz as a function of *VGS* and *IDS* for 400×1.5 µm n-channel

The 1/*f* noise characteristics for each of the dielectrics on the p-channel MOSFETs are shown in Figures 34, 35 and 36 for HV06, CR25 and CR27, respectively. The data in Figures 34(a), 35(a) and 36(a) show a plot of the NNSPD against frequency for varying (*VGS)* for each of the pchannel MOSFETs, HV06, CR25 and CR27, respectively. Both HV06 and CR25 exhibit a similar characteristic and suggest that 1/*f* noise is higher at low gate biases (during weak inversion) and reduces at higher gate biases (at strong inversion) as shown by the data in Figures 34(a) and 35(a). However, the data for sample CR27 shown in Figure 36(a) shows that NNSPD increases slightly with increasing gate bias for sample CR27; however, the noise level is substantially lower than the noise level in both HV06 and CR25. A plot of the normalised noise spectrum power density (NNSPD) at 10 Hz against *VGS* and *IDS* is shown for each of the devices

As with the n-channel devices, CR27 exhibits the lowest noise characteristics of the three pchannel samples, supporting the hypothesis that the quality of the silicon carbide–oxide

whereα and β are fitting parameters. The frequency exponent (α) describes how much the trend deviates from a pure <sup>−</sup><sup>1</sup> f behaviour. The data in Figure 33 shows the variation of this frequency exponent, α, as a function of gate overdrive (VGS-VTH) for each of the n-channel MOSFETs, HV06, CR25 and CR27, respectively. As shown by the data, all three devices have consistently deviated from the common low-frequency noise exponent (α=1), and α values of between 0.5 and 1 have been extracted across the measured voltage range. According to theory, the frequency exponent deviates from 1 if the trap density is not uniform in depth, and because the extracted values of α<1, this suggests that the trap

density is higher close to the silicon carbide–oxide interface and reduces further into the oxide [49].

Figure 33. Variation of the frequency exponent as a function of gate overdrive for 400×1.5 µm n-channel MOSFETs

The 1/f noise characteristics for each of the dielectrics on the p-channel MOSFETs are shown in Figures 34, 35 and 36 for HV06, CR25 and CR27, respectively. The data in Figures 34(a), 35(a) and 36(a) show a plot of the NNSPD against frequency for varying (VGS) for each of the p-channel MOSFETs, HV06, CR25 and CR27, respectively. Both HV06 and CR25 exhibit a similar characteristic and suggest that 1/f noise is higher at low gate biases (during weak inversion) and reduces at higher gate biases (at strong inversion) as shown by the data in Figures 34(a) and 35(a). However, the data for sample CR27 shown in Figure 36(a) shows that NNSPD increases slightly with increasing gate bias for sample CR27; however, the noise level is substantially lower than the noise level in both HV06 and CR25. A plot of the normalised noise spectrum power density (NNSPD) at 10 Hz against VGS and IDS is shown for each of the devices in Figures 34(b),

In general, the frequency dependence of the NNPSD is described by equation 16:

**Figure 33.** Variation of the frequency exponent as a function of gate overdrive for 400×1.5 µm n-channel MOSFETs

Figure 34. (a) NNPSD–f characteristics and (b) NNPSD at 10 Hz as a function of VGS and IDS for 8000×1.5µm p-channel MOSFET with HV06 dielectric **Figure 34.** (a) NNPSD–f characteristics and (b) NNPSD at 10 Hz as a function of *VGS* and *IDS* for 8000×1.5µm p-channel MOSFET with HV06 dielectric

The data in Figure 37 shows the variation of the frequency exponent as a function of gate overdrive (*VGS –VTH*) for each of the p-channel MOSFETs. The frequency exponent (*α*) was extracted from the data in Figures 34(a), 35(a) and 36(a) based on equation 16. The data for all three devices show consistent deviation from the common low-frequency noise expo‐ nent (*α=1*), and values between 1 and 2 have been extracted across the measured voltage range. In contrast to data for the n-channel devices shown in Figure 33, the *α* values for the p-channel devices are all greater than 1. This indicates that in the case of the pchannel devices, the trap density is lower at the silicon carbide–oxide interface than in the bulk of the oxide and increases further into the oxide [49], similar to reported values for nitrided gate oxides in SOI MOSFETs [50]. Figure 35. (a) NNPSD–f characteristics and (b) NNPSD at 10 Hz as a function of VGS and IDS for 8000×1.5µm p-channel MOSFET with CR25 dielectric

The contrast between the distribution of the trapping states extracted from the 1/*f* noise data suggests that optimisation of the dielectric process steps for CMOS structures with monolith‐

Figure 36. (a) NNPSD–f characteristics and (b) NNPSD at 10 Hz as a function of VGS and IDS for 8000×1.5µm p-channel MOSFET with

the hypothesis that the quality of the silicon carbide–oxide interface is highest in this sample.

As with the n-channel devices, CR27 exhibits the lowest noise characteristics of the three p-channel samples, supporting

CR27 dielectric

HV06 dielectric

HV06 dielectric

CR27 dielectric

CR25 dielectric

Figure 34. (a) NNPSD–f characteristics and (b) NNPSD at 10 Hz as a function of VGS and IDS for 8000×1.5µm p-channel MOSFET with

Figure 34. (a) NNPSD–f characteristics and (b) NNPSD at 10 Hz as a function of VGS and IDS for 8000×1.5µm p-channel MOSFET with

Figure 35. (a) NNPSD–f characteristics and (b) NNPSD at 10 Hz as a function of VGS and IDS for 8000×1.5µm p-channel MOSFET with CR25 dielectric **Figure 35.** (a) NNPSD–f characteristics and (b) NNPSD at 10 Hz as a function of *VGS* and *IDS* for 8000×1.5µm p-channel MOSFET with CR25 dielectric Figure 35. (a) NNPSD–f characteristics and (b) NNPSD at 10 Hz as a function of VGS and IDS for 8000×1.5µm p-channel MOSFET with

As with the n-channel devices, CR27 exhibits the lowest noise characteristics of the three p-channel samples, supporting the hypothesis that the quality of the silicon carbide–oxide interface is highest in this sample. Figure 36. (a) NNPSD–f characteristics and (b) NNPSD at 10 Hz as a function of VGS and IDS for 8000×1.5µm p-channel MOSFET with CR27 dielectric **Figure 36.** (a) NNPSD–f characteristics and (b) NNPSD at 10 Hz as a function of *VGS* and *IDS* for 8000×1.5µm p-channel MOSFET with CR27 dielectric

**Figure 37.** Variation of the frequency exponent as a function of gate overdrive for 8000×1.5µm p-channel MOSFETs

ically fabricated n- and p-channel devices is more complex than the purely n-channel devices common in power electronic applications. The variation in depth of the highest trap density within the dielectric layer suggests that the electron interact with traps in the oxide close to the interface, whereas, holes interact with traps at deeper energy levels within the oxide.

#### **10. Summary**

Figure 34. (a) NNPSD–f characteristics and (b) NNPSD at 10 Hz as a function of VGS and IDS for 8000×1.5µm p-channel MOSFET with

Figure 34. (a) NNPSD–f characteristics and (b) NNPSD at 10 Hz as a function of VGS and IDS for 8000×1.5µm p-channel MOSFET with

Figure 35. (a) NNPSD–f characteristics and (b) NNPSD at 10 Hz as a function of VGS and IDS for 8000×1.5µm p-channel MOSFET with

**Figure 35.** (a) NNPSD–f characteristics and (b) NNPSD at 10 Hz as a function of *VGS* and *IDS* for 8000×1.5µm p-channel

Figure 35. (a) NNPSD–f characteristics and (b) NNPSD at 10 Hz as a function of VGS and IDS for 8000×1.5µm p-channel MOSFET with

Figure 36. (a) NNPSD–f characteristics and (b) NNPSD at 10 Hz as a function of VGS and IDS for 8000×1.5µm p-channel MOSFET with

the hypothesis that the quality of the silicon carbide–oxide interface is highest in this sample.

the hypothesis that the quality of the silicon carbide–oxide interface is highest in this sample.

As with the n-channel devices, CR27 exhibits the lowest noise characteristics of the three p-channel samples, supporting

As with the n-channel devices, CR27 exhibits the lowest noise characteristics of the three p-channel samples, supporting

Figure 36. (a) NNPSD–f characteristics and (b) NNPSD at 10 Hz as a function of VGS and IDS for 8000×1.5µm p-channel MOSFET with

**Figure 36.** (a) NNPSD–f characteristics and (b) NNPSD at 10 Hz as a function of *VGS* and *IDS* for 8000×1.5µm p-channel

**Figure 37.** Variation of the frequency exponent as a function of gate overdrive for 8000×1.5µm p-channel MOSFETs

HV06 dielectric

90 Advanced Silicon Carbide Devices and Processing

HV06 dielectric

CR25 dielectric

CR25 dielectric

MOSFET with CR25 dielectric

CR27 dielectric

CR27 dielectric

MOSFET with CR27 dielectric

The focus of this chapter was on the investigation of the electrical characteristics and device performance parameters of the 4H-SiC n- and p-channel MOSFETs that had undergone a range of dielectric process treatments to establish the suitability of conventional oxidation and deposited dielectrics for the realisation of complementary metal–oxide semiconductor circuits. The investigation into the temperature-dependent electrical characteristics of the devices demonstrated that all of the devices showed similar characteristics across the measured temperature range including an increase in *IDS,* a reduction in *VTH*, a reduction in *Dit* and, therefore, an increase in *μFE* with increasing temperature. This demonstrated that as temper‐ ature increases, there is a reduction of interface trapping effects, and therefore, Coulomb scattering reduces causing the device mobility and current to increase.

The CR27 samples for both n- and p-channel MOSFETs exhibit the highest field effect mobility characteristics, suggesting that a thin thermally grown oxide provides improved interfacial characteristics. This was further validated by the 1/*f* noise characteristics of the CR27 MOS‐ FETs, which exhibited the lowest 1/*f* noise characteristics out of the three dielectrics at 298 K.

All three dielectrics in both the n- and p-channel devices showed severely high mobility limiting surface roughness scattering during strong inversion and high electric fields, which suggests that a process parameter – which is consistent amongst all three dielectrics and both the n- and p-channel devices – is causing high surface roughness in the channel, which is acting to degrade the channel mobility. In order to improve the device characteristics, a major focus should be given to increasing the surface roughness mobility of the samples. There is a strong trend across all of the examined samples of extremely low surface roughness mobility from applied electric fields of 1 MV cm-1 onwards, which is consistent across all of the processed samples and much lower than other reported devices. This is also consistent between the nand p-channel devices, which suggests that it is inherent in the process technique used in both devices. This suggests that process contributions that are acting to degrade the surface roughness mobility of the devices is a major factor which is consistent across all of the samples. This suggests that the severely low *μSR* is not a contribution of the dielectric processing steps but could be a product of the ion implantation or the post-implantation anneal process.

An investigation into the 1/*f* noise characteristics of each of the MOSFET samples between 1 Hz and 100 kHz showed that in the n-channel MOSFETs, the oxide trap density was higher close to the interface, whereas, in the p-channel MOSFETs, the trap density was consistently higher further away from the silicon carbide–oxide interface consistently across all three dielectrics. The investigation also highlighted that in weak inversion, the 1/*f* noise characteristic of all of the devices is dominated by mobility fluctuations due to charge trapping at the interface as a consequence of Coulomb scattering, which can be described by the McWhorter low-frequency noise model.

Finally, an investigation into the impact of the threshold voltage-adjust ion implantation procedure on the device characteristics was investigated for the CR27 n-channel MOSFETs. The findings showed that the increasing nitrogen dose was successful in acting to reduce the device threshold voltage; however, the nitrogen implant within the p-well also acts to improve the low electric field mobility characteristics of the n-channel 4H-SiC MOSFETs as an increased dose of nitrogen during the implant acts to reduce the effects of Coulomb scattering and therefore increase Coulomb mobility.

#### **Author details**

Lucy Martin, Hua-Khee Chan, Ming-Hung Weng and Alton Horsfall\*

\*Address all correspondence to: Alton.horsfall@newcastle.ac.uk

School of Electrical and Electronic Engineering, University of Newcastle, Newcastle, UK

#### **References**


interface as a consequence of Coulomb scattering, which can be described by the McWhorter

Finally, an investigation into the impact of the threshold voltage-adjust ion implantation procedure on the device characteristics was investigated for the CR27 n-channel MOSFETs. The findings showed that the increasing nitrogen dose was successful in acting to reduce the device threshold voltage; however, the nitrogen implant within the p-well also acts to improve the low electric field mobility characteristics of the n-channel 4H-SiC MOSFETs as an increased dose of nitrogen during the implant acts to reduce the effects of Coulomb scattering and

Lucy Martin, Hua-Khee Chan, Ming-Hung Weng and Alton Horsfall\*

School of Electrical and Electronic Engineering, University of Newcastle, Newcastle, UK

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pp. 175–177


**Chapter 4**

## **Investigation of SiC/Oxide Interface Structures by Spectroscopic Ellipsometry**

Sadafumi Yoshida, Yasuto Hijikata and Hiroyuki Yaguchi

Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/61082

#### **Abstract**

We have investigated SiC/oxide interface structures by the use of spectroscopic ellipsometry. The depth profile of the optical constants of thermally grown oxide layers on SiC was obtained by observing the slope-shaped oxide layers, and the results suggest the existence of the interface layers, around 1 nm in thickness, having high refractive index than those of both SiC and SiO2. The wavelength dispersions of optical constants of the interface layers were measured in the range of visible to deep UV spectral region, and we found the interface layers have similar dispersion to that of SiC, though the refractive indices are around 1 larger than SiC, which suggests the interface layers are neither transition layers nor roughness layers, but modified SiC, e.g., strained and/or modified composition. By the use of an in-situ ellipsometer, realtime observation of SiC oxidation was performed, and the growth rate enhancement was found in the thin thickness regime as in the case of Si oxidation, which cannot be explained by the Deal-Grove model proposed for Si oxidation. From the measure‐ ments of the oxidation temperature and oxygen partial pressure dependences of oxidation rate in the initial stage of oxidation, we have discussed the interface structures and their formation mechanisms within the framework of the interfacial Si-C emission model we proposed for SiC oxidation mechanism.

**Keywords:** SiC-MOSFET, SiC/oxide interface, spectroscopic ellipsometry, SiC oxi‐ dation mechanism, interface state density

© 2015 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

#### **1. Introduction**

SiC metal-oxide-semiconductor field effect transistors (MOSFETs) are still the main targets in the research and development of SiC switching devices, because of their capability of ultralow loss, high-frequency and high-temperature operation, and high-current and high-voltage tolerance, resulting in, for example, reducing the volume of electric power conversion modules compared with those using Si devices. However, SiC-MOSFETs have some problems to be solved before wide use, such as their higher on-resistance and lower reliability than those predicted from bulk properties. These poor device characteristics have been attributed to, for example, low carrier mobility due to high interface state density at the SiC/oxide interface and crystal defects. To elucidate the origin of poor characteristics of interfaces, it is important to make clear the interface structures as well as the study on the relation between interface structures and electrical properties.

#### **1.1. Observation methods of interface structures**

As metal-semiconductor and insulator-semiconductor junctions, and semiconductor heterojunctions are key components of semiconductor devices, many measurement and observation techniques, e.g., X-ray photoelectron spectroscopy (XPS), transmission electron microscopy (TEM), scanning TEM (STEM), secondary electron microscopy (SEM), photoluminescence (PL) and cathodoluminescence (CL) spectroscopy, Rutherford backscattering spectroscopy (RBS), secondary ion mass spectroscopy (SIMS), have been adopted for the investigation of their interface structures. These techniques can be divided into three categories, i.e., (Figure 1)


In the cases of categories (1) and (2), there is a danger of the change and/or damage on the interface structures in the preparation process of specimens and by exposing the interface to the air, and a fear of non-uniformity of etching and/or sputtering of upper layers in an atomic layer thickness scale. In the case of cross-sectional TEM images, the specimen is required to reduce the thickness less than 100 nm. However, as the specimen is composed of still dozens of atomic layers, the image is formed by summing over the beams coming from a number of atomic layers in the specimen, and thus, it is hard to distinguish the effect due to the existence of interface layer from that of interface roughness and/or non-uniformity.

While, in the case of category (3), the observation is carried out without sample preparation, like thinning by etching and sputtering, and thus, there is no fear of the problems for the case of categories (1) and (2). In other words, the observation technologies belonging to category (3) are ideal ones which can observe the buried interface without any treatment, i.e., kept intact. However, this technique is only applicable to the case where the probing and signal beams from the interface can transmit through the upper or over layers, and thus, generally, the techniques are applicable only to the cases of very thin over layers or transparent ones for the probe beam. Optical methods like ellipsometry and infrared reflectance spectroscopy, X-ray reflectivity (XRR), and RBS are the examples of the technologies of category (3). In the case of technologies of this category, however, as the signals from the interface are mixed with those from the upper and lower layers, it is necessary to analyze the signal under the assumption of a certain structural model. The information on interface structures is derived by the fitting of the calculated values by use of the model assumed and the observed data. Therefore, the results strongly depend on the model assumed, and thus, to build up an appropriate structural model is very important for obtaining significant information of interfaces from the observation. The model assumed is, in a word, a hypothesis, and thus, it is necessary to verify the validity of the model used. The influence of the selection of model used in the analysis of the obtained data will be discussed in the case of ellipsometric measurements of SiC/oxide interfaces in Section 2.

**Figure 1.** Three categories for the observation methods or techniques of interface structures.

#### **1.2. Measurements by use of ellipsometry**

**1. Introduction**

98 Advanced Silicon Carbide Devices and Processing

structures and electrical properties.

**1.1. Observation methods of interface structures**

**1.** observations of the interfaces on the cross section of specimens,

**3.** analysis of the signal coming from the interface through the upper layers.

of interface layer from that of interface roughness and/or non-uniformity.

SiC metal-oxide-semiconductor field effect transistors (MOSFETs) are still the main targets in the research and development of SiC switching devices, because of their capability of ultralow loss, high-frequency and high-temperature operation, and high-current and high-voltage tolerance, resulting in, for example, reducing the volume of electric power conversion modules compared with those using Si devices. However, SiC-MOSFETs have some problems to be solved before wide use, such as their higher on-resistance and lower reliability than those predicted from bulk properties. These poor device characteristics have been attributed to, for example, low carrier mobility due to high interface state density at the SiC/oxide interface and crystal defects. To elucidate the origin of poor characteristics of interfaces, it is important to make clear the interface structures as well as the study on the relation between interface

As metal-semiconductor and insulator-semiconductor junctions, and semiconductor heterojunctions are key components of semiconductor devices, many measurement and observation techniques, e.g., X-ray photoelectron spectroscopy (XPS), transmission electron microscopy (TEM), scanning TEM (STEM), secondary electron microscopy (SEM), photoluminescence (PL) and cathodoluminescence (CL) spectroscopy, Rutherford backscattering spectroscopy (RBS), secondary ion mass spectroscopy (SIMS), have been adopted for the investigation of their interface structures. These techniques can be divided into three categories, i.e., (Figure 1)

**2.** measurements of the thickness profile by etching or sputtering of the over or upper layers,

In the cases of categories (1) and (2), there is a danger of the change and/or damage on the interface structures in the preparation process of specimens and by exposing the interface to the air, and a fear of non-uniformity of etching and/or sputtering of upper layers in an atomic layer thickness scale. In the case of cross-sectional TEM images, the specimen is required to reduce the thickness less than 100 nm. However, as the specimen is composed of still dozens of atomic layers, the image is formed by summing over the beams coming from a number of atomic layers in the specimen, and thus, it is hard to distinguish the effect due to the existence

While, in the case of category (3), the observation is carried out without sample preparation, like thinning by etching and sputtering, and thus, there is no fear of the problems for the case of categories (1) and (2). In other words, the observation technologies belonging to category (3) are ideal ones which can observe the buried interface without any treatment, i.e., kept intact. However, this technique is only applicable to the case where the probing and signal beams from the interface can transmit through the upper or over layers, and thus, generally, the techniques are applicable only to the cases of very thin over layers or transparent ones for the

As the oxide layers formed by thermal oxidation of SiC are transparent in the visible and ultraviolet spectral ranges, optical methods are suitable to detect the signal from the interface through the upper oxide layer. Especially, ellipsometry, i.e., the measurement of the changes in polarization upon the reflection of light from a surface, has very high sensitivity for very thin films because of the measurement of phase difference between p and s polarized light components and using oblique incident light beams, which brings about longer path in the films than those for perpendicularly incident light.

Many studies on the structures of Si/oxide interface by spectroscopic ellipsometry have been reported. Deal and Grove [1] measured the thickness of the thermal oxide on Si by using a multiple beam interferometer in the range between 0.1 and 10 µm and derived the linearparabolic model, so-called, D-G model, for Si oxidation. Taft and Cordes [2] reported the existence of the interface layers, 0.6 nm in thickness and 2.8 in refractive index by use of an ellipsometer at the wavelength *λ* = 546.1 nm. Aspnes and Theeten [3] have analyzed the interface structures in detail by spectroscopic ellipsometry. They proposed the equation to calculate the dielectric constants for two kinds of interface layers, i.e., physical mixture of amorphous Si and SiO2, which corresponds to the cases of micro-roughness and inclusion or void in Si, and chemically mixed Si and O atoms. In the former, they used Bruggeman's effective medium approximation (EMA), and in the latter, they used Si-centered tetrahedral O atoms, Si4-νO (*ν* = 0-4) model by Philipp and composite medium theory by the Clausius-Mossotti relation. They reported that their results of spectroscopic ellipsometry for thermal oxides on Si are incompatible with either micro-roughness or an abrupt transition from Si to SiO2, but rather support a graded transition layer, 0.7 ± 0.2 nm region in thickness of atomically mixed Si and O of average stoichiometry SiO0.4±0.2. Massoud et al. [4] have performed in situ measurements of the thickness of Si oxides during the thermal oxidation in reduced oxygen partial pressure by the use of an automatic ellipsometer, and found the enhancement of the oxidation rate in thin thickness regime, which cannot be explained by the D-G mode, and showed good fit can be obtained by adding exponential term to D-G equation, though the physical meaning of adding new term, i.e., the origin of the exponential term, has not been ascertained. Nguyen et al. [5] found that the dielectric function of interface layers is similar to that of Si except the 0.02 eV red shift of inter-band critical point *E*<sup>1</sup> peak energy with rather small absolute values, from which they concluded there exist 2.2 nm thick interface layers composed of strained Si layer of 1.5 nm in thickness, and micro-roughness with 0.7 nm in optically equivalent thickness. They also said the transition layers reported by Aspnes and Theeten cannot be found, though the existence of the transition layers have been reported by using angle-resolved XPS, i.e., two monolayer compositional transition layers and one monolayer Si strained layer formed on a Si (001) face [6]. The refractive indices of very thin Si oxide layers were determined as a function of oxide thickness by ellipsometry using the thickness determined from tunnel current oscillation measurements [7]. Herzinger et al. measured the refractive indices of oxides on Si at the photon energy between 0.75 and 6.5eV by the use of variable-angle spectroscopic ellipsometry [8].

#### **1.3. Observations of SiC/oxide interfaces**

So far, many studies on SiC/oxide interface structures have been performed using various techniques, e.g., cross-sectional TEM and STEM belonging to category (1), and e.g., XPS and SIMS belonging to category (2). However, the results are sometimes contradicted with each other, and/or the results cannot be verified because of the fears mentioned above. For example, it has been reported that the SIMS measurement shows C atoms piled up near the interface more than 20%, and several percent even in Si oxide layers. On the contrary, it has been reported that XPS and medium energy ion scattering (MEIS) measurements suggest no such excess C around the interface and in the oxide films [9-11]. This contradiction is considered to be partly due to the difficulty in distinguishing between C atoms bonded to Si in adjacent SiC layers, the content of which is 1022/cm3 order and excess C atoms near the interface in the case of SIMS observation. In the case of XPS, C atoms bonded with Si and O can be distinguished between each other by the difference in their chemical shifts. As another example, Zheleva et al. [12] reported that high-resolution STEM combined with EELS measurements show the existence of interface layers, around 10 nm in thickness, with C-rich composition, and the thickness of the interface layers well correlates with the interface state density [13]. On the contrary, Hatakeyama et al. [14] reported that nosuch thick interface layer was observed by use of the same techniques, HAADF-STEM and EELS measurements, and, if there exists, it is less than 1 nm, which agrees with other measurements including our results by the use of spectroscopic ellipsometry.

multiple beam interferometer in the range between 0.1 and 10 µm and derived the linearparabolic model, so-called, D-G model, for Si oxidation. Taft and Cordes [2] reported the existence of the interface layers, 0.6 nm in thickness and 2.8 in refractive index by use of an ellipsometer at the wavelength *λ* = 546.1 nm. Aspnes and Theeten [3] have analyzed the interface structures in detail by spectroscopic ellipsometry. They proposed the equation to calculate the dielectric constants for two kinds of interface layers, i.e., physical mixture of amorphous Si and SiO2, which corresponds to the cases of micro-roughness and inclusion or void in Si, and chemically mixed Si and O atoms. In the former, they used Bruggeman's effective medium approximation (EMA), and in the latter, they used Si-centered tetrahedral O atoms, Si4-νO (*ν* = 0-4) model by Philipp and composite medium theory by the Clausius-Mossotti relation. They reported that their results of spectroscopic ellipsometry for thermal oxides on Si are incompatible with either micro-roughness or an abrupt transition from Si to SiO2, but rather support a graded transition layer, 0.7 ± 0.2 nm region in thickness of atomically mixed Si and O of average stoichiometry SiO0.4±0.2. Massoud et al. [4] have performed in situ measurements of the thickness of Si oxides during the thermal oxidation in reduced oxygen partial pressure by the use of an automatic ellipsometer, and found the enhancement of the oxidation rate in thin thickness regime, which cannot be explained by the D-G mode, and showed good fit can be obtained by adding exponential term to D-G equation, though the physical meaning of adding new term, i.e., the origin of the exponential term, has not been ascertained. Nguyen et al. [5] found that the dielectric function of interface layers is similar to that of Si except the 0.02 eV red shift of inter-band critical point *E*<sup>1</sup> peak energy with rather small absolute values, from which they concluded there exist 2.2 nm thick interface layers composed of strained Si layer of 1.5 nm in thickness, and micro-roughness with 0.7 nm in optically equivalent thickness. They also said the transition layers reported by Aspnes and Theeten cannot be found, though the existence of the transition layers have been reported by using angle-resolved XPS, i.e., two monolayer compositional transition layers and one monolayer Si strained layer formed on a Si (001) face [6]. The refractive indices of very thin Si oxide layers were determined as a function of oxide thickness by ellipsometry using the thickness determined from tunnel current oscillation measurements [7]. Herzinger et al. measured the refractive indices of oxides on Si at the photon energy between 0.75 and 6.5eV

by the use of variable-angle spectroscopic ellipsometry [8].

So far, many studies on SiC/oxide interface structures have been performed using various techniques, e.g., cross-sectional TEM and STEM belonging to category (1), and e.g., XPS and SIMS belonging to category (2). However, the results are sometimes contradicted with each other, and/or the results cannot be verified because of the fears mentioned above. For example, it has been reported that the SIMS measurement shows C atoms piled up near the interface more than 20%, and several percent even in Si oxide layers. On the contrary, it has been reported that XPS and medium energy ion scattering (MEIS) measurements suggest no such excess C around the interface and in the oxide films [9-11]. This contradiction is considered to be partly due to the difficulty in distinguishing between C atoms bonded to Si in adjacent SiC layers, the content of which is 1022/cm3 order and excess C atoms near the interface in the case

**1.3. Observations of SiC/oxide interfaces**

100 Advanced Silicon Carbide Devices and Processing

Ellipsometry has been used mainly in the measurements of the thickness of oxide layers, where the interface structures were not taken into account. Suzuki et al. [15] and Zheng et al. [16] for 6H-SiC and Fung and Kopanski [17] for 3C-SiC measured oxide thickness by use of ellipsom‐ etry, and explained the oxidation time dependence of the oxide thickness by diverting the D-G model proposed for Si oxidation. Song et al. [18] measured oxide thickness of thermally grown oxide on 4H-SiC by use of RBS and spectroscopic ellipsometry, and found good agreement with each other, and they modified the D-G model in order to apply to SiC oxidation, i.e., adding the process of CO diffusing out from interface to surface as well as oxygen diffusion from surface to interface in the diffusion-limited regime, and used to explain their experimental results for oxidation time dependence of oxide thickness. It is noted that all of these measurements were performed by ex situ ellipsometry measurements, i.e., ellipso‐ metric measurements were performed in air at room temperature after taking out from the oxidation furnace.

Sometimes, the thicknesses derived from the ellipsometry measurements are used as "physical thickness", or index of the progress of oxidation in the studies on, for examples, thickness dependences of some physical and chemical properties of oxide layers on SiC. If oxide layers are optically not uniform in the depth direction from SiC/oxide interface to oxide surface, and/ or if the refractive indices of oxide layers are not same as those of stoichiometric SiO2, e.g., there exist interface layers having different composition or properties from that of oxide layers, the thicknesses obtained are never physical thickness, because the thicknesses were derived under the assumption of an optically uniform single layer of stoichiometric SiO2 on SiC with abrupt interface.

RBS, XRR, and Fourier-transformed infrared (FTIR) spectroscopy, the technologies belonging to category (3), have also been used to characterize SiC/oxide interfaces. RBS technique has been used mostly combined with ellipsometry. Ray et al. [19] measured oxide thickness by spectroscopic ellipsometry in the range thinner than 15 nm, and by RBS and ion channeling technologies as well as spectroscopic ellipsometry in the large thickness range, and studied on the oxygen partial pressure dependence of oxidation mechanisms and interface density by use of the analysis using the D-G model. Szilagyi et al. [20] measured oxide thickness and density by using spectroscopic ellipsometry and RBS, and roughness by atomic force microscopy (AFM), and the differences in oxidation process for Si- and C-faces of 4H-SiC were discussed comparing with that of Si. They also used modified D-G model to analyze oxidation mecha‐ nisms. A limited number of the results on the SiC/oxide interface structures obtained by use of XRR and FTIR spectroscopy have been reported so far. The effects of NO annealing after oxidation of SiC to the interface structures and electrical properties were studied by use of XRR measurements for 6H-SiC [21] and 4H-SiC [22]. FT-IR spectroscopy by using attenuated total reflection (ATR) method has been performed to know the structures of the ultra-thin oxides on SiC [23,24]. The differences in stress and chemical state of oxides and oxide/SiC interface have been studied from the observation of TO and LO mode absorption due to Si-O-Si bond asymmetric stretching vibration for the oxides on Si- and C-faces of 6H-SiC and 4H-SiC.

We have employed spectroscopic ellipsometry for observing the SiC/oxide interface to investigate SiC/oxide interface structures. We have developed the characterization method of the oxide layers and SiC/oxide interfaces, i.e., the method using sloped oxide layers, and made clear the depth profile of the refractive indices and interface structures, i.e., there exist interface layers, around 1 nm in thickness, having high refractive indices [25,26], the values of which closely relate to the electrical properties of MOS diodes [27]. By the extension of measurement of wavelength to deep ultraviolet range, the structures of interface layers were discussed [28]. We have also developed the observation system in order to perform real time *in-situ* observa‐ tion of SiC oxidation [29] for the first time. By using this system, we have found the enhance‐ ment of oxidation rate of SiC in thin-thickness regime less than several nm [30,31] as in the case of Si oxidation, and discussed on the oxidation and interface layer formation mechanisms [32]. These results have led to the proposal of a novel oxidation mechanism of SiC, i.e., "interfacial Si-C emission model" [33].

In this paper, the measurements of the depth profile of the refractive indices of thermal oxidation layers on SiC by using spectroscopic ellipsometry are described in Section 2, followed by the characterization of the interface layers, and their relation to the electrical properties of MOS diodes in Section 3, the real-time observation of SiC oxidation in Section 4, and the discussions on the SiC oxidation process and interface layer formation process based on SiC oxidation mechanisms in Section 5, and finally we summarize the investigations of SiC/ oxide interface structures by using spectroscopic ellipsometry. All the spectroscopic ellips‐ ometry measurements in this chapter were performed using a commercial spectroscopic ellipsometer typed GESP-5 (Sopra), typically at an angle of incidence of 75°.

### **2. Measurements of the depth profile of the refractive indices of thermal oxidation layers on SiC**

#### **2.1. Thickness dependence of apparent refractive indices of oxide films**

The (0001) Si-faces of commercial 6H polytype SiC epilayers, 5 µm in thickness and n-type with the carrier concentration of 5 × 1015cm-3, were oxidized by two methods, pyrogenic oxidation and oxidation in dry oxygen flow, so-called dry oxidation [25]. Pyrogenic oxidation was conducted at 1100°C in a flow of oxygen and hydrogen gases for 1-8 h. Dry oxidation was conducted at 1000°C in a flow of oxygen for 4-16 h. Ellipsometry measurements were per‐ formed in the wavelength range from 250 to 850 nm. We have derived the optical constants and the thickness of the oxide films under the assumption that the films have an optically single-layer structure and have uniform and isotropic optical properties. Here, we call the refractive indices obtained under the model of a single layer as "apparent refractive indices", in order to distinguish from those by use of a two-layers model mentioned in the next section. The wavelength dependence of the refractive indices of oxide films were assumed to follow Sellmeier's dispersion law,

of XRR and FTIR spectroscopy have been reported so far. The effects of NO annealing after oxidation of SiC to the interface structures and electrical properties were studied by use of XRR measurements for 6H-SiC [21] and 4H-SiC [22]. FT-IR spectroscopy by using attenuated total reflection (ATR) method has been performed to know the structures of the ultra-thin oxides on SiC [23,24]. The differences in stress and chemical state of oxides and oxide/SiC interface have been studied from the observation of TO and LO mode absorption due to Si-O-Si bond asymmetric stretching vibration for the oxides on Si- and C-faces of 6H-SiC and 4H-SiC.

We have employed spectroscopic ellipsometry for observing the SiC/oxide interface to investigate SiC/oxide interface structures. We have developed the characterization method of the oxide layers and SiC/oxide interfaces, i.e., the method using sloped oxide layers, and made clear the depth profile of the refractive indices and interface structures, i.e., there exist interface layers, around 1 nm in thickness, having high refractive indices [25,26], the values of which closely relate to the electrical properties of MOS diodes [27]. By the extension of measurement of wavelength to deep ultraviolet range, the structures of interface layers were discussed [28]. We have also developed the observation system in order to perform real time *in-situ* observa‐ tion of SiC oxidation [29] for the first time. By using this system, we have found the enhance‐ ment of oxidation rate of SiC in thin-thickness regime less than several nm [30,31] as in the case of Si oxidation, and discussed on the oxidation and interface layer formation mechanisms [32]. These results have led to the proposal of a novel oxidation mechanism of SiC, i.e.,

In this paper, the measurements of the depth profile of the refractive indices of thermal oxidation layers on SiC by using spectroscopic ellipsometry are described in Section 2, followed by the characterization of the interface layers, and their relation to the electrical properties of MOS diodes in Section 3, the real-time observation of SiC oxidation in Section 4, and the discussions on the SiC oxidation process and interface layer formation process based on SiC oxidation mechanisms in Section 5, and finally we summarize the investigations of SiC/ oxide interface structures by using spectroscopic ellipsometry. All the spectroscopic ellips‐ ometry measurements in this chapter were performed using a commercial spectroscopic

**2. Measurements of the depth profile of the refractive indices of thermal**

The (0001) Si-faces of commercial 6H polytype SiC epilayers, 5 µm in thickness and n-type with the carrier concentration of 5 × 1015cm-3, were oxidized by two methods, pyrogenic oxidation and oxidation in dry oxygen flow, so-called dry oxidation [25]. Pyrogenic oxidation was conducted at 1100°C in a flow of oxygen and hydrogen gases for 1-8 h. Dry oxidation was conducted at 1000°C in a flow of oxygen for 4-16 h. Ellipsometry measurements were per‐ formed in the wavelength range from 250 to 850 nm. We have derived the optical constants

ellipsometer typed GESP-5 (Sopra), typically at an angle of incidence of 75°.

**2.1. Thickness dependence of apparent refractive indices of oxide films**

"interfacial Si-C emission model" [33].

102 Advanced Silicon Carbide Devices and Processing

**oxidation layers on SiC**

$$m = \sqrt{1 + \frac{\left(n\_{\rm inj}^2 - 1\right) \mathcal{X}^2}{\mathcal{X}^2 - \mathcal{X}\_0^2}},\tag{1}$$

where parameter *n*inf is the refractive index of the wavelength at infinity, while parameter *λ*<sup>0</sup> is the wavelength corresponding to characteristic oscillation. Here, we assumed the extinction coefficient *k* = 0 over the wavelength range measured. The values of the thickness of the film and the parameters *n*inf and *λ*<sup>0</sup> were derived by fitting the wavelength-dependence curves of calculated ellipsometric parameters (*Ψ*, *∆*) to the measured ones. The surface roughness of the oxide films on SiC was examined by means of atomic force microscopy (AFM) measurement, and the root mean square of the surface roughness is around 0.2 nm.

Figure 2(a) shows the wavelength dependences of the refractive indices of the oxide films, thickness of which are both 20 nm, oxidized with two different methods, i.e., pyrogenic and dry oxidation. For comparison, the values for oxide films on Si are also shown in the figure. It is found from the figure that the refractive indices of the oxide films on SiC are both smaller than those of the oxide films on Si at all the wavelengths measured. The figure also reveals that the refractiveindices fordryoxidationaresmallerthanthoseforpyrogenicoxidation.Therefractive indices increase with oxidation time or oxide thickness and reaching to the values for oxide films on Si, though the values of all the films are smaller than those of oxide on Si. The thick‐ ness dependences of the refractive indices at the wavelength of 630 nm for dry oxidation are shown in Figure 2(b). For pyrogenic oxidation,the refractive indices decrease with the decrease of film thickness as in the case of dry oxidation. It has been reported that, for Si, the refractive indices of the oxide films increase with the decrease of film thickness, as shown by the dotted line in the figures [7], which is quite different from those for the oxide films on SiC reported here.In Si oxidation,the increase ofrefractive indices along with thedecrease of oxide thickness has been explained by the existence of the transition layers, i.e., suboxide layers SiO*x* with *x* < 2 at Si/SiO2 interfaces, whose refractive indices are larger than those of SiO2, while the decrease ofrefractiveindicesforSiCoxidationcannotbeexplainedbytheexistenceofaSiC-SiO2 transition layers. As the refractive indices of SiC are larger than those of SiO2, the refractive indices of transition layer, i.e., the SiC-SiO2 mixed layer SiC*x*O*y* should be larger than those of SiO2.

As another candidate to explain these phenomena, the roughness of SiC/oxide interfaces can be considered. The roughness observed by AFM shows that there exists rugged structure with the various peak to valley height and interval over the surface much less than 1 nm, which are both much smaller than the wavelength of light used in ellipsometry measurements. In such a case, i.e., the case that the wavelength of a prove beam is much larger than the scale of surface microstructures, the rough surface can be treated as the existence of an optically equivalent layer having the composition of the mixture of the adjacent layers of interface. Therefore, the refractive indices of optically equivalent layers corresponding to rough interface are also the values between the refractive indices of SiC and those of SiO2, i.e., larger than those of SiO2, and thus small refractive indices of oxide films cannot be explained by the effect of interface roughness.

**Figure 2.** (a) Wavelength dependences of the refractive indices of oxide films formed by dry and pyrogenic oxidation. (b) Oxide thickness dependence of refractive indices of oxide films by dry oxidation. The dotted lines show the values for oxide film on Si [25].

#### *figure\_2.* **2.2. Measurements of the depth profile of the refractive indices using sloped oxide films**

In the previous section, the apparent refractive indices *n*app obtained under the assumption of an optically single layer structure are shown to be smaller than those of the oxide films on Si, and increase with oxide film thickness, reaching the values of Si oxides of around 60 nm in thickness. To make clear why these apparent refractive indices change with oxidation time or oxide thickness, the depth profile of the refractive indices of oxide films on SiC was measured by spectroscopic ellipsometry [26].

For measurements of the depth profile or thickness dependence of the refractive indices of oxide films, we have proposed the method of using a slope-shaped oxide films. The pieces of SiC substrates with oxide layers were immersed gradually in buffered hydrogen fluoride at a constant speed to form slope-shaped oxide layers. The schematic illustration of the method is shown in Figure 3 [34]. Using the sloped oxide films, it is possible to measure the optical properties of the oxide films having various thicknesses using one sample. This means only the film thickness changes along the slope, though the interface structures are the same for all positions, i.e., for all oxide thicknesses. Of course, oxide films with various thicknesses can also be obtained by changing the oxidation time. By this method, however, there is a fear of change in the film structures, particularly the interface structures with the oxidation time.

(0001) Si-faces of n-type 6H-SiC epilayers having 5 µm in thickness and the carrier concentra‐ tion of 5 × 1015 cm-3 were used for the study. The epilayer surfaces were oxidized in dry oxygen flow at 1100°C for 16 h to form the oxide films with around 60 nm in thickness. The sloped

**Figure 3.** Schematic illustration of the method to fabricate a slope-shaped oxide film on SiC.

microstructures, the rough surface can be treated as the existence of an optically equivalent layer having the composition of the mixture of the adjacent layers of interface. Therefore, the refractive indices of optically equivalent layers corresponding to rough interface are also the values between the refractive indices of SiC and those of SiO2, i.e., larger than those of SiO2, and thus small refractive indices of oxide films cannot be explained by the effect of interface

*figure\_2.*

(b)

1.30 <sup>0</sup> <sup>10</sup> <sup>20</sup> <sup>30</sup> <sup>40</sup> <sup>50</sup> <sup>60</sup> <sup>70</sup>

Oxide thickness (nm)

roughness.

104 Advanced Silicon Carbide Devices and Processing

1.38 1.40 1.42 1.44 1.46 1.48 1.50

for oxide film on Si [25].

by spectroscopic ellipsometry [26].

R

efractive index *n*app

200 300 400 500 600 700 800 900

Wavelength (nm)

pyrogenic

Pyrogenic Dry

Oxide on Si

(a)

1.50

1.40

Refractive index *n*app

**Figure 2.** (a) Wavelength dependences of the refractive indices of oxide films formed by dry and pyrogenic oxidation. (b) Oxide thickness dependence of refractive indices of oxide films by dry oxidation. The dotted lines show the values

**2.2. Measurements of the depth profile of the refractive indices using sloped oxide films**

In the previous section, the apparent refractive indices *n*app obtained under the assumption of an optically single layer structure are shown to be smaller than those of the oxide films on Si, and increase with oxide film thickness, reaching the values of Si oxides of around 60 nm in thickness. To make clear why these apparent refractive indices change with oxidation time or oxide thickness, the depth profile of the refractive indices of oxide films on SiC was measured

For measurements of the depth profile or thickness dependence of the refractive indices of oxide films, we have proposed the method of using a slope-shaped oxide films. The pieces of SiC substrates with oxide layers were immersed gradually in buffered hydrogen fluoride at a constant speed to form slope-shaped oxide layers. The schematic illustration of the method is shown in Figure 3 [34]. Using the sloped oxide films, it is possible to measure the optical properties of the oxide films having various thicknesses using one sample. This means only the film thickness changes along the slope, though the interface structures are the same for all positions, i.e., for all oxide thicknesses. Of course, oxide films with various thicknesses can also be obtained by changing the oxidation time. By this method, however, there is a fear of change

in the film structures, particularly the interface structures with the oxidation time.

(0001) Si-faces of n-type 6H-SiC epilayers having 5 µm in thickness and the carrier concentra‐ tion of 5 × 1015 cm-3 were used for the study. The epilayer surfaces were oxidized in dry oxygen flow at 1100°C for 16 h to form the oxide films with around 60 nm in thickness. The sloped

dry

oxide films were fabricated by the method mentioned above, and ellipsometry measurements have been carried out at the positions along the slope.

Firstly, we have obtained the apparent refractive indices and film thickness assuming an optically single-layer structure with uniform optical properties, same as in Section 2.1. The variations of oxide thickness in the measured position along the slope are shown in Figure 4(a). From the figure, it is found that the oxide thickness changes almost linearly with the position, except in very small oxide thickness region, which means that the oxide films were etched at an angle as expected. Figure 4(b) shows the changes in *n*app along the slope at the wavelength *λ* = 630 nm, for example. Figure 5 shows those as a function of oxide thickness. The refractive indices decrease with film thickness at all the wavelengths measured as in the case at 630 nm. It is found from the figure that *n*app at 60 nm in thickness is around 1.45, which is almost the same as that reported for stoichiometric SiO2, i.e., fused quartz. With the decrease of oxide film thickness, the value of *n*app decreases gradually. At the positions with oxide thickness smaller than 5 nm, the values of *n*app decrease markedly with the decrease of oxide thickness and approaches 1 at the position of the oxide film thickness = 0. As this feature is nearly the same as those observed for the oxide films formed by other oxidation methods mentioned in Section 2.1, it can be said that *n*app decreases with decreasing oxide film thickness regardless of the oxidation method.

These results contradict the assumption used for the evaluation of the refractive indices and the thickness from the measured ellipsometeric parameters, i.e., the films are composed of optically single layers and have uniform and isotropic optical properties. This contradiction, therefore, suggests that this assumption is inadequate for the analysis. Then, we have consid‐ ered the film structure models that can explain the thickness dependence of the refractive indices obtained from the ellipsometry measurements. For the oxide films on Si, it has been said there exists a compositional transition layer at the interface between Si and oxide [7]. Similarly, for the oxide films on SiC, it can be considered the presence of a transition layer at

**Figure 4.** (a) Oxide thickness and (b) apparent refractive indices (*λ* = 630 nm) of a sloped oxide film on SiC along the slope [26].

*figure\_4.*

*figure\_5.*

**Figure 5.** Thickness dependence of *n*app of an oxide film on SiC at *λ* = 630 nm [26].

the interface between SiC and oxide layer. However, we have failed to explain the thickness dependences of *n*app observed by the model taking into account the presence of the transition layer, the optical constants of which changes gradually from those of SiC to those of SiO2.

Then, we attempted to obtain the optical properties of interface layers under the assumption of two-layers structure model, i.e., the structure of stoichiometric SiO2 layer/interface layer/SiC substrates. Here, we assumed the presence of interface layers, not a transition layer but the layer having the wavelength dependence of the refractive indices of the interface layers that follows Sellmeier's dispersion law given by Eq. (1). We have used the optical constant of fused quartz for stoichiometric SiO2. We have obtained the fitting parameters *n*inf and *λ*<sup>0</sup> appeared in Eq. (1) and the thicknesses of interface layer and SiO2 layer from the ellipsometry parameters measured as a function of wavelength. Figures 6(a) and (b) shows the values of the thicknesses of the SiO2 layers and the interface layers, and the values of *n*inf and *λ*0, obtained at each measurement position, respectively. It is found from the figures that the thickness of the SiO2 layer changes almost linearly along the slope, and the thickness and the parameters *n*inf and *λ*0 of the interface layers do not change but are almost constant over the positions measured. These results indicate that the thickness dependence of *n*app in oxide films on SiC can be explained by changing the thickness of the SiO2 layer only, which suggest that the SiO2 layer lies on the interface layer having the refractive indices given by the Sellmeier's equation with the parameter values *n*inf ∼4 and *λ*<sup>0</sup> ∼ 0.15 and the thickness ∼1 nm. As the parameter *n*inf in Sellmeier's equation indicates the refractive index at long wavelengths, this means that there exist interface layers, around 1 nm in thickness with the refractive indices higher than those of SiC and SiO2 (*n* = 2.6 and 1.45 at *λ* = 630 nm, respectively). These results strongly suggest that the interface layers are not mixed layers between SiC and SiO2, i.e., neither transition layers nor optically equivalent layer due to interface roughness.

**Figure 6.** (a) Thicknesses of the SiO2 and the interface layers, and (b) the Sellmeier's parameters *n*inf and *λ*<sup>0</sup> of the inter‐ face layers as a function of the measurement position [26].

*figure\_6.* We have derived the refractive indices of the interface layers *n*it as a function of wavelength on the assumption of the Sellmeier's dispersion law for refractive indices and the extinction coefficient *k*it = 0. This is not self-explanatory in general. Then, we attempted to derive the optical constants of the interface layers at each wavelength from the measured (*Ψ, ∆*) values without using any assumption for optical constants [35]. The results reveal that the values of extinction coefficient are in the order of 0.1 though the values vary widely. The values of the refractive indices obtained at each wavelength almost agree with the values calculated from the values of *n*inf and *λ*0 obtained under the assumption of *k*it = 0 and the Sellmeier's dispersion law for *n*it. These results suggest that the assumption of the Sellmeier's dispersion law for *n*it is also reasonable.

the interface between SiC and oxide layer. However, we have failed to explain the thickness dependences of *n*app observed by the model taking into account the presence of the transition layer, the optical constants of which changes gradually from those of SiC to those of SiO2.

Oxide thickness (nm)

0 10 20 30 40 50 70 60

**Figure 4.** (a) Oxide thickness and (b) apparent refractive indices (*λ* = 630 nm) of a sloped oxide film on SiC along the

Apparent refractive index *napp*

1.50

1.40

1.30

1.10

1.20

1.00

**Figure 5.** Thickness dependence of *n*app of an oxide film on SiC at *λ* = 630 nm [26].

slope [26].

106 Advanced Silicon Carbide Devices and Processing

*figure\_4.*

*figure\_5.*

Then, we attempted to obtain the optical properties of interface layers under the assumption of two-layers structure model, i.e., the structure of stoichiometric SiO2 layer/interface layer/SiC substrates. Here, we assumed the presence of interface layers, not a transition layer but the layer having the wavelength dependence of the refractive indices of the interface layers that follows Sellmeier's dispersion law given by Eq. (1). We have used the optical constant of fused quartz for stoichiometric SiO2. We have obtained the fitting parameters *n*inf and *λ*<sup>0</sup> appeared in Eq. (1) and the thicknesses of interface layer and SiO2 layer from the ellipsometry parameters measured as a function of wavelength. Figures 6(a) and (b) shows the values of the thicknesses of the SiO2 layers and the interface layers, and the values of *n*inf and *λ*0, obtained at each measurement position, respectively. It is found from the figures that the thickness of

We have analyzed the interface layers for various formation methods of oxide, i.e., dry oxidation and low-temperature deposition of oxide (LTO), as well as pyrogenic oxidation. Dry oxidation was done in the pure oxygen flow at 1100°C for 16 h. Pyrogenic oxidation was done in a hydrogen-oxygen flame at 1100°C for 8 h. LTO films were deposited by low-pressure chemical vapor deposition (LPCVD) using SiH4 and O2 gases at 400°C and post-oxidation annealing (POA) in Ar atmosphere was performed at 1200°C for 1 h [36]. For all of the samples, the values of parameter *n*inf and *λ*0 are almost constant against oxide film thickness. Therefore, the results of the ellipsometric measurements along the slope of the oxide films can be explained by two-layers mode mentioned above regardless of oxide formation methods. All the values of the refractive indices calculated using the values of *n*inf and *λ*<sup>0</sup> obtained for three oxide films are higher than those of stoichiometric SiO2 and bulk SiC. The values of *n*inf depend on the oxidation process, and the values for LTO films are smaller than those for pyrogenic and dry oxidation, though the values of *λ*0 are not different largely among these three layers.

From these results, we can conclude that there exist interface layers, having high refractive indices compared with those of SiC and SiO2, the values of which depend on the oxide layer formation method, around 1 nm in thickness, at oxide/SiC interface and only the thickness of the SiO2 layers changes with oxidation time or oxide thickness. It can be said that the optical properties estimated form the analysis using the single layer model mentioned in the previous section, i.e., the oxide films are assumed to be optically uniform single layer on SiC, are "apparent" features and it is not true that the optical constants of the oxide layers change with oxidation time or oxide thickness.

### **3. Characterization of the interfaces between SiC and oxides, and their relation to the electrical properties of MOS diodes**

#### **3.1. Characterization of the optical properties of interface layers between SiC and oxide**

In the previous sections, it is said that the refractive indices of interface layers depend on the oxide layer formation process. For example, the values of *n*inf for LTO films are smaller than those of pyrogenic and dry oxidation, while the LTO films are known to have lower interface state densities and effective oxide charge density than those of thermally oxidized films. Therefore, these results suggest the values of *n*inf of the interface layers may be related to the electrical properties of SiC MOS structures in some extent. The large refractive indices evaluated suggest the existence of bonds with large polarization, like Si-Si bonds at the interface, which may influence on the electrical properties of the interfaces.

We have evaluated the oxide/SiC interfaces by spectroscopic ellipsometry measurements in the spectral range between 1.4 and 4.3 eV in Section 2. It has been reported in the studies on Si/oxide interfaces that the wavelength of optical constants in the absorption region, i.e., direct interband transition region, gives the information on a structural defect near the interfaces, such as oxide-induced stacking fault [37] and interface strain [5] because these defects bring about the shift of peaks corresponding to critical point. For Si, the absorption peak corre‐ sponding to *E*<sup>1</sup> (3.35eV) point locates in the visible to ultraviolet (UV) spectral range as shown in Figure 7 [38,39]. Therefore, the measurements in visible and ultraviolet spectral ranges can be reflected from the direct optical transition of Si. The band gap energy of 4H-SiC, for example, is 3.2 eV, which can be covered in the measurements mentioned above i.e., 250-850 nm or 4.96-1.46 eV. However, its absorption is very small up to around 4eV because SiC is an indirect energy bandgap semiconductor, and the absorption rises up near the direct transitions, for example, *E*<sup>0</sup> (5.65eV for 4H-SiC) [40]. Thus, the measurements including the deep UV (DUV) spectral range may be capable to give more information on the SiC/oxide interface structures. Therefore, to obtain the information on the properties in direct interband transition region, we have expanded the wavelength range of the spectroscopic ellipsometry to deep UV region, i.e., to 200 nm, or 6.0 eV, which covers the *E*0 peak of 4H-SiC [28].

the results of the ellipsometric measurements along the slope of the oxide films can be explained by two-layers mode mentioned above regardless of oxide formation methods. All the values of the refractive indices calculated using the values of *n*inf and *λ*<sup>0</sup> obtained for three oxide films are higher than those of stoichiometric SiO2 and bulk SiC. The values of *n*inf depend on the oxidation process, and the values for LTO films are smaller than those for pyrogenic and dry oxidation, though the values of *λ*0 are not different largely among these three layers. From these results, we can conclude that there exist interface layers, having high refractive indices compared with those of SiC and SiO2, the values of which depend on the oxide layer formation method, around 1 nm in thickness, at oxide/SiC interface and only the thickness of the SiO2 layers changes with oxidation time or oxide thickness. It can be said that the optical properties estimated form the analysis using the single layer model mentioned in the previous section, i.e., the oxide films are assumed to be optically uniform single layer on SiC, are "apparent" features and it is not true that the optical constants of the oxide layers change with

**3. Characterization of the interfaces between SiC and oxides, and their**

**3.1. Characterization of the optical properties of interface layers between SiC and oxide**

In the previous sections, it is said that the refractive indices of interface layers depend on the oxide layer formation process. For example, the values of *n*inf for LTO films are smaller than those of pyrogenic and dry oxidation, while the LTO films are known to have lower interface state densities and effective oxide charge density than those of thermally oxidized films. Therefore, these results suggest the values of *n*inf of the interface layers may be related to the electrical properties of SiC MOS structures in some extent. The large refractive indices evaluated suggest the existence of bonds with large polarization, like Si-Si bonds at the

We have evaluated the oxide/SiC interfaces by spectroscopic ellipsometry measurements in the spectral range between 1.4 and 4.3 eV in Section 2. It has been reported in the studies on Si/oxide interfaces that the wavelength of optical constants in the absorption region, i.e., direct interband transition region, gives the information on a structural defect near the interfaces, such as oxide-induced stacking fault [37] and interface strain [5] because these defects bring about the shift of peaks corresponding to critical point. For Si, the absorption peak corre‐ sponding to *E*<sup>1</sup> (3.35eV) point locates in the visible to ultraviolet (UV) spectral range as shown in Figure 7 [38,39]. Therefore, the measurements in visible and ultraviolet spectral ranges can be reflected from the direct optical transition of Si. The band gap energy of 4H-SiC, for example, is 3.2 eV, which can be covered in the measurements mentioned above i.e., 250-850 nm or 4.96-1.46 eV. However, its absorption is very small up to around 4eV because SiC is an indirect energy bandgap semiconductor, and the absorption rises up near the direct transitions, for example, *E*<sup>0</sup> (5.65eV for 4H-SiC) [40]. Thus, the measurements including the deep UV (DUV)

**relation to the electrical properties of MOS diodes**

interface, which may influence on the electrical properties of the interfaces.

oxidation time or oxide thickness.

108 Advanced Silicon Carbide Devices and Processing

**Figure 7.** Photon energy dependences of the real and imaginary parts of dielectric constants for bulk Si and 4H-SiC [38,39].

*figure\_7.* Epitaxial wafers of 4H-SiC with 8° off-oriented (0001) Si-faces, n-types, were used in this study. A sample was oxidized at 1100°C in a dry oxygen atmosphere. By the oxidation for various time from 2.4 to 14.5 h, we obtained the oxide layers from 15.5 to 42.2 nm in thickness. The ellipsometric measurements were performed in the photon energy range between 2.0 and 6.0 eV. For the analysis of oxide layers on SiC, we used a two-layers structure model, i.e., the oxide layers are composed of a SiO2 layer having the refractive indices for stoichiometric SiO2 composition and an interface layer lain on SiC. Firstly, in the energy range between 2.0 and 4.0 eV, we evaluated the thicknesses of oxide layer and interface layer by fitting the calculated (*Ψ, ∆*) spectra to the measured values in this energy range. Here, we used the modified Sellmeier's dispersion relation, which takes into consideration of weak absorption, because the optical absorption of the interface is considered to be quite small in this photon energy range.

$$\varepsilon\_1 = 1 + \frac{\left(n\_{\rm inf}^2 - 1\right)\lambda^2}{\lambda^2 - \lambda\_0^2}, \text{ } \varepsilon\_2 = \frac{\text{C}\_1}{\lambda} + \frac{\text{C}\_2}{\lambda^2} + \frac{\text{C}\_3}{\lambda^3},\tag{2}$$

where *ε*1 and *ε*<sup>2</sup> are the real and imaginary parts of dielectric constant, respectively, *n*inf and *λ*<sup>0</sup> are the refractive index of the wavelength at infinity, and the characteristic oscillation wave‐ length, respectively, and *C*1, *C*2, and *C*<sup>3</sup> are the fitting parameters for the optical absorption, so that we could obtain the thickness and optical constants of the interface layer as well as the SiO2 layer thickness. After the determination of the SiO2 and interface layer thicknesses in 2.0-4.0 eV range, by using these thickness values, the optical constants (*n*it*, k*it) of the interface layer were evaluated at each photon energy in the entire range from 2.0 to 6.0 eV from the ellipsometric parameters (*Ψ, ∆*) measured at the corresponding energies.

The thicknesses of the interface layers obtained are almost constant around 1 nm for all the oxide thicknesses measured. Figure 8 shows the photon energy dependence of *n*it*,* and *k*it, of the interface layer at various oxide thicknesses from 15.7 to 42.2 nm. In the figure, the values of *n* and *k* for 4H-SiC are also shown by the red-colored lines. The values of optical constants in the range between 2 and 4 eV derived at each photon energy agree well with those obtained by use of the Sellmeier's relation determined by curve fitting in the same energy range. This agreement indicates that the structural model used in the analysis of ellipsometric data is appropriate. The figure suggests that the photon energy dispersion of *n*it is quite similar to that of SiC, though the absolute values are around 1 larger than those of SiC, and slightly decreases with oxide thickness, and the differences between the interface layer and SiC tend to increase with photon energy. The photon energy dispersion of *k*it is seen to be quite similar to that of SiC in entire energy range, i.e., nearly zero below 4 eV and a rise at around 5 eV.

The experimental results can be summarized as follow. There exists an interface layer of about 1 nm in thickness, though the absolute values of refractive index are 0.5-1 larger than that of SiC. The optical constants of the interface layer have similar energy dispersion to those of SiC in the photon energy range from 2.0 and 6.0 eV. These results indicate the existence of an interface layer, the material of which has a similar band structure as that of SiC. This leads the conclusion that the interface layer is not the transition layer between SiC and SiO2, but a material having the modified structure and/or composition from SiC.

In the case of the thickest oxide sample, the energy where *k*it rises up is smaller than that of bulk 4H-SiC. Nguyen et al. [5] evaluated the photon energy dependence of the dielectric constants of the interface layers for Si and found a red shift of 0.042 eV of the interband critical point *E*1 (3.35eV) compared with the bulk silicon values, and concluded there exists a strain layer of Si by the compressive stress due to the lattice expansion by oxidation, as well as the layer due to rough interface or transition of composition less than 0.7 nm in thickness. Our result of the increase of *kit* in the deep UV region for the thickest oxide of SiC can be explained by the red shift of *E*0 peak of SiC due to the increase of interfacial strain accompanied with oxidation, because the expansion of Si bond due to oxidation is expected also for SiC.

We will discuss on the formation mechanisms and the structures of interface layers in Sections 4 and 5, relating with the oxidation mechanisms of SiC.

#### **3.2. Relation between the optical and electrical properties of interface layers**

#### **i. Performance of spectroscopic ellipsometry measurements and** *C*-*V* measurements on the same samples

It is found that there exist interface layers around 1 nm in thickness and the refractive indices *n*it depend on the oxidation conditions, i.e., oxidation method and oxidation temperature, which suggests that the values of *n*it may reflect the change of the interface structures to some extent. Under these considerations, we have tried to investigate SiO2/4H-SiC interfaces by using capacitance-voltage (*C*-*V*) measurements and FTIR spectroscopy, in parallel with spectroscopic ellipsometry measurements [41]. In the cases of the oxide layers formed by dry oxygen, we found high densities of interface trap, larger shift of *C*-*V* curve along the gate

The thicknesses of the interface layers obtained are almost constant around 1 nm for all the oxide thicknesses measured. Figure 8 shows the photon energy dependence of *n*it*,* and *k*it, of the interface layer at various oxide thicknesses from 15.7 to 42.2 nm. In the figure, the values of *n* and *k* for 4H-SiC are also shown by the red-colored lines. The values of optical constants in the range between 2 and 4 eV derived at each photon energy agree well with those obtained by use of the Sellmeier's relation determined by curve fitting in the same energy range. This agreement indicates that the structural model used in the analysis of ellipsometric data is appropriate. The figure suggests that the photon energy dispersion of *n*it is quite similar to that of SiC, though the absolute values are around 1 larger than those of SiC, and slightly decreases with oxide thickness, and the differences between the interface layer and SiC tend to increase with photon energy. The photon energy dispersion of *k*it is seen to be quite similar to that of

SiC in entire energy range, i.e., nearly zero below 4 eV and a rise at around 5 eV.

material having the modified structure and/or composition from SiC.

4 and 5, relating with the oxidation mechanisms of SiC.

on the same samples

110 Advanced Silicon Carbide Devices and Processing

The experimental results can be summarized as follow. There exists an interface layer of about 1 nm in thickness, though the absolute values of refractive index are 0.5-1 larger than that of SiC. The optical constants of the interface layer have similar energy dispersion to those of SiC in the photon energy range from 2.0 and 6.0 eV. These results indicate the existence of an interface layer, the material of which has a similar band structure as that of SiC. This leads the conclusion that the interface layer is not the transition layer between SiC and SiO2, but a

In the case of the thickest oxide sample, the energy where *k*it rises up is smaller than that of bulk 4H-SiC. Nguyen et al. [5] evaluated the photon energy dependence of the dielectric constants of the interface layers for Si and found a red shift of 0.042 eV of the interband critical point *E*1 (3.35eV) compared with the bulk silicon values, and concluded there exists a strain layer of Si by the compressive stress due to the lattice expansion by oxidation, as well as the layer due to rough interface or transition of composition less than 0.7 nm in thickness. Our result of the increase of *kit* in the deep UV region for the thickest oxide of SiC can be explained by the red shift of *E*0 peak of SiC due to the increase of interfacial strain accompanied with

oxidation, because the expansion of Si bond due to oxidation is expected also for SiC.

**3.2. Relation between the optical and electrical properties of interface layers**

We will discuss on the formation mechanisms and the structures of interface layers in Sections

**i. Performance of spectroscopic ellipsometry measurements and** *C*-*V* measurements

It is found that there exist interface layers around 1 nm in thickness and the refractive indices *n*it depend on the oxidation conditions, i.e., oxidation method and oxidation temperature, which suggests that the values of *n*it may reflect the change of the interface structures to some extent. Under these considerations, we have tried to investigate SiO2/4H-SiC interfaces by using capacitance-voltage (*C*-*V*) measurements and FTIR spectroscopy, in parallel with spectroscopic ellipsometry measurements [41]. In the cases of the oxide layers formed by dry oxygen, we found high densities of interface trap, larger shift of *C*-*V* curve along the gate

figure\_8. **Figure 8.** The photon energy dependences of optical constants, *nit* and *kit*, of the interface layers at various oxide thick‐ nesses for oxide films on Si-face of 4H-SiC by dry oxidation [28].

voltage axis and large leakage current from *C*-*V* measurements. FT-IR measurements suggest lower vibration frequency of the Si-O-Si stretching mode compared to that of fused quartz.

Based on these preliminary results, we have performed systematic studies on the SiC-oxide interfaces fabricated by various oxidation methods grown on SiC (0001) Si- and (000-1) C-face surfaces to make clear the relation between the refractive indices of interface layers derived from spectroscopic ellipsometry measurements and the interface sate densities derived from *C*-*V* measurements [27]. *C*-*V* measurements were performed on the same samples used in the ellipsometric measurements for the purpose of direct comparison between optical and electrical characteristics. Based on the results obtained, we have discussed on the structures of SiC/oxide interfaces related to the interface states which degrade the electrical properties of SiC-MOS structure, like channel mobility of the carriers.

For optical measurements, we have evaluated the refractive indices of the interfaces *n*it from the ellipsometric measurements by the analytical methods mentioned in the previous section as well as the results from XPS measurements [42]. To keep high sensitivity in the measure‐ ments over the wide photon energy range, i.e*.*, wide spectral range from deep UV to visible range, the measurements were carried out at the different angles of incidence of 70° and 75° for 1.5-2.0eV and 2.0-6.4 eV, respectively. For electrical measurements, we have performed high-frequency *C*-*V* measurements at 1 MHz for the same samples used in the optical meas‐ urements to evaluate interface state density *D*it by way of the Terman method.

These optical and electrical measurements using same samples have been carried out for the oxides grown on SiC with various growth conditions, i.e., dry and wet oxidation at 1000°C and 1100°C for Si-face, and dry oxidation at 900, 1000, and 1100°C, and wet oxidation at 900, 950, and 1000°C for C-face, as well as the samples with post-oxidation annealing. By using the results obtained from the measurements, we have compared the growth condition depend‐ ences of optical and electrical properties, i.e., refractive indices of interface *n*it and interface trap density *D*it to make clear the correlation between *n*it and *D*it.

#### **ii. Dependences of** *n***it and** *D***it on oxidation temperature, oxide method, and surface polarity**

Figures 9 and 10 show the values of optical constants *n*it and *k*it as a function of photon energy, and *D*it as a function of energy from the Fermi levels, for Si-face and C-face, respectively, oxidized by wet and dry oxidation at various oxidation temperatures. It is found from Figure 9 that the values of *n*it and *D*it for wet oxidation are both larger than those for dry oxidation, and both change little with oxidation temperature for Si face. While for C-face, as seen in Figure. 10, the values of *n*it and *D*it for dry oxidation are both larger than those for wet oxidation, and both change remarkably with oxidation temperature and increase with increasing oxidation temperatures for dry oxidation. Contrary, for wet oxidation, *D*it increases with increasing temperature as in the case of dry oxidation, but *n*it increases, i.e., the oxidation temperature dependences of *n*it has opposite tendency for dry oxidation. These results are summarized in Tables 1(a) and (b) for temperature, surface polarity and oxidation method dependences. We have found that the growth condition dependences of *n*it are well corresponding to those of *D*it, though the case of C-face oxidized by wet oxidation is an exception. The reasons of this exception have been discussed elsewhere [27], comparing with the researches on the oxidation temperature and oxidation method dependences of *D*it reported [36, 43-45].

**Figure 9.** Refractive index, *n*it, and extinction coefficient. *k*it, of the interface layer (a), and interface states density *D*it (b), for Si-face. The solid and broken lines in (a) show the optical constants of SiC and SiO2, respectively [27].

figure\_10.

The differences in *D*it for oxidation method, surface polarity and oxidation temperature have been reported by many researchers and the origins have been studied by use of, for example, XPS [46] and EPR [47].

high-frequency *C*-*V* measurements at 1 MHz for the same samples used in the optical meas‐

These optical and electrical measurements using same samples have been carried out for the oxides grown on SiC with various growth conditions, i.e., dry and wet oxidation at 1000°C and 1100°C for Si-face, and dry oxidation at 900, 1000, and 1100°C, and wet oxidation at 900, 950, and 1000°C for C-face, as well as the samples with post-oxidation annealing. By using the results obtained from the measurements, we have compared the growth condition depend‐ ences of optical and electrical properties, i.e., refractive indices of interface *n*it and interface

**ii. Dependences of** *n***it and** *D***it on oxidation temperature, oxide method, and surface**

Figures 9 and 10 show the values of optical constants *n*it and *k*it as a function of photon energy, and *D*it as a function of energy from the Fermi levels, for Si-face and C-face, respectively, oxidized by wet and dry oxidation at various oxidation temperatures. It is found from Figure 9 that the values of *n*it and *D*it for wet oxidation are both larger than those for dry oxidation, and both change little with oxidation temperature for Si face. While for C-face, as seen in Figure. 10, the values of *n*it and *D*it for dry oxidation are both larger than those for wet oxidation, and both change remarkably with oxidation temperature and increase with increasing oxidation temperatures for dry oxidation. Contrary, for wet oxidation, *D*it increases with increasing temperature as in the case of dry oxidation, but *n*it increases, i.e., the oxidation temperature dependences of *n*it has opposite tendency for dry oxidation. These results are summarized in Tables 1(a) and (b) for temperature, surface polarity and oxidation method dependences. We have found that the growth condition dependences of *n*it are well corresponding to those of *D*it, though the case of C-face oxidized by wet oxidation is an exception. The reasons of this exception have been discussed elsewhere [27], comparing with the researches on the oxidation

<sup>10</sup><sup>11</sup>

(b)

0.2 0.3 0.4 0.5 0.6 *E c -E* [eV]

wet1100<sup>o</sup> C wet1000<sup>o</sup> C

dry1100<sup>o</sup> C dry1000<sup>o</sup> C

<sup>10</sup><sup>12</sup>

*D*it [1/eV cm2

**Figure 9.** Refractive index, *n*it, and extinction coefficient. *k*it, of the interface layer (a), and interface states density *D*it (b),

for Si-face. The solid and broken lines in (a) show the optical constants of SiC and SiO2, respectively [27].

]

<sup>10</sup><sup>13</sup>

<sup>10</sup><sup>14</sup>

urements to evaluate interface state density *D*it by way of the Terman method.

trap density *D*it to make clear the correlation between *n*it and *D*it.

temperature and oxidation method dependences of *D*it reported [36, 43-45].

**polarity**

112 Advanced Silicon Carbide Devices and Processing

it

it

**Figure 10.** Refractive indices of the interface layer *n*it (a), and interface states density *D*it (b), for C-face [27].


**Table 1.** Oxidation temperature (a) and oxidation method and polarity dependences (b) of both the refractive indices of interface *n*it and interface state density *D*it

#### **iii. Effect of post-oxidation annealing on** *n***it and** *D***it** for wet oxidation

To understand the differences in *n*it and *D*it by oxidation method, we have performed postoxidation annealing (POA) in Ar and O2 atmosphere at 600°C for 3 h for wet oxidation samples based on the results reported [25]. Figures 11 and 12 show *n*it and *D*it values for Si- and C-face, respectively, with and without POA. The figures reveal that, for both polarities, the values of *n*it and *D*it come close to those for dry oxidation by POA. From these, it is considered that as grown samples by wet oxidation, hydrogen-related species terminate the dangling bonds of Si or C at the interface, and then they are removed by POA, which brings about the interface characteristic close to those for dry oxidation. The changes by annealing in oxygen and argon atmosphere are almost the same with each other for Si-face. Contrary, for C-face, the changes by annealing in oxygen are much larger than that in argon atmosphere, which is considered to be due to the oxidation even at around 600°C for C-face.

**Figure 11.** Changes in *n*it (a) and *D*it (b) on Si-face by POA for wet oxidation [27].

**Figure 12.** Changes in *n*it (a) and *D*it (b) on C-face by POA for wet oxidation [27].

#### **iv.** Effect of the change in oxidation rate on *n*it and *D*it for C-face

figure\_12. In Figures 9 and 10, the measurements were performed on the samples oxidized at the same temperatures for Si- and C-faces to know the surface polarity dependences of *n*it and *D*it. It is well known that the oxidation for C-face is around 10 times faster than that for Si-face. Therefore, these results were obtained from the oxides with different oxidation rates for Cand Si-faces. Then, we have prepared oxide films grown with same growth rate to avoid the influence from the growth rate to polarity dependence. The oxidation rate for C-face at 850°C is reported to be almost same as that for Si-face at 1100°C. The values of *n*it and *D*it for dry oxidation of C-face at various oxidation temperatures between 800°C and 1100°C as well as those of Si-face at 1100°C are shown in Figure 13. It is found from the figure that the differences i*n n*it and *D*it between the oxides for C-face at low temperatures and those for Si-face grown at 1100°C considerably reduce with decreasing oxidation temperature, which suggests that the lowering in the oxidation rate is quite effective for reducing *n*it and *D*it values. However, the method of changing oxidation temperature is possible to result in the change of the oxidation reaction process. Therefore, we have prepared the samples for C-face oxidized at the same temperature, 900°C, but with low oxygen partial pressure between 0.4 and 0.6 atm. However, similar tendency in the case of decreasing oxidation temperature for the values of *n*it and *D*it were obtained [27].

**Figure 13.** The values of *n*it (a) and *D*it (b) on C-face at oxidation temperatures between 800°C and 1100ºC [27].

figure\_11.

figure\_12.

0.2 0.3 0.4 0.5 0.6 E c -E [eV]

> dry900<sup>o</sup> C

0.2 0.3 0.4 0.5 0.6 E c -E [eV]

O<sup>2</sup> Ar

wet900<sup>o</sup> C O2 Ar

wet1100<sup>o</sup> C

dry1100<sup>o</sup> C

5.5 5.0 4.5 4.0 3.5 3.0

5.5 5.0 4.5 4.0 3.5 3.0

O<sup>2</sup> Ar

(a)

n

nit

(a)

114 Advanced Silicon Carbide Devices and Processing

2 3 4 5 6 Photon energy [eV]

**Figure 11.** Changes in *n*it (a) and *D*it (b) on Si-face by POA for wet oxidation [27].

dry900<sup>o</sup> C

> wet900<sup>o</sup> C

2 3 4 5 6 Photon energy [eV]

**Figure 12.** Changes in *n*it (a) and *D*it (b) on C-face by POA for wet oxidation [27].

**iv.** Effect of the change in oxidation rate on *n*it and *D*it for C-face

O2 Ar

> dry1100<sup>o</sup> C

10<sup>11</sup>

10<sup>11</sup>

(b)

10<sup>12</sup>

Dit [1/eV cm2

In Figures 9 and 10, the measurements were performed on the samples oxidized at the same temperatures for Si- and C-faces to know the surface polarity dependences of *n*it and *D*it. It is well known that the oxidation for C-face is around 10 times faster than that for Si-face. Therefore, these results were obtained from the oxides with different oxidation rates for Cand Si-faces. Then, we have prepared oxide films grown with same growth rate to avoid the influence from the growth rate to polarity dependence. The oxidation rate for C-face at 850°C is reported to be almost same as that for Si-face at 1100°C. The values of *n*it and *D*it for dry oxidation of C-face at various oxidation temperatures between 800°C and 1100°C as well as those of Si-face at 1100°C are shown in Figure 13. It is found from the figure that the differences i*n n*it and *D*it between the oxides for C-face at low temperatures and those for Si-face grown at 1100°C considerably reduce with decreasing oxidation temperature, which suggests that the lowering in the oxidation rate is quite effective for reducing *n*it and *D*it values. However, the method of changing oxidation temperature is possible to result in the change of the oxidation reaction process. Therefore, we have prepared the samples for C-face oxidized at the same temperature, 900°C, but with low oxygen partial pressure between 0.4 and 0.6 atm. However,

]

10<sup>13</sup>

10<sup>14</sup>

(b)

10<sup>12</sup>

Dit [1/eV cm2

]

10<sup>13</sup>

10<sup>14</sup>

wet1100<sup>o</sup> C

n

nit

#### figure\_13. **v. Verification of the correlation between** *n***it and** *D***it of interface layers by γ-ray irradiation**

We have found the refractive indices of interface layers measured by spectroscopic ellipsom‐ etry correlate well with the interface state density estimated by *C*-*V* measurements. To verify this correlation quantitatively, it is necessary to perform quantitative comparison between the changes of the interface state density and the refractive indices of the interfaces. It is well known that γ-lay irradiation brings about the increase of interface state density. Therefore, the quantitative correlation between the change in the refractive indices and interface state densities can be studied by performing *C*-*V* and ellipsometric measurements using the samples increased in interface state density artificially by γ-ray irradiation.

We have prepared the samples, interface state density of which were increased by γ-ray irradiation, and, for these samples, we have performed *C*-*V* and ellipsometric measurements before and after γ-ray irradiation [48]. Si-face of 6H-SiC with epilayers, 5 µm in thickness and n-type, 5 × 1015cm-3 were used. The epilayers were oxidized at 1100°C for 2 h by pyrogenic oxidation method to form oxide layers, around 30 nm in thickness. The ellipsometric meas‐ urements were carried out for the slope-shaped oxide films formed by gradually immersing the samples into BHF solution at a constant speed. After the optical measurement, the oxide layers were removed. Then, the samples were oxidized again, and Au and Al electrodes for gate and ohmic contacts, respectively, were formed on oxide layer and back surface of SiC substrate to form MOS diodes.

After *C*-*V* measurements, the samples were subjected to 60Co γ-ray for various duration times from 1 to 38 h (0.4-14.7 kC/kg with the rate of 2.58-3.87×102 C/kg h) at room temperature, and again *C*-*V* measurements were carried out. Finally, after the electrodes were removed, slopeshaped oxide films were formed and ellipsometric measurements were carried out. Optical analysis is the same as in the cases of that mentioned in the previous sections, i.e., using twolayers model composed of a SiO2 layer and an interface layer on SiC. The values of *n*inf and *λ*<sup>0</sup> parameters appeared in the Sellmeier's dispersion equation Eq. (1) for the interfaces of samples before and after γ-ray irradiation were measured.

The results reveal the values of *nint* increases, while that of *λ*0 show little change by γ-ray irradiation, i.e., the refractive indices of interface layer increase by γ-ray irradiation. The changes in the value of *n*inf, *∆n*inf and interface state density, *∆N<sup>i</sup>*<sup>t</sup> , are plotted as a function of absorption dose, where *N*it (cm-2) is the integration of *D*it (eV-1cm-2) by energy, and are shown in Figure 14 (a). Figure 14 (b) shows the relation between *∆n*inf and *∆N*it. The figure shows there exists a strong correlation between them, almost linear relation, though the data points are not so much. This result suggests the values of refractive indices of interface obtained from ellipsometery measurements are well reflected from the electrical properties of interface, like interface state density. Finally, it should be noted about the influence of γ-ray irradiation to the SiO2 layers. We have confirmed that the influence on the derivation of the refractive indices of the interface layers by the change in refractive index of SiO2 layer by γ-ray irradiation, around 0.02, is small enough to neglect.

**Figure 14.** (a) Changes in *n*inf, *∆n*inf and interface state density, *∆N<sup>i</sup>*<sup>t</sup> , as a function of γ-ray absorption dose, and (b) the relation between *∆n*inf and *∆N*it.

figure\_14.

#### **4. Real-time observation of SiC oxidation**

#### **4.1. Real-time observation of SiC oxidation using an in situ spectroscopic ellipsometer**

We have found that, in the thermal oxides on SiC, there exist interface layers, around 1 nm in thickness, with the optical constants having similar energy dispersion with SiC, though absolute values of refractive indices are around 1 higher than that of SiC. And, we also found that the values of refractive indices correlate well to the interface state density. As the interface structures may form during the oxidation, the interface structures should be closely related to oxidation mechanisms of SiC, and therefore, it is necessary to study the oxidation mechanisms to know the formation mechanism of the interface layer i.e., to make clear the origin of interface layers observed, which may lead how to reduce the interface state density at the SiC-oxide interface. Therefore, in order to elucidate the origin of the interface states, it is also important to know the mechanism of SiC oxidation, especially at the initial stage of oxidation. For these requirements, the precise measurements of oxidation rate, especially in very thin-thickness regime, are indispensable. Many studies have been performed on the oxidation time depend‐ ences of oxide films of SiC by use of various methods, including spectroscopic ellipsometry for various SiC polytypes [15-18,20]. In these studies, however, the measurements were performed after the oxidation, i.e., *ex-situ* measurements, where accurate oxide thickness as a function of oxidation time cannot be obtained because the oxidation proceeds even during rising and dropping in substrate temperature. Especially in small thickness range, i.e., the initial oxidation stage, this inaccuracy may bring about the difficulty in the precise study on the oxidation process. Therefore, to study on the mechanism of SiC oxidation in more detail, especially in initial stage of oxidation, a real-time observation technique is indispensable.

parameters appeared in the Sellmeier's dispersion equation Eq. (1) for the interfaces of samples

The results reveal the values of *nint* increases, while that of *λ*0 show little change by γ-ray irradiation, i.e., the refractive indices of interface layer increase by γ-ray irradiation. The

absorption dose, where *N*it (cm-2) is the integration of *D*it (eV-1cm-2) by energy, and are shown in Figure 14 (a). Figure 14 (b) shows the relation between *∆n*inf and *∆N*it. The figure shows there exists a strong correlation between them, almost linear relation, though the data points are not so much. This result suggests the values of refractive indices of interface obtained from ellipsometery measurements are well reflected from the electrical properties of interface, like interface state density. Finally, it should be noted about the influence of γ-ray irradiation to the SiO2 layers. We have confirmed that the influence on the derivation of the refractive indices of the interface layers by the change in refractive index of SiO2 layer by γ-ray irradiation,

**4.1. Real-time observation of SiC oxidation using an in situ spectroscopic ellipsometer**

We have found that, in the thermal oxides on SiC, there exist interface layers, around 1 nm in thickness, with the optical constants having similar energy dispersion with SiC, though absolute values of refractive indices are around 1 higher than that of SiC. And, we also found that the values of refractive indices correlate well to the interface state density. As the interface structures may form during the oxidation, the interface structures should be closely related to oxidation mechanisms of SiC, and therefore, it is necessary to study the oxidation mechanisms to know the formation mechanism of the interface layer i.e., to make clear the origin of interface layers observed, which may lead how to reduce the interface state density at the SiC-oxide interface. Therefore, in order to elucidate the origin of the interface states, it is also important

, are plotted as a function of

figure\_14.

, as a function of γ-ray absorption dose, and (b) the

before and after γ-ray irradiation were measured.

116 Advanced Silicon Carbide Devices and Processing

around 0.02, is small enough to neglect.

**Figure 14.** (a) Changes in *n*inf, *∆n*inf and interface state density, *∆N<sup>i</sup>*<sup>t</sup>

**4. Real-time observation of SiC oxidation**

relation between *∆n*inf and *∆N*it.

changes in the value of *n*inf, *∆n*inf and interface state density, *∆N<sup>i</sup>*<sup>t</sup>

We have developed an in situ ellipsometric measurement system, composed of a lamp-heated furnace and a spectroscopic ellipsometer (SOPRA,GESP5), to observe the SiC oxidation in real time. The details of the system are described elsewhere [29]. Figure 15 (a) illustrates schemat‐ ically the in situ spectroscopic ellipsometer we designed. The furnace has two optical windows for incident beam and reflected light beam from the sample surface for ellipsometric meas‐ urements. The fused quartz glass windows are angled so that the surfaces of the window glass are normal to the incident and reflected beams, i.e., inclined ±15° from the normal direction of the sample surface, to perform the ellipsometric measurements at an angle of incidence of 75°. The samples were heated up to a prescribed temperature between 600°C and 1200°C by the IR beam from a halogen lamp focused on the sample surface through the guiding quartz rod. The temperature of the samples was measured by using an IR radiation thermometer. The furnace was evacuated by a turbo molecular pump down to 2 × 10-6 Pa and Ar gas was introduced into the chamber during the measurement of optical constants of SiC substrate before oxidation at the oxidation temperature. Oxidations were performed by introducing dry oxygen and wet oxygen for dry and wet oxidations, respectively.

figure\_15. **Figure 15.** (a) Schematic diagram of the in situ spectroscopic ellipsometer we designed, and (b) an example of the ob‐ served values of (*Ψ, ∆*) over the oxidation time range from 5 min to 6 h in the case of the oxidation temperature 972°C. The values of *Ψ* and *∆* are plotted in the radius and angle in this pole figure, respectively.

Figure 15 (b) shows an example of the observed values of (*Ψ, ∆*), plotted on a pole figure coordinate, over the oxidation time range from 5 min to 6 h at 972°C. The experimental points (*Ψ, ∆*) move clockwise with oxidation time. It should be noted the merit of pole figure, i.e., *Ψ* and *∆* are shown by the radius and angle, respectively. Comparing with a right angle coordi‐ nate, there is no jump but connected at 0° and 360° or 2π in *∆*, and the figure reveals that the precision of *∆* depends on the absolute values of *Ψ*.

We have carried out real-time *in-situ* measurements at various growth temperatures between 893°C and 1147°C. The oxide thicknesses are plotted as a function of oxidation time in Figure 16. Compared with the previously reported results obtained from *ex situ* measurements [15,18], it is found from the figure that the data during the initial oxidation stage were obtained with much improved detail and much smaller spread.

For Si thermal oxidation, Deal and Grove [1] have considered two rate-determining processes, i.e., the reaction process at the interface and the process of oxygen diffusion through the oxide layer, and proposed, so-called, D-G-model, given as,

$$AX^2 + AX = B\left(1 + \tau\right) \tag{3}$$

where, *X*, *t* and *τ* are the oxide thickness, oxidation time, and initial oxidation time, respec‐ tively. *B/A* and *B* are denoted as the linear and parabolic rate constants of oxidation, respec‐ tively. Many researchers have applied D-G model to explain SiC oxidation [15, 18]. We also applied the D-G model to the results obtained from in situ ellipsometric measurements. The fitted curves derived using Eq. (3) are shown by the broken lines in Figure 16, which reveals that the fits are good at all the oxidation temperatures in our experiments. However, there is a discrepancy between the values of *B/A* and *B* obtained in this study and those reported by, for example, Song et al. [18], who modified D-G model for Si oxidation to that for SiC by taking into account the presence of carbon, i.e., adding the out diffusion process of CO from the interface to the surface. One of the reasons of this discrepancy is considered to be the difference of measurement method, i.e., the *ex-situ* measurements performed after the oxidation have been used in the previously reported studies, while we used *in-situ* real-time measurements and thus, the relations between oxide thickness and oxidation time can be precisely obtained. The reasons of these discrepancies in the values of rate constants appeared in D-G model between ours and those by Song et al. have been discussed in details by Goto et al. [49] with the relation of the oxide growth rate enhancement in thin thickness regime for SiC oxidation.

#### **4.2. Oxide growth rate enhancement of SiC in thin oxide regime**

In the previous section, we mentioned that real-time observation of SiC thermal oxidation using an *in-situ* ellipsometer has been performed for the first time and shown that the results are well explained by the D-G model. However, it has been reported that the oxidation behavior of Si in thin oxide thickness range cannot be explained using the D-G model, where the oxide growth rate enhancement has been found. Therefore, we have studied the initial oxidation stage of SiC in more details to make clear such an oxide growth rate enhancement occurs also for SiC or not.

figure\_16.

Figure 15 (b) shows an example of the observed values of (*Ψ, ∆*), plotted on a pole figure coordinate, over the oxidation time range from 5 min to 6 h at 972°C. The experimental points (*Ψ, ∆*) move clockwise with oxidation time. It should be noted the merit of pole figure, i.e., *Ψ* and *∆* are shown by the radius and angle, respectively. Comparing with a right angle coordi‐ nate, there is no jump but connected at 0° and 360° or 2π in *∆*, and the figure reveals that the

We have carried out real-time *in-situ* measurements at various growth temperatures between 893°C and 1147°C. The oxide thicknesses are plotted as a function of oxidation time in Figure 16. Compared with the previously reported results obtained from *ex situ* measurements [15,18], it is found from the figure that the data during the initial oxidation stage were obtained with

For Si thermal oxidation, Deal and Grove [1] have considered two rate-determining processes, i.e., the reaction process at the interface and the process of oxygen diffusion through the oxide

where, *X*, *t* and *τ* are the oxide thickness, oxidation time, and initial oxidation time, respec‐ tively. *B/A* and *B* are denoted as the linear and parabolic rate constants of oxidation, respec‐ tively. Many researchers have applied D-G model to explain SiC oxidation [15, 18]. We also applied the D-G model to the results obtained from in situ ellipsometric measurements. The fitted curves derived using Eq. (3) are shown by the broken lines in Figure 16, which reveals that the fits are good at all the oxidation temperatures in our experiments. However, there is a discrepancy between the values of *B/A* and *B* obtained in this study and those reported by, for example, Song et al. [18], who modified D-G model for Si oxidation to that for SiC by taking into account the presence of carbon, i.e., adding the out diffusion process of CO from the interface to the surface. One of the reasons of this discrepancy is considered to be the difference of measurement method, i.e., the *ex-situ* measurements performed after the oxidation have been used in the previously reported studies, while we used *in-situ* real-time measurements and thus, the relations between oxide thickness and oxidation time can be precisely obtained. The reasons of these discrepancies in the values of rate constants appeared in D-G model between ours and those by Song et al. have been discussed in details by Goto et al. [49] with the relation of the oxide growth rate enhancement in thin thickness regime for SiC oxidation.

In the previous section, we mentioned that real-time observation of SiC thermal oxidation using an *in-situ* ellipsometer has been performed for the first time and shown that the results are well explained by the D-G model. However, it has been reported that the oxidation behavior of Si in thin oxide thickness range cannot be explained using the D-G model, where the oxide growth rate enhancement has been found. Therefore, we have studied the initial oxidation stage of SiC in more details to make clear such an oxide growth rate enhancement

t

(3)

( ) <sup>2</sup> *X AX B* +=+1

precision of *∆* depends on the absolute values of *Ψ*.

118 Advanced Silicon Carbide Devices and Processing

much improved detail and much smaller spread.

layer, and proposed, so-called, D-G-model, given as,

**4.2. Oxide growth rate enhancement of SiC in thin oxide regime**

occurs also for SiC or not.

**Figure 16.** Oxide thickness as a function of oxidation time at various oxidation temperatures. The broken lines show the fitting curves by use of D-G model [29].

In the study mentioned in Section 4.1, the real-time measurements of (*Ψ, ∆*) were performed at the single wavelength *λ* = 400 nm. In order to observe the oxidation in initial oxidation stage, i.e., to elucidate the oxidation process and interface layer formation in more detail, we have undertaken the spectroscopic observation of SiC oxidation by using a CCD detector. We have performed the measurements of oxidation rate in thin-thickness regime both for C- and Sifaces of 4H-SiC by in situ real-time observation using a spectroscopic ellipsometer with CCD detector [30,31,50].

Ellipsometric measurements were carried out at wavelengths between 310 and 410 nm, where we can perform the ellipsometric measurements without the disturbance by the strong light emission from the heated sample. We have derived the thickness of oxide layers as a function of oxidation time by using the same analytical method mentioned in the previous sections.

Firstly, we have applied the D-G model to the results obtained at various oxidation tempera‐ tures. Though the fits are seen in general well over the wide thickness range in the thickness range of thinner than around 20 nm, it was found there exists a tendency for the observed values to be slightly larger than the calculated ones by using the D-G model. To see these discrepancies in more detail, we have derived the oxidation rates d*X/*d*t* from the observed curves of oxide thickness *X*(t).

Figure 17 shows the oxide thickness dependences of oxidation rate for C-face and Si-face. The figures reveal that the values of the oxidation rate including the thin thickness range of less than 10 nm can be obtained by real-time in situ spectroscopic observation. However, the figures also suggest that the oxidation rates calculated using the D-G model cannot be fitted to the observed ones over the entire oxide thickness range at all the oxidation temperatures meas‐ ured, though the fitting is well in the range thicker than around 20 nm for C-face and several nm for Si-face, as shown by the solid lines in Figure 17(a). While, in the thin thickness region, the oxidation rates are larger than the values calculated by use of the D-G model regardless of oxidation temperature. These results reveal that the oxidation having a larger growth rate than that predicted by the D-G model occurs in thin-thickness range, though the critical thickness is different between C-face and Si-face.

By the D-G model, the relation between the growth rate d*X/*d*t* and the oxide thickness *X* is given [1] as,

$$\frac{dX}{dt} = \frac{B}{A + 2X}.\tag{4}$$

In small thickness range, i.e., *X*<<*A*, the oxidation is limited by the reaction rate at the inter‐ face, and the growth rates are constant, equal to *B/A* from Eq.(4). However, the experimental results shown in Figure 17(b) reveal that, the growth rates are not constant but increase with decreasing oxide thickness in small thickness range. These experimental results for C- and Siface suggest that the oxidation enhancement occurs regardless of surface polarity.

**Figure 17.** Oxide thickness dependences of oxide growth rates at various oxidation temperatures for (a) C-face, and (b) Si face [30,31].

#### **4.3. Application of Massoud's empirical equation to SiC oxidation**

Many researchers have tried to explain the oxide growth rate enhancement in thin-thickness regime for Si oxidation [4,51-54]. Massoud et al. [4] have proposed an empirical equation giving the oxidation rate as a function of oxidation thickness by adding an exponential term to the D-G equation, as,

$$\frac{dX}{dt} = \frac{B}{A + 2X} + \text{Cexp}\left(-\frac{X}{L}\right) \tag{5}$$

where *C* and *L* are the pre-exponential constant and the characteristic length, respectively.

We have tried to fit the calculated values to the observed ones by use of Eq. (5) for both Si- and C-faces. In all the oxidation temperatures, much better fittings than those using Eq. (4) were obtained, as shown by the broken and solid lines, respectively, in Figures 18 (a) and (b). From the curve fitting, the values of *L* as well as *C*, *B/A* and *B* were derived. Both for Si- and C-faces, the values of *L* scarcely depend on the oxidation temperature, around 7 nm, the behavior of which is almost the same as that for the oxidation of Si [4]. These results suggest that oxidation enhancement is predominant when oxide thickness is smaller than around 7 nm for both faces of SiC and Si oxidations.

#### **i. Temperature dependences of oxidation rates**

observed ones over the entire oxide thickness range at all the oxidation temperatures meas‐ ured, though the fitting is well in the range thicker than around 20 nm for C-face and several nm for Si-face, as shown by the solid lines in Figure 17(a). While, in the thin thickness region, the oxidation rates are larger than the values calculated by use of the D-G model regardless of oxidation temperature. These results reveal that the oxidation having a larger growth rate than that predicted by the D-G model occurs in thin-thickness range, though the critical thickness

By the D-G model, the relation between the growth rate d*X/*d*t* and the oxide thickness *X* is

. <sup>2</sup> <sup>=</sup> <sup>+</sup> *dX B*

face suggest that the oxidation enhancement occurs regardless of surface polarity.

In small thickness range, i.e., *X*<<*A*, the oxidation is limited by the reaction rate at the inter‐ face, and the growth rates are constant, equal to *B/A* from Eq.(4). However, the experimental results shown in Figure 17(b) reveal that, the growth rates are not constant but increase with decreasing oxide thickness in small thickness range. These experimental results for C- and Si-

**Figure 17.** Oxide thickness dependences of oxide growth rates at various oxidation temperatures for (a) C-face, and (b)

Many researchers have tried to explain the oxide growth rate enhancement in thin-thickness regime for Si oxidation [4,51-54]. Massoud et al. [4] have proposed an empirical equation giving

**4.3. Application of Massoud's empirical equation to SiC oxidation**

*dt A X* (4)

is different between C-face and Si-face.

120 Advanced Silicon Carbide Devices and Processing

given [1] as,

Si face [30,31].

We discuss the temperature dependences of the four parameters *B/A, B, C*, and *L* below. Figure 18(a) shows the Arrhenius plots of the linear rate constant *B/A* for C-face and Si-face. The *B/A* values for C-face are one order of magnitude larger than those for Si-face at all the temperatures measured, which corresponds well to the experimental results that the growth rate of C-face is about 10 times larger than that of Si-face. The figure suggests that the values of *B/A* for Siface lie on a single straight line having the activation energy of 1.31 eV, while for C-face the values lie on two straight lines the breaking point of which is around 1000°C. The activation energies for the higher and the lower temperature ranges are 0.75 and 1.76 eV, respectively. In this experiment, the growth rates of SiC for oxide thickness smaller than around 100 nm were measured. Therefore, we do not discuss the temperature dependences of the values of *B* here because of insufficient precision in determining the parabolic rate constant *B* without data for more thick oxide.

The values of *C*/(*B/A*) are around 2-6 for Si-face, but for C-face smaller than 1. As the values of *C/(A/B)* give the magnitude of oxide growth enhancement, the growth rate enhancement phenomenon is suggested to be more marked for Si-face than for C-face. The Arrhenius plots of the parameters *C* and *L* are shown in Figure 18(b). The figure reveals that the values of *C* for Si-face are almost independent of temperature, but those for C-face increase with the increase of temperature. While for the values of *L*, that for C face reveals little dependence on temperature, but that for Si-face steeply increase with temperature. The absolute values of *L* for Si face and C-face are around 3 and 6 nm, respectively, at 1100°C. It is found from the figure that the temperature dependences of *C* and *L* are different between Si-face and C-face of SiC. For Si oxidation, in comparison, it has been reported that *L* are around 7 nm and almost independent of temperature, and the values of *C* increase with temperature [4], which are the same for SiC C-face, but different for SiC Si-face. From these results, it can be said that the oxidation mechanism of SiC C-face is similar to that of Si in some sense, while that of SiC Siface is quite different from that of Si.

**Figure 18.** Arrhenius plots of the linear rate constant *B/A* (a), and *C* and *L* (b)*,* for C- and Si-faces [31].

#### **ii. Oxygen-partial-pressure dependence of oxidation rates**

In the previous section, we have studied the temperature dependences of oxidation rate. Another parameter to control the oxidation rates is the quantity of oxygen supplied to the interface. Therefore, we have studied the pressure dependence of oxidation rate. Especially at reduced pressure, the oxidation rates become small, which is good to observe the initial oxidation stage in details.

Figures 19(a) and (b) show the oxide thickness dependence of oxide growth rate at various oxygen partial pressures for C- and Si-face, respectively. These figures reveal that the oxide growth rate enhancement occurs at any partial pressure, as in the cases at 1 atm. Figures 20(a) and (b) show the oxygen-partial-pressure, *p*, dependence of the values of the linear rate constant *B/A* and the enhancement parameters *C* and *L* for C-face and Si-face. It is found from Figure 20(a) that the values of *B/A* behave similar pressure dependences for both surface polarities, as ~ *p*0.6. The D-G model [1] leads the results that *B/A* and *B* are proportional to *p,* which contradicts to our results, as well as for Si oxidation, i.e., ~ p0.7-0.8 [4]. We have already reported that the value of *B* for both Si- and C-faces is proportional to *p* [50], which also contradicts to the prediction from D-G model. Figure 20(b) shows the variations of the values of *C* and *L* with oxygen pressure for Si- and C-faces. It is found from the figure that those values for both surface polarities are almost constant with respect to pressure, which is different from the pressure dependence of the values of *B/A* and B. The fact that the enhancement parameters *C* and *L* are independent of pressure, which is quite different from those for *B/A* and *B* values, suggests the existence of an additional oxidation-rate-limiting mechanism, which is inde‐ pendent of the quantity of oxygen supplied, other than the interface reaction of oxygen with SiC (*A/B*) and the diffusion of oxygen and CO through SiO2 layers (*B*).

Investigation of SiC/Oxide Interface Structures by Spectroscopic Ellipsometry http://dx.doi.org/10.5772/61082 123

oxidation mechanism of SiC C-face is similar to that of Si in some sense, while that of SiC Si-

**Figure 18.** Arrhenius plots of the linear rate constant *B/A* (a), and *C* and *L* (b)*,* for C- and Si-faces [31].

In the previous section, we have studied the temperature dependences of oxidation rate. Another parameter to control the oxidation rates is the quantity of oxygen supplied to the interface. Therefore, we have studied the pressure dependence of oxidation rate. Especially at reduced pressure, the oxidation rates become small, which is good to observe the initial

Figures 19(a) and (b) show the oxide thickness dependence of oxide growth rate at various oxygen partial pressures for C- and Si-face, respectively. These figures reveal that the oxide growth rate enhancement occurs at any partial pressure, as in the cases at 1 atm. Figures 20(a) and (b) show the oxygen-partial-pressure, *p*, dependence of the values of the linear rate constant *B/A* and the enhancement parameters *C* and *L* for C-face and Si-face. It is found from Figure 20(a) that the values of *B/A* behave similar pressure dependences for both surface polarities, as ~ *p*0.6. The D-G model [1] leads the results that *B/A* and *B* are proportional to *p,* which contradicts to our results, as well as for Si oxidation, i.e., ~ p0.7-0.8 [4]. We have already reported that the value of *B* for both Si- and C-faces is proportional to *p* [50], which also contradicts to the prediction from D-G model. Figure 20(b) shows the variations of the values of *C* and *L* with oxygen pressure for Si- and C-faces. It is found from the figure that those values for both surface polarities are almost constant with respect to pressure, which is different from the pressure dependence of the values of *B/A* and B. The fact that the enhancement parameters *C* and *L* are independent of pressure, which is quite different from those for *B/A* and *B* values, suggests the existence of an additional oxidation-rate-limiting mechanism, which is inde‐ pendent of the quantity of oxygen supplied, other than the interface reaction of oxygen with

**ii. Oxygen-partial-pressure dependence of oxidation rates**

SiC (*A/B*) and the diffusion of oxygen and CO through SiO2 layers (*B*).

face is quite different from that of Si.

122 Advanced Silicon Carbide Devices and Processing

oxidation stage in details.

**Figure 19.** Oxide thickness dependences of oxide growth rates at various oxygen pressures for (a) C-face, and (b) Siface [31,50].

**Figure 20.** Oxygen pressure dependences of the values of the parameters, *B/A, C*, and *L* for C- and Si-faces [31].

#### **5. Studies on the SiC oxidation process and interface formation based on SiC oxidation mechanisms**

In the previous sections, we have studied SiC oxidation process by use of in situ real-time observation using automatic spectroscopic ellipsometry and found the oxidation rate en‐ hancement in very thin-thickness regime, for the first time, which cannot be explained by using the D-G model. Then, we have applied Massord's equation proposed for the growth rate enhancement for Si, and discussed the oxidation temperature and oxygen partial pressure dependences of the parameters appeared in the equation. However, the Massord's equation was derived without considering any physical and/or chemical mechanisms of Si oxidation, i.e., the equation was derived for fitting to the experimental results on the oxide thickness dependence of growth rate. Therefore, the Massourd's equation (Eq.(5)) is one of the empirical equations, and thus, it may not be appropriate to discuss the physical or/and chemical meaning from the results of the nature of parameters in the equation.

Growth rate enhancement has been observed also for Si oxidation in thin-thickness regime. Kageshima et al. [52] and Uematsu et al. [55] have proposed the model for Si oxidation, called "interfacial Si emission model", where Si atoms are emitted into the oxide layers as well as into Si substrate, owing to the strain that arises from the expansion of Si lattices to form SiO2 lattice. By the interfacial Si emission model, the oxidation rate at the interface is primarily large and becomes suppressed by the accumulation of emitted Si atoms near the interface with the progress of oxidation. This means that the oxidation rate never enhances in small thickness range but rapidly decreases with the increase of oxide thickness.

The interfacial Si emission model suggests that the stress near/at the oxide-Si interface originated from the formation of SiO2 lattice brings about the growth enhancement in the initial oxidation stage. The density of Si atoms in SiC (4.80 × 1022 cm-3) [56] is almost equal to that in Si (5 × 1022 cm-3)[57], which may bring about almost identical situation for SiC oxidation as in the case of Si oxidation. Therefore, it can be considered that the interfacial emission of atoms caused by the interfacial stress also brings about the growth enhancement in SiC oxidation. Based on these considerations, we have proposed the model, called "interfacial Si-C emission model", taking into account the presence of carbon in SiC to explain the experimental results for SiC oxidation reported [33],

As the formation of interface structures is considered to be closely related with the initial oxidation process, we have studied initial oxidation of SiC in more detail at reduced oxygen partial pressers, and discussed on the formation process of the interface layers in terms of SiC oxidation mechanism in ultra-thin-thickness regime. Though the oxide growth rate of SiC is much smaller than that of Si, it is still too fast to observe the initial growth process in detail. Therefore, a reduction in the growth rate, for examples, by lowering oxidation temperature, and/or lowering the oxygen partial pressure, is believed to be useful for observation of the initial oxide growth process of SiC more minutely. To make clear the oxygen partial pressure dependence of the SiC oxidation process, ex situ measurements have been carried out at the pressures from 10-3 to 4 atm [16,19]. However, the initial oxidation process has not been examined in detail, partly due to the limit of the precision of the data obtained by ex situ measurements in small thickness regime.

#### **5.1. Observation of SiC oxidation in ultra-thin oxide regime at low temperatures**

We have studied SiC oxidation at low temperatures or under reduced oxygen pressure in detail by performing in situ and real-time spectroscopic ellipsometry in ultra-thin oxide thickness regime [58]. Figures 21(a) and (b) show the oxidation time dependences of the thicknesses of SiO2 and interface layer for the oxidation at 850° and 700°C, respectively, in the oxygen pressure of 1 atm. At 850°C, both the interface layer and the SiO2 layer thicknesses increase with time, but the thickness of interface layer is saturated at about 1 nm by the oxidation time more than 2 h though the continuous increase in SiO2 layer thickness is seen even after 2 h. While the oxidation at 700°C brings about the rapid increase of SiO2 thickness up to around 1 nm and then the very small oxidation rate, resulting in the 1.2 nm in thickness even after 8 h oxidation. The figure also shows that the thicknesses of the interface layer are almost zero up to 8 h, indicating that no interface layer is formed between SiO2 and SiC at 700°C. These results suggest that an interfacial layer is not formed by low temperature oxidation, but is formed at 850°C. From the experimental results mentioned above, it is also possible to derive the conclusion that the interface layer is not formed or is extremely thin when the SiO2 layer is thinner than around 1nm but is formed when SiO2 thickness is over 1-2 nm. That is to say, there are two possibilities in the condition of realizing oxide layers on SiC with no interface layer, i.e., low oxidation temperatures or/and oxide layers thinner than around 2 nm. However, it is hard to study interface structure in this oxide thickness range at 850°C, because the oxide layer, around 1 nm in thickness, is formed in too short time to measure in details even at 850°C.

Growth rate enhancement has been observed also for Si oxidation in thin-thickness regime. Kageshima et al. [52] and Uematsu et al. [55] have proposed the model for Si oxidation, called "interfacial Si emission model", where Si atoms are emitted into the oxide layers as well as into Si substrate, owing to the strain that arises from the expansion of Si lattices to form SiO2 lattice. By the interfacial Si emission model, the oxidation rate at the interface is primarily large and becomes suppressed by the accumulation of emitted Si atoms near the interface with the progress of oxidation. This means that the oxidation rate never enhances in small thickness

The interfacial Si emission model suggests that the stress near/at the oxide-Si interface originated from the formation of SiO2 lattice brings about the growth enhancement in the initial oxidation stage. The density of Si atoms in SiC (4.80 × 1022 cm-3) [56] is almost equal to that in Si (5 × 1022 cm-3)[57], which may bring about almost identical situation for SiC oxidation as in the case of Si oxidation. Therefore, it can be considered that the interfacial emission of atoms caused by the interfacial stress also brings about the growth enhancement in SiC oxidation. Based on these considerations, we have proposed the model, called "interfacial Si-C emission model", taking into account the presence of carbon in SiC to explain the experimental results

As the formation of interface structures is considered to be closely related with the initial oxidation process, we have studied initial oxidation of SiC in more detail at reduced oxygen partial pressers, and discussed on the formation process of the interface layers in terms of SiC oxidation mechanism in ultra-thin-thickness regime. Though the oxide growth rate of SiC is much smaller than that of Si, it is still too fast to observe the initial growth process in detail. Therefore, a reduction in the growth rate, for examples, by lowering oxidation temperature, and/or lowering the oxygen partial pressure, is believed to be useful for observation of the initial oxide growth process of SiC more minutely. To make clear the oxygen partial pressure dependence of the SiC oxidation process, ex situ measurements have been carried out at the pressures from 10-3 to 4 atm [16,19]. However, the initial oxidation process has not been examined in detail, partly due to the limit of the precision of the data obtained by ex situ

**5.1. Observation of SiC oxidation in ultra-thin oxide regime at low temperatures**

We have studied SiC oxidation at low temperatures or under reduced oxygen pressure in detail by performing in situ and real-time spectroscopic ellipsometry in ultra-thin oxide thickness regime [58]. Figures 21(a) and (b) show the oxidation time dependences of the thicknesses of SiO2 and interface layer for the oxidation at 850° and 700°C, respectively, in the oxygen pressure of 1 atm. At 850°C, both the interface layer and the SiO2 layer thicknesses increase with time, but the thickness of interface layer is saturated at about 1 nm by the oxidation time more than 2 h though the continuous increase in SiO2 layer thickness is seen even after 2 h. While the oxidation at 700°C brings about the rapid increase of SiO2 thickness up to around 1 nm and then the very small oxidation rate, resulting in the 1.2 nm in thickness even after 8 h oxidation. The figure also shows that the thicknesses of the interface layer are almost zero up to 8 h, indicating that no interface layer is formed between SiO2 and SiC at 700°C. These results

range but rapidly decreases with the increase of oxide thickness.

for SiC oxidation reported [33],

124 Advanced Silicon Carbide Devices and Processing

measurements in small thickness regime.

**Figure 21.** Oxidation time dependences of thicknesses of the SiO2 layer and the interface layer for the oxidation at (a) 850°C and (b) 700°C [58].

figure\_21. By way of reducing the partial pressure during the oxidation, we have examined the oxidation at 850°C more precisely in order to clarify the formation process of interface layers. The reduction of oxygen pressure down to 0.01 atm brings about the oxidation rate almost the same as that of 700°C, 1 atm. At the reduced oxide growth rates, we can obtain the information about the interface layer in the thin oxide thickness range less than 1 nm even for the oxidation at 850°C. The results reveal that the interface layer thickness is extremely thin, when the SiO2 layer thickness is smaller than ~1 nm. Therefore, the formation of an interface layer is consid‐ ered to be independent of oxidation temperature but depends on the SiO2 layer thickness. These results, as well as those in the study mentioned in Section 3.1, suggest that the interface layers are never transition layers between SiC and SiO2, like as SiO*x*, and/or SiO*x*C*y*, but the layers modified a little from SiC.

According to the interfacial Si-C emission model [33], Si atoms are considered to be emitted not only to oxide layer side but also to SiC substrate side. The Si atoms emitted into SiC may form SiC layers including Si interstitials near the SiC/oxide interface. The SiC layers with Si interstitial may have large refractive indices than SiC due to the large atomic density, but may have similar band structures due to, not the displacement of lattice sites, but the occupation of interstitial sites. Together with the experimental results that the interface layers have large refractive indices but have extinction coefficient just like SiC, the interface layers formed by SiC oxidation are supposed to SiC layers with interstitial Si atoms emitted from the interface accompanied by the oxidation of SiC. For Si oxidation, Nguyen et al. have found the existence of strained Si layers just near the Si/oxide interface and have attributed to the strain due to the expansion of Si lattices by oxidation [5]. As the red shift of th*e E*0 gap energy is arose by the tensile stress in Si, the layers having different optical constants from Si are formed near the interfaces. Similarly, for SiC, the stress due to the oxidation is considered to generate the layers having different optical constants from that of SiC near the interface. The stress is reported to cause the polytype conversion from 4H-SiC to 3C-type, which is also possible to change the properties of SiC near the interface. Based on the interfacial Si-C emission model, the fact that the interface layer is not formed or the thickness of the interface layer is very small for thin oxide layers can be understood as follows. As a strain at the interface is considered to increase with the increase of oxide layer thickness, the strain in thin oxide layers is very small, and thus a little amount of Si atoms are emitted, which results in no or very thin interface layer formed. The critical thickness of the oxides at which an interface layer forms, or the noticeable changes of optical constants occur in the SiC layer near the interface, may be around 1nm.

#### **5.2. Observation of SiC oxidation in thin oxide regime and the discussion on SiC oxidation and interface formation mechanisms**

In the previous section, we have studied the initial oxidation stage, up to several nm in oxide thickness, by use of oxidation at low temperatures or under reduced oxygen pressure up to several nm in thickness of oxide, and discussed the structure and formation mechanisms of interface layer. However, it is feared that the oxidation mechanism changes with oxidation temperatures, like lower than 1000°C. Therefore, we have studied the initial oxidation stage, up to several 10 nm in thickness, at reduced oxygen pressure down to 0.02 atm at 1100°C to discuss on the formation process of the interface layers in the frame of SiC oxidation mecha‐ nism, i.e., the interfacial Si-C emission model [33], in thin-thickness regime.

Epitaxial wafers of 4H -SiC with a 0.5° off-oriented (000-1) C-face and a 8° off-oriented (0001) Si-face, both are n-types, having a net donor concentration *N*d - *N*a = 3 × 1015 cm-3 and 1 × 1016cm-3, respectively, were used in this study. All the oxidations were conducted at the oxidation temperature of 1100°C under various oxygen partial pressures between 0.02 and 1 atm. The obtained (*Ψ, ∆*) spectra were analyzed using a two-layers structure model and optical constants of the interface layers were assumed to follow the modified Sellmeier's dispersion relation taking a weak optical absorption into account, Eq. (2).

Figures 22(a) and (b) show the oxide thickness dependence of the interface layer thickness and those of *n*inf of the interface layers on the SiC (000-1) C-face and (0001) Si-face, respectively. The values of *n*inf for 4H-SiC and SiO2 are also shown by the broken lines in the figures. As seen in Figure 22, the interface layer thickness increases with increasing oxide thickness and saturates around 1.5 nm at the oxide thickness of around 7 nm, and this saturation thickness depends slightly on the partial pressure. The figures also show that the values of *n*inf are also saturated around 7 nm in oxide thickness and the saturated values depend slightly on the partial pressure.

The oxide thickness dependence of the oxide growth rates on the 4H-SiC C-face and Si-face are shown in Figures 23 (a) and (b), respectively. The figures indicate, for both Si- and C-faces, basically similar oxide thickness dependences of the growth rate are seen at the partial pressures lower than 0.1 atm to those at above 0.1 atm shown in Section 4, even at the partial pressures lowered to 0.02 atm. Namely, just after the oxidation starts, the oxide growth rates

Investigation of SiC/Oxide Interface Structures by Spectroscopic Ellipsometry http://dx.doi.org/10.5772/61082 127

tensile stress in Si, the layers having different optical constants from Si are formed near the interfaces. Similarly, for SiC, the stress due to the oxidation is considered to generate the layers having different optical constants from that of SiC near the interface. The stress is reported to cause the polytype conversion from 4H-SiC to 3C-type, which is also possible to change the properties of SiC near the interface. Based on the interfacial Si-C emission model, the fact that the interface layer is not formed or the thickness of the interface layer is very small for thin oxide layers can be understood as follows. As a strain at the interface is considered to increase with the increase of oxide layer thickness, the strain in thin oxide layers is very small, and thus a little amount of Si atoms are emitted, which results in no or very thin interface layer formed. The critical thickness of the oxides at which an interface layer forms, or the noticeable changes

of optical constants occur in the SiC layer near the interface, may be around 1nm.

nism, i.e., the interfacial Si-C emission model [33], in thin-thickness regime.

relation taking a weak optical absorption into account, Eq. (2).

**and interface formation mechanisms**

126 Advanced Silicon Carbide Devices and Processing

pressure.

**5.2. Observation of SiC oxidation in thin oxide regime and the discussion on SiC oxidation**

In the previous section, we have studied the initial oxidation stage, up to several nm in oxide thickness, by use of oxidation at low temperatures or under reduced oxygen pressure up to several nm in thickness of oxide, and discussed the structure and formation mechanisms of interface layer. However, it is feared that the oxidation mechanism changes with oxidation temperatures, like lower than 1000°C. Therefore, we have studied the initial oxidation stage, up to several 10 nm in thickness, at reduced oxygen pressure down to 0.02 atm at 1100°C to discuss on the formation process of the interface layers in the frame of SiC oxidation mecha‐

Epitaxial wafers of 4H -SiC with a 0.5° off-oriented (000-1) C-face and a 8° off-oriented (0001) Si-face, both are n-types, having a net donor concentration *N*d - *N*a = 3 × 1015 cm-3 and 1 × 1016cm-3, respectively, were used in this study. All the oxidations were conducted at the oxidation temperature of 1100°C under various oxygen partial pressures between 0.02 and 1 atm. The obtained (*Ψ, ∆*) spectra were analyzed using a two-layers structure model and optical constants of the interface layers were assumed to follow the modified Sellmeier's dispersion

Figures 22(a) and (b) show the oxide thickness dependence of the interface layer thickness and those of *n*inf of the interface layers on the SiC (000-1) C-face and (0001) Si-face, respectively. The values of *n*inf for 4H-SiC and SiO2 are also shown by the broken lines in the figures. As seen in Figure 22, the interface layer thickness increases with increasing oxide thickness and saturates around 1.5 nm at the oxide thickness of around 7 nm, and this saturation thickness depends slightly on the partial pressure. The figures also show that the values of *n*inf are also saturated around 7 nm in oxide thickness and the saturated values depend slightly on the partial

The oxide thickness dependence of the oxide growth rates on the 4H-SiC C-face and Si-face are shown in Figures 23 (a) and (b), respectively. The figures indicate, for both Si- and C-faces, basically similar oxide thickness dependences of the growth rate are seen at the partial pressures lower than 0.1 atm to those at above 0.1 atm shown in Section 4, even at the partial pressures lowered to 0.02 atm. Namely, just after the oxidation starts, the oxide growth rates

figure\_22. **Figure 22.** Oxide thickness dependence of interface layer thickness and *n*inf. at various oxygen partial pressures on (a) the (000-1) C-face and (b) the (0001) Si-face [32].

rapidly decrease and the deceleration rate changes to a gentle one at around 7 nm in oxide thickness (hereafter the two oxidation stages are denoted as the rapid and gentle deceleration stage, respectively).

**Figure 23.** Oxide growth rates as a function of oxide thickness at various oxygen partial pressures on (a) the (000-1) Cface and (b) the (0001) Si-face. Broken lines are fitted to the experimental data using exponential functions [32].

figure\_23.

We fitted the experimental data at each partial pressure with two straight lines, as shown by the dotted lines in Figures 23 (a) and (b), and derived the initial growth rate of the two deceleration stages, *R*0 and *R*1, by extrapolating the straight line to oxide thickness *X* = 0 in the rapid and gentle deceleration stages, respectively. The figures show that the thickness at which the deceleration rate changes from a rapid to a gentle one (termed "deceleration-rate-change thickness *X*c "), i.e., the cross point of the two decay lines, is almost constant around 7 nm regardless of the oxygen partial pressure or surface polarity.

Figure 24 shows the oxygen partial pressure dependence of *R*0 and *R*<sup>1</sup> on the C- and Si-faces. Since oxide growth in the thin region was too fast to follow spectroscopic ellipsometry measurements in the case of 1 atm pressure on the C-face, it was hard to estimate the oxide growth rates in the rapid deceleration stage accurately. Thus, the value of *R*0 for the C-face at 1 atm is not shown in this figure. The dashed line in Figure 24 shows the data proportional to the oxygen partial pressure and fitted to the *R*1 data for the C-face. For both polar faces, the data points of *R*1 are almost on the line, suggesting that *R*1 is proportional to the partial pressure, though, for the Si-face, *R*1 becomes slightly smaller as seen from the linear relation approaching 1 atm. It should be noted that the rates are almost equal for the C- and Si-faces at low pressures, which is different from the fact that the oxide growth rates for the C-face are about 10 times larger than those for the Si-face in the several 10 nm thickness region at atmospheric oxygen pressure [15,18,19,31].

**Figure 24.** Oxygen partial pressure dependence of the initial growth rate, *R*<sup>0</sup> (unfilled symbols), and the gentle deceler‐ ation growth rate, *R*1 (filled symbols), on the C-face (circles) and Si-face (triangles) [32].

figure\_24. We will discuss these results based on the oxidation mechanisms, especially, by use of interfacial Si-C atoms emission model, as follows. Here, we briefly state the essence of the Si and C emission model that we proposed for a description of the SiC oxidation process [33]. During oxidation, Si and C interstitials are emitted from the SiC/oxide interface, and a decrease in the interfacial reaction rate, *k*, as expressed by the following function, occurs as the inter‐ stitials accumulate inside the oxide near the interface accompanying progress in oxidation,

$$k = k\_0 \left( 1 - \frac{\mathbb{C}\_{Si}^{int}}{\mathbb{C}\_{Si}^{lim}} \right) \left( 1 - \frac{\mathbb{C}\_{\mathbb{C}}^{int}}{\mathbb{C}\_{\mathbb{C}}^{lim}} \right) \tag{6}$$

where *C*int and *C*lim are the concentrations at the interface and the solubility limit in the oxide, respectively, of the corresponding interstitial atoms, i.e., Si and C, and *k*0 is the initial interfacial oxidation rate. If the oxide grows only at the interface, the oxide growth rate d*X/*d*t* is repre‐ sented by the equation,

$$k\mathcal{N}\_0 \frac{d\mathbf{X}}{dt} = k\mathcal{C}\_0^{\mathrm{int}} \tag{7}$$

where *N*0 is the molecular density of SiO2, and *C*intO is the concentration of oxygen at the interface. As seen from this equation, a decrease in *k* corresponds to a decrease in d*X/*d*t*. It should be noted that the D-G model corresponds to the case that *k* is constant regardless of the oxide thickness in this oxidation model.

#### **i. Formation and structures of the interface layers**

We fitted the experimental data at each partial pressure with two straight lines, as shown by the dotted lines in Figures 23 (a) and (b), and derived the initial growth rate of the two deceleration stages, *R*0 and *R*1, by extrapolating the straight line to oxide thickness *X* = 0 in the rapid and gentle deceleration stages, respectively. The figures show that the thickness at which the deceleration rate changes from a rapid to a gentle one (termed "deceleration-rate-change thickness *X*c "), i.e., the cross point of the two decay lines, is almost constant around 7 nm

Figure 24 shows the oxygen partial pressure dependence of *R*0 and *R*<sup>1</sup> on the C- and Si-faces. Since oxide growth in the thin region was too fast to follow spectroscopic ellipsometry measurements in the case of 1 atm pressure on the C-face, it was hard to estimate the oxide growth rates in the rapid deceleration stage accurately. Thus, the value of *R*0 for the C-face at 1 atm is not shown in this figure. The dashed line in Figure 24 shows the data proportional to the oxygen partial pressure and fitted to the *R*1 data for the C-face. For both polar faces, the data points of *R*1 are almost on the line, suggesting that *R*1 is proportional to the partial pressure, though, for the Si-face, *R*1 becomes slightly smaller as seen from the linear relation approaching 1 atm. It should be noted that the rates are almost equal for the C- and Si-faces at low pressures, which is different from the fact that the oxide growth rates for the C-face are about 10 times larger than those for the Si-face in the several 10 nm thickness region at atmospheric oxygen

regardless of the oxygen partial pressure or surface polarity.

1

4 6 8 0.01

ation growth rate, *R*1 (filled symbols), on the C-face (circles) and Si-face (triangles) [32].

2 4 6 8

**Figure 24.** Oxygen partial pressure dependence of the initial growth rate, *R*<sup>0</sup> (unfilled symbols), and the gentle deceler‐

We will discuss these results based on the oxidation mechanisms, especially, by use of interfacial Si-C atoms emission model, as follows. Here, we briefly state the essence of the Si

0.1

R0

Partial pressure [atm]

2 4 6 8

R<sup>1</sup> <sup>~</sup><sup>p</sup>

1

 C-face Si-face

2

figure\_24.

10

Growth rate [nm/h]

100

pressure [15,18,19,31].

128 Advanced Silicon Carbide Devices and Processing

We have reported [27,28] that the photon energy dependence of the optical constants *nit* and *kit* derived from the complex dielectric constants between 2 and 6 eV, covering the direct interband transition energy *E*<sup>0</sup> of 4H -SiC of 5.65 eV, is similar to that of bulk 4H -SiC, though the absolute values of *n*it are about 1 larger than those of SiC, which were again confirmed in this study. The similarity in the energy dispersion of the optical constants of the interface layers suggests that the interface layer is not a transition layer between SiC and SiO2. Rather, it is a layer having a modified structure and/or composition compared to SiC, such as a stressed or interstitials-incorporated SiC layer, locating not on the SiO2 side but on the SiC side of the SiC/ oxide interface.

The experimental results also indicated that the thickness at which the interface layer thickness and the value of *n*inf becomes constant (i.e., 7 nm) is determined not from the surface polarity or oxygen partial pressure but from the oxide thickness. The Si-C emission model describes this behavior by considering that Si and C atoms are emitted into both directions of the SiC/ oxide interface accompanying oxidation at the interface, i.e., into not only the oxide layer but also the SiC layer, and accumulation of interstitial Si and/or C atoms emitted into the SiC substrate may form a layer having similar optical properties as SiC but larger refractive indices compared to SiC. Since accumulation of interstitials is linked to the growth of the oxide, it is considered that growth of the interface layer is saturated at some intrinsic oxide thickness even if the oxygen pressure is changed. We will discuss the behavior of the interface layer as well as that of *X*c, later.

#### **ii. Oxide thickness dependence of oxide growth rate**

As mentioned above, there are two oxidation stages in the oxide growth rate curves, i.e., first rapid deceleration and second gentle deceleration. Since the growth rates at each deceleration stage are seen as a straight line in a semi-logarithm plot (shown by broken lines in Figures 23 (a) and (b)) in the respective stage, the oxide thickness dependence of the oxide growth rate can be approximated by the sum of two exponential functions [59] as

$$\frac{dX}{dt} = R\_0 \exp\left(-\frac{X}{L\_1}\right) - R\_1 \exp\left(-\frac{X}{L\_2}\right) \tag{8}$$

where *R*0 and *R*<sup>1</sup> (*R*0>>*R*1) have the same meaning as in Figure 23, i.e., pre-exponential constants, and *L*0 and *L*1 (*L*0<*L*1) are the characteristic lengths for the deceleration of oxide growth rate in each oxidation stage, respectively. Equation (8) means that in the thin oxide regime, oxide growth occurs by two ways and they proceed not in series but in parallel because the growth rate is given by the sum of two terms and is chiefly determined by the faster one in each stage. Obviously, the *L*0 and *L*<sup>1</sup> values correspond to the gradients of the fitted line in the rapid and gentle deceleration stage, respectively. As shown in Figure 23, the *L*0 value decreases with decreasing partial pressure, which corresponds to the more remarkable rapid deceleration. In contrast, the *L*<sup>1</sup> value is almost constant regardless of the partial pressure. This suggests that the oxidation process is different between the rapid and gentle deceleration stages. We will discuss these two deceleration stages relevant to the oxide growth mechanism.

#### **iii. Discussion of the two decelerating stages in terms of SiC and Si oxidation mech‐ anisms**

The existence of a rapid deceleration stage in the oxide growth rate just after oxidation starts (*X* < 10 nm) has also been observed for Si oxidation [4,60]. However, in investigations on Si oxidation mechanisms, the cause of the rapid deceleration has not yet been clarified. That is, the Deal-Grove model cannot fully account for the initial rapid deceleration [1]. An empirical equation, i.e., the D-G term plus an exponential term, proposed by Massoud et al.[4], can only reproduce the observed growth rates numerically, but does not provide a physical meaning. The interfacial Si emission model [52] is now believed to be the model that can reproduce the observed oxide growth rate quantitatively very well for Si oxidation. However, the model also cannot reproduce the remarkable rapid deceleration at subatmospheric oxygen pressures, as pointed out by Farjas and Roura [60]. For SiC oxidation, we have tried to reproduce the observed data using Massoud's empirical equation [30,31,50]. Here, we discuss the reasons why two deceleration stages exist in the thickness dependence of oxide growth rate, based on the interfacial Si-C emission model.

The interfacial reaction rate (*k* in Eq. (6)) is unlikely to depend on the oxygen partial pressure, *p*, because it corresponds to the rate at which one SiC molecule is changed to one SiO2 molecule, which should not depend on *p*. In the thin oxide regime discussed here, the interface oxygen concentration *C*intO can be expressed as *C*intO ~ *pC*limo by Henry's law, where *C*limO is the solubility limit of oxygen in SiO2. Therefore, the growth rate in the thin oxide regime, *R*, should be proportional to *p*, which is in good agreement with the experimental results in the gentle deceleration stage, i.e., *R*1.

if the oxygen pressure is changed. We will discuss the behavior of the interface layer as well

As mentioned above, there are two oxidation stages in the oxide growth rate curves, i.e., first rapid deceleration and second gentle deceleration. Since the growth rates at each deceleration stage are seen as a straight line in a semi-logarithm plot (shown by broken lines in Figures 23 (a) and (b)) in the respective stage, the oxide thickness dependence of the oxide growth rate

1 2

*dt <sup>L</sup> <sup>L</sup>* (8)

èø èø

where *R*0 and *R*<sup>1</sup> (*R*0>>*R*1) have the same meaning as in Figure 23, i.e., pre-exponential constants, and *L*0 and *L*1 (*L*0<*L*1) are the characteristic lengths for the deceleration of oxide growth rate in each oxidation stage, respectively. Equation (8) means that in the thin oxide regime, oxide growth occurs by two ways and they proceed not in series but in parallel because the growth rate is given by the sum of two terms and is chiefly determined by the faster one in each stage. Obviously, the *L*0 and *L*<sup>1</sup> values correspond to the gradients of the fitted line in the rapid and gentle deceleration stage, respectively. As shown in Figure 23, the *L*0 value decreases with decreasing partial pressure, which corresponds to the more remarkable rapid deceleration. In contrast, the *L*<sup>1</sup> value is almost constant regardless of the partial pressure. This suggests that the oxidation process is different between the rapid and gentle deceleration stages. We will

**iii. Discussion of the two decelerating stages in terms of SiC and Si oxidation mech‐**

The existence of a rapid deceleration stage in the oxide growth rate just after oxidation starts (*X* < 10 nm) has also been observed for Si oxidation [4,60]. However, in investigations on Si oxidation mechanisms, the cause of the rapid deceleration has not yet been clarified. That is, the Deal-Grove model cannot fully account for the initial rapid deceleration [1]. An empirical equation, i.e., the D-G term plus an exponential term, proposed by Massoud et al.[4], can only reproduce the observed growth rates numerically, but does not provide a physical meaning. The interfacial Si emission model [52] is now believed to be the model that can reproduce the observed oxide growth rate quantitatively very well for Si oxidation. However, the model also cannot reproduce the remarkable rapid deceleration at subatmospheric oxygen pressures, as pointed out by Farjas and Roura [60]. For SiC oxidation, we have tried to reproduce the observed data using Massoud's empirical equation [30,31,50]. Here, we discuss the reasons why two deceleration stages exist in the thickness dependence of oxide growth rate, based on

The interfacial reaction rate (*k* in Eq. (6)) is unlikely to depend on the oxygen partial pressure, *p*, because it corresponds to the rate at which one SiC molecule is changed to one SiO2 molecule, which should not depend on *p*. In the thin oxide regime discussed here, the interface oxygen

**ii. Oxide thickness dependence of oxide growth rate**

can be approximated by the sum of two exponential functions [59] as

0 1

discuss these two deceleration stages relevant to the oxide growth mechanism.

*dX <sup>X</sup> <sup>X</sup> R R*

exp exp æö æö = -- - ç÷ ç÷

as that of *X*c, later.

130 Advanced Silicon Carbide Devices and Processing

**anisms**

the interfacial Si-C emission model.

According to the Si-C emission model [33], as the number of accumulated atoms increases with oxidation, and is thus proportional to the quantity of oxidized molecules, i.e., the thickness of the oxide *X*, the variation in *k* may be approximately given as an exponential function of *X* in the form of *C*exp(-*X/L*), where *C* and *L* are the pre-exponential term and characteristic length, respectively, related to the accumulation of Si and C interstitials at the interface. From these considerations, as well as the fact that *R*1 is proportional to *p*, the gentle deceleration of the oxide growth rate can be attributed to the accumulation of Si and C interstitials near the interface, and given approximately as d*X/*d*t* ~ *R*1exp(-*X/L*1), which is coincident with the second term in Eq. (8).

If the initial growth rate *R*<sup>0</sup> in the rapid deceleration stage is also followed by Eq. (7), it can be expressed as *R*0 ~ *k*0*C*intO/*N*0, where *k*<sup>0</sup> is the interfacial reaction rate when the oxidation starts. As the value of *k*0 is also unlikely to depend on the oxygen partial pressure, *R*0 should be proportional to the oxygen pressure. As seen in Figure 24, while *R*0 is not proportional to *p*, it decreases with decreasing *p* in the low *p* region. This suggests that *R*0, i.e., the rapid decelera‐ tion, is not related to the interfacial oxide growth. In the case of Si oxidation, the experimental data show almost no dependence of *R*0 with respect to *p* [4].

We next consider the reason why *R*<sup>0</sup> is not proportional to but rather is almost independent of the oxygen partial pressure, both for Si and SiC oxidations. It has been considered that oxide growth occurs only or mainly at the Si/oxide (SiC/oxide) interface. However, according to the Si emission model [52] for Si oxidation and the Si and C emission model [33] for SiC oxidation, Si atoms (Si and C atoms) are emitted into the oxide layer, some of which encounter the oxidant inside the oxide to form SiO2. If the oxide is so thin that, some of the Si atoms emitted can go through the oxide layer and reach the oxide surface, those Si atoms are instantly oxidized to form a SiO2 layer at the surface. This indicates there exist another oxide growth process other than the oxide formation at the SiC/oxide interface and that due to the oxidation of Si inter‐ stitials inside the oxide layers, i.e., the oxide formation by way of the oxidation of Si interstitials at the oxide surface. It is noted that this oxide formation process on the surface has not been considered in the Si emission model for Si oxidation [52]. The oxide growth rate of SiC is, therefore, totally given by the sum of these three oxide formation processes. In the case of oxidation inside the oxide, the probability of the emitted Si interstitials meeting the oxidant inside the oxide should be proportional to the oxygen concentration in the oxide. Therefore, this oxidation process should be proportional to *p* like *R*1, and thus can be excluded as a candidate of the origin of *R*0.

In contrast, in the case of oxidation on the oxide surface, the amount of oxygen is thought to be sufficient to oxidize all the Si atoms emitted and appearing on the surface, because the number of oxygen molecules impinging onto the surface from the gaseous atmosphere is several orders larger than the number of emitted Si atoms transmitted through the oxide even if the oxygen pressure is as low as 0.02 atm. Therefore, the oxide growth rate for oxidation on the oxide surface should be independent of the oxygen partial pressure, which is in good agreement with the behavior of *R*0. Besides, the possibility that Si interstitials go through the oxide and reach the oxide surface is considered to decrease rapidly with increasing oxide thickness, and can be given the form exp(-*X/L*0), where *L*0 (<*L*1) is the escape depth of Si atoms from the oxide layer. From these considerations, the rapid deceleration stage of oxide growth rate observed just after oxidation starts is thought to be due to oxidation of Si interstitials on the oxide surface. Therefore, the value of *X*c obtained from the experiments of 7 nm indicates that the escape depth of Si atoms from the oxide is estimated to be several nanometers at 1100°C. Since the behavior of Si interstitials other than at the interface should be the same for the C- and Si-faces, it is reasonable that the value of *X*<sup>c</sup> does not depend on the polarity of the SiC faces. Moreover, the fact that the growth rates in the thin regime at low pressures are not very different for the C- and Si-faces can be explained by considering that surface oxide growth is dominant over oxide growth in this stage and oxidation on the oxide surface may proceed independent of the surface polarity.

Theoretical calculations of the growth rates reported so far have not taken into account the surface oxide growth for both Si and SiC oxidations. However, in the extremely thin oxide thickness range and especially at low oxygen partial pressures, the contribution from surface oxide growth as well as those from the interface and internal oxide growth should be taken into account. However, to confirm the argument derived from the experimental results in this study, it is necessary to perform numerical calculations of the oxide growth rates within the framework of the Si-C emission model, taking into account the contribution from oxidation on the surface. In the case of Si oxidation, the interfacial Si emission model [52] cannot reproduce the growth rate in the thin oxide region at sub-atmospheric pressures, as pointed out by Farjas and Roura [60], where the introduction of the contribution from the surface oxide growth may dissolve the disagreement between the calculated and the observed oxide growth rates.

As mentioned above, the *X*c value is almost constant around 7 nm regardless of the oxygen partial pressure, though the rapid deceleration stage can be observed more remarkably at lower partial pressures. In the case of Si oxidation, a rapid deceleration stage has also been observed just after oxidation starts, and the thickness corresponding to *X*c is also almost independent of the oxygen partial pressure, though the growth rates at *X*<sup>c</sup> depend on the oxygen partial pressure [4,60]. Therefore, it can be stated that *X*c is determined only by the thickness of the oxide layer for both the Si and the SiC oxidation cases. It is to be noted that the value of *X*<sup>c</sup> is very close to the thickness at which the interface structures become constant as revealed above. In addition, the pressure dependence of the oxide thickness when the interface layer becomes unchanged also exhibits the same behavior, i.e., they are almost independent of pressure. These results suggest that an interface layer gradually grows during the surface oxide growth and, after transforming to the interfacial and internal oxide growth, the interface layer stops growing. It is considered that the interface layer located on the SiC side of the interface may be oxidized to form SiO2 and a new interface layer may form on the SiC side, which results in movement of the position of the interface layer in the direction of the SiC substrate with progress in oxidation. Therefore, the brake for the interface layer growth is considered to be responsible for the abrupt change in growth rate at *X*c. Otherwise, during the surface oxide growth, fewer interstitials emit into the SiC-side because the concentration of interstitials in the oxide is quite low; in turn, the emission into the SiC-side increases with accumulation of interstitials in the oxide and then the accumulation of interstitials is saturated when it balances with the progress in oxidation front.

#### **6. Summary**

the oxide surface should be independent of the oxygen partial pressure, which is in good agreement with the behavior of *R*0. Besides, the possibility that Si interstitials go through the oxide and reach the oxide surface is considered to decrease rapidly with increasing oxide thickness, and can be given the form exp(-*X/L*0), where *L*0 (<*L*1) is the escape depth of Si atoms from the oxide layer. From these considerations, the rapid deceleration stage of oxide growth rate observed just after oxidation starts is thought to be due to oxidation of Si interstitials on the oxide surface. Therefore, the value of *X*c obtained from the experiments of 7 nm indicates that the escape depth of Si atoms from the oxide is estimated to be several nanometers at 1100°C. Since the behavior of Si interstitials other than at the interface should be the same for the C- and Si-faces, it is reasonable that the value of *X*<sup>c</sup> does not depend on the polarity of the SiC faces. Moreover, the fact that the growth rates in the thin regime at low pressures are not very different for the C- and Si-faces can be explained by considering that surface oxide growth is dominant over oxide growth in this stage and oxidation on the oxide surface may proceed

Theoretical calculations of the growth rates reported so far have not taken into account the surface oxide growth for both Si and SiC oxidations. However, in the extremely thin oxide thickness range and especially at low oxygen partial pressures, the contribution from surface oxide growth as well as those from the interface and internal oxide growth should be taken into account. However, to confirm the argument derived from the experimental results in this study, it is necessary to perform numerical calculations of the oxide growth rates within the framework of the Si-C emission model, taking into account the contribution from oxidation on the surface. In the case of Si oxidation, the interfacial Si emission model [52] cannot reproduce the growth rate in the thin oxide region at sub-atmospheric pressures, as pointed out by Farjas and Roura [60], where the introduction of the contribution from the surface oxide growth may dissolve the disagreement between the calculated and the observed oxide growth

As mentioned above, the *X*c value is almost constant around 7 nm regardless of the oxygen partial pressure, though the rapid deceleration stage can be observed more remarkably at lower partial pressures. In the case of Si oxidation, a rapid deceleration stage has also been observed just after oxidation starts, and the thickness corresponding to *X*c is also almost independent of the oxygen partial pressure, though the growth rates at *X*<sup>c</sup> depend on the oxygen partial pressure [4,60]. Therefore, it can be stated that *X*c is determined only by the thickness of the oxide layer for both the Si and the SiC oxidation cases. It is to be noted that the value of *X*<sup>c</sup> is very close to the thickness at which the interface structures become constant as revealed above. In addition, the pressure dependence of the oxide thickness when the interface layer becomes unchanged also exhibits the same behavior, i.e., they are almost independent of pressure. These results suggest that an interface layer gradually grows during the surface oxide growth and, after transforming to the interfacial and internal oxide growth, the interface layer stops growing. It is considered that the interface layer located on the SiC side of the interface may be oxidized to form SiO2 and a new interface layer may form on the SiC side, which results in movement of the position of the interface layer in the direction of the SiC substrate with progress in oxidation. Therefore, the brake for the interface layer growth

independent of the surface polarity.

132 Advanced Silicon Carbide Devices and Processing

rates.

We have employed spectroscopic ellipsometry, one of the methods of observing buried interfaces keeping intact for observing SiC/oxide interfaces to investigate their structures. We have developed the characterization method of the oxide layers and SiC/oxide interfaces, i.e., by using sloped oxide layers, and made clear the depth profile of the refractive indices and interface structures, i.e., there exist interface layers, having high refractive indices compared with those of SiC and SiO2, the values of which depend on the oxide layer formation method, around 1 nm in thickness, at oxide/SiC interface and only the thickness of the SiO2 layers changes with oxidation time or oxide thickness. It can be said that the optical properties estimated from the analysis using the single layer model, i.e., the oxide films are assumed to be optically uniform single layer on SiC, are "apparent" features, and it is not true that the optical constants of the oxide layers change with oxidation time or oxide thickness. The results that the refractive indices of the interface are larger than those of both SiC and SiO2 reveal that the interfaces are neither the transition layers having the composition between SiO2 and SiC nor those due to interface roughness.

Optical and electrical evaluations of SiC/oxide interface based on the spectroscopic ellipsom‐ etry in the visible to deep UV region and the *C-V* measurements by using the same samples for both measurements have been carried out for the samples with both surface polarities, and formed by various oxidation methods and temperatures, including the samples after various POA. Quite good correlations between the changes in refractive indices of the interface layers *n*it by the oxidation condition and those in interface state density *D*it are found for all the cases of oxidation conditions. These correlations suggest that the formation of the interface layers with large refractive indices is related to the generation of interface states. It is also found that the wavelength dependences of extinction coefficient of the interface layers *k*it are quite similar to those of SiC in the entire wavelength range measured, suggesting the presence of layers with a little different band structures from that of bulk SiC, e.g., strained SiC layers. By using the method of inducing interface state density by γ-ray irradiation, we have confirmed that the values of refractive indices of interfaces obtained from spectroscopic ellipsometery are well correlated with the electrical properties of interface, like interface state density, which strongly supports that the values of refractive indices of interface layers are reflected from the electrical properties of interfaces.

We have also developed the observation system in order to perform real-time *in-situ* obser‐ vation of SiC oxidation for the first time. By using this system, we have observed the occurrence of the oxide growth rate enhancement in the thin oxide regime for the oxidation of SiC both for Si- and C-faces. We have also observed that the growth rate of SiC for both polar faces can be well represented by the Massoud's empirical equation using the four adjusting parameters. From the differences in temperature and oxygen partial pressure dependences of these parameters, we have discussed on the difference of the oxidation mechanisms between Si-face and C-face of SiC.

Finally, we have studied the oxygen partial pressure dependence of the SiC oxidation process in the initial oxidation stage in details at oxygen partial pressures ranging from 0.02 to 1.0 atm. It was found that regardless of the surface polarity as well as the oxygen partial pressure, an interface layer having modified SiC structures is formed accompanied by oxidation just below the SiC/oxide interface in the same manner, i.e., the thickness and refractive indices of the interface layer increase with an increase in the oxide thickness, the interface layer thickness reaches about 1.5 nm at an oxide thickness of around 7 nm, and then the thickness and structure of the interface layer do not change anymore with further increase in oxide thickness. The oxide thickness dependence of the growth rate at sub-atmospheric oxygen partial pressures down to 0.02 atm is similar to those at 1 atm. Namely, just after the oxidation starts, the oxide growth rate rapidly decreases and the deceleration-rate changes to a gentle mode at around 7 nm in oxide thickness, which is almost the same thickness at which the thickness and the structure of the interface layers become constant. We have shown that the interfacial Si-C emission model can explain the cause for the change in deceleration rate of the oxide growth rate from the oxygen partial pressure dependence and found that the oxide growth due to oxidation of Si interstitials on the oxide surface plays a dominant role in the extremely thin thickness region, less than several nanometers.

Through the studies on SiC/oxide interfaces based on the spectroscopic ellipsometry meas‐ urements, we have found the existence of strong correlation between the optical properties of interface, like *n*it, and the electrical properties, like *D*it. However, in general, the mechanisms of the relation between the MOS characteristics of SiC, i.e., low carrier mobility and threshold voltage instability, and the interface structures have not been made clear. It is eager to understand the mechanisms of SiC-MOS characteristics in relation to the interface structures. The results obtained suggest the interface structures, i.e., the formation of interface layers with high refractive indices depend on oxide thickness as well as the oxidation conditions. There‐ fore, it can be said that the process of forming no interface layers or the interface layers with very thin or having lower refractive indices is desirable, by the methods of, for example, using very thin oxide layers. The formation of insulated layers for MOS structures not by oxidation of SiC, but by the deposition of insulator materials, for examples, Si oxide and Al oxide, may be other candidates, though caution should be taken to avoid the proceed of oxidation during the device process performed after the formation of MOS interface. Anyway, the important point is to develop the process based on the information of "true" interface structures obtained by use of non-distractive measurement methods, like ellipsometry, with selecting an appro‐ priate model for the analyses of measured data.

#### **Author details**

for Si- and C-faces. We have also observed that the growth rate of SiC for both polar faces can be well represented by the Massoud's empirical equation using the four adjusting parameters. From the differences in temperature and oxygen partial pressure dependences of these parameters, we have discussed on the difference of the oxidation mechanisms between Si-face

Finally, we have studied the oxygen partial pressure dependence of the SiC oxidation process in the initial oxidation stage in details at oxygen partial pressures ranging from 0.02 to 1.0 atm. It was found that regardless of the surface polarity as well as the oxygen partial pressure, an interface layer having modified SiC structures is formed accompanied by oxidation just below the SiC/oxide interface in the same manner, i.e., the thickness and refractive indices of the interface layer increase with an increase in the oxide thickness, the interface layer thickness reaches about 1.5 nm at an oxide thickness of around 7 nm, and then the thickness and structure of the interface layer do not change anymore with further increase in oxide thickness. The oxide thickness dependence of the growth rate at sub-atmospheric oxygen partial pressures down to 0.02 atm is similar to those at 1 atm. Namely, just after the oxidation starts, the oxide growth rate rapidly decreases and the deceleration-rate changes to a gentle mode at around 7 nm in oxide thickness, which is almost the same thickness at which the thickness and the structure of the interface layers become constant. We have shown that the interfacial Si-C emission model can explain the cause for the change in deceleration rate of the oxide growth rate from the oxygen partial pressure dependence and found that the oxide growth due to oxidation of Si interstitials on the oxide surface plays a dominant role in the extremely thin

Through the studies on SiC/oxide interfaces based on the spectroscopic ellipsometry meas‐ urements, we have found the existence of strong correlation between the optical properties of interface, like *n*it, and the electrical properties, like *D*it. However, in general, the mechanisms of the relation between the MOS characteristics of SiC, i.e., low carrier mobility and threshold voltage instability, and the interface structures have not been made clear. It is eager to understand the mechanisms of SiC-MOS characteristics in relation to the interface structures. The results obtained suggest the interface structures, i.e., the formation of interface layers with high refractive indices depend on oxide thickness as well as the oxidation conditions. There‐ fore, it can be said that the process of forming no interface layers or the interface layers with very thin or having lower refractive indices is desirable, by the methods of, for example, using very thin oxide layers. The formation of insulated layers for MOS structures not by oxidation of SiC, but by the deposition of insulator materials, for examples, Si oxide and Al oxide, may be other candidates, though caution should be taken to avoid the proceed of oxidation during the device process performed after the formation of MOS interface. Anyway, the important point is to develop the process based on the information of "true" interface structures obtained by use of non-distractive measurement methods, like ellipsometry, with selecting an appro‐

and C-face of SiC.

134 Advanced Silicon Carbide Devices and Processing

thickness region, less than several nanometers.

priate model for the analyses of measured data.

Sadafumi Yoshida1\*, Yasuto Hijikata2 and Hiroyuki Yaguchi2

\*Address all correspondence to: s.yoshida@aist.go.jp

1 Advanced Power Electronics Research Center, National Institute of Advanced Industrial Science and Technology (AIST), Tsukuba, Japan

2 Graduate School of Science and Engineering, Saitama University, Saitama, Japan

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## **Comparative Study of Optimally Designed DC-DC Converters with SiC and Si Power Devices**

O. Deblecker, Z. De Grève and C. Versèle

Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/61018

#### **Abstract**

In this chapter, power losses and mass of optimally designed Si- vs. SiC-based isolated DC-DC converters are compared in quantitative terms. To that end, an adapted version of a computer-aided design tool, previously published by the authors, is used. The database of the existing tool was completed with new wide band gap semicon‐ ductor devices currently available from manufacturers. The results are presented for two switch-mode power supplies, each constituted of an isolated DC-DC converter, operating at very different power levels: a 100 kW auxiliary railway power supply and a multiple output 33.5 W power supply intended for a space application. The gains in terms of power losses and mass from one technology to the other can advantageously be evaluated thanks to the developed tool.

**Keywords:** Multiobjective optimization, genetic algorithms, DC-DC converters, SiC devices

#### **1. Introduction**

The electric energy is one of the most flexible forms of energy available today, which is mainly due to the development of power electronics over the past decades. Nevertheless, a correct design of power electronic converters is not a trivial task: it usually involves the minimization of multiple conflicting objectives such as, *e.g.* (but not restricted to), the power losses and mass, while ensuring the satisfaction of several technological and thermal constraints. In this context, the authors proposed in a previous work [1,2] a computer-aided design (CAD) tool dedicated

© 2015 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

to isolated DC-DC converters, based on multiobjective (MO) optimization using genetic algorithms (GAs). A key advantage of that predesign tool is that it does not restrict to one solution. Instead, it proposes to the designer a set of optimal solutions so that he can choose *a posteriori* which solution best fits the application under consideration or which objective function to favor.

Modern DC-DC power converters often belong to the category of switched mode power supplies (SMPS), for their high-energy efficiency (more than 90%) and their ability to ensure galvanic isolation [3]. Moreover, SMPS are employed in a lot of applications, covering a wide power range (from several tens of watts to hundreds of kilowatts) and fed by different voltage levels. For instance, they are more and more used in vehicular applications (traction and auxiliary converters in trains and electric automobile vehicles) as well as in aeronautics and space.

In addition to passive components, such as filter capacitors/inductors and transformers for providing the electrical isolation, SMPS include power transistors continually switching between low dissipative full-on and full-off states. The switching frequency of those semicon‐ ductor devices strongly impacts the design of the magnetic components. Indeed, it is well known that a high-switching frequency yields small values of the core cross section and hence smaller inductors or transformers. Knowing that magnetic components can account for more than 50% of the volume and mass of a power converter, one then understands how crucial it is to use semiconductor devices with fast switching speeds. Yet it should be kept in mind that increasing the switching frequency also increases the switching losses, which can lead to abnormally high-junction temperatures and/or heat sink module dimensions [3]. Currently, the power switches (IGBTs and MOSFETs) as well as diodes are based on silicon (Si) technol‐ ogy, and hence, the continuously increasing demand for lightweight power converters forces the engineers to operate the components at switching frequencies close to their intrinsic limits. This maximum value is however seldom reached, as a trade-off between the switching losses and the speed is needed.

It is now well established in the power electronics community that silicon-carbide (SiC) and gallium-nitride (GaN) semiconductor materials show superior properties, enabling potential power device operation at higher voltages, temperatures, and switching speeds than conven‐ tional Si technology (see Figure 1). As a result, this gives rise to new perspectives for the design of power converters with enhanced performances [4–7]. Until now, GaN-based power transistors are still restricted to low voltage applications, whereas SiC components are available with higher voltage ratings and therefore higher power capability. Some manufac‐ turing limitations of GaN devices can be found in [8,9]. Note that, recently, the experimental prototype of a hard switched 20 W/50 V RF GaN-based DC-DC converter intended for use in an envelope-tracking power amplification system has been presented, achieving an efficiency up to 91.6% at 50 MHz [10]. Regarding the performances, power devices based on diamond would be, of course, the most interesting, but this option is not economically acceptable today.

Within this framework, the present contribution aims at comparing in quantitative terms power losses and mass of optimally designed Si- *vs*. SiC-based isolated DC-DC power converters [11]. To that end, an adapted version of the previously mentioned MO optimization

Comparative Study of Optimally Designed DC-DC Converters with SiC and Si Power Devices http://dx.doi.org/10.5772/61018 145

**Figure 1.** Summary of Si, SiC, and GaN relevant material properties.

to isolated DC-DC converters, based on multiobjective (MO) optimization using genetic algorithms (GAs). A key advantage of that predesign tool is that it does not restrict to one solution. Instead, it proposes to the designer a set of optimal solutions so that he can choose *a posteriori* which solution best fits the application under consideration or which objective

Modern DC-DC power converters often belong to the category of switched mode power supplies (SMPS), for their high-energy efficiency (more than 90%) and their ability to ensure galvanic isolation [3]. Moreover, SMPS are employed in a lot of applications, covering a wide power range (from several tens of watts to hundreds of kilowatts) and fed by different voltage levels. For instance, they are more and more used in vehicular applications (traction and auxiliary converters in trains and electric automobile vehicles) as well as in aeronautics and

In addition to passive components, such as filter capacitors/inductors and transformers for providing the electrical isolation, SMPS include power transistors continually switching between low dissipative full-on and full-off states. The switching frequency of those semicon‐ ductor devices strongly impacts the design of the magnetic components. Indeed, it is well known that a high-switching frequency yields small values of the core cross section and hence smaller inductors or transformers. Knowing that magnetic components can account for more than 50% of the volume and mass of a power converter, one then understands how crucial it is to use semiconductor devices with fast switching speeds. Yet it should be kept in mind that increasing the switching frequency also increases the switching losses, which can lead to abnormally high-junction temperatures and/or heat sink module dimensions [3]. Currently, the power switches (IGBTs and MOSFETs) as well as diodes are based on silicon (Si) technol‐ ogy, and hence, the continuously increasing demand for lightweight power converters forces the engineers to operate the components at switching frequencies close to their intrinsic limits. This maximum value is however seldom reached, as a trade-off between the switching losses

It is now well established in the power electronics community that silicon-carbide (SiC) and gallium-nitride (GaN) semiconductor materials show superior properties, enabling potential power device operation at higher voltages, temperatures, and switching speeds than conven‐ tional Si technology (see Figure 1). As a result, this gives rise to new perspectives for the design of power converters with enhanced performances [4–7]. Until now, GaN-based power transistors are still restricted to low voltage applications, whereas SiC components are available with higher voltage ratings and therefore higher power capability. Some manufac‐ turing limitations of GaN devices can be found in [8,9]. Note that, recently, the experimental prototype of a hard switched 20 W/50 V RF GaN-based DC-DC converter intended for use in an envelope-tracking power amplification system has been presented, achieving an efficiency up to 91.6% at 50 MHz [10]. Regarding the performances, power devices based on diamond would be, of course, the most interesting, but this option is not economically acceptable today. Within this framework, the present contribution aims at comparing in quantitative terms power losses and mass of optimally designed Si- *vs*. SiC-based isolated DC-DC power converters [11]. To that end, an adapted version of the previously mentioned MO optimization

function to favor.

144 Advanced Silicon Carbide Devices and Processing

and the speed is needed.

space.

CAD tool, completed with a new database of wide band gap semiconductor devices, will be used. Two power supplies operating at very different power levels will be selected as appli‐ cation examples: a high-power (100 kW) auxiliary railway SMPS and a low-power (33.5 W) SMPS intended for a space application.

The remainder of this chapter is organized as follows. In Section 2, a comparison between Si and wide band gap (WBG) materials is first presented. Then the WBG devices (mainly SiC) that will be taken into account in this work are listed in the same section. In Section 3, basic information about the models employed to represent the power converters are given. The existing CAD tool, based on GA, is briefly reviewed in the fourth section. The MO optimal design of the two above-mentioned power supplies, each constituted of an isolated DC-DC converter, is conducted in Sections 5 and 6, with and without including SiC devices in the optimization procedure in order to evaluate the gains in terms of power losses and mass. Finally, conclusions and perspectives are exposed in Section 7.

#### **2. Wide band gap materials and power electronic devices**

Since the 1950s, WBG materials are expected to replace silicon in semiconductor power devices when it reaches its limits [12]. However, their use in power electronics has been widely considered only recently due to their advantages over Si power devices regarding temperature and power operation [4]. The purpose of this section is to briefly review the intrinsic properties and figures of merit of the principal WBG materials, in comparison with classical Si material. Then the WBG semiconductor devices (mainly SiC) that will be considered in this chapter are listed.

#### **2.1. Properties of wide band gap semiconductors**

Several interesting properties of Si and WBG semiconductor materials are reported in Table 1, at a temperature of 300 K [5,13,14]. Note that different polytypes of SiC material exist, each one being characterized by its own crystal lattice structure. They differ in their electronic properties but feature similar mechanical and thermal behavior, which is due to the particular nature of the Si-C chemical link. Among those, the most commonly used is the polytype 4H-SiC.


**Table 1.** Comparison between intrinsic properties of Si and WBG semiconductor materials.

The band gap width *E*g refers to the energy needed for one electron to jump from the valence to the conduction band. A material with a high *E*<sup>g</sup> implies that the probability for an electron to cross the band gap under thermal excitation is low, thus allowing high working temperature operation. Note that the term "wide band" usually refers to values of *E*<sup>g</sup> greater than 2 eV [6]. Materials with a high band gap are also less subject to electron jumps caused by radiations, which is an asset in the case of space or nuclear applications.

The maximum working temperature *T*max is defined as the temperature for which the number of intrinsic carriers becomes greater than doping. In that case, the material loses its semicon‐ ducting properties. For instance, in Table 1, it can be noticed that WBG materials have higher *T*max than Si. Diamond and SiC are also better heat conductors than Si, according to the values of their thermal conductivity *λ*.

Then the WBG semiconductor devices (mainly SiC) that will be considered in this chapter are

Several interesting properties of Si and WBG semiconductor materials are reported in Table 1, at a temperature of 300 K [5,13,14]. Note that different polytypes of SiC material exist, each one being characterized by its own crystal lattice structure. They differ in their electronic properties but feature similar mechanical and thermal behavior, which is due to the particular nature of the Si-C chemical link. Among those, the most commonly used is the polytype 4H-

**Properties (at 300 K) Si 4H-SiC 6H-SiC 3C-SiC GaN Diamond**

Relative permittivity *ε* <sup>r</sup> 11.8 10 9.7 9.7 9 5.5

The band gap width *E*g refers to the energy needed for one electron to jump from the valence to the conduction band. A material with a high *E*<sup>g</sup> implies that the probability for an electron to cross the band gap under thermal excitation is low, thus allowing high working temperature operation. Note that the term "wide band" usually refers to values of *E*<sup>g</sup> greater than 2 eV [6]. Materials with a high band gap are also less subject to electron jumps caused by radiations,

**Table 1.** Comparison between intrinsic properties of Si and WBG semiconductor materials.

which is an asset in the case of space or nuclear applications.

1.12 3.26 3.03 2.3 3.45 5.45

0.3 2.2 2.5 2 2 10

9.6 × 109 5 × 10-9 1.6 × 10-6 1.5 × 10-1 1.9 × 10-10 1.6 × 10-27

1500 1000 500 800 1250 2200

600 115 101 40 850 850

1.5 4.9 4.9 3.2 1.3 22

1 2 2 2.5 2.2 2.7

150 760 760 500 800 1100

listed.

SiC.

Band gap width *E* <sup>g</sup> [eV]

Breakdown electric field *E* <sup>c</sup> [MV·cm-1]

Intrinsic carrier concentration *ni* [cm-3]

> Electrons mobility *μ* <sup>N</sup> [cm2 ·V-1·s-1]

Holes mobility *μ* <sup>P</sup> [cm2 ·V-1·s-1]

Thermal conductivity *λ* [W·K cm-1]

Saturation velocity *v* sat [×107 cm·s-1]

Maximum working temperature *T* max [°C]

**2.1. Properties of wide band gap semiconductors**

146 Advanced Silicon Carbide Devices and Processing

A WBG also corresponds to a high breakdown electric field *E*c, which permits to build components with high voltage capabilities (currently up to 20 kV for SiC power devices). Indeed, the breakdown electric field for WBG materials is more or less one order of magnitude higher than for Si, according to the value reported in Table 1. Thus, WBG components might be, for example, interesting candidates for use in power supplies of space traveling wave tubes, which have to produce voltages up to several kilovolts [15].

As explained in [6,14], the reverse leakage current of bipolar junctions is proportional to *ni* or *ni* 2 , with *ni* the intrinsic carriers concentration. Thus, considering the values of *ni* in Table 1, the reverse leakage current is several order of magnitudes smaller with WBG components compared to Si.

Generally, high values for the charge carrier mobilities *μ*N (electrons) and *μ*P (holes), and for the saturation velocity *v*sat (which is the maximum velocity the charge carriers can reach under the application of an electric field), are needed. In that way, it is possible to operate at higher current densities and switching frequencies [16]. It can be seen in Table 1 that SiC and GaN materials have slightly smaller mobilities than Si. Yet that drawback is balanced by a higher saturation velocity. Moreover, a large value of *v*sat, combined with small values of the electrical permittivity *ε*r, is important for high-frequency applications [14].

The conduction losses essentially depend on *ε*r and the breakdown electrical field *E*c. Indeed, the on-state resistance *r*on of a unipolar component, as, e.g., a metal oxide semiconductor field effect transistor (MOSFET), is inversely proportional to these two variables [14]:

$$r\_{on} \propto \frac{1}{\sigma\_r E\_c} \tag{1}$$

This permits to highlight another advantage of WBG components over classical Si ones. Indeed, Figure 2 represents the on-state resistance *r*on as a function of the maximum supported voltage for Si and WBG unipolar components, once again at 300 K. Commonly, a value of a few hundreds of mΩ cm2 yields reasonable conduction losses. In that case, Figure 2 shows that the maximum supported voltage for Si components is approximately limited to 1 kV, whereas WBG components can support a few tens of kilovolts.

For a comparison of the possible power electronics performances of these materials, some commonly known figures of merit, i.e., special quality criteria, are listed in Table 2 [17,18]. The values reported in this table have been calculated from the data given in Table 1 and normal‐ ized with respect to Si. A larger value represents a better material performance in the corre‐ sponding category.

300 K.

components can support a few tens of kilovolts.

This permits to highlight another advantage of WBG components over classical Si ones. Indeed, Figure 2 represents the on-state resistance ron as a function of the maximum supported voltage for Si and WBG unipolar components, once again at 300 K. Commonly, a value of a few hundreds of m�·cm<sup>2</sup> yields reasonable conduction losses. In that case, Figure 2

From Table 2, it can be noticed that the figures of merit for diamond are at least 40–50 times more than those of any other semiconductor material (except for Keyes' criterion). On the other hand, SiC polytypes and GaN have more or less

> JFM 1 215.1 277.8 277.8 215.5 81000 KFM 1 5 5.1 3.7 1.5 35.3 BFM 1 222.8 158.6 129.9 188.3 25319 BHFM 1 35.9 23.1 23.7 37 1629.6 SFM 1 64.4 39.5 19 30.8 5207.1

Si SiC (4H) SiC (6H) SiC (3C) GaN Diamond

<sup>3</sup> (with µ the mobility of current carriers).

Figure 2. Theoretical limits of Si and WBG unipolar components on-state resistance as a function of the maximum supported voltage, at **Figure 2.** Theoretical limits of Si and WBG unipolar components on-state resistance as a function of the maximum sup‐ ported voltage, at 300 K.

Johnson has proposed to use the product of the breakdown electric field and the saturation velocity as a figure of merit (JFM), which determines the ultimate power-frequency capability of the material: JFM = (*E*<sup>c</sup> *v*sat /π*)* 2 *.* Later, the following criterion was defined by Keyes: KFM = *λ* (*v*sat /*ε*r) 1/2, which provides a thermal limitation to the switching behavior of transistors. Baliga has proposed yet another figure of merit (BFM) for evaluating a semiconductor material. It is related to the operating losses of a high-power field-effect transistor: BFM = *ε*<sup>r</sup> *μ E*<sup>c</sup> 3 (with *μ* the mobility of current carriers). However, this criterion was associated primarily with ohmic losses due to the specific on-resistance of the drift region and was used to assess the capabilities of a semiconductor from the standpoint of low-frequency devices. For the assessment of highfrequency devices, the losses associated with the commutations must also be considered. The criterion BHFM = *μ E*<sup>c</sup> 2 , based on the assumption that switching losses are caused by the recharging input capacitance of a device, was proposed in [18]. Finally, Schneider proposed a figure of merit to assess the performances of high-voltage bipolar components, taking into account the thermal dissipation and maximum operating temperature of the semiconductor material [19]: SFM = *E*c (*μ*N*+μ*P) *λT*max. For a comparison of the possible power electronics performances of these materials, some commonly known figures of merit, i.e., special quality criteria, are listed in Table 2 [17,18]. The values reported in this table have been calculated from the data given in Table 1 and normalized with respect to Si. A larger value represents a better material performance in the corresponding category. Johnson has proposed to use the product of the breakdown electric field and the saturation velocity as a figure of merit (JFM), which determines the ultimate power-frequency capability of the material: JFM = (E<sup>c</sup> vsat /π)<sup>2</sup>. Later, the following criterion was defined by Keyes: KFM = λ (vsat /εr)1/2, which provides a thermal limitation to the switching behavior of transistors. Baliga has proposed yet another figure of merit (BFM) for evaluating a semiconductor material. It is related to the operating losses of a high-power field-effect transistor: BFM = ε<sup>r</sup> µ E<sup>c</sup> However, this criterion was associated primarily with ohmic losses due to the specific on-resistance of the drift region and was used to assess the capabilities of a semiconductor from the standpoint of low-frequency devices. For the

From Table 2, it can be noticed that the figures of merit for diamond are at least 40–50 times more than those of any other semiconductor material (except for Keyes' criterion). On the other hand, SiC polytypes and GaN have more or less similar figures of merit, which implies similar performances. assessment of high-frequency devices, the losses associated with the commutations must also be considered. The criterion BHFM = µ Ec2, based on the assumption that switching losses are caused by the recharging input capacitance of a device, was proposed in [18]. Finally, Schneider proposed a figure of merit to assess the performances of high-voltage bipolar components, taking into account the thermal dissipation and maximum operating temperature of the

semiconductor material [19]: SFM = E<sup>c</sup> (µN+µP) λTmax.

similar figures of merit, which implies similar performances.

Table 2. . Main figures of merit for WBG semiconductors compared with Si.


**Table 2.** Main figures of merit for WBG semiconductors compared with Si.

#### **2.2. Wide band gap power devices**

Johnson has proposed to use the product of the breakdown electric field and the saturation velocity as a figure of merit (JFM), which determines the ultimate power-frequency capability

**Figure 2.** Theoretical limits of Si and WBG unipolar components on-state resistance as a function of the maximum sup‐

<sup>10</sup><sup>5</sup> <sup>10</sup>-4

Maximum supported voltage [V]

has proposed yet another figure of merit (BFM) for evaluating a semiconductor material. It is

mobility of current carriers). However, this criterion was associated primarily with ohmic losses due to the specific on-resistance of the drift region and was used to assess the capabilities of a semiconductor from the standpoint of low-frequency devices. For the assessment of highfrequency devices, the losses associated with the commutations must also be considered. The

recharging input capacitance of a device, was proposed in [18]. Finally, Schneider proposed a figure of merit to assess the performances of high-voltage bipolar components, taking into account the thermal dissipation and maximum operating temperature of the semiconductor

to the operating losses of a high-power field-effect transistor: BFM = ε<sup>r</sup> µ E<sup>c</sup>

From Table 2, it can be noticed that the figures of merit for diamond are at least 40–50 times more than those of any other semiconductor material (except for Keyes' criterion). On the other hand, SiC polytypes and GaN have more or less similar figures of merit, which implies similar

related to the operating losses of a high-power field-effect transistor: BFM = *ε*<sup>r</sup> *μ E*<sup>c</sup>

1/2, which provides a thermal limitation to the switching behavior of transistors. Baliga

*.* Later, the following criterion was defined by Keyes: KFM =

104

, based on the assumption that switching losses are caused by the

3

From Table 2, it can be noticed that the figures of merit for diamond are at least 40–50 times more than those of any other semiconductor material (except for Keyes' criterion). On the other hand, SiC polytypes and GaN have more or less

> JFM 1 215.1 277.8 277.8 215.5 81000 KFM 1 5 5.1 3.7 1.5 35.3 BFM 1 222.8 158.6 129.9 188.3 25319 BHFM 1 35.9 23.1 23.7 37 1629.6 SFM 1 64.4 39.5 19 30.8 5207.1

Si SiC (4H) SiC (6H) SiC (3C) GaN Diamond

This permits to highlight another advantage of WBG components over classical Si ones. Indeed, Figure 2 represents the on-state resistance ron as a function of the maximum supported voltage for Si and WBG unipolar components, once again at 300 K. Commonly, a value of a few hundreds of m�·cm<sup>2</sup> yields reasonable conduction losses. In that case, Figure 2

Si limit <sup>T</sup> = 300 K

Diamond limit

(with *μ* the

2

103

SiC limit

GaN limit

semiconductor material [19]: SFM = E<sup>c</sup> (µN+µP) λTmax.

similar figures of merit, which implies similar performances.

Table 2. . Main figures of merit for WBG semiconductors compared with Si.

components can support a few tens of kilovolts.

of the material: JFM = (*E*<sup>c</sup> *v*sat /π*)*

the corresponding category.

criterion BHFM = *μ E*<sup>c</sup>

performances.

2

material [19]: SFM = *E*c (*μ*N*+μ*P) *λT*max.

*λ* (*v*sat /*ε*r)

300 K.

ported voltage, at 300 K.

102

<sup>10</sup>-2

100

On-state resistance

 ron

[mΩ⋅cm²]

102

104

106

108

148 Advanced Silicon Carbide Devices and Processing

Collecting enough information about WBG devices in order to enrich the database of the existing CAD tool was a difficulty of this work. Indeed, these technologies are relatively recent and their market penetration is still at the beginning. Components switching times and losses, on-state resistances, etc., were for instance difficult to obtain. Consequently, an important bibliographical task has been performed in order to create a database sufficiently rich to be exploited, by consulting the scientific literature and manufacturer data sheets, and by partic‐ ipating to international conferences and exhibitions.

Figure 2. Theoretical limits of Si and WBG unipolar components on-state resistance as a function of the maximum supported voltage, at For a comparison of the possible power electronics performances of these materials, some commonly known figures of merit, i.e., special quality criteria, are listed in Table 2 [17,18]. The values reported in this table have been calculated from the data given in Table 1 and normalized with respect to Si. A larger value represents a better material performance in Currently, the only SiC semiconductor devices which are widely available are unipolar components (MOSFETs and Junction Field Effect Transistors, or JFETs). On the contrary, bipolar components as, e.g., insulated gate bipolar transistors (IGBTs), are still in research and development phase (some prototypes have nevertheless been presented in literature, see, e.g., [14] for a summary). GaN-on-Si switches have been introduced and commercialized for applications in power electronics converters. These switches benefit from fast switching times of GaN technology while maintaining a comparable cost with Si technology.

> Currently, several manufacturers are commercializing WBG power devices. Those that will be considered further in this chapter include the following:


**•** SiC Schottky diodes available from *Infineon*, *Fairchild*, *Cree*, *Semisouth*, etc., with ratings from 600 V/1 A up to 1.2 kV/30 A or 1.7 kV/25 A. Bipolar diodes and Junction Barrier Schottky (JBS) diodes will not be considered in this study.

Note that the database of WBG and classical Si devices will be completed over time in order to extent the design possibilities of the CAD tool. A version of the database is available from [21] but not reported here for the sake of conciseness.

It should also be noted that, even if the maximum working temperature of SiC material is theoretically superior to 700°C (see Table 1), for reasons of packaging, reliability, etc., the components currently available cannot be used at junction temperatures above 200°C (or even 175°C according to some manufacturers) [4]. Likewise, GaN power transistors from *EPC* should not be operated at a junction temperature higher than typically 125°C.

#### **3. DC-DC converters modeling**

Three types of models are commonly used in the design stages of electrical systems and components, namely, analytical models, simulation models (using dedicated software as, e.g., Saber or PSIM), and finite elements (FE) models. The choice of the type of model results from a trade-off between accuracy and computation time.

In this contribution, analytical models are adopted mainly for three reasons.

First, most of the analytical models that will be considered are available in the literature and well accepted among the researchers community. Some FE studies have also been conducted to confirm that the analytical and FE models show the same result tendencies. Second, analytical models have a lower computation time compared to the other types of models. This allows for exploring the entire search space in a reasonable amount of execution time when they are included in an optimization procedure. It is a key advantage for this work because the optimization procedure based on GA will require computing the values of the considered objectives a high number of times. Third, even if, in principle, analytical models are less accurate than the other types of models, this should not be taken as a limitation, at least in the scope of this study. Indeed, as the existing CAD tool compares together solutions obtained with the same models, a lack of accuracy in the computation of the objectives will be the same for all the solutions, and so will not affect the final choice of the designer.

The typical structure of an SMPS is shown in Figure 3. A DC input voltage is first converted into AC using a DC-AC (inverter) cell composed of power switches and diodes. A mediumor high-frequency transformer, which often comprises multiple windings, provides the electrical isolation and lowers the voltage levels. The AC voltage is then transformed using an AC-DC (rectifier) cell made of diodes and filtered with passive components (inductors and capacitors). Assuming only one output, the specifications of the converter are given by the three variables *V*d, *V*o, and *P*o, respectively, the input and output voltages, and the output power. Heat sinks are associated with both cells in order to keep the junction temperatures of the power devices within acceptable limits. The DC output is typically regulated by means of a feedback control loop that employs a pulse-width modulation controller.

**•** SiC Schottky diodes available from *Infineon*, *Fairchild*, *Cree*, *Semisouth*, etc., with ratings from 600 V/1 A up to 1.2 kV/30 A or 1.7 kV/25 A. Bipolar diodes and Junction Barrier Schottky

Note that the database of WBG and classical Si devices will be completed over time in order to extent the design possibilities of the CAD tool. A version of the database is available from

It should also be noted that, even if the maximum working temperature of SiC material is theoretically superior to 700°C (see Table 1), for reasons of packaging, reliability, etc., the components currently available cannot be used at junction temperatures above 200°C (or even 175°C according to some manufacturers) [4]. Likewise, GaN power transistors from *EPC*

Three types of models are commonly used in the design stages of electrical systems and components, namely, analytical models, simulation models (using dedicated software as, e.g., Saber or PSIM), and finite elements (FE) models. The choice of the type of model results from

First, most of the analytical models that will be considered are available in the literature and well accepted among the researchers community. Some FE studies have also been conducted to confirm that the analytical and FE models show the same result tendencies. Second, analytical models have a lower computation time compared to the other types of models. This allows for exploring the entire search space in a reasonable amount of execution time when they are included in an optimization procedure. It is a key advantage for this work because the optimization procedure based on GA will require computing the values of the considered objectives a high number of times. Third, even if, in principle, analytical models are less accurate than the other types of models, this should not be taken as a limitation, at least in the scope of this study. Indeed, as the existing CAD tool compares together solutions obtained with the same models, a lack of accuracy in the computation of the objectives will be the same

The typical structure of an SMPS is shown in Figure 3. A DC input voltage is first converted into AC using a DC-AC (inverter) cell composed of power switches and diodes. A mediumor high-frequency transformer, which often comprises multiple windings, provides the electrical isolation and lowers the voltage levels. The AC voltage is then transformed using an AC-DC (rectifier) cell made of diodes and filtered with passive components (inductors and capacitors). Assuming only one output, the specifications of the converter are given by the three variables *V*d, *V*o, and *P*o, respectively, the input and output voltages, and the output power. Heat sinks are associated with both cells in order to keep the junction temperatures of

should not be operated at a junction temperature higher than typically 125°C.

In this contribution, analytical models are adopted mainly for three reasons.

for all the solutions, and so will not affect the final choice of the designer.

(JBS) diodes will not be considered in this study.

150 Advanced Silicon Carbide Devices and Processing

[21] but not reported here for the sake of conciseness.

a trade-off between accuracy and computation time.

**3. DC-DC converters modeling**

**Figure 3.** Typical structure of an SMPS with an intermediate medium- or high-frequency transformer.

 Réseau alternatif

Designing a system using optimization algorithms implies to use models which represent the different constituting parts of the isolated DC-DC converter under study. Indeed, the optimi‐ zation procedures require multiple evaluations of several objective functions (e.g., the power losses and mass), while satisfying some constraints. Only electric and thermal models are of concern in this work. For the electrical aspect, the following parts need to be modeled:


For the thermal aspect, the following components need also to be modeled:


Note that all the employed analytical models are described in more detail in [1,21].

#### **4. Existing CAD tool**

The existing CAD tool, previously published by the authors [1,2], is briefly reviewed in this section. The basic structure of the tool, founded on a multiobjective optimization using GA, is shown in Figure 4.

The elitist nondominated sorting genetic algorithm, also known as NSGA-II [30], is used to perform search and optimization (such a choice is duly justified in [1,21]), whereas analytic models are used for the modeling of the power converters. The aim of this tool is to design converters optimized with respect to power loss, mass, and cost (the latter objective will not be considered in this chapter), while ensuring the satisfaction of constraints such as, e.g., appropriate limits on transformer or junctions temperature rise. Typical optimization variables (denoted *x* in Figure 4) are the switching frequency *f*s, the current density *J*<sup>w</sup> in the transformer windings, the maximum flux density *B*m in the magnetic core, the transformer size *via* dimensionless coefficients *k*1, *k*2, *k*3, the winding conductor diameter *d*s, the core material (among FeSi alloys, ferrite, nanocrystalline material and amorphous material), the conducting material (among copper -Cu- and aluminum -Al-), the type of DC-DC converter topology (among those mentioned in the previous section), the type of semiconductor devices (among silicon-based IGBT and power MOSFET), and the number of these devices associated in parallel per switch *N*dev, the number of DC-DC converter cells of the same topology which are associated in serial or parallel *N*cell as well as the kinds of input and output connections (series or parallel) of these cells (see Figure 5 for *N*cell = 2).

First, a random initial population is generated. The objective functions *F*(*x*) and constraints *g*(*x*) are evaluated based on the initial population and the specified analytical models of the isolated DC-DC converter. A convergence test is then performed to check for a termination criterion. If this criterion is not satisfied, the reproduction procedure using genetic operators (crossover and mutation) starts. A new population is so generated, and the previous steps are repeated until the termination criterion is verified. Otherwise, the Pareto front, i.e., the nondominated solutions within the entire search space, is plotted and the optimization procedure ends.

The DC-DC converter modeling part, from which the objective functions are evaluated, is now briefly described. First, the DC-DC converter specifications (input and output voltages, output power, etc.) and the constraints are fed into the computer memory. Then based on the values of some of the optimization variables, the converter topology and the kinds of core and conductor materials are selected. Recall that the design equations of each converter topology and the specifications of the materials are prestored in the computer memory. Once the topology has been chosen, the stresses on the semiconductor power devices and the specifi‐ cations of the filters and the transformer can be determined. Thus, the semiconductor devices with suitable ratings can be selected from the tool database, and the transformer and filters are designed. Hence, the total power loss of the magnetic components and the semiconductor devices is easily computed by using well-known formulae [31]. Then the heat sink is designed to keep the junction temperature rise of the semiconductor devices within the appropriate limits (typically 125°C for conventional Si-based components).

Finally, it should be noted that the main limitation of the CAD tool here described is that it can only be used in the first stages of the design procedure. In order to use it in the next phases, more accurate models of the converters should be considered.

**Figure 4.** Basic structure of the CAD tool founded on multiobjective optimization using NSGA-II.

### **5. Design of a high-power DC-DC converter for auxiliary railway power supply**

#### **5.1. Specifications**

For the thermal aspect, the following components need also to be modeled:

application).

152 Advanced Silicon Carbide Devices and Processing

**4. Existing CAD tool**

or parallel) of these cells (see Figure 5 for *N*cell = 2).

shown in Figure 4.

**•** *Heat sink modules*. They have to be designed in order to evacuate the heat produced by the conducting and switching losses of the semiconductor power devices, so that it is possible to keep their junction temperatures within acceptable limits. In this work, thermal resistance models are used, combined with information taken from the cooler manufacturer data sheets [28,29]. The heat transfer modes that will be considered further in the application examples are thermal conduction and natural convection (except, of course, for the space

**•** *Transformer*. In practice, the windings and magnetic core temperatures may not exceed the prescribed limits under the risk of being damaged. Thermal resistance networks are used

The existing CAD tool, previously published by the authors [1,2], is briefly reviewed in this section. The basic structure of the tool, founded on a multiobjective optimization using GA, is

The elitist nondominated sorting genetic algorithm, also known as NSGA-II [30], is used to perform search and optimization (such a choice is duly justified in [1,21]), whereas analytic models are used for the modeling of the power converters. The aim of this tool is to design converters optimized with respect to power loss, mass, and cost (the latter objective will not be considered in this chapter), while ensuring the satisfaction of constraints such as, e.g., appropriate limits on transformer or junctions temperature rise. Typical optimization variables (denoted *x* in Figure 4) are the switching frequency *f*s, the current density *J*<sup>w</sup> in the transformer windings, the maximum flux density *B*m in the magnetic core, the transformer size *via* dimensionless coefficients *k*1, *k*2, *k*3, the winding conductor diameter *d*s, the core material (among FeSi alloys, ferrite, nanocrystalline material and amorphous material), the conducting material (among copper -Cu- and aluminum -Al-), the type of DC-DC converter topology (among those mentioned in the previous section), the type of semiconductor devices (among silicon-based IGBT and power MOSFET), and the number of these devices associated in parallel per switch *N*dev, the number of DC-DC converter cells of the same topology which are associated in serial or parallel *N*cell as well as the kinds of input and output connections (series

First, a random initial population is generated. The objective functions *F*(*x*) and constraints *g*(*x*) are evaluated based on the initial population and the specified analytical models of the isolated DC-DC converter. A convergence test is then performed to check for a termination criterion. If this criterion is not satisfied, the reproduction procedure using genetic operators (crossover and mutation) starts. A new population is so generated, and the previous steps are repeated until the termination criterion is verified. Otherwise, the Pareto front, i.e., the

to estimate the working temperatures and hot spots inside the transformer.

Note that all the employed analytical models are described in more detail in [1,21].

Auxiliary power supplies are used in modern railways coaches to provide a continuous energy supply to auxiliary equipments such as lighting, air conditioning, pressure protection, etc.

**Figure 5.** Possible associations between the DC-DC converters cells for *N*cell = 2.

They are directly connected to the catenary and represent the interface between the overhead line and the vehicle onboard low voltage consumers. Currently, the galvanic isolation is realized by a heavy and bulky 50 Hz transformer. However, in order to reduce the size and mass of the devices (filters, transformer, etc.), the trend is to use new structures, which include an intermediate conversion stage using a lightweight MF transformer (typically several kilohertz) [32]. The principle scheme of such a structure to supply a three-phase 400 V AC consumer is illustrated in Figure 6. Note that only the part framed by the dashed line, which represents an SMPS of the type shown in Figure 3, will be subject to the MO optimization.

Some typical electrical specifications of an auxiliary railway SMPS are given in Table 3. These specifications match with a 1.5 kV DC catenary system. The continuous failure-free operation of the power supply must be guaranteed within the following limits of the DC supply voltage [33]:

$$1.0.67\ V\_{d,nom} \le V\_d \le 1.3\ V\_{d,nom} \tag{2}$$

where *V*d,nom is the conventional nominal value of the catenary voltage.

**Figure 6.** Principle scheme of a high-power SMPS with an intermediate isolated DC-DC conversion stage.


**Table 3.** Typical specifications of an auxiliary railway SMPS matching with a 1.5-kV DC catenary system.

They are directly connected to the catenary and represent the interface between the overhead line and the vehicle onboard low voltage consumers. Currently, the galvanic isolation is realized by a heavy and bulky 50 Hz transformer. However, in order to reduce the size and mass of the devices (filters, transformer, etc.), the trend is to use new structures, which include an intermediate conversion stage using a lightweight MF transformer (typically several kilohertz) [32]. The principle scheme of such a structure to supply a three-phase 400 V AC consumer is illustrated in Figure 6. Note that only the part framed by the dashed line, which represents an SMPS of the type shown in Figure 3, will be subject to the MO optimization.

Parallèle / Série Parallèle / Parallèle

Parallel/series Parallel/parallel

**DC**

154 Advanced Silicon Carbide Devices and Processing

2 *Vd*

2 *Vd*

*Vd*

*Vd*

*DC*

*DC*

*DC*

**DC**

*Vd Vd*

2 *Vo*

*Vo*

DC-DC cell

**Cellule de conversion d'énergie MF**

*DC*

2

2 *Vd* *DC*

*DC*

*DC*

*Vd*

Série / Série Série / Parallèle

Series/series Series/parallel

*DC*

*Vo*

*Vd Vo*

*DC*

*DC*

*Vd Vo*

*Vd Vo*

*DC*

2 *Vo*

2 *Vo*

> 2 *Vo*

*Vo*

*Vo*

*Vd Vo*

*DC*

*DC*

*DC*

**Figure 5.** Possible associations between the DC-DC converters cells for *N*cell = 2.

Some typical electrical specifications of an auxiliary railway SMPS are given in Table 3. These specifications match with a 1.5 kV DC catenary system. The continuous failure-free The optimization variables (denoted *x* in the previous section) are listed in Table 4. Recall that, in this contribution, the database of the CAD tool was enriched with WBG semiconductor power devices. Hence, the type of switching semiconductor devices can now be selected among Si IGBT, Si MOSFET, Si MOSFET with SiC antiparallel diode, SiC JFET, and SiC MOSFET. The rectifier diodes can be chosen, as for them, between Si or SiC Schottky devices.

The constraints that have to be ensured are of two natures: thermal and technological. The thermal constraints concern the semiconductor devices (maximum junction temperature limited to 150°C using SiC components) and the MF transformer (maximum temperatures for the windings and the magnetic core which cannot exceed 180°C and 125°C, respectively). From the technological aspect, the lower and upper bounds of each component of *x* are reported in the third column of Table 4. The current loss factor (defined from the Dowell model) is also limited to 1.25, and some constraints must be added in order to verify that the windings can be inserted in the window area of the magnetic component.


**Table 4.** Optimization variables for the design of an auxiliary railway SMPS.

#### **5.2. Results using SiC and Si technologies**

The Pareto front obtained for the two-objective problem (minimizing the power losses and mass) is shown in Figure 7. These results have been obtained in 140 s CPU time, with a 3.4 GHz processor and 3 Gb RAM. The population size, i.e., the number of individuals in the front, and the number of generations were set to 100 and 500, respectively.

All the optimal solutions combine two DC-DC cells in full-bridge topology (series input and parallel output associations). The series input association permits to use semiconductor devices with lower voltage ratings than the maximum input voltage *V*d,max (=1.95 kV). The

Transformer winding current density J<sup>w</sup>

Transformer geometrical factor k<sup>1</sup>

Transformer geometrical factor k<sup>2</sup>

Transformer geometrical factor k<sup>3</sup>

Maximum flux density in magnetic core B<sup>m</sup>

Winding conductor diameter ds

Number of parallel semiconductor devices per switch Ndev

Type of switching

Input connection (series or

Output connection (series or

5.2. Results using SiC and Si technologies

Table 4. Optimization variables for the design of an auxiliary railway SMPS.

Continuous [1; 6] A/mm<sup>2</sup>- -

Continuous [1; 5] - -

Continuous [1; 5] - -

Continuous [1; 2] - -

Continuous [0.01; Bsat] T - -

Discrete 2 {1;2;3}

mm - -

Continuous [0.04; 0.56]

Magnetic material Discrete 2 {0;1;2;3} DC-DC topology Discrete 3 {0;1;2;3;4}

semiconductor devices Discrete 3 {0;1;2;3;4}

parallel) Zero-one 1 {0;1}

parallel) Zero-one 1 {0;1}

Type of rectifier diodes Zero-one 1 {0;1}

the number of individuals in the front, and the number of generations were set to 100 and 500, respectively.

Number of DC-DC cells Ncell Discrete 2 {1;2;3} Conducting material Zero-one 1 {0;1}

limited to 1.25, and some constraints must be added in order to verify that the windings can

Switching frequency *f* <sup>s</sup> Continuous [1; 200] kHz - -

Transformer geometrical factor *k* <sup>1</sup> Continuous [1; 5] - - Transformer geometrical factor *k* <sup>2</sup> Continuous [1; 5] - - Transformer geometrical factor *k* <sup>3</sup> Continuous [1; 2] - -

Winding conductor diameter *d* <sup>s</sup> Continuous [0.04; 0.56] mm - -

Number of DC-DC cells *N* cell Discrete 2 {1;2;3} Conducting material Zero-one 1 {0;1}

Type of rectifier diodes Zero-one 1 {0;1}

The Pareto front obtained for the two-objective problem (minimizing the power losses and mass) is shown in Figure 7. These results have been obtained in 140 s CPU time, with a 3.4 GHz processor and 3 Gb RAM. The population size, i.e., the number of individuals in the front,

All the optimal solutions combine two DC-DC cells in full-bridge topology (series input and parallel output associations). The series input association permits to use semiconductor devices with lower voltage ratings than the maximum input voltage *V*d,max (=1.95 kV). The

Input connection (series or parallel) Zero-one 1 {0;1} Output connection (series or parallel) Zero-one 1 {0;1}

**Table 4.** Optimization variables for the design of an auxiliary railway SMPS.

and the number of generations were set to 100 and 500, respectively.

**5.2. Results using SiC and Si technologies**

Magnetic material Discrete 2 {0;1;2;3} DC-DC topology Discrete 3 {0;1;2;3;4}

**Bounds (continuous variables)**

Continuous [1; 6] A/mm2 - -

Continuous [0.01; *B* sat] T - -

Discrete 2 {1;2;3}

Discrete 3 {0;1;2;3;4}

**String length**

**Possible values (discrete variables)**

be inserted in the window area of the magnetic component.

**Variables Type**

Transformer winding current density *J* w

156 Advanced Silicon Carbide Devices and Processing

Maximum flux density in magnetic core *B* <sup>m</sup>

Number of parallel semiconductor devices per switch *N* dev

Type of switching semiconductor devices

Figure 7. Pareto front of the two-objective problem using SiC and Si devices in the case of the design of a high-power SMPS (blue stars stand for optimal solutions in full-bridge topology). **Figure 7.** Pareto front of the two-objective problem using SiC and Si devices in the case of the design of a high-power SMPS (blue stars stand for optimal solutions in full-bridge topology).

parallel output association allows for the use of power devices with smaller current capabili‐ ties. All the optimal solutions combine two DC-DC cells in full-bridge topology (series input and parallel output associations). The series input association permits to use semiconductor devices with lower voltage ratings than the

For every solution, the number of parallel semiconductor devices (1.2 kV/100 A SiC MOSFET) per switch is two. The rectifier diodes are all Si-based with ratings 1.7 kV/200 A. SiC Schottky diodes are not selected here because, to the best of our knowledge, such current capability is still not available and, in its current state of development, the CAD tool does not offer the possibility to connect several rectifier diodes in parallel.

The values of the other optimization variables are reported in Table 5 for three points of the Pareto front (see solutions 1 to 3 in Figure 7), including solution 3, which is the closest to the ideal one. This utopic solution is constructed by keeping the minimum of each objective separately. As can be seen, some of the variables have converged towards their optimal value. In all cases, the windings are composed of Litz wire (either made of aluminum or copper), with an optimal elementary conductor diameter of 0.2 mm, and the transformer is designed with a ferrite core whose geometrical factor *k*3 is approximately 1.6. The maximum flux density *B*<sup>m</sup> in the core is around 25% of the saturation value *B*sat of the employed ferrites. Such a small value results from a trade-off between the two considered objectives, which can be explained as follows.

According to the area product method, which is used here to model the transformer, its mass *m*TFO is linked to the maximum flux density by

$$m\_{\rm TFO} \propto B\_{\rm max}^{-34} \tag{3}$$

On the other hand, the natural Steimetz equation permits to express the magnetic loss density (in W/kg) as a function of *B*m:

$$P\_{mugn} \propto B\_{max}^{\rho} \tag{4}$$

with *β* varying between 2 and 2.5, depending on the selected core material. If *B*m is doubled, *m*TFO is multiplied by 0.59 (=1/23/4), whereas *P*magn is multiplied by a value comprised between 4 and 5.65. Hence, the magnetic losses in the core, *P*magn × *m*TFO, are multiplied by a factor between 2.36 and 3.33. Since the mass and the power losses have to be minimized jointly, it can be concluded that the gain in terms of mass with a high value of *B*m does not compensate the ensuing losses. This is the reason of the relatively small values obtained for the maximum flux density *B*m in this design example.

Note that the values of the switching frequency are not discussed here as a detailed analysis will be conducted in the following subsection.


**Table 5.** Analysis of three solutions of the Pareto front shown in Figure 7.

#### **5.3. Comparison with Si technology only**

The optimization procedure is now carried out using Si technology only, with approximately the same execution time as above. Hence, the two Pareto fronts using Si and SiC technologies are shown in Figure 8 for comparison.

Using SiC technology clearly leads to lighter power converters with reduced power losses. Let us compare, for example, the power losses at a given mass (say 100 kg). In Figure 8, the corresponding power converters dissipate 4.5 kW in Si technology against only 2.8 kW taking into account SiC devices, which corresponds to a 1.7% gain in terms of efficiency. Similarly, for a given power loss (say 4 kW), the gain in mass is 53% (150 kg in Si technology against 70 kg with SiC).

A detailed analysis of the two Pareto fronts shows that the only design variable which differs significantly from the use of one or the other technology is the switching frequency *f*s. In this vein, Figures 9 and 10 show the variations of the switching frequency along the two Pareto fronts as functions of each objective. As can be seen, *f*s is up to 22 kHz for the optimal solutions designed in SiC, against maximum 6.7 kHz using Si devices only.

2000 2500 3000 3500 4000 4500 5000 5500

2 2.5 3 3.5 4 4.5 5 5.5

Pareto Front

Front de en technologie SiC Pareto

Pareto front using SiC and Si technologies

Front de en technologie Si Pareto

Pareto front using Si technology only

> Pont complet (2 ou 3 cellules)

Full-bridge (2 or 3 cells)

50

50

100

100

150

150

200

200

Masse [kg] Masse [kg]

Mass [kg]

250

250

300

300

350

350

400

400

On the other hand, the natural Steimetz equation permits to express the magnetic loss density

b

with *β* varying between 2 and 2.5, depending on the selected core material. If *B*m is doubled, *m*TFO is multiplied by 0.59 (=1/23/4), whereas *P*magn is multiplied by a value comprised between 4 and 5.65. Hence, the magnetic losses in the core, *P*magn × *m*TFO, are multiplied by a factor between 2.36 and 3.33. Since the mass and the power losses have to be minimized jointly, it can be concluded that the gain in terms of mass with a high value of *B*m does not compensate the ensuing losses. This is the reason of the relatively small values obtained for the maximum

Note that the values of the switching frequency are not discussed here as a detailed analysis

1 22.2 3.27 3.11 3.73 1.61 0.09 0.2 Ferrite Al 2 10.3 3.22 3.03 3.29 1.61 0.11 0.2 Ferrite Al 3 4.3 2.32 2.41 2.77 1.59 0.13 0.2 Ferrite Cu

The optimization procedure is now carried out using Si technology only, with approximately the same execution time as above. Hence, the two Pareto fronts using Si and SiC technologies

Using SiC technology clearly leads to lighter power converters with reduced power losses. Let us compare, for example, the power losses at a given mass (say 100 kg). In Figure 8, the corresponding power converters dissipate 4.5 kW in Si technology against only 2.8 kW taking into account SiC devices, which corresponds to a 1.7% gain in terms of efficiency. Similarly, for a given power loss (say 4 kW), the gain in mass is 53% (150 kg in Si technology against 70

A detailed analysis of the two Pareto fronts shows that the only design variable which differs significantly from the use of one or the other technology is the switching frequency *f*s. In this vein, Figures 9 and 10 show the variations of the switching frequency along the two Pareto fronts as functions of each objective. As can be seen, *f*s is up to 22 kHz for the optimal solutions

*] k1 k2 k3 Bm [T] ds [mm]* **Magnetic**

µ (4)

**material**

**Conducting material**

*magn max P B*

(in W/kg) as a function of *B*m:

158 Advanced Silicon Carbide Devices and Processing

flux density *B*m in this design example.

**No.** *fs [kHz] Jw [A/mm2*

will be conducted in the following subsection.

**Table 5.** Analysis of three solutions of the Pareto front shown in Figure 7.

designed in SiC, against maximum 6.7 kHz using Si devices only.

**5.3. Comparison with Si technology only**

are shown in Figure 8 for comparison.

kg with SiC).

optimal solutions designed in SiC, against maximum 6.7 kHz using Si devices only. Figure 8. Pareto fronts of the two-objective problem in the case of the design of a high-power SMPS. Comparison between Si only and **Figure 8.** Pareto fronts of the two-objective problem in the case of the design of a high-power SMPS. Comparison be‐ tween Si only and SiC+Si technologies (blue stars stand for optimal solutions in full bridge topology).

SiC+Si technologies (blue stars stand for optimal solutions in full bridge topology).

Figure 9. Variation of the switching frequency along the two Pareto fronts shown in Figure 8, as a function of the power losses. **Figure 9.** Variation of the switching frequency along the two Pareto fronts shown in Figure 8, as a function of the pow‐ er losses. 10 [kHz]<sup>s</sup>ffs [kHz]10

<sup>2000</sup> <sup>2500</sup> <sup>3000</sup> <sup>3500</sup> <sup>4000</sup> <sup>4500</sup> <sup>5000</sup> <sup>5500</sup> <sup>0</sup>

Pertes [W]

Power losses [kW] 2 2.5 3 3.5 4 4.5 5 5.5

5

5

0

15

15

Figure 9. Variation of the switching frequency along the two Pareto fronts shown in Figure 8, as a function of the power losses.

Figure 10. Variation of the switching frequency along the two Pareto fronts shown in Figure 8, as a function of the mass. **Figure 10.** Variation of the switching frequency along the two Pareto fronts shown in Figure 8, as a function of the mass.

Several more comments can be made about the results shown in these figures. First, at a given switching frequency, the power losses are significantly reduced in SiC technology. For instance, a reduction of at least 1 kW is expected at 5 kHz, which corresponds to 1 % gain in efficiency. On the other hand, the masses are practically equal at 5 kHz as, for the considered application, the passive components largely contribute to the overall weight. The mass is, however, significantly lowered at higher values of the switching frequency by use of SiC devices. Several more comments can be made about the results shown in these figures. First, at a given switching frequency, the power losses are significantly reduced in SiC technology. For instance, a reduction of at least 1 kW is expected at 5 kHz, which corresponds to 1 % gain in efficiency. On the other hand, the masses are practically equal at 5 kHz as, for the considered application, the passive components largely contribute to the overall weight. The mass is, however, significantly lowered at higher values of the switching frequency by use of SiC devices.

Second, the variation of the switching frequency as a function of the power losses in SiC is more or less linear (see Figure 9), which can be explained by the fact that the total power loss is strongly impacted by the switching losses Psw, proportional to fs. On the other hand, the variation of fs as a function of the mass can be justified as follows. As said above, the overall mass of the DC-DC converter is mainly dominated by the passive components and, more particularly, the mass of the MF transformer, which is linked to the switching frequency by Second, the variation of the switching frequency as a function of the power losses in SiC is more or less linear (see Figure 9), which can be explained by the fact that the total power loss is strongly impacted by the switching losses *P*sw, proportional to *f*s. On the other hand, the variation of *f*<sup>s</sup> as a function of the mass can be justified as follows. As said above, the overall mass of the DC-DC converter is mainly dominated by the passive components and, more particularly, the mass of the MF transformer, which is linked to the switching frequency by

$$\mathfrak{m}\_{\text{TFO}} \propto f\_s^{-34} \tag{5}$$

0 500 1000 1500 2000 2500

Power losses [W]

Finally, the power loss distribution (conduction on and switching sw) related to the devices composing one of the DC-DC cells is shown in Figure 11, considering two solutions of the Pareto fronts (one on each front in Figure 8) at the same switching frequency of 5 kHz and with the same number of cells. Depending on the technology, the switching devices (T) are either 1.2 kV/150 A Si IGBTs or 1.2 kV/100 A SiC MOSFETs. For reasons already mentioned, the rectification stage of the DC-DC cell is made of Si diodes (D) with ratings 1.7 kV/200 A, whatever the case. As can be seen in Figure 11, a

> Série1 Série2 Série3 Série4

PT,on PT,sw PD,on PD,sw

global power losses reduction of 36.2% is achieved or, even, 47.1% disregarding the losses due the diodes.

f<sup>s</sup> = 5 kHz

Gain of 36.2 %

according to the area product method. This result is more or less in line with the shape of the SiC-based evolution according to the area product method. This result is more or less in line with the shape of the SiC-based evolution represented in Figure 10.

3 4 m f TFO s

SiC

SiC+Si

Si

Si only

<sup>−</sup> ∝ (5)

represented in Figure 10. Finally, the power loss distribution (conduction *on* and switching *sw*) related to the devices composing one of the DC-DC cells is shown in Figure 11, considering two solutions of the

> Gain of 47.1 %

significantly lowered at higher values of the switching frequency by use of SiC devices.

the mass of the MF transformer, which is linked to the switching frequency by

0 50 100 150 200 250 300 350 400

0 50 100 150 200 250 300 350 400

 Technologie SiC Technologie Si

SiC and Si technologies

• •

Si technology only

Masse [kg]

Mass [kg]

Figure 10. Variation of the switching frequency along the two Pareto fronts shown in Figure 8, as a function of the mass.

Several more comments can be made about the results shown in these figures. First, at a given switching frequency, the power losses are significantly reduced in SiC technology. For instance, a reduction of at least 1 kW is expected at 5 kHz, which corresponds to 1 % gain in efficiency. On the other hand, the masses are practically equal at 5 kHz as, for the considered application, the passive components largely contribute to the overall weight. The mass is, however,

Second, the variation of the switching frequency as a function of the power losses in SiC is more or less linear (see Figure 9), which can be explained by the fact that the total power loss is strongly impacted by the switching losses Psw, proportional to fs. On the other hand, the variation of fs as a function of the mass can be justified as follows. As said above, the overall mass of the DC-DC converter is mainly dominated by the passive components and, more particularly,

according to the area product method. This result is more or less in line with the shape of the SiC-based evolution

Finally, the power loss distribution (conduction on and switching sw) related to the devices composing one of the DC-DC

Pareto fronts (one on each front in Figure 8) at the same switching frequency of 5 kHz and with the same number of cells. Depending on the technology, the switching devices (*T*) are either 1.2 kV/150 A Si IGBTs or 1.2 kV/100 A SiC MOSFETs. For reasons already mentioned, the rectification stage of the DC-DC cell is made of Si diodes (*D*) with ratings 1.7 kV/200 A, whatever the case. As can be seen in Figure 11, a global power losses reduction of 36.2% is achieved or, even, 47.1% disregarding the losses due the diodes. cells is shown in Figure 11, considering two solutions of the Pareto fronts (one on each front in Figure 8) at the same switching frequency of 5 kHz and with the same number of cells. Depending on the technology, the switching devices (T) are either 1.2 kV/150 A Si IGBTs or 1.2 kV/100 A SiC MOSFETs. For reasons already mentioned, the rectification stage of the DC-DC cell is made of Si diodes (D) with ratings 1.7 kV/200 A, whatever the case. As can be seen in Figure 11, a global power losses reduction of 36.2% is achieved or, even, 47.1% disregarding the losses due the diodes.

considered application, the passive components largely contribute to the overall weight. The mass is, however, significantly lowered at higher values of the switching frequency by use of SiC devices. **Figure 11.** Power losses distribution in the semiconductor devices of one DC-DC cell of the high-power SMPS. Com‐ parison between Si only and SiC+Si technologies, considering two solutions at the same switching frequency.

#### 9), which can be explained by the fact that the total power loss is strongly impacted by the switching losses Psw, **6. Design of a low-power DC-DC converter for space application**

#### proportional to fs. On the other hand, the variation of fs as a function of the mass can be justified as follows. As said above, the overall mass of the DC-DC converter is mainly dominated by the passive components and, more particularly, **6.1. Specifications**

3 4 m f TFO s

0

0

5

5

10

10

15

15

 [kHz]

[kHz]

<sup>s</sup>f

fs 20

20

25

25

<sup>−</sup> ∝ (5)

Second, the variation of the switching frequency as a function of the power losses in SiC is more or less linear (see Figure

Finally, the power loss distribution (conduction on and switching sw) related to the devices composing one of the DC-DC cells is shown in Figure 11, considering two solutions of the Pareto fronts (one on each front in Figure 8) at the same switching frequency of 5 kHz and with the same number of cells. Depending on the technology, the switching devices (T) are either 1.2 kV/150 A Si IGBTs or 1.2 kV/100 A SiC MOSFETs. For reasons already mentioned, the rectification stage of the DC-DC cell is made of Si diodes (D) with ratings 1.7 kV/200 A, whatever the case. As can be seen in Figure 11, a

> Série1 Série2 Série3 Série4

PT,on PT,sw PD,on PD,sw

global power losses reduction of 36.2% is achieved or, even, 47.1% disregarding the losses due the diodes.

f<sup>s</sup> = 5 kHz

Gain of 36.2 %

the mass of the MF transformer, which is linked to the switching frequency by


0 500 1000 1500 2000 2500

Gain of 47.1 %

Power losses [W]

0 50 100 150 200 250 300 350 400

0 50 100 150 200 250 300 350 400

 Technologie SiC Technologie Si

SiC and Si technologies

• •

Si technology only

Masse [kg]

**Figure 10.** Variation of the switching frequency along the two Pareto fronts shown in Figure 8, as a function of the

Several more comments can be made about the results shown in these figures. First, at a given switching frequency, the power losses are significantly reduced in SiC technology. For instance, a reduction of at least 1 kW is expected at 5 kHz, which corresponds to 1 % gain in efficiency. On the other hand, the masses are practically equal at 5 kHz as, for the considered application, the passive components largely contribute to the overall weight. The mass is, however, significantly lowered at higher values of the switching frequency by use of SiC

Second, the variation of the switching frequency as a function of the power losses in SiC is more or less linear (see Figure 9), which can be explained by the fact that the total power loss is strongly impacted by the switching losses *P*sw, proportional to *f*s. On the other hand, the variation of *f*<sup>s</sup> as a function of the mass can be justified as follows. As said above, the overall mass of the DC-DC converter is mainly dominated by the passive components and, more particularly, the mass of the MF transformer, which is linked to the switching frequency by

3 4 *m f TFO s*

according to the area product method. This result is more or less in line with the shape of the

Finally, the power loss distribution (conduction *on* and switching *sw*) related to the devices composing one of the DC-DC cells is shown in Figure 11, considering two solutions of the

Mass [kg]

3 4 m f TFO s

SiC-based evolution represented in Figure 10.

SiC

SiC+Si

Si

Si only

0

0

5

5

10

10

15

15

 [kHz]

[kHz]

<sup>s</sup>f

fs

mass.

devices.

20

20

25

25

160 Advanced Silicon Carbide Devices and Processing

<sup>−</sup> ∝ (5)

represented in Figure 10.

according to the area product method. This result is more or less in line with the shape of the SiC-based evolution Nowadays, SMPS are more and more used in aeronautics and for space applications. Figure 12 shows, for instance, the simplified architecture of a DC power distribution system embed‐ ded in a satellite where the primary power source consists of a solar array and batteries. Among all the electronic equipments connected to the main bus, several DC-DC power converters are used for the power matching between the DC interface and the different loads and batteries. These converters are subject to particular constraints related to the space environment that must be taken into account in the early stages of the design procedure. Typical examples of constraints are the presence of ionizing radiation, the absence of convection cooling, the degassing of certain materials, etc [34]. Their reliability is also of prime importance, which implies *inter alia* that the converters are most often designed fault-tolerant, and that the power switches must be derated with respect to their current and voltage capabilities.

**Figure 12.** Simplified architecture of a DC power distribution system embedded in a satellite [35].

This section deals with the MO design of an SMPS that can be mounted either on the platform or on the payload side of a satellite (see Figure 13). The power supply has a somewhat more complex structure compared to the previous application example. Indeed, it consists of a cascaded (two stages) DC-DC converter with an input filter [21,36,37]. The front-end stage is used to achieve a step-down (buck) voltage conversion in continuous conduction mode, whereas the back-end stage is a multioutput current-fed converter with a push-pull topology (without output inductor) taken here as an example. The main operational characteristics of the circuit are as follows [37]. First, the switching frequency of the buck stage is twice that of the push-pull converter, which is operating at *f*s. Second, one of the converter outputs (say *V*o1) is controlled by adjusting the duty ratio *D*<sup>B</sup> of the switch *T*1. Finally, the switches T2 and T3 are controlled alternately with a duty ratio of 0.5 (i.e., the push-pull stage just behaves as a nonregulated DC transformer providing electrical isolation). It is important to keep in mind that other topologies can be chosen to realize the output stage as, e.g., a half-bridge or full-bridge converter. It should also be noted that the SMPS considered here is not fault tolerant, in the sense that there is no redundancy of its components, but it tolerates the short circuit of one switch, whatever the stage it belongs to. Even so, in this case, the availability of the power supply will be lost.

The typical electrical specifications of the above shown SMPS are given in Table 6. These are in accordance with the DC-DC converter data sheet available in [36]. The optimization variables *x* are reported in Table 7, with their lower and upper bounds. Note that the indices "1" and "2" are chosen to indicate the buck and output stages, respectively. The topology of the latter is considered as an optimization variable. The type of the magnetic core material does

implies *inter alia* that the converters are most often designed fault-tolerant, and that the power

 Convertisseur continu - continu

Dc-dc power converter

converter

 Convertisseur continu - continu

Dc-dc power converter

DC-DC converter

Charge 1 Charge 2

Load #1 Load #2DC-DC

Load 1 Load 2

switches must be derated with respect to their current and voltage capabilities.

 Autres équipements

Other equipments

Other equipements

Chargeur de batteries

Batteries charger

DC-DC converter

Battery

**Figure 12.** Simplified architecture of a DC power distribution system embedded in a satellite [35].

This section deals with the MO design of an SMPS that can be mounted either on the platform or on the payload side of a satellite (see Figure 13). The power supply has a somewhat more complex structure compared to the previous application example. Indeed, it consists of a cascaded (two stages) DC-DC converter with an input filter [21,36,37]. The front-end stage is used to achieve a step-down (buck) voltage conversion in continuous conduction mode, whereas the back-end stage is a multioutput current-fed converter with a push-pull topology (without output inductor) taken here as an example. The main operational characteristics of the circuit are as follows [37]. First, the switching frequency of the buck stage is twice that of the push-pull converter, which is operating at *f*s. Second, one of the converter outputs (say *V*o1) is controlled by adjusting the duty ratio *D*<sup>B</sup> of the switch *T*1. Finally, the switches T2 and T3 are controlled alternately with a duty ratio of 0.5 (i.e., the push-pull stage just behaves as a nonregulated DC transformer providing electrical isolation). It is important to keep in mind that other topologies can be chosen to realize the output stage as, e.g., a half-bridge or full-bridge converter. It should also be noted that the SMPS considered here is not fault tolerant, in the sense that there is no redundancy of its components, but it tolerates the short circuit of one switch, whatever the stage it belongs to. Even so, in this case, the availability of the power

The typical electrical specifications of the above shown SMPS are given in Table 6. These are in accordance with the DC-DC converter data sheet available in [36]. The optimization variables *x* are reported in Table 7, with their lower and upper bounds. Note that the indices "1" and "2" are chosen to indicate the buck and output stages, respectively. The topology of the latter is considered as an optimization variable. The type of the magnetic core material does

Panneaux

Solar array

Solar array

supply will be lost.

solaires *bus <sup>v</sup>*

162 Advanced Silicon Carbide Devices and Processing

*vbus*

*Vd*

**Figure 13.** Principle scheme of an SMPS intended for a space application (in push-pull topology regarding the backend stage).

not appear as an optimization variable here because, for the SMPS under consideration, only

ferrite cores should be selected from the database due to technological constraints.


**Table 6.** Typical specifications of an SMPS intended for a space application.


**Table 7.** Optimization variables for the design of an SMPS intended for a space application.

#### **6.2. Changes to the existing tool**

In order to address this design problem, it was necessary to adapt the existing CAD tool to the specific requirements of the SMPS for space application. The main changes to the analytical models have been described in detail in [37]. They are briefly reviewed below:


maximum operating temperature, which results, in particular, in a reduction of the voltage and/or current ratings of the various components. Thus, for this application, a 50% voltage derating of the semiconductor devices is applied. Their current capability is also derated according to the junction temperature value of the component. A 50% current derating is adopted up to a junction temperature of 70°C and, above this limit, the current capability declines linearly to zero at 110°C.

**•** *Cooling of the components.* As there is no exchange of heat by convection in the vacuum and radiation is negligible inside the satellite, the thermal models must be modified to take into account only the heat transfer by conduction. For this application, the various components are located on a heat-pipe cooled plate, which is assumed isothermal at 60°C. The thermal model of a semiconductor device is represented with two thermal resistances, one between junction and case and the other between case and cooled plate. Similarly, the cooling of a magnetic component is only by conduction through the core surface in contact with the plate (through an aluminum sole-plate). An equivalent circuit of thermal resistances is adopted to deal with the heat transfers between the various parts of the element itself.

Note also that the design of the input filter shown in Figure 13 was fully described in [39], as well as the optimization of its shunt damping circuit. Thus, in the present contribution, this part of the SMPS is not directly optimized by GA. Instead, the procedure to calculate the filter elements was implemented as exposed in [37].

#### **6.3. Results using SiC and Si technologies**

**Variables Type**

Wire diameter of transformer coil *d* s,2 Continuous [0.032; 0.5] mm

Transformer winding current density *J* w,2

164 Advanced Silicon Carbide Devices and Processing

Maximum flux density in inductor core *B* m,1

Maximum flux density in transformer core *B* m,2

Number of parallel semiconductor devices per switch *N* dev,1

Number of parallel semiconductor devices per switch *N* dev,2

**6.2. Changes to the existing tool**

is used for windings instead of Litz wire.

**Bounds (continuous variables)**

Continuous [0.01; 0*.*38] T - -

Discrete 2 {1;2;3}

Discrete 2 {1;2;3}

Switching frequency *f* <sup>s</sup> Continuous [50; 250] kHz - - Inductor winding current density *J* w,1 Continuous [1; 6] A/mm2 - -

Continuous [1; 6] A/mm2

Continuous [0.01; 0*.*38] T

Inductor wire diameter *d* s,1 Continuous [0.032; 0.5] mm - -

DC-DC topology (output stage) Discrete 2 {0;1;2}

Type of switch *T* <sup>1</sup> Discrete 3 {0;1;2;3;4} Type of switches (output stage) Discrete 3 {0;1;2;3;4} Number of DC-DC cells *N* cell Discrete 2 {1;2;3} Conducting material Zero-one 1 {0;1} Input connection (series or parallel) Zero-one 1 {0;1} Output connection (series or parallel) Zero-one 1 {0;1}

Type of diode D1 Zero-one 1 {0;1} Type of rectifier diodes Zero-one 1 {0;1}

In order to address this design problem, it was necessary to adapt the existing CAD tool to the specific requirements of the SMPS for space application. The main changes to the analytical

**•** *Magnetic components*. The magnetic core is now selected from a database of ferrite cores (instead of being optimized from dimensionless geometric coefficients). In the case of a transformer, the RM ferrite core, which has an area product directly superior to the calcu‐ lated value, is selected from the database. In the case of an inductor, a toroidal core is chosen instead of an RM type one for reasons of mechanical design. Note also that enameled wire

**•** *Derating of the semiconductor devices*. In order to improve the reliability of the power con‐ verters used in space environment, different actions must be taken at the early design stage [38]. Among them, a part stress analysis is always performed taking into account the

**Table 7.** Optimization variables for the design of an SMPS intended for a space application.

models have been described in detail in [37]. They are briefly reviewed below:

**String length**

**Possible values (discrete variables)**

> The Pareto front of the two-objective problem using SiC and Si devices is represented in Figure 14. As can be seen, the power losses are reduced as the proportion of SiC devices grows. The CPU time needed to obtain these results was 173 s, which is comparable to the execution time related to the previous application example (with the same population size and number of generations).

> All the optimal solutions are designed with only one DC-DC cell (regarding the output stage), which corresponds to either a full-bridge or a push-pull configuration. The half-bridge topology is not retained here because, in that case, a capacitive divider is needed to obtain a voltage source behavior and the output filter inductor cannot be eliminated, which yields a higher number of passive components. It can be observed in Figure 14 that the full-bridge topology is interesting at low loss, but a higher mass since more semiconductor devices are needed, whereas the push-pull architecture is clearly the best trade-off between both objec‐ tives. The rectifier diodes are all Si-based with ratings 100 V/3 A for output 1 and 100 V/1 A for outputs 2 to 5. Indeed, the SiC diodes available from the current CAD tool database are rated at least for 600 V/1 A, which is much too high for the output voltage levels specified in Table 6.

> The values of the other optimization variables are reported in Table 8 for six particular solutions, including solution 4, which is the closest to the ideal point. Most of them have converged towards their optimal value. In particular, it is noticed that the switching frequency

and number of generations).

6.3. Results using SiC and Si technologies

The Pareto front of the two-objective problem using SiC and Si devices is represented in Figure 14. As can be seen, the power losses are reduced as the proportion of SiC devices grows. The CPU time needed to obtain these results was 173 s, which is comparable to the execution time related to the previous application example (with the same population size

All the optimal solutions are designed with only one DC-DC cell (regarding the output stage), which corresponds to either a full-bridge or a push-pull configuration. The half-bridge topology is not retained here because, in that case, a capacitive divider is needed to obtain a voltage source behavior and the output filter inductor cannot be eliminated, which yields a higher number of passive components. It can be observed in Figure 14 that the full-bridge topology is interesting at low loss, but a higher mass since more semiconductor devices are needed, whereas the push-pull architecture is clearly the best trade-off between both objectives. The rectifier diodes are all Si-based with ratings 100 V/3

> Transformer core

Conducting material

Diode D1 Switch T<sup>1</sup>

JFET SiC 500 V/5 A (6 in parallel)

JFET SiC 500 V/5 A (4 in parallel)

JFET SiC 500 V/5 A (2 in parallel)

JFET SiC 500 V/5 A (2 in parallel)

MOSFET Si 500 V/10 A (2 in parallel)

V/1 A

V/1 A

V/1 A

V/1 A

V/1 A

Switches (output stage)

JFET SiC 500 V/5 A (3 in parallel)

JFET SiC 500 V/5 A (2 in parallel)

JFET SiC 500 V/5 A

JFET SiC 500 V/5 A

JFET SiC 500 V/5 A

rated at least for 600 V/1 A, which is much too high for the output voltage levels specified in Table 6.

3 123 2 3.5 0.37 0.11 0.04 0.33 RM8 Al SiC 600

4 141 3.2 3.8 0.38 0.19 0.041 0.33 RM6 Al SiC 600

5 124 3.6 3.8 0.38 0.13 0.04 0.33 RM8 Al SiC 600

Figure 14. Pareto front of the two-objective problem using SiC and Si devices in the case of the design of a low-power SMPS (blue and **Figure 14.** Pareto front of the two-objective problem using SiC and Si devices in the case of the design of a low-power SMPS (blue and black stars stand for optimal solutions in full-bridge and push-pull topologies, respectively).

remains practically unchanged along the Pareto front (but for solution 4 where *f*<sup>s</sup> is equal to 141 kHz), which is in contrast with the previous design example. black stars stand for optimal solutions in full-bridge and push-pull topologies, respectively). The values of the other optimization variables are reported in Table 8 for six particular solutions, including solution 4,

In the power supply, the overall mass is distributed among the passive components (trans‐ former, etc.) and the semiconductor power devices. The corresponding repartition is shown in Figure 15 for the six solutions of interest. Unlike the application of an auxiliary railway SMPS, it can be seen that the passive components are no longer the main contributors with respect to that criterion, and for certain solutions, their mass may even be much less than that of the semiconductor devices (see, e.g., solution 1). This can be justified from the fact that the mass of a ferrite core (say of RM8 type), which has a strong impact on the calculation of the mass linked to the passive components, can be estimated at 13 g, whereas the one of a JFET SiC 500 V/5 A is already about 15 g and several of them are needed to constitute only one switch of the output stage. which is the closest to the ideal point. Most of them have converged towards their optimal value. In particular, it is noticed that the switching frequency remains practically unchanged along the Pareto front (but for solution 4 where fs is equal to 141 kHz), which is in contrast with the previous design example. No. <sup>f</sup><sup>s</sup> [kHz] Jw,1 [A/mm<sup>2</sup>] Jw,2 [A/mm<sup>2</sup>] B<sup>m</sup>,<sup>1</sup> [T] B<sup>m</sup>,<sup>2</sup> [T] d<sup>s</sup>,<sup>1</sup> [mm] d<sup>s</sup>,<sup>2</sup> [mm]

In the same way, Figure 16 shows the distribution of the power losses among the passive components and the semiconductor power devices. For the latter, the distinction is made between the conducting and switching losses. It can be observed that the total power dissipa‐ tion is mainly due to the on-state power losses, whatever the solution. The switching losses are, as for them, growing in importance as the proportion of SiC devices decreases from 1 123 2 3.5 0.37 0.05 0.04 0.33 RM8 Al SiC 600 2 123 2 3.5 0.37 0.05 0.041 0.33 RM8 Al SiC 600 A for output 1 and 100 V/1 A for outputs 2 to 5. Indeed, the SiC diodes available from the current CAD tool database are rated at least for 600 V/1 A, which is much too high for the output voltage levels specified in Table 6. Comparative Study of Optimally Designed DC-DC Converters with SiC and Si Power Devices http://dx.doi.org/10.5772/61018 167


which is the closest to the ideal point. Most of them have converged towards their optimal value. In particular, it is **Table 8.** Analysis of six solutions of the Pareto front shown in Figure 14.

noticed that the switching frequency remains practically unchanged along the Pareto front (but for solution 4 where fs is solutions 1 to 6, and the power losses in the passive components are about one order of magnitude less than the conduction losses.

#### Switches **6.4. Comparison with Si technology only**

parallel)

JFET SiC 500 V/5 A

JFET SiC 500 V/5 A

JFET SiC 500 V/5 A

parallel)

JFET SiC 500 V/5 A (2 in parallel)

JFET SiC 500 V/5 A (2 in parallel)

MOSFET Si 500 V/10 A (2 in parallel)

V/1 A

V/1 A

V/1 A

B<sup>m</sup>,<sup>1</sup> [T]

B<sup>m</sup>,<sup>2</sup> [T]

3 123 2 3.5 0.37 0.11 0.04 0.33 RM8 Al SiC 600

4 141 3.2 3.8 0.38 0.19 0.041 0.33 RM6 Al SiC 600

5 124 3.6 3.8 0.38 0.13 0.04 0.33 RM8 Al SiC 600

d<sup>s</sup>,<sup>1</sup> [mm]

d<sup>s</sup>,<sup>2</sup> [mm]

Transformer core

Conducting material

equal to 141 kHz), which is in contrast with the previous design example.

Jw,2 [A/mm<sup>2</sup>]

6.3. Results using SiC and Si technologies

and number of generations).

The Pareto front of the two-objective problem using SiC and Si devices is represented in Figure 14. As can be seen, the power losses are reduced as the proportion of SiC devices grows. The CPU time needed to obtain these results was 173 s, which is comparable to the execution time related to the previous application example (with the same population size

All the optimal solutions are designed with only one DC-DC cell (regarding the output stage), which corresponds to either a full-bridge or a push-pull configuration. The half-bridge topology is not retained here because, in that case, a capacitive divider is needed to obtain a voltage source behavior and the output filter inductor cannot be eliminated, which yields a higher number of passive components. It can be observed in Figure 14 that the full-bridge topology is interesting at low loss, but a higher mass since more semiconductor devices are needed, whereas the push-pull architecture is clearly the best trade-off between both objectives. The rectifier diodes are all Si-based with ratings 100 V/3

In the power supply, the overall mass is distributed among the passive components (trans‐ former, etc.) and the semiconductor power devices. The corresponding repartition is shown in Figure 15 for the six solutions of interest. Unlike the application of an auxiliary railway SMPS, it can be seen that the passive components are no longer the main contributors with respect to that criterion, and for certain solutions, their mass may even be much less than that of the semiconductor devices (see, e.g., solution 1). This can be justified from the fact that the mass of a ferrite core (say of RM8 type), which has a strong impact on the calculation of the mass linked to the passive components, can be estimated at 13 g, whereas the one of a JFET SiC 500 V/5 A is already about 15 g and several of them are needed to constitute only one switch

In the same way, Figure 16 shows the distribution of the power losses among the passive components and the semiconductor power devices. For the latter, the distinction is made between the conducting and switching losses. It can be observed that the total power dissipa‐ tion is mainly due to the on-state power losses, whatever the solution. The switching losses are, as for them, growing in importance as the proportion of SiC devices decreases from

Jw,1 [A/mm<sup>2</sup>]

No. <sup>f</sup><sup>s</sup>

[kHz]

of the output stage.

166 Advanced Silicon Carbide Devices and Processing

Diode D1 Switch T<sup>1</sup> (output stage) 1 123 2 3.5 0.37 0.05 0.04 0.33 RM8 Al SiC 600 V/1 A JFET SiC 500 V/5 A (6 in parallel) JFET SiC 500 V/5 A (3 in parallel) 2 123 2 3.5 0.37 0.05 0.041 0.33 RM8 Al SiC 600 V/1 A JFET SiC 500 V/5 A (4 in JFET SiC 500 V/5 A (2 in For comparison, the two Pareto fronts with and without including the selection of SiC devices in the optimization procedure are shown together in Figure 17. As can be observed, the two Pareto fronts merge each other when the objective of mass is preferred, which is consistent with the results reported in Figure 14 (where the lighter solutions are Si-based only). For a given mass (say 100 g), the power supply dissipates 4.6 W with Si against only 3.4 W, taking into account SiC devices, which corresponds to a 3.6% gain in terms of efficiency. Note also that all the solutions obtained with Si technology only correspond to one DC-DC cell in pushpull topology.

solutions in Table 8.

50

50

100

100

150

150

6.4. Comparison with Si technology only

switch of the output stage.

with Si technology only correspond to one DC-DC cell in push-pull topology.

6 124 3.6 3.8 0.38 0.22 0.04 0.33 RM7 Al Si 150 V/1

In the power supply, the overall mass is distributed among the passive components (transformer, etc.) and the semiconductor power devices. The corresponding repartition is shown in Figure 15 for the six solutions of interest. Unlike the application of an auxiliary railway SMPS, it can be seen that the passive components are no longer the main contributors with respect to that criterion, and for certain solutions, their mass may even be much less than that of the semiconductor devices (see, e.g., solution 1). This can be justified from the fact that the mass of a ferrite core (say of RM8 type), which has a strong impact on the calculation of the mass linked to the passive components, can be estimated at 13 g, whereas the one of a JFET SiC 500 V/5 A is already about 15 g and several of them are needed to constitute only one

In the same way, Figure 16 shows the distribution of the power losses among the passive components and the semiconductor power devices. For the latter, the distinction is made between the conducting and switching losses. It can be observed that the total power dissipation is mainly due to the on-state power losses, whatever the solution. The switching losses are, as for them, growing in importance as the proportion of SiC devices decreases from solutions 1 to 6, and the power losses in the passive components are about one order of magnitude less than the conduction losses.

For comparison, the two Pareto fronts with and without including the selection of SiC devices in the optimization procedure are shown together in Figure 17. As can be observed, the two Pareto fronts merge each other when the objective of mass is preferred, which is consistent with the results reported in Figure 14 (where the lighter solutions are

account SiC devices, which corresponds to a 3.6% gain in terms of efficiency. Note also that all the solutions obtained

Table 8. Analysis of six solutions of the Pareto front shown in Figure 14.

A

MOSFET Si 500 V/10 A (2 in parallel)

MOSFET Si 500 V/10 A

Figure 15. Repartition of the masses between the passive components and the semiconductor power devices for the six particular **Figure 15.** Repartition of the masses between the passive components and the semiconductor power devices for the six particular solutions in Table 8.

Figure 16. Distribution of the power losses among the passive components and the semiconductor devices (on-state and switching power losses) for the six particular solutions in Table 8. **Figure 16.** Distribution of the power losses among the passive components and the semiconductor devices (on-state and switching power losses) for the six particular solutions in Table 8.

200 250 300 350 Pareto Front Masse [g] 350 300 250 200 Mass [g] Pareto front in SiC and Si technologies Pareto front in Si technology only Mass [g] Finally, Figure 18 compares the power losses in the semiconductor devices, with and without SiC. To that end, two solutions of the Pareto fronts having the same mass of 100 g (one on each front in Figure 17) are selected. The switching frequency is equal to 100.2 kHz for the Si solution and to 119.9 kHz for the SiC one. Globally, a power losses reduction of 25.3% is obtained using SiC JFETs instead of Si MOSFETs as switching devices. As can be observed, the switching losses in the power transistors (*P*T,sw) are more particularly decreased (a gain of 97% is achieved in this case). On the other hand, as above-mentioned, all the rectifier diodes are Si-based, and that even for the solutions designed with SiC components. This is the reason why, in Figure

circles correspond to Si only solutions in push-pull topology).

3 3.5 4 4.5 5 5.5 6

3 3.5 4 4.5 5 5.5 6 Losses [W]

Pertes [W]

Power losses [W]

Figure 17. Pareto fronts of the two-objective problem in the case of the design of a low-power SMPS. Comparison between Si only and SiC+Si technologies (Blue and black stars stand for optimal SiC+Si solutions in full-bridge and push-pull topologies, respectively; black

Finally, Figure 18 compares the power losses in the semiconductor devices, with and without SiC. To that end, two solutions of the Pareto fronts having the same mass of 100 g (one on each front in Figure 17) are selected. The switching frequency is equal to 100.2 kHz for the Si solution and to 119.9 kHz for the SiC one. Globally, a power losses reduction of 25.3% is obtained using SiC JFETs instead of Si MOSFETs as switching devices. As can be observed, the switching losses in the power transistors (P<sup>T</sup>,sw) are more particularly decreased (a gain of 97% is achieved in this case). On the other hand, as above-mentioned, all the rectifier diodes are Si-based, and that even for the solutions designed with SiC components. This is the reason why, in Figure 18, the conduction losses of the diodes P<sup>D</sup>,on (≅2.8 W) are practically unchanged from one technology to the another. Still, the use of SiC to implement the freewheeling diode D1 of the buck stage (the latter operating at twice de switching frequency fs) allows for gain of 52.5% as regards the turn-off losses of the diodes P<sup>D</sup>,sw.

#1 #2 #3 #4 #5 #6

Figure 16. Distribution of the power losses among the passive components and the semiconductor devices (on-state and switching

Série1 Série2 Série3

On-state Switching

Passive components

25.3% is obtained using SiC JFETs instead of Si MOSFETs as switching devices. As can be observed, the switching losses

0

0

0,5

0.5

1

1

1,5

1.5

Power losses

 [W]

2

2

2,5

2.5

3

3

3,5

3.5

4

4

6 124 3.6 3.8 0.38 0.22 0.04 0.33 RM7 Al Si 150 V/1

In the power supply, the overall mass is distributed among the passive components (transformer, etc.) and the semiconductor power devices. The corresponding repartition is shown in Figure 15 for the six solutions of interest. Unlike the application of an auxiliary railway SMPS, it can be seen that the passive components are no longer the main contributors with respect to that criterion, and for certain solutions, their mass may even be much less than that of the semiconductor devices (see, e.g., solution 1). This can be justified from the fact that the mass of a ferrite core (say of RM8 type), which has a strong impact on the calculation of the mass linked to the passive components, can be estimated at 13 g, whereas the one of a JFET SiC 500 V/5 A is already about 15 g and several of them are needed to constitute only one

In the same way, Figure 16 shows the distribution of the power losses among the passive components and the semiconductor power devices. For the latter, the distinction is made between the conducting and switching losses. It can be observed that the total power dissipation is mainly due to the on-state power losses, whatever the solution. The switching losses are, as for them, growing in importance as the proportion of SiC devices decreases from solutions 1 to 6, and the power losses in the passive components are about one order of magnitude less than the conduction losses.

For comparison, the two Pareto fronts with and without including the selection of SiC devices in the optimization procedure are shown together in Figure 17. As can be observed, the two Pareto fronts merge each other when the objective of mass is preferred, which is consistent with the results reported in Figure 14 (where the lighter solutions are Si-based only). For a given mass (say 100 g), the power supply dissipates 4.6 W with Si against only 3.4 W, taking into account SiC devices, which corresponds to a 3.6% gain in terms of efficiency. Note also that all the solutions obtained

> Série2 Série3

> > Série1 Série2 Série3

On-state Switching

Passive components

Passive components Semiconductor devices

Figure 15. Repartition of the masses between the passive components and the semiconductor power devices for the six particular

Figure 16. Distribution of the power losses among the passive components and the semiconductor devices (on-state and switching

Figure 17. Pareto fronts of the two-objective problem in the case of the design of a low-power SMPS. Comparison between Si only and SiC+Si technologies (Blue and black stars stand for optimal SiC+Si solutions in full-bridge and push-pull topologies, respectively; black

Finally, Figure 18 compares the power losses in the semiconductor devices, with and without SiC. To that end, two solutions of the Pareto fronts having the same mass of 100 g (one on each front in Figure 17) are selected. The switching frequency is equal to 100.2 kHz for the Si solution and to 119.9 kHz for the SiC one. Globally, a power losses reduction of 25.3% is obtained using SiC JFETs instead of Si MOSFETs as switching devices. As can be observed, the switching losses in the power transistors (P<sup>T</sup>,sw) are more particularly decreased (a gain of 97% is achieved in this case). On the other hand, as above-mentioned, all the rectifier diodes are Si-based, and that even for the solutions designed with SiC components. This is the reason why, in Figure 18, the conduction losses of the diodes P<sup>D</sup>,on (≅2.8 W) are practically unchanged from one technology to the another. Still, the use of SiC to implement the freewheeling diode D1 of the buck stage (the latter operating at twice de switching frequency fs) allows for gain of 52.5% as regards the turn-off losses of the diodes P<sup>D</sup>,sw.

Table 8. Analysis of six solutions of the Pareto front shown in Figure 14.

switch of the output stage.

168 Advanced Silicon Carbide Devices and Processing

solutions in Table 8.

4 3.5 3 2.5 2 1.5 1 0.5 0

0 0,5 1 1,5 2 2,5 3 3,5 4

50

50

100

100

150

150

200

200

Masse [g]

Mass [g]

Mass [g]

250

250

300

300

350

350

Power losses

 [W]

particular solutions in Table 8.

0

50

100

150

200

250

300

Mass [g]

6.4. Comparison with Si technology only

with Si technology only correspond to one DC-DC cell in push-pull topology.

#1 #2 #3 #4 #5 #6

#1 #2 #3 #4 #5 #6

Pareto Front

Pareto front in SiC and Si technologies

Pareto front in Si technology only

**Figure 16.** Distribution of the power losses among the passive components and the semiconductor devices (on-state

Finally, Figure 18 compares the power losses in the semiconductor devices, with and without SiC. To that end, two solutions of the Pareto fronts having the same mass of 100 g (one on each front in Figure 17) are selected. The switching frequency is equal to 100.2 kHz for the Si solution and to 119.9 kHz for the SiC one. Globally, a power losses reduction of 25.3% is obtained using SiC JFETs instead of Si MOSFETs as switching devices. As can be observed, the switching losses in the power transistors (*P*T,sw) are more particularly decreased (a gain of 97% is achieved in this case). On the other hand, as above-mentioned, all the rectifier diodes are Si-based, and that even for the solutions designed with SiC components. This is the reason why, in Figure

power losses) for the six particular solutions in Table 8.

and switching power losses) for the six particular solutions in Table 8.

circles correspond to Si only solutions in push-pull topology).

3 3.5 4 4.5 5 5.5 6

3 3.5 4 4.5 5 5.5 6 Losses [W]

Pertes [W]

Power losses [W]

**Figure 15.** Repartition of the masses between the passive components and the semiconductor power devices for the six

A

MOSFET Si 500 V/10 A (2 in parallel)

MOSFET Si 500 V/10 A

Figure 17. Pareto fronts of the two-objective problem in the case of the design of a low-power SMPS. Comparison between Si only and SiC+Si technologies (Blue and black stars stand for optimal SiC+Si solutions in full-bridge and push-pull topologies, respectively; black **Figure 17.** Pareto fronts of the two-objective problem in the case of the design of a low-power SMPS. Comparison be‐ tween Si only and SiC+Si technologies (Blue and black stars stand for optimal SiC+Si solutions in full-bridge and pushpull topologies, respectively; black circles correspond to Si only solutions in push-pull topology).

18, the conduction losses of the diodes *P*D,on (≅2.8 W) are practically unchanged from one technology to the another. Still, the use of SiC to implement the freewheeling diode D1 of the buck stage (the latter operating at twice de switching frequency *f*s) allows for gain of 52.5% as regards the turn-off losses of the diodes *P*D,sw. circles correspond to Si only solutions in push-pull topology). Finally, Figure 18 compares the power losses in the semiconductor devices, with and without SiC. To that end, two solutions of the Pareto fronts having the same mass of 100 g (one on each front in Figure 17) are selected. The switching frequency is equal to 100.2 kHz for the Si solution and to 119.9 kHz for the SiC one. Globally, a power losses reduction of

Figure 18. Power losses distribution in the semiconductor devices of the low-power SMPS. Comparison between Si only and SiC+Si technologies, considering two solutions having the same mass of 100 g. **Figure 18.** Power losses distribution in the semiconductor devices of the low-power SMPS. Comparison between Si on‐ ly and SiC+Si technologies, considering two solutions having the same mass of 100 g.

In this chapter, power losses and mass of optimally designed Si- vs. SiC-based isolated DC-DC power converters have been compared in quantitative terms. Two application examples operating at very different output power levels have been studied: a 100 kW auxiliary railway SMPS and a multiple output 33.5 W SMPS intended for a space application. To that end, a CAD tool dedicated to the MO optimization of isolated DC-DC converters and based on genetic algorithms (NSGA-II in particular) has been employed. Fast analytical models have been used to account for the electrical and thermal phenomena occurring inside the power converters. An important effort has been made to enrich the database of the existing tool with WBG devices (mainly SiC) currently available from manufacturers. The results show clearly that the SiC technology leads to the design of lighter SMPS, with less power losses compared to Si technology only. Besides, the use of the MO optimization CAD tool permits to evaluate the gains in terms of power losses and mass from one

In future work, the packaging aspects using, e.g., analytical formulas accounting for the component integration in the power converter [40] and electromagnetic compatibility considerations (constraints on the voltage and current gradients) should be included in the tool. Performing a sensitivity analysis could be another perspective. Such an analysis would be useful to give a designer with important information about the stability of one particular optimal solution against others. It should also be reminded that the CAD tool used in this study is a predesign tool based on simple and fast analytical models. For example, rapid transients on switches and parasitic capacitive effects in the magnetic components are not taken into account. Once the optimal solution is chosen from the tool and the designer know-how, finer models have to be employed around that particular design configuration in order to refine the solution, at the cost of higher computational burden (performing, e.g., transient circuit simulations or using numerical methods such as the FE technique). Lastly, it should be noted that, in this study, GaN-based power transistors were not selected for the space application because their voltage ratings in the database are still too low. Yet since in a near future the commercial offer concerning WBG components is expected to drastically increase, the tool database will be completed over time and,

[1] Versèle C., Deblecker O., Lobry J. A computer-aided design tool dedicated to isolated DC-DC converters based on multiobjective optimization using genetic algorithms. COMPEL: International Journal of Computations and

[2] Versèle C., Deblecker O., Lobry J. A decision-making aid tool dedicated to the design of auxiliary railway

[3] Mohan N., Undeland T., Robbins W. Power Electronics: Converters, Applications and Design (3rd ed.).

Mathematics in Electrical and Electronic Engineering. 2012; 31(2): 583–603.

power supplies. European Journal of Electrical Engineering. 2011; 14(4): 421–450.

7. Conclusion and perspectives

technology to the other, which is an advantage.

hence, the design possibilities considerably extended.

Hoboken (NJ): Wiley; 2003.

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#### **7. Conclusion and perspectives**

In this chapter, power losses and mass of optimally designed Si- *vs*. SiC-based isolated DC-DC power converters have been compared in quantitative terms. Two application examples operating at very different output power levels have been studied: a 100 kW auxiliary railway SMPS and a multiple output 33.5 W SMPS intended for a space application. To that end, a CAD tool dedicated to the MO optimization of isolated DC-DC converters and based on genetic algorithms (NSGA-II in particular) has been employed. Fast analytical models have been used to account for the electrical and thermal phenomena occurring inside the power converters. An important effort has been made to enrich the database of the existing tool with WBG devices (mainly SiC) currently available from manufacturers. The results show clearly that the SiC technology leads to the design of lighter SMPS, with less power losses compared to Si technology only. Besides, the use of the MO optimization CAD tool permits to evaluate the gains in terms of power losses and mass from one technology to the other, which is an advantage.

In future work, the packaging aspects using*,* e.g., analytical formulas accounting for the component integration in the power converter [40] and electromagnetic compatibility consid‐ erations (constraints on the voltage and current gradients) should be included in the tool. Performing a sensitivity analysis could be another perspective. Such an analysis would be useful to give a designer with important information about the stability of one particular optimal solution against others. It should also be reminded that the CAD tool used in this study is a predesign tool based on simple and fast analytical models. For example, rapid transients on switches and parasitic capacitive effects in the magnetic components are not taken into account. Once the optimal solution is chosen from the tool and the designer know-how, finer models have to be employed around that particular design configuration in order to refine the solution, at the cost of higher computational burden (performing, e.g., transient circuit simulations or using numerical methods such as the FE technique). Lastly, it should be noted that, in this study, GaN-based power transistors were not selected for the space application because their voltage ratings in the database are still too low. Yet since in a near future the commercial offer concerning WBG components is expected to drastically increase, the tool database will be completed over time and, hence, the design possibilities considerably extended.

#### **Author details**

O. Deblecker\* , Z. De Grève and C. Versèle

\*Address all correspondence to: olivier.deblecker@umons.ac.be

Electrical Engineering Division, Faculty of Engineering, University of Mons (UMONS), Mons, Belgium

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**7. Conclusion and perspectives**

170 Advanced Silicon Carbide Devices and Processing

advantage.

extended.

**Author details**

, Z. De Grève and C. Versèle

\*Address all correspondence to: olivier.deblecker@umons.ac.be

O. Deblecker\*

Mons, Belgium

In this chapter, power losses and mass of optimally designed Si- *vs*. SiC-based isolated DC-DC power converters have been compared in quantitative terms. Two application examples operating at very different output power levels have been studied: a 100 kW auxiliary railway SMPS and a multiple output 33.5 W SMPS intended for a space application. To that end, a CAD tool dedicated to the MO optimization of isolated DC-DC converters and based on genetic algorithms (NSGA-II in particular) has been employed. Fast analytical models have been used to account for the electrical and thermal phenomena occurring inside the power converters. An important effort has been made to enrich the database of the existing tool with WBG devices (mainly SiC) currently available from manufacturers. The results show clearly that the SiC technology leads to the design of lighter SMPS, with less power losses compared to Si technology only. Besides, the use of the MO optimization CAD tool permits to evaluate the gains in terms of power losses and mass from one technology to the other, which is an

In future work, the packaging aspects using*,* e.g., analytical formulas accounting for the component integration in the power converter [40] and electromagnetic compatibility consid‐ erations (constraints on the voltage and current gradients) should be included in the tool. Performing a sensitivity analysis could be another perspective. Such an analysis would be useful to give a designer with important information about the stability of one particular optimal solution against others. It should also be reminded that the CAD tool used in this study is a predesign tool based on simple and fast analytical models. For example, rapid transients on switches and parasitic capacitive effects in the magnetic components are not taken into account. Once the optimal solution is chosen from the tool and the designer know-how, finer models have to be employed around that particular design configuration in order to refine the solution, at the cost of higher computational burden (performing, e.g., transient circuit simulations or using numerical methods such as the FE technique). Lastly, it should be noted that, in this study, GaN-based power transistors were not selected for the space application because their voltage ratings in the database are still too low. Yet since in a near future the commercial offer concerning WBG components is expected to drastically increase, the tool database will be completed over time and, hence, the design possibilities considerably

Electrical Engineering Division, Faculty of Engineering, University of Mons (UMONS),


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[13] Opzinci B., Tolbert L. M. Comparison of wide-bandgap seminconductors for power electronics applications. http://web.ornl.gov/~webworks/cppr/y2001/rpt/118817.pdf

[14] Mousa R. Caractérisation, modélisation et intégration du JFET de puissance en car‐ bure de silicium dans des convertisseurs haute température et haute tension. PhD

[15] Bijeev N.V., et al. Design and realization challenges of power supplies for TWT. Pro‐ ceedings of IEEE International Vacuum Electronics Conference, IVEC'2011, February

[16] Krämer M. C. J. C. M. Gallium nitride-based microwave high-power heterostructure field effect transistors—design, theory and characterization. PhD thesis. Technische

[17] Lebedev A. A., Chelnokov V. E. Wide-gap semiconductors for high-power electron‐

[18] Baliga B. J. Power semiconductor device figure of merit for high-frequency applica‐

[19] Schneider H., Sanchez J., Achard J. The diamond for power electronics devices. Pro‐ ceedings of the 11th Conference on Power Electronics and Applications, EPE'2005,

[20] Richmond J. Hard-switching silicon IGBTs ? Cut switching losses in half with silicon

[21] Versèle C. Contribution à l'optimisation multiobjectif de convertisseurs électroniques de puissance. Application aux convertisseurs continu-continu isolés. PhD thesis, Uni‐

[22] McLyman W. T. Transformer and inductor design handbook (3rd ed.). New York:

[23] Hurley W. G., Wölfle W. H., Breslin J. G. Optimized transformer design: inclusive of high frequency effects. IEEE Transactions on Power Electronics. 1998; 13(4): 651–659.

[24] Dowell P. L. Effects of eddy currents in transformer windings. Proceedings of IEEE.

[25] Gu W.-J., Liu R. A study of volume and weight vs. frequency for high-frequency transformers. Proceeding of the 24th IEEE Power Electronics Specialists Conference,

[26] Maniktala S. Switching power supply design and optimization. New York: Mac‐

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2011, Bangalore, India.

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#### **Chapter 6**

## **Novel Developments and Challenges for the SiC Power Devices**

Yintang Yang, Baoxing Duan, Song Yuan and Hujun Jia

Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/61123

#### **Abstract**

Silicon Carbide (SiC) is believed to be a revolutionary semiconductor material for power devices of the future; many SiC power devices have emerged as superior alternative power switch technology, especially in harsh environments with high temperature or high electric field. In this chapter, the challenges and recent develop‐ ments of SiC power devices are discussed. The first part is focused on SiC power diodes including SiC Schottky barrier diode (SBD), SiC PiN diodes (PiN,) SiC junction/ Schottky diodes (JBS), then SiC UMOSFETs, DMOSFETs and several MESFETs are introduced, and the third part is about SiC bipolar devices such as BJT and IGBT. Finally, the challenges during the development of SiC power devices, especially about its material growth and packaging are discussed.

**Keywords:** Silicon Carbide, Power Device, Diode, MOSFETs, MESFETs

#### **1. Introduction**

The first-generation and second-generation semiconductor materials are represented by silicon (Si) and gallium arsenide (GaAs), respectively. Wide band gap materials, such as silicon carbide (SiC) and gallium nitride (GaN), are known as the third generation semiconductor materials. SiC was discovered in 1824 by Berzelius during his diamond synthesis experiment. The first use of SiC was as an abrasive. This was followed by electronic applications. In the beginning of the 20th century, SiC was used as a detector in the first radios, and then became

© 2015 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

popular since 1907 when Henry Joseph Round produced the first LED by applying voltage to a SiC crystal and observing yellow, green, and orange emissions at the cathode. This attracted much of the electronic researchers' attention and about half a century ago, the potential of SiC in the semiconductor industry was recognized. Compared with Si, the most widely-used semiconductor material, SiC has many remarkable electronic properties including wide band gap, large critical electric field, high thermal conductivity, high electron saturation velocity, chemical inertness, and radiation hardness [1-3]. These excellent properties make SiC very well-suited for high-voltage, high-power, and high-temperature applications.

SiC power devices began to be developed during the 1970s. Based on the efforts of many researchers, great improvement had been achieved in its crystal quality and fabrication technology during the 1980s, then various kinds of SiC devices were developed, and their performance has rapidly improved.

Nowadays, the primary theoretical stage of SiC power devices had been completed. The commercial availability stage is developing rapidly; process technology, such as single-crystal substrate and device fabrication processes, has had great progress. Since 2001, Infineon Corporation started to supply SiC Schottky diodes. Now SiC diodes, MOSFETs, JFTs, BJTs, and other SiC three-terminal devices are available, CREE, Toshiba, STMicroelectronics and other companies have the ability to supply SiC power devices.

However, the main obstacles for the development of SiC-based devices are the quality and costs of SiC materials compared with its Si-based counterparts. With the recent progress in the process of SiC epitaxial materials, it is feasible to obtain high-quality 4H-SiC substrates and epilayers, and thus achieve excellent power performances for SiC power devices. For instance, 100-mm 4H-SiC substrates and epilayers are readily available for manufacturing power devices. Since more and more researchers and companies are paying attention to SiC materials, a massive drop in costs is forthcoming and affordable costs can be expected in the near future; which, in turn, will promote the development of SiC power devices.

#### **2. Silicon carbide diode**

Power diodes are the key components in modern power applications. The classical rectification function was upgraded by high demands of turn-on and turn-off speeds. In order to fabricate SiC power devices, ohmic contacts play a very important role in the signal transfer between the semiconductor and the external circuitry. A large number of ohmic contacts materials have been investigated during the last decades, both in terms of structural characterization and electrical performance. For ohmic contacts on the n-type SiC material, the most promising metal is nickel (Ni). It has been demonstrated that Ni films annealed in the range of 900-1000ºC can form good ohmic contacts on n-type SiCs with a specific contact resistance of 1×10-6 Ω⋅cm<sup>2</sup> [4]. For the p-type materials, due to the higher Schottky barrier, ohmic contact formation is even more difficult than n-type materials. Much research has been focused on aluminum/ titanium (Al/Ti) contacts, which give a specific contact resistance of about 10-5Ω⋅cm<sup>2</sup> [5].

#### **2.1. Schottky Barrier Diode (SBD)**

popular since 1907 when Henry Joseph Round produced the first LED by applying voltage to a SiC crystal and observing yellow, green, and orange emissions at the cathode. This attracted much of the electronic researchers' attention and about half a century ago, the potential of SiC in the semiconductor industry was recognized. Compared with Si, the most widely-used semiconductor material, SiC has many remarkable electronic properties including wide band gap, large critical electric field, high thermal conductivity, high electron saturation velocity, chemical inertness, and radiation hardness [1-3]. These excellent properties make SiC very

SiC power devices began to be developed during the 1970s. Based on the efforts of many researchers, great improvement had been achieved in its crystal quality and fabrication technology during the 1980s, then various kinds of SiC devices were developed, and their

Nowadays, the primary theoretical stage of SiC power devices had been completed. The commercial availability stage is developing rapidly; process technology, such as single-crystal substrate and device fabrication processes, has had great progress. Since 2001, Infineon Corporation started to supply SiC Schottky diodes. Now SiC diodes, MOSFETs, JFTs, BJTs, and other SiC three-terminal devices are available, CREE, Toshiba, STMicroelectronics and

However, the main obstacles for the development of SiC-based devices are the quality and costs of SiC materials compared with its Si-based counterparts. With the recent progress in the process of SiC epitaxial materials, it is feasible to obtain high-quality 4H-SiC substrates and epilayers, and thus achieve excellent power performances for SiC power devices. For instance, 100-mm 4H-SiC substrates and epilayers are readily available for manufacturing power devices. Since more and more researchers and companies are paying attention to SiC materials, a massive drop in costs is forthcoming and affordable costs can be expected in the near future;

Power diodes are the key components in modern power applications. The classical rectification function was upgraded by high demands of turn-on and turn-off speeds. In order to fabricate SiC power devices, ohmic contacts play a very important role in the signal transfer between the semiconductor and the external circuitry. A large number of ohmic contacts materials have been investigated during the last decades, both in terms of structural characterization and electrical performance. For ohmic contacts on the n-type SiC material, the most promising metal is nickel (Ni). It has been demonstrated that Ni films annealed in the range of 900-1000ºC can form good ohmic contacts on n-type SiCs with a specific contact resistance of 1×10-6 Ω⋅cm<sup>2</sup> [4]. For the p-type materials, due to the higher Schottky barrier, ohmic contact formation is even more difficult than n-type materials. Much research has been focused on aluminum/

titanium (Al/Ti) contacts, which give a specific contact resistance of about 10-5Ω⋅cm<sup>2</sup>

[5].

well-suited for high-voltage, high-power, and high-temperature applications.

other companies have the ability to supply SiC power devices.

which, in turn, will promote the development of SiC power devices.

performance has rapidly improved.

176 Advanced Silicon Carbide Devices and Processing

**2. Silicon carbide diode**

As a unipolar device, SBD has zero reverse recovery current. Figure 1 shows a general structure of SiC SBD; it is formed by an electrically nonlinear contact between a metal and a semicon‐ ductor bulk region. SBD fabricated by SiC offers a new degree in the design of power circuits, which has been commercially available since 2001. The most remarkable advantage of SiC SBD is the continuing increase in blocking voltage and conduction current ratings, which have been increased from the initial 300 V, 10 A and 600 V, 6 A [6] to the current 600 V, 20 A [7]. Fur‐ thermore, it is expected that SBD can be applied with a blocking voltage up to 2,000 V (as merged solutions also up to 3 kV) [8]. 4H-SiC with field plate terminal technology had been reported for the first time with a breakdown voltage of 1,750 V [9]. It is even foreseen that this type of diode may replace Si bipolar diodes in medium-power motor drive modules. Due to the absence of reverse recovery charge in SBD, it has an extremely fast turn-on performance, which is well suited for high-speed switching applications and for drastically reducing the dynamic losses for typical circuits. The high thermal conductivity of SiC is also a great advantage for SiC SBD in comparison with Si and GaAs diodes since it allows the SBD to operate at higher current density ratings with smaller size cooling systems. However, its reverse leakage current is large, especially at high temperatures, due to its lower built-in potential barrier.

**Figure 1.** Conventional structure of SiC SBD.

#### **2.2. Silicon carbide PiN diodes (PiN)**

Owing to the absence of conductivity modulation effects, the drift region resistance of SBD increases so fast with the rise of breakdown voltage, so the maximum breakdown voltage of SBD cannot compete with PiN diodes due to the unacceptably large ON-state resistance.

Figure 2 shows a general structure of a SiC PiN diode, it consists of a highly doped n-type substrate, a lightly doped n-type epitaxial layer with specified thickness, and a highly doped p-type region for the anode. The advantage of the SiC PiN diode is its low leakage current and low ON-state voltage drop in high current conduction due to minority carrier injection in the epitaxial drift region resulting in conductivity modulation. However, conductivity modulation causes significant reverse recovery current during switching, which is undesirable because it causes additional turn-on loss in the active switch. Since SiC PiN diodes are gaining more and more attention due to its higher breakdown voltage and smaller size and weight, its switching speed has been greatly improved. Recently, Johji Nishio et al. have fabricated the mesa SiC PiN diodes, which have a blocking voltage of 10.2 kV [10]. In 2007, Cree Company has reported a 8.7×8.7 mm2 SiC PiN diodes with the blocking voltage of 10 kV, as is shown in Figure 3 [11]. However, it has been reported that high power SiC PiN diodes exhibit an increase in the static forward voltage drop after exposing it to long-term operation during the test [12]. Various physical characterization techniques have shown that structural defects would be created in the epilayers during the operation. Encouragingly, Cree researchers have reported [13] that a process modification, which suppresses this degradation phenomenon, has been found but they have not released any details. Tsunenobu Kimoto et al. have reported 15 kV SiC PiN diodes with various junction terminal technologies [14]. In Ref. [15], 4H-SiC PiN had been applied in high temperature and high power circumstance with the breakdown voltage of 1,000 V.

**Figure 2.** Conventional structure of SiC PiN.

#### **2.3. Silicon carbide junction/schottky diodes (JBS)**

Schottky rectifiers are expected to dominate in power devices with a blocking voltage below 3 kV. However, the reverse leakage current of SBD is generally excessive, particularly at high

**Figure 3.** Blocking voltages characteristics of 10 kV SiC PiN diodes [11].

temperatures, due to lower Schottky barrier at high reverse voltage. The second-generation SiC diodes usually combine the attractive benefits of low ON-state voltage drop of a Schottky contact and the high blocking voltage of PiN diodes. These diodes have Schottky-like ON-state and switching behavior and PiN-like OFF-state characteristics at the same time. The basic JBS diode is fabricated by merging a Schottky diode and PiN diode structure [16]. Figure 4 shows a general structure of the SiC JBS; it consists of interleaved Schottky and p+ doped regions.The adjacent pn junction is used to suppress the rise of the electric field at the Schottky junction. When operating at voltages lower than the turn-on voltage of the pn junction, JBS exhibits faster switching speed than PiN diodes due to the absence of minority carrier injection. In recent time, Cree has manufactured a series of JBS with voltage ratings of 300, 600, and 1200 V and single-die current ratings from 1 to 10 Amps. In conclusion, the ON-state and switching characteristics of JBS are similar to Schottky diodes. The blocking characteristic is optimized due to the merged PiN diode structure compared with the SiC SBD.

#### **3. Silicon carbide unipolar devices**

#### **3.1. Silicon carbide MOSFETs**

Figure 2 shows a general structure of a SiC PiN diode, it consists of a highly doped n-type substrate, a lightly doped n-type epitaxial layer with specified thickness, and a highly doped p-type region for the anode. The advantage of the SiC PiN diode is its low leakage current and low ON-state voltage drop in high current conduction due to minority carrier injection in the epitaxial drift region resulting in conductivity modulation. However, conductivity modulation causes significant reverse recovery current during switching, which is undesirable because it causes additional turn-on loss in the active switch. Since SiC PiN diodes are gaining more and more attention due to its higher breakdown voltage and smaller size and weight, its switching speed has been greatly improved. Recently, Johji Nishio et al. have fabricated the mesa SiC PiN diodes, which have a blocking voltage of 10.2 kV [10]. In 2007, Cree Company has reported a 8.7×8.7 mm2 SiC PiN diodes with the blocking voltage of 10 kV, as is shown in Figure 3 [11]. However, it has been reported that high power SiC PiN diodes exhibit an increase in the static forward voltage drop after exposing it to long-term operation during the test [12]. Various physical characterization techniques have shown that structural defects would be created in the epilayers during the operation. Encouragingly, Cree researchers have reported [13] that a process modification, which suppresses this degradation phenomenon, has been found but they have not released any details. Tsunenobu Kimoto et al. have reported 15 kV SiC PiN diodes with various junction terminal technologies [14]. In Ref. [15], 4H-SiC PiN had been applied in high temperature and high power circumstance with the breakdown voltage of

1,000 V.

**Figure 2.** Conventional structure of SiC PiN.

178 Advanced Silicon Carbide Devices and Processing

**2.3. Silicon carbide junction/schottky diodes (JBS)**

Schottky rectifiers are expected to dominate in power devices with a blocking voltage below 3 kV. However, the reverse leakage current of SBD is generally excessive, particularly at high Metal oxide semiconductor field effect transistors (MOSFETs) have been of interest since Si devices have become the most successful devices. Due to the excellent material properties of SiC, SiC power MOSFETs can operate at higher switching frequency and operating tempera‐ tures compared with conventional Si MOSFETs. It has been expected to be the next-generation switching device to replace conventional Si power devices in many applications. The first SiC power MOSFET was demonstrated in 1994 in the form of a vertical trench gate structure (UMOSFET) [17]. The reported device had a breakdown voltage of 150 V and specific on-

**Figure 4.** Conventional structure of SiC JBS.

resistance of 3.3 mΩ⋅cm<sup>2</sup> . The breakdown voltage of the device was restricted by the high electric field in the gate oxide at the trench corner. To avoid the high electric field in a UMOS‐ FET, a SiC planar gate MOSFET with a p-base formed by a double implantation MOS process was fabricated (DMOSFET), this 6H-SiC DMOSFET has a breakdown voltage of 760 V based on a 10µm-thick and 6.5×1015 cm3 -doped n-type drift layer. [18]. Figure 5 is the schematic diagram of the structure of the typical UMOSFET (UMOS) and DMOSFET (DMOS).

**Figure 5.** Schematic diagram of SiC (a) UMOS and (b) DMOS.

Later on, a 10 kV, 123 mΩ⋅cm<sup>2</sup> 4H-SiC power DMOSFET was reported [19]. The effective channel carrier mobility is only 22 cm2 /V⋅s. However, the very low inversion channel electron mobility in 4H-SiC has prevented the fabrication of the low-resistance MOSFETs for many years. Besides, electron mobility in the channel has been proved to be low when measured on p-implanted regions due to the implantation damage. SiC has a higher density of dangling Si and C bonds at the SiC/SiO2 interface due to its higher surface density of atoms per unit area compared with Si. Therefore, various intrinsic defects not related to dopants or impurities can be observed at the SiC/SiO2 interface, these defects appeared in the energy gap of SiC as traps for electrons leading to the low channel mobility in 4H-SiC. This made the reduction of interface state density at the SiO2/SiC boundary play a critical role in increasing channel mobility and improving high temperature performance, as well as the reliability of power SiC MOSFETs or IGBTs. In the past few decades, a lot of efforts have been devoted to developing SiC power devices, and great progress has been achieved. With the advanced process tech‐ nology, there are two approaches that are effective in improving the quality of the metal-oxidesemiconductor interface. One is using nitrogen during post-oxidation annealing and the other is selecting specific crystal faces for the formation of the MOS channel. Now, the SiC MOSFETs with peak mobility of 140 cm2 /V⋅s and 216 cm2 /V⋅s in the channel have been fabricated. However, interface state densities are still two orders of magnitude higher than those devices achieved by using Si MOS technology, which has been adopted by Cree to fabricate highcurrent (2 A), large-area (2 mm2 ) lateral MOSFETs. The University of Tokyo has reported a lateral DMOSFET (LDMOSFET) with its blocking voltage and specific on-resistance of 1.5 kV and 54 mΩ⋅cm<sup>2</sup> , respectively [20]. A breakdown voltage of 3,520 V was achieved for the 4H-SiC lateral MOSFETs with specific on-resistance of 600 mΩ⋅cm<sup>2</sup> [21]. This is the best result for SiC LDMOSFET.

Since 2012, Takuji Hosoi reported an AlON high-k gate dielectric technology implemented into both planar and trench SiC MOSFETs. The high-k gate dielectric technology can efficiently reduce the gate leakage and its higher dielectric breakdown field would be beneficial in improving the devices' reliability and channel carrier mobility. In 2013, a 1,600 V/150 A 4H-SiC DMOSFETs are presented by Lin Cheng. The SiC DMOSFET with smaller chip size shows superior static and dynamic performance over the commercially available 1,200 V/200 A trench gate Si IGBT from 25°C up to 200°C. In 2014, Ryota Nakamura presented a 1,200 V 4H-SiC MOSFETs with double-trench structure SiC MOSFETs. The trench structure can reduce the on-resistance by about 50% from 25℃ to 150℃.

#### **3.2. Silicon carbide MESFETs**

resistance of 3.3 mΩ⋅cm<sup>2</sup>

on a 10µm-thick and 6.5×1015 cm3

**Figure 4.** Conventional structure of SiC JBS.

180 Advanced Silicon Carbide Devices and Processing

**Figure 5.** Schematic diagram of SiC (a) UMOS and (b) DMOS.

Later on, a 10 kV, 123 mΩ⋅cm<sup>2</sup>

channel carrier mobility is only 22 cm2

. The breakdown voltage of the device was restricted by the high


4H-SiC power DMOSFET was reported [19]. The effective

/V⋅s. However, the very low inversion channel electron

electric field in the gate oxide at the trench corner. To avoid the high electric field in a UMOS‐ FET, a SiC planar gate MOSFET with a p-base formed by a double implantation MOS process was fabricated (DMOSFET), this 6H-SiC DMOSFET has a breakdown voltage of 760 V based

(a) (b)

mobility in 4H-SiC has prevented the fabrication of the low-resistance MOSFETs for many

diagram of the structure of the typical UMOSFET (UMOS) and DMOSFET (DMOS).

For the SiC power metal semiconductor field effect transistors (MESFETs), the breakdown voltage is a very important parameter that allows the power devices to achieve a specific power density and power conversion. Figure 6 is the schematic diagram of the conventional SiC MESFET. Prior research has proposed many techniques to improve the breakdown voltage [22, 23]. In order to optimize the surface electric field and improve the breakdown voltage, new technologies had been proposed, which includes the REBULF (reduced bulk field) [24] and complete 3D Reduced SURface Field (RESURF) [25]. The high breakdown had been obtained on the ultra-thin epitaxial layer with the REBULF technology. It can be ensured that these new technologies can be transplanted directly onto SiC power MESFETs. Thus, several new SiC power MESFETs had been designed to optimize the characteristic of the breakdown voltage, specific on-resistance, frequency, and transconductance.

**Figure 6.** Schematic diagram of the conventional SiC MESFET structure.

Figure 7 is the schematic diagram of the structure of the Buffer-Gate SiC MESFETs structure [26]. Compared with the conventional 4H-SiC MESFETs (Figure 6), a low-doped, gate-buffer layer is introduced between the gate and channel layer. In Buffer-Gate 4H-SiC MESFETs, the gate length is 0.7 µm. Meanwhile, the thickness and doping concentration for the channel layer are 0.26 µm and 1.7×1017 cm-3; between the gate and channel is the gate-buffer layer that has a thickness of 0.15 µm and doping concentration of 1×1015 cm-3.

**Figure 7.** Schematic diagram of the structure of the Buffer-Gate SiC MESFET in saturation mode operation.

The channel current in the channel for the structure above can be expressed by (1):

$$I\_c = q\mathcal{W}n(\mathbf{x})\,\mu(\mathbf{E})\mathbf{E}(\mathbf{x})\Big[\,a - h(\mathbf{x})\Big] \tag{1}$$

Where *q* is the magnitude of the electronic charge, *W* is the channel width, *a* is the channel layer thickness, *E(x)* is the lateral electric field strength, and *n(x)* is the electron concentration of the channel. *h(x)* is the thickness of the depletion layer in the channel layer and obtained by solving the 1-D Poisson's equation (2):

$$h(\mathbf{x}) = a\_0 \left( 1 - \frac{N\_0}{N\_D} + \frac{V(\mathbf{x}) + V\_G + V\_{bl}}{\frac{qN\_D}{2\varepsilon}a\_0^2} \right) - a\_0 \tag{2}$$

Where *N0* is the uniform doping concentration of the gate-buffer layer, which is smaller than *ND*, *a0* is the gate-buffer layer thickness, and ε is the dielectric constant. *V(x)* is the potential at the point x away from the source, *VG* is the gate bias and *Vbi* the build-in voltage. To solve the 2-D Poisson's equation:

**Figure 6.** Schematic diagram of the conventional SiC MESFET structure.

182 Advanced Silicon Carbide Devices and Processing

thickness of 0.15 µm and doping concentration of 1×1015 cm-3.

**h0**

**x**

Figure 7 is the schematic diagram of the structure of the Buffer-Gate SiC MESFETs structure [26]. Compared with the conventional 4H-SiC MESFETs (Figure 6), a low-doped, gate-buffer layer is introduced between the gate and channel layer. In Buffer-Gate 4H-SiC MESFETs, the gate length is 0.7 µm. Meanwhile, the thickness and doping concentration for the channel layer are 0.26 µm and 1.7×1017 cm-3; between the gate and channel is the gate-buffer layer that has a

**a0**

**h x( ) h1**

**yN+ N+**

*I II III*

**N0**

**L2 L3**

**SG D**

**L1**

**Figure 7.** Schematic diagram of the structure of the Buffer-Gate SiC MESFET in saturation mode operation.

$$
\mu\_1 \left( \mathbf{V}\_{\mathbf{C}'} \mathbf{V}\_{\mathbf{D}} \right) = \frac{h\_1}{a} = \sqrt{1 - \frac{N\_0}{N\_D}} \left| \frac{a\_0^2}{a^2} + \frac{V \left( \mathbf{L}\_1 \right) + V\_{\mathbf{C}} + V\_{\mathbf{b}'}}{V\_p} - \frac{a\_0}{a} \right| \tag{3}
$$

$$\begin{split} &V\left(\mathbf{L} + \mathbf{L}\_{\circ}\right) \cdot \mathbf{V}\left(\mathbf{L}\_{\circ}\right) = \left(\frac{2\left(\mathbf{a}\mathbf{u}\_{\circ} + \mathbf{a}\_{\circ}\right)}{\pi} + \frac{\mathbf{L}\_{\circ}}{3}\right) \mathbf{E}\_{\circ} \sinh\left(\frac{\pi \mathbf{L}\_{\circ}}{2\left(\mathbf{a}\mathbf{u}\_{\circ} + \mathbf{a}\_{\circ}\right)}\right) \exp\left(\frac{-\pi \mathbf{L}\_{\circ}}{2\left(\mathbf{a}\mathbf{u}\_{\circ} + \mathbf{a}\_{\circ}\right)}\right) + \\ &+\frac{\mathbf{E}\_{\circ}}{3} \Big(2\exp(\frac{\pi \mathbf{L}\_{\circ}}{2\left(\mathbf{a}\mathbf{u}\_{\circ} + \mathbf{a}\_{\circ}\right)}\Big) + 1\end{split} \tag{4}$$

$$\begin{split} & \text{Li}^{2} \| \frac{qN\_{\text{D}}a\mathbf{u}\_{\text{L}}}{\varepsilon} - E \exp\Big(\frac{\pi \mathcal{L}\_{\text{L}}}{2\left(\mathbf{a}\mathbf{u} + \mathbf{a}\_{\text{e}}\right)}\Big) + \frac{E\_{\text{s}}}{\eta} \sinh\Big(\frac{\pi \mathcal{L}\_{\text{L}}}{2\left(\mathbf{a}\mathbf{u} + \mathbf{a}\_{\text{e}}\right)}\Big) \Big(1 + \tan\Big(\frac{\pi a\_{\text{e}}}{2\left(\mathbf{a}\mathbf{u} + \mathbf{a}\_{\text{e}}\right)}\Big)\Big) \\ &= \left(a\mathbf{u}\_{\text{l}}\right)^{2} E\_{\text{l}} \| \exp\Big(\frac{\pi \mathcal{L}\_{\text{L}}}{2\left(\mathbf{a}\mathbf{u} + \mathbf{a}\_{\text{e}}\right)}\Big) - 1 - \sinh\Big(\frac{\pi \mathcal{L}\_{\text{L}}}{2\left(\mathbf{a}\mathbf{u} + \mathbf{a}\_{\text{e}}\right)}\Big) \exp\Big(\frac{-\pi \mathcal{L}\_{\text{s}}}{2\left(\mathbf{a}\mathbf{u} + \mathbf{a}\_{\text{e}}\right)}\Big) \end{split} \tag{5}$$

$$\eta = \tan\left(\frac{\pi a\_0}{2\left(\mathbf{au} \cdot \mathbf{a}\_0\right)}\right) \cos\left(\frac{\pi a \,\mathbf{u} \cdot \mathbf{u}}{2\left(\mathbf{au} \cdot \mathbf{a}\_0\right)}\right) + \sin\left(\frac{\pi a \,\mathbf{u} \cdot \mathbf{u}}{2\left(\mathbf{au} \cdot \mathbf{a}\_0\right)}\right) \tag{6}$$

$$\mathbf{V}\left(\mathbf{L} + \mathbf{L}\_{\text{3}}\right) = \mathbf{V}\_{\text{D}} \cdot \mathbf{I}\_{\text{C}} \mathbf{R}\_{\text{D}} \tag{7}$$

From equations (1-7), the drain current can be achieved when the structure parameters (*L, W, a, a0, ND, N0*) and bias voltage (*VG,VD*) are given.

ISE TCAD is used in the simulation. To obtain accurate results, several basic physical models such as band gap and electron affinity models, generation-recombination models, quantization models, and incomplete ionization models are utilized, which precisely describe the material properties. Figure 8 (a) shows the effect of the gate-buffer layer on the current in the channel. It reveals that the drain current increased as the gate-buffer layer gets thicker at first, but if the thickness of the gate-buffer layer gets thicker than 0.3 µm, this correlation doesn't exist, the drain current is saturated. And the heavier the doping concentration is the bigger the drainsaturated current is. This is because the decrease of the depletion layer thickness in the channel decreased with the increase of the doping concentration and thickness of the gate-buffer layer dcrease so the channel width would increase, which makes the drain current get bigger. Figure 8 (b) shows the breakdown characteristics for the two structures. It can be seen that the breakdown voltage (*V*b) of the Buffer-Gate SiC MESFETs is significantly increased, compared with that of the conventional structure (a0=0µm, shown in Figure 5). This is because the breakdown happens at the gate corner near to the drain side due to the electric field crowding here for both structures. Different from the conventional 4H-SiC MESFETs, Buffer-Gate SiC MESFETs have an inserted lower-doped gate-buffer layer that makes the surface electric field more uniform, so the electric field peak at the gate corner is also lowered. Figure 8 (c) shows the electric field distribution. The mechanism for the suppression of the electric field at the gate corner in the Buffer-Gate SiC MESFETs is similar to the lightly-doped drain (LDD) in the MOSFETs [27].

The schematic diagram of the GDSE (Gate-Drain Surface Epitaxial layer) MESFETs is shown in Figure 9 [28]. Compared with the conventional 4H-SiC MESFETs, a low-doped p-type surface epitaxial layer is introduced between the gate and drain, which has a doping concen‐ tration two orders lower than that of the channel layer. As the layer has been introduced, firstly, the electric field peak at the gate corner will be reduced by the build-in potential in the p-n junction between the p-type epitaxial layer and n-type channel layer or n+ cap layer, which makes the electric field distribution more uniform. Secondly, due to the much lower doping concentration of the p-type epitaxial layer, most of the depletion region in the p-n junction lies in the p-type region. Therefore, the gate-drain p-type epitaxial layer has little bad effect on the current density.

As mentioned above, the two-dimensional simulator ISE TCAD is used, to precisely describe the surface trap effect along the SiC/SiO2 interfaces. The density and capture cross section of the near interface trap(NIT) are set to 5.3×1012 cm-2 and 1×10-19 cm2 , while the density and capture cross section of the deep interface trap(DIT) are set to 1.2×1013 cm-2 and 1.4×10-15 cm2 [29, 30]. Schottky barrier tunneling (SBT) and initial trap populating (ITP) are taken into account for transient investigation. Similar studies concerning these mechanisms can be found elsewhere and the accuracy of relevant models has been verified [31].

Novel Developments and Challenges for the SiC Power Devices http://dx.doi.org/10.5772/61123 185

V L+L =V -I R ( ) 3 DCD (7)

cap layer, which

, while the density and

From equations (1-7), the drain current can be achieved when the structure parameters (*L, W,*

ISE TCAD is used in the simulation. To obtain accurate results, several basic physical models such as band gap and electron affinity models, generation-recombination models, quantization models, and incomplete ionization models are utilized, which precisely describe the material properties. Figure 8 (a) shows the effect of the gate-buffer layer on the current in the channel. It reveals that the drain current increased as the gate-buffer layer gets thicker at first, but if the thickness of the gate-buffer layer gets thicker than 0.3 µm, this correlation doesn't exist, the drain current is saturated. And the heavier the doping concentration is the bigger the drainsaturated current is. This is because the decrease of the depletion layer thickness in the channel decreased with the increase of the doping concentration and thickness of the gate-buffer layer dcrease so the channel width would increase, which makes the drain current get bigger. Figure 8 (b) shows the breakdown characteristics for the two structures. It can be seen that the breakdown voltage (*V*b) of the Buffer-Gate SiC MESFETs is significantly increased, compared with that of the conventional structure (a0=0µm, shown in Figure 5). This is because the breakdown happens at the gate corner near to the drain side due to the electric field crowding here for both structures. Different from the conventional 4H-SiC MESFETs, Buffer-Gate SiC MESFETs have an inserted lower-doped gate-buffer layer that makes the surface electric field more uniform, so the electric field peak at the gate corner is also lowered. Figure 8 (c) shows the electric field distribution. The mechanism for the suppression of the electric field at the gate corner in the Buffer-Gate SiC MESFETs is similar to the lightly-doped drain (LDD) in the

The schematic diagram of the GDSE (Gate-Drain Surface Epitaxial layer) MESFETs is shown in Figure 9 [28]. Compared with the conventional 4H-SiC MESFETs, a low-doped p-type surface epitaxial layer is introduced between the gate and drain, which has a doping concen‐ tration two orders lower than that of the channel layer. As the layer has been introduced, firstly, the electric field peak at the gate corner will be reduced by the build-in potential in the p-n

makes the electric field distribution more uniform. Secondly, due to the much lower doping concentration of the p-type epitaxial layer, most of the depletion region in the p-n junction lies in the p-type region. Therefore, the gate-drain p-type epitaxial layer has little bad effect on the

As mentioned above, the two-dimensional simulator ISE TCAD is used, to precisely describe the surface trap effect along the SiC/SiO2 interfaces. The density and capture cross section of

capture cross section of the deep interface trap(DIT) are set to 1.2×1013 cm-2 and 1.4×10-15 cm2 [29, 30]. Schottky barrier tunneling (SBT) and initial trap populating (ITP) are taken into account for transient investigation. Similar studies concerning these mechanisms can be found

junction between the p-type epitaxial layer and n-type channel layer or n+

the near interface trap(NIT) are set to 5.3×1012 cm-2 and 1×10-19 cm2

elsewhere and the accuracy of relevant models has been verified [31].

*a, a0, ND, N0*) and bias voltage (*VG,VD*) are given.

184 Advanced Silicon Carbide Devices and Processing

MOSFETs [27].

current density.

**Figure 8.** (a) Dependence of the drain current on the gate-buffer layer for N0=1×1015 cm-3 N0=5×1015 cm-3 and N0=1×1016 cm-3.VGS=0 V, VDS=5 V. (b) The simulated breakdown characteristics for *a*0=0 µm (open) and *a*0=0.15 µm (filled). (c) The distribution of the surface electric field for *a*0=0 µm (dash) and *a*0=0.15 µm (solid).

**Figure 9.** The schematic diagram of MESFETs with gate-drain surface epi-layer [28].

The introduced p-type spacer layer has a thickness of 0.1 µm and a doping concentration of 3×1015 cm-3, the thickness and doping concentration of the n-type channel used as the conduc‐ tive channel for device operation is 0.22 µm and 3×1017 cm-3. And the buffer layer is 0.6 µm thick with a doping concentration of 5×1015 cm-3. The breakdown characteristics and surface electric field distribution are shown in Figure 10. It had been shown that the breakdown voltage of the GDSE structure is the largest one for the three structures in Figure 10 (a) owing to the inserted lower-doped p-type epitaxial layer the electric field peak at the gate corner is signif‐ icantly lowered (i.e., the surface electric field is more uniform), so the breakdown voltage for the GDSE MESFETs increased as is shown in Figure 10 (b).

**Figure 10.** Comparison of the (a) breakdown voltage and the (b) surface electric field for the conventional, field-plated, and the GDSE structure.

The schematic diagram of the L-gate 4H-SiC MESFETs with partial p-type spacer is shown in Figure 11. Compared with the conventional 4H-SiC MESFETs, the L-gate and partial p-type spacer are introduced. The L-gate structure has lower and upper gates that effectively controls a thinner and a thicker part of the channel, respectively. It can decrease the gate capacitance and reduce the depletion layer under the gate, which makes the conduct channel under the Lgate wider, so the saturation drain current increases effectively. Since the p-n junction formed between the p-spacer and the n-channel also leads a distinct reduction of the gate-drain capacitance, the proposed structure has a significant improvement of the DC and RF perform‐ ances compared with conventional SiC MESFETs.

**Figure 11.** The schematic diagram of the L-gate 4H-SiC MESFETs with partial p-type spacer.

The introduced p-type spacer layer has a thickness of 0.1 µm and a doping concentration of 3×1015 cm-3, the thickness and doping concentration of the n-type channel used as the conduc‐ tive channel for device operation is 0.22 µm and 3×1017 cm-3. And the buffer layer is 0.6 µm thick with a doping concentration of 5×1015 cm-3. The breakdown characteristics and surface electric field distribution are shown in Figure 10. It had been shown that the breakdown voltage of the GDSE structure is the largest one for the three structures in Figure 10 (a) owing to the inserted lower-doped p-type epitaxial layer the electric field peak at the gate corner is signif‐ icantly lowered (i.e., the surface electric field is more uniform), so the breakdown voltage for

(a)

(b)

**Figure 10.** Comparison of the (a) breakdown voltage and the (b) surface electric field for the conventional, field-plated,

and the GDSE structure.

the GDSE MESFETs increased as is shown in Figure 10 (b).

186 Advanced Silicon Carbide Devices and Processing

Figure 12 (a) shows the simulated output characteristics of C-MESFET, L-gate-MESFET, and LP-MESFET under the gate bias (VGS) vary from 0 V to -12 V with a step of 4 V. It can be seen that due to the thicker gate-drain drift region and wider channel region outside the L-gate, the LP-MESFET has a higher saturation drain current (IDsat) than that of conventional ones at VGS=0 V. It also should be noted that the p-n junction formed between the p-spacer and nchannel that leads to a reduction in effective thickness of the gate-drain drift region slightly decreases the saturated drain current of the LP-MESFET comparing with that of the L-gate-MESFET.

Figure 12 (b) shows the three-terminal breakdown characteristics for 4H-SiC C-MESFET, Lgate-MESFET, and LP-MESFET simulated with an applied VGS=VT. The drain current (ID) and the gate leakage current (IG) with respect to VDS are displayed for the three MESFETs. It can be seen that the drain current will increase with the gate leakage current increasing, this illustrates that the breakdown of 4H-SiC MESFETs at the applied VGS occurs at the gate-drain drift region, which is because the electric field for all the structures crowding at the gate corner near the drain. Therefore, owing to the extension of gate metal on the surface acted as a field plate resulting in a gradual field distribution, the high electric field peak at the bottom edge of gate toward the drain side is suppressed, the MESFETs with a L-Gate has an improvement of the breakdown voltages shown in Figure 11 (a) [32]. It can be seen that the breakdown voltages are 250 V for the C-MESFET, 360 V for the L-gate-MESFET, and 340 V for the proposed structure LP-MESFET, which is 36% higher than that of C-MESFET. The maximum output power density Pmax for the 4H-SiCC-MESFET, L-gate-MESFET, and LP-MESFET at VGS=4 V and VDS=40 V is 4.2 W/mm, 9.1 W/mm, and 8.2W/mm, respectively. Output power density of the LP-MESFET structure is about 95% larger than that of the C-MESFET structure. [33].

Figure 12 (c) shows the simulated CGD versus frequency at VDS=40 V and VGS=-5 V. It can be seen that the CGD of the LP-MESFET structure is smaller than that of the C-MESFET structure and the L-gate-MESFET structure. As is known to all, the CGD consists of depletion layer capacitance and drift region diffuse capacitance. From the device structure, we can see that the partial p-type spacer has a distance from the gate edge towards the drain, so the decrease of CGD is not derived from the reducing depletion layer extension to drain. That means the reducing CGD is mainly attributed to the decreased gate-drain drift region diffused capacitance brought by the partial p-type spacer.

**Figure 12.** (a) The simulated ID-VDS characteristics of different structures. (b) Simulated three-terminal breakdown char‐ acteristics for 4H-SiC C-MESFET, L-gate-MESFET. and LP-MESFET. (c) Dependences of the simulated drain-gate ca‐ pacitance (CGD) on the frequency of the three structures under DC bias conditions of VDS=40 V and VGS=-5 V.

#### **4. Silicon carbide bipolar devices**

There has been great progress in SiC bipolar power devices such as BJT and IGBT. SiC BJT exhibits 20~50 times lower than Si BJT in switching losses and ON-state voltage. In Si BJT, the second breakdown is widespread, which significantly affects the devices' performance. However, it is negligible in SiC BJT since the critical current density is 100 times lower than that of Si BJT. Moreover, the base region and collector region are allowed to be fabricated very thin so as to improve the current gain and switching speed due to the large critical electric field of SiC material. The Cree company has reported another 4H-SiC BJT with its current gain of 44, blocking voltage of 3.2 kV, and specific on-resistance of 8.1 mΩ⋅cm<sup>2</sup> [34]. The driving circuit of SiC BJT is complex compared with that of a MOSFET. However, its manufacturing process is simpler than that of a JFET. In the area of SiC IGBT, Q. Zhang has reported a UMOSFET 4H-SiC IGBT with a blocking voltage and specific on-resistance of 10 kV and 175 mΩ⋅cm<sup>2</sup> at 25°C [35]. In 2007, Purdue University fabricated a p-IGBT with a p-region width of 175 µm, as high as 20 kV in blocking voltage [36]. This IGBT can provide approximately twice the ON-state current as MOSFETs at 177°C, which is superior to the IGBT based on the Si. In the same year, Cree reported a SiC n-IGBT with a blocking voltage of 12 kV, and its switching characteristic is shown in Figure 13 in comparison with that of Si-IGBT [37].

**Figure 13.** 12kV 4H-SiC N-IGBT ON-state characteristics [35].

4.2 W/mm, 9.1 W/mm, and 8.2W/mm, respectively. Output power density of the LP-MESFET

Figure 12 (c) shows the simulated CGD versus frequency at VDS=40 V and VGS=-5 V. It can be seen that the CGD of the LP-MESFET structure is smaller than that of the C-MESFET structure and the L-gate-MESFET structure. As is known to all, the CGD consists of depletion layer capacitance and drift region diffuse capacitance. From the device structure, we can see that the partial p-type spacer has a distance from the gate edge towards the drain, so the decrease of CGD is not derived from the reducing depletion layer extension to drain. That means the reducing CGD is mainly attributed to the decreased gate-drain drift region diffused capacitance

(a) (b)

(c)

**Figure 12.** (a) The simulated ID-VDS characteristics of different structures. (b) Simulated three-terminal breakdown char‐ acteristics for 4H-SiC C-MESFET, L-gate-MESFET. and LP-MESFET. (c) Dependences of the simulated drain-gate ca‐

There has been great progress in SiC bipolar power devices such as BJT and IGBT. SiC BJT exhibits 20~50 times lower than Si BJT in switching losses and ON-state voltage. In Si BJT, the

pacitance (CGD) on the frequency of the three structures under DC bias conditions of VDS=40 V and VGS=-5 V.

structure is about 95% larger than that of the C-MESFET structure. [33].

brought by the partial p-type spacer.

188 Advanced Silicon Carbide Devices and Processing

**4. Silicon carbide bipolar devices**

Since key technologies, such as low mobility in the inverse channel layer and reliability of the gate oxide layer with the high electric field, have not been overcome, SiC MESFETs (or JFETs) and BJTs may be the only widespread SiC devices commercially. At present, process technologies, such as injection, oxidation, and etching processes, should be improved in order to optimize device structures. In the long run, researchers should focus their attentions on the process theory and technology of gate oxidation for fabricating superior MOSFETs and IGBTs.

#### **5. Forthcoming challenges for silicon carbide power devices**

#### **5.1. Defects for silicon carbide materials**

Reducing and eliminating the defects density in the SiC wafer is a knotty task, which is the main reason that is limiting the wafer dimension. There has been significant development in reducing and eliminating defects density. Cree has been supplying 4-inch SiC wafers with zero micro-pipe since 2007. Now, the research of defects is focusing on the effects of dislocation, such as screw dislocation, basal plane dislocations, edge dislocation, and other defects on the characteristics of the devices.

#### **5.2. Challenges for silicon carbide power devices**

This technical review is one of the series of reports on semiconductor power devices. Three IETE articles have been reported on the application of electric field modulation to silicon and silicon-on-insulator power devices [36,37]. There are two bottleneck techniques in SiC MOSFETs that need to be broken down, the low electron mobility in the inversion channel layer and gate oxide reliability with high temperature or high electric field. The recent reported electron mobility is 30-250 cm2 /V⋅s, which does not manifest the advantage of the SiC MOSFET. Therefore, special gate oxidation technologies are needed to eliminate the SiC/SiO2 interface defects and increase the mobility of the electron in the inversion layer, such as the postoxidation annealing in the H2 environment, and gate oxidation or annealing in NO or N2O environment. It is unknown what causes the current gain instability; one possible reason may be the stacking fault in the epitaxial base region. The new SiC power devices can be designed by applying the electric field modulation effect. Electric field modulation had been proposed by the authors for the first time [38-40]. Several new structures for the silicon power devices and AlGaN/GaN HEMTs had been reported, which can be used to design new SiC power devices [41-47].

The packaging of the SiC power device is also a pressing problem. The packaging reliability for SiC devices will be a key factor affecting the performance of the circuits once the material and process challenges are overcome. Packaging reliability is also important when the devices operate at high temperatures (≥ 200°C) or the coolant temperature require the operation temperature should above today's limits of ~150°C. For example, the automotive motor drives using engine coolant, oil and gas drilling and extraction, avionics power supplies, space power supplies, and military applications. It's important to increase the power handling capability to reduce the expensive chip area and cooling cost. Thus, new package materials for high temperature application are necessary.

As the great reduction of switching energy is attained by very fast switching and when SiC power devices are applied in the fast switching area, the internal electromagnetic parasitic issues between the device and package should be taken into account. The advanced power module architectures are very important.

During the application of SiC power devices, people should think about the high electric field issue. Due to the high device internal electric field, the field stress in the passivation layer and at the chip surfaces is so high that the average electric field for the chip/gel interface at the terminal edge is around 3 times higher than the SiC diode. With such high surface field strengths, any contamination in the form of particles or mobile ions may lead to possible electrochemical driven corrosion processes; any material defect in the passivation layers and any delamination/insufficient adhesion of encapsulation may become extremely critical. This makes the advanced insulation technology of great importance.

#### **6. Conclusion**

**5. Forthcoming challenges for silicon carbide power devices**

Reducing and eliminating the defects density in the SiC wafer is a knotty task, which is the main reason that is limiting the wafer dimension. There has been significant development in reducing and eliminating defects density. Cree has been supplying 4-inch SiC wafers with zero micro-pipe since 2007. Now, the research of defects is focusing on the effects of dislocation, such as screw dislocation, basal plane dislocations, edge dislocation, and other defects on the

This technical review is one of the series of reports on semiconductor power devices. Three IETE articles have been reported on the application of electric field modulation to silicon and silicon-on-insulator power devices [36,37]. There are two bottleneck techniques in SiC MOSFETs that need to be broken down, the low electron mobility in the inversion channel layer and gate oxide reliability with high temperature or high electric field. The recent reported

Therefore, special gate oxidation technologies are needed to eliminate the SiC/SiO2 interface defects and increase the mobility of the electron in the inversion layer, such as the postoxidation annealing in the H2 environment, and gate oxidation or annealing in NO or N2O environment. It is unknown what causes the current gain instability; one possible reason may be the stacking fault in the epitaxial base region. The new SiC power devices can be designed by applying the electric field modulation effect. Electric field modulation had been proposed by the authors for the first time [38-40]. Several new structures for the silicon power devices and AlGaN/GaN HEMTs had been reported, which can be used to design new SiC power

The packaging of the SiC power device is also a pressing problem. The packaging reliability for SiC devices will be a key factor affecting the performance of the circuits once the material and process challenges are overcome. Packaging reliability is also important when the devices operate at high temperatures (≥ 200°C) or the coolant temperature require the operation temperature should above today's limits of ~150°C. For example, the automotive motor drives using engine coolant, oil and gas drilling and extraction, avionics power supplies, space power supplies, and military applications. It's important to increase the power handling capability to reduce the expensive chip area and cooling cost. Thus, new package materials for high

As the great reduction of switching energy is attained by very fast switching and when SiC power devices are applied in the fast switching area, the internal electromagnetic parasitic issues between the device and package should be taken into account. The advanced power

During the application of SiC power devices, people should think about the high electric field issue. Due to the high device internal electric field, the field stress in the passivation layer and

/V⋅s, which does not manifest the advantage of the SiC MOSFET.

**5.1. Defects for silicon carbide materials**

190 Advanced Silicon Carbide Devices and Processing

**5.2. Challenges for silicon carbide power devices**

characteristics of the devices.

electron mobility is 30-250 cm2

temperature application are necessary.

module architectures are very important.

devices [41-47].

In conclusion, SBD has an extremely fast turn-on performance due to the absence of reverse recovery charge, which is well suited for high-speed switching applications, drastically reducing the dynamic losses of typical circuits, and yet minimizing the size of cooling systems. The SiC PiN diodes have the characteristics of low gate leakage current and high breakdown voltage, and thus can be used as switches in high voltage and low frequency circumstances. The JBS shows the ON-state and switching characteristics similar to Schottky diodes and blocking characteristics similar to PiN diodes. MESFETs have superior RF performance compared to JFETs due to the reduced gate capacitance and higher transconductance. SiC BJT exhibits much lower switching losses and ON-state voltage than Si BJT. Unless the electron mobility in the inverse channel layer and reliability of the gate oxidation layer are broken through, SiC MOSFETs will not be commercially widespread.

#### **Author details**

Yintang Yang, Baoxing Duan\* , Song Yuan and Hujun Jia

\*Address all correspondence to: bxduan@163.com

Key Laboratory of the Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices, School of Microelectronics, Xidian University, Xi'an, China

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194 Advanced Silicon Carbide Devices and Processing


**Section 3**

**Novel SiC Devices**

## **High-responsivity SiC Ultraviolet Photodetectors with SiO2 and Al2O3 Films**

Feng Zhang

Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/61019

#### **Abstract**

Silicon carbide (SiC) has shown considerable potential for ultraviolet (UV) photode‐ tectors due to its properties such as wide band gap (3.26 eV for 4H-SiC), high break down electric field and high thermal stability. 4H-SiC-based UV photodetectors such as Schottky, metal-semiconductor-metal (MSM), metal-insulator-semiconductor (MIS) and avalanche have been presenting excellent performance for UV detection application in flame detection, ozone-hole sensing, short-range communication, etc. Generally, the most widely used antireflection coating and passivation layer for 4H-SiC-based photodetectors are native SiO2 grown by heating 4H-SiC in O2 in order to improve the absorption and passivation of photodetectors. Nevertheless, the thermally grown SiO2 single layer suffers from high reflection, large absorption and inaccurate thickness. Therefore, in this chapter, UV antireflection coatings were designed, fabricated and applied in order to reduce optical losses and improve the quantum efficiency (QE) of 4H-SiC-based photodetectors. The important results will be introduced as follows:

According to transparent range, extinction coefficient, refractive index, mechanical properties and chemical reliability, Al2O3 and SiO2 films were selected in tens of optical film materials as antireflection coatings on 4H-SiC-based UV photodetectors. SiO2 film was designed between Al2O3 film and 4H-SiC substrate and Al2O3 film was deposited on SiO2 film according to its reliability. The optical thicknesses of Al2O3 and SiO2 film were designed according to the admittance matching technology. Al2O3/SiO2 films were deposited on 4H-SiC substrates by using electron-beam evaporation according to the film's design. The minimum reflectance of the films was 0.25% at 276 nm, which is the minimum attained so far. The minimum reflectance shifted to shorter wave‐ lengths with the increase of annealing temperature due to reduction of film thickness. The surface grains appeared to get larger in size and the root mean square (RMS)

© 2015 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

roughness of the annealed films increased with annealing temperature but was less than that of the as-deposited. Although the Al2O3/SiO2 film was kept amorphous, there were diffusion that Al silicates and Si suboxides were formed at the interface between films and 4H-SiC substrate.

4H-SiC-based MSM UV photodetectors with Al2O3/SiO2 films have been fabricated and compared with SiO2/4H-SiC MSM detectors. The photocurrent of the former was twice as large as the latter, while the dark current was also larger. The Al2O3/SiO2/4H-SiC devices showed a peak responsivity of 0.12 A/W at 290 nm under 20 V, which was twice as much as that of MSM detectors. The internal and external QE of the Al2O3/ SiO2/4H-SiC devices were 50% and 77% at 280 nm, respectively, which are the highest attained so far for 4H-SiC-based MSM photodetectors. The responsivity of the Al2O3/ SiO2/4H-SiC devices agreed well with their surface reflectance of 240–300 nm.

The Al2O3/SiO2 films prepared by oxidation and electron-beam evaporation were applied on 4H-SiC-based MIS photodiodes. The dark current of the devices was 1 pA, which was larger than that of SiO2/4H-SiC detectors due to undercutting of the mesa sidewall. But the photocurrent of the former was 2.8 nA, which is 2.8 times as large as that of the latter. There were slight gains in these two devices with the increase of backward bias voltage. The peak responsivities of Al2O3/SiO2/4H-SiC and SiO2/4H-SiC devices were 49 mA/W at 270 nm and 23 mA/W at 260 nm, respectively, corre‐ sponding to external QEs of 23% and 15%. The peak responsivities of these two devices agreed well with their minimum surface reflectances.

**Keywords:** Photodetectors, Antireflection coatings, Refraction index, Band gap, Transparent range

#### **1. Introduction**

Silicon carbide (SiC) has been considered to be a new generation semiconductor material for optoelectronic and power devices due to its wide band gap (3.26 eV for 4H-SiC), high break down electric field (3.0 MV/cm for 4H-SiC) and high thermal stability (4.9 W/cm K for 4H-SiC). In the recent decade, SiC-based ultraviolet (UV) photodetectors have been improved and developed greatly with all sorts of structures including Schottky diodes[1-3], metal-semicon‐ ductor-metal (MSM)[4-6], p-i-n[7-9], metal-insulator-semiconductor (MIS)[10] and avalanche photodiodes (APD)[11-13] for application in flame detection, ozone-hole sensing, short-range communication, etc. Generally, the photons can be absorbed in 4H-SiC overall below 360 nm except that more than 20% of them are reflected, as shown in Figure 1(a). Meanwhile, the absorption coefficient of the 4H-SiC is larger than 1000 below a wavelength of 300 nm and the penetration length of the previously mentioned UV light in 4H-SiC is below 4 µm, as depicted in Figure 1(b). Thus, high-quality antireflection (AR) coatings and clean interface between 4H-SiC and coatings are needed for reducing optical loss on the surfaces and interfaces in these SiC-based photodetectors. The recent results showed that the internal quantum efficiency of SiC photodetectors had reached 100%. Thus, improvement of external quantum efficiency of SiC photodetectors is particularly important and significant, which can be approached by depositing AR coatings. efficiency of SiC photodetectors had reached 100%. Thus, improvement of external quantum efficiency of SiC photodetectors is particularly important and significant, which can be approached by depositing AR coatings. The most widely used AR coatings for SiC-based photodetectors is silicon dioxide (SiO2), which

Silicon carbide (SiC) has been considered to be a new generation semiconductor material for optoelectronic and power devices due to its wide band gap (3.26 eV for 4H-SiC), high break down electric field (3.0 MV/cm for 4H-SiC) and high thermal stability (4.9 W/cm·K for 4H-SiC). In the recent decade, SiC-based ultraviolet (UV) photodetectors have been improved and developed greatly with all sorts of structures including Schottky diodes[1-3], metal-semiconductor-metal (MSM)[4-6], p-i-n[7-9], metal-insulator-semiconductor (MIS)[10] and avalanche photodiodes (APD)[11-13] for application in flame detection, ozone-hole sensing, short-range communication, etc. Generally, the photons can be absorbed in 4H-SiC overall below 360 nm except that more than 20% of them are reflected, as shown in Figure 1(a). Meanwhile, the absorption coefficient of the 4H-SiC is larger than 1000 below a wavelength of 300 nm and the penetration length of the previously mentioned UV light in 4H-SiC is below 4 μm, as depicted in Figure 1(b). Thus, high-quality antireflection (AR) coatings

The most widely used AR coatings for SiC-based photodetectors is silicon dioxide (SiO2), which is thermally grown by oxidizing the surface of SiC in a furnace at 1100°C–1300°C[14]. The reflection can be reduced to below 8% in the range of 220–380 nm. Although the SiO2 layer usually has good passivation quality, its optical properties such as large absorption, uncertain refractive index, inaccurate film thickness and high reflection cannot be controlled ideally. Therefore, it is necessary to redesign and grow the AR coatings for 4H-SiC UV photodetectors. is thermally grown by oxidizing the surface of SiC in a furnace at 1100C–1300C[14]. The reflection can be reduced to below 8% in the range of 220–380 nm. Although the SiO2 layer usually has good passivation quality, its optical properties such as large absorption, uncertain refractive index, inaccurate film thickness and high reflection cannot be controlled ideally. Therefore, it is necessary to redesign and grow the AR coatings for 4H-SiC UV photodetectors.

**Figure 1.** (a) The transmittance and reflectance spectra on a 4H-SiC surface without any coatings and (b) reflectance spectra of thermally grown SiO2 single layer in the 200–400 nm spectral range.

Figure 1. (a) The transmittance and reectance spectra on a 4H-SiC surface without any coatings and (b)

#### **2. Selection of AR coatings**

**Introduction**

roughness of the annealed films increased with annealing temperature but was less than that of the as-deposited. Although the Al2O3/SiO2 film was kept amorphous, there were diffusion that Al silicates and Si suboxides were formed at the interface between

4H-SiC-based MSM UV photodetectors with Al2O3/SiO2 films have been fabricated and compared with SiO2/4H-SiC MSM detectors. The photocurrent of the former was twice as large as the latter, while the dark current was also larger. The Al2O3/SiO2/4H-SiC devices showed a peak responsivity of 0.12 A/W at 290 nm under 20 V, which was twice as much as that of MSM detectors. The internal and external QE of the Al2O3/ SiO2/4H-SiC devices were 50% and 77% at 280 nm, respectively, which are the highest attained so far for 4H-SiC-based MSM photodetectors. The responsivity of the Al2O3/ SiO2/4H-SiC devices agreed well with their surface reflectance of 240–300 nm.

The Al2O3/SiO2 films prepared by oxidation and electron-beam evaporation were applied on 4H-SiC-based MIS photodiodes. The dark current of the devices was 1 pA, which was larger than that of SiO2/4H-SiC detectors due to undercutting of the mesa sidewall. But the photocurrent of the former was 2.8 nA, which is 2.8 times as large as that of the latter. There were slight gains in these two devices with the increase of backward bias voltage. The peak responsivities of Al2O3/SiO2/4H-SiC and SiO2/4H-SiC devices were 49 mA/W at 270 nm and 23 mA/W at 260 nm, respectively, corre‐ sponding to external QEs of 23% and 15%. The peak responsivities of these two devices

**Keywords:** Photodetectors, Antireflection coatings, Refraction index, Band gap,

Silicon carbide (SiC) has been considered to be a new generation semiconductor material for optoelectronic and power devices due to its wide band gap (3.26 eV for 4H-SiC), high break down electric field (3.0 MV/cm for 4H-SiC) and high thermal stability (4.9 W/cm K for 4H-SiC). In the recent decade, SiC-based ultraviolet (UV) photodetectors have been improved and developed greatly with all sorts of structures including Schottky diodes[1-3], metal-semicon‐ ductor-metal (MSM)[4-6], p-i-n[7-9], metal-insulator-semiconductor (MIS)[10] and avalanche photodiodes (APD)[11-13] for application in flame detection, ozone-hole sensing, short-range communication, etc. Generally, the photons can be absorbed in 4H-SiC overall below 360 nm except that more than 20% of them are reflected, as shown in Figure 1(a). Meanwhile, the absorption coefficient of the 4H-SiC is larger than 1000 below a wavelength of 300 nm and the penetration length of the previously mentioned UV light in 4H-SiC is below 4 µm, as depicted in Figure 1(b). Thus, high-quality antireflection (AR) coatings and clean interface between 4H-SiC and coatings are needed for reducing optical loss on the surfaces and interfaces in these SiC-based photodetectors. The recent results showed that the internal quantum efficiency of

agreed well with their minimum surface reflectances.

films and 4H-SiC substrate.

200 Advanced Silicon Carbide Devices and Processing

Transparent range

**1. Introduction**

There are many factors that need to be considered for the selection of UV AR coatings for 4H-SiC photodetectors including transparent range, refraction index, mechanical and chemical properties, etc. Although there are hundreds of materials that can be prepared for AR coatings, few of them are suitable for 4H-SiC in UV range.


**Table 1.** Optical and Mechanical Properties of Several Coating Materials in UV Range

#### **2.1. Transparent range**

Transparent range is the first and most important factor for 4H-SiC UV photodetectors, which means that AR coatings need to be transparent in the UV range especially at 200–400 nm. Only several oxides and fluorides can satisfy the condition such as Al2O3, SiO2, HfO2, CaF2, BaF2, MgF2, etc., as shown in Table 1. These materials have a large band gap so that the UV photons do not have adequate energy to achieve transition. Extinction coefficient is another factor that can characterize the transparent level of an optical film. The lower the extinction coefficient is, the better the transmittance of the film. The extinction coefficient is related to the crystal structure of the AR coatings. Generally, polycrystalline films have the largest extinction coefficients, amorphous films have lower extinction coefficients and single crystal lowest extinction coefficients. UV AR coatings have higher requirements on transmittance and extinction coefficients than visible AR coatings, thus only a few materials can meet the requirements, as shown in Table 1.

#### **2.2. Refraction index**

Refraction index is another important parameter for an optical material to be applied in photodetectors, which is required to match that of substrates so that AR effect can be achieved. Generally, refraction index increases with the decrease of the wavelength. The relationship between refraction index (*n*) and wavelength (*λ*) is[15]

$$\text{Im}\left(\mathcal{X}\right) = A\_1 + A\_2 \;/\; \mathcal{X}^2 + A\_3 \;/\; \mathcal{X}^4 \tag{1}$$

where *A*1, *A*2 and *A*3 are undetermined coefficients. Refraction index is also related to the density of optical materials, in which those with a higher density usually have a higher refraction index. Take Al2O3 for example, the refraction index of the Al2O3 film prepared by physical vapor deposition (PVD) or chemical vapor deposition (CVD) is lower than that of sapphire due to its lower density.

#### **2.3. Mechanical property and stability**

SiC is a superstable material with ultrahigh hardness, which is only lower than that of diamond. Thus, its AR coatings require suited mechanical property and high stability. Generally, fluorides such as CaF2, BaF2 and MgF2 are very soft materials, although their transparent ranges are adequately wide, as shown in Table 1, which are not suitable for SiC photodetectors. Oxides are probably the most suitable materials because they not only have high hardness but also high stability. It is necessary to notice that some oxides such as MgO have suitable transparent range and hardness but it is not stable and reacts with CO2 in the air, which cannot be used for AR coatings. Oxides such as Al2O3 and HfO2 have ultrahigh hardness, as shown in Table 1, which are good choices for SiC photodetectors.

#### **2.4. Electronic property**

**2.1. Transparent range**

202 Advanced Silicon Carbide Devices and Processing

requirements, as shown in Table 1.

sapphire due to its lower density.

**2.3. Mechanical property and stability**

between refraction index (*n*) and wavelength (*λ*) is[15]

l

as shown in Table 1, which are good choices for SiC photodetectors.

**2.2. Refraction index**

Transparent range is the first and most important factor for 4H-SiC UV photodetectors, which means that AR coatings need to be transparent in the UV range especially at 200–400 nm. Only several oxides and fluorides can satisfy the condition such as Al2O3, SiO2, HfO2, CaF2, BaF2, MgF2, etc., as shown in Table 1. These materials have a large band gap so that the UV photons do not have adequate energy to achieve transition. Extinction coefficient is another factor that can characterize the transparent level of an optical film. The lower the extinction coefficient is, the better the transmittance of the film. The extinction coefficient is related to the crystal structure of the AR coatings. Generally, polycrystalline films have the largest extinction coefficients, amorphous films have lower extinction coefficients and single crystal lowest extinction coefficients. UV AR coatings have higher requirements on transmittance and extinction coefficients than visible AR coatings, thus only a few materials can meet the

Refraction index is another important parameter for an optical material to be applied in photodetectors, which is required to match that of substrates so that AR effect can be achieved. Generally, refraction index increases with the decrease of the wavelength. The relationship

> ( ) 2 4 12 3 *n AA A*

where *A*1, *A*2 and *A*3 are undetermined coefficients. Refraction index is also related to the density of optical materials, in which those with a higher density usually have a higher refraction index. Take Al2O3 for example, the refraction index of the Al2O3 film prepared by physical vapor deposition (PVD) or chemical vapor deposition (CVD) is lower than that of

SiC is a superstable material with ultrahigh hardness, which is only lower than that of diamond. Thus, its AR coatings require suited mechanical property and high stability. Generally, fluorides such as CaF2, BaF2 and MgF2 are very soft materials, although their transparent ranges are adequately wide, as shown in Table 1, which are not suitable for SiC photodetectors. Oxides are probably the most suitable materials because they not only have high hardness but also high stability. It is necessary to notice that some oxides such as MgO have suitable transparent range and hardness but it is not stable and reacts with CO2 in the air, which cannot be used for AR coatings. Oxides such as Al2O3 and HfO2 have ultrahigh hardness,

ll

=+ + / / (1)

In photodetectors, AR coatings are also used as passivation layers to restrain the leakage current. Thus, electronic properties of the AR coatings are also significant for 4H-SiC UV photodetectors. Excellent coatings have wide band gap, high dielectric constant, high critical electric field and high conduction band gap. As shown in Table 2, some materials such as HfO2 have high dielectric constant but its critical electric field and conduction band gap are low. Meanwhile, other materials such as AlN and Si3N4 have ideal critical electric field and conduction band gap but narrow band gap and low dielectric constant.

Under comprehensive evaluation, though dielectric constants are not adequate high, Al2O3 and SiO2 are materials that not only have wide band gap and ideal transparent range but also suitable refractive index, high critical electric field and conduction band gap, which is the most suitable optical material as AR coatings for application in SiC UV photodetectors.


**Table 2.** Optical and Electronic Parameters of 4H-SiC and Dielectrics[16, 17]

#### **3. Design of AR coatings**

Design of AR coatings is the procedure to determine the thickness and refractive index of the optical materials. Admittance matching method was used to design AR films for 4H-SiC photodetectors. The reflection will happen when the incidence of UV light is from one material to another due to the mismatch of the refraction indices. The relationship between admittance (*Y*) and refraction index (*N*) is *Y* = *N* (*ε*0/*μ*0) 1/2. Thus, admittance matching is important and significant for the design of the AR coatings.

#### **3.1. Single-layer AR coating**

Single-layer AR coating is considered at first due to it is the simple system, as shown in Figure 2. The reflection coefficient of single-layer AR coating is

$$r = \frac{r\_1 + r\_2 \exp\left(-2i\delta\_1\right)}{1 + r\_1 r\_2 \exp\left(-2i\delta\_1\right)}\tag{2}$$

**Figure 2.** Incidence of UV light from a single-layer AR film to a SiC substrate (multiple reflections in AR films are ig‐ nored).

where *r*1 and *r*2 are reflection coefficients of surfaces of substrate and AR film, which can be presented as *r*<sup>1</sup> <sup>=</sup> *<sup>n</sup>*<sup>0</sup> <sup>−</sup> *<sup>n</sup>*<sup>1</sup> *n*<sup>0</sup> + *n*<sup>1</sup> and *r*<sup>2</sup> = *n*<sup>1</sup> −*n*<sup>2</sup> *n*<sup>1</sup> + *n*<sup>2</sup> . *δ*<sup>1</sup> is the phase thickness of single-layer AR coating and can be presented as *δ*<sup>1</sup> <sup>=</sup> <sup>2</sup>*<sup>π</sup> <sup>λ</sup> n*1*d*1cos*θ*1. Then the reflectance R is

$$R = \left| r \right|^2 = \frac{r\_1^2 + r\_2^2 + 2r\_1r\_2\cos 2\mathcal{S}\_1}{1 + r\_1^2r\_2^2 + 2r\_1r\_2\cos 2\mathcal{S}\_1} \tag{3}$$

Thus, when the light beam performs vertical incidence, the sufficient condition of *R* = 0 at some wavelength *λ*0 for single-layer AR coating is


If satisfying these two conditions, the coating is matching to the substrate and incident medium.

#### **3.2. Double-layer AR coatings**

Refraction indices of a substrate and an incident medium are *n*3 and *n*0, respectively. And refraction indices of double-layer AR coatings are *n*1 and *n*2, respectively, as shown in Figure 3. Then the interference matrix is

High-responsivity SiC Ultraviolet Photodetectors with SiO2 and Al2O3 Films http://dx.doi.org/10.5772/61019 205

$$
\begin{pmatrix} B \\ C \end{pmatrix} = \begin{pmatrix} \cos \delta\_1 & i \sin \delta\_1 / n\_1 \\ i n\_1 \sin \delta\_1 & \cos \delta\_1 \end{pmatrix} \begin{pmatrix} \cos \delta\_2 & i \sin \delta\_2 / n\_2 \\ i n\_2 \sin \delta\_2 & \cos \delta\_2 \end{pmatrix} \begin{pmatrix} 1 \\ n\_3 \end{pmatrix} \tag{4}$$

**Figure 3.** Incidence of UV light from double-layer AR films to a SiC substrate (multiple reflections in AR films are ig‐ nored).

$$Y = \frac{\mathbb{C}}{B} \tag{5}$$

If *Y* =*n*0, the *R* =0, the two following equations can be obtained:

$$\tan \mathcal{S}\_1 \tan \mathcal{S}\_2 = \frac{n\_1 n\_2 \left(n\_3 - n\_0\right)}{n\_1^2 n\_3 - n\_0 n\_2^2} \tag{6}$$

$$\frac{\tan \delta\_2}{\tan \delta\_1} = \frac{n\_2 \left(n\_0 n\_3 - n\_1^2\right)}{n\_1 \left(n\_2^2 - n\_0 n\_3\right)}\tag{7}$$

The equations can be transformed into

where *r*1 and *r*2 are reflection coefficients of surfaces of substrate and AR film, which can be

**Figure 2.** Incidence of UV light from a single-layer AR film to a SiC substrate (multiple reflections in AR films are ig‐

*<sup>λ</sup> n*1*d*1cos*θ*1. Then the reflectance R is

+ + = = + + *r r rr R r*

2 2 <sup>2</sup> 1 2 12 1 2 2

1 2 cos2

Thus, when the light beam performs vertical incidence, the sufficient condition of *R* = 0 at some

If satisfying these two conditions, the coating is matching to the substrate and incident

Refraction indices of a substrate and an incident medium are *n*3 and *n*0, respectively. And refraction indices of double-layer AR coatings are *n*1 and *n*2, respectively, as shown in Figure

1 2 12 1 2 cos2

d

d

. *δ*<sup>1</sup> is the phase thickness of single-layer AR coating and

*r r rr* (3)

presented as *r*<sup>1</sup> <sup>=</sup> *<sup>n</sup>*<sup>0</sup> <sup>−</sup> *<sup>n</sup>*<sup>1</sup>

nored).

medium.

can be presented as *δ*<sup>1</sup> <sup>=</sup> <sup>2</sup>*<sup>π</sup>*

*n*<sup>0</sup> + *n*<sup>1</sup>

204 Advanced Silicon Carbide Devices and Processing

wavelength *λ*0 for single-layer AR coating is

**3.2. Double-layer AR coatings**

3. Then the interference matrix is

and *r*<sup>2</sup> =

*n*<sup>1</sup> −*n*<sup>2</sup> *n*<sup>1</sup> + *n*<sup>2</sup>

**1.** Optical thickness of the coating is *λ*<sup>0</sup> / 4, that is *n*1*d*<sup>1</sup> =*λ*<sup>0</sup> / 4.

**2.** The refraction index *n*1 of the coating must satisfy *n*<sup>1</sup> <sup>=</sup> *<sup>n</sup>*0*n*2.

$$\tan^2 \mathcal{S}\_1 = \frac{\left(n\_3 - n\_0\right)\left(n\_2^2 - n\_0 n\_3\right)n\_1^2}{\left(n\_1^2 n\_3 - n\_0 n\_2^2\right)\left(n\_0 n\_3 - n\_1^2\right)}\tag{8}$$

$$\tan^2 \delta\_2 = \frac{\left(n\_3 - n\_0\right)\left(n\_0 n\_3 - n\_1^2\right)n\_2^2}{\left(n\_1^2 n\_3 - n\_0 n\_2^2\right)\left(n\_2^2 - n\_0 n\_3\right)}\tag{9}$$

Generally, there are three cases for the solutions:


**Figure 4.** Reflectance spectra of designed Al2O3/SiO2 double and SiO2 single AR coatings.

Comparison of reflectance has been made between Al2O3/SiO2 double layer and SiO2 single layer, as shown in Figure 4. (1) The reflectance of the Al2O3/SiO2 film (0.071%) has lower value than that of SiO2 film (2.1%). (2) The reflectance spectrum of the Al2O3/SiO2 film is narrower than that of SiO2 film, which indicates that there is a better selection of the wavelength for the Al2O3/SiO2 film. Therefore, the Al2O3/SiO2 film is more suitable as the AR coating for the 4H-SiC-based photodetectors.

#### **4. Growth of AR coatings**

#### **4.1. Thermal oxidation**

Generally, there are three cases for the solutions:

to (2) and (3), *δ*<sup>1</sup> =(2*n* −1)

206 Advanced Silicon Carbide Devices and Processing

layer that reduces the reflectance.

absorption of the films.

another can be solved by Equations (2) and (3).

*π*

**Figure 4.** Reflectance spectra of designed Al2O3/SiO2 double and SiO2 single AR coatings.

Comparison of reflectance has been made between Al2O3/SiO2 double layer and SiO2 single layer, as shown in Figure 4. (1) The reflectance of the Al2O3/SiO2 film (0.071%) has lower value than that of SiO2 film (2.1%). (2) The reflectance spectrum of the Al2O3/SiO2 film is narrower than that of SiO2 film, which indicates that there is a better selection of the wavelength for the

<sup>2</sup> , if the light beam performs vertical incidence, the optic thicknesses of the

<sup>2</sup> , *δ*<sup>2</sup> =*π*, that is, *n*1*d*<sup>1</sup> =*λ*<sup>0</sup> / 4 and *n*2*d*<sup>2</sup> =*λ*<sup>0</sup> / 2. In this case, the reflectance of the light

beam is not influenced by the second layer. However, this layer has an achromatic effect for the light beam with a wavelength of *λ*0. Therefore, for the system of air, Al2O3, SiO2 films and 4H-SiC substrate, the third case is the same as the second. The second layer SiO2 film has no contribution to the reflectance of the light beam. The Al2O3 film is the

<sup>2</sup> , *δ*<sup>2</sup> =*nπ* (*n* = 1, 2, 3...), *n* = 1 is selected to reduce the optical

two films are both *λ*<sup>0</sup> / 4, that is, *n*1*d*<sup>1</sup> =*n*2*d*<sup>2</sup> =*λ*<sup>0</sup> / 4, one of the *n*1 and *n*<sup>2</sup> can be fixed at first,

**2.** Set *n*1 and *n*2, according to Equations (2) and (3), *δ*1 and *δ*2 can be solved. The refraction indices are fixed to solve the thickness of the two films. For the system of air, Al2O3, SiO2 films and 4H-SiC substrate under the vertical incidence of light with the wavelength of *λ*0 = 280 nm, the refraction indices are *n*0 = 1.000, *n*1 = 1.685, *n*2 = 1.495, *n*3 = 2.995, according

**1.** Set *δ*<sup>1</sup> <sup>=</sup>*δ*<sup>2</sup> <sup>=</sup> *<sup>π</sup>*

**3.** Set *δ*<sup>1</sup> <sup>=</sup> *<sup>π</sup>*

SiO2 formed by thermal oxidation of SiC is most widely used as AR coatings in SiC UV photodetectors. As shown in Figure 5, the SiC wafers are put into the middle of the furnace with permanent temperature. Dry and wet oxygen (with H2O) are used to oxidize the SiC at 1100°C–1300°C. The oxidation rate is nonlinear and very low that 40-nm-thick SiO2 layer usually takes 4 h. With the increase of thickness, the oxidation rate is greatly reduced. Although the oxidized SiO2 is the densest state compared to the other growth methods and the leakage current of SiC devices with the layer is the lowest, absorption is also the largest especially in Si suboxides, which are usually formed at the interface between SiO2 and SiC. People added NO, N2O[18, 19], POCl3[20], etc., during the oxidation, which can reduce the sub-oxides and interface states. However, the absorption of the films still cannot be ignored. Thus, the oxidized SiO2 is suitable for passivation layer not for AR coatings on the window of SiC UV photode‐ tectors.

**Figure 5.** Thermal oxidation system for SiC up to 1300°C.

#### **4.2. Electron beam evaporation**

Electron beam evaporation is a physical vapor deposition that is applied to deposit oxides, fluorides, metals, etc. The electron beam is used to heat the surface of bulk materials to be vapor state and then the vapor deposit on the dome with lots of substrates, as illustrated in Figure 6. The AR coatings prepared by electron beam evaporation usually have high trans‐ mittance and low absorption, which perfectly meet the requirement of the AR coatings so that optical films are widely deposited and grown by using this technique. A shortcoming of the technique is that the deposited films are not as dense as that prepared by other techniques such as oxidation and sputtering, which may induce large leakage current in the 4H-SiC photode‐ tectors. Therefore, the electron beam evaporation can be applied to grow AR coatings on the windows of the 4H-SiC photodetectors but is not suitable for deposition of passivation layer to reduce the leakage current.

**Figure 6.** Cross-section view of electron beam evaporation system.

#### **4.3. Atomic layer deposition**

Atomic layer deposition (ALD) is a special chemical vapor deposition that is widely applied in microelectronic and optoelectronic fields to deposit oxides, nitrides, metals, etc[21-23]. As illustrated in Figure 7, the precursors and oxidants are pulsed into the chamber successively to deposit on the surface of the substrates monolayer by monolayer and cleaned by inert gases such as nitrogen during the deposition. A deposition sequence is usually that oxidants → nitrogen → precursors → nitrogen.

The precursors and oxidants do not meet and react with each other directly, otherwise, that would be a typical chemical vapor deposition. Al2O3[24], SiO2[25] and HfO2[26] films are usually grown by using ALD as gate dielectrics in microelectronic fields, which are so uniform that they can be deposited on a rough surface with almost the same thickness by using this technique. The leakage current can also be restrained well through the deposition. Optical

**Figure 7.** Atomic layer deposition system with *in situ* quartz crystal microbalance.

windows of the 4H-SiC photodetectors but is not suitable for deposition of passivation layer

Atomic layer deposition (ALD) is a special chemical vapor deposition that is widely applied in microelectronic and optoelectronic fields to deposit oxides, nitrides, metals, etc[21-23]. As illustrated in Figure 7, the precursors and oxidants are pulsed into the chamber successively to deposit on the surface of the substrates monolayer by monolayer and cleaned by inert gases such as nitrogen during the deposition. A deposition sequence is usually that oxidants →

The precursors and oxidants do not meet and react with each other directly, otherwise, that would be a typical chemical vapor deposition. Al2O3[24], SiO2[25] and HfO2[26] films are usually grown by using ALD as gate dielectrics in microelectronic fields, which are so uniform that they can be deposited on a rough surface with almost the same thickness by using this technique. The leakage current can also be restrained well through the deposition. Optical

to reduce the leakage current.

208 Advanced Silicon Carbide Devices and Processing

**Figure 6.** Cross-section view of electron beam evaporation system.

**4.3. Atomic layer deposition**

nitrogen → precursors → nitrogen.

properties of ALD films[27, 28] were examined and demonstrated that ALD can be an advanced technique to balance the optical and electrical properties of thin films. In order to get the best optical and electrical properties, thermal oxidation and electron beam evaporation were both applied to deposit Al2O3 and SiO2 AR films. SiC UV photodetectors with Al2O3 and SiO2 AR films are studied and demonstrated in the following sections.

### **5. SiC Photodetectors with Al2O3 and SiO2 films**

#### **5.1. 4H-SiC MSM photodetectors with Al2O3 and SiO2 films**

Two 4H-SiC MSM photodetectors were separately fabricated with electron beam-evaporated Al2O3/SiO2 double-layer films and thermal SiO2 single-layer films for comparison, which were prepared on two identical n-type 4H-SiC wafers with epilayers of 3.4 µm and doping level of 3.0 × 1015 cm–3. One of them was oxidized at 1150°C in an O2 atmosphere for 4 h. The final thickness of the SiO2 layer was approximately 40 nm, as measured by an ellipsometer. SiO2 and A12O3 layers were successively deposited on the other wafer by electron beam evapora‐ tion. The final thicknesses of the A12O3 and SiO2 films were 42 nm and 96 nm, respectively, which are quarter-wave and half-wave of the UV wavelength of 280 nm corresponding to calculated peak responsivity. Then, the reflectance spectra of these samples were measured by a commercial spectrophotometer. After confirmation of the spectra, the device fabrication process was immediately performed on two samples. Lithography and wet etching were done on the samples, then interdigitated electrodes were deposited by sputtering Au and Ni with a width and spacing of 2 and 2 µm, as shown in Figure 8. Finally, Au bonding pads were deposited on the ends of the electrodes. The spectral response measurements were performed on the devices by using a light source of LAX 1450 M Xe lamp and an Actron SpectraPro-2500i monochromator. The output power of the monochromatic light was measured and calibrated by a Si 222 photodetector. Then the light was illuminated on these two MSM photodetectors. The current-voltage (I–V) characteristics of these devices were measured by using an electro‐ meter and sourcemeter.

**Figure 8.** A cross-sectional view of 4H-SiC MSM photodetectors with Al2O3 and SiO2 films deposited by using electron beam evaporation.

These two Al2O3/SiO2/4H-SiC and SiO2/4H-SiC MSM devices both exhibit excellent optoelec‐ tronic properties, as presented in Figure 9(a). The photocurrent of Al2O3/SiO2/4H-SiC devices are approximately double that of SiO2/4H-SiC due to the lower reflection and absorption of Al2O3/SiO2 films. Meanwhile, the photocurrent of SiO2/4H-SiC devices increased with increas‐ ing voltage, which may be attributed to the charge traps at the interface between SiO2 and 4H-SiC. The dark current of the SiO2/4H-SiC (around 0.50 pA) was lower than that of the Al2O3/ SiO2/4H-SiC devices (7.5 pA at 10 V), as shown in Figure 9(b), which is attributed to the fact that the thermally grown SiO2 layer on 4H-SiC substrates was denser than the electron beam evaporated Al2O3/SiO2 films to restrain the leakage current of the devices.

Spectral responses of Al2O3/SiO2/4H-SiC and SiO2/4H-SiC MSM photodetectors were meas‐ ured under reverse voltage from 5 to 20 V, as shown in Figure 10(a). The peak responsivity of Al2O3/SiO2/4H-SiC photodetectors is 0.12 A/W at 20 V, which is more than twice that of SiO2/4H-SiC (0.055 A/W at 20 V) due to the lower reflection on Al2O3/SiO2/4H-SiC surface, as shown in Figure 10(b). Both devices achieved high UV to visible rejection ratio of >103 . The

the devices by using a light source of LAX 1450 M Xe lamp and an Actron SpectraPro-2500i

Al2O3/SiO2 double-layer films and thermal SiO2 single-layer films for comparison, which were prepared on two identical n-type 4H-SiC wafers with epilayers of 3.4 μm and doping level of 3.0 ×

the SiO2 layer was approximately 40 nm, as measured by an ellipsometer. SiO2 and A12O3 layers were successively deposited on the other wafer by electron beam evaporation. The final thicknesses of the A12O3 and SiO2 films were 42 nm and 96 nm, respectively, which are quarter-wave and half-wave of the UV wavelength of 280 nm corresponding to calculated peak responsivity. Then, the reflectance spectra of these samples were measured by a commercial spectrophotometer. After confirmation of the spectra, the device fabrication process was immediately performed on two samples. Lithography and wet etching were done on the samples, then interdigitated electrodes were deposited by sputtering Au and Ni with a width and spacing of 2 and 2 μm, as shown in Figure 8. Finally, Au bonding pads were deposited on the ends of the electrodes. The spectral response measurements were performed on the devices by using a light source of LAX 1450 M Xe lamp and an Actron SpectraPro-2500i monochromator. The output power of the monochromatic light was measured and calibrated by a Si 222 photodetector. Then the light was illuminated on these two MSM photodetectors. The

Al2O3/SiO2 double-layer films and thermal SiO2 single-layer films for comparison, which were prepared on two identical n-type 4H-SiC wafers with epilayers of 3.4 μm and doping level of 3.0 ×

the SiO2 layer was approximately 40 nm, as measured by an ellipsometer. SiO2 and A12O3 layers were successively deposited on the other wafer by electron beam evaporation. The final thicknesses of the A12O3 and SiO2 films were 42 nm and 96 nm, respectively, which are quarter-wave and half-wave of the UV wavelength of 280 nm corresponding to calculated peak responsivity. Then, the reflectance spectra of these samples were measured by a commercial spectrophotometer. After confirmation of the spectra, the device fabrication process was immediately performed on two samples. Lithography and wet etching were done on the samples, then interdigitated electrodes were deposited by sputtering

. One of them was oxidized at 1150C in an O2 atmosphere for 4 h. The final thickness of

. One of them was oxidized at 1150C in an O2 atmosphere for 4 h. The final thickness of

1015 cm<sup>3</sup>

1015 cm<sup>3</sup>

sourcemeter.

which are quarter-wave and half-wave of the UV wavelength of 280 nm corresponding to calculated peak responsivity. Then, the reflectance spectra of these samples were measured by a commercial spectrophotometer. After confirmation of the spectra, the device fabrication process was immediately performed on two samples. Lithography and wet etching were done on the samples, then interdigitated electrodes were deposited by sputtering Au and Ni with a width and spacing of 2 and 2 µm, as shown in Figure 8. Finally, Au bonding pads were deposited on the ends of the electrodes. The spectral response measurements were performed on the devices by using a light source of LAX 1450 M Xe lamp and an Actron SpectraPro-2500i monochromator. The output power of the monochromatic light was measured and calibrated by a Si 222 photodetector. Then the light was illuminated on these two MSM photodetectors. The current-voltage (I–V) characteristics of these devices were measured by using an electro‐

**Figure 8.** A cross-sectional view of 4H-SiC MSM photodetectors with Al2O3 and SiO2 films deposited by using electron

These two Al2O3/SiO2/4H-SiC and SiO2/4H-SiC MSM devices both exhibit excellent optoelec‐ tronic properties, as presented in Figure 9(a). The photocurrent of Al2O3/SiO2/4H-SiC devices are approximately double that of SiO2/4H-SiC due to the lower reflection and absorption of Al2O3/SiO2 films. Meanwhile, the photocurrent of SiO2/4H-SiC devices increased with increas‐ ing voltage, which may be attributed to the charge traps at the interface between SiO2 and 4H-SiC. The dark current of the SiO2/4H-SiC (around 0.50 pA) was lower than that of the Al2O3/ SiO2/4H-SiC devices (7.5 pA at 10 V), as shown in Figure 9(b), which is attributed to the fact that the thermally grown SiO2 layer on 4H-SiC substrates was denser than the electron beam

Spectral responses of Al2O3/SiO2/4H-SiC and SiO2/4H-SiC MSM photodetectors were meas‐ ured under reverse voltage from 5 to 20 V, as shown in Figure 10(a). The peak responsivity of Al2O3/SiO2/4H-SiC photodetectors is 0.12 A/W at 20 V, which is more than twice that of SiO2/4H-SiC (0.055 A/W at 20 V) due to the lower reflection on Al2O3/SiO2/4H-SiC surface, as shown in Figure 10(b). Both devices achieved high UV to visible rejection ratio of >103

. The

evaporated Al2O3/SiO2 films to restrain the leakage current of the devices.

meter and sourcemeter.

210 Advanced Silicon Carbide Devices and Processing

beam evaporation.

Figure 9. (a) Photocurrent and (b) dark (leakage) current of 4H-SiC MSM photodetectors with Al2O3/SiO2 **Figure 9.** (a) Photocurrent and (b) dark (leakage) current of 4H-SiC MSM photodetectors with Al2O3/SiO2 double-layer and thermal SiO2 single-layer films. Reproduced with permission from Ref. [5]. These two Al2O3/SiO2/4H-SiC and SiO2/4H-SiC MSM devices both exhibit excellent optoelectronic properties, as presented in Figure 9(a). The photocurrent of Al2O3/SiO2/4H-SiC devices are

**Figure 10.** (a) Spectral response and external quantum efficiency of SiO2/4H-SiC and Al2O3/SiO2/4H-SiC MSM photode‐ tectors under reverse voltages from 5 to 20 V. (b) Reflection spectra of the thermally grown SiO2 layer and evaporated Al2O3/SiO2 films on 4H-SiC from 200 to 400 nm. Reproduced with permission from Ref. [5].

Figure 10. (a) Spectral response and external quantum efficiency of SiO2/4H-SiC and Al2O3/SiO2/4H-SiC MSM

minimum reflectance of SiO2/4H-SiC was 3.2% at 262 nm, more than twelve times higher than that of Al2O3/SiO2/4H-SiC (0.25% at 284 nm close to the reference wavelength 280 nm). However, the peak responsivity of the SiO2/4H-SiC detectors was kept at a wavelength of 290 nm with the increasing voltage, which mainly relied on the thickness of the active epilayer (3.4 µm). The penetration depths of 4H-SiC were approximately 2.8 and 3.6 µm at the wavelengths of 290 and 300 nm, respectively, which indicates that photons can penetrate the active layer at the wavelength of 300 nm. Meanwhile, the shorter-wavelength light was also absorbed by the thermally grown SiO2 layer and the difference of reflectance between 260 nm and 290 nm was very small. Therefore, the wavelength corresponding to peak responsivity is 290 nm in SiO2/4H-SiC devices. The same phenomenon and analysis can also be observed and used in the Al2O3/SiO2/4H-SiC detectors.

The external quantum efficiency *ηe* of photodetectors can be obtained from *η<sup>e</sup>* ≅1241*R* / *λ* [29], where *R* is the responsivity in A/W and *λ* is the wavelength in nanometer. The maximum external quantum efficiency of the Al2O3/SiO2/4H-SiC UV photodetectors was approximately 50% at 280 nm, which is twice as much as that of SiO2/4H-SiC devices, as shown in Figure 10(a). These results were consistent with the reflectance of the Al2O3/SiO2/4H-SiC, which achieved the minimum of 0.25% at 280 nm on Al2O3/SiO2/4H-SiC and was just 1/14 of SiO2/4H-SiC, as shown in Figure 10(b). The relationship between external quantum efficiency *η*e and internal *η*<sup>i</sup> of MSM photodetectors can be expressed by the following equation:

$$\boldsymbol{\eta}\_{\varepsilon} = \boldsymbol{\eta}\_{i} \left( \mathbf{1} - \boldsymbol{R} \right) \left[ \mathbf{1} - \exp \left( -\alpha d \right) \right] \left[ \boldsymbol{W}\_{s} \left( \boldsymbol{W}\_{f} + \boldsymbol{W}\_{s} \right) \right] \tag{10}$$

where *R* is the reflectance of photodetectors, *α* an*d d* are the absorption coefficient and thickness of the active layer, W*<sup>f</sup>* and W*s* are separately the widths of electrodes and spacing. The internal quantum efficiencies were calculated to be 77% and 38% at 280 nm for Al2O3/SiO2/4H-SiC and SiO2/4H-SiC photodetectors, respectively. The highest quantum efficiency was obtained for 4H-SiC-based MSM photodetectors with Al2O3/SiO2 films, which indicates that the Al2O3/ SiO2 AR coatings can improve the optical and electrical properties efficiently.

**Figure 11.** X-ray photoelectron spectra of (a) electron beam evaporated Al2O3/SiO2 films and (b) thermally grown SiO2 layer.

The absorption of Al2O3/SiO2 films was ignored in the above expression because of the low extinction coefficients (10–5) of the coatings prepared by electron beam evaporation and inexistence of Si suboxides, as shown in Figure 11(a). While the absorption of the thermally grown SiO2 layer cannot be ignored due to the larger density and Si sub-oxides such as Si+ at the SiO2/4H-SiC interface, as shown in Figure 11(b), which are the reasons for the low quantum efficiency of SiO2/4H-SiC photodetectors.

The external quantum efficiency *ηe* of photodetectors can be obtained from *η<sup>e</sup>* ≅1241*R* / *λ* [29], where *R* is the responsivity in A/W and *λ* is the wavelength in nanometer. The maximum external quantum efficiency of the Al2O3/SiO2/4H-SiC UV photodetectors was approximately 50% at 280 nm, which is twice as much as that of SiO2/4H-SiC devices, as shown in Figure 10(a). These results were consistent with the reflectance of the Al2O3/SiO2/4H-SiC, which achieved the minimum of 0.25% at 280 nm on Al2O3/SiO2/4H-SiC and was just 1/14 of SiO2/4H-SiC, as shown in Figure 10(b). The relationship between external quantum efficiency *η*e and

of MSM photodetectors can be expressed by the following equation:

a

where *R* is the reflectance of photodetectors, *α* an*d d* are the absorption coefficient and thickness

quantum efficiencies were calculated to be 77% and 38% at 280 nm for Al2O3/SiO2/4H-SiC and SiO2/4H-SiC photodetectors, respectively. The highest quantum efficiency was obtained for 4H-SiC-based MSM photodetectors with Al2O3/SiO2 films, which indicates that the Al2O3/

**Figure 11.** X-ray photoelectron spectra of (a) electron beam evaporated Al2O3/SiO2 films and (b) thermally grown SiO2

( ) =- - - + é ùé ù ë ûë û *e i R dWWW s fs* (10)

and W*s* are separately the widths of electrodes and spacing. The internal

( ) () 1 1 exp /

SiO2 AR coatings can improve the optical and electrical properties efficiently.

internal *η*<sup>i</sup>

layer.

of the active layer, W*<sup>f</sup>*

h h

212 Advanced Silicon Carbide Devices and Processing

**Figure 12.** Comparison of spectral response and reflection spectra of Al2O3/SiO2/4H-SiC MSM UV photodetectors. Re‐ produced with permission from Ref. [5].

Comparisons between reflectance and response spectra were made in the Al2O3/SiO2/4H-SiC photodetectors to examine the spectral restriction effect of the Al2O3/SiO2 films, as shown in Figure 12. The spectral response is not exactly consistent with the reflectance from 200 to 240 nm, which may be due to the influence of the surface recombination. Then the variation of the spectral response matches the reflectance from 240 to 300 nm, which indicates that reflection is the dominant factor when the photons can be absorbed by the active layer completely as discussed above. Spectral response is not consistent with the reflectance from 300 to 380 nm, which is attributed to the fact that the photons can only be absorbed partly by the epilayer so that the photon absorption became dominant and the restriction effect of Al2O3/SiO2 films weakened.

The 4H-SiC MSM photodetectors with Al2O3/SiO2 AR coatings and SiO2 layer were fabricated and demonstrated. The highest responsivity and maximum external quantum efficiency were obtained with the Al2O3/SiO2 films, which proved that the design and application of Al2O3/ SiO2 films on the 4H-SiC MSM photodetectors are successful. The optical and electrical properties of the Al2O3/SiO2 films prepared by electron beam evaporation will be further studied in 4H-SiC MIS photodetectors.

#### **5.2. 4H-SiC MIS Photodiodes with Al2O3 and SiO2 films**

Two 4H-SiC MIS UV photodetectors with Al2O3/SiO2 and SiO2 films were fabricated on 4H-SiC wafers with a structure of 250 nm p type (*N*A = 1.6 × 1019 cm–3) top layer and 2300 nm n type (*N*<sup>D</sup> = 5 × 1015 cm–3) epitaxial layer on an n type (*N*<sup>D</sup> = 1 × 1020 cm–3) substrate. The substrate and epilayers both have orientations of 8° off the Si face (0001). Photoactive windows (200 × 200 µm2 ) were defined by using inductively coupled plasma (ICP) etcher. Wafers were oxidized in oxygen in the same conditions mentioned in the fabrication of MSM photodetectors and 40 nm SiO2 layers were obtained. Lithography and wet etching were carried out on the SiO2 layers until 6 nm left, as shown in Figure 13. Then Au and Ni/Au electrodes were deposited on the top and backside of 4H-SiC wafers and annealed at 1050°C in Ar for 5 min to get the ohmic contact. 42 nm thick Al2O3 and 48 nm thick SiO2 films were deposited as AR coatings on one 4H-SiC wafer by electron-beam evaporation. Thus, the final thicknesses of A12O3/SiO2 stack films were 42 and 88 nm, respectively. Then the reflection spectra of SiO2 and A12O3/SiO2 films on 4H-SiC substrates were examined by using a commercial spectrophotometer, respectively. Finally, the SiO2/4H-SiC and A12O3/SiO2/4H-SiC MIS photodetectors were finished.

**Figure 13.** A cross-sectional schematic of 4H-SiC MIS photodetectors with Al2O3/SiO2 films.

Photocurrents of SiO2/4H-SiC and A12O3/SiO2/4H-SiC MIS detectors are shown in Figure 14(a). The photocurrents of A12O3/SiO2/4H-SiC device was almost triple as much as that of SiO2/4H-SiC at 10 V, which is attributed to the fact that more photons can be absorbed by the devices with lower reflectance of A12O3/SiO2 films and generate more electron-hole pairs than the device with thermally grown SiO2 layer.

**5.2. 4H-SiC MIS Photodiodes with Al2O3 and SiO2 films**

214 Advanced Silicon Carbide Devices and Processing

µm2

Two 4H-SiC MIS UV photodetectors with Al2O3/SiO2 and SiO2 films were fabricated on 4H-SiC wafers with a structure of 250 nm p type (*N*A = 1.6 × 1019 cm–3) top layer and 2300 nm n type (*N*<sup>D</sup> = 5 × 1015 cm–3) epitaxial layer on an n type (*N*<sup>D</sup> = 1 × 1020 cm–3) substrate. The substrate and epilayers both have orientations of 8° off the Si face (0001). Photoactive windows (200 × 200

) were defined by using inductively coupled plasma (ICP) etcher. Wafers were oxidized in oxygen in the same conditions mentioned in the fabrication of MSM photodetectors and 40 nm SiO2 layers were obtained. Lithography and wet etching were carried out on the SiO2 layers until 6 nm left, as shown in Figure 13. Then Au and Ni/Au electrodes were deposited on the top and backside of 4H-SiC wafers and annealed at 1050°C in Ar for 5 min to get the ohmic contact. 42 nm thick Al2O3 and 48 nm thick SiO2 films were deposited as AR coatings on one 4H-SiC wafer by electron-beam evaporation. Thus, the final thicknesses of A12O3/SiO2 stack films were 42 and 88 nm, respectively. Then the reflection spectra of SiO2 and A12O3/SiO2 films on 4H-SiC substrates were examined by using a commercial spectrophotometer, respectively.

Finally, the SiO2/4H-SiC and A12O3/SiO2/4H-SiC MIS photodetectors were finished.

**Figure 13.** A cross-sectional schematic of 4H-SiC MIS photodetectors with Al2O3/SiO2 films.

the device with thermally grown SiO2 layer.

Photocurrents of SiO2/4H-SiC and A12O3/SiO2/4H-SiC MIS detectors are shown in Figure 14(a). The photocurrents of A12O3/SiO2/4H-SiC device was almost triple as much as that of SiO2/4H-SiC at 10 V, which is attributed to the fact that more photons can be absorbed by the devices with lower reflectance of A12O3/SiO2 films and generate more electron-hole pairs than

Figure 14. (a) Photocurrent and (b) leakage current of SiO2/4H-SiC and A12O3/SiO2/4H-SiC MIS photodetectors. Reproduced with permission from Ref. [10]. **Figure 14.** (a) Photocurrent and (b) leakage current of SiO2/4H-SiC and A12O3/SiO2/4H-SiC MIS photodetectors. Repro‐ duced with permission from Ref. [10].

The MIS photodetectors are actually a combination of MIS and p-i-n devices. Thus, the photocurrent was determined by both MIS and p-i-n structures in the devices. When the SiO2 layer in MIS was tunneled at a certain voltage, p-i-n junction restrained the tunneling currents so that the photocurrent was constant, as illustrated in Figure 14(a). However, the photocurrent of A12O3/SiO2/4H-SiC saturated form 0 V while that of S/4H-SiC saturated from 2.5 V, which is attributed to the fact that lots of electrons were trapped in the evaporated A12O3/SiO2 films as described above, and the charges made holes accumulate on the surface of 4H-SiC substrate and tunneled through the SiO2 layer. Therefore, built-in field and depletion regions were formed in the p-i-n structure and photocurrent can be generated without voltage applied, which is called the normally-on mode. However, the charges in SiO2/4H-SiC photodetectors were few so that the carriers could not tunnel through the SiO2 layer. A The MIS photodetectors are actually a combination of MIS and p-i-n devices. Thus, the photocurrent was determined by both MIS and p-i-n structures in the devices. When the SiO2 layer in MIS was tunneled at a certain voltage, p-i-n junction restrained the tunneling currents so that the photocurrent was constant, as illustrated in Figure 14(a). However, the photocurrent of A12O3/SiO2/4H-SiC saturated form 0 V while that of S/4H-SiC saturated from 2.5 V, which is attributed to the fact that lots of electrons were trapped in the evaporated A12O3/SiO2 films as described above, and the charges made holes accumulate on the surface of 4H-SiC substrate and tunneled through the SiO2 layer. Therefore, built-in field and depletion regions were formed in the p-i-n structure and photocurrent can be generated without voltage applied, which is called the normally-on mode. However, the charges in SiO2/4H-SiC photo‐ detectors were few so that the carriers could not tunnel through the SiO2 layer. A certain voltage needs to be applied on the device to achieve this purpose, which can be recognized as normallyoff mode.

certain voltage needs to be applied on the device to achieve this purpose, which can be recognized as normally-off mode. Leakage (dark) currents of SiO2/4H-SiC and A12O3/SiO2/4H-SiC MIS photodetectors were measured from 0 to 15 V to examine the electrical property of these films, as shown in Figure 14(b). Good passivation property of SiO2/4H-SiC was achieved for that the leakage current was lower than 0.13 pA at 10 V. However, the leakage current of the A12O3/SiO2/4H-SiC MIS device was 3.9 pA at 10 V, nearly 30 times higher than that of SiO2/4H-SiC device, which is due to the fact that the electron Leakage (dark) currents of SiO2/4H-SiC and A12O3/SiO2/4H-SiC MIS photodetectors were measured from 0 to 15 V to examine the electrical property of these films, as shown in Figure 14(b). Good passivation property of SiO2/4H-SiC was achieved for that the leakage current was lower than 0.13 pA at 10 V. However, the leakage current of the A12O3/SiO2/4H-SiC MIS device was 3.9 pA at 10 V, nearly 30 times higher than that of SiO2/4H-SiC device, which is due to the fact that the electron beam-evaporated A12O3/SiO2 films were not as dense as the thermally grown SiO2 layers and had trapped charges when the films were prepared. Thus, the electrical properties of the electron beam evaporated A12O3/SiO2 films need to be further improved.

beam-evaporated A12O3/SiO2 films were not as dense as the thermally grown SiO2 layers and had trapped charges when the films were prepared. Thus, the electrical properties of the electron beam evaporated A12O3/SiO2 films need to be further improved. The spectral response of the 4H-SiC UV detectors with A12O3/SiO2 and SiO2 films were measured and studied in the wavelength range from 200 to 400 nm. The peak responsivities of these devices were 30 mA/W at 260 nm with a single SiO2 layer and 50 mA/W at 270 nm with A12O3/SiO2 double-layer, respectively, as shown in Figure 15(a). The surface reflectances of the two coatings on 4H-SiC substrate are shown in Figure 15(b). The minimum reflectance of A12O3/SiO2 films is 0.34% nm and only 1/10 of single SiO2 layer, which agrees well with the

to 10 V. (b) Reflection spectra of SiO2/4H-SiC and A12O3/SiO2/4H-SiC in the spectral range of 200–400 nm. Reproduced with permission from Ref. [10]. **Figure 15.** (a) Spectral response of SiO2/4H-SiC and A12O3/SiO2/4H-SiC MIS detectors from 200 to 400 nm at 0 to 10 V. (b) Reflection spectra of SiO2/4H-SiC and A12O3/SiO2/4H-SiC in the spectral range of 200–400 nm. Reproduced with permission from Ref. [10].

Figure 15. (a) Spectral response of SiO2/4H-SiC and A12O3/SiO2/4H-SiC MIS detectors from 200 to 400 nm at 0

AR coatings designed above. It is interesting that the peak responsivity of the A12O3/SiO2/4H-SiC detectors is not at the wavelength of 280 nm, which corresponds to the minimum reflec‐ tance of the A12O3/SiO2 films. The following reasons can be considered. First, the active region length in the device is 2.25 µm, including the thickness of depletion region and hole diffusion length. The penetration depths of the wavelength at 270 and 280 nm are 1.83 and 2.30 µm[30], respectively, so that the 270 nm UV light can be absorbed completely. Thus, the peak respon‐ sivity of the A12O3/SiO2/4H-SiC MIS photodetectors is at the wavelength of 270 nm. Mean‐ while, the diffusion length of the electron is approximately 21 µm, which is longer than the nonintentionally doped n-type epilayer so that the electrons can approach the bottom electrode easily. The responsivity of these two devices was not as much as above MSM photodetectors because the carriers need to tunnel through the 6 nm SiO2 insulator in the MIS detectors, which reduced the quantum efficiency and responsivity. Nevertheless, the leakage current of the MIS device was improved greatly, which is only 1/5 of the MSM device. The UV-to-visible rejection ratios in MIS detectors also achieved 2 × 103 by using the A12O3/SiO2 double-layer AR coatings, which is the highest in 4H-SiC-based MIS photodetectors and is attributed to good passivation property of thermally grown SiO2 layer and A12O3/SiO2 double-layer and low leakage current. The spectral response of the 4H-SiC UV detectors with A12O3/SiO2 and SiO2 films were measured and studied in the wavelength range from 200 to 400 nm. The peak responsivities of these devices were 30 mA/W at 260 nm with a single SiO2 layer and 50 mA/W at 270 nm with A12O3/SiO2 double-layer, respectively, as shown in Figure 15(a). The surface reflectances of the two coatings on 4H-SiC substrate are shown in Figure 15(b). The minimum reflectance of A12O3/SiO2 films is 0.34% nm and only 1/10 of single SiO2 layer, which agrees well with the AR coatings designed above. It is interesting that the peak responsivity of the A12O3/SiO2/4H-SiC detectors is not at the wavelength of 280 nm, which corresponds to the minimum reflectance of the A12O3/SiO2 films. The following reasons can be considered. First, the active region length in the device is 2.25 µm, including the thickness of depletion region and hole diffusion length. The penetration depths of the wavelength at 270 and 280 nm are 1.83 and 2.30 µm[30], respectively, so that the 270 nm UV light can be absorbed completely. Thus, the peak responsivity of the A12O3/SiO2/4H-SiC MIS photodetectors is at the wavelength of 270 nm. Meanwhile, the diffusion length of the electron is approximately 21 µm,

In the wavelength from 250 to 380 nm, the responsivity of 4H-SiC MIS detectors with A12O3/ SiO2 film is higher than that of with SiO2 film, as shown in Figure 15(a). The wavelength range is even wider than the lower reflectance region (260 to 300 nm) of the A12O3/SiO2 films, as shown in Figure 15(b). I-V characteristics of these two devices were performed without UV exposure to study the wideband higher response. Ohmic conduction mechanism is dominant according to the current curve-fitting in the low electric field, as illustrated in Figure 16(a). Fowler–Nordheim (FN) tunneling is converted to the main conduction mechanism in both devices with increasing electric field (*E*), which can be expressed by[31] which is longer than the nonintentionally doped n-type epilayer so that the electrons can approach the bottom electrode easily. The responsivity of these two devices was not as much as above MSM photodetectors because the carriers need to tunnel through the 6 nm SiO2 insulator in the MIS detectors, which reduced the quantum efficiency and responsivity. Nevertheless, the leakage current of the MIS device was improved greatly, which is only 1/5 of the MSM device. The UV-to-visible rejection ratios in MIS detectors also achieved 2 × 103 by using the A12O3/SiO2 double-layer AR coatings, which is the highest in 4H-SiC-based MIS photodetectors and is attributed to good

passivation property of thermally grown SiO2 layer and A12O3/SiO2 double-layer and low leakage

$$J = A \bullet E^2 \exp\left(-B / E\right) \tag{11}$$

passivation property of thermally grown SiO2 layer and A12O3/SiO2 double-layer and low leakage High-responsivity SiC Ultraviolet Photodetectors with SiO2 and Al2O3 Films http://dx.doi.org/10.5772/61019 217

by using the A12O3/SiO2 double-layer AR

coatings, which is the highest in 4H-SiC-based MIS photodetectors and is attributed to good

rejection ratios in MIS detectors also achieved 2 × 103

current.

were 30 mA/W at 260 nm with a single SiO2 layer and 50 mA/W at 270 nm with A12O3/SiO2 double-layer, respectively, as shown in Figure 15(a). The surface reflectances of the two coatings on 4H-SiC substrate are shown in Figure 15(b). The minimum reflectance of A12O3/SiO2 films is 0.34% nm and only 1/10 of single SiO2 layer, which agrees well with the AR coatings designed above. It is interesting that the peak responsivity of the A12O3/SiO2/4H-SiC detectors is not at the wavelength of 280 nm, which corresponds to the minimum reflectance of the A12O3/SiO2 films. The following reasons can be considered. First, the active region length in the device is 2.25 µm, including the thickness of depletion region and hole diffusion length. The penetration depths of the wavelength at 270 and 280 nm are 1.83 and 2.30 µm[30], respectively, so that the 270 nm UV light can be absorbed completely. Thus, the peak responsivity of the A12O3/SiO2/4H-SiC MIS photodetectors is at the wavelength of 270 nm. Meanwhile, the diffusion length of the electron is approximately 21 µm, which is longer than the nonintentionally doped n-type epilayer so that the electrons can approach the bottom electrode easily. The responsivity of these two devices was not as much as above MSM photodetectors because the carriers need to tunnel through the 6 nm SiO2 insulator in the MIS detectors, which reduced the quantum efficiency and responsivity. Nevertheless, the leakage current of the MIS device was improved greatly, which is only 1/5 of the MSM device. The UV-to-visible

Figure 16. (a) I-V characteristics of SiO2/4H-SiC and A12O3/SiO2/4H-SiC photodetectors without UV exposure and (b) band alignment of A12O3/SiO2/4H-SiC structure under UV exposure in accumulation state. Reproduced with permission from Ref. [10]. **Figure 16.** (a) I-V characteristics of SiO2/4H-SiC and A12O3/SiO2/4H-SiC photodetectors without UV exposure and (b) band alignment of A12O3/SiO2/4H-SiC structure under UV exposure in accumulation state. Reproduced with permis‐ sion from Ref. [10].

where *A* = *q*<sup>3</sup> *m*SiC/(8*πhm<sup>i</sup> Φ*B) and *B* = 4(2*mi Φ*<sup>B</sup> 3 ) 1/2/(3*qћ*). *q* is the electron charge, *m*SiC and *mi* are effective electron masses in 4H-SiC and SiO2, respectively. *h* (*ћ*) is the (reduced) Planck constant, and *Φ*<sup>B</sup> is the barrier height of SiO2 on 4H-SiC. The *Φ*<sup>B</sup> was calculated to be 1.94 eV by using Equation (10). Then, the valence band offset was 3.8 eV by using *E*v = *E*SiO2 – *E*4H-SiC – *Φ*B, where *E*v, *E*SiO2 and E4H-SiC are valence band offset, band gaps of SiO2 and 4H-SiC, respec‐ tively. Then, band alignments of the A12O3/SiO2/4H-SiC and SiO2/4H-SiC were obtained, as shown in Figure 16(b). Tunneling probability (*T*) was increased through the electrons trapped in evaporated A12O3/SiO2 films attract more holes. The responsivity (Rrep) of the MIS photo‐ detectors is determined by Rrep = (λ/1241)∙(1 – R – Afilm)∙T. where λ is wavelength of incident light, R and Afilm are reflectance and absorptance of AR coatings, respectively. According to the expression, the tunneling probability of holes in the SiO2 films was lower than in the A12O3/SiO2 films so that high spectral response range can be wider than low reflectance region. In the wavelength from 250 to 380 nm, the responsivity of 4H-SiC MIS detectors with A12O3/SiO2

4H-SiC-based MIS UV photodetectors with thermally grown SiO2 layer and evaporated A12O3/SiO2 films were fabricated and demonstrated. Low leakage current and high UV-tovisible rejection ratios >2 × 103 had been achieved for these devices. The 4H-SiC MIS photode‐ tectors with A12O3/SiO2 AR coatings presented higher responsivity and quantum efficiency, which demonstrate that the design and deposition of Al2O3/SiO2 films are effective and significant for the 4H-SiC UV photodetectors.

#### **Acknowledgements**

AR coatings designed above. It is interesting that the peak responsivity of the A12O3/SiO2/4H-SiC detectors is not at the wavelength of 280 nm, which corresponds to the minimum reflec‐ tance of the A12O3/SiO2 films. The following reasons can be considered. First, the active region length in the device is 2.25 µm, including the thickness of depletion region and hole diffusion length. The penetration depths of the wavelength at 270 and 280 nm are 1.83 and 2.30 µm[30], respectively, so that the 270 nm UV light can be absorbed completely. Thus, the peak respon‐ sivity of the A12O3/SiO2/4H-SiC MIS photodetectors is at the wavelength of 270 nm. Mean‐ while, the diffusion length of the electron is approximately 21 µm, which is longer than the nonintentionally doped n-type epilayer so that the electrons can approach the bottom electrode easily. The responsivity of these two devices was not as much as above MSM photodetectors because the carriers need to tunnel through the 6 nm SiO2 insulator in the MIS detectors, which reduced the quantum efficiency and responsivity. Nevertheless, the leakage current of the MIS device was improved greatly, which is only 1/5 of the MSM device. The UV-to-visible rejection

**Figure 15.** (a) Spectral response of SiO2/4H-SiC and A12O3/SiO2/4H-SiC MIS detectors from 200 to 400 nm at 0 to 10 V. (b) Reflection spectra of SiO2/4H-SiC and A12O3/SiO2/4H-SiC in the spectral range of 200–400 nm. Reproduced with

Figure 15. (a) Spectral response of SiO2/4H-SiC and A12O3/SiO2/4H-SiC MIS detectors from 200 to 400 nm at 0 to 10 V. (b) Reflection spectra of SiO2/4H-SiC and A12O3/SiO2/4H-SiC in the spectral range of 200–400 nm.

The spectral response of the 4H-SiC UV detectors with A12O3/SiO2 and SiO2 films were measured and studied in the wavelength range from 200 to 400 nm. The peak responsivities of these devices were 30 mA/W at 260 nm with a single SiO2 layer and 50 mA/W at 270 nm with A12O3/SiO2 double-layer, respectively, as shown in Figure 15(a). The surface reflectances of the two coatings on 4H-SiC substrate are shown in Figure 15(b). The minimum reflectance of A12O3/SiO2 films is 0.34% nm and only 1/10 of single SiO2 layer, which agrees well with the AR coatings designed above. It is interesting that the peak responsivity of the A12O3/SiO2/4H-SiC detectors is not at the wavelength of 280 nm, which corresponds to the minimum reflectance of the A12O3/SiO2 films. The following reasons can be considered. First, the active region length in the device is 2.25 µm, including the thickness of depletion region and hole diffusion length. The penetration depths of the wavelength at 270 and 280 nm are 1.83 and 2.30 µm[30], respectively, so that the 270 nm UV light can be absorbed completely. Thus, the peak responsivity of the A12O3/SiO2/4H-SiC MIS photodetectors is at the wavelength of 270 nm. Meanwhile, the diffusion length of the electron is approximately 21 µm, which is longer than the nonintentionally doped n-type epilayer so that the electrons can approach the bottom electrode easily. The responsivity of these two devices was not as much as above MSM photodetectors because the carriers need to tunnel through the 6 nm SiO2 insulator in the MIS detectors, which reduced the quantum efficiency and responsivity. Nevertheless, the leakage current of the MIS device was improved greatly, which is only 1/5 of the MSM device. The UV-to-visible

**Refelctance (%)**

which is the highest in 4H-SiC-based MIS photodetectors and is attributed to good passivation property of thermally grown SiO2 layer and A12O3/SiO2 double-layer and low leakage current.

In the wavelength from 250 to 380 nm, the responsivity of 4H-SiC MIS detectors with A12O3/ SiO2 film is higher than that of with SiO2 film, as shown in Figure 15(a). The wavelength range is even wider than the lower reflectance region (260 to 300 nm) of the A12O3/SiO2 films, as shown in Figure 15(b). I-V characteristics of these two devices were performed without UV exposure to study the wideband higher response. Ohmic conduction mechanism is dominant according to the current curve-fitting in the low electric field, as illustrated in Figure 16(a). Fowler–Nordheim (FN) tunneling is converted to the main conduction mechanism in both

coatings, which is the highest in 4H-SiC-based MIS photodetectors and is attributed to good passivation property of thermally grown SiO2 layer and A12O3/SiO2 double-layer and low leakage

devices with increasing electric field (*E*), which can be expressed by[31]

rejection ratios in MIS detectors also achieved 2 × 103

by using the A12O3/SiO2 double-layer AR coatings,

by using the A12O3/SiO2 double-layer AR

**200 240 280 320 360 400**

**Wavelength (nm)**

 **SiO2 /4H-SiC**

 **Al2 O3 /SiO2 /4H-SiC**

( ) <sup>2</sup> *J AE B E* = - g exp / (11)

ratios in MIS detectors also achieved 2 × 103

**200 250 300 350 400 <sup>10</sup>-7**

 **0V 5V 10V**

**SiO2 /4H-SiC 0V 5V 10V Al2 O3 /SiO2 /4H-SiC**

**Wavelength (nm)**

**10-6 10-5 10-4 10-3 10-2 10-1**

**(a)**

216 Advanced Silicon Carbide Devices and Processing

Reproduced with permission from Ref. [10].

**Responsivity (A/W)**

permission from Ref. [10].

The author acknowledges support from the National Basic Research Program of China (grant no. 2015CB759600), National Natural Science Foundation of China (grant no. 61474113) and Beijing Natural Science Foundation (grant no. 4132076).

#### **Author details**

#### Feng Zhang

Address all correspondence to: fzhang@semi.ac.cn

Key Laboratory of Semiconductor Material Sciences, Institute of Semiconductors, Chinese Academy of Sciences, Beijing, People's Republic of China

#### **References**


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**Author details**

218 Advanced Silicon Carbide Devices and Processing

Address all correspondence to: fzhang@semi.ac.cn

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Stefania Castelletto, Lorenzo Rosa and Brett C. Johnson Stefania Castelletto1∗, Lorenzo Rosa2, 3 and Brett C. Johnson4

Additional information is available at the end of the chapter Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/61166 10.5772/61166

#### **Abstract**

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[28] Y. Kim, S. M. Lee, C. S. Park, S. I. Lee, and M. Y. Lee. Substrate dependence on the optical properties of Al2O3 films grown by atomic layer deposition. Applied Physics

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[30] S. G. Sridhara, R. P. Devaty, and W. J. Choyke. Absorption coefficient of 4H silicon carbide from 3900 to 3250 angstrom. Journal of Applied Physics 1998; 84 2963-2964.

[31] K. Y. Cheong, J. H. Moon, H. J. Kim, W. Bahng, and N. K. Kim. Current conduction mechanisms in atomic-layer-deposited HfO(2)/nitrided SiO(2) stacked gate on 4H sil‐

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Silicon carbide (SiC) has recently been investigated as an alternative material to host deep optically active defects suitable for optical and spin quantum bits. This material presents a unique opportunity to realise more advanced quantum-based devices and sensors than currently possible. We will summarise key results revealing the role that defects have played in enabling optical and spin quantum measurements in this material such as single photon emission and optical spin control. The great advantage of SiC lies in its existing and well-developed device processing protocols and the possibilities to integrate these defects in a straightforward manner. There is particular current interest in nanomaterials and nanophotonics in SiC that could, once realised, introduce a new platform for quantum nanophotonics and in general for photonics. We will summarise SiC nanostructures exhibiting optical emission due to multiple polytypic bandgap engineering and deep defects. The combination of nanostructures and in-built paramagnetic defects in SiC could pave the way for future single-particle and single-defect quantum devices and related biomedical sensors with single-molecule sensitivity. We will review relevant classical devices in SiC (photonics crystal cavities, microdiscs) integrated with intrinsic defects. Finally, we will provide an outlook on future sensors that could arise from the integration of paramagnetic defects in SiC nanostructures and devices.

**Keywords**: Silicon carbide deep defects, Paramagnetic properties, Optical-detected magnetic resonance, Single-photon sources

#### **1. Introduction**

The most common and technologically advanced SiC polytypes are 4H-SiC and 6H-SiC with hexagonal structures and 3C-SiC with a zinc-blende crystal structure (cubic). High-quality

Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. © 2015 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

©2012 Author(s), licensee InTech. This is an open access chapter distributed under the terms of the Creative

bulk single-crystal 3C-SiC can be grown epitaxially on different substrates, most notably on silicon. This has led to many exciting devices fabricated with this particular polytype[1]. SiC has a wide bandgap (2.4-3.2 eV depending on the polytype), a high thermal conductivity, the ability to sustain high electric fields before breakdown and the highest maximum current density, making it ideal for high-power electronics [2]. More recently, it has become a notable material in the field of quantum computing and spintronics as several of its intrinsic defects are associated with an electron spin that can be used as quantum bit [3, 4]. To enhance solid-state quantum systems scalability, a fully integrated device with quantum control should be built; thus, quantum systems should be part of the material used to fabricate the final device. Other solid-state quantum systems fully integrated into a functional device[5–7] operate at cryogenic temperatures (4 K or below), limiting their engineering and scalability. A room temperature solid-state "qubit" is the nitrogen vacancy (NV) centre[8] in diamond; yet diamond is not mature for standard device fabrication protocols. SiC, on the other hand, is widely used in LEDs (commonly as a substrate for GaN films), power electronics and microelectromechanical and nano-electromechanical systems (MEMs, NEMs) [9, 10] and has well-developed device processing protocols which are compatible with industry standards. In addition, nanostructures can be formed in SiC such as nanoparticles, quantum dots, nanowires and nanopillars. The ability to grow SiC on silicon provides an unprecedented advantage which facilitates the fabrication of nanophotonic cavities[11, 12]. As a compound semiconductor, SiC harbours a rich assortment of optically active intrinsic and extrinsic defects that can be used as quantum systems.

In this chapter, we will summarise key findings and the main properties of deep optical and paramagnetic defects in bulk SiC that very recently have prompted novel quantum effects such as single-photon source (SPS) and quantum coherence control of their spin[13–17]. We will review defects with optical emission used in quantum spintronics and quantum optics, optically detected resonance methods applied to these defects, the achievement of coherent control of ensemble and single spins and their present spin coherence times. We will review single-photon emission from nanostructures of silicon carbide[18, 19]. We will review recent nanophotonics advances[20–30] in this material to achieve defect integration and enhancement. Other applications of the engineered defects in quantum technologies are also summarised. Some challenges still remain before this material can fully realise its potential in advancing quantum technology. In the summary, we critically analyse present challenges based on the reported results and provide an outlook of likely future investigations that can lead to successful application of SiC for quantum devices.

#### **2. Deep defects in SiC with quantum properties**

Many deep-energy-level defects within the bandgap give rise to radiative recombination in SiC with photoluminescence (PL) from the UV to the infrared. The dual compound nature and the existence of nonequivalent lattice sites in different polytypes (quasi-cubic, k, and hexagonal, h) give rise to a large variety of possible PL. Here, we will discuss only recently investigated defects that provided so far experimental evidence of quantum effects[14–16]. These defects are intrinsic defects, known as silicon vacancies (VSi)[31–33], divacancies (VSiVC)[34] and carbon antisite-vacancy pair (CSiVC )[35, 36]. In Figures 1-3, we show the atomistic defect structure and the presently understood energy levels corresponding to so far identified quantum systems in 4H, 6H and 3C polytypes. These defects coincide with the most commonly previously observed intrinsic defects in the material. They can be created in ensemble by neutron or electron irradiation, followed by annealing, as well as they can be created during growth. Recent experimental challenges rely in their creation as isolated systems or individual defects with their correlation to the ensemble level for their identification in bulk SiC. For this to be reliable, due to the large variability properties of the bulk material, which also can present many defects at the same time, the purity of the pristine wafer resulted to be essential. Therefore, the isolation of single defects as quantum systems was performed in high purity 4H intrinsic SiC. These defects act as radiative recombination centres within the bandgap with a PL achieved by out-of-resonance excitation with a laser. The PL is typically characterised by a sharp zero-phonon line (ZPL) and phonon side bands (PSB) at longer emission wavelengths. Recombination centres are modelled as a quantum system with ground, excited and metastable states (a two- or three-level system). These defects can have different ZPLs in the first instance according to the polytype, which provides nonequivalent crystallographic sites in the matrix. Additionally, the material doping can influence the emission wavelength. They are often characterised by a charge state which also can influence the spectral location of the ZPL peak. The charge state is also associated to the spin state (mostly of the ground state) of the defect, which can be observed from PL measurements as a reduction/enhancement (depending on the mechanism of the population of the energy levels) of the PL, when probed with the application of an additional magnetic field or a microwave excitation in resonance with the spin sublevels. Other defects also yielding quantum properties are not yet presently completely identified. The main effect on the variation of the defects ZPLs is related to the polytype, whether the defect occupies an axial position in the lattice (orientation along the c-axis, hh or kk lattice location) or an off-axis position (hk, kh orientation basal); thus, at least 2*<sup>n</sup>* ZPLs can be present for n-nonequivalent crystallographic site positions. In addition, the symmetry of the defects can give rise to other ZPLs with an excited state split by Jahn-Teller distortion, reducing the symmetry and introducing additional ZPLs. VSi consists of a missing silicon atom in the matrix. In 4H-SiC, VSi shows two ZPLs (two nonequivalent sites) stable up to 500-600◦C; in addition, two possible charge states are known. The ZPL, known as V1, emits at 862.2 nm, while V2 emits at 917.0 nm. These lines have been associated to a negative charge state, while the neutral charge state has ZPLs at 859.0 nm and 861.7 nm, respectively. Both defects are quite common in 4H- and 6H-SiC, as well as in 3C. The VSi negative charge in 4H and 6H has a high spin (S=3/2) ground state, shown in Figure 1(c)[32]. VSi ZPL emissions in 6H-SiC are known as V1,V2 and V3 lines, owning to the three nonequivalent sites (h,k1,k2; see Figure 1) at 865 nm, 887 nm and 906 nm, respectively.

2 Silicon Carbide Devices

defects that can be used as quantum systems.

lead to successful application of SiC for quantum devices.

**2. Deep defects in SiC with quantum properties**

bulk single-crystal 3C-SiC can be grown epitaxially on different substrates, most notably on silicon. This has led to many exciting devices fabricated with this particular polytype[1]. SiC has a wide bandgap (2.4-3.2 eV depending on the polytype), a high thermal conductivity, the ability to sustain high electric fields before breakdown and the highest maximum current density, making it ideal for high-power electronics [2]. More recently, it has become a notable material in the field of quantum computing and spintronics as several of its intrinsic defects are associated with an electron spin that can be used as quantum bit [3, 4]. To enhance solid-state quantum systems scalability, a fully integrated device with quantum control should be built; thus, quantum systems should be part of the material used to fabricate the final device. Other solid-state quantum systems fully integrated into a functional device[5–7] operate at cryogenic temperatures (4 K or below), limiting their engineering and scalability. A room temperature solid-state "qubit" is the nitrogen vacancy (NV) centre[8] in diamond; yet diamond is not mature for standard device fabrication protocols. SiC, on the other hand, is widely used in LEDs (commonly as a substrate for GaN films), power electronics and microelectromechanical and nano-electromechanical systems (MEMs, NEMs) [9, 10] and has well-developed device processing protocols which are compatible with industry standards. In addition, nanostructures can be formed in SiC such as nanoparticles, quantum dots, nanowires and nanopillars. The ability to grow SiC on silicon provides an unprecedented advantage which facilitates the fabrication of nanophotonic cavities[11, 12]. As a compound semiconductor, SiC harbours a rich assortment of optically active intrinsic and extrinsic

In this chapter, we will summarise key findings and the main properties of deep optical and paramagnetic defects in bulk SiC that very recently have prompted novel quantum effects such as single-photon source (SPS) and quantum coherence control of their spin[13–17]. We will review defects with optical emission used in quantum spintronics and quantum optics, optically detected resonance methods applied to these defects, the achievement of coherent control of ensemble and single spins and their present spin coherence times. We will review single-photon emission from nanostructures of silicon carbide[18, 19]. We will review recent nanophotonics advances[20–30] in this material to achieve defect integration and enhancement. Other applications of the engineered defects in quantum technologies are also summarised. Some challenges still remain before this material can fully realise its potential in advancing quantum technology. In the summary, we critically analyse present challenges based on the reported results and provide an outlook of likely future investigations that can

Many deep-energy-level defects within the bandgap give rise to radiative recombination in SiC with photoluminescence (PL) from the UV to the infrared. The dual compound nature and the existence of nonequivalent lattice sites in different polytypes (quasi-cubic, k, and hexagonal, h) give rise to a large variety of possible PL. Here, we will discuss only recently investigated defects that provided so far experimental evidence of quantum effects[14–16]. These defects are intrinsic defects, known as silicon vacancies (VSi)[31–33], divacancies (VSiVC)[34] and carbon antisite-vacancy pair (CSiVC )[35, 36]. In Figures 1-3, we show the atomistic defect structure and the presently understood energy levels corresponding to so far identified quantum systems in 4H, 6H and 3C polytypes. These defects coincide with The closest pair of VSi and carbon vacancy VC, the divacancy VSiVC , can form during the migration of the isolated vacancies. PL arising from VSiVC is attributed to its neutral charge state (VSi*V*<sup>0</sup> <sup>C</sup>) and has several ZPLs in 4H- and 6H-SiC. In 4H-SiC, the VSiVC defects possess four ZPLs (stable up to 1,500◦C) associated to specific PL at 997.5 nm, 1013.6 nm, 1050.7 nm and 1053.9 nm. These ZPLs are related the axial (hh, kk) and basal (hk, kh) location in the lattice (see Figure 2). Other ZPLs in a similar wavelength range have been recently found [38] denominated PL5 (1043 nm) and PL6 (1039 nm) due to their unknown origin. In 6H-SiC, the VSiVC-defect-known ZPLs are at 998.7nm, 1010.9 nm, 1030 nm, 1048.7 nm and 1074.6nm. ZPLs obtained in irradiated 6H samples at 1,139 nm; 1,135 nm; 1,124 nm; 1,108 nm; and 1,093 nm were found to have quantum characteristics similar to the (VSiV0 <sup>C</sup>)[39] and were associated with UD2 defect, previously known in 4H- and 6H-SiC[40, 41].

**Figure 1.** Representation of the atomic structure of the VSi in the SiC lattice in **a** 4H and **b** 6H polytypes, located in different nonequivalent sites (k,h in 4H) and (h, k1,k2 in 6H). **c** Visualisation of the energy levels in the negatively charged state of the VSi for 4H, where the ground state (GS), excited state (ES) and metastable state (MS) structures are visualised, with the ZPL, PSB and spin level of the high spin S=3/2 ground state. A microwave transition in the GS is responsible for the PL enhancement of the ZPL in the presence of a microwave excitation (MW). Both 4H and 6H polytypes containing these defects have been used for quantum control of the ground state spin[16, 37]

In a dual element semiconductor, the antisite-vacancy complex is an intrinsic defect. The defect possesses C3*<sup>v</sup>* symmetry if CSi is along the c-axis (on-axis configurations, CSiVC(kk) and CSiVC(hh)), while it has C1*<sup>h</sup>* symmetry if CSi is out of the c-axis (off-axis configurations, CSiVC(kh) and CSiVC(hk)) in 4H-SiC (see Figure 3**a**). Its PL was found to be in the 648-678 nm range and initially attributed to its neutral charge state[36]. It has been known as AB lines found in both 4H- and 6H-SiC with also different doping. According to recent modelling, the neutral charged state of the CSiVC defect associated to the AB lines should not have any visible PL; therefore, the visible PL is attributed to the positive charge state of this defect with S=1/2. Eight ZPLs were associated with the CSiVC in 4H-SiC, labelled as A1 = 648.7 nm, A2 =651.8 nm, A3 = 665.1 nm, A4=668.5 nm, B1 = 671.7 nm, B2 =673.0 nm, B3 =675.2 nm and B4 = 676.5 nm. The eight AB PL lines in 4H-SiC can naturally account for the four ground-state configurations (hh, kk, hk, kh) where each possesses two ZPLs due to the splitting of the excited state.

#### **3. Single-photon source in bulk material**

Over the past decade, single-photon generation has been observed in many physical systems such as single molecules[42], quantum dots[43, 44], diamond colour centres[45] and others[46, 47]. The generation and detection of single photons play a central role in the foundation of quantum mechanics. Additionally, an efficient and high-quality single-photon

4 Silicon Carbide Devices

excited state.

**3. Single-photon source in bulk material**

**Figure 1.** Representation of the atomic structure of the VSi in the SiC lattice in **a** 4H and **b** 6H polytypes, located in different nonequivalent sites (k,h in 4H) and (h, k1,k2 in 6H). **c** Visualisation of the energy levels in the negatively charged state of the VSi for 4H, where the ground state (GS), excited state (ES) and metastable state (MS) structures are visualised, with the ZPL, PSB and spin level of the high spin S=3/2 ground state. A microwave transition in the GS is responsible for the PL enhancement of the ZPL in the presence of a microwave excitation (MW). Both 4H and 6H

In a dual element semiconductor, the antisite-vacancy complex is an intrinsic defect. The defect possesses C3*<sup>v</sup>* symmetry if CSi is along the c-axis (on-axis configurations, CSiVC(kk) and CSiVC(hh)), while it has C1*<sup>h</sup>* symmetry if CSi is out of the c-axis (off-axis configurations, CSiVC(kh) and CSiVC(hk)) in 4H-SiC (see Figure 3**a**). Its PL was found to be in the 648-678 nm range and initially attributed to its neutral charge state[36]. It has been known as AB lines found in both 4H- and 6H-SiC with also different doping. According to recent modelling, the neutral charged state of the CSiVC defect associated to the AB lines should not have any visible PL; therefore, the visible PL is attributed to the positive charge state of this defect with S=1/2. Eight ZPLs were associated with the CSiVC in 4H-SiC, labelled as A1 = 648.7 nm, A2 =651.8 nm, A3 = 665.1 nm, A4=668.5 nm, B1 = 671.7 nm, B2 =673.0 nm, B3 =675.2 nm and B4 = 676.5 nm. The eight AB PL lines in 4H-SiC can naturally account for the four ground-state configurations (hh, kk, hk, kh) where each possesses two ZPLs due to the splitting of the

Over the past decade, single-photon generation has been observed in many physical systems such as single molecules[42], quantum dots[43, 44], diamond colour centres[45] and others[46, 47]. The generation and detection of single photons play a central role in the foundation of quantum mechanics. Additionally, an efficient and high-quality single-photon

polytypes containing these defects have been used for quantum control of the ground state spin[16, 37]

**Figure 2.** Representation of the atomic structure of the VSiVC in the SiC lattice in **a** 4H and **b** 6H polytypes, located in different nonequivalent sites (k, h in 4H) and (h, k1,k2 in 6H).**c** Visualisation of the energy levels in the neutral state of the (VSi*V*<sup>0</sup> <sup>C</sup>) for 4H, where the ground state (3*A*2), excited state (3*E*) and metastable state (1*A*1) structures are visualised, with the ZPL, PBS and spin level of the high spin S=1 ground state. A microwave transition in the GS is responsible for the PL enhancement of the ZPL in presence of a microwave excitation (MW). Both 4H and 6H polytypes containing these defects have been used for quantum control of the ground state spin [15, 38, 39]

**Figure 3.** Representation of the atomic structure of the CSiVC in the SiC lattice in **a** 4H, located in different nonequivalent sites (k, h in 4H). Visualisation of the energy levels in the positive charge state of the (CSiV<sup>+</sup> <sup>C</sup> ) for 4H, where the ground state (2*A*1) and excited state (2*E*) are visualised, with the ZPLs in the axial **b** and basal **c** defects position [14]

**Figure 4.** Confocal maps of **a** untreated sample that occasionally shows native defects whose origin is yet unclear and **b** confocal map showing irradiated generated single defects with a low temperature annealing of 300 ◦C. The colour code indicates much brighter emitters in the irradiated samples. **c** Experimental set-up.**d** Typical room temperature PL of the SPS. **e** Photon correlation of two SPSs in the irradiated sample excited at 532 and 660 nm. The reduction of photon coincidence at zero delay time below 0.5 indicates the presence of single-photon statistics

source operating at room temperature is needed to ensure secure communication channels via the implementation of protocols of quantum key distribution. SPSs are needed to establish quantum photonics communication networks[48]. At the present, SiC has provided in bulk materials SPS from all the defects discussed in Section 1, isolated in ultrapure 4H-SiC. The first observation of single-photon statistics from SiC was associated with the PL from a single C antisite-vacancy pair. This defect is the brightest single-photon emitter in a bulk solid state system operating at room temperature, showing up to 106counts/s at saturation, indicating a high quantum efficiency and occurring in the region 650-700 nm. The single-photon emission corresponds to a 3-level atomic system, due to the presence of a metastable state. The brightness is associated to the polarisation selection rules of these defects, most of the time parallel to the excitation electric field, as well as to the dipole strength (short radiative lifetime of 1.5 ns). The defect has been isolated using confocal microscopy in electron-irradiated high-purity, semi-insulating (HPSI) SiC along the main axis (1,000) from a 3-inch wafer, containing VC <sup>∼</sup> <sup>10</sup>14/cm3, B<sup>∼</sup> 1014/cm3, N and other defects*<* 1014/cm3. Electron irradiation with energy of 2Mev was used to create defects deeper in the material, and fluences of 1013-1014cm−<sup>3</sup> were used for the single-defect creation. In Figure 4, the confocal maps, experimental set-up, typical PL and photon correlation measured using a Hanbury Brown and Twiss interferometer indicate SPS. PL at room temperature in single emitters was compared to ensemble generated with electron fluences of 1017cm−3, showing high similarity when excited at 532 nm.

10.5772/61166

6 Silicon Carbide Devices

**Figure 4.** Confocal maps of **a** untreated sample that occasionally shows native defects whose origin is yet unclear and **b** confocal map showing irradiated generated single defects with a low temperature annealing of 300 ◦C. The colour code indicates much brighter emitters in the irradiated samples. **c** Experimental set-up.**d** Typical room temperature PL of the SPS. **e** Photon correlation of two SPSs in the irradiated sample excited at 532 and 660 nm. The reduction of photon

source operating at room temperature is needed to ensure secure communication channels via the implementation of protocols of quantum key distribution. SPSs are needed to establish quantum photonics communication networks[48]. At the present, SiC has provided in bulk materials SPS from all the defects discussed in Section 1, isolated in ultrapure 4H-SiC. The first observation of single-photon statistics from SiC was associated with the PL from a single C antisite-vacancy pair. This defect is the brightest single-photon emitter in a bulk solid state system operating at room temperature, showing up to 106counts/s at saturation, indicating a high quantum efficiency and occurring in the region 650-700 nm. The single-photon emission corresponds to a 3-level atomic system, due to the presence of a metastable state. The brightness is associated to the polarisation selection rules of these defects, most of the time parallel to the excitation electric field, as well as to the dipole strength (short radiative lifetime of 1.5 ns). The defect has been isolated using confocal microscopy in electron-irradiated high-purity, semi-insulating (HPSI) SiC along the main axis (1,000) from a 3-inch wafer, containing VC <sup>∼</sup> <sup>10</sup>14/cm3, B<sup>∼</sup> 1014/cm3, N and other defects*<* 1014/cm3. Electron irradiation with energy of 2Mev was used to create defects deeper in the material, and fluences of 1013-1014cm−<sup>3</sup> were used for the single-defect creation. In Figure 4, the confocal maps, experimental set-up, typical PL and photon correlation measured using a Hanbury Brown and Twiss interferometer indicate SPS. PL at room temperature in single emitters was compared to ensemble generated with electron fluences

coincidence at zero delay time below 0.5 indicates the presence of single-photon statistics

of 1017cm−3, showing high similarity when excited at 532 nm.

**Figure 5.** Confocal map of **a** a solid immersion lens (SIL) containing a single VSi defect and the SIL SEM image. **b** PL at room temperature of the VSi.**c** Photon correlation of defect PL in the irradiated sample. The reduction of photon coincidence at zero delay time below 0.5 indicates the presence of single-photon statistic. **d** Photon count rate from a single defect versus excitation power with and without the SIL. Images reproduced with permission from Macmillan Publishers Ltd: Nature Materials [16], copyright (2015)

VSi denoted as V2 lines with ZPL at 917 nm in bulk 4H-SiC has also been isolated [16], using confocal microscopy exciting the substrate by a 730 nm laser. The defect at the single level was created by electron irradiation and low-temperature annealing in vacuum. Due to the geometry of the defect location in the material cut along (1,000) axis, this defect could not be excited with the laser polarisation along to the defect axis, yielding a very low count rate at the single-photon level (15,000counts/s) at saturation. A solid immersion lens of 20 *µ*m diameter was milled using a Ga focussed ion beam in the material to increase the collection efficiency of the single photons, proving an enhancement of a 2.5 factor. Similar results are shown of isolation of this defect in 4H by [17]; in this case, the defect was created using neutron irradiation, and a clear increase of the number of defects with radiation fluences was observed. Similar count rate and PL broad emission in the 900 nm region was observed for the single emitter. A lifetime of 6.1 ns was determined and perfect photo-stability was observed. In Figure 5, we show the main properties of this defect as a SPS.

Divacancies were also isolated from 120 *µ*m 4H-SiC single-crystal epitaxial film grown on an n-type 4H-SiC substrate. The substrate was grown by hotwall chemical vapour deposition, a technique used to create commercial quality, multilayer electronic structures at the wafer scale. The epilayer is optimised to have no basal plane dislocations or polytype inclusions and a very low (5 1013cm−3) unintentional dopant density. The epilayer was mechanically separated from the substrate, polished and diced and then irradiated with 2 MeV electrons at a range of fluences 5 <sup>×</sup>1012 cm−<sup>2</sup> to 1015cm−2. Annealing was used to achieve the migration of the vacancy to form the defects. Superconducting nanowire-based single-photon detectors able to detect the infrared emission were integrated into a home-built confocal microscope.

**Figure 6.** Confocal map of **a** a 4H-SiC membrane irradiated at 10<sup>13</sup> cm−<sup>3</sup> electron fluence. PL is collected by a confocal at a depth of 20 *µ*m at a temperature of 20 K. PL spots were mostly identified as divacancies, though not all bright spots correspond to isolated single defects. **b** Photo-correlation *g*(2)(*τ*) measurements for single divacancy defects located corresponding to (hh), (kk) and (kh) sites. Fits to a simple two-level model are shown. Images reproduced with permission from Macmillan Publishers Ltd: Nature Materials [15], Copyright (2015)

Excitation was performed with 975 nm continuous-wave laser. The sample was cooled to 20 K to observe distinct bright spots in a scanning PL image, as shown in Figure 6. The optical lifetimes of the neutral divacancies is 14±3 ns. The measured count rates were very low in the range of 3000-5000 counts/s, due to detector losses (∼ 28% detection efficiency) in the spectral region of their ZPLs and the low collection efficiency from low NA objective in the cryostat. In addition, because of a high background due to polishing artifacts it was required to focus deep (20 *µ*m) below the SiC surface to observe isolated single emitters, which added another 20-30% optical losses.

#### **4. Single-photon sources in nanomaterials**

SiC nanomaterial scientific interest is motivated by the material larger potentials at the nanoscale in optoelectronics as an efficient ultraviolet emitter. SiC nanomaterial has also generated interest for its biocompatibility in nanomedicine or as emitting nanoprobes for imaging[49–51]. PL spectra of SiC nanostructures and nanopowder have been largely studied. The most common PL origin due to subgap emission is radiative recombination of defects and surface states[52], while above-gap emission is attributed to quantum confinement phenomenon in small nanocrystals such as quantum dots (QDs). At present the peak emission wavelengths of the SiC QDs are in the UV-blue-green region, typically between 380 nm and 550 nm[53–56]. This spectral emission region, however, is not ideal for biomedical applications due to the cell autofluorescence in the same spectral band. Additionally, infrared would be desirable for in-depth biological tissue imaging.

Recently the first demonstration of a deep defect within the bandgap has been shown in SiC nanocrystals obtained from 3C polytype[18], showing an emission in the red spectral region (650 nm). This red emission has been demonstrated to emit single photons. Two sources of SiC nanoparticles were explored: commercial 3C SiC nanomaterial with an average

8 Silicon Carbide Devices

**Figure 6.** Confocal map of **a** a 4H-SiC membrane irradiated at 10<sup>13</sup> cm−<sup>3</sup> electron fluence. PL is collected by a confocal at a depth of 20 *µ*m at a temperature of 20 K. PL spots were mostly identified as divacancies, though not all bright spots correspond to isolated single defects. **b** Photo-correlation *g*(2)(*τ*) measurements for single divacancy defects located corresponding to (hh), (kk) and (kh) sites. Fits to a simple two-level model are shown. Images reproduced with

Excitation was performed with 975 nm continuous-wave laser. The sample was cooled to 20 K to observe distinct bright spots in a scanning PL image, as shown in Figure 6. The optical lifetimes of the neutral divacancies is 14±3 ns. The measured count rates were very low in the range of 3000-5000 counts/s, due to detector losses (∼ 28% detection efficiency) in the spectral region of their ZPLs and the low collection efficiency from low NA objective in the cryostat. In addition, because of a high background due to polishing artifacts it was required to focus deep (20 *µ*m) below the SiC surface to observe isolated single emitters, which added

SiC nanomaterial scientific interest is motivated by the material larger potentials at the nanoscale in optoelectronics as an efficient ultraviolet emitter. SiC nanomaterial has also generated interest for its biocompatibility in nanomedicine or as emitting nanoprobes for imaging[49–51]. PL spectra of SiC nanostructures and nanopowder have been largely studied. The most common PL origin due to subgap emission is radiative recombination of defects and surface states[52], while above-gap emission is attributed to quantum confinement phenomenon in small nanocrystals such as quantum dots (QDs). At present the peak emission wavelengths of the SiC QDs are in the UV-blue-green region, typically between 380 nm and 550 nm[53–56]. This spectral emission region, however, is not ideal for biomedical applications due to the cell autofluorescence in the same spectral band.

Recently the first demonstration of a deep defect within the bandgap has been shown in SiC nanocrystals obtained from 3C polytype[18], showing an emission in the red spectral region (650 nm). This red emission has been demonstrated to emit single photons. Two sources of SiC nanoparticles were explored: commercial 3C SiC nanomaterial with an average

Additionally, infrared would be desirable for in-depth biological tissue imaging.

permission from Macmillan Publishers Ltd: Nature Materials [15], Copyright (2015)

**4. Single-photon sources in nanomaterials**

another 20-30% optical losses.

**Figure 7.** Representation of the atomic structure of the CSiVC in the 3C-SiC lattice in **a**. **b** Visualisation of the energy levels in the double-positive charge state of the (CSiV2<sup>+</sup> <sup>C</sup> ) for 3C, where the ground state and excited state are visualised. The defect ZPL is around 648 nm from ensemble measurements (not clearly observed at the single level at room temperature).**c** Experimental set-up used to study the 3C-SiC nanoparticle defect SPS and room temperature PL measured from SPS [18]

size of 45 nm suspended in ethanol and large (size: 200-500nm) in-house synthesised SiC nanocrystals suspended in MilliQ, dried on glass cover slip[57]. A room temperature custom-built confocal microscope combined with an atomic force microscope (Figure 7**c**) was used to correlate the size of the nanocrystals with PL, while photon correlation was used to determine the quantum properties of the PL. Low-temperature Raman spectroscopy and cathodoluminescence were used to aid the study of the origin of the SPS PL in 3C nanocrystals, indicating that the PL was not due to surface defects. A distinctive ZPL was observed at 648 nm at 80 K from ensemble measurements. A CW laser pump at 532 nm was used to excite the samples, while a pulsed 532 nm laser was used to measure the fluorescence lifetime, which results in the range of (2 ÷ 5.3)±0.2 ns, depending on the treatment. Some nanocrystals provided SPSs with partial polarisation in absorption and emission. We tentatively attributed the defect responsible for SPS in 3C to the carbon antisite-vacancy pair by comparing to ensemble low-temperature PL in bulk 3C heavily irradiated sample. This defect has C3*<sup>v</sup>* symmetry in 3C-SiC lattice (see Figure 7**a**). Because of the relatively small bandgap of 3C-SiC, the double-positive charge state was considered as possible candidates for the PL. The calculated (2+→+) charge transition level is at 1.95 eV which is very close to the ZPL energy of the bulk material defect ZPL.

SPS has also been observed in SiC nanotetrapods[19]. The tetrapod crystal phase structure consists of 3C core and 4H arms. The coexistence of 3C and 4H polytypes in these nanostructures led first to the observation of PL in the spectral region between 650 and 780 nm, not observed before in SiC nanostructures. This has been understood as a new quantum confined system accessible at room temperature. In this case, the quantum confinement and the nonclassical emission originated from the homogeneous heterostructure of 3C core and 4H legs, forming a quantum well in SiC nanotetrapod. The schematic of the SiC tetrapods

**Figure 8. a** Schematics of the tetrapod structure where the diameter of 3C core is *d*3*C*. Top: Band line-up for 4H/3C/4H-SiC heterostructures for the ideal symmetry case T*d*. Bottom: Quantum confinement model of SiC tetrapods when an asymmetric structure is considered and a polarisation potential change on both legs is ∆*V*=0.4 eV. **b** Scanning electron microscope of grown tetrapods. Every tetrapod has an average leg length of ∼ 100 nm. Inset: exemplary PL form a single tetrapod corresponding to an SPS.**c** Measured ZPL central emission for SPS in single nanotetrapods. **d** Calculated emission wavelengths from this model where ∆*V* is the potential difference along the arms and *rcore* is the radius of the 3C core, respectively. The steep potential curve with a height of ∆*V* arises from the different lengths of the 4H-SiC legs of a tetrapod[19]

is shown in Figure 8, accompanied by a high-resolution scanning electron microscope (SEM) image of the tetrapods. The nanotetrapods were measured to have an average leg length of 100 nm and leg diameter smaller than 50 nm, while the core was estimated as small as several nanometres. The possible band structure in SiC tetrapods is analysed by means of quantum mechanical simulations on a simplified model. The exciton is confined along the quasi one-dimensional potential curve created by 4H(leg)- 3C(core)- 4H(leg) structure. The emission wavelength of the individual tetrapods depends on their geometry, particularly, on their global symmetry, and much less on the diameter of 3C core (Figure 8 **c**). If the length of 4H legs was the same for all tetrapods (global T*<sup>d</sup>* symmetry), then a classical rectangular quantum well forms for the electrons in the conduction band (0.92 eV) and a minor potential barrier for the holes in the valence band (0.05 eV), so that the potential curve does not show any steepness (∆*V* = 0) (Figure 8 **a** (top)). The symmetric tetrapods should show no polarisation of light. However, if the length of the 4H legs was different (i.e. not all the legs have the same length) in a SiC tetrapod, then this induces different polarisations of surface charges at the end of 4H legs in these tetrapods, so a steep potential curve ( ∆*V >* 0) both for the electrons and holes in the conduction and valence band edges (Figure 8 **a**(bottom)). This effect creates a triangular potential well for the electron in the conduction band and starts to push the hole away from 3C region.

10.5772/61166

**Figure 9. a** Schematic of the optical set-up used to measure the ODMR signal. **b** Energy-level diagram of a spin system with a quartet ground state based on the VSi [16, 37]. *D* and *De* denote the zero-field splitting of the ground singlet state and the excited state, respectively. The population of the spin substate levels is indicated by the grey circles. Further details in the text

#### **5. Optical control of spin state**

10 Silicon Carbide Devices

230 Advanced Silicon Carbide Devices and Processing

the 4H-SiC legs of a tetrapod[19]

band and starts to push the hole away from 3C region.

**Figure 8. a** Schematics of the tetrapod structure where the diameter of 3C core is *d*3*C*. Top: Band line-up for 4H/3C/4H-SiC heterostructures for the ideal symmetry case T*d*. Bottom: Quantum confinement model of SiC tetrapods when an asymmetric structure is considered and a polarisation potential change on both legs is ∆*V*=0.4 eV. **b** Scanning electron microscope of grown tetrapods. Every tetrapod has an average leg length of ∼ 100 nm. Inset: exemplary PL form a single tetrapod corresponding to an SPS.**c** Measured ZPL central emission for SPS in single nanotetrapods. **d** Calculated emission wavelengths from this model where ∆*V* is the potential difference along the arms and *rcore* is the radius of the 3C core, respectively. The steep potential curve with a height of ∆*V* arises from the different lengths of

is shown in Figure 8, accompanied by a high-resolution scanning electron microscope (SEM) image of the tetrapods. The nanotetrapods were measured to have an average leg length of 100 nm and leg diameter smaller than 50 nm, while the core was estimated as small as several nanometres. The possible band structure in SiC tetrapods is analysed by means of quantum mechanical simulations on a simplified model. The exciton is confined along the quasi one-dimensional potential curve created by 4H(leg)- 3C(core)- 4H(leg) structure. The emission wavelength of the individual tetrapods depends on their geometry, particularly, on their global symmetry, and much less on the diameter of 3C core (Figure 8 **c**). If the length of 4H legs was the same for all tetrapods (global T*<sup>d</sup>* symmetry), then a classical rectangular quantum well forms for the electrons in the conduction band (0.92 eV) and a minor potential barrier for the holes in the valence band (0.05 eV), so that the potential curve does not show any steepness (∆*V* = 0) (Figure 8 **a** (top)). The symmetric tetrapods should show no polarisation of light. However, if the length of the 4H legs was different (i.e. not all the legs have the same length) in a SiC tetrapod, then this induces different polarisations of surface charges at the end of 4H legs in these tetrapods, so a steep potential curve ( ∆*V >* 0) both for the electrons and holes in the conduction and valence band edges (Figure 8 **a**(bottom)). This effect creates a triangular potential well for the electron in the conduction Spin-dependent luminescence can be used to study magnetic and hyperfine parameters for excited states of defects in SiC. A wealth of knowledge about the atomic origin of defects and their properties has been extracted from such optical measurements. More recently, with the emergence of quantum information processing technologies, optical methods have been developed to coherently control and read out the spin of a defect centre. Figure 9**a** shows a schematic of a basic set-up often used to measure spin-dependent luminescence in SiC by the optically detected magnetic resonance (ODMR) technique. The main components are the excitation laser, a dichroic mirror and a diode to collect the filtered light in the spectral region of interest. A microwave carrying wire lays in close proximity to the probed defects, and an external magnetic field may also be applied. The electron paramagnetic resonance (EPR) spectrum is recorded by monitoring the PL intensity, while the frequency of the applied microwave excitation is varied. Figure 9 **b** shows an example of an energy-level scheme for a defect (based on the VSi [16, 37]). Firstly, the defect is optically excited. In this system, intersystem crossing (MS) causes the higher-lying spin sublevel of the ground state (*ms* = ±3/2) to be preferentially populated. When resonance with an allowed EPR transition occurs on the application of a microwave field, such as |*ms* = ±3/2→|*ms* = ±1/2, the steady-state population of the sublevels is redistributed. This leads to an enhanced singlet ground-state absorption and an increase in the PL intensity. Decreases in PL can also be observed depending on the relative values of the populating and decay rates. ODMR has only been observed for a limited number of systems, most notably for single NV centres in diamond [58] and more recently single *V*Si [16] and *V*Si*V*<sup>C</sup> [15] centres in SiC which will be discussed further below. Optically induced alignment (polarisation) of the ground-state spin sublevels of the VSi in 4H- and 6H-SiC was observed recently for the first time at room temperature [59, 60]. The alignment schemes vary depending on the crystal polytype and crystallographic position of VSi in the crystal lattice, as well as their zero-field splitting parameters. For 6H-SiC, the zero-field splitting parameter of VSi is 9 <sup>×</sup> <sup>10</sup>−<sup>4</sup> cm−<sup>1</sup> (26.9 MHz for the *<sup>k</sup>*-site) and 42.8 <sup>×</sup> <sup>10</sup>−<sup>4</sup> cm−<sup>1</sup> (128.3 MHz for the *<sup>h</sup>*-site), while for 4H, it was found

to be 22 <sup>×</sup> <sup>10</sup>−<sup>4</sup> cm−<sup>1</sup> (65.9 MHz for the *<sup>h</sup>*-site). The spin states of the UD-2 lines have recently been optically addressed and coherently controlled [38, 39]. In this work, with the four UD-2 lines labelled as PL1-PL4, the spin-1 ground state of each line was investigated as well as a pair of defect spin states of unidentified origin (PL5 and PL6). Room temperature Hahn echo measurements of these latter two defects was demonstrated with *T*∗ <sup>2</sup> times of 214 ns and 1248 ns, respectively, similar to the *VSi* defect. The spin coherence times were found to be comparable to those of the NV in diamond[61]. Such measurements have been performed in 3C, 4H and 6H polytypes with defects existing in the as-grown material or those formed by ion implantation [39]. The UD-2 family of PL lines in 6H-SiC also show ODMR signals and are labelled QL1-QL6. The QL1 line is associated with a spin system with a zero-field splitting of 1.299 GHz. In contrast to conventional EPR where the transverse magnetisation of a large spin ensemble is detected, ODMR can have single spin sensitivity due to linking weakly allowed magnetic dipole transitions to highly allowed electric dipole emission processes. Optically addressing and coherently controlling the spin state of single defect is a potential basis for quantum information and nanoscale sensing applications. This has recently been demonstrated [15, 16] by using a range of pulsed ODMR techniques. Many of the detection and pulse sequences developed for EPR can be applied to ODMR experiments with minor modifications. Such measurements have allowed unprecedented insight into the spin of defects at the ensemble concentration level and now to the single-defect level. Figure 10 shows two ODMR modes of operation as applied to a single *V*Si defect in SiC [16]. For this centre, spin transitions between ground state sublevels are induced by the microwave excitation giving rise to an enhancement of the PL intensity (Figure 10a and b). The line width is 6 MHz and is limited by the inhomogeneous spin coherence time *T*∗ <sup>2</sup> with laser and microwave power broadening effects superimposed. Pulsed methods can be used to circumvent this. Figure 10c shows a simple sequence of pulses that can be used to measure the Rabi oscillations, the characteristic signature of a coherent system interacting with an electromagnetic field. Oscillations reflect the behaviour of a population of an excited state as a function of the input pulse area or qubit rotations. The microwave frequency is set to resonance and the oscillation period is proportional to the microwave field strength. The largest Rabi frequency measured was 8.4 MHz (*B*<sup>1</sup> = 0.16 mT), corresponding to a *π*/2 rotation in about 30 ns. Interactions of the spin system with its environment cause a relaxation of polarisation and coherence and are characterised by two time constants, the longitudinal time *T*<sup>1</sup> (spin-lattice relaxation time) and the transverse relaxation time *T*<sup>2</sup> (spin-spin relaxation time). Long spin coherence is essential for quantum information and sensing applications. Using a Hahn-echo pulse sequence (*π*/2 − *τ* − *π* − *τ* −projection), Widmann *et al.* placed a lower bound to the spin coherence time of 160 *µ*s and an upper bound of 1 ms, limited by the spin relaxation time. The accuracy was limited by modulations in the signals possibly due to hyperfine coupling to a 29Si nuclear spin close by. These long coherence times collected at room temperature are an indication that SiC is a promising platform for quantum technologies. The main issues are the weak PL intensities (40 kcts/s when integrated with a solid immersion lens) and the poor ODMR contrast (*<* 1%). Christle et al.[15] report the coherent control of the electronic spin of individual neutral divacancies with emission in the NIR compatible with telecommunication wavelengths. At a temperature of 20 K, a coherence time of 1.2 ms was obtained. The inhomogeneous spin dephasing time, *T*∗ <sup>2</sup> , measured by a Ramsey pulse sequence, *π*/2 − *τ* − *π*/2, was found to be up to 4.4 *µ*s. These were longer than that observed earlier for ensembles [38]. A spin coherence time of 1.2 ms was also deduced for a spin ensemble rather than on a single-defect level owing to

10.5772/61166

*B*1 (G)

0.8

Fixed

−0.4 0.4 0.0 Echo intensity

−0.4

0.4 0.0 Echo intensity

(%)

(%)

**Methods**

0 20 40 60 80

0 50 100

Free precession time (µs)

Hahn-echo pulse scheme

τ' Laser π/2 π Projection Laser

τ

Time

Free precession time (µs)

**Experimental set-up.** For the creation of single defects, commercial on-axis high-purity semi-insulating 4H–SiC substrates were irradiated by 2 MeV electrons with a fluence of 1013–5 ⇥ 1014 cm−<sup>3</sup> along the *c*-axis of the SiC crystal. The concentration of the created silicon vacancy centres is linearly dependent on the electron flux (Supplementary Information). Several SILs of various sizes were created on a 6⇥1013 cm−<sup>3</sup> irradiated sample by ion milling using a 40 keV Ga focused ion beam. A SIL with 20 µm diameter was used in this report. A bright emission layer near the surface was found using a confocal fluorescence microscope after ion milling. Optical identification of the defect centres created was possible only after this damaged layer was removed (Supplementary Information). A typical home-built confocal set-up was used after optimizing for emission in the wavelength range around 900 nm. Polarization optics were also added to suppress the crosstalk due to the breakdown flash of silicon avalanche photodiodes (APDs) which arises at around 900 nm (Supplementary Information). The excitation laser wavelength used to collect all the data presented in this report was 730 nm. For spin manipulation, the RF field was irradiated via a 20 µm diameter copper wire placed over the sample surface. For continuous wave ODMR, as in Fig. 3c,d, RF irradiation was applied continuously for 20 ms at each frequency and the frequency was changed in 1 MHz steps. All experiments were done at room temperature. Further details of the methods can

**Estimation of the effective nuclear spin bath concentration.** The nuclear spin concentration of diamond is determined by the natural abundance of 13C (1.1%)—that is, *⇢*diamond =*⇢*13. In SiC, taking into account two independent nuclear spin baths, the effective nuclear spin bath concentration is estimated as *⇢*SiC =0.5⇥*⌘<sup>V</sup> (⇢*<sup>13</sup> +*⇢*<sup>29</sup> ⇥*⌘γ )*. Here, *⇢*<sup>29</sup> =4.7% is the natural abundance of 29Si.

SiC as compared to diamond, with *d*Si−<sup>C</sup> =1.88Å and *d*<sup>C</sup>−<sup>C</sup> =1.54Å being the Si–C and C–C bond lengths in SiC and diamond, respectively. The smaller

nuclear spin flip-flop rate between 29Si nuclei. With these numbers, the effective nuclear spin concentration of SiC is similar to that of diamond—that is, *⇢*SiC*/⇢*diamond ⇡1. Consequently, the SiC nuclear spin bath should give a similar electron spin decoherence rate to that of 13C in diamond. The estimation is consistent with more detailed numerical calculations based on the cluster expansion method, which predicts a very long coherence time, of as much as

), yielding *⌘γ* =*(γ*29*/γ*13*)*

<sup>3</sup> =0.55 describes the unit cell volume expansion of

) compared to that of 13C

<sup>2</sup> =0.63, accounts for the smaller

*B*0 = 288 G

*B*0 = 270 G

150 200

100

. The same sequence is repeated by

0.4 0.8 1.2 1.6

SiC nuclear spin bath than, for example, in diamond. However,

further decrease the effective nuclear spin bath concentration. In total, the effective nuclear spin bath concentration in SiC is fairly similar to that in diamond and one would expect a couple of hundred µs, and even up to an order of milliseconds for *T*<sup>2</sup> (see Methods and Supplementary Information). Suppression of such decoherence can be achieved by diluting the remaining nuclear spin bath in isotopically purified host crystals, which have become available recently29. The electron spin coherence time in solids is also influenced by an electron spin bath of surrounding electron paramagnetic impurities. For example, the *T*<sup>2</sup> of nitrogen-vacancy centres in diamond can be significantly shortened to a few µs when the concentration of electron paramagnetic impurities is high30. The sample used in this study already contains a considerable amount of impurities—that is, N and B impurities up to 5⇥1015 cm−<sup>3</sup> (ref. 31). It also contains a variety of intrinsic point defects even before irradiation, such as carbon vacancies32, carbon vacancy-antisite pairs21 and divacancies9,32 which have electronic spins of 1/2 or 1 and concentrations up to approximately ⇠3–6 ⇥ 1015 cm−<sup>3</sup> (ref. 32).

, as well as other

). A major challenge in the present

, the Zeeman energy difference is larger than

**4 NATURE MATERIALS** | ADVANCE ONLINE PUBLICATION | www.nature.com/naturematerials

be found in the Supplementary Information.

gyromagnetic ratio of 29Si (*γ*<sup>29</sup> =2⇡⇥0.85 kHz G−<sup>1</sup>

milliseconds (Supplementary Information; ref. 27).

The ratio *⌘<sup>V</sup>* =*(d*<sup>C</sup>−<sup>C</sup>*/d*Si−<sup>C</sup>*)*

(*γ*<sup>13</sup> =2⇡⇥1.07 kHz G−<sup>1</sup>

simplicity. **b**, Calculated energy eigenvalues, expressed in frequency units, of each spin sublevel as a function of the axial *B*<sup>0</sup> field strength. **c**, ODMR spectrum of a single *T*V2a centre at |*B*0|=50G, with *B*<sup>0</sup> k*c*-axis (*✓* =0±4◦). Black dots: measured data expressed as a relative fluorescent intensity (=*1*PL*/*PLo, where PLo is the PL intensity o-resonance). Red curves: Lorentzian fit with full-width at half-maximum (FWHM) ⇡ 6 MHz. **d**, Experimentally obtained frequency dependence of ODMR lines with axial *B*0. Red curves are based on calculations for the allowed transitions using **Figure 4 | Room-temperature coherent spin manipulation of a single** *T***V2 centre in 4H–SiC. a**, Pulse sequence for detecting spin Rabi oscillations (see text). **b**, Measured Rabi frequencies (*f*Rabi), extracted from **c**, and converted RF field (*B*1) strength versus the square root of the total RF power (*P*RF) applied to the wire. For conversion, *<sup>f</sup>*Rabi <sup>=</sup>p3*gµ*B*B*1*/<sup>h</sup>* is used22. The red line is a linear fit. **<sup>c</sup>**, Spin Rabi oscillations of the <sup>|</sup>*m*<sup>s</sup> =+3*/*2i\$|*m*<sup>s</sup> =+1*/*2<sup>i</sup> transition of a single *T*V2a centre at |*gµ*B*B*0,*z*|⇡4*D*⇡50G and various field strengths *B*1. The spin signal is obtained by integrating the photon counts in the first 60–120 ns of the fluorescence response to the readout laser pulse. Red curves: exponentially decaying sinusoidal fits. The numbers indicate the extracted Rabi frequencies, which are linearly dependent on the *B*<sup>1</sup> field strength as shown in **b**. **d**, Hahn-echo decay at |*B*0,*z*|⇡270 and 288 G. Top: pulse **Figure 10. a** Schematic of the continuous wave ODMR method with the microwave frequency varied while the PL is measured. **b** Pulse sequence used to detect spin Rabi oscillations. **b** ODMR spectrum of the VSi in a magnetic field of 50 G parallel to the c-axis. **d** Spin Rabi oscillations of the |*ms* = +3/2→|*ms* = +1/2 transition of a single VSi for various field strengths *B*1. **c** and **d** reprinted by permission from Macmillan Publishers Ltd: Nature Materials 14, 164, copyright (2015)[16]

presumably spin-dependent, resulting in GS spin polarization. For the fit functions in Fig. 2b,d, ES and GS are assumed to consist of a single state for

equation (1). Dashed red line: expected |*m*<sup>s</sup> =−1*/*2i\$|*m*<sup>s</sup> =−3*/*2i transition (see text). ⇡ 13 MHz). The observed resonance frequencies (Fig. 3d) are in good agreement with predictions for *T*V2a using equation (1) (Fig. 3b and Supplementary Information). However, the observed signal at zero magnetic field reveals further fine structure. We also observed a similar structure from a *T*V2a ensemble (Supplementary Information). Such fine structure at zero field cannot be explained by our spin Hamiltonian, even with the known hyperfine coupling to 29Si and 13C, and is still under investigation. We proceeded to test the room-temperature spin coherence of a single *T*V2a at |*B*0,*<sup>z</sup>* | ≥ 50 G. We chose two states, |*m*<sup>s</sup> = +3*/*2i and |*m*<sup>s</sup> = +1*/*2i, to measure coherent spin dynamics (Supplementary Information). To demonstrate the coherent manipulation of a single electron spin in SiC, we first established optical polarization into |*m*<sup>s</sup> = +1*/*2i by applying a 400 ns laser pulse followed by a 600 ns as a lower bound for *T*2. The upper bound is given by the electron spin relaxation *T*1, which we measured to be *T*<sup>1</sup> ⇡ 500 µs (Supplementary Information). Hence as the upper limit we expect *T*<sup>2</sup> to be around 1 ms (Supplementary Information). If not limited by spin–phonon interactions, magnetic fluctuations arising from surrounding nuclear and electron spin baths are the two main sources of decoherence. Because the silicon vacancy electron spin is highly localized around the defect8 , its coupling to the bath nuclear spins is mainly of a dipolar form. The coherence time due to the dipolar coupled bath spins is inversely proportional to the bath spin concentration28. In SiC, two types of nuclear spin species, namely, 29Si and 13C (with natural abundance 4.7% and 1.1%, respectively), form the nuclear spin bath. Because of the higher abundance of 29Si than 13C, intuitively, one may expect faster decoherence in a sequence consisting of ⇡*/*2 and ⇡ pulses separated by *⌧* , and an additional ⇡*/*2 for projection after another delay *⌧* 0 replacing the last ⇡*/*2 pulse with a 3⇡*/*2 pulse. The dierence between the two data, normalized by their average, is plotted as an echo intensity to remove any contribution from unknown relaxation processes. Middle and bottom: the measured Hahn echo at 288 and 270 G, respectively. The blue curve shows the simulated Hahn echo modulated by the coupling to a proximal 29Si nuclear spin (Supplementary Information). Assuming that the central spin is coupled to the bath electron spins via dipole–dipole interactions with an electron spin concentration of around 1016 cm−<sup>3</sup> , we estimate the decoherence time in the given sample to be of the order of 100 µs (Supplementary Information). This decoherence mechanism can be suppressed by applying high magnetic fields30 as well as dynamical decoupling33. Reducing the common residual B acceptor and N donor in chemical vapour deposition (CVD)-grown layers to 1013–1014 cm−<sup>3</sup> while retaining n-type conductivity, which is necessary for the formation of the negatively charged Si vacancy, by optimizing growth conditions and using modified CVD growth methods, is common nowadays34,35. The most abundant intrinsic defects in as-grown SiC CVD layers are limitations in their photon collection efficiency. This duration is remarkably long and much greater than that found for the NV centre in isotropically pure diamond [61]. In addition, still greater spin coherence times might be achieved if the SiC is also isotropically purified [62]. This result may be counterintuitive since the natural abundance of 29Si is greater than 13C. Theoretical calculations attribute this phenomenon to three factors: the longer bond length in SiC, the smaller gyromagnetic ratio of 29Si and the suppression of heteronuclear spin pair flip-flop processes in the strong magnetic field regime [63]. Long-lived spin coherence is essential to implement quantum information and sensing technologies; in SiC, it seems to be a common feature of the spins in all three polytypes. Single-spin coherent control has been achieved for both the VSi and VSiVC centres. Although the NV centre in diamond dominates this field, SiC shows some advantages being compatible with standard device processing protocols, available in high-quality 3-inch wafers and available in a wide range of polytypes. SiC-based devices in which single spins act as the active device element may be employed in emerging quantum technologies.

#### is complete. We then applied a rectangular RF pulse resonant to the |*m*<sup>s</sup> =+3*/*2i\$|*m*<sup>s</sup> =+1*/*2i transition, followed by an identical as the gyromagnetic ratio difference between two nuclear spin types is ⇠150 Hz G−<sup>1</sup> 1012 cm−<sup>3</sup> range without creating Si vacancies at detectable levels, by controlling the Si/C ratio of precursor gases. Such defect reduction **6. Photonics nanocavities and micro-cavities**

delay to ensure that the decay from the shelving state to the GS

SiC, we recorded Hahn-echo decays at *B*<sup>0</sup> ⇡ 270 and 288 G. As before, we used a 400 ns laser pulse for polarization and readout before and after the projective Hahn-echo sequence, respectively (Fig. 4d). An apparent feature is the strong envelope modulation (Fig. 4d), which we attribute to hyperfine coupling to a proximal 29Si nuclear spin at a close distance (for example, ⇠1 nm) from the defect electron spin (Supplementary Information; refs 9,15,25–27). In Fig. 4d the middle panel (*B*<sup>0</sup> ⇡288 G) shows a distinctly different modulation pattern, with modulation frequencies different from the lower panel (*B*<sup>0</sup> ⇡270 G). In both cases the data quality and the complex modulation pattern do not allow one to determine a conclusive decoherence time. The data set in the lower panel (*B*<sup>0</sup> ⇡ 270 G) also shows envelope modulations whose dominant modulation frequency is similar to the theoretical prediction. Although the observed curve still shows beating patterns, which is not predicted by our model and may be due to the misalignment of the applied *B*<sup>0</sup> field, we note that the maximum amplitude is restored at around 160 µs. Therefore, 160 µs should be considered

**c**

12 Silicon Carbide Devices

coherence time *T*∗

*T*∗

to be 22 <sup>×</sup> <sup>10</sup>−<sup>4</sup> cm−<sup>1</sup> (65.9 MHz for the *<sup>h</sup>*-site). The spin states of the UD-2 lines have recently been optically addressed and coherently controlled [38, 39]. In this work, with the four UD-2 lines labelled as PL1-PL4, the spin-1 ground state of each line was investigated as well as a pair of defect spin states of unidentified origin (PL5 and PL6). Room temperature

214 ns and 1248 ns, respectively, similar to the *VSi* defect. The spin coherence times were found to be comparable to those of the NV in diamond[61]. Such measurements have been performed in 3C, 4H and 6H polytypes with defects existing in the as-grown material or those formed by ion implantation [39]. The UD-2 family of PL lines in 6H-SiC also show ODMR signals and are labelled QL1-QL6. The QL1 line is associated with a spin system with a zero-field splitting of 1.299 GHz. In contrast to conventional EPR where the transverse magnetisation of a large spin ensemble is detected, ODMR can have single spin sensitivity due to linking weakly allowed magnetic dipole transitions to highly allowed electric dipole emission processes. Optically addressing and coherently controlling the spin state of single defect is a potential basis for quantum information and nanoscale sensing applications. This has recently been demonstrated [15, 16] by using a range of pulsed ODMR techniques. Many of the detection and pulse sequences developed for EPR can be applied to ODMR experiments with minor modifications. Such measurements have allowed unprecedented insight into the spin of defects at the ensemble concentration level and now to the single-defect level. Figure 10 shows two ODMR modes of operation as applied to a single *V*Si defect in SiC [16]. For this centre, spin transitions between ground state sublevels are induced by the microwave excitation giving rise to an enhancement of the PL intensity (Figure 10a and b). The line width is 6 MHz and is limited by the inhomogeneous spin

<sup>2</sup> with laser and microwave power broadening effects superimposed. Pulsed

methods can be used to circumvent this. Figure 10c shows a simple sequence of pulses that can be used to measure the Rabi oscillations, the characteristic signature of a coherent system interacting with an electromagnetic field. Oscillations reflect the behaviour of a population of an excited state as a function of the input pulse area or qubit rotations. The microwave frequency is set to resonance and the oscillation period is proportional to the microwave field strength. The largest Rabi frequency measured was 8.4 MHz (*B*<sup>1</sup> = 0.16 mT), corresponding to a *π*/2 rotation in about 30 ns. Interactions of the spin system with its environment cause a relaxation of polarisation and coherence and are characterised by two time constants, the longitudinal time *T*<sup>1</sup> (spin-lattice relaxation time) and the transverse relaxation time *T*<sup>2</sup> (spin-spin relaxation time). Long spin coherence is essential for quantum information and

Widmann *et al.* placed a lower bound to the spin coherence time of 160 *µ*s and an upper bound of 1 ms, limited by the spin relaxation time. The accuracy was limited by modulations in the signals possibly due to hyperfine coupling to a 29Si nuclear spin close by. These long coherence times collected at room temperature are an indication that SiC is a promising platform for quantum technologies. The main issues are the weak PL intensities (40 kcts/s when integrated with a solid immersion lens) and the poor ODMR contrast (*<* 1%). Christle et al.[15] report the coherent control of the electronic spin of individual neutral divacancies with emission in the NIR compatible with telecommunication wavelengths. At a temperature of 20 K, a coherence time of 1.2 ms was obtained. The inhomogeneous spin dephasing time,

<sup>2</sup> , measured by a Ramsey pulse sequence, *π*/2 − *τ* − *π*/2, was found to be up to 4.4 *µ*s. These were longer than that observed earlier for ensembles [38]. A spin coherence time of 1.2 ms was also deduced for a spin ensemble rather than on a single-defect level owing to

sensing applications. Using a Hahn-echo pulse sequence (*π*/2 − *τ* − *π* − *τ*

<sup>2</sup> times of

−projection),

Hahn echo measurements of these latter two defects was demonstrated with *T*∗

laser pulse for readout. This sequence (Fig. 4a) was repeated while increasing the RF pulse length up to 3 µs. The result (Fig. 4c) shows long-lived spin Rabi oscillations. The expected linear dependence of the Rabi frequency on the *B*<sup>1</sup> field strength is confirmed in Fig. 4b. To quantify electron spin coherence of a single spin in the typical dipolar coupling between nuclear spins (⇠100 Hz) at the given magnetic field strength. Hence, nuclear spin flip-flops are greatly suppressed. As a result, 29Si and 13C nuclear spins behave as two independent spin baths. Furthermore, the large Si–C bond length in SiC and small gyromagnetic ratio of 29Si in CVD layers can lower the electron spin dipolar coupling strength by up to three orders of magnitude. Thus, diluting the electron spin bath concentration is a further option. Our results show that SiC can host single-point defects with long spin coherence times, making it promising for long-lived qubits. This applies not only to the specific point defect used in this study, Spontaneous emission from an SPS can be enhanced if the defect or an equivalent 2-level system is placed inside a cavity. The magnitude of the enhancement depends on the coupling (*g*) between the cavity and the atom's emission modes. The enhancement of the spontaneous emission of a dipole in a cavity is the Purcell factor, given by *F* =

and transition metal defects7

single quantum system.

carbon vacancies, whose concentration can also be reduced to the

but also to other deep defect qubit candidates in SiC, such as carbon

point defects, such as substitutional defects7 (that is, N impurity10

work is the weak spin signal of single *T*V2a centres. It, however, has been shown that *T*V2a centre ensembles show drastically enhanced optical spin signals at cryogenic temperatures, up to more than 100% relative intensity16, which will shorten the measurement time by roughly a factor of a hundred. This, combined with the narrow PL line (⌧1 nm) of *T*V2 centres at low temperature37 and mature fabrication methods, strongly suggests that SiC is a promising platform for integrating spintronics, electronics and photonics in a

vacancies, divacancies36 and antisite-vacancy pairs7

**NATURE MATERIALS** | ADVANCE ONLINE PUBLICATION | www.nature.com/naturematerials **3**

3/4*π*2*Q*/*V*(*λ*/*n*)3, where the quality factor *Q* = 2*πνc*/*k* is related to the cavity resonance frequency *ν<sup>c</sup>* and the cavity field decay rate *k*, while *V* is the mode volume of the cavity. Nanophotonics is recently an expanding area for quantum technologies as it can provide a strong confinement of photons in a tiny space and potential applications such as ultrasmall and integrated photonic chips, slowing and stopping lights, quantum information processing and environmental sensing. Quantum emitters in bulk materials have inherently poor directional emission, prohibiting high collection and coupling efficiencies to fibre networks for long-range communication. One approach is to utilise cavities to enhance coupling to a specific optical mode. Using a photonic-crystal waveguide yields extraordinarily high coupling efficiencies. Similarly, optical microresonators offer the possibility to increase the coupling of quantum emission with the cavity mode. SiC-based nanophotonics is recently an expanding area as it could further improve present technologies based on Si or GaAs. One reason is due to the suppression of two-photon absorption at high input powers, because of its larger bandgap. Additionally, SiC can provide broadband operation, even in the visible range. The ability to construct nanocavities and optical microdiscs in SiC will possibly allow relevant technological advance in room temperature SPSs based on SiC defects and the coupling of multi-emitters to reach strong coupling regime. The main nanofabrication advantage available in SiC is based on its routinely achievable p- and n-doped in different polytypes and in its possibility to be grown epitaxially on a sacrificial silicon substrate; these features allow dopant-selective photoelectrochemical etching[64, 65] and more amenable application of reactive ion etching procedures to nano-fabricate photonics or micro-mechanical structures[21].

#### **6.1. SiC photonics cavities**

SiC 2D-photonic nanocavity crystals were initially fabricated on thin SiC-on-insulator wafers, which were specially prepared using the smart-cut technique[66]. The main challenge for 4H and 6H is related to the fact that SiC is much harder than silicon, and therefore, the important challenges here are the preparation of SiC membrane structure and the etching of SiC material as the conventional plasma etching technique for Si cannot be used. The wafers consisted of a SiC (6H crystalline structure) surface layer with a thickness of 180 nm above an SiO2 layer (680 nm), on top of a Si substrate (300 nm) that was used for handling. Quality factors up to 1,300 were achieved with such crystals, and their resonance tuning from the visible to the infrared can allow the selective enhancement of the SiC SPSs[12]. The PCh cavities were L3 nanocavities with three missing air holes. Designs and realisation based on schematics of air hole-shifted and heterostructured nanocavities[67] showed higher *Q* factors of 6×10<sup>3</sup> and up to 5×105, demonstrating that the design concepts previously used in Si can be applied to the SiC hexagonal polytypes. Regardless these were the first attempts, these PCh nanocavities showed so far the highest *Q* (see Figure 11). More recently 3C-SiC polytype is used for better integration with Si photonics, by heteroepitaxial growth on sacrificial Si substrate, allowing for direct patterning without ion implantation damage. With this method, an L3 PhC cavity has been fabricated in a thin-film (200 nm) 3C-SiC slab, obtaining Q-factor of 1,000 and modal volume of 0.75(*λ*/*n*)<sup>3</sup> over the band between 1250 and 1600 nm in the telecom IR range[22]. The possibility to incorporate colour centres with optically addressable spins similar to NV centres in diamond has been shown by fabricating H1 and L3 PhC cavities in 300-nm-thick 3C-SiC, as shown in Figure 12, with experimental *Q* of 1,000 for the strongly coupled cavity and (*λ*/*n*)<sup>3</sup> mode volume, tuned to the zero phonon line of the Ky5 colour

**Figure 11.** Schematics of **a** SiC-based (L3) nanocavity with three missing air holes and a *Q* ≈1200; **b** air hole-shifted *Q* ≈6000 and ˛A**c** heterostructured PCh nanocavity with higher *Q* obtained in 6H polytype, *Q* ≈500000. *a* is the cavity lattice constant related to the holes radius that for NIR range of 1380÷1590 nm is a = 550 nm[11]. Lattice constant as small as *a*=150 nm was achieved for resonance frequencies at 550-600 nm. Image adapted from ref[11]

centre (emission band 1,100 to 1,300 nm at 20 K), enhancing PL collection up to 10 times[23]. PhC structures made by a square or hexagonal lattice of SiC rods in air have also been proposed for telecom band applications[28], resulting in the confinement of the cavity mode in air, with the aim of reducing modal dispersion and temperature sensitivity. Theoretical modelling of a defect A1 cavity in SiC hexagonal lattice (photonic bandgap, PBG, from 1,380 to 1,850 nm) showed a thermal shift of the cavity TE mode seven times smaller as compared to a Si-based lattice with similar PBG, for a temperature range between 25 and 200 ◦C, with a maximum Q of 224. The highest *<sup>Q</sup>* reported to date of 7.69 <sup>×</sup> 104 has been achieved using a 45-*µ*m-long 1D PhC nanobeam cavity at 1.5 *µ*m wavelength [29]. It was fabricated on a 280-nm-thick amorphous SiC (a-SiC) film, deposited on an Si substrate by plasma-enhanced chemical vapour deposition (PECVD) in a gas mixture of silane and methane and patterned by e-beam lithography and reactive-ion etching with CF4/O2 plasma. The nanobeam was released in KOH with subsequent critical point drying.

#### **6.2. SiC microresonators**

14 Silicon Carbide Devices

3/4*π*2*Q*/*V*(*λ*/*n*)3, where the quality factor *Q* = 2*πνc*/*k* is related to the cavity resonance frequency *ν<sup>c</sup>* and the cavity field decay rate *k*, while *V* is the mode volume of the cavity. Nanophotonics is recently an expanding area for quantum technologies as it can provide a strong confinement of photons in a tiny space and potential applications such as ultrasmall and integrated photonic chips, slowing and stopping lights, quantum information processing and environmental sensing. Quantum emitters in bulk materials have inherently poor directional emission, prohibiting high collection and coupling efficiencies to fibre networks for long-range communication. One approach is to utilise cavities to enhance coupling to a specific optical mode. Using a photonic-crystal waveguide yields extraordinarily high coupling efficiencies. Similarly, optical microresonators offer the possibility to increase the coupling of quantum emission with the cavity mode. SiC-based nanophotonics is recently an expanding area as it could further improve present technologies based on Si or GaAs. One reason is due to the suppression of two-photon absorption at high input powers, because of its larger bandgap. Additionally, SiC can provide broadband operation, even in the visible range. The ability to construct nanocavities and optical microdiscs in SiC will possibly allow relevant technological advance in room temperature SPSs based on SiC defects and the coupling of multi-emitters to reach strong coupling regime. The main nanofabrication advantage available in SiC is based on its routinely achievable p- and n-doped in different polytypes and in its possibility to be grown epitaxially on a sacrificial silicon substrate; these features allow dopant-selective photoelectrochemical etching[64, 65] and more amenable application of reactive ion etching procedures to

SiC 2D-photonic nanocavity crystals were initially fabricated on thin SiC-on-insulator wafers, which were specially prepared using the smart-cut technique[66]. The main challenge for 4H and 6H is related to the fact that SiC is much harder than silicon, and therefore, the important challenges here are the preparation of SiC membrane structure and the etching of SiC material as the conventional plasma etching technique for Si cannot be used. The wafers consisted of a SiC (6H crystalline structure) surface layer with a thickness of 180 nm above an SiO2 layer (680 nm), on top of a Si substrate (300 nm) that was used for handling. Quality factors up to 1,300 were achieved with such crystals, and their resonance tuning from the visible to the infrared can allow the selective enhancement of the SiC SPSs[12]. The PCh cavities were L3 nanocavities with three missing air holes. Designs and realisation based on schematics of air hole-shifted and heterostructured nanocavities[67] showed higher *Q* factors of 6×10<sup>3</sup> and up to 5×105, demonstrating that the design concepts previously used in Si can be applied to the SiC hexagonal polytypes. Regardless these were the first attempts, these PCh nanocavities showed so far the highest *Q* (see Figure 11). More recently 3C-SiC polytype is used for better integration with Si photonics, by heteroepitaxial growth on sacrificial Si substrate, allowing for direct patterning without ion implantation damage. With this method, an L3 PhC cavity has been fabricated in a thin-film (200 nm) 3C-SiC slab, obtaining Q-factor of 1,000 and modal volume of 0.75(*λ*/*n*)<sup>3</sup> over the band between 1250 and 1600 nm in the telecom IR range[22]. The possibility to incorporate colour centres with optically addressable spins similar to NV centres in diamond has been shown by fabricating H1 and L3 PhC cavities in 300-nm-thick 3C-SiC, as shown in Figure 12, with experimental *Q* of 1,000 for the strongly coupled cavity and (*λ*/*n*)<sup>3</sup> mode volume, tuned to the zero phonon line of the Ky5 colour

nano-fabricate photonics or micro-mechanical structures[21].

**6.1. SiC photonics cavities**

High-*Q* optical microresonators can also dramatically enhance optical fields inside a small volume and are considered relevant in applications to enhance nonlinear optics effects and their implication to quantum optics. In addition, they are important in fields such as cavity optomechanics[68, 69]. In general for microresonators, the materials play a crucial role based on its properties such as linear/nonlinear optical susceptibilities and mechanical property. High-*Q* microresonators generally exhibit large thermal and mechanical sensitivities, making them desired for practical application. Microresonators are commonly fabricated in disc shapes resting on a central pedestal; however, recently suspended ring resonators have been proposed in order to obtain better waveguide dispersion engineering properties for nonlinear processes[20]. Some materials, such as Si and GaAs, have small bandgaps that limit the operating spectral range. Others, such as lithium niobate and chalcogenide glass, exhibit photorefractive effect or two-photon absorption and strong Raman scattering, making it challenging to handle high optical powers. For microphotonic/nanophotonic applications, it is crucial to search for a material platform with combined superior optical, mechanical and thermal properties. SiC seems to match some of these requirements for an optimal microresonator performance. Since strong coupling between a point defect optical source and the resonant cavity is challenging, due to having to place the defect at the field maximum of the cavity mode, a disc resonator in this respect has the good feature of supporting multiple modes, which cover almost the whole volume of the disc, making overlapping and tuning to

the zero phonon line of the defect easier[26]. The single-crystalline 3C-SiC in Lu et al.[21] was epitaxially grown on a (100) silicon substrate by the two-step atmospheric pressure chemical vapour deposition. A disc geometry was patterned by electron-beam lithography and etched by reactive ion etching with CF4/Ar plasma, optimised to form the well-defined device structure. The silicon substrate was undercut by XeF2 to form the supporting pedestal. The intrinsic *<sup>Q</sup>* factor is shown to be 6.19 <sup>×</sup> <sup>10</sup>3. The damage to the crystal incurred during ion etching can impair the optical efficiency and the spin coherence of the defect sources, so an alternative is sought by low-damage selective chemical etch processes, such as photoelectrochemical etching, exploiting the higher etch rate of n-doped to p-doped material under direct UV illumination in HF or KOH solutions[24]. Epitaxial p-doped SiC on n+-SiC was patterned by reactive-ion etching (RIE) in SF6/O2 plasma using 3 *µ*m alumina microspheres as masking agents; then the p-layer was undercut by KOH etching under UV illumination. Well-undercut microdiscs reached a measured *Q*-factor of 9,200 at 617.4 nm resonance, with a theoretical maximum of 105, limited by light leakage into the supporting pillar. The issue of light loss in the supporting Si substrate was addressed by exploiting the high stiffness of an 860-nm-thick 3C-SiC layer, building a 20 *µ*m radius ring microresonator suspended in air from a central pedestal by 200-nm-wide spokes and by e-beam lithography followed by CHF3/O2 RIE[20]. An intrinsic *Q* factor of 14,100 was measured at 1,543 nm wavelength. PL from 3C-SiC in the visible range was first demonstrated for multi-emitter cavity quantum electrodynamics at room temperature in disc microresonators of 210 nm thickness and diameter below 2 *µ*m, fabricated by two-step chemical vapour deposition (CVD) followed by e-beam patterning, HBr/Cl2 plasma etching and XeF2 undercut to form the pedestal[30]. Characterisation by laser scanning confocal microscopy between 650 and 850 nm wavelength evidenced whispering gallery modes with *Q*-factor up to 2,300 and mode volume around 2 <sup>×</sup> (*λ*/*n*)3. The highest *<sup>Q</sup>*-factor reported to date for a disc microresonator is 5.12 <sup>×</sup> 104, obtained at 1,551 nm wavelength with e-beam-patterned heteroepitaxial 3C-SiC on Si, ion etched in CF4/Ar plasma with subsequent KOH undercut[26]. The resulting disc had a thickness of 700 nm and a radius of 6.25 *µ*m, and simulations showed a strong coupling regime with a cooperativity *C*=20 and a maximum theoretical radiation-limited *Q*-factor above 108.

#### **6.3. Nonlinear effects**

SiC is a non-centrosymmetric material, which means that it has nonzero second-order susceptibility, permitting the observation of nonlinear effects such as second-harmonic generation (SHG), and Pockels effect, which are not available in the more common centrosymmetric materials (SiO2, SiN*<sup>x</sup>* and others whose molecule's symmetry allows only third-order susceptibility). Differently from other non-centrosymmetric semiconductors and crystals such as LiNbO3, SiC has the ability to house optically active defects for quantum processing. Nonlinear effects in this material combined with colour centres have the potential to increase the applications in other fields such as nonlinear photonic, including all-optical switching, wavelength conversion and harmonic generation. These effects are important for

the development of quantum devices based on nonlinear effects[70]. SiC second order, *<sup>χ</sup>*(2) *<sup>i</sup>*,*j*,*k*, and electro-optical *ri*,*j*,*<sup>k</sup>* coefficients were predicted from ab initio calculations in 3C, 4H and 6H [71] and measured [72–75] in 4H and 6H polytypes. Second-order nonlinear optical coefficients are at the core of the physics of nonlinear optical processes; their knowledge and high values are essential to increase the efficiency of frequency conversion. Hexagonal SiC is

16 Silicon Carbide Devices

*Q*-factor above 108.

**6.3. Nonlinear effects**

the zero phonon line of the defect easier[26]. The single-crystalline 3C-SiC in Lu et al.[21] was epitaxially grown on a (100) silicon substrate by the two-step atmospheric pressure chemical vapour deposition. A disc geometry was patterned by electron-beam lithography and etched by reactive ion etching with CF4/Ar plasma, optimised to form the well-defined device structure. The silicon substrate was undercut by XeF2 to form the supporting pedestal. The intrinsic *<sup>Q</sup>* factor is shown to be 6.19 <sup>×</sup> <sup>10</sup>3. The damage to the crystal incurred during ion etching can impair the optical efficiency and the spin coherence of the defect sources, so an alternative is sought by low-damage selective chemical etch processes, such as photoelectrochemical etching, exploiting the higher etch rate of n-doped to p-doped material under direct UV illumination in HF or KOH solutions[24]. Epitaxial p-doped SiC on n+-SiC was patterned by reactive-ion etching (RIE) in SF6/O2 plasma using 3 *µ*m alumina microspheres as masking agents; then the p-layer was undercut by KOH etching under UV illumination. Well-undercut microdiscs reached a measured *Q*-factor of 9,200 at 617.4 nm resonance, with a theoretical maximum of 105, limited by light leakage into the supporting pillar. The issue of light loss in the supporting Si substrate was addressed by exploiting the high stiffness of an 860-nm-thick 3C-SiC layer, building a 20 *µ*m radius ring microresonator suspended in air from a central pedestal by 200-nm-wide spokes and by e-beam lithography followed by CHF3/O2 RIE[20]. An intrinsic *Q* factor of 14,100 was measured at 1,543 nm wavelength. PL from 3C-SiC in the visible range was first demonstrated for multi-emitter cavity quantum electrodynamics at room temperature in disc microresonators of 210 nm thickness and diameter below 2 *µ*m, fabricated by two-step chemical vapour deposition (CVD) followed by e-beam patterning, HBr/Cl2 plasma etching and XeF2 undercut to form the pedestal[30]. Characterisation by laser scanning confocal microscopy between 650 and 850 nm wavelength evidenced whispering gallery modes with *Q*-factor up to 2,300 and mode volume around 2 <sup>×</sup> (*λ*/*n*)3. The highest *<sup>Q</sup>*-factor reported to date for a disc microresonator is 5.12 <sup>×</sup> 104, obtained at 1,551 nm wavelength with e-beam-patterned heteroepitaxial 3C-SiC on Si, ion etched in CF4/Ar plasma with subsequent KOH undercut[26]. The resulting disc had a thickness of 700 nm and a radius of 6.25 *µ*m, and simulations showed a strong coupling regime with a cooperativity *C*=20 and a maximum theoretical radiation-limited

SiC is a non-centrosymmetric material, which means that it has nonzero second-order susceptibility, permitting the observation of nonlinear effects such as second-harmonic generation (SHG), and Pockels effect, which are not available in the more common centrosymmetric materials (SiO2, SiN*<sup>x</sup>* and others whose molecule's symmetry allows only third-order susceptibility). Differently from other non-centrosymmetric semiconductors and crystals such as LiNbO3, SiC has the ability to house optically active defects for quantum processing. Nonlinear effects in this material combined with colour centres have the potential to increase the applications in other fields such as nonlinear photonic, including all-optical switching, wavelength conversion and harmonic generation. These effects are important for the development of quantum devices based on nonlinear effects[70]. SiC second order, *<sup>χ</sup>*(2)

and electro-optical *ri*,*j*,*<sup>k</sup>* coefficients were predicted from ab initio calculations in 3C, 4H and 6H [71] and measured [72–75] in 4H and 6H polytypes. Second-order nonlinear optical coefficients are at the core of the physics of nonlinear optical processes; their knowledge and high values are essential to increase the efficiency of frequency conversion. Hexagonal SiC is

*<sup>i</sup>*,*j*,*k*,

**Figure 12. a** Simulated *Ey* field distribution, **b** SEM image and **c** PL at 20K from an L3 photonic-crystal cavity in 3C-SiC. The cavity resonance is tuned by size reduction and shift of the neighbouring crystal holes, for 1,060 nm excitation of the embedded Ky5 colour centre[23]. **d** SEM image of a fabricated a-SiC 45-*µ*m-long PhC nanobeam cavity, achieving the highest Purcell factor reported of 10<sup>4</sup> at 1.5 *µ*m wavelength[29]. **e** SEM micrographs of high-Q disc resonators obtained by low-damage photoelectrochemical selective etching of p-SiC over n+-SiC. Notice the different undercuts achieved by wet etching and the surface porosity of the supporting pillar, which does not affect the etched microdisc[24]. Images reproduced from [23, 24, 29] with Copyright permission 2014-2015, AIP Publishing LLC

characterised by three independent components of the second-order nonlinear optical tensor, recently measured accurately as *d*<sup>31</sup> = *d*<sup>32</sup> = 6.7(6.5)pm/V, *d*<sup>15</sup> = *d*<sup>24</sup> = 6.5(6.7)pm/V and *d*<sup>33</sup> = −12.5(−11.7)pm/V in 6H (4H). The refractive indices and the birefringence are used to determine if phase matching can be realised; they have been remeasured from the visible to the mid-infrared region, and Sellmeier equations for ordinary and extraordinary refractive index in 4H and 6H have been provided[76]. This has led to mid-infrared region laser output tunable from 3.90 to 5.60 *µm* by phase-matched difference frequency generation in 4H-SiC. In this case, the material can withstand high power and for laser higher outputs in this spectral region. For applications, it is important to enhance SHG in photonics cavities. The first demonstration of SHG in SiC-based nanophotonic structures used a 6H-SiC PhC cavity tuned to 1560 nm with a Q of 10,000, taking advantage of the high refractive index of SiC (2.5) to increase confinement and of the large electronic bandgap (3.0 eV) to extend the operating bandwidth from IR to visible and to suppress two-photon absorption. A conversion efficiency of 2.59 <sup>×</sup> <sup>10</sup>−<sup>5</sup> was obtained for 0.17 mW average input power[25]. A high-*Q* amorphous SiC disc microresonator has been demonstrated for nonlinear applications, with an optical *<sup>Q</sup>* of 1.3 <sup>×</sup> 105 in the 1,550 nm telecom band[27]. With PECVD deposition followed by e-beam patterning and plasma etching, a smooth-sidewall disc with 570 nm thickness and 6 *µ*m radius was fabricated, and its Kerr nonlinearity was characterised with a pump-probe self-/cross-phase modulation scheme using two high-*Q* whispering-gallery modes. The resonator was pumped at 1545 nm with sinusoidally modulated light, transferring the modulation on the refractive index due to optical Kerr effect, which was then measured by a weak probe signal coupled at 1,498 nm. This gave a nonlinear coefficient *<sup>n</sup>*<sup>2</sup> <sup>=</sup> 5.9 <sup>×</sup> <sup>10</sup>−<sup>15</sup> cm2/W, higher than any other material in use to generate frequency combs. Recently, SHG microscopy was used as a non-invasive method for imaging and identification of structural defects such as polytype inclusions and stacking faults in SiC epilayers, grown on hexagonal SiC by the vapour-liquid-solid techniques. This technique is competitive with destructive sample preparation and severely limited area of analysis to tens of microns associated instead with high-resolution TEM. By combining the SHG-based imaging with X-ray diffraction and SHG rotational anisotropy, the growth of 3C polytype on the 4H-SiC substrate was confirmed, and the polytype of the imaged defects was identified[77].

#### **7. Other applications**

Paramagnetic defects in SiC have been integrated into some devices as a proof of principle demonstration of their electrical control or of their ability to sense changes in strain, magnetic field and temperature. The discovery of single-photon emission and its engineering and isolating single defects with proper transition energy on demand can open a route for an efficient electrical single-photon source, particularly in the IR region, due to the described subgap defects. To fabricate devices, standard semiconductor manufacturing technology in combination with high-energy electron irradiation of the material can allow, for instance, the construction of LEDs with radiative recombination occurring at irradiation-induced intrinsic defects. Such LEDs have been demonstrated with two strong PL emission bands in the visible and near infrared (NIR), associated with two different intrinsic defects, one being the Si vacancy[78]. Selective manipulation of individual defect spin can be achieved. The spin separation required to achieve strong dipolar coupling between spins is of the order of tens of nanometres. Electric fields can be confined on similar length scales; therefore, electrically driven spin resonance methods can be used to manipulate the defect spin state[79]. Divacancy defects in 4H- and 6H-SiC possess a spin-dependent optical cycle, which allows non-resonant laser illumination to polarise first and then read out its ground-state spin. Since the defect PL depends on whether its spin state is *ms* = 0 or *ms* = ±1, it is possible to control the defect spin dynamics by the measuring differential PL (∆IPL) between an initial state and one that has been evolved by applying a magnetic or electric field pulses. These ∆IPL measurements, in addition to enabling conventional (magnetically driven) ODMR, can also be used for electrically driven ODMR (EODMR). In Figure 13, we show the electrical control of the QL1 (unknown yet) defect in 6H-SiC with similar spin properties of the neutral divacancies, with ZPL at 1.088 eV and ODMR at 1.3GHz[39]. Ac electric fields are used to drive the Rabi oscillations across a magnetic-dipole forbidden spin transition (m*<sup>s</sup>* = ±2) of the optically addressable electronic spin. A flow cryostat cools the device illustrated in Figure 13**b** to 20 K, and a permanent magnet is used to provide a static magnetic field parallel to the defect magnetic dipole. QL1 colour centres were produced in 6H-SiC substrates via a carbon implantation and annealing process introducing defects immediately below the surface. The spins were localised within a 400-nm-thick layer immediately beneath the 6H-SiC surface and were optically pumped with a 976 nm laser addressing 104 defects in the optical excitation volume. We show in Figures 13 **c** and **d** the effect observed from the application of an electric field via the electrode to the transition corresponding to the

10.5772/61166

18 Silicon Carbide Devices

238 Advanced Silicon Carbide Devices and Processing

was identified[77].

**7. Other applications**

whispering-gallery modes. The resonator was pumped at 1545 nm with sinusoidally modulated light, transferring the modulation on the refractive index due to optical Kerr effect, which was then measured by a weak probe signal coupled at 1,498 nm. This gave a nonlinear coefficient *<sup>n</sup>*<sup>2</sup> <sup>=</sup> 5.9 <sup>×</sup> <sup>10</sup>−<sup>15</sup> cm2/W, higher than any other material in use to generate frequency combs. Recently, SHG microscopy was used as a non-invasive method for imaging and identification of structural defects such as polytype inclusions and stacking faults in SiC epilayers, grown on hexagonal SiC by the vapour-liquid-solid techniques. This technique is competitive with destructive sample preparation and severely limited area of analysis to tens of microns associated instead with high-resolution TEM. By combining the SHG-based imaging with X-ray diffraction and SHG rotational anisotropy, the growth of 3C polytype on the 4H-SiC substrate was confirmed, and the polytype of the imaged defects

Paramagnetic defects in SiC have been integrated into some devices as a proof of principle demonstration of their electrical control or of their ability to sense changes in strain, magnetic field and temperature. The discovery of single-photon emission and its engineering and isolating single defects with proper transition energy on demand can open a route for an efficient electrical single-photon source, particularly in the IR region, due to the described subgap defects. To fabricate devices, standard semiconductor manufacturing technology in combination with high-energy electron irradiation of the material can allow, for instance, the construction of LEDs with radiative recombination occurring at irradiation-induced intrinsic defects. Such LEDs have been demonstrated with two strong PL emission bands in the visible and near infrared (NIR), associated with two different intrinsic defects, one being the Si vacancy[78]. Selective manipulation of individual defect spin can be achieved. The spin separation required to achieve strong dipolar coupling between spins is of the order of tens of nanometres. Electric fields can be confined on similar length scales; therefore, electrically driven spin resonance methods can be used to manipulate the defect spin state[79]. Divacancy defects in 4H- and 6H-SiC possess a spin-dependent optical cycle, which allows non-resonant laser illumination to polarise first and then read out its ground-state spin. Since the defect PL depends on whether its spin state is *ms* = 0 or *ms* = ±1, it is possible to control the defect spin dynamics by the measuring differential PL (∆IPL) between an initial state and one that has been evolved by applying a magnetic or electric field pulses. These ∆IPL measurements, in addition to enabling conventional (magnetically driven) ODMR, can also be used for electrically driven ODMR (EODMR). In Figure 13, we show the electrical control of the QL1 (unknown yet) defect in 6H-SiC with similar spin properties of the neutral divacancies, with ZPL at 1.088 eV and ODMR at 1.3GHz[39]. Ac electric fields are used to drive the Rabi oscillations across a magnetic-dipole forbidden spin transition (m*<sup>s</sup>* = ±2) of the optically addressable electronic spin. A flow cryostat cools the device illustrated in Figure 13**b** to 20 K, and a permanent magnet is used to provide a static magnetic field parallel to the defect magnetic dipole. QL1 colour centres were produced in 6H-SiC substrates via a carbon implantation and annealing process introducing defects immediately below the surface. The spins were localised within a 400-nm-thick layer immediately beneath the 6H-SiC surface and were optically pumped with a 976 nm laser addressing 104 defects in the optical excitation volume. We show in Figures 13 **c** and **d** the effect observed from the application of an electric field via the electrode to the transition corresponding to the

**Figure 13. a** The ground state spin structure of QL1 defect in 6H-SiC, where the spin levels m*<sup>s</sup>* = 0, ±1 are shown in the presence of a magnetic field *B*. The allowed optical transition m*<sup>s</sup>* = ±1 are in orange, while the m*<sup>s</sup>* = ±2 in blue are not allowed. **b** Experimental set-up used for PL collection via a dichroic mirror and measured with a photodiode. The spins are driven electrically by the electrodes and magnetically by the stripline directly on the bulk material.**c** A clear EODMR feature is observed at the frequency difference (778 MHz) of the m*<sup>s</sup>* = | + 1 and m*<sup>s</sup>* = | − 1, indicating population transfer across the two levels. On the top of the panel, the time sequence of the microwave pulse and the electric field are applied to achieve EODMR. The length of P is fixed and its frequency is swept. The electrode power was 0.09 W and the magnetic *B*=139 G.**d** ODMR signal when the stripline is driven at B=139 G. The m*<sup>s</sup>* = ±1 resonances are shaded orange, and the m*<sup>s</sup>* = ±2 resonance (at 778 MHz, shaded blue) is not seen in ODMR only. Images reproduced from [79] with Copyright permission 2014 American Physical Society

prohibited optical transition. Another PL resonance appears in the presence of the m*<sup>s</sup>* = ±2 transition indicating a population transfer between the two-spin states.

Falk et al.[80] state that the spin states of neutral divacancies in 4H-SiC are highly sensitive to electrical and mechanical perturbations of material. The experiments were done in high-purity semi-insulating 4H-SiC wafers, purchased from Cree Inc., where neutral divacancies were incorporated during crystal growth. A 50 *µ*m membrane from the sample was cut and mounted on top of a piezo actuator. The piezo actuation applies tensile strain to the SiC membrane perpendicular to the c-axis. The device was cooled to 20 K. The neutral divacancy's ZPLs were excited optically at 976 nm and monitored. Microwave excitation for electron spin resonance was supplied by waveguide antennae on the chip. A variation of the ODMR signal was observed in the presence of strain. The strain sensitivity is inferred to be 10−7/ <sup>√</sup>*HzN*, where *<sup>N</sup>* is the number of spins. Also, the electric field response exhibited significant spin-dependent PL, 2-7 times stronger than with NV centres in diamond. Electric field pulses were applied across the SiC membrane, using patterned electrodes that transmit light, and the ODMR signal was monitored. If these techniques were extended to single defects, these properties could be applicable to the nanometre scale, and they could be applied for sensing intracellular electric fields, integrating nanoscale sensing into SiC bioelectronics[81], or coupling spins to SiC nano-mechanical resonators[9]. In another work, the spin resonances of the VSi defect at 128 MHz and 28 MHz associated with the V2 and V3 ZPLs in 6H SiC were used to monitor magnetic field and temperature variation [82].

An important milestone is to achieve the integration of these defects in nanoparticles. The first demonstration of optical spin control of silicon vacancy in 600-nm-size material was achieved in [83]. High-quality, defect-free 6H-SiC bulk material using the well-established sublimation technique in argon atmosphere at a high temperature (2500÷2600 ◦C) was grown from a specially prepared source pure SiC powder synthesised from silicon and carbon mixture of spectral purity. Macroscopic crystal fragments in the mm range were synthesised and then placed in the central irradiation tube of a TRIGA Mark II nuclear reactor, where vacancies were formed by neutron irradiation followed by annealing, achieving an initial concentration of VSi defects of the order of 10 <sup>15</sup> cm−3. High-energy milling process was used to achieve size from 60 to 600 nm. PL from VSi (V1,2,3) was observed in 60 nm and 600 nm crystals at room and cryogenic temperature for comparison to identify the ZPLs. No single-photon emission was observed while V3 and V2 from VSi spin resonances were observed at 27 MHz and 127 MHz with positive and negative ODMR contrast, respectively.

#### **8. Summary and outlook**

We have summarised SiC paramagnetic defects with quantum properties observed following single-defect creation and isolation. These defects are present in various polytypes, and their variety in different crystal sites increases their space of applications. We also reviewed the state of the art of quantum effects observed in SiC nanostructures. SiC as a host for quantum systems is just at its inception, though the beginning indicates it could be one of the most prominent and rich material to investigate or to employ in the future. A large variety of deep defects were investigated from the point of view of paramagnetic and optical properties in the past, and now other quantum properties have been revealed, providing additional information not available at the ensemble level and novel insights relative to previously known defects. The challenge of engineering a desired defect in a specific location in the material is still an open problem, though it has been successfully demonstrated so far with electron, neutron and ion irradiation. SiC single defects in bulk and in the red part of the spectrum is one of the best SPS operating at room temperature, surpassing in terms of brightness other materials. The properties of these defects are also important for their spin coherent control and their use as spin qubits. The spin coherence time in ensemble and at the single level of intrinsic defects in SiC is very promising and comparable to NV in diamond. Isolation of intrinsic single spin has been achieved. However, for the most interesting spectral region in the infrared, it appears that the emission is not very bright and needs further enhancement via integration of the defects in photonics crystal cavities or microresonator. The spin coherence control still requires cryogenic temperature for the IR emitters. Since both Si and C have spin-free isotopes (28Si12C), it is expected that the measured coherence times could be enhanced through the sublimation crystal growth to reduce the abundance of 29Si and 13C isotopes having nonzero nuclear spins. While the challenge of the nano-fabrication of this material seems to indicate its feasibility and viability, for this to be successful, a major challenge needs to be addressed, specifically, the creation of the defects in a specific location close to the material surface within the photonic devices. Another option could be to integrate SiC QDs in hybrid photonics systems. This will require the successful incorporation of the desired defects with high yield in QDs and NPs. Additionally, many other potential defects in the material should be explored, particularly extrinsic defects that could facilitate their on-demand integration in devices. Alternatively for intrinsic defects originated from damage, more precise damage techniques could aid to the accurate location of the defects in the lattice. Nanostructures are ready to be integrated with deep optical and paramagnetic defects, though better design of cavities and choice of higher quality material would allow to take full advantage of functionalities related to single-photon emission and spin sensing to further advance their current applications. If all these challenges will be overcome in the next years, we envision the construction of SiC-defect-based LEDs and photonic crystal structures with in-built active quantum systems, for next-generation quantum technology devices.

#### **Author details**

20 Silicon Carbide Devices

**8. Summary and outlook**

An important milestone is to achieve the integration of these defects in nanoparticles. The first demonstration of optical spin control of silicon vacancy in 600-nm-size material was achieved in [83]. High-quality, defect-free 6H-SiC bulk material using the well-established sublimation technique in argon atmosphere at a high temperature (2500÷2600 ◦C) was grown from a specially prepared source pure SiC powder synthesised from silicon and carbon mixture of spectral purity. Macroscopic crystal fragments in the mm range were synthesised and then placed in the central irradiation tube of a TRIGA Mark II nuclear reactor, where vacancies were formed by neutron irradiation followed by annealing, achieving an initial concentration of VSi defects of the order of 10 <sup>15</sup> cm−3. High-energy milling process was used to achieve size from 60 to 600 nm. PL from VSi (V1,2,3) was observed in 60 nm and 600 nm crystals at room and cryogenic temperature for comparison to identify the ZPLs. No single-photon emission was observed while V3 and V2 from VSi spin resonances were observed at 27 MHz and 127 MHz with positive and negative ODMR contrast, respectively.

We have summarised SiC paramagnetic defects with quantum properties observed following single-defect creation and isolation. These defects are present in various polytypes, and their variety in different crystal sites increases their space of applications. We also reviewed the state of the art of quantum effects observed in SiC nanostructures. SiC as a host for quantum systems is just at its inception, though the beginning indicates it could be one of the most prominent and rich material to investigate or to employ in the future. A large variety of deep defects were investigated from the point of view of paramagnetic and optical properties in the past, and now other quantum properties have been revealed, providing additional information not available at the ensemble level and novel insights relative to previously known defects. The challenge of engineering a desired defect in a specific location in the material is still an open problem, though it has been successfully demonstrated so far with electron, neutron and ion irradiation. SiC single defects in bulk and in the red part of the spectrum is one of the best SPS operating at room temperature, surpassing in terms of brightness other materials. The properties of these defects are also important for their spin coherent control and their use as spin qubits. The spin coherence time in ensemble and at the single level of intrinsic defects in SiC is very promising and comparable to NV in diamond. Isolation of intrinsic single spin has been achieved. However, for the most interesting spectral region in the infrared, it appears that the emission is not very bright and needs further enhancement via integration of the defects in photonics crystal cavities or microresonator. The spin coherence control still requires cryogenic temperature for the IR emitters. Since both Si and C have spin-free isotopes (28Si12C), it is expected that the measured coherence times could be enhanced through the sublimation crystal growth to reduce the abundance of 29Si and 13C isotopes having nonzero nuclear spins. While the challenge of the nano-fabrication of this material seems to indicate its feasibility and viability, for this to be successful, a major challenge needs to be addressed, specifically, the creation of the defects in a specific location close to the material surface within the photonic devices. Another option could be to integrate SiC QDs in hybrid photonics systems. This will require the successful incorporation of the desired defects with high yield in QDs and NPs. Additionally, many other potential defects in the material should be explored, particularly extrinsic defects that could facilitate their on-demand integration in devices. Alternatively for intrinsic defects originated from damage, more precise damage techniques could aid to the accurate location of the defects in Stefania Castelletto1∗, Lorenzo Rosa2,3 and Brett C. Johnson4

\*Address all correspondence to: stefania.castelletto@rmit.edu.au

1 School of Aerospace, Mechanical and Manufacturing Engineering RMIT University, Melbourne, Australia

2 Swinburne University of Technology, Centre for Micro-Photonics (H74), Hawthorn, Australia


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