**4. Hardware approaches**

signal compression, the optimal choice is a wavelet function that can approximate the action potentials waveform with minimum DWT coefficients and error. It has been shown that by proper selection of the wavelet basis, most of the spike energy is concentrated in a few large coefficients, while many small coefficients carry insignificant information and are mainly attributed to noise [19]. Therefore, in order to achieve higher data reduction rates, the DWT coefficients are passed through a thresholding stage. In this block, data coefficients smaller than desired certain threshold level are set to zero, while others are left unchanged. It is obvious that the threshold value plays an important role in the overall data compression rate, and also in the quality of the reconstructed signal. Hence, the threshold level should be set carefully

Due to power and size constrains in biomedical implants, VLSI implementation of DWT is of great importance. In [20], it has been shown that from a signal compression standpoint, *symmlet4* wavelet basis is advantageous over other wavelet functions for neural recording applications. It is believed that this is mainly because of the similarity of this function to the general wave shape of action potentials. For hardware implementation of *symmlet4* function, lifting method is proposed in [21]. Furthermore, two different circuit designs, pipelined and sequential, are presented and compared for the lifting scheme. It is demonstrated that for single-level single-channel integer DWT, the pipelined approach consumes lower power, but occupies more silicon area compared with the sequential implementation. On the other hand, 4-level multi-channel implementation of the two designs indicates that the sequential ap‐ proach requires significantly smaller chip area, while the power consumption of both is almost the same. As a result, the sequential execution architecture is employed in [23] to design a complete 32-channel compression system based on the 4-level *symmlet4* DWT. The chip consumes 3 mW of power and occupies only 5.75 mm2 in a 0.5-μm CMOS technology. Also, with a sampling rate of 25 KSample/Sec per channel and 10-bits data samples, the system provides data compression of more than 20 times, resulting in a total output bit rate of less

In [26], a neural signal compression method based on the Discrete *Haar* Wavelet Transforms (DHWT) is proposed. From the standpoint of data compression, *Haar* basis function may not perform as efficient as complex functions such as high-order *Daubechies* and *symmlet*, but due to its simple hardware implementation, it can be easily used for large number of neural channels with less concern about power and area. As discussed in [26] for two-point DHWT, data coefficients can be calculated by only a buffer, an adder, and a subtractor. Moreover, in order to compare *Haar* and *symmlet4* basis functions, they have been both designed for processing a single channel with 8-bits data samples. Results indicate that before the thresh‐ olding stage, relative error (between the original signal and the corresponding reconstructed signal) for the DHWT is only 0.01% larger than the *symmlet4* case, which is obviously negligible. On the other hand, hardware implementation of the DHWT shows around 83% saving in number of transistors, and more than 90% in the occupied silicon area, when physically laid out in a 0.13-μm CMOS technology. The complete 64-channel DHWT-based neural compressor achieves a compression rate of 112 with an error of 2.22%. Additionally, the compressor circuit

consumes as low as 0.12 mW @1.2 V supply voltage, and occupies less than 0.1 mm2

in a 0.13-

based on the requirements of the target application.

than 370 kbps.

300 Advances in Bioengineering

To avoid adding extra power- and area-hungry signal processing blocks for data reduction, and at the same time preserving important information of the neural signals, there is a different category of data reduction techniques, known as *hardware approaches*. These are the approaches focused on modifying the hardware of the recording system in such a way that considerable bit-rate reduction can be achieved. Obvious advantages of these approaches are smaller silicon area and power consumption as compared with the mathematical approaches explained in the previous section.

To benefit from the advantages associated with digital signal processing and also digital data communication (as opposed to their analog counterparts), neural recording devices are commonly designed to convert neural signals into digital as the first step. As a result, analogto-digital converters (ADCs) are known as one of the key building blocks in such systems. Recently some efforts are put on designing application-specific ADCs to efficiently utilize the bandwidth allocated for wireless data telemetry. In this section, an efficient method for analogto-digital (A/D) conversion of neural signals is discussed. This method results in significant reduction of data-rate for multi-channel cortical neural recording microsystems.

#### **4.1. Anti-logarithmc quantization**

Although linear ADCs are typically used to digitize neural signals in neural recording microsystems, it is beneficial to design a nonlinear ADC for such specific signals. Choosing the best-suited nonlinearity function for a specific signal requires recognition of the concen‐ tration of information along the signal amplitude range. As illustrated in the left side of Figure 10, in general, signals can be categorized into three types according to how the information they carry is distributed along the amplitude range.

*Type-I* signals are named "Signals with *Non-Concentrated Information* (*NCI*)" due to their almost uniform distribution of information concentration. Important information for *Type-II* signals is concentrated at the lower side of the amplitude range. Audio signals are of this type, referred to as "signals with *Information Concentration at Low Amplitudes*(*ICLA*)". Conversely, for "signals with *Information Concentration at High Amplitudes* (*ICHA*)", i.e., *Type-III* signals, more informa‐ tion is present at higher side of the amplitude range, with neural signals as examples.

Figure 10 provides intuitive illustration of the choice of different quantization functions for the three signal types discussed. With a constant slope (i.e., linear) quantization function, an NCI signal is better digitized. Decreasing slope quantization functions such as logarithmic function are recommended for ICLA signals. These functions put more emphasis on lower amplitudes, where more information is concentrated. For example, compressing/expanding (companding) of audio signals in communications systems is based on logarithmic quantiza‐ tion, which increases the dynamic range and improves the SNR [28]. Whereas quantization functions with increasing slope along the input amplitude range, such as the exponential function, put more resolution in the quantization of the larger amplitudes and are preferred for ICHA signals.

PDF Domain

Time Domain

Figure 10. Selecting quantization function for NCI, ICLA, and ICHA signals **Figure 10.** Selecting quantization function for NCI, ICLA, and ICHA signals

Baseline

Figure 11. Neural signal composed of APs and B-Noise

Background Noise

Baseline

Neural Signal

Action Potentials

Baseline

**Figure 11.** Neural signal composed of APs and B-Noise

amplitudes, where more information is concentrated. For example, compressing/expanding (companding) of audio signals in communications systems is based on logarithmic quantiza‐ tion, which increases the dynamic range and improves the SNR [28]. Whereas quantization functions with increasing slope along the input amplitude range, such as the exponential function, put more resolution in the quantization of the larger amplitudes and are preferred

> Input Signal Amplitude

Input Signal Amplitude

Digital Code Info. Power Info. Power Info. Power

Digital Code Info. Power Info. Power Info. Power

Input Signal Amplitude

Input Signal Amplitude

Input Signal Amplitude

Input Signal Amplitude

Digital Code Info. Power Info. Power Info. Power

Input Signal Amplitude

*Information*

*Amplitudes*

Input Signal Amplitude

Input Signal Amplitude

Input Signal Amplitude

Input Signal Amplitude

*High at Concentration*

Input Signal Amplitude

Info. Conc. Info. Conc. Info. Conc.

*Low at Concentration*

*(ICLA)*

PDF Domain

Time Domain

*Information*

*Amplitudes*

Input Signal Amplitude

Input Signal Amplitude

Input Signal Amplitude

> *(ICHA)*

Figure 10. Selecting quantization function for NCI, ICLA, and ICHA signals

Background Noise

Baseline

**Concentra**

*Concentrated*

*(NCI)*

Neural Signal

*‐ Non*

*Information*

**�on ↓** 

**Information**

**Figure 10.** Selecting quantization function for NCI, ICLA, and ICHA signals

Baseline

Figure 11. Neural signal composed of APs and B-Noise

Action Potentials

Baseline

for ICHA signals.

302 Advances in Bioengineering

**Logarithmic**

**Linear ADC**

**Quantization**

**Func**

**�on →** 

 **ADC**

**Exponential**

 **ADC**

**Figure 12.** Quantization of a neural signal with linear and nonlinear quantization steps

**Basic Idea**. As shown in Figure 11, in time domain a typical intracortically-recorded extracel‐ lular neural signal can be divided into two parts: action potentials (APs) and background noise (B-Noise). In probability density function (PDF) domain, APs are concentrated at large amplitudes while B-Noise is concentrated at small amplitudes. In a wide variety of neuro‐ scientific and neurophysiological studies, as well as in many neuroprosthetic applications, it is the APs that carry the useful information embedded in neural signals. As illustrated in Figure 12, in implantable neural recording microdevices, neural signals are usually digitized using linear ADCs, i.e., ADCs with linear quantization characteristics. This means that the non-useful B-Noise is digitized with the same resolution as the useful APs are. In other words, when telemetering a digitized neural signal, part of the outgoing bit-rate is wasted to carry the noise content present in the neural signal. In [29] the idea of digitizing neural signals using an ADC **Page No.** 

5 Eq. (1)

14 Fig. 13

17 Equa tion (11)

21 Table 1

21 Table 1

21 Table 1

21 Table 1

REFRENCES

Analog Input Signal

Digital Output

**Line** 

10 1 than that

**ADC**

ADC Characteristic

Analog Output

ADC Characteristic

Analog Input

2

1st row, 3rd column:

1st row, 4th column:

1st row, 5th column:

1st row, 6th column:

23 9 Neural Engineering laboratory,

Laboratory,

23 7 Integrated Silicon Systems (ISiS)

[x]

[x]

[x]

[x]

*k*

2 ln

<sup>1</sup> ( ) exp, *<sup>a</sup>*

**Log‐DAC Anti‐Log**

ADC+DAC Characteristic

DAC Characteristic

Digital Input

*a n*

<sup>1</sup>

17 2 (a) linear ADC (a) logarithmic ADC

DAC Characteristic

Analog Output

Digital Output Signal

ADC+DAC Characteristic

Analog Input

 

*<sup>P</sup> <sup>n</sup> HR <sup>N</sup> <sup>N</sup>* . <sup>2</sup>

[34]

[35]

[36]

[37]

 

2 <sup>1</sup> <sup>1</sup> ln

*n*

with non-uniform quantization steps has been proposed. According to the classification presented in the previous section, neural signals are categorized under Type-III (i.e., ICHA). Hence, the best type of nonlinearity function for the quantization of neural signals is signals with increasing slopes such as parabolic and exponential functions.

Digitizing neural signals using exponential ADC (exp-ADC) helps saving the bandwidth in wireless data telemetry between the implanted device and the external host. Data reduction for an 8-bit exp-ADC is 24% as compared with its linear counterpart. Along with data reduc‐ tion, anti-logarithmic quantization of neural signals significantly reduces the power consump‐ tion of the ADC, comparing with a standard linear ADC. This is due to less number of digital code transitions for the exp-ADC. Moreover, anti-logarithmic quantization increases the SNR of neural signal by reducing its noise content. **Proof Corrections Form Author(s) Name(s): Mohsen Judy, Alireza Akhavian and Farzad Asgarian Chapter Title: Data Reduction Techniques in Neural Recording Microsystems** 

**Converting Back to Analog.** The transfer characteristics for conventional linear analog-todigital-to-analog (A/D/A) conversion process is a linear function, i.e., analog input signal is digitized by a linear ADC and then is converted back to the analog domain using a linear DAC. On the other hand, in a nonlinear A/D/A conversion process, analog input signal is digitized by a nonlinear quantization function. As shown in Figure 13 to convert back to the analog domain, digital signal should be passed through a nonlinear DAC with exact inverse charac‐ teristic. The resulted A/D/A conversion transfer characteristic is similar to that of a linear A/D/A conversion process, except that the quantization steps are non-uniform. In the case of anti-logarithmic A/D/A conversion, quantization steps are decreasing in length along the input amplitude range. **PROOF CORRECTIONS FORM No. Delete Replace with** 8 21 Figure Figure 9

( 1) exp <sup>2</sup> exp <sup>2</sup> ( ) ,

 *Log HR <sup>N</sup> <sup>N</sup> <sup>a</sup> kn <sup>k</sup> <sup>n</sup> <sup>P</sup> <sup>n</sup>*

 

1

 **Figure 13.** Transfer characteristics of an anti-logarithmic A/D/A conversion

ADC+DAC Characteristic

Digital Output Signal

Figure 13. Transfer characteristics of an anti-logarithmic A/D/A conversion

**Log‐DAC Anti‐Log**

ADC+DAC Characteristic

DAC Characteristic

DAC Characteristic

Analog Output

**ADC**

ADC Characteristic

Analog Output

ADC Characteristic

Analog Input

Analog Input Signal

Digital Output

with non-uniform quantization steps has been proposed. According to the classification presented in the previous section, neural signals are categorized under Type-III (i.e., ICHA). Hence, the best type of nonlinearity function for the quantization of neural signals is signals

Digitizing neural signals using exponential ADC (exp-ADC) helps saving the bandwidth in wireless data telemetry between the implanted device and the external host. Data reduction for an 8-bit exp-ADC is 24% as compared with its linear counterpart. Along with data reduc‐ tion, anti-logarithmic quantization of neural signals significantly reduces the power consump‐ tion of the ADC, comparing with a standard linear ADC. This is due to less number of digital code transitions for the exp-ADC. Moreover, anti-logarithmic quantization increases the SNR

**Converting Back to Analog.** The transfer characteristics for conventional linear analog-todigital-to-analog (A/D/A) conversion process is a linear function, i.e., analog input signal is digitized by a linear ADC and then is converted back to the analog domain using a linear DAC. On the other hand, in a nonlinear A/D/A conversion process, analog input signal is digitized by a nonlinear quantization function. As shown in Figure 13 to convert back to the analog domain, digital signal should be passed through a nonlinear DAC with exact inverse charac‐ teristic. The resulted A/D/A conversion transfer characteristic is similar to that of a linear A/D/A conversion process, except that the quantization steps are non-uniform. In the case of anti-logarithmic A/D/A conversion, quantization steps are decreasing in length along the input

**Log-DAC Anti-Log**

ADC+DAC Characteristic

DAC Characteristic

Digital Input

( 1) exp <sup>2</sup> exp <sup>2</sup> ( ) ,

 *Log HR <sup>N</sup> <sup>N</sup> <sup>a</sup> kn <sup>k</sup> <sup>n</sup> <sup>P</sup> <sup>n</sup>*

DAC Characteristic

Analog Output

Digital Output Signal

ADC+DAC Characteristic

Analog Input

 

**ADC**

ADC Characteristic

Analog Output

1

with increasing slopes such as parabolic and exponential functions.

of neural signal by reducing its noise content.

**Proof Corrections Form** 

304 Advances in Bioengineering

**PROOF CORRECTIONS FORM**

**Author(s) Name(s): Mohsen Judy, Alireza Akhavian and Farzad Asgarian**

**Chapter Title: Data Reduction Techniques in Neural Recording Microsystems** 

8 21 Figure Figure 9

**Log‐DAC Anti‐Log**

ADC+DAC Characteristic

DAC Characteristic

Digital Input

17 2 (a) linear ADC (a) logarithmic ADC

<sup>1</sup>

*a n*

DAC Characteristic

Analog Output

10 1 than that

**ADC**

ADC Characteristic

Analog Output

ADC Characteristic

Analog Input

2

1st row, 3rd column:

1st row, 4th column:

1st row, 5th column:

1st row, 6th column:

23 9 Neural Engineering laboratory,

Laboratory,

23 7 Integrated Silicon Systems (ISiS)

[x]

[x]

[x]

[x]

*k*

2 ln

<sup>1</sup> ( ) exp, *<sup>a</sup>*

**Page No.** 

5 Eq. (1)

14 Fig. 13

17 Equa tion (11)

21 Table 1

21 Table 1

21 Table 1

21 Table 1

REFRENCES

Analog Input Signal

Digital Output

**Line** 

amplitude range.

Digital Output Signal

Analog Input Signal

> Digital Output

ADC Characteristic

Analog Input

**Figure 13.** Transfer characteristics of an anti-logarithmic A/D/A conversion

ADC+DAC Characteristic

Analog Input

 

*<sup>P</sup> <sup>n</sup> HR <sup>N</sup> <sup>N</sup>* . <sup>2</sup>

[34]

[35]

[36]

[37]

2 <sup>1</sup> <sup>1</sup> ln

*n*

**No. Delete Replace with**

Figure 14. An FR-ADC designed to digitize neural signals using two HR-ADCs with exponential quantization function **Figure 14.** An FR-ADC designed to digitize neural signals using two HR-ADCs with exponential quantization function

Dummy Text **Covering the Full Range**. Assuming that the neural signal is preamplified and positioned around a certain baseline level, as illustrated in Figure 14, the nonlinear quantization function needs to be defined in an odd symmetric form around the baseline of the signal. Therefore, the nonlinear ADC needed to cover the entire input signal range, fullrange ADC (FR-ADC), is realized using two complimentary half-range ADCs (HR-ADCs) each covering half of the input signal range. Hence, assuming that the basic nonlinear quantization function is used for the upper half-range ADC (UHR-ADC), fUHR(x), the quantization function used for the lower half-range ADC (LHR-ADC) will be: f x =- f -x . LHR UHR (3) **Covering the Full Range**. Assuming that the neural signal is preamplified and positioned around a certain baseline level, as illustrated in Figure 14, the nonlinear quantization function needs to be defined in an odd symmetric form around the baseline of the signal. Therefore, the nonlinear ADC needed to cover the entire input signal range, full-range ADC (FR-ADC), is realized using two complimentary half-range ADCs (HR-ADCs) each covering half of the input signal range. Hence, assuming that the basic nonlinear quantization function is used for the upper half-range ADC (UHR-ADC), fUHR(x), the quantization function used for the lower halfrange ADC (LHR-ADC) will be:

$$\mathbf{f}\_{\rm LHR}\left(\mathbf{x}\right) = \mathbf{f}\_{\rm UHR}\left(\cdot \mathbf{x}\right). \tag{3}$$

Dummy Text **Half-Range Characteristic Function.** The input-output relationship for an N-bit HR-ADC with exponential quantization function is: The nonlinear ADC discussed hereafter is assumed to be the ADC that covers the upper half of the input signal range, i.e., the UHR-ADC, unless otherwise stated.

.[exp( ) 1], <sup>2</sup> 2 ... <sup>0</sup> 1 <sup>1</sup> *k V v a b b FS in N N N* (4) **Half-Range Characteristic Function.** The input-output relationship for an N-bit HR-ADC with exponential quantization function is:

$$\frac{b\_{N-1}\mathcal{Z}^{N-1} + \dots + b\_0}{\mathcal{Z}^N} = a. \text{[exp}(\frac{\nu\_{is}}{V\_{S\bar{S}}} \times k) - 1\text{]},\tag{4}$$

where (*bN-1...b1b0*) is digital representation of analog input, *vin*, and *VFS* is the full-scale input range for the UHR-ADC. To satisfy the boundary conditions for minimum and maximum values of *vin* it can be shown that:

$$k = \ln(\frac{1}{a} + l). \tag{5}$$

Parameter *a* sets the curvature of the characteristic function. The smaller this parameter is, the more rapid the exponential input-output relationship will be. Quantization steps along the input range are known, in general, as least significant bits (LSB), and are calculated as:

$$V\_{LSB,i} = \frac{V\_{FS}}{k} \ln\left(\frac{1}{i + a\,\mathbf{2}^N} + \mathbf{l}\right) \tag{6}$$

for *i=0,1,...,2N-1.* The largest and the smallest quantization steps, *LSBmax* and *LSBmin*, are calculated using eq.(6) for *i=0* and *2N-1*, respectively, as:

$$V\_{LS9,\max} = \frac{V\_{FS}}{k} \ln\left(\frac{1}{a\mathcal{Q}^N} + \mathcal{l}\right) \tag{7}$$

and

$$V\_{LSB,\min} = \frac{V\_{FS}}{k} \ln\left(\frac{1}{(a+l)2^N - 1} + l\right). \tag{8}$$

In general, dynamic range (DR) of a nonlinear ADC is defined to be the ratio of the full-scale input voltage to the smallest resolvable signal, VLSB,min [32]. DR in the case of exp-ADC is achieved as:

$$DR = \frac{V\_{FS}}{V\_{LSB,\min}} = \frac{k}{\ln\left(\frac{1}{(a+1)2^N - 1} + 1\right)}.\tag{9}$$

The choice of the largest quantization step, VLSB,max, is perhaps the most critical decision in forming the quantization function for the exp-ADC. This is because of its key role in the reduction of the noise content of the neural signal. The largest LSB is responsible for the largest quantization error. It is along the VLSB,max that variations of the input signal are intentionally not seen and replaced with 0 (the baseline level in our design). By using this method, not only the quantization error is not a disturbing phenomenon for the signal, but it also plays a denoising role as it replaces the B-Noise around the baseline with 0. To achieve significant reduction in the B-Noise power, VLSB,max is set to 3σ, where σ is the standard deviation of the B-Noise PDF. This way, most of the B-Noise will be intentionally removed from the neural signal during the digitization process.

<sup>1</sup> *<sup>k</sup>* ln( 1). *<sup>a</sup>* = + (5)

è ø <sup>+</sup> (6)

è ø (7)

è ø + (8)

(9)

Parameter *a* sets the curvature of the characteristic function. The smaller this parameter is, the more rapid the exponential input-output relationship will be. Quantization steps along the input range are known, in general, as least significant bits (LSB), and are calculated as:

> <sup>1</sup> ln 1 2

for *i=0,1,...,2N-1.* The largest and the smallest quantization steps, *LSBmax* and *LSBmin*, are

<sup>1</sup> ln 1 2

<sup>1</sup> ln 1 . ( 1)2 1

In general, dynamic range (DR) of a nonlinear ADC is defined to be the ratio of the full-scale input voltage to the smallest resolvable signal, VLSB,min [32]. DR in the case of exp-ADC is

> *a* = = æ ö

The choice of the largest quantization step, VLSB,max, is perhaps the most critical decision in forming the quantization function for the exp-ADC. This is because of its key role in the reduction of the noise content of the neural signal. The largest LSB is responsible for the largest quantization error. It is along the VLSB,max that variations of the input signal are intentionally not seen and replaced with 0 (the baseline level in our design). By using this method, not only the quantization error is not a disturbing phenomenon for the signal, but it also plays a denoising role as it replaces the B-Noise around the baseline with 0. To achieve significant reduction in the B-Noise power, VLSB,max is set to 3σ, where σ is the standard deviation of the B-Noise PDF. This way, most of the B-Noise will be intentionally removed from the neural

æ ö = + ç ÷

> . <sup>1</sup> ln <sup>1</sup> ( 1)2 1

*N*

ç ÷ + è ø +

,

calculated using eq.(6) for *i=0* and *2N-1*, respectively, as:

and

306 Advances in Bioengineering

achieved as:

*<sup>V</sup> <sup>V</sup>*

,max

*FS LSB N*

,min

*V k DR*

*FS LSB*

*V*

signal during the digitization process.

*k a*

,min

*<sup>V</sup> <sup>V</sup>*

*<sup>V</sup> <sup>V</sup>*

*FS LSB i N*

*k ia* æ ö = + ç ÷

*FS LSB N*

*k a* æ ö = + ç ÷

*Noise Analysis.* PDF of quantization noise (Q-Noise) for linear ADC is uniform along the input amplitude range. This can be shown by eq. (10) which formulates PDF of the Q-Noise associated with **Figure 15.** Q-Noise PDF for (a) logarithmic ADC and (b) exp-ADC; (c) Q-Noise for exp-ADC vs. B-Noise of a neural signal

of a neural signal

Figure 15. Q-Noise PDF for (a) linear ADC and (b) exp-ADC; (c) Q-Noise for exp-ADC vs. B-Noise

code n in an N-bit linear HR-ADC [30]: . <sup>2</sup> 1 2 1 2 2 <sup>1</sup> ( ) , <sup>1</sup> *Lin HR <sup>N</sup> <sup>N</sup> <sup>N</sup> <sup>n</sup> <sup>n</sup> <sup>P</sup> <sup>n</sup>* (10) **Noise Analysis.** PDF of quantization noise (Q-Noise) for linear ADC is uniform along the input amplitude range. This can be shown by eq. (10) which formulates PDF of the Q-Noise associ‐ ated with code n in an N-bit linear HR-ADC [30]:

$$P\_{La,HR}(n) = \frac{1}{2} \left[ \left( \frac{n}{2^N} \right) - \left( \frac{n-1}{2^N} \right) \right] = \frac{1}{2^{N+1}}.\tag{10}$$

N-bit logarithmic HR-ADC is formulated in eq. (11) and is illustrated in Figure 15(a): <sup>1</sup> . <sup>2</sup> <sup>1</sup> <sup>1</sup> ln 2 ln 2 <sup>1</sup> ( ) exp, *a n a n k P n HR <sup>N</sup> <sup>N</sup>* (11) In the case of the anti-logarithmic N-bit HR-ADC, the Q-Noise PDF associated with code n is derived as: <sup>1</sup> . <sup>2</sup> <sup>1</sup> <sup>1</sup> ln ln <sup>1</sup> ( ) , *n n P n Exp HR <sup>N</sup> <sup>N</sup>* (12) Uniform distribution of Q-Noise along the input amplitude makes linear ADCs suitable for digitizing NCI signals. For specific signals an NLADC might be useful in terms of SNR improvement. This advantage comes from the fact that NLADCs exhibit non-uniform Q-Noise distribution. In a Logarithmic ADC, Q-Noise energy is shifted to large amplitudes. As a result, logarithmic ADC has widely been used in digitizing of ICLA signals, such as audio. PDF of Q-noise associated with code n for an N-bit logarithmic HR-ADC is formulated in eq. (11) and is illustrated in Figure 15(a):

2

*a*

2

*k*

been used in digitizing of ICLA signals, such as audio. PDF of Q-noise associated with code n for an

$$P\_{L\text{og},HR}(n) = \frac{a}{2} \left[ \exp\left(\frac{kn}{2^N}\right) - \exp\left(\frac{k(n-1)}{2^N}\right) \right].\tag{11}$$

*a*

In the case of the anti-logarithmic N-bit HR-ADC, the Q-Noise PDF associated with code n is derived as:

$$P\_{Exp,HR}(n) = \frac{1}{2k} \left[ \ln \left( \frac{n}{2^N a} + 1 \right) - \ln \left( \frac{n-1}{2^N a} + 1 \right) \right]. \tag{12}$$

As shown in Figure 15(b), exp-ADC shapes the Q-Noise in such a way that most of its energy concentrates at small amplitudes, making it suitable for digitizing ICHA signals. As an example, in neural signals, APs with large amplitudes are quantized with higher SQNR as opposed to the B-Noise with rather small amplitudes. Figure 15(c) illustrates that most of the noise content of the signal (B-Noise) lies within the very first LSBs. The interesting point here is that since it is some of the noise content of the neural signal that is lost during the quantization process, not only the associated quantization error is not undesirable, but it is also welcomed as it leads to noise-content reduction and consequently to significant improvement in the SNR of the neural signal being digitized.

*Noise-Content-Reduction Ratio*, *NCRR*, is a measure of capability of an ADC in reducing the noise content of the neural signal being digitized, and can be defined as [29]:

$$\text{NCRR (dB)} = 10 \log\_{10} \left( \frac{\text{average noise power (\overline{a}\) input}}{\text{average noise power (\overline{a}\) output}} \right) \tag{13}$$

where the average noise power at the input of the ADC is calculated as:

$$\overline{\left(n\_i^{\;2}(t)\right)} = \overline{\int\_{-\infty}^{\ast \infty} n\_i^{\;2}(t) P\_{n\_i}(n\_i) dn\_i} \tag{14}$$

In this equation, *Pni(ni )* is the probability density function for noise content of the neural signal, *ni (t)*. Similarly, the average noise power of the signal at the output of the ADC is derived to be:

$$\overline{\ln\_o^2(t)} = \overline{\int\_{-\infty}^{\ast \cdot \alpha} n\_o^{\ast \cdot \ast}(t) P\_{n\_i}(n\_i) dn\_o} \tag{15}$$

where *no(t)* is the noise content of the neural signal after passing through the ADC:

$$n\_o(t) = n\_i(t) \times \left[ \text{ADCCharacteristic Curve} \right]. \tag{16}$$

Figure 16 illustrates how the B-Noise is reduced as it passes through the exp-ADC, already formulated by equations (14)-(16).

In the case of the anti-logarithmic N-bit HR-ADC, the Q-Noise PDF associated with code n is

1 1 ( ) ln 1 ln 1 . 22 2 *Exp HR N N*

*ka a*

As shown in Figure 15(b), exp-ADC shapes the Q-Noise in such a way that most of its energy concentrates at small amplitudes, making it suitable for digitizing ICHA signals. As an example, in neural signals, APs with large amplitudes are quantized with higher SQNR as opposed to the B-Noise with rather small amplitudes. Figure 15(c) illustrates that most of the noise content of the signal (B-Noise) lies within the very first LSBs. The interesting point here is that since it is some of the noise content of the neural signal that is lost during the quantization process, not only the associated quantization error is not undesirable, but it is also welcomed as it leads to noise-content reduction and consequently to significant improvement in the SNR

*Noise-Content-Reduction Ratio*, *NCRR*, is a measure of capability of an ADC in reducing the

æ ö <sup>=</sup> ç ÷

*(t)*. Similarly, the average noise power of the signal at the output of the ADC is derived to

noise content of the neural signal being digitized, and can be defined as [29]:

10

where the average noise power at the input of the ADC is calculated as:

2 2 () () ( ) *<sup>i</sup> <sup>i</sup> i ni i n t n t P n dn* +¥

2 2 () () ( ) *<sup>i</sup> <sup>o</sup> o ni o n t n t P n dn* +¥

where *no(t)* is the noise content of the neural signal after passing through the ADC:

( ) ( ) ´ ù û = é

average noise power @ input NCRR (dB) 10log average noise power @ output

é ù æ öæ ö = + + ê ú ç ÷ç ÷ ë û è øè ø (12)

è ø (13)

¥ <sup>=</sup> ò (14)

¥ <sup>=</sup> ò (15)

*)* is the probability density function for noise content of the neural signal,

ë . *o i n t n t ADC Characteristic Curve* (16)

*n n P n*

derived as:

308 Advances in Bioengineering

,

of the neural signal being digitized.

In this equation, *Pni(ni*

*ni*

be:

**Figure 16.** The process of B-Noise reduction as the signal passes through the NLADC, formulated by eqs. (14)-(16)

**Figure 17.** Circuit schematic for the two-step SAR ADC designed to implement exp-ADC and its simplified timing dia‐ gram

**Circuit Design.** To realize the proposed exp-ADC with reasonable power and silicon area, successive-approximation register (SAR) architecture was chosen [31]. In order to facilitate the realization of the exponential quantization function needed for the ADC, a piecewise-linear (PWL) approximation of the required function was implemented. As shown in the timing diagram of Figure 17, the proposed ADC operates in three phases: sign detection (SD), offset cancelation (OC), and conversion. In the SD phase, the analog input voltage, vin, is compared with a certain threshold voltage, VTH, which is temporarily set to the baseline voltage, VBL. The result of this comparison determines the half range in which the input voltage is located. In the OC phase, an ordinary offset cancellation technique is applied on the comparator and buffers. In the conversion phase, successive approximation algorithm first finds the segment of interest, encoded by b6b5b4, in 3 clock cycles. These 3 bits are converted to a 7-bit thermometer code, T7~T1, which will be used in the *Segment Selection* block to generate two analog voltages associated with the endpoints of the segment of interest. An in-segment linear A/D conversion process is then performed to determine the remained 4 LSBs, b3b2b1b0, in 4 clock cycles. Finally, an end of conversion signal is generated to reset the ADC and prepare for the next conversion cycle. A low-voltage band-gap reference (BGR) was designed to generate the required baseline, reference and threshold voltages for the exp-ADC. As shown in the timing diagram of Figure 17, the proposed ADC operates in three phases: sign detection (SD), offset cancelation (OC), and conversion. In the SD phase, the analog input voltage, vin, is compared with a certain threshold voltage, VTH, which is temporarily set to the baseline voltage, VBL. The result of this comparison determines the half range in which the input voltage is located. In the OC phase, an ordinary offset cancellation technique is applied on the comparator and buffers. In the conversion phase, successive approximation algorithm first finds the segment of interest, encoded by b6b5b4, in 3 clock cycles. These 3 bits are converted to a 7-bit thermometer code, T7~T1, which will be used in the Segment Selection block to generate two analog voltages associated with the endpoints of the segment of interest. An in-segment linear A/D conversion process is then performed to determine the remained 4 LSBs, b3b2b1b0, in 4 clock cycles. Finally, an end of conversion signal is generated to reset the ADC and prepare for the next conversion cycle. A low-voltage band-gap reference (BGR) was designed to generate the required baseline, reference and threshold voltages

for the exp-ADC.

Figure 16. The process of B-Noise reduction as the signal passes through the NLADC, formulated by eqs. (14)-(16)

**In-Segment Digitization** 

8Cb 2Cb Cb Cb 4Cb

b3 b1 b0 b2

SD Phase OC Phase

**V** PH1 **in** 

ADC Characteristic curve

Background

Input average

noise PDF Pni(ni

noise power ni

Output average no noise power 2 (t) Pni(ni

VLSB,max

**Segment Selection** 

1.67Cu

1.15Cu

T7

1.15Cu

Cu

Cu

1.36Cu

1.36Cu

T1 T2 T3 T4 T5 T6

2.15Cu

2.15Cu

3.02Cu

3.02Cu

**VREF VBL**

T1 T2 T3 T4 T5 T6 T7

1.67Cu

Analog Input (ni

Baseline

)

PH1

 **Vin** PH2

> **PH0 PH1 PH2**

**CLK** 

PH0

PH1

**VBL**

PH1

UGB

UGB

)

<sup>2</sup> (t) Pni(ni )

PH1

19.11Cu

5.14Cu

5.14Cu

PH2

19.11Cu

**VREF** 

**VBL**

Digital Output (no)

)

Figure 17. Circuit schematic for the two-step SAR ADC designed to implement exp-ADC and its simplified timing diagram

Dummy Text **Circuit Design.** To realize the proposed exp-ADC with reasonable power and silicon area, successiveapproximation register (SAR) architecture was chosen [31]. In order to facilitate the realization of the exponential quantization function needed for the ADC, a piecewise-linear (PWL) approximation of the required function was implemented.

Segment Selection b6 b5 b4 b7

**VTH** 

T7-T1

In-Segment Digitization b3 b2 b1 b0

Conversion Phase

**SAR & Switch Control Logic** 

b3-b0 b7-b0

SAR b7- b0

Binary to Thermometer Converter

> End of Conversion

Digital Output

b6 - b4

**Figure 18.** Chip photograph of the proposed NLADC

**Experimental Results.** The presented exp-ADC was fabricated in a standard 0.18-μm CMOS process. A chip photograph is shown in Figure 18, in which the chip occupies a total size of 220 ×230 μm2 . The measured worst-case differential non-linearity (DNL) and integral nonlinearity (INL) are +0.8/-0.9 LSB and +4.3/-2.1 LSB, respectively. Table 1 summarizes the specifications of the NLADC and compares it with some of the nonlinear and linear ADCs reported in the literature.

A proof-of-concept prototype of a 4-channel neural recording system based on anti-logarithmic quantization was reported in [6]. As shown in the block diagram of Figure 19, a time-domain multiplexer (TDM) shares an anti-logarithmic ADC (AL-ADC) between 4 channels (each sampled at 20kSps). The output digital codes are then packed by the data packaging block to be transmitted to the outside world via a wireless link. At the external host, received signal is first recovered and then converted back to analog via a PC software. This inverse conversion is performed using a logarithmic DAC. Quantization characteristic function for the DAC is an exact inverse for that of the NLADC used in the recording system. To evaluate the operation of the system, neural signals recorded from the auditory cortex of a Guinea pig are used for in-vitro tests. Figure 20 shows the input signal to one of the neural channels before entering the nonlinear quantization process on the implant side along with the associated signal on the external setup after reconstruction. To verify the concept of the noise reduction caused by As shown in the timing diagram of Figure 17, the proposed ADC operates in three phases: sign detection (SD), offset cancelation (OC), and conversion. In the SD phase, the analog input voltage, vin, is compared with a certain threshold voltage, VTH, which is temporarily set to the baseline voltage, VBL. The result of this comparison determines the half overlapping PDFs for B-Noise and Q-Noise, distributions of the measured quantization error along the input amplitude are depicted in Figure 21.

**Figure 19.** Block diagram of the prototyped neural recording system


**Table 1.** Performance Comparison
