**1. Introduction**

Nowadays, implantable devices developed for electrically interfacing to the brain are of great interest. Such devices, also known as *brain-machine interfaces (BMI)*, are expected to revolu‐ tionalize so many aspects of the human life, such as the way we interface with the external world, and how we cure deseases and disabilities such as the Parkinson's desease, paralysis, and blindness. General concept of intra-cortical neural recording using implantable microsys‐ tems along with an example of such systems is illustrated in Figure 1. In a wide variety of applications for such systems, there is a need for recording neural activities from a certain region of the brain with enough spatial resolution. To be able to come up with meaningful information from the region of interest in the brain, implantable neural recording devices are typically designed to record from tens to hundreds of recording sites [1-3].

#### **1.1. General building blocks**

A neural recording system, in general, comprises two parts: a neural recording implant, and an external setup. Implantable cortical neural recoding microsystems (the implant) typically consist of three main parts:


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Figure 1. (a) Intra-cortical neural recording using an implantable microsystem [6] (b) a 64-channel neural recording microsystem developed at the University of Michigan [1] **Figure 1.** (a) Intra-cortical neural recording using an implantable microsystem [6] (b) a 64-channel neural recording microsystem developed at the University of Michigan [1]

**• wireless interface module;** This module is used for data exchange with the external setup and in some cases for supporting power telemetry from the outside to the implant. *- wireless interface module;* This module is used for data exchange with the external setup and in some cases for supporting power telemetry from the outside to the implant.

#### **1.2. Challenges in the development of high-density neural recording microsystems Challenges in the development of high-density neural recording microsystems**

As the number of recording channels for a wireless neural recording microsystem increases, many aspects of the design of the system will be challenging. From among the more important design challenges, one can point to the low power consumption and small physical dimensions of the system. For tens to hundreds of recording channels, transferring a huge amount of neural

Figure 2. Passive silicon probes with four 20mx20m recording sites [5] **Figure 2.** Passive silicon probes with four 20μmx20μm recording sites [5]

data through a wireless link is also a design bottleneck. This is simply due to the fact that an implantable neural recording device needs to transmit the recorded neural information to the external world through wireless connection, and the frequency band used for wireless communication is not unlimited. One of the efficient ways to overcome this problem is to either compress the data being telemetered or at least to extract and transmit only the useful information needed for the target application. *- neural signal processing module;* This is where most of the signal handling and signal processing tasks take place, e.g., analog signal processing, analog/digital conversion, and digital signal processing. *- wireless interface module;* This module is used for data exchange with the external setup and in some cases for supporting power telemetry from the outside to the implant.

**Challenges in the development of high-density neural recording microsystems** 

#### **2. Spike reporting** As the number of recording channels for a wireless neural recording microsystem increases, many

**• wireless interface module;** This module is used for data exchange with the external setup and in some cases for supporting power telemetry from the outside to the implant.

(b)

**Figure 1.** (a) Intra-cortical neural recording using an implantable microsystem [6] (b) a 64-channel neural recording

(a)

*- wireless interface module;* This module is used for data exchange with the external setup and in

As the number of recording channels for a wireless neural recording microsystem increases, many aspects of the design of the system will be challenging. From among the more important design challenges, one can point to the low power consumption and small physical dimensions of the system. For tens to hundreds of recording channels, transferring a huge amount of neural

**1.2. Challenges in the development of high-density neural recording microsystems**

**Challenges in the development of high-density neural recording microsystems** 

Figure 1. (a) Intra-cortical neural recording using an implantable microsystem [6] (b) a 64-channel neural recording microsystem developed at the University

some cases for supporting power telemetry from the outside to the implant.

of Michigan [1]

292 Advances in Bioengineering

microsystem developed at the University of Michigan [1]

An intra-cortically-recorded neural signal, in general, comprises three major components: *action potentials* (also known as *neural spikes* or simply *spikes*), *local field potential (LFP)*, and *background noise*. It is believed that most of the important information in neural signals is reflected in the occurrence rate of neural spikes. As a result, in some applications (e.g., prosthetic applications) only the occurrence of spikes is detected and reported to the external world. In some other applications (e.g., neuroscientific research), however, researchers and scientists need more information on how or where the neural activities occur. challenges, one can point to the low power consumption and small physical dimensions of the system. For tens to hundreds of recording channels, transferring a huge amount of neural data through a wireless link is also a design bottleneck. This is simply due to the fact that an implantable neural recording device needs to transmit the recorded neural information to the external world through wireless connection, and the frequency band used for wireless communication is not unlimited. One of the efficient ways to overcome this problem is to either compress the data being telemetered or at least to extract and transmit only the useful information needed for the target application.

aspects of the design of the system will be challenging. From among the more important design

Recording the entire neural signal (action potentials superposed with background noise) is the maximum function expected from a general neural recording system, which allows for studying different components of a neural signal including the background noise. For multichannel wireless neural recording implants, because of the limited bandwidth available for transmitting the neural data, the number of recording channels will be limited if the entire signal is intended to be telemetered. In many applications, the rate of spike occurrence is the most important information that is expected from a neural recording system to provide. Hence, it will be much more bandwidth-efficient if the spikes are detected by the implanted recording system and only the occurrences of the spikes are reported to the external host rather than transmitting the entire neural signal. SPIKE REPORTING An intra-cortically-recorded neural signal, in general, comprises three major components: *action potentials* (also known as *neural spikes* or simply *spikes*), *local field potential (LFP)*, and *background noise*. It is believed that most of the important information in neural signals is reflected in the occurrence rate of neural spikes. As a result, in some applications (e.g., prosthetic applications) only the occurrence of spikes is detected and reported to the external world. In some other applications (e.g., neuroscientific research), however, researchers and scientists need more information on how or where the neural activities occur. Recording the entire neural signal (action potentials superposed with background noise) is the maximum function expected from a general neural recording system, which allows for studying different components of a neural signal including the background noise. For multi-channel wireless neural recording implants, because of the limited bandwidth available for transmitting the neural data, the

number of recording channels will be limited if the entire signal is intended to be telemetered. In many

#### **2.1. Spike detection**

In addition to the small action potentials with the amplitude of around 100~500μV, a neural signal contains background noise and probably low-frequency baseline variations. To prepare the neural signal for spike detection, it is amplified with a gain of around 40~60dB and also its low-frequency (below 1~10Hz) and high-frequency (above 7~10kHz) contents are filtered out [7], [2]. Then, this preconditioned signal is delivered to a spike detector.

There are various spike detection approaches that can be classified into two major categories: feature-based spike detection methods, and spike detection by hard thresholding. In the former, a preprocessor searches the input neural signal for certain features of a spike to occur, while in the latter, a threshold level is defined and a spike is detected when the neural signal goes beyond the threshold.

**Feature-Based Approaches.** Only a few years after artificial neural networks (ANN's) were introduced as an efficient tool to implement artificial intelligence, due to the feature extraction capability that certain types of ANN's had, they showed to be attractive candidates for automatic spike detection either by themselves or in conjunction with preprocessors [8-9]. Kohonen and Grossberg networks with unsupervised learning, and Multi-Layered Perceptron network with "error back-propagation" as a supervised learning algorithm have been used to perform spike detection. Although there are cases where the raw neural signal is fed to the ANN for spike detection [9-10], it is mostly preferred to use a preprocessor for extracting certain spike features first, and then use an ANN for processing them and detecting the spikes, as illustrated in Figure 3. Because of their relatively large area- and power-consuming electronic implementations, this class of spike processors has never been used in implantable neural recording microsystems.

**Figure 3.** Employing neural networks for spike detection

**Spike Detection Based on Nonlinear Energy Operator (NEO).** Traditional spike detectors (explained above) usually need prior information about action potentials, which is usually not available before recording the neural signals in real applications. In contrast with these methods, which are mostly based on the amplitude or time-domain features of the neural signal, detection of action potentials, i.e., spikes, can also be performed based on the energy content of the signal. Direct square of the signal, absolute value operator, and variance estimator are the energy-based operators commonly used for the detection of bio-potentials. The nonlinear energy operator (NEO), also called the Teager energy operator (TEO) is one of the unsupervised action potential detectors exhibiting satisfactory performance in the case of low signal-to-noise ratio (SNR) for the neural signal and also convincing speed for the alignment of spikes in the real time. In its original form, continuous-time NEO is defined as:

$$
\psi\left(\mathbf{x}(t)\right) = \left(\frac{d\mathbf{x}(t)}{dt}\right)^2 - \mathbf{x}\left(t\right)\left(\frac{d^2\mathbf{x}(t)}{dt^2}\right). \tag{1}
$$

which is sensitive to signal with short time interval and at a high-frequency band [11]. An efficient hardware implementation for an NEO neural signal processor employing custom OTA1 -C analog circuits was reported in [12].

#### **2.2. Hard thresholding**

**2.1. Spike detection**

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goes beyond the threshold.

neural recording microsystems.

In addition to the small action potentials with the amplitude of around 100~500μV, a neural signal contains background noise and probably low-frequency baseline variations. To prepare the neural signal for spike detection, it is amplified with a gain of around 40~60dB and also its low-frequency (below 1~10Hz) and high-frequency (above 7~10kHz) contents are filtered out

There are various spike detection approaches that can be classified into two major categories: feature-based spike detection methods, and spike detection by hard thresholding. In the former, a preprocessor searches the input neural signal for certain features of a spike to occur, while in the latter, a threshold level is defined and a spike is detected when the neural signal

**Feature-Based Approaches.** Only a few years after artificial neural networks (ANN's) were introduced as an efficient tool to implement artificial intelligence, due to the feature extraction capability that certain types of ANN's had, they showed to be attractive candidates for automatic spike detection either by themselves or in conjunction with preprocessors [8-9]. Kohonen and Grossberg networks with unsupervised learning, and Multi-Layered Perceptron network with "error back-propagation" as a supervised learning algorithm have been used to perform spike detection. Although there are cases where the raw neural signal is fed to the ANN for spike detection [9-10], it is mostly preferred to use a preprocessor for extracting certain spike features first, and then use an ANN for processing them and detecting the spikes, as illustrated in Figure 3. Because of their relatively large area- and power-consuming electronic implementations, this class of spike processors has never been used in implantable

> . . .

Extracted Features

Input Output

**Spike Detection Based on Nonlinear Energy Operator (NEO).** Traditional spike detectors (explained above) usually need prior information about action potentials, which is usually not available before recording the neural signals in real applications. In contrast with these methods, which are mostly based on the amplitude or time-domain features of the neural signal, detection of action potentials, i.e., spikes, can also be performed based on the energy content of the signal. Direct square of the signal, absolute value operator, and variance

**Preprocessor** 

**for** 

**Feature** 

**Extraction** 

**Figure 3.** Employing neural networks for spike detection

**ANN** 

[7], [2]. Then, this preconditioned signal is delivered to a spike detector.

Four possible ways of spike detection by hard thresholding are illustrated in Figure 4. Spike detection is mostly performed to detect either positive (Figure 4 (a)) or negative (Figure 4 (b)) spikes [7], [2], [13]. Having such a fixed pre-assumption for the polarity of the spikes limits the operation of the system. Recognition of both positive and negative spikes, i.e., bi-phasic spike detection, can be realized in two major ways, illustrated in Figure 4 (c) and (d). In Figure 4 (c), the spike detector returns a logical "1" on the Spike Occurrence (S.O.) output upon the detection of a spike, no matter if it is positive or negative. This is a bandwidth-efficient way of bi-phasic spike detection, which requires almost the same bandwidth as the uni-phasic methods, but pays the price by losing the spike polarity. The simplest realization of this idea is to filter out the DC component of the input signal, find its absolute value, and then detect the spikes using one comparator and one threshold [14] as shown in Figure 5(a). Aside from the need for a precise full-wave rectifier in this realization, the fact that both the positive and the negative spikes are compared with the same threshold level might be considered as a drawback. Figure 5 (b) shows another realization of bi-phasic spike detection with no polarity, which uses two comparators and an OR gate and also allows for comparing positive and negative spikes with separate threshold levels. This approach is used in [7],[13] with positive and negative thresholds, VTH,P and VTH,N, defined by a threshold value (THR) and a threshold offset (ThrOS), as shown in Figure 6.

The circuit shown in Figure 5 (b) can also be used with minor modifications to realize the complete bi-phasic spike detection method illustrated in Figure 4 (d), which returns two bits per detected spike. These two bits can be either Spike Occurrence (S.O.) and Spike Polarity (S.P.) as shown, or one bit assigned to detected positive spikes and the other to detected negative spikes.

<sup>1</sup> Operational Transconductor Amplifier

**Figure 4.** Spike detection approaches (a) Positive (b) Negative (c) Simple bi-phasic (d) Bi-phasic with spike polarity [13]

Figure 4. Spike detection approaches (a) Positive (b) Negative (c) Simple bi-phasic

S.O. S.O .

(c ) (d)

(d) Bi-phasic with spike polarity [13]

There is a variety of methods for generating the thresholds required for spike detection. The threshold

can be either statically defined by the user [2], [13] or automatically set by the internal circuitry.

Figure 5. Implementations of biphasic spike detection with no polarity **Figure 5.** Implementations of biphasic spike detection with no polarity

There is a variety of methods for generating the thresholds required for spike detection. The threshold can be either statically defined by the user [2], [13] or automatically set by the internal circuitry.

VTH,P

VTH,P

(a ) (b)

S.O. S.O.

V TH,P

(a) (b)

VTH,N

V TH,P

S.O. S.O .

V TH ,N

S.O. S.P.

(c ) (d)

Figure 4. Spike detection approaches (a) Positive (b) Negative (c) Simple bi-phasic

DC Rejection

VTH,P

VTH,N

*Input* 

*Input* 

S.O . S.P.

(d) Bi-phasic with spike polarity [13]

296 Advances in Bioengineering

(c) (d)

There is a variety of methods for generating the thresholds required for spike detection. The threshold

(b)

can be either statically defined by the user [2], [13] or automatically set by the internal circuitry.

Figure 5. Implementations of biphasic spike detection with no polarity

**Figure 5.** Implementations of biphasic spike detection with no polarity

**Figure 4.** Spike detection approaches (a) Positive (b) Negative (c) Simple bi-phasic (d) Bi-phasic with spike polarity [13]

ABS

VTH

*Detected Positive Spikes* 

*Detected Negative Spikes* 

(a)

S.O.

S.O .

VTH,N

V TH,N

VTH,P

VTH,N

V TH,P

V TH,N

*Output* 

*Output* 

**Automatic Threshold Setting.** The 32-channel spike detector ASIC reported by [7] uses a straightforward approach for automatic threshold generation. In this method, the average (AVG) and the standard deviation (SD) of the neural signal is calculated, and then the two thresholds required for bi-phasic spike detection are set above and below the average value as:

$$\text{THR} \newline \text{AVG} \newline \pm \text{k.SD} \newline \tag{2}$$

where k is a constant. Typical value for k varies from 3 to 7 depending on the signal-to-noise ratio (SNR) of the recorded neural signal. Functional block diagram of this spike processor implementing the above method in digital domain is shown in Figure. Thirty two channels of preconditioned neural signals, which are already time-division multiplexed on four lines in analog domain by a recording front-end (not shown), are delivered to the spike detector ASIC. The four multiplexed inputs each carrying 8 channels of neural signals are first converted to digital by four A/D converters simultaneously. The *Sample Distributor*, which is synchronized with the time-division multiplexer on the recording front-end, demultiplexes the amplitude samples into 32 digital neural channels. Then, the digital spike detector computes the averages and standard deviations of the 32 channels separately and accordingly calculates their threshold values. After the *Threshold Calculation* program is executed, the *Spike Detection* program is run. The amplitude sample of each channel is compared to the associated threshold, and if it is beyond the threshold level, it is considered as a detected spike. As long as a channel is active, its amplitude samples are tagged with the associated channel address, and put in a buffer to be sent to a wireless interface.

offset (ThrOS) [13] **Figure 6.** Defining positive and negative thresholds using a threshold value (THR) and an offset (ThrOS) [13]

Figure 6. Defining positive and negative thresholds using a threshold value (THR) and an

wireless interface.

where k is a constant. Typical value for k varies from 3 to 7 depending on the signal-to-noise ratio (SNR) of the recorded neural signal. Functional block diagram of this spike processor implementing the above method in digital domain is shown in Figure . Thirty two channels of preconditioned neural signals, which are already time-division multiplexed on four lines in analog domain by a recording frontend (not shown), are delivered to the spike detector ASIC. The four multiplexed inputs each carrying 8 channels of neural signals are first converted to digital by four A/D converters simultaneously. The *Sample Distributor*, which is synchronized with the time-division multiplexer on the recording front-end, demultiplexes the amplitude samples into 32 digital neural channels. Then, the digital spike detector computes the averages and standard deviations of the 32 channels separately and accordingly calculates their threshold values. After the *Threshold Calculation* program is executed, the *Spike Detection* program is run. The amplitude sample of each channel is compared to the associated threshold, and if it is beyond the threshold level, it is considered as a detected spike. As long as a channel is active, its amplitude samples are tagged with the associated channel address, and put in a buffer to be sent to a

Figure 7. Functional block diagram of the 32-channel digital spike detector ASIC reported in [7] **Figure 7.** Functional block diagram of the 32-channel digital spike detector ASIC reported in [7]

In [15], a spike detector circuit is reported that computes the detection threshold in analog domain. Functional diagram of this circuit is shown in Figure 8. One of the advantages of this circuit is that unlike the spike detector in [7], the threshold is computed in real time. The circuit assumes that the input signal has already been amplified and band-pass filtered, and the background noise has a Gaussian distribution. Since the input signal is assumed to have no DC component, the noise can be described by its RMS value, *V1<sup>σ</sup>* , which is equivalent to its standard deviation, *σ*. In order to be well above the noise level, the threshold voltage is set to *VK<sup>σ</sup>* =*K.V1<sup>σ</sup>* , with K set to 5 in [15]. Although it is assumed that the low-frequency baseline variations of the input signal have been already filtered out, further analysis of this method shows that the detection threshold can adaptively follow the baseline variations. There is, however, an upper bound on the frequency-amplitude product of the baseline variations that the adaptive threshold is capable of following [16]. Power dissipation of the implementation of this approach is very low, in the range of microwatt and occupies very small silicon area. The drawbacks of this method include the circuit's sensitivity to the absolute value of some of the circuit elements, which are usually subject to relatively large fabrication tolerances, and the difficulty in implementing the lowfrequency low-pass filter required in the RMS block. *K V1 VK Vin Vout* RMS + \_ In [15], a spike detector circuit is reported that computes the detection threshold in analog domain. Functional diagram of this circuit is shown in Figure 8. One of the advantages of this circuit is that unlike the spike detector in [7], the threshold is computed in real time. The circuit assumes that the input signal has already been amplified and band-pass filtered, and the background noise has a Gaussian distribution. Since the input signal is assumed to have no DC component, the noise can be described by its RMS value, *V1σ,* which is equivalent to its standard deviation, *σ*. In order to be well above the noise level, the threshold voltage is set to *VKσ* =*K.V1σ,* with K set to 5 in [15]. Although it is assumed that the low-frequency baseline variations of the input signal have been already filtered out, further analysis of this method shows that the detection threshold can adaptively follow the baseline variations. There is, however, an upper bound on the frequency-amplitude product of the baseline variations that the adaptive threshold is capable of following [16]. Power dissipation of the implementation of this approach is very low, in the range of microwatt and occupies very small silicon area. The drawbacks of this method include the circuit's sensitivity to the absolute value of some of the circuit elements, which are usually subject to relatively large fabrication tolerances, and the difficulty in implementing the low-frequency low-pass filter required in the RMS block.

tion threshold level is set by Vbias, which along with the other bias and reference voltages should be properly set, and probably fine-tuned for long-term recordings. **Figure 8.** Functional diagram of the analog spike detector of [15]

Figure 9. shows another idea in analog spike detection, in which two OTA-based low-pass filters with different cut-off frequencies play the key role [17]. One filter has a higher cut-off frequency to remove high frequency noise, and the other has a lower cut-off frequency to make a local average. The difference between the high-pass filtered signal and its local average is provided by an OTA, and is recognized by another OTA as a detected spike when exceeds a certain reference value (Vref). This method is robust against changes in both noise level and the input signal's DC offsets, both of which are likely to happen in long-term neural recording. The OTAs operate in subthreshold region to reduce power. The τ bias voltages are set off chip to enable adjustment of the cut-off frequencies after fabrication. In this circuit, the spike detection threshold level is set by Vbias, which along with the other bias and reference voltages should be properly set, and probably fine-tuned for long-term recordings.

**Figure 9.** Schematic diagram of the analog spike detector of [16]

In both of the above analog approaches, there are device and circuit parameters that should be set by the user for proper operation, which make these circuits inappropriate for implantable applications.
