**3. Mathematical approaches**

Figure 7. Functional block diagram of the 32-channel digital spike detector ASIC reported in [7]

*Vout*

 *VK*s

Digital Spike Processor

frequency low-pass filter required in the RMS block.

*K V1 VK*

*Adaptive Threshold Generator* 

> RMS + \_

RMS + \_

ADC

ADC

ADC

**Multiplexed Analog Inputs** 

298 Advances in Bioengineering

*Vin*

*Vin*

**Figure 8.** Functional diagram of the analog spike detector of [15]

ADC

**Figure 7.** Functional block diagram of the 32-channel digital spike detector ASIC reported in [7]

Sample Distributor

32

Digital

Channels

In [15], a spike detector circuit is reported that computes the detection threshold in analog domain. Functional diagram of this circuit is shown in Figure 8. One of the advantages of this circuit is that unlike the spike detector in [7], the threshold is computed in real time. The circuit assumes that the input signal has already been amplified and band-pass filtered, and the background noise has a Gaussian distribution. Since the input signal is assumed to have no DC component, the noise can be described by its RMS value, *V1σ,* which is equivalent to its standard deviation, *σ*. In order to be well above the noise level, the threshold voltage is set to *VKσ* =*K.V1σ,* with K set to 5 in [15]. Although it is assumed that the low-frequency baseline variations of the input signal have been already filtered out, further analysis of this method shows that the detection threshold can adaptively follow the baseline variations. There is, however, an upper bound on the frequency-amplitude product of the baseline variations that the adaptive threshold is capable of following [16]. Power dissipation of the implementation of this approach is very low, in the range of microwatt and occupies very small silicon area. The drawbacks of this method include the circuit's sensitivity to the absolute value of some of the circuit elements, which are usually subject to relatively large fabrication tolerances, and the difficulty in implementing the low-frequency low-pass filter required in the RMS block.

Figure 8. Functional diagram of the analog spike detector of [15]

 *V1*s

 *K*

probably fine-tuned for long-term recordings.

Figure 9. shows another idea in analog spike detection, in which two OTA-based low-pass filters with different cut-off frequencies play the key role [17]. One filter has a higher cut-off

*Adaptive Threshold Generator* 

In [15], a spike detector circuit is reported that computes the detection threshold in analog domain. Functional diagram of this circuit is shown in Figure 8. One of the advantages of this circuit is that unlike the spike detector in [7], the threshold is computed in real time. The circuit assumes that the input signal has already been amplified and band-pass filtered, and the background noise has a Gaussian distribution. Since the input signal is assumed to have no DC component, the noise can be described by its RMS value, *V1<sup>σ</sup>* , which is equivalent to its standard deviation, *σ*. In order to be well above the noise level, the threshold voltage is set to *VK<sup>σ</sup>* =*K.V1<sup>σ</sup>* , with K set to 5 in [15]. Although it is assumed that the low-frequency baseline variations of the input signal have been already filtered out, further analysis of this method shows that the detection threshold can adaptively follow the baseline variations. There is, however, an upper bound on the frequency-amplitude product of the baseline variations that the adaptive threshold is capable of following [16]. Power dissipation of the implementation of this approach is very low, in the range of microwatt and occupies very small silicon area. The drawbacks of this method include the circuit's sensitivity to the absolute value of some of the circuit elements, which are usually subject to relatively large fabrication tolerances, and the difficulty in implementing the low-

**Serial Bit Stream** 

Figure shows another idea in analog spike detection, in which two OTA-based low-pass filters with different cut-off fre-

*Vout*

quencies play the key role [17]. One filter has a higher cut-off frequency to remove high frequency noise, and the other has a lower cut-off frequency to make a local average. The difference between the high-pass filtered signal and its local average is provided by an OTA, and is recognized by another OTA as a detected spike when exceeds a certain reference value (Vref). This method is robust against changes in both noise level and the input signal's DC offsets, both of which are likely to happen in long-term neural recording. The OTAs operate in subthreshold region to reduce power. The τ bias voltages are set off chip to enable adjustment of the cut-off frequencies after fabrication. In this circuit, the spike detection threshold level is set by Vbias, which along with the other bias and reference voltages should be properly set, and Mathematical transforms are among the most common methods of data compression. Recently, the Discrete Wavelet Transform (DWT) has been successfully employed in neural recording microsystems to compress the neural information, while preserving the wave shape of action potentials [18-26]. The DWT transforms discrete signals from the time domain into the time-frequency domain. One-level DWT for a given signal is achieved by convolving the signal samples through low-pass and high-pass decomposition filters [19,21]. The filtering is then followed by sub sampling to obtain the *approximation* and *detail* coefficients. For multilevel DWT, approximation coefficients should be fed to the same decomposition filters recursively [27]. Characteristics of the filters are determined by the wavelet basis. For neural signal compression, the optimal choice is a wavelet function that can approximate the action potentials waveform with minimum DWT coefficients and error. It has been shown that by proper selection of the wavelet basis, most of the spike energy is concentrated in a few large coefficients, while many small coefficients carry insignificant information and are mainly attributed to noise [19]. Therefore, in order to achieve higher data reduction rates, the DWT coefficients are passed through a thresholding stage. In this block, data coefficients smaller than desired certain threshold level are set to zero, while others are left unchanged. It is obvious that the threshold value plays an important role in the overall data compression rate, and also in the quality of the reconstructed signal. Hence, the threshold level should be set carefully based on the requirements of the target application.

Due to power and size constrains in biomedical implants, VLSI implementation of DWT is of great importance. In [20], it has been shown that from a signal compression standpoint, *symmlet4* wavelet basis is advantageous over other wavelet functions for neural recording applications. It is believed that this is mainly because of the similarity of this function to the general wave shape of action potentials. For hardware implementation of *symmlet4* function, lifting method is proposed in [21]. Furthermore, two different circuit designs, pipelined and sequential, are presented and compared for the lifting scheme. It is demonstrated that for single-level single-channel integer DWT, the pipelined approach consumes lower power, but occupies more silicon area compared with the sequential implementation. On the other hand, 4-level multi-channel implementation of the two designs indicates that the sequential ap‐ proach requires significantly smaller chip area, while the power consumption of both is almost the same. As a result, the sequential execution architecture is employed in [23] to design a complete 32-channel compression system based on the 4-level *symmlet4* DWT. The chip consumes 3 mW of power and occupies only 5.75 mm2 in a 0.5-μm CMOS technology. Also, with a sampling rate of 25 KSample/Sec per channel and 10-bits data samples, the system provides data compression of more than 20 times, resulting in a total output bit rate of less than 370 kbps.

In [26], a neural signal compression method based on the Discrete *Haar* Wavelet Transforms (DHWT) is proposed. From the standpoint of data compression, *Haar* basis function may not perform as efficient as complex functions such as high-order *Daubechies* and *symmlet*, but due to its simple hardware implementation, it can be easily used for large number of neural channels with less concern about power and area. As discussed in [26] for two-point DHWT, data coefficients can be calculated by only a buffer, an adder, and a subtractor. Moreover, in order to compare *Haar* and *symmlet4* basis functions, they have been both designed for processing a single channel with 8-bits data samples. Results indicate that before the thresh‐ olding stage, relative error (between the original signal and the corresponding reconstructed signal) for the DHWT is only 0.01% larger than the *symmlet4* case, which is obviously negligible. On the other hand, hardware implementation of the DHWT shows around 83% saving in number of transistors, and more than 90% in the occupied silicon area, when physically laid out in a 0.13-μm CMOS technology. The complete 64-channel DHWT-based neural compressor achieves a compression rate of 112 with an error of 2.22%. Additionally, the compressor circuit consumes as low as 0.12 mW @1.2 V supply voltage, and occupies less than 0.1 mm2 in a 0.13μm CMOS technology. Therefore, it can be said that with this architecture, the gain in circuit simplicity and the bit-rate improvement are much more significant than the penalty paid by the noise added to the signal. However, it is worth mentioning that, in general, the appropriate architecture should be selected based on the application.
