**5. Conclusion**

the OC phase, an ordinary offset cancellation technique is applied on the comparator and buffers. In the conversion phase, successive approximation algorithm first finds the segment of interest, encoded by b6b5b4, in 3 clock cycles. These 3 bits are converted to a 7-bit thermometer code, T7~T1, which will be used in the *Segment Selection* block to generate two analog voltages associated with the endpoints of the segment of interest. An in-segment linear A/D conversion process is then performed to determine the remained 4 LSBs, b3b2b1b0, in 4 clock cycles. Finally, an end of conversion signal is generated to reset the ADC and prepare for the next conversion cycle. A low-voltage band-gap reference (BGR) was designed to generate the required baseline,

> Nonlinear Cap. Arrays

220 µm

SAR & Switch Control Logic

**Experimental Results.** The presented exp-ADC was fabricated in a standard 0.18-μm CMOS process. A chip photograph is shown in Figure 18, in which the chip occupies a total size of

linearity (INL) are +0.8/-0.9 LSB and +4.3/-2.1 LSB, respectively. Table 1 summarizes the specifications of the NLADC and compares it with some of the nonlinear and linear ADCs

A proof-of-concept prototype of a 4-channel neural recording system based on anti-logarithmic quantization was reported in [6]. As shown in the block diagram of Figure 19, a time-domain multiplexer (TDM) shares an anti-logarithmic ADC (AL-ADC) between 4 channels (each sampled at 20kSps). The output digital codes are then packed by the data packaging block to be transmitted to the outside world via a wireless link. At the external host, received signal is first recovered and then converted back to analog via a PC software. This inverse conversion is performed using a logarithmic DAC. Quantization characteristic function for the DAC is an exact inverse for that of the NLADC used in the recording system. To evaluate the operation of the system, neural signals recorded from the auditory cortex of a Guinea pig are used for in-vitro tests. Figure 20 shows the input signal to one of the neural channels before entering the nonlinear quantization process on the implant side along with the associated signal on the external setup after reconstruction. To verify the concept of the noise reduction caused by

Linear Cap. Array

. The measured worst-case differential non-linearity (DNL) and integral non-

Comp, UGBs

T1 T2 T3 T4 T5 T6

2.15Cu

2.15Cu

3.02Cu

3.02Cu

**Segment Selection** 

1.67Cu

1.15Cu

T7

1.15Cu

Cu

Cu

1.36Cu

1.36Cu

**VREF VBL**

T1 T2 T3 T4 T5 T6 T7

1.67Cu

for the exp-ADC.

BGR

220 µm

Figure 16. The process of B-Noise reduction as the signal passes through the NLADC, formulated by eqs. (14)-(16)

**In-Segment Digitization** 

8Cb 2Cb Cb Cb 4Cb

b3 b1 b0 b2

SD Phase OC Phase

**V** PH1 **in** 

ADC Characteristic curve

Background

Input average

noise PDF Pni(ni

noise power ni

Output average no noise power 2 (t) Pni(ni

VLSB,max

Analog Input (ni

Baseline

)

PH1

 **Vin** PH2

> **PH0 PH1 PH2**

**CLK** 

PH0

PH1

**VBL**

PH1

UGB

UGB

)

<sup>2</sup> (t) Pni(ni )

PH1

19.11Cu

5.14Cu

5.14Cu

PH2

19.11Cu

**VREF** 

**VBL**

Digital Output (no)

)

Figure 17. Circuit schematic for the two-step SAR ADC designed to implement exp-ADC and its simplified timing diagram

Dummy Text **Circuit Design.** To realize the proposed exp-ADC with reasonable power and silicon area, successiveapproximation register (SAR) architecture was chosen [31]. In order to facilitate the realization of the exponential quantization function needed for the ADC, a piecewise-linear (PWL) approximation of the required function was implemented.

Segment Selection b6 b5 b4 b7

**VTH** 

T7-T1

In-Segment Digitization b3 b2 b1 b0

Conversion Phase

**SAR & Switch Control Logic** 

b3-b0 b7-b0

SAR b7- b0

Binary to Thermometer Converter

> End of Conversion

Digital Output

b6 - b4

range in which the input voltage is located. In the OC phase, an ordinary offset cancellation technique is applied on the

reference and threshold voltages for the exp-ADC.

**Figure 18.** Chip photograph of the proposed NLADC

220 ×230 μm2

310 Advances in Bioengineering

reported in the literature.

To overcome bandwidth limitation in the wireless telemetry of recorded neural data, a wide variety of data reduction techniques has been reported. These techniques range from spike reporting approaches such as spike detection and spike sorting techniques to mathematical approaches such as the discrete wavelet transform. Although it is proven that spike reporting approaches contain enough information to actuate prosthetic devices [33], in some other applications, such as neuroscientific studies, they are not satisfactory due to considerable loss of important information, e.g., spike wave shapes. Mathematical approaches, on the other hand, have been successful from the standpoint of data compression, while preserving wave shape of the spikes. Nonetheless, increasing the number of recording channels can result in the potential problems of these approaches: large silicon area and high power consumption. In contrast with all of the mentioned techniques, hardware approaches are capable of data reduction without adding any extra block to the microsystem. This is achieved by modifying the present hardware of the implant. An implementation of one of these approaches focusing on the ADC circuit of the system was presented and discussed in detail. The proposed method results in considerable reduction of bit-rate in multi-channel neural recording microsystems. Thus, efficient design of application-specific circuits for building blocks of neural implants should be taken into account as an appropriate method of data reduction.

**Figure 20.** Recorded neural signal and reconstructed neural signal

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[2] Harrison, R., Watkins, P., Kier, R., R. Lovejoy, Black, D., Normann, D. and Solzbacher, F. A Low-Power Integrated Circuit for a Wireless 100-Electrode Neural Recording System. IEEE Interna-

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[4] Wise, K.D., Angell, J. B. and Starr, A. An Integrated Circuit Approach to Extracellular Microelec-

[5] Sodagar, A.M. Integrated Circuit and System (ICAS) Lab Internal Report. K. N. Toosi University

[6] Akhavian, A., Judy, M. and Sodagar, A.M. Anti-Logarithmic Quantization for Data Reduction in Multi-Channel Intra-Cortical Neural Recording Implants. IEEE-EMBS International Conference on

[8] Eberhart, R.C, Dobbins, R.W. and Webber, W.R.S. EEG Waveform Analysis Using CaseNet. Proceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biolo-

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Systems and Rehabilitation Engineering 2009, 17, 312-21.

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Figure 21. (a) Measured quantization error in the time domain (b) Distributions of the measured **Figure 21.** quantization error and the measured B-Noise (a) Measured quantization error in the time domain (b) Distributions of the measured quantization error and the measured B-Noise
