**Modelling and Implementation of a Series DC Motor Drive System**

Angelo José Junqueira Rezek, Carlos Alberto Murari Pinheiro, Tony Youssif Teixeira Darido, Valberto Ferreira da Silva, Otávio Henrique Salvi Vicentini, Wanderson de Oliveira Assis and Rafael Di Lorenzo Corrêa

Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/59814

**1. Introduction**

For the purpose, of controlling a DC motor in a mono quadrant, a totally controlled Graetz converter bridge (a static converter) was used. For the implemented system, a microcomputer, a data acquisition board, an electronic firing circuit, as well as a current and speed sensors were used.

In this computer study, C++ language was used for the implementation of a controlled DC drive using a DC series motor.

Through the computer, the system control was performed directly via software and a data acquisition board containing A/D and D/A converters.

The board used was a PCL-711B PC-Multilab card from Advantech Co. (www.advan‐ tech.com), with A/D and D/A conversion, as well as digital inputs and outputs. The A/D conversion had 12 bits resolution, with eight input channels programmable for input ranges of ±5 [V] and a conversion time of 25 [µs]. The D/A conversion had the same resolution (12 bits) but with a single output channel that had an accommodation time of 30 [µs] and output ranges from 0 to +5 [V].

Two input channels were used for A/D conversion, corresponding to the speed and current feedback signals; one output channel D/A was used for the control signal (VCC).

The control software was responsible for the acquisition of input data, for the A/D and D/A conversions, implementation of the control algorithm for the speed and current grids, and for

generation of the control signal for the firing circuit. The program also included an on-line parameters setting. An output DC signal of the card (0-10 [V]) was used as the input of the firing circuit in order to control the series DC motor and for this purpose, two regulators, connected in a cascading fashion in terms of speed and current loops, was projected. The load torque was imposed using a three phase synchronous generator, connected to the same shaft of the series DC motor and supplying a three-phase resistor bank. generation of the control signal for the firing circuit. The program include also, on-line parameters setting. An output DC signal of the card (0-10 [V]) has been used to the input of the firing circuit, in order to control the series DC motor and for this purpose, two regulators, connected in cascade, in the speed and current loops, will be

projected. The load torque was imposed by using a three phase synchronous generator, connected to the same shaft of the series DC motor , supplying a three phase resistor bank.

### **2. Motor block diagram** 2. Motor block diagram

### **2.1. Mechanical part equating**

mechanical part is also presented.

Figure 1 shows the series DC motor armature circuit. The diagram of the drive system's mechanical part is also presented. 2.1 Mechanical part equating Figure 1 shows the series DC motor armature circuit. The diagram of the drive system

Figure 1. Motor armature circuit and diagram of the drive system mechanical part Being: U: Counter electromotive force [V] E: Applied voltage [V] Ra, La: Total resistance and inductance of the armature circuit Ф: Motor flux Ia: Armature current U: Counter electromotive force [V] E: Applied voltage [V] Ra, La: Total resistance and inductance of the armature circuit Ф: Motor flux Ia: Armature current M: Motor torque Tc: Load torque J: Moment of inertia (motor + load) n: Speed [rpm] ω: Rotation [rad / s]

M: Motor torque **Figure 1.** Motor armature circuit and diagram for the drive system mechanical part, being:

Tc: Load torque J: Moment of inertia (motor + load) n: Speed [rpm] Also:

ω: Rotation [rad / s]

For the accelerating torque:

$$M = K\_1 \Phi I\_{\underline{\ast}}$$

� = ��

 � = �

 � − � = � (2)

�1�

�� �� �3�

 Also: M KI = Φ<sup>1</sup> <sup>a</sup> Being *Ia* the armature current average value and also, K1Φ = KIa, therefore:

Being <sup>a</sup> I the armature current average value and also, K1Φ=KIa therefore:

Modelling and Implementation of a Series DC Motor Drive System http://dx.doi.org/10.5772/59814 103

$$M = K I\_{\mu}^2 \tag{1}$$

For the accelerating torque:

$$\mathbf{M} - \mathbf{T}\_c = \mathbf{B} \tag{2}$$

$$B = J \frac{d\mathbf{w}}{dt} \tag{3}$$

$$
\rho \alpha = \frac{2\pi}{60} n\_0 \frac{n}{n\_0} \tag{4}
$$

Being:

generation of the control signal for the firing circuit. The program also included an on-line parameters setting. An output DC signal of the card (0-10 [V]) was used as the input of the firing circuit in order to control the series DC motor and for this purpose, two regulators, connected in a cascading fashion in terms of speed and current loops, was projected. The load torque was imposed using a three phase synchronous generator, connected to the same shaft

generation of the control signal for the firing circuit. The program include also, on-line

 been used to the input of the firing circuit, in order to control the series DC motor and for this purpose, two regulators, connected in cascade, in the speed and current loops, will be projected. The load torque was imposed by using a three phase synchronous generator, connected to the same shaft of the series DC motor , supplying a three phase resistor bank.

Figure 1 shows the series DC motor armature circuit. The diagram of the drive system's

Figure 1. Motor armature circuit and diagram of the drive system mechanical part

M KI = Φ<sup>1</sup> <sup>a</sup>

*MKI* <sup>1</sup> *<sup>a</sup>* = F

 � − � = � (2)

�1�

�� �� �3�

� = ��

 � = �

Being <sup>a</sup> I the armature current average value and also, K1Φ=KIa therefore:

Being *Ia* the armature current average value and also, K1Φ = KIa, therefore:

Ra, La: Total resistance and inductance of the armature circuit

**Figure 1.** Motor armature circuit and diagram for the drive system mechanical part, being:

Ra, La: Total resistance and inductance of the armature circuit

Figure 1 shows the series DC motor armature circuit. The diagram of the drive system

of the series DC motor and supplying a three-phase resistor bank.

parameters setting. An output DC signal of the card (0-10 [V]) has

**2. Motor block diagram**

102 Fuzzy Logic - Tool for Getting Accurate Solutions

2. Motor block diagram

Being:

Ф: Motor flux

n: Speed [rpm] ω: Rotation [rad / s]

Also:

Also:

**2.1. Mechanical part equating**

2.1 Mechanical part equating

mechanical part is also presented.

U: Counter electromotive force [V]

J: Moment of inertia (motor + load)

U: Counter electromotive force [V]

J: Moment of inertia (motor + load)

For the accelerating torque:

E: Applied voltage [V]

Ф: Motor flux Ia: Armature current M: Motor torque Tc: Load torque

E: Applied voltage [V]

Ia: Armature current M: Motor torque Tc: Load torque

n: Speed [rpm] ω: Rotation [rad / s]

mechanical part is also presented.

### n0: No load speed [rpm]

Mn : Rated torque.

$$B = M\_n \frac{B}{M\_n} \tag{5}$$

(4) e (5) into (3) results:

$$\begin{aligned} \mathcal{M}\_n \frac{\mathcal{B}}{\mathcal{M}\_n} &= \mathsf{J} \, \mathrm{d} \, \frac{2\pi}{dt} n \frac{n}{dt} \\ \mathcal{M}\_n \frac{\mathcal{B}}{\mathcal{M}\_n} &= \mathsf{J} \, \frac{2\pi}{60} \frac{n\_o}{n\_o} \frac{dn}{dt} \\ n &= \frac{n\_0}{\mathcal{M}\_n} \frac{1}{\frac{2\pi}{60} \int \frac{n\_0}{\mathcal{M}\_n}} \Big[ \mathcal{B}.dt \end{aligned} \tag{6}$$

By defining the acceleration time constant TH, as:

$$T\_H = \frac{2\pi}{60} \frac{J\nu\_0}{M\_\pi} \tag{7}$$

 � <sup>=</sup> �

� <sup>=</sup> <sup>2</sup>� <sup>60</sup> �

 � = �

Being:

torque.

n0: No load speed [rpm] Mn : Rated torque.

(4) e (5) into (3) results:

� �

 (4)

 (5)

� �. �� �6�

� �

2

π

o o

n n

<sup>60</sup> =J d

n o B dn <sup>n</sup> <sup>M</sup> M n dt π

> 1 �

<sup>B</sup> <sup>n</sup> <sup>M</sup> M dt

> <sup>2</sup> =J 60 o

n n

n

�

This time constant may be interpreted as the time required for the motor to reach no load speed from a resting state, when it is accelerated by a resultant torque equal to the rated motor torque. � == <sup>2</sup>� 60 � (7) This time constant may be interpreted as the time required for the motor to reach no load

��

$$m = \frac{m\_0}{\mathcal{M}\_n} \frac{1}{T\_H} \int B \, dt \tag{8}$$

Figure 2 illustrates the block diagram related to the mechanical motor part. Figure 2 illustrates the block diagram related to the motor mechanical part.

�

�

**Figure 2.** Block diagram of the drive mechanical part.

Figure 2. Block diagram of the drive mechanical part

Setting the magnitude values in pu, current, load torque, accelerating torque, speed and motor torque results in:

$$\frac{I\_s}{I\_N} = \dot{\mathbf{r}}\_s \text{ (pu)}$$

$$\frac{T\_c}{M\_n} = \mathbf{f}\_c \text{ (pu)}$$

$$\frac{B}{M\_n} = b \text{ (pu)}$$

$$\frac{n}{n\_o} = n\_u \text{ (pu)}$$

$$\frac{M}{M\_n} = m \text{ (pu)}$$

The block diagram in Figure 2 can be represented in pu as shown in Figure 3.

#### **2.2. Armature circuit equating**

$$E = R\_a I\_a + L\_a \frac{dI\_a}{dt} + U$$

Setting the magnitude values in pu, current, load torque, accelerating torque, speed and

 (pu) <sup>a</sup> a

 (pu) <sup>c</sup> c

(pu)

(pu) <sup>u</sup>

t <sup>M</sup> <sup>=</sup>

n n =

i <sup>I</sup> <sup>=</sup>

N

T

n

n <sup>B</sup> <sup>b</sup> <sup>M</sup> <sup>=</sup>

o

M

The block diagram of Figure 2, can be represented in pu as shown in Figure 3.

n

I

Figure 3. Representation of the motor mechanical part in pu. **Figure 3.** Representation of the motor mechanical part in pu.

> � <sup>=</sup> � �

Applying the Laplace transform results in: 2.2 Armature circuit equating

motor torque, results in:

$$\begin{aligned} E(S) &= R\_{\underline{a}} I\_{\underline{a}}(S) + SL\_{\underline{a}} I\_{\underline{a}}(S) + LI(S), \\ E(S) - LI(S) &= I\_{\underline{a}}(S) \Big[ R\_{\underline{a}} + SL\_{\underline{a}} \Big] \end{aligned}$$

() () () () E S R I S SL I S U S =+ + aa aa

� + ��

a

$$I\_{a(S)} = \frac{E\{S\} - U\{S\}}{R\_a + SL\_a} \tag{9}$$

Defining: �() <sup>=</sup> ���� <sup>−</sup> �(�) Defining:

This time constant may be interpreted as the time required for the motor to reach no load speed from a resting state, when it is accelerated by a resultant torque equal to the rated motor torque.

�� �

60

 This time constant may be interpreted as the time required for the motor to reach no load speed from rest, when it is accelerated by a resultant torque equal to the rated motor

<sup>0</sup> <sup>1</sup> . *n H <sup>n</sup> n B dt*

1 �

Setting the magnitude values in pu, current, load torque, accelerating torque, speed and motor

*a a N c*

*M*

*<sup>I</sup> <sup>i</sup> I T*

=

*n*

=

*<sup>B</sup> <sup>b</sup> M n n*

=

*o*

*M*

The block diagram in Figure 2 can be represented in pu as shown in Figure 3.

*n M*

*n*

(pu)

(pu)

*c n*

*t*

=

(pu)

(pu)

*u*

*m*

=

*aa a dI E RI L U*

(pu)

*a*

*dt* =+ +

�

Figure 2 illustrates the block diagram related to the mechanical motor part.

Figure 2 illustrates the block diagram related to the motor mechanical part.

� <sup>=</sup> <sup>2</sup>� <sup>60</sup> �

 � = �

 � <sup>=</sup> �

104 Fuzzy Logic - Tool for Getting Accurate Solutions

By defining the acceleration time constant TH, as:

 � == <sup>2</sup>�

 � <sup>=</sup> �

Figure 2. Block diagram of the drive mechanical part

**Figure 2.** Block diagram of the drive mechanical part.

torque results in:

**2.2. Armature circuit equating**

Being:

torque.

n0: No load speed [rpm] Mn : Rated torque.

(4) e (5) into (3) results:

� �

 (4)

� �

2

π

o o

n n

<sup>60</sup> =J d

n o B dn <sup>n</sup> <sup>M</sup> M n dt π

> 1 �

<sup>B</sup> <sup>n</sup> <sup>M</sup> M dt

> <sup>2</sup> =J 60 o

n n

n

�

*M T* <sup>=</sup> ò (8)

 (5)

� �. �� �6�

 (7)

� �. �� (8)

$$T\_a = \frac{L\_a}{R\_a} \tag{10}$$

 (9)

$$I\_s(S) = \frac{E(S) - \mathcal{U}(S)}{1 + ST\_s} \times \frac{1}{R\_s} \tag{11}$$

1

Regrouping:

$$\begin{aligned} \frac{I\_a}{I\_N} \times I\_N &= \frac{\mathbf{E} \cdot \mathbf{U}}{R\_a} \frac{E\_N}{E\_N} \times \frac{1}{1 + S T\_a} \\\frac{I\_a}{I\_N} &= \frac{\mathbf{E} \cdot \mathbf{U}}{E\_N R\_a} \frac{E\_N}{I\_N} \times \frac{1}{1 + S T\_a} \\\frac{I\_a}{I\_N} &= \frac{\mathbf{E} \cdot \mathbf{U}}{E\_N} \frac{E\_N}{R\_a I\_N} \times \frac{1}{1 + S T\_a} \end{aligned}$$

The armature current Ia appears to be normalized by the nominal current IN. Voltages E and U are also normalized by the nominal voltage EN, setting the normalized values as:

Setting the normalized values as:

Regrouping:

$$i\_a = \frac{I\_a}{I\_N} \tag{12}$$

E-U 1

N aN a

N N aN a

I E R I ST

E-U 1

I R E ST ×= ×

a N N

a N

I E

1

1

+

+

$$e = \frac{E}{E\_N} \tag{13}$$

$$
\mu = \frac{\mathcal{U}}{E\_N} \tag{14}
$$

$$V\_i = \frac{E\_N}{R\_a I\_N} \tag{15}$$

The block diagram of the armature circuit l is shown in Figure 4. � <sup>=</sup> � �� (15)

The block diagram of the armature circuitl is shown in Figure 4.

Figure 4. Block diagram of the DC motor armature circuit.

 The factor 1 i a <sup>+</sup> ST can be considered a delay element of 1 ª order. The determination of the **Figure 4.** Block diagram of the DC motor armature circuit.

V

time constant Ta can be done in two ways: a) Measuring La and Ra; The factor *Vi* 1 + *STa* can be considered a delay element of 1 ª order. Time constant Ta can be determined in two ways:

**a.** Measuring La and Ra;

**b.** Applying a reduced voltage step in the armature circuit when the rotor of the motor is blocked.

Figure 5 shows the armature circuit.

Figure 5. Reduced voltage step applied to the armature circuit. **Figure 5.** Reduced voltage step applied to the armature circuit.

blocked. Figure 5 shows.

*a*

a N N

a N

I E

I E <sup>I</sup>

E-U 1

N aN a

N Na N a

N N aN a

The armature current Ia seems normalized by the nominal current IN .Voltages E and U are

�

�

�

��

<sup>+</sup> ST can be considered a delay element of 1 ª order. The determination of the

can be considered a delay element of 1 ª order. Time constant Ta can be

**b.** Applying a reduced voltage step in the armature circuit when the rotor of the motor is

I E R I ST = ×

E-U 1

I E R I ST = ×

E-U 1

I R E ST ×= ×

1

1

1

+

+

+

*<sup>I</sup>* <sup>=</sup> (12)

*<sup>E</sup>* <sup>=</sup> (13)

*<sup>E</sup>* <sup>=</sup> (14)

 (12)

 (13)

 (14)

 (15)

*R I* <sup>=</sup> (15)

*N <sup>I</sup> <sup>i</sup>*

I E

a N

*N E e*

*N U u*

*N*

*a N*

*i*

The block diagram of the armature circuitl is shown in Figure 4.

Figure 4. Block diagram of the DC motor armature circuit.

The block diagram of the armature circuit l is shown in Figure 4.

also normalized by the nominal voltage EN.

 � <sup>=</sup> �

 � <sup>=</sup> �

 � <sup>=</sup> �

 � <sup>=</sup> �

Setting the normalized values as:

*<sup>E</sup> <sup>V</sup>*

*a*

Regrouping:

106 Fuzzy Logic - Tool for Getting Accurate Solutions

The factor

The factor

1 i a

a) Measuring La and Ra;

Figure 5 shows the armature circuit.

*Vi* 1 + *STa*

determined in two ways:

**a.** Measuring La and Ra;

blocked.

V

**Figure 4.** Block diagram of the DC motor armature circuit.

time constant Ta can be done in two ways:

 The current Ia is captured through an oscillograph or storage oscilloscope(voltage drop in the shunt resistor RSH). Figure 6 illustrates the expected time transient response. The current Ia is captured through an oscillograph or storage oscilloscope (voltage drop in the shunt resistor RSH). Figure 6 illustrates the expected time transient response. A current clamp can also be used, instead of the resistor RSH. Figure 5. Reduced voltage step applied to the armature circuit. The current Ia is captured through an oscillograph or storage oscilloscope(voltage drop in the shunt resistor RSH). Figure 6 illustrates the expected time transient response.

 Marking up to 63% of the regime value and checking the corresponding time on the **Figure 6.** Current response for a voltage step applied to the armature circuit.

��

��

�

�

horizontal axis, one has a time constant τa. Results, from Figure 4.

Figure 6. Current response for a voltage step applied to the armature circuit.

 � <sup>=</sup> � <sup>−</sup> � 1++�� � (16) horizontal axis, one has a time constant τa. Results, from Figure 4. � <sup>=</sup> � <sup>−</sup> � � (16) Marking up to 63% of the regime value and checking the corresponding time on the horizontal axis, yields the time constant τa, as shown in Figure 4.

1++��

Marking up to 63% of the regime value and checking the corresponding time on the

$$\dot{\mathbf{u}}\_a = \frac{e - u}{1 + \dots + ST\_a} V\_i \tag{16}$$

 � <sup>=</sup> � � (17) � <sup>=</sup> � (18) � <sup>=</sup> � � (17) � <sup>=</sup> � (18) Considering an interpretation of the constant Vi (equation 15) results in a motor with the rotor locked and with a rated voltage applied to the armature.

$$I\_{AK} = \frac{E\_N}{R\_a} \tag{17}$$

$$\frac{I\_{AK}}{I\_N} = \frac{E\_N}{R\_a I\_N} \tag{18}$$

Comparing (18) e (15), results in :

Comparing (18) e (15), results:

$$I\_{AK} = V\_i I\_N \tag{19}$$

The Vi factor can be interpreted as the multiplying factor of the rated current for gaining a current with the rotor locked when nominal voltage is applied to the armature circuit (starting current in pu). � = �� (19) . Soon, the Vi factor can be interpreted as the multiplying factor of the rated current for getting a current with the rotor locked, when nominal voltage is applied to the armature Comparing (18) e (15), results:

Figure 7 shows a schematic diagram of the series DC motor with rated flow and considering the normalized magnitudes (pu). circuit (starting current in pu). Figure 7 shows the schematic diagram of the series DC motor with rated flow, and � = �� (19) . Soon, the Vi factor can be interpreted as the multiplying factor of the rated current for

getting a current with the rotor locked, when nominal voltage is applied to the armature

**Figure 7.** Schematic block diagram of the series DC motor.

considering the normalized magnitudes(pu).

#### Figure 8 shows the controlled drive complete block diagram. **3. Complete block diagram including regulators, filters and transducers** 3. Complete block diagram with inclusion of regulators filters and transducers

3. Complete block diagram with inclusion of regulators filters and transducers

Figure 8 shows the controlled drive complete block diagram. Figure 8 shows the controlled drive complete block diagram.

τgs1: Filter time constant of the reference channel of the speed loop; τgs2: Filter time constant of the reference channel of the current loop;

Figure 7. Schematic block diagram of the series DC motor.

Figure 7. Schematic block diagram of the series DC motor.

 Where: τgs1: Filter time constant of the reference channel of the speed loop; Figure 8. Controlled drive complete block diagram. **Figure 8.** Controlled drive complete block diagram.

VRi: Gain of the current regulator; τn: Time constant of the speed regulator; τi: Time constant of the current regulator; τgn: Filter time constant of the speed transducer;

VRN: Gain of the speed regulator; VRi: Gain of the current regulator; τn: Time constant of the speed regulator; τi: Time constant of the current regulator; τgn: Filter time constant of the speed transducer;

τgs2: Filter time constant of the reference channel of the current loop; VRN: Gain of the speed regulator; Where: Where:

τgs1: Filter time constant of the reference channel of the speed loop

τgs2: Filter time constant of the reference channel of the current loop

VRN: Gain of the speed regulator

Comparing (18) e (15), results in :

108 Fuzzy Logic - Tool for Getting Accurate Solutions

Comparing (18) e (15), results:

the normalized magnitudes (pu).

circuit (starting current in pu).

Comparing (18) e (15), results:

considering the normalized magnitudes(pu).

considering the normalized magnitudes(pu).

**Figure 7.** Schematic block diagram of the series DC motor.

Figure 7. Schematic block diagram of the series DC motor.

Figure 8 shows the controlled drive complete block diagram.

Figure 7. Schematic block diagram of the series DC motor.

Figure 8 shows the controlled drive complete block diagram.

Figure 8 shows the controlled drive complete block diagram.

Figure 8. Controlled drive complete block diagram.

Figure 8. Controlled drive complete block diagram.

VRN: Gain of the speed regulator; VRi: Gain of the current regulator; τn: Time constant of the speed regulator; τi: Time constant of the current regulator; τgn: Filter time constant of the speed transducer;

VRN: Gain of the speed regulator; VRi: Gain of the current regulator; τn: Time constant of the speed regulator; τi: Time constant of the current regulator; τgn: Filter time constant of the speed transducer;

**Figure 8.** Controlled drive complete block diagram.

τgs1: Filter time constant of the reference channel of the speed loop; τgs2: Filter time constant of the reference channel of the current loop;

τgs1: Filter time constant of the reference channel of the speed loop; τgs2: Filter time constant of the reference channel of the current loop;

circuit (starting current in pu).

The Vi

.

Where:

Where:

Where:

.

current in pu).

*AK i N I VI* = (19)

 factor can be interpreted as the multiplying factor of the rated current for gaining a current with the rotor locked when nominal voltage is applied to the armature circuit (starting

Figure 7 shows a schematic diagram of the series DC motor with rated flow and considering

 � = �� (19)

Figure 7 shows the schematic diagram of the series DC motor with rated flow, and

Figure 7 shows the schematic diagram of the series DC motor with rated flow, and

 Soon, the Vi factor can be interpreted as the multiplying factor of the rated current for getting a current with the rotor locked, when nominal voltage is applied to the armature

3. Complete block diagram with inclusion of regulators filters and transducers

3. Complete block diagram with inclusion of regulators filters and transducers

**3. Complete block diagram including regulators, filters and transducers**

 � = �� (19)

 Soon, the Vi factor can be interpreted as the multiplying factor of the rated current for getting a current with the rotor locked, when nominal voltage is applied to the armature VRi: Gain of the current regulator

τn: Time constant of the speed regulator

τi : Time constant of the current regulator

τgn: Filter time constant of the speed transducer

τgi: Filter time constant of the current transducer

τss: Time constant of the firing circuit

Vs: Gain of the static converter

The regulators in Figure 8 were considered as PI (proportional integral) type and its parameters will be determined by the design procedure.

### **4. Design of the current regulator and filters of the current control loop**

Figure 9 illustrates the current regulation loop.

Series DC motor data:


The current transducer is a diode bridge that supplies resistors connected to the AC (alternat‐ ing current) side and feeds through the secondary current transformers (CTs), 30/5 [A]. Figure 10 shows the current transducer.

A current hall sensor can also be used as current transducer in DC side.

Where: Ld: Smoothing reactor inductance


Series DC motor data: - Power: 1.7 [KW] - Current: 7.72 [A]


reactor)

τgi: Filter time constant of the current transducer;

Figure 9 illustrates the current regulation loop.


parameters will be determined by the design procedure.


τss: Time constant of the firing circuit; Vs: Gain of the static converter

The regulators of figure 8 were considered as PI (proportional integral) type , and its

4. Design of the current regulator and filters of the current contreol loop

Figure 9. Current regulation loop. **Figure 9.** Current regulation loop.

 Where: Ld : Smoothing reactor inductance. **Figure 10.** Current transducer.

Ls: Series field inductance Ls: Series field inductance

The Vi constant is equal:

The Vi signal (current transducer) has, as is known, a (1/6) cycle ripple wave. It should have: The Vi signal (current transducer), has, as know, a (1/6 ) of cycle ripple wave. It should have:

������

� ≤ 1

be used. The time constant τa, was obtained measuring La and Ra.

a

a L

 This constant has been calculated taking into account the total inductance La in series with the armature circuit, which corresponds to the inductances of machine (armature, inter poles and series field), added with the inductance of the external smoothing reactor .

R τ = =

$$
\pi\_{g^{\circ}} \le \frac{1}{2} \frac{Period}{N^{\circ} ofpulses}
$$

τgi = 1.5 [ms]

 The firing circuit cannot instantly respond to the change in the firing angle α. This time constant can vary by the range of zero to one sixth of a cycle. The value τss= 2,5 [ms], will

70 [ ] <sup>a</sup>

ms

For 60 [Hz], a period of 16.7 [ms] and six pulse bridges, the following is adopted:

$$
\tau\_{\oplus} = 1.5 \left[ \text{ms} \right]
$$

The firing circuit cannot instantly respond to the change in the firing angle α. This time constant can vary by a range of zero to one sixth of a cycle. The value τss = 2.5 [ms] will be used. The time constant τa was obtained measuring La and Ra.

$$
\pi\_a = \frac{L\_a}{R\_a} = \mathcal{T}0 \text{ [}m\text{s]}
$$

This constant has been calculated taking into account the total inductance La in the series with the armature circuit, which corresponds to the inductances of machine (armature, interpoles and series field) added to the inductance of the external smoothing reactor.

The Vi constant is equal to:

Ls: Series field inductance

**Figure 10.** Current transducer.

Figure 10. Current transducer

Ls: Series field inductance

The Vi constant is equal:

Where: Ld : Smoothing reactor inductance.

τgi: Filter time constant of the current transducer;

Figure 9 illustrates the current regulation loop.


Figure 9. Current regulation loop.

**Figure 9.** Current regulation loop.

(CTs), 30/5 [A]. Figure 10 shows.

parameters will be determined by the design procedure.


The regulators of figure 8 were considered as PI (proportional integral) type , and its


 The current transducer is a diode bridge, supplying resistors, connected to the AC(alternating current) side and feeding through the secondary of current transformers

4. Design of the current regulator and filters of the current contreol loop

τss: Time constant of the firing circuit; Vs: Gain of the static converter

Series DC motor data: - Power: 1.7 [KW] - Current: 7.72 [A]


reactor)


110 Fuzzy Logic - Tool for Getting Accurate Solutions

signal (current transducer) has, as is known, a (1/6) cycle ripple wave. It should have:

������ � �� ������

*Period N ofpulses*

τgi = 1.5 [ms]

 The firing circuit cannot instantly respond to the change in the firing angle α. This time constant can vary by the range of zero to one sixth of a cycle. The value τss= 2,5 [ms], will

70 [ ] <sup>a</sup>

ms

1 2 *gi <sup>o</sup>*

The Vi signal (current transducer), has, as know, a (1/6 ) of cycle ripple wave. It should

t£

For 60 [Hz], period of 16.7 [ms], and six pulse bridge, it is adopted:

be used. The time constant τa, was obtained measuring La and Ra.

a

a L

 This constant has been calculated taking into account the total inductance La in series with the armature circuit, which corresponds to the inductances of machine (armature, inter poles and series field), added with the inductance of the external smoothing reactor .

R τ = =

� ≤ 1 2

The Vi

have:

$$V\_i = \frac{E\_n}{R\_a I\_a} = 4.07$$

The Vs gain of the converter is obtained, as follows:

$$E = 1.35 
 \text{L}\_2 
 sin a$$

Being U2, the AC supply voltage of converter bridge is:

$$\frac{dE}{da} = -1.35 L\_z \sin a$$

Multiplying member by member by *<sup>π</sup> EN* , results:

$$\frac{d\left(\frac{E}{E\_N}\right)}{d\left(\alpha/\pi\right)} = -1.35 \frac{U\_2}{E\_N} \pi \sin \alpha$$

The value of U<sup>2</sup> is determined for the DC side-rated voltage as being equal to (220V), consid‐ ering the value of the firing angle at 30°. This procedure results in U2 = 188 [V].

Also:

$$\begin{aligned} \frac{de}{d\alpha\_2} &= -1.35 \times \frac{188}{220} \times \pi \sin \alpha \\\ \frac{de}{d\alpha\_\mu} &= -1.15 \pi \sin \alpha \end{aligned} \tag{20}$$

Being As the value in (pu) of the firing angle α, is equal to *α<sup>u</sup>* <sup>=</sup> *<sup>α</sup> π* Results:

$$Vs = \left| \frac{de}{da\_2} \right| = 1.15\pi sin\alpha$$

When α = 90 ° the maximum gain is:

$$p \mid\_{a = 90^{\circ}} = 1.15\pi$$

$$\text{Vs}\_{1} = \left| \frac{de}{da\_{2}} \right| $$

For α = 30°, gain is given by:

$$p \land\_{\alpha = 30^{\circ}} = 1.15 \times \pi \times 0.5$$

$$\text{Vs}\_2 = \left| \frac{de}{da\_2} \right| $$

The average gain, Vs, can be determined as:

$$\text{Vs} = \text{2.71} \tag{21}$$

The current regulation system gain is then obtained as:

$$\mathbf{V}\mathbf{s}\mathbf{i}\mathbf{a} = \mathbf{V}\mathbf{s} \times \mathbf{V}\mathbf{i} = \mathbf{2}.71 \times \mathbf{4}.07 = \mathbf{11}.03\tag{22}$$

The sum of the small time constants is:

$$
\sigma = \mathfrak{r}\_{ss} + \mathfrak{r}\_{\mathfrak{g}^i} = 4 \text{ [}ms\text{]}.
$$

The relationship *<sup>τ</sup><sup>a</sup>* <sup>4</sup>*<sup>σ</sup>* =4.37>1

Also:

Results:

When α = 90 ° the maximum gain is:

112 Fuzzy Logic - Tool for Getting Accurate Solutions

For α = 30°, gain is given by:

The average gain, Vs, can be determined as:

The sum of the small time constants is:

The current regulation system gain is then obtained as:

2

a

*d*

Being As the value in (pu) of the firing angle α, is equal to *α<sup>u</sup>* <sup>=</sup> *<sup>α</sup>*

*u*

a

*d*

<sup>188</sup> 1.35 220

p a

> p a

*π*

*Vs* = 2.71 (21)

*Vsia Vs Vi* =´= ´ = 2.71 4.07 11.03 (22)

4 [ ]

(20)

*de sin*

=- ´ ´

1.15

2 1.15 *de Vs sin <sup>d</sup>* = =

90

a

30

a

st

 t=+= *ss gi ms*

2

*p* / 1.15 0.5 *<sup>o</sup>*

<sup>=</sup> = ´´

*de Vs d*

=

*p* / 1.15 *<sup>o</sup>*

<sup>=</sup> =

*de Vs d*

=

1

2

2

a

p

a

p

a

p a

*de sin*

= -

According to Table 6.3 (pp 339) in *Introduction to Electronic Control* (Spanish) [4] by Friedrich Fröhr and Fritz Orttenburguer, the regulator type PI should be used (designed by type *cake recipe*).

According to Table 6.4 (pp 341) of the same text, the gain and the time constant of the regulator can be obtained thus:

$$V\_{Rj} = \frac{\tau\_s}{2V\_{s\text{ia}}\sigma} = 0.8 \tag{23}$$

$$
\pi\_i = 4\sigma \frac{\tau\_a}{\tau\_a + 3\sigma} = 13.66 \left[ ms \right] \tag{24}
$$

The time constant value of the reference channel filter in [ms] is:

$$\pi\_{g\approx 2} = 4\sigma \left( 1 - e^{-\left(\frac{r\_s}{4\sigma - 1}\right)} \right) = 15.84 \left[ ms \right] \tag{25}$$

Thus, in summary:

### CURRENT REGULATOR


### **5. Design of the regulator and filters of the speed control loop**

### **5.1. Design of the speed regulator**

The current loop will be replaced by a corresponding retarder block of the first order, whose time constant, according to [4] is obtained thus:

$$
\pi\_c = 2\sigma + \frac{1}{2}\tau\_{g\circ 2} = 15\left[ms\right] \tag{26}
$$

$$\sigma\_{\circ n} = 100 \text{ [}ms\text{]}$$

$$\begin{aligned} \tau\_H &= 1.2 \boxed{s} \\ \tau\_c &= 15 \boxed{ms} \\ \tau\_{\mathcal{S}^m} &= 100 \boxed{ms} \end{aligned} $$

$$
\sigma^\cdot = \mathfrak{r}\_e + \mathfrak{r}\_{en} = 115 \lceil ms \rceil
$$

$$V\_{RN} = \frac{\pi\_H}{2\sigma'} = 5.2\tag{27}$$

The speed regulator time constant, is:

This results in a block diagram for the speed control loop as shown in Figure 11.

1+ STn

nREF <sup>X</sup> m **b**

SPEED REGULATOR


1 1+ ST gS1

**Figure 11.** Speed loop regulation.

In the

The relationship, ��

time constant is:

The relationship, *<sup>τ</sup><sup>H</sup>*

���

The speed regulator time constant, is:

be used (designed by type *cake recipe*).

Figure 11. Speed loop regulation

FILTER

114 Fuzzy Logic - Tool for Getting Accurate Solutions

Thus, results the block diagram of the speed control loop, as shown in Figure 11.

STn VR <sup>N</sup> tC

1 1+ STe

CURRENT LOOP

FILTER

1 1+ STgn

100 [ ]

100 [ ]

*gn ms*

*gn* = *ms*

�� � ������ �� � ������ ��� � �������

The small time constants τe e τgn, will be grouped by an equivalent time constant σ'.

*H e gn*

t

t

t

1.2 15 100

= é ù ë û = é ù ë û = é ù ë û

*s ms ms*

 According to Table 6.4 [4] the gain and the time constant of the regulator are: ��� � ��

'

s

The small time constants τe e τgn, will be grouped by an equivalent time constant σ':

tt

 115 =+ = *e gn* é ù *ms* ë û

**5.2 Design of the speed refernce and transducer feedback channels filters**

According to Table 6.4 [4] the gain and the time constant of the regulator are:

�� � �� � ��� � �������

�� � ��� � ������� ����

 The speed transducer is a DC tachogenerator coupled to the shaft of the DC motor. It has been used a filter due to the ripple wave of the tachogenerator output voltage. The adopted

2 ' *<sup>H</sup> VRN* = = t

s

 ��� � ������� ����

5.2

� ���� � � and in accordance with Table 6.3 [4], a PI

� ��� ����

<sup>4</sup>*<sup>σ</sup>* ' =4.56>1 and in accordance with Table 6.3 [4], a PI type regulator should

���

A speed transducer filter will be needed, for which the time constant is adopted as:.

A speed transducer filter will be needed, for which the following time constant is adopted:

t

In the speed regulation loop, there are the time constants:

The speed regulation loop contains the following time constants:

type regulator should be used (designed by type *cake recipe*).

ia


> 1 STH

MOTOR MECHANICAL BLOCK

nu

(27)

$$
\sigma\_n = 4\sigma^\cdot = 460 \boxed{m} \text{s} \tag{28}
$$

### **5.2. Design of the speed reference and transducer feedback channels filters**

The speed transducer is a DC tachogenerator coupled to the shaft of the DC motor. A filter is used due to the ripple wave of the tachogenerator output voltage. The adopted time constant is:

$$
\left[\pi\_{\rm gu} = 100 \boxed{m}\right] \tag{29}
$$

The speed reference channel filter has the following time constant value [4]:

$$
\sigma\_{\llcorner 1} = 4\sigma^{\cdot} = 460 \boxed{ms}
$$

Thus, in summary, one has:

### SPEED REGULATOR


### **6. Ramp type firing circuit**

The firing system used is a ramp type, implemented with the TCA 780 integrated circuit and manufactured by Siemens, as shown in Figure 12.

The intersection of the DC level with a ramp, which is internally generated in the TCA 780 integrated circuit, produces the pulses. Voltage VCC is the output of the current regulator, as shown in Figure 8. Three TCA 780 integrated circuits were used to produce six firing pulses for the thyristorized GRAETZ converter bridge, which are P1 and P2 for thyristors 1 and 4, P3 and P6, for thyristors 3 and 6 and P5 and P2 for thyristors 5 and 2, respectively. This process explains the firing circuit pulse generation stage. The other pulses include: enlargement of pulses, galvanic isolation of pulses and pulse amplification, the circuit description and explanation for which were not the objective of this work.

Thus, in summary, one has:

 **6. Ramp type firing circuit** 

SPEED REGULATOR




The speed reference channel filter has a time constant value: [4].



߬௦ଵ ൌ Ͷߪ<sup>ᇱ</sup> ൌ ͶͲሾ݉ݏሿ

 Figure 12 : Ramp type firing circuit **Figure 12.** Ramp type firing circuit.

### **7. Control using fuzzy logic** The intersection of the DC level with a ramp, which is internally generated in the TCA 780

This procedure is based on research provided in [10]. integrated circuit, produce the pulses. Voltage VCC is the output of the current regulator, as

### **7.1. Fuzzy regulator** shown in Figure 8. Three TCA 780 integrated circuits should be used to produce six firing

With the objective of understanding how this type of regulator works, it is helpful to under‐ stand the basics of fuzzy logic. Based on the theory of the fuzzy sets proposed by ZADEH in 1965 [9], this type of logic has proven to be one of the most interesting technologies for application in sophisticated control systems, providing a simple approach to decreasing costs and increasing the efficiency of such systems. pulses, for the thyristorized GRAETZ converter bridge, which are P1 and P2, for the thyristors 1 and 4; P3 and P6, for the thyristors 3 and 6; and P5 and P2, for the thyristors 5 and 2, respectively. This is the explanation of the firing circuit pulse generation stage. The other ones are: enlargement of pulses, galvanic isolation of pulses and pulse amplification,

This chapter provides an introduction to this technology in the controlled drive of a DC machine with series excitation aimed at speed control and current limitation. According to [8], this type of system (a non-linear process) is better controlled with fuzzy controllers as opposed to conventional compensators. whose circuit description and explanation are not the objective of this work. **7. Control using fuzzy logic** 

### **7.2. Fuzzy control** This procedure is based according to reference [10].

The theory for control using fuzzy logic characterizes the variables of interest through linguistic expressions such as "very large", "large", "small", "hot", "cold", etc. These linguistic expressions are numerically represented by fuzzy sets, each set being characterized by a pertinence function varying from 0 to 1. The fuzzy control algorithm performs control actions written in terms of these imprecise ideas. The input variables of the fuzzy controller considered of interest (current regulator) are obtained by: **7.1 Fuzzy regulator**  With the objective to understand how this kind of regulator works, it is convenient to understand a little of the Fuzzy Logic. Based on the theory of the fuzzy sets proposed by

machine with series excitation aiming at the speed control and current limitation.

$$\operatorname{LE}\begin{pmatrix}k\end{pmatrix} = I\_{\text{out}}\begin{pmatrix}k\end{pmatrix} - I\_{\text{ref}}\begin{pmatrix}k\end{pmatrix} \tag{30}$$

$$PE\left(k\right) = GEE \times LE\left(k\right)\tag{31}$$

$$\text{IIIE}\left(k\right) = \text{IIE}\left(k-1\right) + \text{GVi} \times \text{IE} \times T \tag{32}$$

Where IE(k) = Error of current; IIE(k) = Current error integral

GEi = Proportional gain; GVi = Integral gain (inverse of the regulator time constant)

Ireal(k) = Feedback current

PE(k) = Proportional error

Iref(k) = Reference current

u(k) (see program listing) = Vcc = Output control;

 The intersection of the DC level with a ramp, which is internally generated in the TCA 780 k = Sampling interval

integrated circuit, produce the pulses. Voltage VCC is the output of the current regulator, as T = Sample time

**7. Control using fuzzy logic**

**Figure 12.** Ramp type firing circuit.

**7.1. Fuzzy regulator**

Figure 12 : Ramp type firing circuit

manufactured by Siemens. Figure 12 shows:

116 Fuzzy Logic - Tool for Getting Accurate Solutions

This procedure is based on research provided in [10].

The speed reference channel filter has a time constant value: [4].



Thus, in summary, one has:

 **6. Ramp type firing circuit** 

SPEED REGULATOR




߬௦ଵ ൌ Ͷߪ<sup>ᇱ</sup> ൌ ͶͲሾ݉ݏሿ

The firing system used is ramp type, implemented with the TCA 780 integrated circuit,

and increasing the efficiency of such systems.

whose circuit description and explanation are not the objective of this work.

of interest (current regulator) are obtained by:

to conventional compensators.

This procedure is based according to reference [10].

**7.2. Fuzzy control**

increase the efficiency of such systems.

**7. Control using fuzzy logic** 

**7.1 Fuzzy regulator** 

With the objective of understanding how this type of regulator works, it is helpful to under‐ stand the basics of fuzzy logic. Based on the theory of the fuzzy sets proposed by ZADEH in 1965 [9], this type of logic has proven to be one of the most interesting technologies for application in sophisticated control systems, providing a simple approach to decreasing costs

This chapter provides an introduction to this technology in the controlled drive of a DC machine with series excitation aimed at speed control and current limitation. According to [8], this type of system (a non-linear process) is better controlled with fuzzy controllers as opposed

The theory for control using fuzzy logic characterizes the variables of interest through linguistic expressions such as "very large", "large", "small", "hot", "cold", etc. These linguistic expressions are numerically represented by fuzzy sets, each set being characterized by a pertinence function varying from 0 to 1. The fuzzy control algorithm performs control actions written in terms of these imprecise ideas. The input variables of the fuzzy controller considered

machine with series excitation aiming at the speed control and current limitation.

() () () *real ref IE k I k I k* = - (30)

*PE k GEi IE k* () () = ´ (31)

shown in Figure 8. Three TCA 780 integrated circuits should be used to produce six firing The pertinence functions are shown in Figure 13; variables are expressed in "pu",. The universe is adopted according to operational conditions.

pulses, for the thyristorized GRAETZ converter bridge, which are P1 and P2, for the thyristors 1 and 4; P3 and P6, for the thyristors 3 and 6; and P5 and P2, for the thyristors 5 and 2, respectively. This is the explanation of the firing circuit pulse generation stage. The Each control and action variable is decomposed into a set of fuzzy sets called labels. Generally, each label or fuzzy subset has an asymmetric form, with a trend toward a larger concentration close to the origin of cartesian axis. This allows for greater precision in the control close to the steady operation point.

other ones are: enlargement of pulses, galvanic isolation of pulses and pulse amplification, The number of labels associated with one given variable must be an odd number between 5 and 9. Additionally, the end of each label must overlap those of neighbouring labels. This overlapping provides the fuzzy controller with continuous and steady action. The overlapping must be between 10 and 50% of the neighbouring area and the sum of the vertical points of the overlapping must preferably be less than 1.

> The control does not require an accuracy modelling. The model can be unknown or badly defined.

 With the objective to understand how this kind of regulator works, it is convenient to understand a little of the Fuzzy Logic. Based on the theory of the fuzzy sets proposed by ZADEH in 1965 [9], this logic has shown to be one of the most interesting technologies for application in sophisticated control systems, providing a simple way to decrease costs and The components of a conventional and of a fuzzy control system are more or less similar. The differences reside in the fact that in the fuzzy system, there is an element that converts the inputs into their fuzzy representations, i.e., the fuzzifier and another that converts the fuzzy outputs inferred into a solution, a numerical and precise value, i.e., the defuzzifier. In a fuzzy system, the value of an input is converted by the fuzzifier. Afterwards, control rules that are met are performed. This process produces a new fuzzy set representing each output or variable solution. The defuzzifier creates a value for the variable output of this new fuzzy set. The output value actuates the physical system. The change is picked up by a sensor and the control is restarted.

 This chapter proposes the introduction of this technology in the controlled drive of a DC The fuzzy variables are defined at a numerical interval commonly called the "universe of discourse". The fuzzy rules are typically of the conditional form IF-THEN, as follows:

13.

$$H\left(\mathbf{^\*}\mathbf{x}^\*\mathbf{\dot{s}}\mathbf{A} \mathbf{ \dot{z}}\mathbf{a}^\*\mathbf{y}^\*\mathbf{\dot{s}}\mathbf{s}\mathbf{B}\right) \mathbf{THEM}\left(\mathbf{^\*}\mathbf{z}^\*\mathbf{\dot{s}}\mathbf{C}\right) \tag{33}$$

Where "x" and "y" are fuzzy variables and A, B and C are fuzzy subsets in the universe of discourse X, Y and Z, respectively. If the condition expressed in the rule is met, then the action specified is performed. To design a fuzzy controller, a series of rules must be built. specified is performed. To design a fuzzy controller, a series of rules must be built. In this case, the error (IE), the error integral (IIE) and the control signal (VCC) are

discourse X, Y, Z respectively. If the condition expressed in the rule is met, then the action

In this case, the error (IE), the error integral (IIE) and the control signal (VCC) are considered fuzzy variables, with possible values given by pertinence functions (µ) to fuzzy sets such as small positive, small negative, zero and so on. considered fuzzy variables, with possible values given by pertinence functions () to fuzzy sets such as small positive, small negative, zero, and so on.

The pertinence functions for the error variable can be represented according to Figure 13. The pertinence functions for the error variable might be represented according to figure

Figure 13. Representation of the typical pertinence functions for a fuzzy variable. **Figure 13.** Representation of the typical pertinence functions for a fuzzy variable.

### **7.3. Design of the fuzzy controller — Current regulator**

**7.3 Design of the fuzzy controller – Current regulator**  Figure 14 shows a representation of the pertinence functions.

 Figure 14 shows representation of the pertinence functions. LN SN Z SP LP Current Error (IE) The elaboration of rules can be based on the intuition and experience of the designer. The number of rules is related to the number of control variables. For the case under study, there were two control variables, each divided into five fuzzy subsets, producing 25 possible input combinations. Thus, 25 rules may be necessary. Here, some care must be taken regarding the number of rules. As each rule represents a part of the knowledge presented, eliminating rules implies omitting information. The fuzzy controller is designed with the help of a control algorithm that considers fuzzification and defuzzification, as well as and all the rules all other rules pertaining to \*\*\*\*. Table 1 shows the base rules adopted for the current fuzzy control in a matrix format.


Integral of the Current Error (IIE)

LN SN Z SP LP


LN SN Z SP LP

Control Signal (V CC )


The elaboration of the rules can be based on intuition and experience of the designer. The

number of rules is related to the number of control variables. For the case under study, there

are two control variables, each of them divided into 5 fuzzy subsets, producing 25 possible

input combinations. Thus, 25 rules can be necessary. Here, some care must be taken about

the number of rules. As each rule represents part of the knowledge, eliminating rules

Figure 14. Representation of the pertinence functions.

Universe

ܨܫሺ̶̶̶̶ሻሺ̶̶ሻሺ͵͵ሻ

 Where "x" and "y" are fuzzy variables and A, B, and C are fuzzy subsets in the universe of discourse X, Y, Z respectively. If the condition expressed in the rule is met, then the action

 In this case, the error (IE), the error integral (IIE) and the control signal (VCC) are considered fuzzy variables, with possible values given by pertinence functions () to fuzzy

The pertinence functions for the error variable might be represented according to figure

Positive

Lage Positive

specified is performed. To design a fuzzy controller, a series of rules must be built.

LN SN SP LP 

Negative Zero Small

Figure 13. Representation of the typical pertinence functions for a fuzzy variable.

Small

sets such as small positive, small negative, zero, and so on.

Lage Negative

Figure 14 shows representation of the pertinence functions.

13.

**Figure 14.** Representation of the pertinence functions.

*IF*("x" is A and "y" is B THEN "z" is C ) () (33)

Where "x" and "y" are fuzzy variables and A, B and C are fuzzy subsets in the universe of discourse X, Y and Z, respectively. If the condition expressed in the rule is met, then the action

ܨܫሺ̶̶̶̶ሻሺ̶̶ሻሺ͵͵ሻ

In this case, the error (IE), the error integral (IIE) and the control signal (VCC) are considered fuzzy variables, with possible values given by pertinence functions (µ) to fuzzy sets such as

The pertinence functions for the error variable can be represented according to Figure 13.

specified is performed. To design a fuzzy controller, a series of rules must be built.

specified is performed. To design a fuzzy controller, a series of rules must be built.

LN SN SP LP

Negative Zero Small

Figure 13. Representation of the typical pertinence functions for a fuzzy variable.

Positive

LN SN Z SP LP

Current Error (IE)

The elaboration of rules can be based on the intuition and experience of the designer. The number of rules is related to the number of control variables. For the case under study, there were two control variables, each divided into five fuzzy subsets, producing 25 possible input combinations. Thus, 25 rules may be necessary. Here, some care must be taken regarding the number of rules. As each rule represents a part of the knowledge presented, eliminating rules implies omitting information. The fuzzy controller is designed with the help of a control algorithm that considers fuzzification and defuzzification, as well as and all the rules all other rules pertaining to \*\*\*\*. Table 1 shows the base rules adopted for the current fuzzy control in


Integral of the Current Error (IIE)

LN SN Z SP LP


LN SN Z SP LP

Control Signal (V CC )


The elaboration of the rules can be based on intuition and experience of the designer. The

number of rules is related to the number of control variables. For the case under study, there

are two control variables, each of them divided into 5 fuzzy subsets, producing 25 possible

input combinations. Thus, 25 rules can be necessary. Here, some care must be taken about

the number of rules. As each rule represents part of the knowledge, eliminating rules

Lage Positive

Universe

Small

**Figure 13.** Representation of the typical pertinence functions for a fuzzy variable.

**7.3. Design of the fuzzy controller — Current regulator**

Figure 14 shows a representation of the pertinence functions.

small positive, small negative, zero and so on.

sets such as small positive, small negative, zero, and so on.

118 Fuzzy Logic - Tool for Getting Accurate Solutions

Lage Negative

**7.3 Design of the fuzzy controller – Current regulator** 

a matrix format.

Figure 14. Representation of the pertinence functions.

Figure 14 shows representation of the pertinence functions.

13.


Where: LN = Large Negative; SN = Small Negative; ZE = Zero; SP = Small Positive; LP = Large Positive.

**Table 1.** Base rules for the current fuzzy control.

As illustrated in Figures 13 and 14, an input numerical value can be a member of more than one fuzzy set. For this, it is sufficient for the value to be situated in an overlapping region. So it means that, for a specific pair of values IE and IIE, more than one rule can be activated. Therefore, the existence of a means for combining the control actions activated by each rule is required so that a simple but significant action can be performed by combining all of these rules. This is the function of the defuzzifier. There are several methods for transformation of the output fuzzy set into a precise value, the latter representing the solution. The centroid method is well-indicated for control systems. Using this method, we can calculate the gravity centre of the activated fuzzy rules, producing a result that is sensitive to all rules and which tends to dislocate itself smoothly through the control surface. The defuzzification by the centroid method selects the output as a value corresponding to the gravity centre of the output pertinence function as is given by (34) as:

$$\mathbf{X}\_{0} = \frac{\int \mathbf{x} \mu\left(\mathbf{x}\_{1}\right) \mu\left(\mathbf{x}\_{2}\right) d\mathbf{x}}{\int \mu\left(\mathbf{x}\_{1}\right) \mu\left(\mathbf{x}\_{2}\right) d\mathbf{x}} = \frac{\sum\_{i=1}^{n} \mathbf{x}\_{i} \mu\left(I\mathbf{E}\_{i}\right) \mu\left(I\mathbf{I}\mathbf{E}\_{i}\right)}{\sum\_{i=1}^{n} \mu\left(I\mathbf{E}\_{i}\right) \mu\left(I\mathbf{I}\mathbf{E}\_{i}\right)}\tag{34}$$

Where:

Vcc = X0 = Gravity centre of the output pertinence function

xi = Gravity centre of the output pertinence function activated by each rule

µ (xi ) = Pertinence function activated by each rule

### **7.4. Design of the fuzzy controller — Speed regulator**

Similar to the current regulator, a diffuse speed regulator can be selected. The variables are the speed error, its integral and the regulator output information, which provides the input of the current regulator. The error of this grid will be the difference between the speed reference (nref) and the real speed (nreal). Corresponding pertinence functions are defined for the speed grid variables. The rules table can be similar to the current grid (Table 1), as it is a standard for several types of fuzzy controller applications. The scale factors (or gains) of a diffuse controller for the speed grid can be termed as GEn and GVn, respectively.

### **8. Experimental results**

The data input parameters for digital control fuzzy regulators were as follows.

### **Speed regulator**

Gen = 5.2 (proportional gain The practice adjusted value was 4.0. GVn = 2.17 (integral gaininverse of the integral time constant τn); digital filter of the reference value – time constant = Tgs1 = 460 [ms] (used only for digital control using conventional PI regulators).

Filter of the speed feedback transducer (analogical) – time constant = Tgn = 100 [ms] (imple‐ mented with RC components for both controls as digital fuzzy regulators and conventional ones).

### **Current regulator**

GEi = 0.8 (proportional gain). The practice adjusted value was 0.1. GVi = 73.2 (integral gaininverse of the integral time constant τ<sup>i</sup> ); digital filter of the reference value – time constant = Tgs2 = 15.84 [ms] (used only for digital control using conventional PI regulators).

Filter of the current feedback transducer (analogical) – time constant = Tgi = 1.5 [ms] (imple‐ mented with RC components, for both controls, as digital fuzzy regulators and conventional ones).

The dynamic behaviour of the controlled drive was verified. The current limiting was adjusted to 1.20 [pu]. The graphs of illustrations were provided with scales and locations: current (top)- 1 division = 5.5 [A]; speed (bottom)- 1 division = 1000[rpm]; time/div.= 2.5[s].

The machine data were: 1.7[kW], 220[V], 7.72 [A], 1500[rpm].

centre of the activated fuzzy rules, producing a result that is sensitive to all rules and which tends to dislocate itself smoothly through the control surface. The defuzzification by the centroid method selects the output as a value corresponding to the gravity centre of the output

> . . . .

*x x dx IE IIE* = =

Similar to the current regulator, a diffuse speed regulator can be selected. The variables are the speed error, its integral and the regulator output information, which provides the input of the current regulator. The error of this grid will be the difference between the speed reference (nref) and the real speed (nreal). Corresponding pertinence functions are defined for the speed grid variables. The rules table can be similar to the current grid (Table 1), as it is a standard for several types of fuzzy controller applications. The scale factors (or gains) of a diffuse controller

Gen = 5.2 (proportional gain The practice adjusted value was 4.0. GVn = 2.17 (integral gaininverse of the integral time constant τn); digital filter of the reference value – time constant =

Filter of the speed feedback transducer (analogical) – time constant = Tgn = 100 [ms] (imple‐ mented with RC components for both controls as digital fuzzy regulators and conventional

GEi = 0.8 (proportional gain). The practice adjusted value was 0.1. GVi = 73.2 (integral gain-

); digital filter of the reference value – time constant =

*x x x dx x IE IIE*

*n*

*n*

m

m

( )( ) ( )( )

(34)

 m

*ii i i*

*i i i*

 m

()() ()()

 m

 m

m

m

Vcc = X0 = Gravity centre of the output pertinence function

) = Pertinence function activated by each rule

**7.4. Design of the fuzzy controller — Speed regulator**

for the speed grid can be termed as GEn and GVn, respectively.

The data input parameters for digital control fuzzy regulators were as follows.

Tgs1 = 460 [ms] (used only for digital control using conventional PI regulators).

Tgs2 = 15.84 [ms] (used only for digital control using conventional PI regulators).

**8. Experimental results**

**Speed regulator**

**Current regulator**

inverse of the integral time constant τ<sup>i</sup>

ones).

= = ò å ò å

1 2 1

1 2 <sup>1</sup>

= Gravity centre of the output pertinence function activated by each rule

pertinence function as is given by (34) as:

120 Fuzzy Logic - Tool for Getting Accurate Solutions

0

*X*

Where:

xi

µ (xi

Figure 15 shows the machine speed and current response during start-up and for a load disturbance torque of 0.33 pu, negative and positive, respectively, using conventional digital PI regulators. The perfect current limiting and speed regulation could then be observed.

Figure 16 shows the machine current and speed response when the negative and positive steps of 0.33 pu in the speed reference set point occurred, respectively, using conventional digital PI regulators.

Figure 17 shows the response of the machine speed and current during start-up and for a load disturbance torque of 0.33 pu, negative and positive, respectively, using digital PI fuzzy regulators. The perfect current limiting and speed regulation could then be observed.

Figure 18 shows the machine current and speed response when negative and positive steps of 0.33 pu in the speed reference set point occurred, respectively, using digital PI fuzzy regulators.

**Figure 15.** Machine current and speed during start-up and for a load disturbance torque of 0.33 pu, negative and posi‐ tive, respectively, using conventional digital PI regulators.

**Figure 16.** Machine current and speed when a negative and positive step of 0.33 pu in the speed reference set point occurred, respectively, using conventional digital PI regulators.

**Figure 17.** Machine current and speed during start-up and for a load disturbance torque of 0.33 pu, negative and posi‐ tive, respectively, using digital PI fuzzy regulators.

**Figure 18.** Machine current and speed when a negative and positive step of 0.33 pu in the speed reference set point occurred, respectively, using digital PI fuzzy regulators.

### **9. Conclusion**

**Figure 16.** Machine current and speed when a negative and positive step of 0.33 pu in the speed reference set point

**Figure 17.** Machine current and speed during start-up and for a load disturbance torque of 0.33 pu, negative and posi‐

occurred, respectively, using conventional digital PI regulators.

122 Fuzzy Logic - Tool for Getting Accurate Solutions

tive, respectively, using digital PI fuzzy regulators.

The experimental results obtained in the laboratory for the present study were satisfactory. The control with fuzzy regulators for the driving of a DC machine with series excitation was shown to be stable and efficient.

The most significant contribution of this work is the experimental implementation of fuzzy regulators in the control application of a non-linear DC series-motor drive. The system is simple to implement, for both DC motors and AC machines, replacing the traditional analogue controllers and allowing for an inexpensive and simple design. A comparison of dynamic drive performance showed that when conventional digital PI and fuzzy regulators were used, a response to steps in load torque (load disturbance torque) and in the speed reference set point was less oscillatory that when digital PI fuzzy regulators were employed, and comparatively so when digital conventional PI regulators were used. In fact, fuzzy logic control was extremely efficient for controlling non-linear systems [7].

Due to the wide flexibility offered by this type of control, the developed technique and the used equipment outlined in this paper can also be used to control other types of general systems.

### **Appendix**

```
CONTROLED DC MOTOR DRIVE PROGRAM USING FUZZY LOGICS (PI-FUZZY) REGULATORS:
/*
*******************************************************************************
*************
* Program : PI Fuzzy Controller *
* Description : Digital control actuator for a series DC motor using a *
* PCL-711B card *
* Version : 2 *
* Date : 25/07/2014 *
*************************************************************************
*/
include <stdio.h>
#include <conio.h> /* Accept directives, including codes*/
#include <stdlib.h> /* of sources, of others */
#include <dos.h> /* programs and directories. */
#include <timer.h> /* program timer */
#include <math.h> /* math functions */
/* Global Variables Declaration */
extern "C" pcl711(int, unsigned int *); /* Includes Function "pcl711"
integer defined, unsigned in a separate module using "C" language*/
unsigned int param[60]; /* Definition of an array of data that make up the 
table and unsigned integer parameters */
unsigned int datain[200], dataout[200]; /* 10 integer data Buffer +
 for conversion*/
unsigned int far * datin, * datout;
/* Above data buffer address
 - pointer – type integer and long:
 2 words with range of 1Mbyte */
int tecla,i, cont1, cont2=0; /* Keyboard reading variables
and number of channels */
/* Variables and control floating points */
float nRef= 1.00, nReal=0.0, ne=nRef, iRef, iR,ie, iReal=0.0 , ilim=1.2;
float a1, a2, b1, b2, b3, b4;
float DataBuf[3];
float Vc1, e, v , Vi1=0.0, j, dd1 ,u1 , Gv1 = 5.2, Ge1=2.17, dt=0.003;
float
ceNL=-1.2, ceNS=-1.0, ceZE= 0.0, cePS= 1.0, cePL= 1.2,
beNL= 1.0, beNS= 1.0, beZE= 1.0, bePS= 1.0, bePL= 1.0,
cvNL=-1.2, cvNS=-1.0, cvZE= 0.0, cvPS= 1.0, cvPL= 1.2,
bvNL= 1.0, bvNS= 1.0, bvZE= 1.0, bvPS= 1.0, bvPL= 1.0,
caNL=-1.2, caNS=-1.0, caZE= 0.0, caPS= 1.0, caPL= 1.2,
ueNL, ueNS, ueZE, uePS, uePL,
uvNL, uvNS, uvZE, uvPS, uvPL;
float r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15, r16,
r17, r18, r19, r20, r21, r22, r23, r24, r25;
float Vc2,e2,v2, Vi2=0.0, dd2, Gv2 = 0.8 , Ge2 = 73.2 , u2 ;
float
ceNL2=-1.5, ceNS2=-1.0, ceZE2= 0.0, cePS2= 1.0, cePL2= 1.5,
beNL2= 1.0, beNS2= 1.0, beZE2= 1.0, bePS2= 1.0, bePL2= 1.0,
```

```
cvNL2=-1.5, cvNS2=-1.0, cvZE2= 0.0, cvPS2= 1.0, cvPL2= 1.5,
bvNL2= 1.0, bvNS2= 1.0, bvZE2= 1.0, bvPS2= 1.0, bvPL2= 1.0,
caNL2=-1.5, caNS2=-1.0, caZE2= 0.0, caPS2= 1.0, caPL2= 1.5,
ueNL2, ueNS2, ueZE2, uePS2, uePL2,
uvNL2, uvNS2, uvZE2, uvPS2, uvPL2;
float r26, r27, r28, r29, r30, r31, r32, r33, r34, r35, r36, r37, r38, r39, 
r40, r41,
r42, r43, r44, r45, r46, r47, r48, r49, r50;
/* Variable Declaration void – means it does not return a value */
void conv_ad(void);
void conv_da(void);
void control1(void);
void control2(void);
void teclado(void);
/* Analog, Digital Conversion Subroutine */
void conv_ad()
{
unsigned int i;
/* Pointer – Memory space – Variable that contains an address, */
/* usually another variable's address." */
datin = datain; /* Assigns the equivalent value to the datin pointer... data-
in variable */
param[0] = 0; /* Card number */
param[1] = 0x220; /* I/O Base Address */
/* sampling frequency = card base frequency /(C1 * C2) */
/* 2M / (10 * 10) = 20 kHz */
param[5] = 10; /* Constant divisor C1 */
param[6] = 10; /* Constant divisor C2 */
param[7] = 0; /* Mode Trigger, 0 : pacer trigger
Allows D/I functions */
/* Buffer Offset, memory address (Buffer) where data will be stored, Segment, 
data Buffer length
*/
param[10] = FP_OFF(datin); /* A/D Buffer A Offset */
param[11] = FP_SEG(datin); /* A/D Buffer A Segment */
param[12] = 0; /* Buffer B Addresss (unused)*/
param[13] = 0; /* Segment- Unused, set to 0 */
/* The A/D conversion covers two input channels, channel 1 – current, and chan-
nel 0 – speed, with values in pu adjusted in +/- 5 V */
param[14] = 2; /* Number of A/D conversions */
param[15] = 0; /* Channel of the A/D conversion initiation*/
param[16] = 1; /* Stop A/D conversion channel*/
param[17] = 0; /* Channel gains, 0 : +/- 5V */
/* conversion A/D fault indication*/
pcl711(3, param); /* Function 3 : Hardware initialization */
if (param[45] != 0) { /* If parameter 45 is different from 0, do: */
 clrscr(); /* Clear screen */
 printf("\n DRIVER INITIALIZATION FAILED!"); /* Print */
 getch(); /* Shows exit screen */
 exit(1); /* Closes loop and exit with status 1 - Error */
 }
pcl711(4, param); /* Function 4 : Conversor A/D initialization*/
```
**Appendix**

/\*

\*/

\*\*\*\*\*\*\*\*\*\*\*\*\*

124 Fuzzy Logic - Tool for Getting Accurate Solutions

\* PCL-711B card \*

include <stdio.h>

CONTROLED DC MOTOR DRIVE PROGRAM USING FUZZY LOGICS (PI-FUZZY) REGULATORS:

\* Program : PI Fuzzy Controller \*

#include <conio.h> /\* Accept directives, including codes\*/

\* Version : 2 \*

#include <stdlib.h> /\* of sources, of others \*/ #include <dos.h> /\* programs and directories. \*/

\* Date : 25/07/2014 \*

#include <timer.h> /\* program timer \*/ #include <math.h> /\* math functions \*/ /\* Global Variables Declaration \*/

table and unsigned integer parameters \*/

/\* Variables and control floating points \*/

r17, r18, r19, r20, r21, r22, r23, r24, r25;

unsigned int far \* datin, \* datout; /\* Above data buffer address

and number of channels \*/

float DataBuf[3];

float

float

float a1, a2, b1, b2, b3, b4;

ueNL, ueNS, ueZE, uePS, uePL, uvNL, uvNS, uvZE, uvPS, uvPL;

for conversion\*/

 - pointer – type integer and long: 2 words with range of 1Mbyte \*/

ceNL=-1.2, ceNS=-1.0, ceZE= 0.0, cePS= 1.0, cePL= 1.2, beNL= 1.0, beNS= 1.0, beZE= 1.0, bePS= 1.0, bePL= 1.0, cvNL=-1.2, cvNS=-1.0, cvZE= 0.0, cvPS= 1.0, cvPL= 1.2, bvNL= 1.0, bvNS= 1.0, bvZE= 1.0, bvPS= 1.0, bvPL= 1.0, caNL=-1.2, caNS=-1.0, caZE= 0.0, caPS= 1.0, caPL= 1.2,

float Vc2,e2,v2, Vi2=0.0, dd2, Gv2 = 0.8 , Ge2 = 73.2 , u2 ;

ceNL2=-1.5, ceNS2=-1.0, ceZE2= 0.0, cePS2= 1.0, cePL2= 1.5, beNL2= 1.0, beNS2= 1.0, beZE2= 1.0, bePS2= 1.0, bePL2= 1.0,

\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*

\* Description : Digital control actuator for a series DC motor using a \*

\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*

extern "C" pcl711(int, unsigned int \*); /\* Includes Function "pcl711" integer defined, unsigned in a separate module using "C" language\*/

unsigned int datain[200], dataout[200]; /\* 10 integer data Buffer +

int tecla,i, cont1, cont2=0; /\* Keyboard reading variables

float nRef= 1.00, nReal=0.0, ne=nRef, iRef, iR,ie, iReal=0.0 , ilim=1.2;

float Vc1, e, v , Vi1=0.0, j, dd1 ,u1 , Gv1 = 5.2, Ge1=2.17, dt=0.003;

float r1, r2, r3, r4, r5, r6, r7, r8, r9, r10, r11, r12, r13, r14, r15, r16,

unsigned int param[60]; /\* Definition of an array of data that make up the

```
if (param[45] != 0) {
 clrscr();
 printf("\n A/D INITIALIZATION FAILURE!");
 getch();
 exit(1);
 }
pcl711(5, param); /* Function 5 : verification of the number of A/D conver-
sions */
if (param[45] != 0) {
 clrscr();
 printf("\n A/D DATA TRANSFER SOFTWARE FAILURE!");
 getch();
 exit(1);
 }
/* A/D Conversions */
for (i = 0; i < param[14]; i++) /* Sampled data – channels 0 e 1 */
 {
 DataBuf[i] = datain[i] & 0xFFF;
 /* Data collect for the buffer on the address 0xFFF
 (the first three hexadecimal digits can be reset because the
remaining, are sufficient to support 4096 binary digits) */
 DataBuf[i] =((5.0 - (-5)) * DataBuf[i] / 4096) + (-5);
 /* conversion so that the voltage signal is available for the recursive 
control equations
 (5 - (-5)) : Input range A/D (-5V to 5V)
 4096 : Scale range of the A/D - 12 bit
 DataBuf : Input data of the A/D
 (-5) : Beginning of the scale of the A/D "-5" V
 */
 }
/* Feedback voltage reading for the speed and current loops, under nominal 
load and speed.*/
/* speed signal conversion – correction to pu*/
 nReal=(DataBuf[0]/1.500);
/* current signal conversion - correction to pu */
iReal=(DataBuf[1]/1.493);
}
void control1()
{
ne = nRef - nReal ; /* Erro */
Vi1 = Vi1 + Gv1*ne*dt; /* Error integral */
if (Vi1 <cvNL) Vi1 = cvNL ; /* Limits */
if (Vi1 >cvPL) Vi1 = cvPL ;
e = Ge1 * ne ;
v = Vi1 ;
teclado(); /* Performs the subroutine that inspects the keystroke */
/* Fuzzification : Triangular Functions */
/* Analyzing with respect to "e" */
if ( ( ( ceNL - beNL ) <= e ) && ( e <= ( ceNL + beNL ) ) )
ueNL = 1.0 - ( fabs( ceNL - e) ) / beNL ;
elseueNL = 0.0 ;
if ( e <ceNL )
```

```
ueNL = 1.0 ;
if ( ( ( ceNS - beNS ) <= e ) && ( e <= ( ceNS + beNS ) ) )
ueNS = 1.0 - ( fabs( ceNS - e ) ) / beNS ;
elseueNS = 0.0 ;
if ( ( ( ceZE - beZE ) <= e ) && ( e <= ( ceZE + beZE ) ) )
ueZE = 1.0 - ( fabs( ceZE - e ) ) / beZE ;
elseueZE = 0.0 ;
if ( ( ( cePS - bePS ) <= e ) && ( e <= ( cePS + bePS ) ) )
uePS = 1.0 - ( fabs( cePS - e ) ) / bePS ;
elseuePS = 0.0 ;
if ( ( ( cePL - bePL ) <= e ) && ( e <= ( cePL + bePL ) ) )
uePL = 1.0 - ( fabs( cePL - e ) ) / bePL ;
elseuePL = 0.0 ;
if ( e >cePL)
uePL = 1.0 ;
/* Analyzing with respect to "v" */
if ( ( ( cvNL - bvNL ) <= v ) && ( v <= ( cvNL + bvNL ) ) )
uvNL = 1.0 - ( fabs( cvNL - v ) ) / bvNL ;
elseuvNL = 0.0 ;
if ( v <cvNL)
uvNL = 1.0 ;
if ( ( ( cvNS - bvNS ) <= v ) && ( v <= ( cvNS + bvNS ) ) )
uvNS = 1.0 - ( fabs( cvNS - v ) ) / bvNS ;
elseuvNS = 0.0 ;
if ( ( ( cvZE - bvZE ) <= v ) && ( v <= ( cvZE + bvZE ) ) )
uvZE = 1.0 - ( fabs( cvZE - v ) ) / bvZE ;
elseuvZE = 0.0 ;
if ( ( ( cvPS - bvPS ) <= v ) && ( v <= ( cvPS + bvPS ) ) )
uvPS = 1.0 - ( fabs( cvPS - v ) ) / bvPS ;
elseuvPS = 0.0 ;
if ( ( ( cvPL - bvPL ) <= v ) && ( v <= ( cvPL + bvPL ) ) )
uvPL = 1.0 - ( fabs( cvPL - v ) ) / bvPL ;
elseuvPL = 0.0 ;
if ( v >cvPL )
uvPL = 1.0 ;
/* Logical Implications – Product Operator*/
r1 = ueNL * uvNL ;
r2 = ueNL * uvNS ;
r3 = ueNL * uvZE ;
r4 = ueNL * uvPS ;
r5 = ueNL * uvPL ;
r6 = ueNS * uvNL ;
r7 = ueNS * uvNS ;
r8 = ueNS * uvZE ;
r9 = ueNS * uvPS ;
r10 = ueNS * uvPL ;
r11 = ueZE * uvNL ;
r12 = ueZE * uvNS ;
r13 = ueZE * uvZE ;
r14 = ueZE * uvPS ;
r15 = ueZE * uvPL ;
r16 = uePS * uvNL ;
```
if (param[45] != 0) {

if (param[45] != 0) {

/\* A/D Conversions \*/

control equations

load and speed.\*/

void control1()

e = Ge1 \* ne ; v = Vi1 ;

elseueNL = 0.0 ; if ( e <ceNL )

DataBuf[i] = datain[i] & 0xFFF;

DataBuf : Input data of the A/D

nReal=(DataBuf[0]/1.500);

ne = nRef - nReal ; /\* Erro \*/

if (Vi1 >cvPL) Vi1 = cvPL ;

iReal=(DataBuf[1]/1.493);

 (5 - (-5)) : Input range A/D (-5V to 5V) 4096 : Scale range of the A/D - 12 bit

/\* speed signal conversion – correction to pu\*/

Vi1 = Vi1 + Gv1\*ne\*dt; /\* Error integral \*/ if (Vi1 <cvNL) Vi1 = cvNL ; /\* Limits \*/

/\* Fuzzification : Triangular Functions \*/ /\* Analyzing with respect to "e" \*/

ueNL = 1.0 - ( fabs( ceNL - e) ) / beNL ;

/\* current signal conversion - correction to pu \*/

(-5) : Beginning of the scale of the A/D "-5" V

printf("\n A/D INITIALIZATION FAILURE!");

printf("\n A/D DATA TRANSFER SOFTWARE FAILURE!");

for (i = 0; i < param[14]; i++) /\* Sampled data – channels 0 e 1 \*/

 /\* Data collect for the buffer on the address 0xFFF (the first three hexadecimal digits can be reset because the remaining, are sufficient to support 4096 binary digits) \*/ DataBuf[i] =((5.0 - (-5)) \* DataBuf[i] / 4096) + (-5);

pcl711(5, param); /\* Function 5 : verification of the number of A/D conver-

/\* conversion so that the voltage signal is available for the recursive

/\* Feedback voltage reading for the speed and current loops, under nominal

teclado(); /\* Performs the subroutine that inspects the keystroke \*/

if ( ( ( ceNL - beNL ) <= e ) && ( e <= ( ceNL + beNL ) ) )

clrscr();

126 Fuzzy Logic - Tool for Getting Accurate Solutions

 getch(); exit(1); }

clrscr();

 getch(); exit(1); }

sions \*/

{

 \*/ }

}

{

```
r17 = uePS * uvNS ;
r18 = uePS * uvZE ;
r19 = uePS * uvPS ;
r20 = uePS * uvPL ;
r21 = uePL * uvNL ;
r22 = uePL * uvNS ;
r23 = uePL * uvZE ;
r24 = uePL * uvPS ;
r25 = uePL * uvPL ;
/* Defuzzification */
dd1 =
caNL*r1+caNL*r2+caNL*r3+caNS*r4+caZE*r5+caNL*r6+caNL*r7+caNS*r8+
caZE*r9+caPS*r10+caNL*r11+caNS*r12+caZE*r13+caPS*r14+caPL*r15+
caNS*r16+caZE*r17+caPS*r18+caPL*r19+caPL*r20+caZE*r21+caPS*r22+
caPL*r23+caPL*r24+caPL*r25;
u1 = dd1 /
(r1+r2+r3+r4+r5+r6+r7+r8+r9+r10+r11+r12+r13+r14+r15+r16+r17+r18+r19+
r20+r21+r22+r23+r24+r25);
//u = u/10.0 ;
if (u1 < -1.0) u1 = -ilim;
if (u1 > 1.0 ) u1 = ilim;
}
void control2()
{
/* Current Loop */
if(iRef>ilim) iRef = ilim ;
if(iRef<-ilim) iRef =-ilim ;
ie = iReal - iRef ; /* Error */
Vi2 = Vi2 + Gv2*ie*dt; /* Integral Error */
if (Vi2 < cvNL2) Vi2 = cvNL2 ; /* Limits */
if (Vi2 > cvPL2) Vi2 = cvPL2 ;
e2 = Ge2 * ie ;
v2 = Vi2 ;
/*: Triangular Functions Fuzzification */
/* Analysis in Relation to "e2" */
if ( ( ( ceNL2 - beNL2 ) <= e2 ) && ( e2 <= ( ceNL2 + beNL2 ) ) )
ueNL2 = 1.0 - ( fabs( ceNL2 - e2) ) / beNL2 ;
else ueNL2 = 0.0 ;
if ( e2 < ceNL2 )
ueNL2 = 1.0 ;
if ( ( ( ceNS2 - beNS2 ) <= e2 ) && ( e2 <= ( ceNS2 + beNS2 ) ) )
ueNS2 = 1.0 - ( fabs( ceNS2 - e2 ) ) / beNS2 ;
else ueNS2 = 0.0 ;
if ( ( ( ceZE2 - beZE2 ) <= e2 ) && ( e2 <= ( ceZE2 + beZE2 ) ) )
ueZE2 = 1.0 - ( fabs( ceZE2 - e2 ) ) / beZE2 ;
else ueZE2 = 0.0 ;
if ( ( ( cePS2 - bePS2 ) <= e2 ) && ( e2 <= ( cePS2 + bePS2 ) ) )
uePS2 = 1.0 - ( fabs( cePS2 - e2 ) ) / bePS2 ;
else uePS2 = 0.0 ;
if ( ( ( cePL2 - bePL2 ) <= e2 ) && ( e2 <= ( cePL2 + bePL2 ) ) )
uePL2 = 1.0 - ( fabs( cePL2 - e2 ) ) / bePL2 ;
else uePL2 = 0.0 ;
```

```
if ( e2 > cePL2)
uePL2 = 1.0 ;
/* Analysis in Relation to "v2" */
if ( ( ( cvNL2 - bvNL2 ) <= v2 ) && ( v2 <= ( cvNL2 + bvNL2 ) ) )
uvNL2 = 1.0 - ( fabs( cvNL2 - v2 ) ) / bvNL2 ;
else uvNL2 = 0.0 ;
if ( v2 < cvNL2)
uvNL2 = 1.0 ;
if ( ( ( cvNS2 - bvNS2 ) <= v2 ) && ( v2 <= ( cvNS2 + bvNS2 ) ) )
uvNS2 = 1.0 - ( fabs( cvNS2 - v2 ) ) / bvNS2 ;
else uvNS2 = 0.0 ;
if ( ( ( cvZE2 - bvZE2 ) <= v2 ) && ( v2 <= ( cvZE2 + bvZE2 ) ) )
uvZE2 = 1.0 - ( fabs( cvZE2 - v2 ) ) / bvZE2 ;
else uvZE2 = 0.0 ;
if ( ( ( cvPS2 - bvPS2 ) <= v2 ) && ( v2 <= ( cvPS2 + bvPS2 ) ) )
uvPS2 = 1.0 - ( fabs( cvPS2 - v2 ) ) / bvPS2 ;
else uvPS2 = 0.0 ;
if ( ( ( cvPL2 - bvPL2 ) <= v2 ) && ( v2 <= ( cvPL2 + bvPL2 ) ) )
uvPL2 = 1.0 - ( fabs( cvPL2 - v2 ) ) / bvPL2 ;
else uvPL2 = 0.0 ;
if ( v2 > cvPL2 )
uvPL2 = 1.0 ;
/* Logical Implications – Product Operator */
r26 = ueNL2 * uvNL2 ;
r27 = ueNL2 * uvNS2 ;
r28 = ueNL2 * uvZE2 ;
r29 = ueNL2 * uvPS2 ;
r30 = ueNL2 * uvPL2 ;
r31 = ueNS2 * uvNL2 ;
r32 = ueNS2 * uvNS2 ;
r33 = ueNS2 * uvZE2 ;
r34 = ueNS2 * uvPS2 ;
r35 = ueNS2 * uvPL2 ;
r36 = ueZE2 * uvNL2 ;
r37 = ueZE2 * uvNS2 ;
r38 = ueZE2 * uvZE2 ;
r39 = ueZE2 * uvPS2 ;
r40 = ueZE2 * uvPL2 ;
r41 = uePS2 * uvNL2 ;
r42 = uePS2 * uvNS2 ;
r43 = uePS2 * uvZE2 ;
r44 = uePS2 * uvPS2 ;
r45 = uePS2 * uvPL2 ;
r46 = uePL2 * uvNL2 ;
r47 = uePL2 * uvNS2 ;
r48 = uePL2 * uvZE2 ;
r49 = uePL2 * uvPS2 ;
r50 = uePL2 * uvPL2 ;
/* Defuzzification */
dd2 =
caNL2*r26+caNL2*r27+caNL2*r28+caNS2*r29+caZE2*r30+caNL2*r31+caNL2*r32+caNS2*r33
+
```
r17 = uePS \* uvNS ; r18 = uePS \* uvZE ; r19 = uePS \* uvPS ; r20 = uePS \* uvPL ; r21 = uePL \* uvNL ; r22 = uePL \* uvNS ; r23 = uePL \* uvZE ; r24 = uePL \* uvPS ; r25 = uePL \* uvPL ; /\* Defuzzification \*/

128 Fuzzy Logic - Tool for Getting Accurate Solutions

caPL\*r23+caPL\*r24+caPL\*r25;

r20+r21+r22+r23+r24+r25);

if (u1 < -1.0) u1 = -ilim; if (u1 > 1.0 ) u1 = ilim;

if(iRef>ilim) iRef = ilim ; if(iRef<-ilim) iRef =-ilim ; ie = iReal - iRef ; /\* Error \*/

if (Vi2 > cvPL2) Vi2 = cvPL2 ;

Vi2 = Vi2 + Gv2\*ie\*dt; /\* Integral Error \*/ if (Vi2 < cvNL2) Vi2 = cvNL2 ; /\* Limits \*/

/\*: Triangular Functions Fuzzification \*/ /\* Analysis in Relation to "e2" \*/

ueNL2 = 1.0 - ( fabs( ceNL2 - e2) ) / beNL2 ;

ueNS2 = 1.0 - ( fabs( ceNS2 - e2 ) ) / beNS2 ;

ueZE2 = 1.0 - ( fabs( ceZE2 - e2 ) ) / beZE2 ;

uePS2 = 1.0 - ( fabs( cePS2 - e2 ) ) / bePS2 ;

uePL2 = 1.0 - ( fabs( cePL2 - e2 ) ) / bePL2 ;

caNL\*r1+caNL\*r2+caNL\*r3+caNS\*r4+caZE\*r5+caNL\*r6+caNL\*r7+caNS\*r8+ caZE\*r9+caPS\*r10+caNL\*r11+caNS\*r12+caZE\*r13+caPS\*r14+caPL\*r15+ caNS\*r16+caZE\*r17+caPS\*r18+caPL\*r19+caPL\*r20+caZE\*r21+caPS\*r22+

(r1+r2+r3+r4+r5+r6+r7+r8+r9+r10+r11+r12+r13+r14+r15+r16+r17+r18+r19+

if ( ( ( ceNL2 - beNL2 ) <= e2 ) && ( e2 <= ( ceNL2 + beNL2 ) ) )

if ( ( ( ceNS2 - beNS2 ) <= e2 ) && ( e2 <= ( ceNS2 + beNS2 ) ) )

if ( ( ( ceZE2 - beZE2 ) <= e2 ) && ( e2 <= ( ceZE2 + beZE2 ) ) )

if ( ( ( cePS2 - bePS2 ) <= e2 ) && ( e2 <= ( cePS2 + bePS2 ) ) )

if ( ( ( cePL2 - bePL2 ) <= e2 ) && ( e2 <= ( cePL2 + bePL2 ) ) )

dd1 =

}

{

u1 = dd1 /

//u = u/10.0 ;

void control2()

e2 = Ge2 \* ie ; v2 = Vi2 ;

else ueNL2 = 0.0 ; if ( e2 < ceNL2 ) ueNL2 = 1.0 ;

else ueNS2 = 0.0 ;

else ueZE2 = 0.0 ;

else uePS2 = 0.0 ;

else uePL2 = 0.0 ;

/\* Current Loop \*/

```
caZE2*r34+caPS2*r35+caNL2*r36+caNS2*r37+caZE2*r38+caPS2*r39+caPL2*r40+
caNS2*r41+caZE2*r42+caPS2*r43+caPL2*r44+caPL2*r45+caZE2*r46+caPS2*r47+
caPL2*r48+caPL2*r49+caPL2*r50;
u2 = dd2 /
(r26+r27+r28+r29+r30+r31+r32+r33+r34+r35+r36+r37+r38+r39+r40+r41+r42+r43+r44+
r45+r46+r47+r48+r49+r50);
if (u2 < 0.0) u2 = 0.0;
if (u2 > 1.0) u2 = 1.0;
}
voidteclado()
{
/* The activation of these subroutine keys, allows online adjustment
system parameters, where settings are displayed on the output */
/* Keys "k" and "l" operating in the value of the reference speed */
if (tecla==108 &&nRef<1.0) nRef=nRef+0.01; /* Limited adjustment to */
if (tecla==107 &&nRef>-1.0) nRef=nRef-0.01; /* range -1.0<nRef<1.0 */
/* Keys "o" and "p" operating in the value of the reference speed */
if (tecla==112 &&nRef<1.0) nRef=nRef+0.05; /* Limited adjustment to */
if (tecla==111 &&nRef>-1.0) nRef=nRef-0.05; /* range -1.0<nRef<1.0 */
/* Keys "q" e "w" operating on the gain Gv1 */
if (tecla==119 && Gv1<99.95) Gv1 = Gv1+0.05 ;
if (tecla==113 && Gv1>0.05) Gv1 = Gv1-0.05 ;
/* Keys "s" e "d" operating on the gain Ge1 */
if (tecla==100 && Ge1< 99.95) Ge1=Ge1+0.05;
if (tecla==115 && Ge1> 0.05) Ge1=Ge1-0.05;
/* Keys "g" e "h" operating on the gain Gv2 */
if (tecla==103 && Gv2< 9.95) Gv2=Gv2+0.05;
if (tecla==104 && Gv2< 0.05) Gv2=Gv2-0.05;
/* Keys "m" e "n" operating on the gain Ge2 */
if (tecla==109 && Ge2< 9.95) Ge2=Ge2+0.05;
if (tecla==110 && Ge2> 0.05) Ge2=Ge2-0.05;
}
/* Digital-Analogic Conversion Subroutine */
voidconv_da()
{
datout=dataout; /* Assigns the equivalent value to the datout pointer
... dataout variable */
param[0]=0; /* Card number */
param[1]=0x220; /* I/O base address */
/* Buffer Offset ' the memory address (Buffer) where data
will be stored. Segment ' the length of the data buffer */
param[20] = FP_OFF(datout); /* Buffer A Offset D/A output data */
param[21] = FP_SEG(datout); /* Buffer A segment D/A output data */
param[22] = 0; /* Buffer B output address(unused) */
param[23] = 0; /* Output segment- Unused, set 0 */
param[24] = 1; /* Number of D/A conversions*/
param[25] = 0; /* D/A conversion initialization channel */
param[26] = 0; /* D/A conversion stop channel */
/* D/A conversion fault indicator */
pcl711(3, param); /* Function 3 : Hardware initialization */
if (param[45] != 0) { /* If parameter 45 different from 0, do: */
 clrscr(); /* Clear screen */
```

```
 printf("\n DRIVER INITIALIZATION FAILURE!"); /* Print */
 getch(); /* Output screen display */
 exit(1); /* Close loop and exit with status 1 - Error */
 }
pcl711(12, param); /* Function 12: D/A conversor initialization */
if (param[45] != 0) {
 clrscr();
 printf("\n D/A INITIALIZATION FAILURE !");
 getch();
 exit(1);
 }
pcl711(13, param); /* Function 13: number of D/A conversions verification*/
if (param[45] != 0) {
 clrscr();
 printf("\n D/A DATA TRANSFER SOFTWARE FAILURE!");
 getch();
 exit(1);
 }
/* conversion for the output voltage signal of the recursive control equations 
in pu to occupy an address space of the output data buffer. */
dataout[0]=(4095*u2); /* Base pu = 4095 */
}
/* Main program */
void main(void)
{
Timer t; /* Timer"t" */
clrscr(); /* Clear screen */
delay(500);
textbackground(4); /* Defines Red Background (4) */
gotoxy(5,2);
cprintf("FUZZY CONTROLLER FOR A DC MOTOR SPEED CONTROL: );
gotoxy(5,4);
delay(500);
cprintf(" Student : Otavio Henrique Salvi Vicentini n 9025 ");
gotoxy(5,5);
cprintf(" Advisor : prof. Angelo J. J. Rezek Date : 25/09/2014 ");
delay(500);
textbackground(1); /* Defines a Blue Background (1) */
gotoxy(1,15); cprintf(" [O] - Decreases the Speed [0.05] ");
gotoxy(40,15); cprintf(" [P] - Increases the Speed [0.05] ");
gotoxy(1,16); cprintf(" [K] - Decreases the Speed [0.01] ");
gotoxy(40,16); cprintf(" [L] - Increases the Speed [0.01] ");
gotoxy(1,17); cprintf(" [Q] - Decreases the Gain Gv1 [0.05] ");
gotoxy(40,17); cprintf(" [W] - Increases the Gain Gv2 [0.05] ");
gotoxy(1,18); cprintf(" [S] - Decreases the Gain Ge1 [0.05] ");
gotoxy(40,18); cprintf(" [D] - Increases the Gain Ge1 [0.05] ");
gotoxy(1,19); cprintf(" [G] - Decreases the Gain Gv2 [0.05] ");
gotoxy(40,19); cprintf(" [H] - Increases the Gain Gv2 [0.05] ");
gotoxy(1,20); cprintf(" [M] - Decreases the Gain Ge2 [0.05] ");
gotoxy(40,20); cprintf(" [N] - Increases the Gain Ge2 [0.05] ");
textbackground(4); /* Defines Red Background (4) */
gotoxy(13,24); cprintf(" PRESS ESC TO END PROGRAM ");
```
caZE2\*r34+caPS2\*r35+caNL2\*r36+caNS2\*r37+caZE2\*r38+caPS2\*r39+caPL2\*r40+ caNS2\*r41+caZE2\*r42+caPS2\*r43+caPL2\*r44+caPL2\*r45+caZE2\*r46+caPS2\*r47+

/\* The activation of these subroutine keys, allows online adjustment system parameters, where settings are displayed on the output \*/ /\* Keys "k" and "l" operating in the value of the reference speed \*/ if (tecla==108 &&nRef<1.0) nRef=nRef+0.01; /\* Limited adjustment to \*/ if (tecla==107 &&nRef>-1.0) nRef=nRef-0.01; /\* range -1.0<nRef<1.0 \*/ /\* Keys "o" and "p" operating in the value of the reference speed \*/ if (tecla==112 &&nRef<1.0) nRef=nRef+0.05; /\* Limited adjustment to \*/ if (tecla==111 &&nRef>-1.0) nRef=nRef-0.05; /\* range -1.0<nRef<1.0 \*/

datout=dataout; /\* Assigns the equivalent value to the datout pointer

/\* Buffer Offset ' the memory address (Buffer) where data will be stored. Segment ' the length of the data buffer \*/ param[20] = FP\_OFF(datout); /\* Buffer A Offset D/A output data \*/ param[21] = FP\_SEG(datout); /\* Buffer A segment D/A output data \*/

param[25] = 0; /\* D/A conversion initialization channel \*/

pcl711(3, param); /\* Function 3 : Hardware initialization \*/ if (param[45] != 0) { /\* If parameter 45 different from 0, do: \*/

param[22] = 0; /\* Buffer B output address(unused) \*/ param[23] = 0; /\* Output segment- Unused, set 0 \*/ param[24] = 1; /\* Number of D/A conversions\*/

param[26] = 0; /\* D/A conversion stop channel \*/

/\* Keys "q" e "w" operating on the gain Gv1 \*/ if (tecla==119 && Gv1<99.95) Gv1 = Gv1+0.05 ; if (tecla==113 && Gv1>0.05) Gv1 = Gv1-0.05 ; /\* Keys "s" e "d" operating on the gain Ge1 \*/ if (tecla==100 && Ge1< 99.95) Ge1=Ge1+0.05; if (tecla==115 && Ge1> 0.05) Ge1=Ge1-0.05; /\* Keys "g" e "h" operating on the gain Gv2 \*/ if (tecla==103 && Gv2< 9.95) Gv2=Gv2+0.05; if (tecla==104 && Gv2< 0.05) Gv2=Gv2-0.05; /\* Keys "m" e "n" operating on the gain Ge2 \*/ if (tecla==109 && Ge2< 9.95) Ge2=Ge2+0.05; if (tecla==110 && Ge2> 0.05) Ge2=Ge2-0.05;

/\* Digital-Analogic Conversion Subroutine \*/

param[1]=0x220; /\* I/O base address \*/

/\* D/A conversion fault indicator \*/

clrscr(); /\* Clear screen \*/

(r26+r27+r28+r29+r30+r31+r32+r33+r34+r35+r36+r37+r38+r39+r40+r41+r42+r43+r44+

caPL2\*r48+caPL2\*r49+caPL2\*r50;

r45+r46+r47+r48+r49+r50); if (u2 < 0.0) u2 = 0.0; if (u2 > 1.0) u2 = 1.0;

u2 = dd2 /

130 Fuzzy Logic - Tool for Getting Accurate Solutions

voidteclado()

}

{

}

{

voidconv\_da()

... dataout variable \*/ param[0]=0; /\* Card number \*/

```
do
{
tecla=0;
if (kbhit()) tecla=getch(); /* Control by keyboard */
j++; /* Increases the number of interactions by 1 */
t.reset(); /* Resets the timer "t" */
t.start(); /* Starts the timer */
asm cli;
conv_ad(); /* Performs A/D subroutine conversion */
asmsti;
ne = nRef-nReal;
control1();
if(iRef<ilim&&iRef>-ilim) control1();
if(iRef==ilim&& ne<0.0) control1();
if(iRef==-ilim&& ne>0.0) control1();
iRef = u1;
ie=iReal-iRef;
if(u2<0.9 && u2>.10) control2();
if(u2>=0.9 &&ie<0.0) control2();
if(u2<=.10 &&ie>0.0) control2();
asm cli;
conv_da(); /* Performs A/D subroutine conversion */
asmsti;
if (j>=100) /* Displays instant results each 100 interactions in the screen */
{
j=0;
gotoxy(7,8);
textbackground(1);
cprintf(" Time spent : %1.6f (s)", dt);
gotoxy(7,9);
cprintf(" Channel [0] - Speed : % 1.3f (pu) Gv1 %1.3f Ge1 %1.3f " , 
nReal,Gv1,Ge1);
gotoxy(7,10);
cprintf(" Channel [1] - Current : % 1.3f (pu) Gv2 %1.3f Ge2 %1.3f " , iRe-
al,Gv2,Ge2);
gotoxy(7,11);
cprintf(" Reference Speed : %1.2f (pu) iRef : %1.2f (pu) " , nRef,iRef);
gotoxy(7,12);
cprintf(" ne : %1.2f ie : %1.2f Vcontr : %1.2f (pu) ", ne, ie, u2);
}
t.stop(); /* Stops timer */
dt = t.time(); /* Sampling time */
} while (tecla!=27); /* Program ends when the Esc key and is pressed.*/
}
CONTROLED DC MOTOR DRIVE PROGRAM USING PI (PROPORTIONAL-INTEGRAL) REGULATORS, 
USING RECURSIVE EQUATIONS DERIVED FROM Z TRANSFORM:
/*
*******************************************************************************
*******************
* Program : MCC Control *
* Description : Digital control for a series DC motor using convention-
al digital
```

```
* PI regulators *
* PCL-711B board *
* Version : 2 *
* Date : 29/09/2014 *
*******************************************************************************
********************
*/
/* Inclusão de Diretivas */
#include <stdio.h>
#include <conio.h> /* Accept directives, including codes */
#include <stdlib.h> /* from other sources */
#include <dos.h> /* programs and folders */
#include <timer.h>
/* Declaração de Variáveis Globais */
extern "C" pcl711(int, unsigned int *); /*Includes function "pcl711" inte-
ger defined, unsigned in module separated using language "C"*/
unsigned int param[60]; /* Defining an data array -
– which makes up an unsigned integer parameter table */
unsigned int datain[200], dataout[200]; /* 10 integer data buffer +
 for conversion*/
unsigned int far * datin, * datout; /* Buffer address of data above
 - pointer – long and integer type:
 2 words with 1Mbyte range */
int tecla,i; /* Keyboard reading variables
 and number of channels*/
/* Control floating point variables */
float nRef=0.72, nReal=0.0, ne=nRef;
float ne_1=0.1, nReal_1=0.0;
float iRef=1.20, iR=1.20, ie=-1.20, iReal=0.0, Ilim=1.20, iRefer=1.20;
float iRef_1=1.20, iR_1=1.20, ie_1=-1.20, iReal_1=0.0, iRefer_1=1.20;
float Tn=0.460, Tgs2=0.01584, Ti=0.01366;
float VRn=5.20, VRi=0.8, Vcc=0.1, Vcc_1=0.1, Vcontr=0.1;
float a1, a2, b1, b2, b3, b4, T=0.003;
float DataBuf[3];
/* Variable declaration void – means it does not return a value */
void conv_ad(void);
void conv_da(void);
void control(void);
void control1(void);
void control2(void);
void teclado(void);
/* AD conversion – Parameters table */
void conv_ad()
{
unsigned int i;
 /* Pointer – Memory space – Variable that contains an address,
usually another variable's address */
datin = datain; /* Assigns to the datin pointer the
 equivalent value of datain variable */
param[0] = 0; /* Board number */
param[1] = 0x220; /* I/O base address */
/* Sampling frequency = Board base frequency/(C1 * C2) */
```
do { tecla=0;

asm cli;

asmsti;

iRef = u1; ie=iReal-iRef;

asm cli;

asmsti;

gotoxy(7,8); textbackground(1);

gotoxy(7,9);

al,Gv2,Ge2); gotoxy(7,11);

gotoxy(7,12);

t.stop(); /\* Stops timer \*/ dt = t.time(); /\* Sampling time \*/

\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*

al digital

}

}

/\*

nReal,Gv1,Ge1); gotoxy(7,10);

{ j=0;

ne = nRef-nReal; control1();

132 Fuzzy Logic - Tool for Getting Accurate Solutions

if (kbhit()) tecla=getch(); /\* Control by keyboard \*/ j++; /\* Increases the number of interactions by 1 \*/

conv\_ad(); /\* Performs A/D subroutine conversion \*/

conv\_da(); /\* Performs A/D subroutine conversion \*/

if (j>=100) /\* Displays instant results each 100 interactions in the screen \*/

cprintf(" Channel [0] - Speed : % 1.3f (pu) Gv1 %1.3f Ge1 %1.3f " ,

cprintf(" Channel [1] - Current : % 1.3f (pu) Gv2 %1.3f Ge2 %1.3f " , iRe-

cprintf(" Reference Speed : %1.2f (pu) iRef : %1.2f (pu) " , nRef,iRef);

} while (tecla!=27); /\* Program ends when the Esc key and is pressed.\*/

CONTROLED DC MOTOR DRIVE PROGRAM USING PI (PROPORTIONAL-INTEGRAL) REGULATORS,

\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*

\* Description : Digital control for a series DC motor using convention-

cprintf(" ne : %1.2f ie : %1.2f Vcontr : %1.2f (pu) ", ne, ie, u2);

USING RECURSIVE EQUATIONS DERIVED FROM Z TRANSFORM:

\* Program : MCC Control \*

t.reset(); /\* Resets the timer "t" \*/ t.start(); /\* Starts the timer \*/

if(iRef<ilim&&iRef>-ilim) control1(); if(iRef==ilim&& ne<0.0) control1(); if(iRef==-ilim&& ne>0.0) control1();

cprintf(" Time spent : %1.6f (s)", dt);

if(u2<0.9 && u2>.10) control2(); if(u2>=0.9 &&ie<0.0) control2(); if(u2<=.10 &&ie>0.0) control2();

```
 /* 2M / (10 * 10) = 20 KHz */
param[5] = 10; /* Constant divisor pacer C1 */
param[6] = 10; /* Constant divisor pacer C2 */
param[7] = 0; /* Trigger Mode, 0 : pacer trigger
 Allows D/I functions */
/* Buffer offset ' the memory address (buffer) where the data
will be stored. Segment' the length of the data buffer */
param[10] = FP_OFF(datin); /* A/D Buffer A offset */
param[11] = FP_SEG(datin); /* A/D Buffer A segment */
param[12] = 0; /* Buffer B address (unused)*/
param[13] = 0; /* Segment - unused, set to 0 */
/* The A/D conversion covers two input channels, channel 1 – current, and chan-
nel 0 – speed, with values in pu adjusted in +/- 5 V */
param[14] = 2; /* Number of A/D conversions */
param[15] = 0; /* Channel of the A/D conversion initiation*/
param[16] = 1; /* Stop A/D conversion channel*/
param[17] = 0; /* Channel gains, 0 : +/- 5V */
/* Conversion A/D fault indication*/
pcl711(3, param); /* Function 3 : Hardware initialization */
if (param[45] != 0) { /* If parameter 45 is different from 0, do: */
 clrscr(); /* Clear screen */
 printf("\n DRIVER INITIALIZATION FAILED!"); /* Print */
 getch(); /* Shows exit screen */
 exit(1); /* Closes loop e exit with status 1 - Error */
 }
pcl711(4, param); /* Function 4 : Converter A/D initialization*/
if (param[45] != 0) {
 clrscr();
 printf("\n A/D INITIALIZATION FAILED!");
 getch();
 exit(1);
 }
pcl711(5, param); /* Function 5 : Number of conversions A/D verification*/
if (param[45] != 0) {
 clrscr();
 printf("\n A/D DATA TRANSFER SOFTWARE FAILURE!");
 getch();
 exit(1);
 }
/* A/D conversions */
for (i = 0; i < param[14]; i++) /* Sampled data – channels 0 e 1 */
 {
 DataBuf[i] = datain[i] & 0xFFF;
 /* Data collect for the buffer on the address 0xFFF
 (the first three hexadecimal digits can be reset because the
remaining, sufficient to support 4096 binary digits) */
 DataBuf[i] =((5.0 - (-5)) * DataBuf[i] / 4096) + (-5);
 /* conversion so that the voltage signal is available for the recursive 
equations control
 (5 - (-5)) : Input range A/D (-5V to 5V)
 4096 : Scale range of the A/D - 12 bit
 DataBuf : Input data of the A/D
```

```
 (-5) : Beginning of the scale of the A/D "-5" V
 */
 }
/* Feedback voltage reading for the speed and current loop mesh, under nominal 
load and speed.*/
/* speed signal conversion – correction to pu*/
 nReal=(DataBuf[0]/1.500);
/* Current signal conversion - correction to pu */
 iReal=(DataBuf[1]/1.493);
}
/* Control */
/* Recursive Equations to perform functions of control */
void control()
{ /* Sampling time considered T */
a1=T/((2*Tgs2)+T);
 /*Tgs2= Filter time constant */
a2=((2*Tgs2)-T)/(T+(2*Tgs2));
b1=VRn+((VRn*T)/(2*Tn)); /* VRn= Speed regulator gain */
 /* Tn= Speed regulator time constant */
b2=((VRn*T)/(2*Tn))-VRn;
b3=VRi+((VRi*T)/(2*Ti)); /* VRi= Current regulator gain */
 /* Ti= Current regulator time constant */
b4=((VRi*T)/(2*Ti))-VRi;
}
/* Speed Regulator */
void control1()
 {
 iRef=(b1*ne)+(b2*ne_1)+iRef_1; /* nreal= Speed feedback */
 iRef_1=iRef; /* nRef= Post filter reference speed */
 ne_1=ne; /* ne= Speed error */
 /* iRef= Current reference - Output
 speed regulator */
/* Reference Current Filter */
iRefer=iRef;
 iR=a1*(iRefer+iRefer_1)+a2*iR_1; /* Which: */
 iR_1=iR; /* iR= Post filter current reference/
 iRefer_1=iRefer; /* iRef= Reference current */
 if(iR>=Ilim) iR=Ilim;
 if(iR<=-Ilim) iR=-Ilim; /* Current reference limit */
}
/* Current Regulator */
void control2()
 { /* Which: */
 Vcc=(b3*ie)+(b4*ie_1)+Vcc_1; /* ireal= feedback current */
 Vcc_1=Vcc; /* iR= Post filter reference current */
 ie_1=ie; /* ie= Current Error- In. regulator */
 if(Vcc>0.95) Vcontr=0.95;
 if(Vcc<.05) Vcontr=.05; /* Control voltage limit */
 if(Vcc<=0.95 && Vcc>=.05) Vcontr=Vcc;
}
/* System parameters alteration */
void teclado()
```
 /\* 2M / (10 \* 10) = 20 KHz \*/ param[5] = 10; /\* Constant divisor pacer C1 \*/ param[6] = 10; /\* Constant divisor pacer C2 \*/ param[7] = 0; /\* Trigger Mode, 0 : pacer trigger Allows D/I functions \*/

134 Fuzzy Logic - Tool for Getting Accurate Solutions

/\* Buffer offset ' the memory address (buffer) where the data will be stored. Segment' the length of the data buffer \*/ param[10] = FP\_OFF(datin); /\* A/D Buffer A offset \*/ param[11] = FP\_SEG(datin); /\* A/D Buffer A segment \*/ param[12] = 0; /\* Buffer B address (unused)\*/ param[13] = 0; /\* Segment - unused, set to 0 \*/

nel 0 – speed, with values in pu adjusted in +/- 5 V \*/

param[15] = 0; /\* Channel of the A/D conversion initiation\*/

pcl711(3, param); /\* Function 3 : Hardware initialization \*/

printf("\n DRIVER INITIALIZATION FAILED!"); /\* Print \*/

exit(1); /\* Closes loop e exit with status 1 - Error \*/

if (param[45] != 0) { /\* If parameter 45 is different from 0, do: \*/

pcl711(4, param); /\* Function 4 : Converter A/D initialization\*/

for (i = 0; i < param[14]; i++) /\* Sampled data – channels 0 e 1 \*/

 /\* Data collect for the buffer on the address 0xFFF (the first three hexadecimal digits can be reset because the

remaining, sufficient to support 4096 binary digits) \*/ DataBuf[i] =((5.0 - (-5)) \* DataBuf[i] / 4096) + (-5);

 (5 - (-5)) : Input range A/D (-5V to 5V) 4096 : Scale range of the A/D - 12 bit DataBuf : Input data of the A/D

pcl711(5, param); /\* Function 5 : Number of conversions A/D verification\*/

/\* conversion so that the voltage signal is available for the recursive

param[14] = 2; /\* Number of A/D conversions \*/

param[16] = 1; /\* Stop A/D conversion channel\*/ param[17] = 0; /\* Channel gains, 0 : +/- 5V \*/

/\* Conversion A/D fault indication\*/

clrscr(); /\* Clear screen \*/

}

 getch(); exit(1); }

 getch(); exit(1); }

{

if (param[45] != 0) { clrscr();

if (param[45] != 0) { clrscr();

/\* A/D conversions \*/

equations control

DataBuf[i] = datain[i] & 0xFFF;

getch(); /\* Shows exit screen \*/

printf("\n A/D INITIALIZATION FAILED!");

printf("\n A/D DATA TRANSFER SOFTWARE FAILURE!");

/\* The A/D conversion covers two input channels, channel 1 – current, and chan-

```
{
/* The activation of these subroutine keys, allows online adjustment of system 
parameters, with the settings being shown in the output screen */
 /* Keys "s" and "d" operating in the value of the reference speed */
 if (tecla==115 && nRef<1.0) nRef=nRef+1.44; /* Adjustment limited to */
 if (tecla==100 && nRef>-1.0) nRef=nRef-1.44; /* range -1.0<nRef<1.0 */
 /* Keys "k" and "l" operating in value of the reference speed */
 if (tecla==107 && nRef<1.0) nRef=nRef+0.01; /* Adjustment limited to */
 if (tecla==108 && nRef>-1.0) nRef=nRef-0.01; /* range -1.0<nRef<1.0 */
 /* Keys "o" and "p" operating in value of the reference speed */
 if (tecla==111 && nRef<1.0) nRef=nRef+0.05; /* Adjustment limited to */
 if (tecla==112 && nRef>-1.0) nRef=nRef-0.05; /* range -1.0<nRef<1.0 */
 /* Keys "f" and "v" operating in VRn gain */
 if (tecla==102 && VRn<40.0) VRn=VRn+0.05;
 if (tecla==118 && VRn>0.02) VRn=VRn-0.05;
 /* Keys "g" and "b" operating on time constant Tn */
 if (tecla==103 && Tn<5.00) Tn=Tn+0.05;
 if (tecla==98 && Tn>0.06) Tn=Tn-0.05;
/* Keys "h" and "n" operating in VRi gain */
 if (tecla==104 && VRi<10.0) VRi=VRi+0.05;
 if (tecla==110 && VRi>0.01) VRi=VRi-0.05;
 /* Keys "j" and "m" operating on time constant Ti */
 if (tecla==106 && Ti<1.000) Ti=Ti+0.005;
 if (tecla==109 && Ti>0.006) Ti=Ti-0.005;
}
/* D/A conversion – Parameter table */
void conv_da()
{
datout=dataout; /* Assigns the equivalent value to the datout pointer */
param[0]=0; /* Card number */
param[1]=0x220; /* I/O base address */
 /* Buffer Offset ' the memory address (Buffer) where data
will be stored. Segment ' the length of the data buffer */
param[20] = FP_OFF(datout); /* Buffer A Offset D/A output data */
param[21] = FP_SEG(datout); /* Buffer A segment D/A output data */
param[22] = 0; /* Buffer B output address(unused) */
param[23] = 0; /* Output segment- Unused, set 0 */
param[24] = 1; /* Number of D/A conversions*/
param[25] = 0; /* D/A conversion initialization channel */
param[26] = 0; /* D/A conversion stop channel */
/* D/A conversion fault indicator */
pcl711(3, param); /* Function 3 : Hardware initialization */
if (param[45] != 0) { /* If parameter 45 different from 0, do: */
 clrscr(); /* Clear screen */
 printf("\n DRIVER INITIALIZATION FAILURE!"); /* Print */
 getch(); /* Output screen display */
 exit(1); /* Close loop and exit with status 1 - Error */
 }
pcl711(12, param); /* Function 12: D/A converter initialization */
if (param[45] != 0) {
 clrscr();
 printf("\n D/A INITIALIZATION FAILURE !");
```

```
 getch();
 exit(1);
 }
pcl711(13, param); /* Function 13: number of D/A conversions verification*/
if (param[45] != 0) {
 clrscr();
 printf("\n D/A DATA TRANSFER SOFTWARE FAILURE!");
 getch();
 exit(1);
 }
 /* Conversion for the output voltage signal of the recursive control equa-
tions in pu to . occupy an address space of the output data buffer. */
dataout[0]=(4095*Vcontr);
}
/* Main program */
void main(void) /* Ensures that global variables do not return values */
{ /* Variable declarations */
int xx=0; /* Initializes the number of interactions in 0*/
Timer t; /* Time counter "t" */
clrscr(); /* Clear screen */
gotoxy(1,10); cprintf("[S] - Invert vel. [+]");
gotoxy(40,10); cprintf("[D] - Invert vel. [-]");
gotoxy(1,11); cprintf("[O] - Increments vel. [0.05]");
gotoxy(40,11); cprintf("[P] - Decrements vel. [0.05]");
gotoxy(1,12); cprintf("[K] - Increments vel. [0.01]");
gotoxy(40,12); cprintf("[L] - Decrements vel. [0.01]");
do{
tecla=0;
if (kbhit()) tecla=getch();
xx++; /* Increments 1 to the number of interactions */
t.reset(); /* Resets timer "t" */
t.start(); /* Starts timing */
asm cli;
conv_ad(); /* Performs the A/ D conversion subroutine */
asm sti;
control();
teclado(); /* Performs the inspecting keystroke subroutine */
ne=nRef-nReal;
if(iR<Ilim && iR>-Ilim) control1();
if(iR==Ilim && ne<0.0) control1();
if(iR==-Ilim && ne>0.0) control1();
ie=iReal-iR;
if(Vcc<0.95 && Vcc>.05)control2();
if(Vcc>=0.95 && ie<0.0 ) control2();
if(Vcc<=.05 && ie>0.0 ) control2();
asm cli;
conv_da(); /* Performs the D/A conversion subroutine */
asm sti;
if (xx>=10) {/* Prints instant results on screen every 100 interactions */
xx=0;
gotoxy(1,1);
cprintf("VRn= %1.3f Tn= %1.4f VRi= %1.3f Ti= %1.4f ", VRn, Tn, VRi, Ti);
```
{

136 Fuzzy Logic - Tool for Getting Accurate Solutions

}

{

void conv\_da()

}

if (param[45] != 0) { clrscr();

/\* The activation of these subroutine keys, allows online adjustment of system

datout=dataout; /\* Assigns the equivalent value to the datout pointer \*/

 /\* Keys "s" and "d" operating in the value of the reference speed \*/ if (tecla==115 && nRef<1.0) nRef=nRef+1.44; /\* Adjustment limited to \*/ if (tecla==100 && nRef>-1.0) nRef=nRef-1.44; /\* range -1.0<nRef<1.0 \*/ /\* Keys "k" and "l" operating in value of the reference speed \*/ if (tecla==107 && nRef<1.0) nRef=nRef+0.01; /\* Adjustment limited to \*/ if (tecla==108 && nRef>-1.0) nRef=nRef-0.01; /\* range -1.0<nRef<1.0 \*/ /\* Keys "o" and "p" operating in value of the reference speed \*/ if (tecla==111 && nRef<1.0) nRef=nRef+0.05; /\* Adjustment limited to \*/ if (tecla==112 && nRef>-1.0) nRef=nRef-0.05; /\* range -1.0<nRef<1.0 \*/

parameters, with the settings being shown in the output screen \*/

 /\* Keys "f" and "v" operating in VRn gain \*/ if (tecla==102 && VRn<40.0) VRn=VRn+0.05; if (tecla==118 && VRn>0.02) VRn=VRn-0.05;

 if (tecla==103 && Tn<5.00) Tn=Tn+0.05; if (tecla==98 && Tn>0.06) Tn=Tn-0.05; /\* Keys "h" and "n" operating in VRi gain \*/ if (tecla==104 && VRi<10.0) VRi=VRi+0.05; if (tecla==110 && VRi>0.01) VRi=VRi-0.05;

 if (tecla==106 && Ti<1.000) Ti=Ti+0.005; if (tecla==109 && Ti>0.006) Ti=Ti-0.005;

/\* D/A conversion – Parameter table \*/

param[1]=0x220; /\* I/O base address \*/

/\* D/A conversion fault indicator \*/

clrscr(); /\* Clear screen \*/

getch(); /\* Output screen display \*/

printf("\n D/A INITIALIZATION FAILURE !");

param[0]=0; /\* Card number \*/

/\* Keys "g" and "b" operating on time constant Tn \*/

/\* Keys "j" and "m" operating on time constant Ti \*/

 /\* Buffer Offset ' the memory address (Buffer) where data will be stored. Segment ' the length of the data buffer \*/ param[20] = FP\_OFF(datout); /\* Buffer A Offset D/A output data \*/ param[21] = FP\_SEG(datout); /\* Buffer A segment D/A output data \*/

param[22] = 0; /\* Buffer B output address(unused) \*/ param[23] = 0; /\* Output segment- Unused, set 0 \*/ param[24] = 1; /\* Number of D/A conversions\*/

param[26] = 0; /\* D/A conversion stop channel \*/

param[25] = 0; /\* D/A conversion initialization channel \*/

pcl711(3, param); /\* Function 3 : Hardware initialization \*/ if (param[45] != 0) { /\* If parameter 45 different from 0, do: \*/

printf("\n DRIVER INITIALIZATION FAILURE!"); /\* Print \*/

exit(1); /\* Close loop and exit with status 1 - Error \*/

pcl711(12, param); /\* Function 12: D/A converter initialization \*/

```
gotoxy(1,2);
cprintf("Time spent: %fs ", T);
gotoxy(1,3);
cprintf("canal[%3d] = % 1.3f (pu) canal[%3d] = % 1.3f (pu) ", 0, nReal, 1, iRe-
al);
gotoxy(1,4);
cprintf("nRef= %1.2f Vcontr= %1.2f iR= %1.4f ie= %1.2f ", nRef, Vcontr, iR, 
ie);
gotoxy(1,5);
cprintf("Said.R.Veloc= %1.3f Said.R.Corr= %1.3f ", iRef, Vcc);
/* %1.4f V, means, real, in 1 field, with 4 decimal digits, in "V".
%3d means, integer, in 3 fields. */
}
t.stop(); /* Ends timing */
T=t.time(); /* We consider the sampling time with initial value
T=0.003 s. If the running time of "t" greater than "T" program, must attempt 
to reduce it. If "t" is smaller we do T=t.*/
}
while (tecla!=27);
}
```
### **Acknowledgements**

The authors would like to thank UNIFEI electrical engineering undergraduate students Ricardo Nogueira Brasil and Thiago Augusto de Mello Araújo, as well as designer José Vander da Silva and English teacher João Castilhos at Speaking, Itajubá/ MG, Brazil, for assistance in the preparation of this work concerning the translation of the paper from Portuguese into English.

The authors also wish to thank everyone who directly or indirectly contributed to the success of this research study.

### **Author details**

Angelo José Junqueira Rezek1\*, Carlos Alberto Murari Pinheiro1 , Tony Youssif Teixeira Darido1 , Valberto Ferreira da Silva1 , Otávio Henrique Salvi Vicentini1 , Wanderson de Oliveira Assis2 and Rafael Di Lorenzo Corrêa2

\*Address all correspondence to: rezek@unifei.edu.br

1 UNIFEI – Federal University of Itajubá, Itajubá–MG, Brazil

2 Mauá School of Engineering, Mauá Institute of Technology, Brazil

### **References**

gotoxy(1,2);

138 Fuzzy Logic - Tool for Getting Accurate Solutions

gotoxy(1,3);

gotoxy(1,4);

gotoxy(1,5);

while (tecla!=27);

al);

ie);

}

}

}

English.

**Acknowledgements**

of this research study.

**Author details**

Tony Youssif Teixeira Darido1

Wanderson de Oliveira Assis2

cprintf("Time spent: %fs ", T);

%3d means, integer, in 3 fields. \*/

to reduce it. If "t" is smaller we do T=t.\*/

Angelo José Junqueira Rezek1\*, Carlos Alberto Murari Pinheiro1

1 UNIFEI – Federal University of Itajubá, Itajubá–MG, Brazil

2 Mauá School of Engineering, Mauá Institute of Technology, Brazil

\*Address all correspondence to: rezek@unifei.edu.br

t.stop(); /\* Ends timing \*/

cprintf("canal[%3d] = % 1.3f (pu) canal[%3d] = % 1.3f (pu) ", 0, nReal, 1, iRe-

cprintf("nRef= %1.2f Vcontr= %1.2f iR= %1.4f ie= %1.2f ", nRef, Vcontr, iR,

T=0.003 s. If the running time of "t" greater than "T" program, must attempt

cprintf("Said.R.Veloc= %1.3f Said.R.Corr= %1.3f ", iRef, Vcc); /\* %1.4f V, means, real, in 1 field, with 4 decimal digits, in "V".

T=t.time(); /\* We consider the sampling time with initial value

The authors would like to thank UNIFEI electrical engineering undergraduate students Ricardo Nogueira Brasil and Thiago Augusto de Mello Araújo, as well as designer José Vander da Silva and English teacher João Castilhos at Speaking, Itajubá/ MG, Brazil, for assistance in the preparation of this work concerning the translation of the paper from Portuguese into

The authors also wish to thank everyone who directly or indirectly contributed to the success

, Valberto Ferreira da Silva1

and Rafael Di Lorenzo Corrêa2

,

, Otávio Henrique Salvi Vicentini1

,


sertation – Federal University of Itajubá (UNIFEI), supervisor: Angelo José Junqueira Rezek, 2004.

[15] Silva,D.S; Gonçalves F., "Digital implementation of fuzzy controllers" (In Portu‐ guese), undergraduate course, end of course work (electrical engineering) - Federal University of Itajubá, supervisor: prof. Dr. Carlos Alberto Murari Pinheiro, Decem‐ ber 1999.

## **Self-Tuning Fuzzy PI Controller (STFPIC)**

### Salman Hameed

sertation – Federal University of Itajubá (UNIFEI), supervisor: Angelo José Junqueira

[15] Silva,D.S; Gonçalves F., "Digital implementation of fuzzy controllers" (In Portu‐ guese), undergraduate course, end of course work (electrical engineering) - Federal University of Itajubá, supervisor: prof. Dr. Carlos Alberto Murari Pinheiro, Decem‐

Rezek, 2004.

140 Fuzzy Logic - Tool for Getting Accurate Solutions

ber 1999.

Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/59810

### **1. Introduction**

Traditionally, control systems are designed through mathematical analysis and synthesis techniques. A wealth of control design techniques through mathematical approaches is available in the literature. Now, the first step for control system design through mathematical techniques is to obtain a proper model of the process to be controlled. However, for a highly nonlinear system like power system, it is often quite difficult to obtain an accurate mathemat‐ ical model. Because of the inaccurate model, it is often quite an arduous task to design a control system which would be effective over a wide range of operating conditions. Under these conditions, Fuzzy Logic Controllers (FLCs) can be used quite effectively for controlling the process. Fuzzy logic controllers are essentially "model free" controllers, which try to control a process, based on the experience of a skilled human operator without requiring a detailed model of the process to be controlled. In many cases, application of fuzzy logic approach makes it possible to design a control system that is more robust, cost-effective, and easier to design as compared to a controller developed based on mathematical techniques.

Motivated by the above features of FLC, an attempt has been made to design fuzzy logic TCSC (Thyristor controlled series capacitor) controllers to improve power system stability. Gener‐ ally, fuzzy PI controllers (FPIC) have been used in which the inputs to the fuzzy controllers are error (e) and charge in error (∆e), while the output of FPIC is the incremental change in the control output (∆u). The error (e) is defined as e = Pref – Pact, where Pref is the steady-state power flowing through the line (in which TCSC is installed) and Pact is the actual power flowing through that particular line following a disturbance. From these two inputs, the FPIC generates the incremental change in TCSC reactance as its output (∆u = ∆xTCSC).The main components of any FLC are fuzzification unit, fuzzy inference unit, fuzzy rule base, and defuzzification unit. The fuzzification unit maps the measured crisp inputs into the fuzzy linguistic values which are subsequently used by the fuzzy inference mechanism. It is to be noted that the actual values of the e and ∆e are not submitted directly to the fuzzification unit. The quantities e and ∆e are first converted to normalized quantities eN and ∆eN, respectively, by using scaling factors Ge

© 2015 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

and G∆e and subsequently these normalized quantities are passed to the fuzzification unit. The fuzzy inference mechanism, utilizing the fuzzy rule base, performs fuzzy logic operations on the fuzzified inputs to infer the control action. Finally, the defuzzification unit converts the inferred fuzzy control action into crisp, normalized incremental change in control output (∆uN), which, in turn, is converted into actual incremental change in control output (∆u) by using the scaling factor Gu.

These three scaling factors (Ge, G∆e, and Gu) are the main parameters for tuning the FPIC because variation of scaling factors (SFs) changes the normalized universe of discourse for input and output variables and their corresponding membership functions. These SFs play a role similar to that of the gains of a conventional controller. Therefore, they are extremely important for the controller stability and performance. Generally, there is no well-defined method for computing the appropriate values of SFs for FLC and as a result, the values of these SFs are sometimes decided by trial-and-error technique. To circumvent this trial-and-error procedure, a genetic algorithm (GA)-based technique is proposed for finding the appropriate values for Ge, G∆e, and Gu. The proposed GA-based technique is described in details in [1]. The scaling factors have been tuned such that the power system oscillations are minimized after the occurrence of a disturbance. Specifically, the aim is to minimize the error between the Pref and Pact following a disturbance. Various performance indices can be used to represent the above goal mathematically. Here, the integral of squared error (ISE) index has been used as it tends to place a greater penalty on large errors.

In many practical cases, even after a controller is established, there is a need to further tune the controller on-line. The necessity of applying further on-line tuning arises in situations where a controller must operate under uncertainty and/or when the available information is so limited that it is impossible or impractical to design in advance a controller with fixed properties. The main goal of the auto-tuning controller is to make the controller robust as far as possible when subjected to a wide range of operating conditions.

In this chapter, a simple and effective fuzzy-logic-based method for on-line tuning of TCSC FPIC is presented. The resulting controller is termed as self-tuning fuzzy PI controller (STFPIC).The effectiveness of the developed STFPIC has been validated through detailed nonlinear dynamic simulation studies on two different multimachine power systems. These study systems are: (a) two-area 4-machine system and (b) 10-machine 39-bus system. The simulation studies have been carried out on MATLAB/SIMULINK environment. A large number of fault cases involving three-phase, 5-cycle, solid short-circuit faults have been investigated on both these study systems for different loading conditions as well as different fault locations. From the simulation results, it has been observed that the proposed STFPIC for TCSC improves the system stability significantly. The detailed description of STFPIC is given in the following sections.

### **2. Self-tuning scheme**

Fuzzy logic controllers (FLCs) contain a number of sets of parameters that can be altered to modify the controller performance. These are:


and G∆e and subsequently these normalized quantities are passed to the fuzzification unit. The fuzzy inference mechanism, utilizing the fuzzy rule base, performs fuzzy logic operations on the fuzzified inputs to infer the control action. Finally, the defuzzification unit converts the inferred fuzzy control action into crisp, normalized incremental change in control output (∆uN), which, in turn, is converted into actual incremental change in control output (∆u) by

These three scaling factors (Ge, G∆e, and Gu) are the main parameters for tuning the FPIC because variation of scaling factors (SFs) changes the normalized universe of discourse for input and output variables and their corresponding membership functions. These SFs play a role similar to that of the gains of a conventional controller. Therefore, they are extremely important for the controller stability and performance. Generally, there is no well-defined method for computing the appropriate values of SFs for FLC and as a result, the values of these SFs are sometimes decided by trial-and-error technique. To circumvent this trial-and-error procedure, a genetic algorithm (GA)-based technique is proposed for finding the appropriate values for Ge, G∆e, and Gu. The proposed GA-based technique is described in details in [1]. The scaling factors have been tuned such that the power system oscillations are minimized after the occurrence of a disturbance. Specifically, the aim is to minimize the error between the Pref and Pact following a disturbance. Various performance indices can be used to represent the above goal mathematically. Here, the integral of squared error (ISE) index has been used as it

In many practical cases, even after a controller is established, there is a need to further tune the controller on-line. The necessity of applying further on-line tuning arises in situations where a controller must operate under uncertainty and/or when the available information is so limited that it is impossible or impractical to design in advance a controller with fixed properties. The main goal of the auto-tuning controller is to make the controller robust as far

In this chapter, a simple and effective fuzzy-logic-based method for on-line tuning of TCSC FPIC is presented. The resulting controller is termed as self-tuning fuzzy PI controller (STFPIC).The effectiveness of the developed STFPIC has been validated through detailed nonlinear dynamic simulation studies on two different multimachine power systems. These study systems are: (a) two-area 4-machine system and (b) 10-machine 39-bus system. The simulation studies have been carried out on MATLAB/SIMULINK environment. A large number of fault cases involving three-phase, 5-cycle, solid short-circuit faults have been investigated on both these study systems for different loading conditions as well as different fault locations. From the simulation results, it has been observed that the proposed STFPIC for TCSC improves the system stability significantly. The detailed description of STFPIC is given

Fuzzy logic controllers (FLCs) contain a number of sets of parameters that can be altered to

using the scaling factor Gu.

142 Fuzzy Logic - Tool for Getting Accurate Solutions

in the following sections.

**2. Self-tuning scheme**

modify the controller performance. These are:

tends to place a greater penalty on large errors.

as possible when subjected to a wide range of operating conditions.

A nonadaptive FLC is one in which these parameters do not change once the controller goes on-line. Adaptive FLCs have the capability of altering these parameters on-line. Further, the adaptive fuzzy controllers that modify the fuzzy set definitions or the scaling factors are called self-tuning or auto-tuning fuzzy logic controllers (FLCs) [2, 3]. Alteration of these parameters essentially fine-tunes an already working controller. On the other hand, adaptive FLCs that alter the rules are called self-organizing controllers [3]. These two types of fuzzy logic con‐ trollers have been developed [4-11] and implemented for various practical processes. Of the various tunable parameters, SFs have the highest priority due to their global effect on the control performance because changing the SFs changes the normalized universe of discourse, the domains, and the membership functions of input/output variables of FLC [3].

### **2.1. Self-tuning fuzzy PI controller (STFPIC)**

It has been experimentally observed that a conventional FLC with constant scaling factors and a limited number of IF–THEN rules may have limited performance for a highly nonlinear plant [12]. As a result, there has been significant research on tuning of FLCs where either the input or output scaling factors or the definitions of the membership functions (MFs) and sometimes the control rules are tuned to achieve the desired control objectives [5, 8, 10]. Here, only the output scaling factor (SF) is tuned due to its strong influence on the performance and stability of the system. In this scheme, the output SF of the FLC is adjusted on-line according to the current states of the controlled processes. Specifically, the tuning of the output SF is based on the value of instantaneous error and change in error (e and Δe). The block diagram of the Self-tuning Fuzzy PI type Control‐ ler (STFPIC) is shown in Fig. 1 [13, 14]. From this figure, it is observed that by the use of a self-tuning mechanism, the controller's output SF gets modified, as shown by the dotted boundary. Thus, the output scaling factor gets modified at each sampling time and is updated by the gain updating factor α. This process depends on the trend followed by the controlled process output and the value of α is obtained using fuzzy rules [13, 19].

In contrast to FPIC (which has only one fuzzy logic block), there are two fuzzy logic blocks in STFPIC as shown in Fig. The top fuzzy logic block in Fig. 1 computes the main control output (Δu) of the FLC. The membership functions (MFs) for e, Δe, and Δu corresponding to this fuzzy logic block are shown in Fig. 2. The rule base for computing Δu is shown in Table The second fuzzy logic block (shown in dotted boundary) calculates the gain updating factor α at each sampling instant. For this second fuzzy block also, the MFs for e and Δe are same as shown in Fig. 2. The membership functions used for the factor α are defined in the domain [1] and are shown in Fig. 3. As each of the two inputs has 7 fuzzified variables, the rule base has a total 49 rules for calculating α as shown in Table 2. This rule base improves the control performance under large disturbances such as sudden loss of a generating unit or a large load, three-phase short circuit on the transmission lines, etc. [13, 20]. For example, immediately after a large disturbance, e may be small but Δe will be sufficiently large (they will be of same sign) and, for this case, α should be large to increase the gain. Therefore, under these circumstances, the appropriate rules are "IF e is PS and Δe is PM, THEN α is B" or "IF e is NS and Δe is NM, THEN α is B." On the other hand, for steady-state conditions (i.e., e ≈ 0 and Δe ≈ 0), controller gain should be very small (e.g., IF e is ZE and Δe is ZE, THEN α is ZE) to avoid chattering problem around the set point. Further justification for using the rule base in Table 2 can be found in [13]. disturbance, e may be small but ∆e will be sufficiently large (they will be of same sign) and, for this case, α should be large to increase the gain. Therefore, under these circumstances, the appropriate rules are "IF e is PS and ∆e is PM, THEN α is B" or "IF e is NS and ∆e is NM, THEN α is B." On the other hand, for steady-state conditions (i.e., e ≈ 0 and ∆e ≈ 0), controller gain should be very small (e.g., IF e is ZE and ∆e is ZE, THEN α is ZE) to avoid chattering problem

around the set point. Further justification for using the rule base in Table 1.2 can be found in [13].

Figure 1. Block diagram of the STFPIC **Figure 1.** Block diagram of the STFPIC

Table 1. Rule Base for ∆u

The following steps have been used for tuning the STFPIC [13]. The following steps have been used for tuning the STFPIC [13].

Step 1: Tune the SFs of the STFPIC without the gain tuning mechanism and assuming α = 1 (i.e., conventional FLC) for a given process to achieve a reasonably good control performance. For the tuning of the conventional FLC, GA [15, 20] has been used. At the end of this step, a good controller without self-tuning feature is obtained and this controller becomes the starting point (input) for the self-tuning controller in Step 2. Step 2: Set the output SF (Gu) of the self-tuning FLC K times greater than that obtained in Step1, keeping the values of *Step 1:* Tune the SFs of the STFPIC without the gain tuning mechanism and assuming α = 1 (i.e., conventional FLC) for a given process to achieve a reasonably good control performance. For the tuning of the conventional FLC, GA [15, 20] has been used. At the end of this step, a good controller without self-tuning feature is obtained and this controller becomes the starting point (input) for the self-tuning controller in Step 2.

<sup>G</sup>e and G∆e same as those of the conventional FLC. In this step, α ≠ 1, and is obtained from the rule base in Table 1.2. This factor K for the STFPIC (to enhance the value of Gu) is found empirically with an objective to maintain the same rise time as that of the conventional FLC [13]. *Step 2:* Set the output SF (Gu) of the self-tuning FLC K times greater than that obtained in Step1, keeping the values of Ge and GΔe same as those of the conventional FLC. In this step, *α* ≠1, and is obtained from the rule base in Table 2. This factor K for the STFPIC (to enhance the value of Gu) is found empirically with an objective to maintain the same rise time as that of the conventional FLC [13].

> ∆e/e NB NM NS ZE PS PM PB NB NB NB NB NM NS NS ZE NM NB NM NM NM NS ZE PS NS NB NM NS NS ZE PS PM ZE NB NM NS ZE PS PM PB PS NM NS ZE PS PS PM PB PM NS ZE PS PM PM PM PB PB ZE PS PS PM PB PB PB

Figure 2. MFs for e, ∆e, and ∆u. N: Negative, P: Positive, ZE: Zero, B: Big, M: Medium, S: Small

1

Fig. 1.2: MFs for e, Δe and Δu. N: Negative, P: Positive, ZE: Zero, B: Big, M: Medium,

**PS** NM NS ZE PS PS PM PB **PM** NS ZE PS PM PM PM PB

S: Small **Figure 2.** MFs for e, Δe, and Δu. N: Negative, P: Positive, ZE: Zero, B: Big, M: Medium, S: Small **Δe/e NB NM NS ZE PS PM PB** 

<sup>1</sup> NB NM NS ZE PS PM PB


**NB** NB NB NB NM NS NS ZE

**Table 1.** Rule Base for Δu

disturbance, e may be small but Δe will be sufficiently large (they will be of same sign) and, for this case, α should be large to increase the gain. Therefore, under these circumstances, the appropriate rules are "IF e is PS and Δe is PM, THEN α is B" or "IF e is NS and Δe is NM, THEN α is B." On the other hand, for steady-state conditions (i.e., e ≈ 0 and Δe ≈ 0), controller gain should be very small (e.g., IF e is ZE and Δe is ZE, THEN α is ZE) to avoid chattering problem around the set point. Further justification for using the rule base in Table 2 can be

around the set point. Further justification for using the rule base in Table 1.2 can be found in [13].

Inference Mechanism

<sup>+</sup> <sup>G</sup><sup>e</sup>

<sup>N</sup> <sup>e</sup> <sup>u</sup> .G <sup>α</sup>

<sup>+</sup> <sup>+</sup>

Inference Mechanism

Rule-base 2

GAIN TUNING MECHANISM

*Step 1:* Tune the SFs of the STFPIC without the gain tuning mechanism and assuming α = 1 (i.e., conventional FLC) for a given process to achieve a reasonably good control performance. For the tuning of the conventional FLC, GA [15, 20] has been used. At the end of this step, a good controller without self-tuning feature is obtained and this controller becomes the starting

*Step 2:* Set the output SF (Gu) of the self-tuning FLC K times greater than that obtained in Step1, keeping the values of Ge and GΔe same as those of the conventional FLC. In this step, *α* ≠1, and is obtained from the rule base in Table 2. This factor K for the STFPIC (to enhance the value of Gu) is found empirically with an objective to maintain the same rise time as that of the

Process

Step 1: Tune the SFs of the STFPIC without the gain tuning mechanism and assuming α = 1 (i.e., conventional FLC) for a given process to achieve a reasonably good control performance. For the tuning of the conventional FLC, GA [15, 20] has been used. At the end of this step, a good controller without self-tuning feature is obtained and this controller

Step 2: Set the output SF (Gu) of the self-tuning FLC K times greater than that obtained in Step1, keeping the values of <sup>G</sup>e and G∆e same as those of the conventional FLC. In this step, α ≠ 1, and is obtained from the rule base in Table 1.2. This factor K for the STFPIC (to enhance the value of Gu) is found empirically with an objective to maintain the same

> ∆e/e NB NM NS ZE PS PM PB NB NB NB NB NM NS NS ZE NM NB NM NM NM NS ZE PS NS NB NM NS NS ZE PS PM ZE NB NM NS ZE PS PM PB PS NM NS ZE PS PS PM PB PM NS ZE PS PM PM PM PB PB ZE PS PS PM PB PB PB

Rule-base 1

Fuzzification

Fuzzification

disturbance, e may be small but ∆e will be sufficiently large (they will be of same sign) and, for this case, α should be large to increase the gain. Therefore, under these circumstances, the appropriate rules are "IF e is PS and ∆e is PM, THEN α is B" or "IF e is NS and ∆e is NM, THEN α is B." On the other hand, for steady-state conditions (i.e., e ≈ 0 and ∆e ≈ 0), controller gain should be very small (e.g., IF e is ZE and ∆e is ZE, THEN α is ZE) to avoid chattering problem

> Defuzzification

> > <sup>1</sup> Z<sup>−</sup>

<sup>N</sup> <sup>∆</sup><sup>u</sup> <sup>∆</sup><sup>u</sup> <sup>u</sup>

Defuzzification

α

found in [13].

y

y

Figure 1. Block diagram of the STFPIC

**Figure 1.** Block diagram of the STFPIC

rise time as that of the conventional FLC [13].

point (input) for the self-tuning controller in Step 2.

Table 1. Rule Base for ∆u

conventional FLC [13].

+ − <sup>1</sup> <sup>Z</sup><sup>−</sup> <sup>∆</sup><sup>e</sup>

−

144 Fuzzy Logic - Tool for Getting Accurate Solutions

G<sup>∆</sup><sup>e</sup>

<sup>N</sup> ∆e

The following steps have been used for tuning the STFPIC [13].

The following steps have been used for tuning the STFPIC [13].

becomes the starting point (input) for the self-tuning controller in Step 2.

Figure 2. MFs for e, ∆e, and ∆u. N: Negative, P: Positive, ZE: Zero, B: Big, M: Medium, S: Small

R e

Fig. 1.3: MFs for gain updating factor (α). ZE: Zero, V: Very, B: Big, M: Medium, S: Small

6

6

0.17 0.83

Fig. 1.3: MFs for gain updating factor (α). ZE: Zero, V: Very, B: Big, M: Medium, S: Small

**Figure 3.** MFs for gain updating factor (α). ZE: Zero, V: Very, B: Big, M: Medium, S: Small

0 0.5


**Table 2.** Rule Base for α

### **2.2. Scaling factor's tuning using genetic algorithm (GA)**

Here, the power system oscillations are minimized by tuning of the scaling factors using GA. The aim is to minimize the error between the steady-state power (*Pref* ) flowing through the line in which the TCSC is installed and the actual power flowing through that line (*Pactual*) after a disturbance [12, 19]. Several performance indices can be used to represent the above goal mathematically. The integral of the squared error (ISE) [12] as shown in eqn. (1) has been selected as it tends to place a greater penalty on large errors. This goal can be formulated as the minimization of the objective function F where,

$$F = \int\_0^{t\_{\rm sat}} e^{2}(t)dt\tag{1}$$

In eqn. (1), *e*(*t*)= *Pref* −*Pactual* is the error in power flow in the line following a disturbance and *tsim* is the total time period of simulation. As the objective function of eqn. (1) is nonconvex in nature, GA has been used to minimize F. A basic introduction to GA is given in Section 2.

### *2.2.1. Genetic algorithm (GA)*

Various conventional optimization techniques are available in the literature, which can be used to optimize the controller parameters effectively. The conventional optimization approach, based on gradient descent technique, sometimes gets stuck at local minima giving suboptimal controllers.

Genetic Algorithms (GAs) offer promising potential for optimizing controller parameters and it uses the concept of Darwin's theory of evolution. As per this theory, the existence of all living things is based on the rule of "survival of the fittest" [1]. GA makes use of three fundamental operators, namely, reproduction, crossover, and mutation, which are explained later in this section. The basic principle of GA is to initially form different possible solutions to a problem and then test them for their performance. By using the rule of "survival of the fittest," only a fraction of the better solutions are selected, eliminating the remaining ones. Genetic operators (reproduction, crossover, and mutation) are then applied to the selected solutions resulting in a new generation of possible solutions (which are expected to perform better than the previous generation). The above steps are repeated until a specific termination criterion is met (such as maximum number of generations, negligible variation in performance or fitness value, etc.). Search space of GA does not confine to a narrow expected region (as in the case of gradient descent), but rather includes a broad spectrum of possible solutions. It is capable of obtaining the global solution of a wide variety of functions such as differentiable or nondifferentiable, linear or nonlinear, continuous or discrete, and analytical or procedural [1]. GA tries to perform an intelligent search for a solution from a nearly infinite number of possible solutions.

### *2.2.2. Basic tuning procedure*

**Δe/e NB NM NS ZE PS PM PB NB** VB VB VB B SB S ZE **NM** VB VB B B MB S VS **NS** VB MB B VB VS S VS **ZE** S SB MB ZE MB SB S **PS** VS S VS VB B MB VB **PM** VS S MB B B VB VB **PB** ZE S SB B VB VB VB

Here, the power system oscillations are minimized by tuning of the scaling factors using GA. The aim is to minimize the error between the steady-state power (*Pref* ) flowing through the line in which the TCSC is installed and the actual power flowing through that line (*Pactual*) after a disturbance [12, 19]. Several performance indices can be used to represent the above goal mathematically. The integral of the squared error (ISE) [12] as shown in eqn. (1) has been selected as it tends to place a greater penalty on large errors. This goal can be formulated as

2

( )

In eqn. (1), *e*(*t*)= *Pref* −*Pactual* is the error in power flow in the line following a disturbance and *tsim* is the total time period of simulation. As the objective function of eqn. (1) is nonconvex in nature, GA has been used to minimize F. A basic introduction to GA is given in Section 2.

Various conventional optimization techniques are available in the literature, which can be used to optimize the controller parameters effectively. The conventional optimization approach, based on gradient descent technique, sometimes gets stuck at local minima giving suboptimal

Genetic Algorithms (GAs) offer promising potential for optimizing controller parameters and it uses the concept of Darwin's theory of evolution. As per this theory, the existence of all living things is based on the rule of "survival of the fittest" [1]. GA makes use of three fundamental operators, namely, reproduction, crossover, and mutation, which are explained later in this section. The basic principle of GA is to initially form different possible solutions to a problem and then test them for their performance. By using the rule of "survival of the fittest," only a fraction of the better solutions are selected, eliminating the remaining ones. Genetic operators (reproduction, crossover, and mutation) are then applied to the selected solutions resulting in

*F e t dt* <sup>=</sup> ò (1)

0

*sim t*

**Table 2.** Rule Base for α

146 Fuzzy Logic - Tool for Getting Accurate Solutions

*2.2.1. Genetic algorithm (GA)*

controllers.

**2.2. Scaling factor's tuning using genetic algorithm (GA)**

the minimization of the objective function F where,

The overall flowchart for optimization using GA is shown in Fig. 4. Initially, a number of populations (N) have been generated for the scaling factors. Each of the populations consists of the binary strings corresponding to the scaling factors Ge, GΔe, and Gu. These strings are created in a random fashion with the constrain that the values of Ge, GΔe, and Gu should lie within their specified ranges. The ranges chosen for each of these scaling factors are shown in Table 3. For each of these N sets of values of Ge, GΔe, and Gu, time domain nonlinear simulation studies have been carried out for evaluating the objective function F of eqn. (1). For this, *tsim* has been taken as 80 s. Based on the values of the objective function, out of these N possible solutions, the good solutions are retained and the others are eliminated (following the principle of survival of the fittest) [1, 15, 19]. The selected solutions undergo the processes of reproduc‐ tion, crossover, and mutation to create a new generation of possible solutions (which are expected to perform better than the previous generation). This process of production of a new generation and its evaluation is performed repetitively. The algorithm stops when a predefined maximum number of generations is achieved [1, 15, 19]. The parameters used for GA are shown in Table 4. 2.2.2. Basic tuning procedure The overall flowchart for optimization using GA is shown in Fig. 1.4. Initially, a number of populations (N) have been generated for the scaling factors. Each of the populations consists of the binary strings corresponding to the scaling factors Ge, G∆e, and Gu. These strings are created in a random fashion with the constrain that the values of Ge, G∆e, and Gu should lie within their specified ranges. The ranges chosen for each of these scaling factors are shown in Table 1.3. For each of these N sets of values of Ge, G∆e, and Gu, time domain nonlinear simulation studies have been carried out for evaluating the objective function F of eqn. (1). For this, tsim has been taken as 80 s. Based on the values of the objective function, out of these N possible solutions, the good solutions are retained and the others are eliminated (following the principle of survival of the fittest) [1, 15, 19]. The selected solutions undergo the processes of reproduction, crossover, and mutation to create a new generation of possible solutions (which are expected to perform better than the previous generation). This process of production of a new generation and its evaluation is performed repetitively. The algorithm stops when a predefined maximum number of generations is achieved [1, 15, 19]. The

Table 3. Ranges for the different scaling factors

Table 4. Parameters used in genetic algorithm

3. Case studies

Section 3.1.1.

Parameters Ge G∆e G<sup>u</sup> Minimum range 0 0 0 Maximum range 0.5 1 1

Parameter Value/Type Maximum generations 50 Population size 25 Mutation rate 0.1 Crossover operator Scattered

The efficacy of the projected STFPIC has been validated on two different multimachine power systems: (a) two-area 4 machine system [16] and (b) 10-machine 39-bus system [16, 19]. The details of these two systems are presented in

parameters used for GA are shown in Table 1.4.

Figure 4. Flowchart of the GA optimization algorithm **Figure 4.** Flowchart of the GA optimization algorithm


**Table 3.** Ranges for the different scaling factors


**Table 4.** Parameters used in genetic algorithm

### **3. Case studies**

The efficacy of the projected STFPIC has been validated on two different multimachine power systems: (a) two-area 4-machine system [16] and (b) 10-machine 39-bus system [16, 19]. The details of these two systems are presented in Section 3.

#### **3.1. Study systems** 3.1. Study systems

The schematic diagram of the two-area 4-machine system is shown in Fig. 5. In this system, machines 1, 2 and 3, 4 form two different coherent groups. The three tie lines connect these two coherent areas. As shown in Fig. 5, a TCSC has been installed in the middle of one of these tie lines [17, 19]. The schematic diagram of the two-area 4-machine system is shown in Fig. 1.5. In this system, machines 1, 2 and 3, 4 form two different coherent groups. The three tie lines connect these two coherent areas. As shown in Fig. 1.5, a TCSC has been installed in the middle of one of these tie lines [17, 19]. The one line diagram of the second study system of this work, i.e., the 10-machine 39-bus system is shown in Fig. 1.6.

has been assumed to be installed in the middle of the tie line connecting buses #39 and #36.

In this diagram, the generators are identified by their bus numbers to which they are connected. In this system, a TCSC

Figure 5. TCSC in a two-area 4-generator system **Figure 5.** TCSC in a two-area 4-generator system

12 11

2

19

18

17 15

3.2. Simulation results

1

14

13

16

31

3

Figure 6. Schematic diagram of 10-machine, 39-bus system

20

33

32

10 8 <sup>28</sup> <sup>26</sup> 29 The one line diagram of the second study system of this work, i.e., the 10-machine 39-bus system is shown in Fig. 6. In this diagram, the generators are identified by their bus numbers

24

27

36

39

34 35

30

25

<sup>38</sup> <sup>37</sup>

6

23

The effectiveness of the self-tuning fuzzy PI controller (STFPIC) has been studied through detailed nonlinear time domain simulation studies for a three-phase, 5-cycle, solid short-circuit faults on both the test systems shown above. The short-circuit faults have been assumed to occur at t = 5 s. The simulation studies have been carried out in the MATLAB/SIMULINK environment [18]. For illustrating the efficacy of the fuzzy controllers developed in this work, results pertaining to two different situations are presented. These situations are: (a) study system with a TCSC

2221

4 5 7

9

11

12

4

3

G3

The schematic diagram of the two-area 4-machine system is shown in Fig. 1.5. In this system, machines 1, 2 and 3, 4 form two different coherent groups. The three tie lines connect these two coherent areas. As shown in Fig. 1.5, a TCSC

The one line diagram of the second study system of this work, i.e., the 10-machine 39-bus system is shown in Fig. 1.6. In this diagram, the generators are identified by their bus numbers to which they are connected. In this system, a TCSC

8

to which they are connected. In this system, a TCSC has been assumed to be installed in the middle of the tie line connecting buses #39 and #36. G2 G4

has been assumed to be installed in the middle of the tie line connecting buses #39 and #36.

<sup>5</sup> <sup>6</sup> <sup>9</sup> <sup>10</sup> <sup>8</sup> <sup>7</sup>

<sup>1</sup> <sup>2</sup>

4

TCSC

3

9 7

Load A Load B

11

has been installed in the middle of one of these tie lines [17, 19].

5

6

3.2. Simulation results **Figure 6.** Schematic diagram of 10-machine, 39-bus system

Figure 6. Schematic diagram of 10-machine, 39-bus system

3.1. Study systems

1

G1

2

10

Figure 5. TCSC in a two-area 4-generator system

#### The effectiveness of the self-tuning fuzzy PI controller (STFPIC) has been studied through detailed nonlinear time **3.2. Simulation results**

**Parameters Ge GΔe Gu** Minimum range 0 0 0 Maximum range 0.5 1 1

**Parameter Value/Type**

The efficacy of the projected STFPIC has been validated on two different multimachine power systems: (a) two-area 4-machine system [16] and (b) 10-machine 39-bus system [16, 19]. The

The schematic diagram of the two-area 4-machine system is shown in Fig. 5. In this system, machines 1, 2 and 3, 4 form two different coherent groups. The three tie lines connect these two coherent areas. As shown in Fig. 5, a TCSC has been installed in the middle of one of these

has been assumed to be installed in the middle of the tie line connecting buses #39 and #36.

<sup>5</sup> <sup>6</sup> <sup>9</sup> <sup>10</sup> <sup>8</sup> <sup>7</sup>

<sup>1</sup> <sup>2</sup> 3 4

9 7

11

Area 1 Area 2

<sup>28</sup> <sup>26</sup>

34 35

30

27

The one line diagram of the second study system of this work, i.e., the 10-machine 39-bus system is shown in Fig. 6. In this diagram, the generators are identified by their bus numbers

36

39

24

Load A Load B

has been installed in the middle of one of these tie lines [17, 19].

5 6

The schematic diagram of the two-area 4-machine system is shown in Fig. 1.5. In this system, machines 1, 2 and 3, 4 form two different coherent groups. The three tie lines connect these two coherent areas. As shown in Fig. 1.5, a TCSC

The one line diagram of the second study system of this work, i.e., the 10-machine 39-bus system is shown in Fig. 1.6. In this diagram, the generators are identified by their bus numbers to which they are connected. In this system, a TCSC

8

<sup>12</sup> TCSC

6

23

The effectiveness of the self-tuning fuzzy PI controller (STFPIC) has been studied through detailed nonlinear time domain simulation studies for a three-phase, 5-cycle, solid short-circuit faults on both the test systems shown above. The short-circuit faults have been assumed to occur at t = 5 s. The simulation studies have been carried out in the MATLAB/SIMULINK environment [18]. For illustrating the efficacy of the fuzzy controllers developed in this work, results pertaining to two different situations are presented. These situations are: (a) study system with a TCSC

2221

4 5 7

29

9

3

4

G4

11

G3

Maximum generations 50 Population size 25 Mutation rate 0.1 Crossover operator Scattered

details of these two systems are presented in Section 3.

3.1. Study systems

1

G1

10

**Figure 5.** TCSC in a two-area 4-generator system

12 11

2

19

18

17 15

3.2. Simulation results

1

14

13

2

G2

Figure 5. TCSC in a two-area 4-generator system

8

16

31

3

Figure 6. Schematic diagram of 10-machine, 39-bus system

20

33

32

25

<sup>38</sup> <sup>37</sup>

10

**Table 3.** Ranges for the different scaling factors

148 Fuzzy Logic - Tool for Getting Accurate Solutions

**Table 4.** Parameters used in genetic algorithm

**3. Case studies**

**3.1. Study systems**

tie lines [17, 19].

domain simulation studies for a three-phase, 5-cycle, solid short-circuit faults on both the test systems shown above. The short-circuit faults have been assumed to occur at t = 5 s. The simulation studies have been carried out in the MATLAB/SIMULINK environment [18]. For illustrating the efficacy of the fuzzy controllers developed in this work, results pertaining to two different situations are presented. These situations are: (a) study system with a TCSC The effectiveness of the self-tuning fuzzy PI controller (STFPIC) has been studied through detailed nonlinear time domain simulation studies for a three-phase, 5-cycle, solid short-circuit faults on both the test systems shown above. The short-circuit faults have been assumed to occur at t = 5 s. The simulation studies have been carried out in the MATLAB/SIMULINK environment [18]. For illustrating the efficacy of the fuzzy controllers developed in this work, results pertaining to two different situations are presented. These situations are: (a) study system with a TCSC controlled by FPIC and (b) study system with a TCSC controlled by STFPIC. For following figures, the rotor angles of the machines have been measured with respect to the Centre of Inertia (COI) reference [16].

### *3.2.1. Two-area 4-machine system*

For this system, initially the short-circuit fault has been assumed to occur at bus 9. The variations of the rotor angles of the two machines (machine 1 and machine 4) and active power flow in line 11–10 (P11-10) for the base case loading condition (the loading condition as described in [16, 21]) are displayed in Figs. 7 and 8, and 9(a), corresponding to scenarios (a) and (b), respectively. In Figs. 7– 9, the dotted lines show the variation of rotor angle with TCSC FPIC, whereas the variation of rotor angle with TCSC STFPIC is depicted with solid lines. For implementing STFPIC, K has been set equal to 3. From Figs. 7 to 8, and 9(a), it is observed that there is perceptible improvement in the performance of the system as the oscillations are damped earlier by the STFPIC proposed for TCSC. The variations of the TCSC reactance (XTCSC) are shown in Fig. 9(b) for situations (a) and (b).

To investigate the performance of the TCSC STFPIC controller at enhanced loading condition, simulation studies were carried out by increasing the system loads by 10% from the base case loading condition. The results are shown in Figs. 10 and 11, and 12, corresponding to scenarios (a) and (b), respectively. From Figs. 10 to 11 and 12(a), it is evident that at 10% higher loading, the TCSC STFPIC improves the system performance. Figure 12(b) shows the variation of the TCSC reactance for this case with TCSC FPIC and TCSC STFPIC. It can be observed from Figs. 9(b) and 12(b) that STFPIC has been able to improve the damping with smaller variation in XTCSC as compared to FPIC for the base case and 110% loading conditions respectively with fault at bus 9.The variations of α for fault at bus 9 are shown in Fig. 13, corresponding to both base case and 10% increased loading conditions. From these figures it is observed that for different loading conditions, the TCSC STFPIC always improves the system performance, showing the robustness of the controller.

The performance of the TCSC STFPIC has also been studied with faults at different locations for both base case and 10% increased loading conditions. The simulation results for faults at bus 8 are shown in Figs. 14– 19 with the variations of α depicted in Fig. 20. Similarly, the results corresponding to fault at bus 5 are shown in Figs. 21– 26 with the variations of α displayed in Fig. 27. From these figures, it is observed that irrespective of the fault location, the TCSC STFPIC always improves the system performance.

### *3.2.2. 10-machine 39-bus system*

In this system, initially the short-circuit fault has been assumed to occur at bus 24. From the fault simulation studies carried out at the base case loading condition (the loading condition as described in [16, 19]), it has been observed that the proposed TCSC STFPIC improved the system performance. Subsequently, a great number of fault studies have been carried out at several increased system loading situations to inspect the effectiveness of the developed STFPIC for improving the performance of the system. After all these studies, it has been found that the TCSC STFPIC helps to further increase the damping for the system. Only a few representative results are presented below to illustrate the effectiveness of the developed STFPIC in further enhancing the performance of the system under study.

controlled by FPIC and (b) study system with a TCSC controlled by STFPIC. For following figures, the rotor angles of

For this system, initially the short-circuit fault has been assumed to occur at bus 9. The variations of the rotor angles of the two machines (machine 1 and machine 4) and active power flow in line 11–10 (P11-10) for the base case loading condition (the loading condition as described in [16, 21]) are displayed in Figs. 1.7 and 1.8, and 1.9(a), corresponding to scenarios (a) and (b), respectively. In Figs. 1.7–1.9, the dotted lines show the variation of rotor angle with TCSC FPIC, whereas the variation of rotor angle with TCSC STFPIC is depicted with solid lines. For implementing STFPIC, K has been set equal to 3. From Figs. 1.7 to 1.8, and 1.9(a), it is observed that there is perceptible improvement in the performance of the system as the oscillations are damped earlier by the STFPIC proposed for TCSC. The variations of

To investigate the performance of the TCSC STFPIC controller at enhanced loading condition, simulation studies were carried out by increasing the system loads by 10% from the base case loading condition. The results are shown in Figs. 1.10 and 1.11, and 1.12, corresponding to scenarios (a) and (b), respectively. From Figs. 1.10 to 1.11 and 1.12(a), it is evident that at 10% higher loading, the TCSC STFPIC improves the system performance. Figure 1.12(b) shows the variation of the TCSC reactance for this case with TCSC FPIC and TCSC STFPIC. It can be observed from Figs. 1.9(b) and 1.12(b) that STFPIC has been able to improve the damping with smaller variation in XTCSC as compared to FPIC for the base case and 110% loading conditions respectively with fault at bus 9.The variations of α for fault at bus 9 are shown in Fig. 1.13, corresponding to both base case and 10% increased loading conditions. From these figures it is observed that for different loading conditions, the TCSC STFPIC always improves the system performance, showing

The performance of the TCSC STFPIC has also been studied with faults at different locations for both base case and

the machines have been measured with respect to the Centre of Inertia (COI) reference [16].

the TCSC reactance (XTCSC) are shown in Fig. 1.9(b) for situations (a) and (b).

3.2.1. Two-area 4-machine system

the robustness of the controller.

the TCSC STFPIC always improves the system performance.

Figure 7. Rotor angle of generator 1 with STFPIC for base case with fault at bus 9 **Figure 7.** Rotor angle of generator 1 with STFPIC for base case with fault at bus 9

*3.2.1. Two-area 4-machine system*

150 Fuzzy Logic - Tool for Getting Accurate Solutions

(XTCSC) are shown in Fig. 9(b) for situations (a) and (b).

showing the robustness of the controller.

*3.2.2. 10-machine 39-bus system*

STFPIC always improves the system performance.

For this system, initially the short-circuit fault has been assumed to occur at bus 9. The variations of the rotor angles of the two machines (machine 1 and machine 4) and active power flow in line 11–10 (P11-10) for the base case loading condition (the loading condition as described in [16, 21]) are displayed in Figs. 7 and 8, and 9(a), corresponding to scenarios (a) and (b), respectively. In Figs. 7– 9, the dotted lines show the variation of rotor angle with TCSC FPIC, whereas the variation of rotor angle with TCSC STFPIC is depicted with solid lines. For implementing STFPIC, K has been set equal to 3. From Figs. 7 to 8, and 9(a), it is observed that there is perceptible improvement in the performance of the system as the oscillations are damped earlier by the STFPIC proposed for TCSC. The variations of the TCSC reactance

To investigate the performance of the TCSC STFPIC controller at enhanced loading condition, simulation studies were carried out by increasing the system loads by 10% from the base case loading condition. The results are shown in Figs. 10 and 11, and 12, corresponding to scenarios (a) and (b), respectively. From Figs. 10 to 11 and 12(a), it is evident that at 10% higher loading, the TCSC STFPIC improves the system performance. Figure 12(b) shows the variation of the TCSC reactance for this case with TCSC FPIC and TCSC STFPIC. It can be observed from Figs. 9(b) and 12(b) that STFPIC has been able to improve the damping with smaller variation in XTCSC as compared to FPIC for the base case and 110% loading conditions respectively with fault at bus 9.The variations of α for fault at bus 9 are shown in Fig. 13, corresponding to both base case and 10% increased loading conditions. From these figures it is observed that for different loading conditions, the TCSC STFPIC always improves the system performance,

The performance of the TCSC STFPIC has also been studied with faults at different locations for both base case and 10% increased loading conditions. The simulation results for faults at bus 8 are shown in Figs. 14– 19 with the variations of α depicted in Fig. 20. Similarly, the results corresponding to fault at bus 5 are shown in Figs. 21– 26 with the variations of α displayed in Fig. 27. From these figures, it is observed that irrespective of the fault location, the TCSC

In this system, initially the short-circuit fault has been assumed to occur at bus 24. From the fault simulation studies carried out at the base case loading condition (the loading condition as described in [16, 19]), it has been observed that the proposed TCSC STFPIC improved the system performance. Subsequently, a great number of fault studies have been carried out at several increased system loading situations to inspect the effectiveness of the developed STFPIC for improving the performance of the system. After all these studies, it has been found that the TCSC STFPIC helps to further increase the damping for the system. Only a few representative results are presented below to illustrate the effectiveness of the developed

STFPIC in further enhancing the performance of the system under study.

0 5 10 15 20 25 30 35 40

(b) XTCSC

0 5 10 15 20 25 30 35 40

Figure 9. Active power flow in line 11-10 and TCSC capacitive reactance with STFPIC for base case with fault at bus 9

Time (sec.)

(a) Power flow in line 11-10

with TCSC STFPIC with TCSC FPIC

with TCSC FPIC with TCSC STFPIC

Figure 8. Rotor angle of generator 4 with STFPIC for base case with fault at bus 9 **Figure 8.** Rotor angle of generator 4 with STFPIC for base case with fault at bus 9



p.u.

0

0.5

p.u.

1




radian



Time (sec.)

Figure 8. Rotor angle of generator 4 with STFPIC for base case with fault at bus 9

δ4

with TCSC FPIC with TCSC STFPIC

Figure 9. Active power flow in line 11-10 and TCSC capacitive reactance with STFPIC for base case with fault at bus 9 **Figure 9.** Active power flow in line 11-10 and TCSC capacitive reactance with STFPIC for base case with fault at bus 9

0 5 10 15 20 25 30 35 40 45 50

Time (sec.)

Figure 11. Rotor angle of generator 4 with STFPIC for 110% loading with fault at bus 9

δ4

with TCSC FPIC with TCSC STFPIC

Figure 10. Rotor angle of generator 1 with STFPIC for 110% loading with fault at bus 9 **Figure 10.** Rotor angle of generator 1 with STFPIC for 110% loading with fault at bus 9





radian



Time (sec.)

Figure 10. Rotor angle of generator 1 with STFPIC for 110% loading with fault at bus 9

δ1

with TCSC FPIC with TCSC STFPIC

Figure 11. Rotor angle of generator 4 with STFPIC for 110% loading with fault at bus 9 **Figure 11.** Rotor angle of generator 4 with STFPIC for 110% loading with fault at bus 9

0

0.05

0.1

0.15

radian

0.2

0.25

0.3

0.35

0 5 10 15 20 25 30 35 40

δ4

with TCSC FPIC with TCSC STFPIC

with TCSC STFPIC with TCSC FPIC

with TCSC FPIC with TCSC STFPIC

with TCSC FPIC with TCSC STFPIC

> with TCSC FPIC with TCSC STFPIC

Time (sec.)

(a) Power flow in line 11-10

0 5 10 15 20 25 30 35 40

(b) XTCSC

0 5 10 15 20 25 30 35 40

Time (sec.)

Figure 9. Active power flow in line 11-10 and TCSC capacitive reactance with STFPIC for base case with fault at bus 9 **Figure 9.** Active power flow in line 11-10 and TCSC capacitive reactance with STFPIC for base case with fault at bus 9

δ1

0 10 20 30 40 50

δ4

0 5 10 15 20 25 30 35 40 45 50

Time (sec.)

Figure 11. Rotor angle of generator 4 with STFPIC for 110% loading with fault at bus 9

Time (sec.)

Figure 10. Rotor angle of generator 1 with STFPIC for 110% loading with fault at bus 9

**Figure 10.** Rotor angle of generator 1 with STFPIC for 110% loading with fault at bus 9

Figure 8. Rotor angle of generator 4 with STFPIC for base case with fault at bus 9


152 Fuzzy Logic - Tool for Getting Accurate Solutions



0





radian



0.05

0.1

0.15

radian

0.2

0.25

0.3

0.35

p.u.

p.u.

0 0.5 1 1.5



radian



Figure 12. Active power flow in line 11-10 and TCSC capacitive reactance with STFPIC for 110% loading with fault at bus 9 (a) Base case **Figure 12.** Active power flow in line 11-10 and TCSC capacitive reactance with STFPIC for 110% loading with fault at bus 9

0 10 20 30 40 50 60

(b) 110% loading

0 10 20 30 40 50 60

Time (sec.)

Figure 13. Variation of α for base case and 110% loading with fault at bus 9

0

1

0

0.5

α

0.5

α

1

p.u.



p.u.

0 5 10 15 20 25 30 35 40 45 50

(b) XTCSC

with TCSC FPIC with TCSC STFPIC

Figure 12. Active power flow in line 11-10 and TCSC capacitive reactance with STFPIC for 110% loading with fault at bus 9

with TCSC STFPIC with TCSC FPIC

Time (sec.)

(a) Power flow in line 11-10

Figure 13. Variation of α for base case and 110% loading with fault at bus 9 **Figure 13.** Variation of α for base case and 110% loading with fault at bus 9

0 5 10 15 20 25 30 35 40

δ4

with TCSC FPIC with TCSC STFPIC

Time (sec.)

Figure 15. Rotor angle of generator 4 with STFPIC for base case with fault at bus 8

Figure 14. Rotor angle of generator 1 with STFPIC for base case with fault at bus 8 **Figure 14.** Rotor angle of generator 1 with STFPIC for base case with fault at bus 8





radian




Time (sec.)

Figure 14. Rotor angle of generator 1 with STFPIC for base case with fault at bus 8

δ1

with TCSC FPIC with TCSC STFPIC

Figure 15. Rotor angle of generator 4 with STFPIC for base case with fault at bus 8 **Figure 15.** Rotor angle of generator 4 with STFPIC for base case with fault at bus 8

0.08 0.1 0.12 0.14 0.16 0.18 0.2 0.22 0.24

radian

0 5 10 15 20 25 30 35 40 45 50

(b) XTCSC

with TCSC FPIC with TCSC STFPIC

Figure 12. Active power flow in line 11-10 and TCSC capacitive reactance with STFPIC for 110% loading with fault at bus 9

with TCSC STFPIC with TCSC FPIC

0 5 10 15 20 25 30 35 40 45 50

Time (sec.)

(a) Base case

0 10 20 30 40 50 60

(b) 110% loading

0 10 20 30 40 50 60

Time (sec.)

δ1

with TCSC FPIC with TCSC STFPIC

0 5 10 15 20 25 30 35 40

Time (sec.)

Figure 14. Rotor angle of generator 1 with STFPIC for base case with fault at bus 8

δ4

with TCSC FPIC with TCSC STFPIC

0 5 10 15 20 25 30 35 40

Time (sec.)

Figure 15. Rotor angle of generator 4 with STFPIC for base case with fault at bus 8

Figure 13. Variation of α for base case and 110% loading with fault at bus 9 **Figure 13.** Variation of α for base case and 110% loading with fault at bus 9

(a) Power flow in line 11-10



0

1

0

0.06





radian




**Figure 14.** Rotor angle of generator 1 with STFPIC for base case with fault at bus 8

0.08

0.1

0.12

0.14

radian

0.16

0.18

0.2

0.22

0.24

0.5

α

0.5

α

1

p.u.

p.u.

Figure 16. Active power flow in line 11-10 and TCSC capacitive reactance with STFPIC for base case with fault at bus 8 δ1 **Figure 16.** Active power flow in line 11-10 and TCSC capacitive reactance with STFPIC for base case with fault at bus 8

with TCSC FPIC with TCSC STFPIC

0 10 20 30 40 50 60

Time (sec.)

Figure 17. Rotor angle of generator 1 with STFPIC for 110% loading with fault at bus 8

0.05

0.1

0.15

radian

0.2

0.25

p.u.



0.05 0.1

0

0 0.2 0.4 0.6 0.8 1

p.u.

0 5 10 15 20 25 30 35 40

(b) XTCSC

Time (sec.)

Figure 16. Active power flow in line 11-10 and TCSC capacitive reactance with STFPIC for base case with fault at bus 8

(a) Power flow in line 11-10

with TCSC STFPIC with TCSC FPIC

with TCSC FPIC with TCSC STFPIC

**Figure 17.** Rotor angle of generator 1 with STFPIC for 110% loading with fault at bus 8 Figure 17. Rotor angle of generator 1 with STFPIC for 110% loading with fault at bus 8

0 10 20 30 40 50 60

(b) XTCSC

with TCSC FPIC with TCSC STFPIC

Figure 19. Active power flow in line 11-10 and TCSC capacitive reactance with STFPIC for 110% loading with fault at bus 8

with TCSC STFPIC with TCSC FPIC

0 10 20 30 40 50 60

Time (sec.)

(a) Power flow in line 11-10

Figure 18. Rotor angle of generator 4 with STFPIC for 110% loading with fault at bus 8 **Figure 18.** Rotor angle of generator 4 with STFPIC for 110% loading with fault at bus 8

0



p.u.

0.05

0.1

0

0.5

p.u.

1

0 10 20 30 40 50 60

δ4

with TCSC FPIC with TCSC STFPIC

Time (sec.)

Figure 18. Rotor angle of generator 4 with STFPIC for 110% loading with fault at bus 8






radian




0 5 10 15 20 25 30 35 40

(b) XTCSC

0 5 10 15 20 25 30 35 40

Figure 16. Active power flow in line 11-10 and TCSC capacitive reactance with STFPIC for base case with fault at bus 8

with TCSC FPIC with TCSC STFPIC

with TCSC FPIC with TCSC STFPIC

Time (sec.)

δ1

0 10 20 30 40 50 60

0 10 20 30 40 50 60

Time (sec.)

Figure 18. Rotor angle of generator 4 with STFPIC for 110% loading with fault at bus 8

**Figure 18.** Rotor angle of generator 4 with STFPIC for 110% loading with fault at bus 8

(a) Power flow in line 11-10

0 10 20 30 40 50 60

(b) XTCSC

with TCSC FPIC with TCSC STFPIC

Figure 19. Active power flow in line 11-10 and TCSC capacitive reactance with STFPIC for 110% loading with fault at bus 8

with TCSC STFPIC with TCSC FPIC

0 10 20 30 40 50 60

Time (sec.)

Time (sec.)

δ4

**Figure 17.** Rotor angle of generator 1 with STFPIC for 110% loading with fault at bus 8 Figure 17. Rotor angle of generator 1 with STFPIC for 110% loading with fault at bus 8

(a) Power flow in line 11-10

with TCSC STFPIC with TCSC FPIC

with TCSC FPIC with TCSC STFPIC

0 0.2 0.4 0.6 0.8 1


156 Fuzzy Logic - Tool for Getting Accurate Solutions

0.05


0



p.u.

0.05

0.1

0

0.5

p.u.

1

1.5





radian




0.1

0.15

radian

0.2

0.25

0.3


p.u.

0.05 0.1

0

p.u.

**Figure 19.** Active power flow in line 11-10 and TCSC capacitive reactance with STFPIC for 110% loading with fault at Figure 19. Active power flow in line 11-10 and TCSC capacitive reactance with STFPIC for 110% loading with fault at bus 8 bus 8

0 5 10 15 20 25 30 35 40

δ1

with TCSC FPIC with TCSC STFPIC

Time (sec.)

Figure 21. Rotor angle of generator 1 with STFPIC for base case with fault at bus 5

Figure 20. Variation of α for base case and 110% loading with fault at bus 8 **Figure 20.** Variation of α for base case and 110% loading with fault at bus 8

0.05

0.1

0.15

0.2

radian

0.25

0.3

0.35

0.2 0.4 0.6 0.8

α

0 0.2 0.4 0.6 0.8

α

0 10 20 30 40 50 60

(b) 110% loading

Time (sec.)

Figure 20. Variation of α for base case and 110% loading with fault at bus 8

(a) Base case

**Figure 21.** Rotor angle of generator 1 with STFPIC for base case with fault at bus 5 Figure 21. Rotor angle of generator 1 with STFPIC for base case with fault at bus 5

0 5 10 15 20 25 30 35 40

(b) XTCSC

0 5 10 15 20 25 30 35 40

Time (sec.)

(a) Power flow in line 11-10

with TCSC STFPIC with TCSC FPIC

with TCSC FPIC with TCSC STFPIC

Figure 23. Active power flow in line 11-10 and TCSC capacitive reactance with STFPIC for base case with fault at bus 5

Figure 22. Rotor angle of generator 4 with STFPIC for base case with fault at bus 5 **Figure 22.** Rotor angle of generator 4 with STFPIC for base case with fault at bus 5

0


p.u.

0.5

p.u.

1

with TCSC FPIC with TCSC STFPIC

Time (sec.)

Figure 22. Rotor angle of generator 4 with STFPIC for base case with fault at bus 5

δ4




radian



0 10 20 30 40 50 60

(b) 110% loading

0 10 20 30 40 50 60

δ1

with TCSC FPIC with TCSC STFPIC

with TCSC FPIC with TCSC STFPIC

0 5 10 15 20 25 30 35 40

Time (sec.)

δ4

0 5 10 15 20 25 30 35 40

Time (sec.)

with TCSC STFPIC with TCSC FPIC

with TCSC FPIC with TCSC STFPIC

Figure 23. Active power flow in line 11-10 and TCSC capacitive reactance with STFPIC for base case with fault at bus 5

Figure 22. Rotor angle of generator 4 with STFPIC for base case with fault at bus 5

**Figure 22.** Rotor angle of generator 4 with STFPIC for base case with fault at bus 5

(a) Power flow in line 11-10

0 5 10 15 20 25 30 35 40

(b) XTCSC

0 5 10 15 20 25 30 35 40

Time (sec.)

**Figure 21.** Rotor angle of generator 1 with STFPIC for base case with fault at bus 5 Figure 21. Rotor angle of generator 1 with STFPIC for base case with fault at bus 5

Time (sec.)

Figure 20. Variation of α for base case and 110% loading with fault at bus 8

(a) Base case

0 0.2 0.4 0.6 0.8

0 0.2 0.4 0.6 0.8

158 Fuzzy Logic - Tool for Getting Accurate Solutions

0.05


0


p.u.

0.5

p.u.

1

1.5



radian



0.1

0.15

0.2

radian

0.25

0.3

0.35

0.4

α

α

**Figure 23.** Active power flow in line 11-10 and TCSC capacitive reactance with STFPIC for base case with fault at bus 5 Figure 23. Active power flow in line 11-10 and TCSC capacitive reactance with STFPIC for base case with fault at bus 5

0 5 10 15 20 25 30 35 40 45 50

δ4

with TCSC FPIC with TCSC STFPIC

Time (sec.)

Figure 25. Rotor angle of generator 4 with STFPIC for 110% loading with fault at bus 5

Figure 24. Rotor angle of generator 1 with STFPIC for 110% loading with fault at bus 5 **Figure 24.** Rotor angle of generator 1 with STFPIC for 110% loading with fault at bus 5





radian



0.05

0.1

0.15

0.2

0.25

radian

0.3

0.35

0.4

0.45

Time (sec.)

Figure 24. Rotor angle of generator 1 with STFPIC for 110% loading with fault at bus 5

δ1

with TCSC FPIC with TCSC STFPIC

Figure 25. Rotor angle of generator 4 with STFPIC for 110% loading with fault at bus 5 **Figure 25.** Rotor angle of generator 4 with STFPIC for 110% loading with fault at bus 5

Figure 26. Active power flow in line 11-10 and TCSC capacitive reactance with STFPIC for 110% loading with fault at bus 5 (a) Base case **Figure 26.** Active power flow in line 11-10 and TCSC capacitive reactance with STFPIC for 110% loading with fault at bus 5

0 10 20 30 40 50 60

(b) 110% loading

0 10 20 30 40 50 60

Time (sec.)

In this system, initially the short-circuit fault has been assumed to occur at bus 24. From the fault simulation studies carried out at the base case loading condition (the loading condition as described in [16, 19]), it has been observed that the proposed TCSC STFPIC improved the system performance. Subsequently, a great number of fault studies have been carried out at several increased system loading situations to inspect the effectiveness of the developed STFPIC for improving the performance of the system. After all these studies, it has been found that the TCSC STFPIC helps to further increase the damping for the system. Only a few representative results are presented below to illustrate the

The performance of the TCSC STFPIC at 160% loading condition (w.r.t. the base case loading condition as described in [16]) is shown in Figs. 1.28–1.31. From these figures it is observed that at 160% loading condition, substantial improvement in the system performance is achieved by the proposed TCSC STFPIC. For implementing STFPIC, K has been set equal to 10. When the system loading level is further increased to 175% of the base case loading condition, the proposed TCSC STFPIC is able to improve the system performance significantly as illustrated in Figs. 1.32 and 1.33. It

effectiveness of the developed STFPIC in further enhancing the performance of the system under study.

Figure 27. Variation of α for base case and 110% loading with fault at bus 5

3.2.2. 10-machine 39-bus system

0

1

0

0.5

α

0.5

α

1

with TCSC STFPIC with TCSC FPIC

with TCSC FPIC with TCSC STFPIC

Figure 26. Active power flow in line 11-10 and TCSC capacitive reactance with STFPIC for 110% loading with fault at bus 5

0 10 20 30 40 50 60

(b) XTCSC

0 10 20 30 40 50 60

Time (sec.)

(a) Power flow in line 11-10

Figure 27. Variation of α for base case and 110% loading with fault at bus 5 **Figure 27.** Variation of α for base case and 110% loading with fault at bus 5

0


0

0.05 0.1

p.u.

0.5

p.u.

1

1.5

0 5 10 15 20 25 30 35 40 45 50

δ4

0 5 10 15 20 25 30 35 40 45 50

Time (sec.)

(a) Power flow in line 11-10

0 10 20 30 40 50 60

(b) XTCSC

0 10 20 30 40 50 60

Time (sec.)

(a) Base case

**Figure 26.** Active power flow in line 11-10 and TCSC capacitive reactance with STFPIC for 110% loading with fault at

0 10 20 30 40 50 60

(b) 110% loading

0 10 20 30 40 50 60

Time (sec.)

Figure 27. Variation of α for base case and 110% loading with fault at bus 5

3.2.2. 10-machine 39-bus system

Figure 25. Rotor angle of generator 4 with STFPIC for 110% loading with fault at bus 5 **Figure 25.** Rotor angle of generator 4 with STFPIC for 110% loading with fault at bus 5

Time (sec.)

Figure 24. Rotor angle of generator 1 with STFPIC for 110% loading with fault at bus 5

δ1

with TCSC FPIC with TCSC STFPIC

> with TCSC FPIC with TCSC STFPIC

with TCSC STFPIC with TCSC FPIC

with TCSC FPIC with TCSC STFPIC

Figure 26. Active power flow in line 11-10 and TCSC capacitive reactance with STFPIC for 110% loading with fault at bus 5

In this system, initially the short-circuit fault has been assumed to occur at bus 24. From the fault simulation studies carried out at the base case loading condition (the loading condition as described in [16, 19]), it has been observed that the proposed TCSC STFPIC improved the system performance. Subsequently, a great number of fault studies have been carried out at several increased system loading situations to inspect the effectiveness of the developed STFPIC for improving the performance of the system. After all these studies, it has been found that the TCSC STFPIC helps to further increase the damping for the system. Only a few representative results are presented below to illustrate the

The performance of the TCSC STFPIC at 160% loading condition (w.r.t. the base case loading condition as described in [16]) is shown in Figs. 1.28–1.31. From these figures it is observed that at 160% loading condition, substantial improvement in the system performance is achieved by the proposed TCSC STFPIC. For implementing STFPIC, K has been set equal to 10. When the system loading level is further increased to 175% of the base case loading condition, the proposed TCSC STFPIC is able to improve the system performance significantly as illustrated in Figs. 1.32 and 1.33. It

effectiveness of the developed STFPIC in further enhancing the performance of the system under study.

0

160 Fuzzy Logic - Tool for Getting Accurate Solutions


0


0

1

0

0.5

α

0.5

α

bus 5

1

0 0.05 0.1

p.u.

0.5

p.u.

1

1.5




radian



0.05

0.1

0.15

0.2

0.25

radian

0.3

0.35

0.4

0.45

3.2.2. 10-machine 39-bus system In this system, initially the short-circuit fault has been assumed to occur at bus 24. From the fault simulation studies carried out at the base case loading condition (the loading condition as described in [16, 19]), it has been observed that the proposed TCSC STFPIC improved the system performance. Subsequently, a great number of fault studies have been carried out at several increased system loading situations to inspect the effectiveness of the developed STFPIC for improving the performance of the system. After all these studies, it has been found that the TCSC STFPIC helps to further increase the damping for the system. Only a few representative results are presented below to illustrate the effectiveness of the developed STFPIC in further enhancing the performance of the system under study. The performance of the TCSC STFPIC at 160% loading condition (w.r.t. the base case loading condition as described in [16]) is shown in Figs. 28– 3 From these figures it is observed that at 160% loading condition, substantial improvement in the system performance is achieved by the proposed TCSC STFPIC. For implementing STFPIC, K has been set equal to 10. When the system loading level is further increased to 175% of the base case loading condition, the proposed TCSC STFPIC is able to improve the system performance significantly as illustrated in Figs. 32 and 33. It can be noticed from Figs. 31(b) and 33(b) that STFPIC has been able to improve the damping with smaller variation in XTCSC as compared to FPIC for 160% and 175% loading conditions, respectively, with fault at bus 24. The variations of α for fault at bus 24 are shown in Fig. 34, corresponding to 160% and 175% loading conditions.

The performance of the TCSC STFPIC at 160% loading condition (w.r.t. the base case loading condition as described in [16]) is shown in Figs. 1.28–1.31. From these figures it is observed that at 160% loading condition, substantial improvement in the system performance is achieved by the proposed TCSC STFPIC. For implementing STFPIC, K has been set equal to 10. When the system loading level is further increased to 175% of the base case loading condition, the proposed TCSC STFPIC is able to improve the system performance significantly as illustrated in Figs. 1.32 and 1.33. It Additional fault simulation studies have also been carried out with faults at different locations, for various loading conditions, to investigate the robustness of the proposed control scheme. For all the simulation studies carried out in this work, the TCSC STFPIC has improved the damping of the system (as compared to the damping obtained with FPIC). Some representative results obtained at 175% loading condition are shown in Figs. 35– 38. Figures 35 and 36 show the results for fault at bus 38, while the results for fault at bus 23 are shown in Figs. 37 and 38. These results amply demonstrate that the TCSC STFPIC helps to enhance the damping capability of the system quite significantly. The variations of α for fault at bus 38 and 23 corresponding to 175% loading conditions are shown in Fig. 39. Variation of the rotor angle of generator 3 only has been shown for 175% loading condition.

can be noticed from Figs. 1.31(b) and 1.33(b) that STFPIC has been able to improve the damping with smaller variation in XTCSC as compared to FPIC for 160% and 175% loading conditions, respectively, with fault at bus 24. The variations of

α for fault at bus 24 are shown in Fig. 1.34, corresponding to 160% and 175% loading conditions.

can be noticed from Figs. 1.31(b) and 1.33(b) that STFPIC has been able to improve the damping with smaller variation in XTCSC as compared to FPIC for 160% and 175% loading conditions, respectively, with fault at bus 24. The variations of

Additional fault simulation studies have also been carried out with faults at different locations, for various loading conditions, to investigate the robustness of the proposed control scheme. For all the simulation studies carried out in this work, the TCSC STFPIC has improved the damping of the system (as compared to the damping obtained with FPIC). Some representative results obtained at 175% loading condition are shown in Figs. 1.35–1.38. Figures 1.35 and 1.36 show the results for fault at bus 38, while the results for fault at bus 23 are shown in Figs. 1.37 and 1.38. These results amply demonstrate that the TCSC STFPIC helps to enhance the damping capability of the system quite significantly. The variations of α for fault at bus 38 and 23 corresponding to 175% loading conditions are shown in Fig.

Additional fault simulation studies have also been carried out with faults at different locations, for various loading conditions, to investigate the robustness of the proposed control scheme. For all the simulation studies carried out in this work, the TCSC STFPIC has improved the damping of the system (as compared to the damping obtained with FPIC). Some representative results obtained at 175% loading condition are shown in Figs. 1.35–1.38. Figures 1.35 and 1.36 show the results for fault at bus 38, while the results for fault at bus 23 are shown in Figs. 1.37 and 1.38. These

significantly. The variations of α for fault at bus 38 and 23 corresponding to 175% loading conditions are shown in Fig.

with TCSC FPIC

1.39. Variation of the rotor angle of generator 3 only has been shown for 175% loading condition.

α for fault at bus 24 are shown in Fig. 1.34, corresponding to 160% and 175% loading conditions.

1.39. Variation of the rotor angle of generator 3 only has been shown for 175% loading condition.

(a) δ<sup>1</sup>

Figure 28. Rotor angles of generator 1 and 2 with STFPIC for 160% loading with fault at bus 24 **Figure 28.** Rotor angles of generator 1 and 2 with STFPIC for 160% loading with fault at bus 24 Figure 28. Rotor angles of generator 1 and 2 with STFPIC for 160% loading with fault at bus 24

Figure 29. Rotor angles of generator 7 and 8 with STFPIC for 160% loading with fault at bus 24 **Figure 29.** Rotor angles of generator 7 and 8 with STFPIC for 160% loading with fault at bus 24

Figure 30. Rotor angles of generator 9 and 10 with STFPIC for 160% loading with fault at bus 24 **Figure 30.** Rotor angles of generator 9 and 10 with STFPIC for 160% loading with fault at bus 24 Time (sec.)

8

can be noticed from Figs. 1.31(b) and 1.33(b) that STFPIC has been able to improve the damping with smaller variation in XTCSC as compared to FPIC for 160% and 175% loading conditions, respectively, with fault at bus 24. The variations of

α for fault at bus 24 are shown in Fig. 1.34, corresponding to 160% and 175% loading conditions.

can be noticed from Figs. 1.31(b) and 1.33(b) that STFPIC has been able to improve the damping with smaller variation in XTCSC as compared to FPIC for 160% and 175% loading conditions, respectively, with fault at bus 24. The variations of

Additional fault simulation studies have also been carried out with faults at different locations, for various loading conditions, to investigate the robustness of the proposed control scheme. For all the simulation studies carried out in this work, the TCSC STFPIC has improved the damping of the system (as compared to the damping obtained with FPIC). Some representative results obtained at 175% loading condition are shown in Figs. 1.35–1.38. Figures 1.35 and 1.36 show the results for fault at bus 38, while the results for fault at bus 23 are shown in Figs. 1.37 and 1.38. These results amply demonstrate that the TCSC STFPIC helps to enhance the damping capability of the system quite significantly. The variations of α for fault at bus 38 and 23 corresponding to 175% loading conditions are shown in Fig.

Additional fault simulation studies have also been carried out with faults at different locations, for various loading conditions, to investigate the robustness of the proposed control scheme. For all the simulation studies carried out in this work, the TCSC STFPIC has improved the damping of the system (as compared to the damping obtained with FPIC). Some representative results obtained at 175% loading condition are shown in Figs. 1.35–1.38. Figures 1.35 and 1.36 show the results for fault at bus 38, while the results for fault at bus 23 are shown in Figs. 1.37 and 1.38. These results amply demonstrate that the TCSC STFPIC helps to enhance the damping capability of the system quite significantly. The variations of α for fault at bus 38 and 23 corresponding to 175% loading conditions are shown in Fig.

α for fault at bus 24 are shown in Fig. 1.34, corresponding to 160% and 175% loading conditions.

1.39. Variation of the rotor angle of generator 3 only has been shown for 175% loading condition.

with TCSC FPIC with TCSC STFPIC

with TCSC FPIC with TCSC STFPIC

with TCSC FPIC with TCSC STFPIC

with TCSC FPIC with TCSC STFPIC

1.39. Variation of the rotor angle of generator 3 only has been shown for 175% loading condition.

0 5 10 15 20 25 30 35 40 45 50

0 5 10 15 20 25 30 35 40 45 50

(b) δ<sup>2</sup>

(a) δ<sup>1</sup>

(b) δ<sup>2</sup>

0 5 10 15 20 25 30 35 40 45 50

Figure 28. Rotor angles of generator 1 and 2 with STFPIC for 160% loading with fault at bus 24

0 5 10 15 20 25 30 35 40 45 50

Time (sec.)

with TCSC FPIC with TCSC STFPIC

> with TCSC FPIC with TCSC STFPIC

with TCSC FPIC with TCSC STFPIC

with TCSC FPIC with TCSC STFPIC

Figure 28. Rotor angles of generator 1 and 2 with STFPIC for 160% loading with fault at bus 24

Time (sec.)

(a) δ<sup>7</sup>

0 5 10 15 20 25 30 35 40 45 50

(b) δ<sup>8</sup>

0 5 10 15 20 25 30 35 40 45 50

(b) δ<sup>8</sup>

0 5 10 15 20 25 30 35 40 45 50

Figure 29. Rotor angles of generator 7 and 8 with STFPIC for 160% loading with fault at bus 24

Figure 29. Rotor angles of generator 7 and 8 with STFPIC for 160% loading with fault at bus 24 **Figure 29.** Rotor angles of generator 7 and 8 with STFPIC for 160% loading with fault at bus 24

0 5 10 15 20 25 30 35 40 45 50

Time (sec.)

Time (sec.)

(a) δ<sup>7</sup>

**Figure 28.** Rotor angles of generator 1 and 2 with STFPIC for 160% loading with fault at bus 24

(a) δ<sup>1</sup>







0.2


0

radian

radian

radian

radian

0

0

0.5

0.5

0

0

0.2

0.2

radian

radian

0


0.2

0

0.2

162 Fuzzy Logic - Tool for Getting Accurate Solutions

radian

radian

(a) Power flow in line 39-36

Figure 30. Rotor angles of generator 9 and 10 with STFPIC for 160% loading with fault at bus 24

**Figure 31.** Active power flow in line 39-36 and TCSC capacitive reactance with STFPIC for 160% loading with fault at Figure 31. Active power flow in line 39-36 and TCSC capacitive reactance with STFPIC for 160% loading with fault at bus 24 bus 24

radian

δ3

Figure 32. Rotor angle of generator 3 for 175% loading with STFPIC for fault at bus 24 **Figure 32.** Rotor angle of generator 3 for 175% loading with STFPIC for fault at bus 24

10

(a) Power flow in line 39-36

Figure 32. Rotor angle of generator 3 for 175% loading with STFPIC for fault at bus 24

Time (sec.)

with TCSC FPIC

**Figure 33.** Active power flow in line 39-36 and TCSC capacitive reactance with STFPIC for 175% loading with fault at Figure 33. Active power flow in line 39-36 and TCSC capacitive reactance with STFPIC for 175% loading with fault at bus 24 bus 24

Figure 34. Variation of α for 160% and 175% loading with fault at bus 24 **Figure 34.** Variation of α for 160% and 175% loading with fault at bus 24 Figure 34. Variation of α for 160% and 175% loading with fault at bus 24

0 10 20 30 40 50 60 70 80

0 10 20 30 40 50 60 70 80

Time (sec.)

δ3

δ3

with TCSC FPIC with TCSC STFPIC

with TCSC FPIC with TCSC STFPIC

Time (sec.)

Figure 32. Rotor angle of generator 3 for 175% loading with STFPIC for fault at bus 24

**Figure 32.** Rotor angle of generator 3 for 175% loading with STFPIC for fault at bus 24

(a) Power flow in line 39-36

Figure 32. Rotor angle of generator 3 for 175% loading with STFPIC for fault at bus 24

(a) Power flow in line 39-36

0 10 20 30 40 50 60 70 80

(b) XTCSC

0 10 20 30 40 50 60 70 80

(b) XTCSC

0 10 20 30 40 50 60 70 80

Time (sec.)

with TCSC FPIC with TCSC STFPIC

> with TCSC FPIC with TCSC STFPIC

with TCSC FPIC with TCSC STFPIC

Figure 33. Active power flow in line 39-36 and TCSC capacitive reactance with STFPIC for 175% loading with fault at bus 24

**Figure 33.** Active power flow in line 39-36 and TCSC capacitive reactance with STFPIC for 175% loading with fault at Figure 33. Active power flow in line 39-36 and TCSC capacitive reactance with STFPIC for 175% loading with fault at bus 24

with TCSC FPIC with TCSC STFPIC

0 10 20 30 40 50 60 70 80

Time (sec.)






0

p.u.



p.u.

bus 24

0.01 0.02


0

p.u.

0

p.u.

10

5

5

10




radian

radian



0

0.1

0

0.1

164 Fuzzy Logic - Tool for Getting Accurate Solutions

Figure 35. Rotor angle of generator 3 for 175% loading with STFPIC for fault at bus 38

0 10 20 30 40 50 60 70 80 Time (sec.) **Figure 35.** Rotor angle of generator 3 for 175% loading with STFPIC for fau Figure 35. Rotor angle of generator 3 for 175% loading with STFPIC for fault at bus 38 lt at bus 38


0.1

radian

Figure 36. Active power flow in line 39-36 and TCSC capacitive reactance with STFPIC for 175% loading with fault at bus 38 δ3 **Figure 36.** Active power flow in line 39-36 and TCSC capacitive reactance with STFPIC for 175% loading with fault at bus 38 0 10 20 30 40 50 60 70 80 -0.02 Time (sec.)

Figure 36. Active power flow in line 39-36 and TCSC capacitive reactance with STFPIC for 175% loading with fault at bus 38

Time (sec.)

Figure 37. Rotor angle of generator 3 for 175% loading with STFPIC for fault at bus 23

Figure 37. Rotor angle of generator 3 for 175% loading with STFPIC for fault at bus 23 **Figure 37.** Rotor angle of generator 3 for 175% loading with STFPIC for fault at bus 23

0 10 20 30 40 50 60 70 80

(b) XTCSC

0 10 20 30 40 50 60 70 80

(b) XTCSC

(a) Power flow in line 39-36

with TCSC FPIC with TCSC STFPIC

Figure 36. Active power flow in line 39-36 and TCSC capacitive reactance with STFPIC for 175% loading with fault at bus 38

with TCSC FPIC with TCSC STFPIC

with TCSC FPIC with TCSC STFPIC

with TCSC FPIC with TCSC STFPIC

> with TCSC FPIC with TCSC STFPIC

with TCSC FPIC with TCSC STFPIC

0 10 20 30 40 50 60 70 80

Time (sec.)

δ3

**Figure 36.** Active power flow in line 39-36 and TCSC capacitive reactance with STFPIC for 175% loading with fault at

0 10 20 30 40 50 60 70 80

Time (sec.)

δ3

Figure 36. Active power flow in line 39-36 and TCSC capacitive reactance with STFPIC for 175% loading with fault at bus 38

0 10 20 30 40 50 60 70 80

Time (sec.)

Figure 37. Rotor angle of generator 3 for 175% loading with STFPIC for fault at bus 23

Figure 37. Rotor angle of generator 3 for 175% loading with STFPIC for fault at bus 23 **Figure 37.** Rotor angle of generator 3 for 175% loading with STFPIC for fault at bus 23

0 10 20 30 40 50 60 70 80

Time (sec.)

(a) Power flow in line 39-36


p.u.


p.u.










radian

radian




0

0.05 0.1

0

0.05

0.1


0 0.01 0.02


0

5

p.u.

bus 38

0

10

p.u.

5

10

166 Fuzzy Logic - Tool for Getting Accurate Solutions

Figure 38. Active power flow in line 39-36 and TCSC capacitive reactance with STFPIC for 175% loading with fault at bus 23 (a) Fault at bus 38 **Figure 38.** Active power flow in line 39-36 and TCSC capacitive reactance with STFPIC for 175% loading with fault at bus 23 0 10 20 30 40 50 60 70 80 Time (sec.)

cases involving three-phase, 5-cycle, solid short-circuit faults have been investigated on both the study systems discussed earlier, for different loading conditions as well as different fault locations. From the simulation results, it has

Figure 38. Active power flow in line 39-36 and TCSC capacitive reactance with STFPIC for 175% loading with fault at bus 23

In this scheme, the output scaling factor of the FPIC is modulated on-line by a gain updating factor (α) whose value is determined by a second fuzzy logic scheme. Hence, the output scaling factor of STFPIC does not remain fixed while

the controller is in operation, rather it is modified at each sampling instant by a gain updating factor "α."

In this chapter, a methodology has been discussed for designing an adaptive FPIC using self-tuning mechanism (STFPIC). The simulation studies have been carried out in MATLAB/SIMULINK environment. A large number of fault cases involving three-phase, 5-cycle, solid short-circuit faults have been investigated on both the study systems discussed earlier, for different loading conditions as well as different fault locations. From the simulation results, it has

In this scheme, the output scaling factor of the FPIC is modulated on-line by a gain updating factor (α) whose value is determined by a second fuzzy logic scheme. Hence, the output scaling factor of STFPIC does not remain fixed while

been observed that the proposed STFPIC for TCSC improves the system stability significantly.

the controller is in operation, rather it is modified at each sampling instant by a gain updating factor "α."

been observed that the proposed STFPIC for TCSC improves the system stability significantly.

In this chapter, a methodology has been discussed for designing an adaptive FPIC using self-tuning mechanism (STFPIC). The simulation studies have been carried out in MATLAB/SIMULINK environment. A large number of fault Figure 39. Variation of α for 175% loading with fault at bus 38 and 23 **Figure 39.** Variation of α for 175% loading with fault at bus 38 and 23

4. Conclusion

0.6 0.8


### **4. Conclusion**

In this chapter, a methodology has been discussed for designing an adaptive FPIC using selftuning mechanism (STFPIC). The simulation studies have been carried out in MATLAB/ SIMULINK environment. A large number of fault cases involving three-phase, 5-cycle, solid short-circuit faults have been investigated on both the study systems discussed earlier, for different loading conditions as well as different fault locations. From the simulation results, it has been observed that the proposed STFPIC for TCSC improves the system stability signifi‐ cantly.

In this scheme, the output scaling factor of the FPIC is modulated on-line by a gain updating factor (α) whose value is determined by a second fuzzy logic scheme. Hence, the output scaling factor of STFPIC does not remain fixed while the controller is in operation, rather it is modified at each sampling instant by a gain updating factor "α."

The effectiveness of the developed STFPIC has been studied through detailed nonlinear fault simulation studies on both the test systems. The same fault cases have also been studied with FPIC and the performances obtained by STFPIC have been compared to those obtained by FPIC. From the comparative simulation results, it can be observed that the proposed STFPIC for TCSC improves the system damping further (as compared to the system damping obtained by FPIC).

The STFPIC, which comprises of two fuzzy logic blocks, requires increased computational time and memory for implementation. Therefore, it would be advantageous to reduce the size of the rule base so that the requirement of computational time and memory for implementation is reduced.

The performances of FPIC and STFPIC discussed in this chapter have been tested with predesigned scaling factors. However, in real life, the operating point in the system may vary continuously, thereby making it almost impossible to predesign the scaling factors. Thus, it is necessary to determine the scaling factors on-line based on some suitable measurements. In future, such a scheme for on-line determination of the scaling factors will be described.

The proposed self-tuning philosophy may possibly be applied for the tuning of input SFs or for tuning of both input and output SFs simultaneously, which may lead to superior perform‐ ances of the FLCs.

The efficacy and suitability of the proposed techniques can be explored further by applying it to larger power systems for different operating conditions.

### **Author details**

Salman Hameed\*

Address all correspondence to: hameeddee@gmail.com

Department of Electrical Engineering, Aligarh Muslim University, Aligarh, India

### **References**

**4. Conclusion**

168 Fuzzy Logic - Tool for Getting Accurate Solutions

cantly.

by FPIC).

is reduced.

ances of the FLCs.

**Author details**

Salman Hameed\*

In this chapter, a methodology has been discussed for designing an adaptive FPIC using selftuning mechanism (STFPIC). The simulation studies have been carried out in MATLAB/ SIMULINK environment. A large number of fault cases involving three-phase, 5-cycle, solid short-circuit faults have been investigated on both the study systems discussed earlier, for different loading conditions as well as different fault locations. From the simulation results, it has been observed that the proposed STFPIC for TCSC improves the system stability signifi‐

In this scheme, the output scaling factor of the FPIC is modulated on-line by a gain updating factor (α) whose value is determined by a second fuzzy logic scheme. Hence, the output scaling factor of STFPIC does not remain fixed while the controller is in operation, rather it is modified

The effectiveness of the developed STFPIC has been studied through detailed nonlinear fault simulation studies on both the test systems. The same fault cases have also been studied with FPIC and the performances obtained by STFPIC have been compared to those obtained by FPIC. From the comparative simulation results, it can be observed that the proposed STFPIC for TCSC improves the system damping further (as compared to the system damping obtained

The STFPIC, which comprises of two fuzzy logic blocks, requires increased computational time and memory for implementation. Therefore, it would be advantageous to reduce the size of the rule base so that the requirement of computational time and memory for implementation

The performances of FPIC and STFPIC discussed in this chapter have been tested with predesigned scaling factors. However, in real life, the operating point in the system may vary continuously, thereby making it almost impossible to predesign the scaling factors. Thus, it is necessary to determine the scaling factors on-line based on some suitable measurements. In future, such a scheme for on-line determination of the scaling factors will be described.

The proposed self-tuning philosophy may possibly be applied for the tuning of input SFs or for tuning of both input and output SFs simultaneously, which may lead to superior perform‐

The efficacy and suitability of the proposed techniques can be explored further by applying it

Department of Electrical Engineering, Aligarh Muslim University, Aligarh, India

at each sampling instant by a gain updating factor "α."

to larger power systems for different operating conditions.

Address all correspondence to: hameeddee@gmail.com


[16] K. R. Padiyar, *Power System Dynamics - Stability and Control*, Interline Publishing Ltd.,

[17] B. Chowdhury, R. Majumder and B. C. Pal, "Application of multiple-model adaptive control strategy for robust damping of interarea oscillations in power system", IEEE Transactions on Control Systems Technology, vol. 12, no. 5, September 2004, pp.

[19] S. Hameed, "A self-tuning fuzzy PI controller for TCSC to improve power system

[20] S. Hameed, "Power system stability enhancement using reduced rule base self-tun‐

[21] S. Hameed, "Reduced rule base self-tuning fuzzy PI controller for TCSC", Int J Elect

[18] MATLAB/SIMULINK Software, Version 7.0.1, Release 14, The Math Works Inc.

ing fuzzy PI controller for TCSC", IEEE PES T&D, 2010, 04/2010

Bangalore, India 1996.

170 Fuzzy Logic - Tool for Getting Accurate Solutions

stability", Elect Power Sys Res, 10/2008

Power Energy Sys, 11/2010

727-736.

### *Edited by Elmer P. Dadios*

This book is a collection of chapters, concerning the developments within the Fuzzy Logic field of study. The book includes scholarly contributions by various authors pertinent to Fuzzy Logic. Each contribution comes as a separate chapter complete in itself but directly related to the books topics and objectives. The target audience comprises scholars and specialists in the field.

Fuzzy Logic - Tool for Getting Accurate Solutions

Fuzzy Logic

Tool for Getting Accurate Solutions

*Edited by Elmer P. Dadios*

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