**5. Design objectives of SiGe pin photodetectors**

## **5.1. Si1-xGex photodetector design parameters**

While some early attempts to develop SiGe IR detectors concentrated on potential LWIR applications [62,63], in this chapter we focus solely the development of devices for applications involving detection in the NIR band (up to ~1700 nm). The most straightforward method by which to adjust the cutoff wavelength of a SiGe photodetector in order to tune its range of response is to modify the Si1-xGex alloy composition. Si and Ge have the same type of crystal‐ lographic structure and the materials can thus be alloyed with varying Ge concentrations. For Si1-xGex alloys, the lattice constant does not exactly follow Vegard's law. The relative change of the lattice constant is given by [63]:

$$a\_{\text{Si}\_{1-x}\text{Ge}\_x} = 0.5431 + 0.1992x + 0.0002733x^2 \text{(nm)}\tag{11}$$

The concentration of Ge in a layer of Si1-xGex may be accurately measured using characteriza‐ tion techniques such as X-ray diffraction (XRD). As the Ge concentration is increased, the band gap of the material is reduced, and therefore the cutoff wavelength of a detector will increase (extending its operational wavelength range) assuming all other factors remain constant. However, from a practical device fabrication standpoint, depositing pure Ge or SiGe with very high Ge concentration entails certain technical challenges; for instance, as predicted by Equation (11), a higher Ge concentration of Si1-xGex grown on Si results in a larger lattice mismatch between the materials. This can lead to Stranski-Krastanov growth in which islands form to relieve the misfit strain, which in turn leads to rougher surfaces [12]. However, as will be discussed in the following section, the incorporation of even small amounts of tensile strain can be utilized to extend the operating range of a SiGe photodetector having an absorption layer of a given Ge concentration further into the NIR regime. In addition, modification of parameters such as the doping concentration and growth temperature can be undertaken to further fine-tune the spectral response of a device. Thus, there are multiple factors that more or less influence the operational wavelength range of a SiGe based detector. These must be properly balanced in the process of designing and developing a detector device that exhibits required and optimal performance characteristics for a given application(s).

**Figure 13.** SiGe *pin* photodetector structure used to evaluate impact of various fabrication methodologies [64].

A diagnostic *pin* photodetector device structure designed to evaluate the impact of various fabrication methodologies to reduce leakage currents and produce higher detector perform‐ ance is shown in Figure 13 [64]. The structure, from the bottom up, consists of a *p*<sup>+</sup> Si substrate, thin *p*<sup>+</sup> Ge seed layer, thicker *i*-Ge layer, and top *n*<sup>+</sup> polysilicon layer with an underlying *n*<sup>+</sup> doped Ge region. The polysilicon layer covers sections of oxide deposited on the sides of the top surface of the cylindrical detector, under which shallow *p*-Ge regions may form. This structure can be used to help to assess the following: ability to grow high quality/low defect density Ge on Si; layer thicknesses necessary for minimal topological and defect density requirements; and isolation of defect states at the Ge/oxide interface from the signal carrying layers. Also of relevance is the determination of the optimum doping level and thickness of the lighter doped *p*-type Ge regions under the oxide to isolate interface states and lateral leakage current that could result between the highly doped *n*<sup>+</sup> Ge region below the polysilicon and the *p*-Ge regions.

### **5.2. Incorporating strain to improve NIR detection**

mismatch between the materials. This can lead to Stranski-Krastanov growth in which islands form to relieve the misfit strain, which in turn leads to rougher surfaces [12]. However, as will be discussed in the following section, the incorporation of even small amounts of tensile strain can be utilized to extend the operating range of a SiGe photodetector having an absorption layer of a given Ge concentration further into the NIR regime. In addition, modification of parameters such as the doping concentration and growth temperature can be undertaken to further fine-tune the spectral response of a device. Thus, there are multiple factors that more or less influence the operational wavelength range of a SiGe based detector. These must be properly balanced in the process of designing and developing a detector device that exhibits

p+ - Si Substrate (100)

A diagnostic *pin* photodetector device structure designed to evaluate the impact of various fabrication methodologies to reduce leakage currents and produce higher detector perform‐

Ge region. The polysilicon layer covers sections of oxide deposited on the sides of the top surface of the cylindrical detector, under which shallow *p*-Ge regions may form. This structure can be used to help to assess the following: ability to grow high quality/low defect density Ge on Si; layer thicknesses necessary for minimal topological and defect density requirements; and isolation of defect states at the Ge/oxide interface from the signal carrying layers. Also of relevance is the determination of the optimum doping level and thickness of the lighter doped

Si substrate,

doped

polysilicon layer with an underlying *n*<sup>+</sup>

**Figure 13.** SiGe *pin* photodetector structure used to evaluate impact of various fabrication methodologies [64].

ance is shown in Figure 13 [64]. The structure, from the bottom up, consists of a *p*<sup>+</sup>

Ge seed layer, thicker *i*-Ge layer, and top *n*<sup>+</sup>

thin *p*<sup>+</sup>

p+ - Ge seed layer

Photon Absorbtion Layer

n+ - poly SiGe Layer p - Ge Layer p - Ge Layer Oxide Oxide

n+ - Ge Layer

>1 m Intrinsic Ge Layer

required and optimal performance characteristics for a given application(s).

336 Advances in Optical Fiber Technology: Fundamental Optical Phenomena and Applications

Strains and consequent stresses normally arise during epitaxial growth of thin films on substrates of different compositions and/or crystal structures. Internal strains and stresses can result from a mismatch in the lattice constants of the individual layers, which is illustrated in Figure 14. If the lattice mismatch between two materials is less than ~9%, the initial layers of film will grow pseudomorphically, i.e., the films strain elastically in order to maintain the same interatomic spacing. As the film grows thicker, the increasing strain will create a series of misfit dislocations separated by regions of relatively good fit.

**Figure 14.** Relationship between lattice mismatch of Si and Ge and misfit dislocations that degrade detector perform‐ ance [18].

Since the lattice constant of Ge exceeds of that of Si by 4.18%, very thin Si1-xGex (*x* > 0) layers grown on a Si substrates are initially compressively strained. Near perfect epitaxial growth of such a strained heteroepitaxial layer can be achieved if its thickness does not exceed a critical thickness for stability. Since the pseudomorphic critical thickness for growth of Ge on Si with strain due to lattice mismatch is less than 1 nm, a Ge layer that is grown with a thickness that is substantially larger than this limit will relax through the forma‐ tion of misfit dislocations [7,10].

However, the difference in thermal expansion coefficients between the layers can also play a significant role in the development of strain following epitaxial growth. Since Ge has a larger thermal expansion coefficient than Si, when the temperature cools to RT after growth the consequent reduction in the lattice constant of a deposited Ge/SiGe layer will be suppressed by the Si substrate [65]. This results in the generation of residual tensile strain in the Ge/SiGe layer normally within the range of 0.15-0.30% [9,66]. The changes in band gap energy and absorption that occur with the introduction of strain are depicted in Figure 15(a) and (b), respectively.

strained Ge [53].

**5.3 Reducing Dark Current** 

increases proportionally to devices size.

dislocations that degrade detector performance [18].

**Figure 14.** Relationship between lattice mismatch of Si and Ge and misfit

Since the lattice constant of Ge exceeds of that of Si by 4.18%, very thin Si1-*x*Ge*x* (*x* > 0) layers grown on a Si substrates are initially compressively strained. Near perfect epitaxial growth of such a strained heteroepitaxial layer can be achieved if its thickness does not exceed a critical thickness for stability. Since the pseudomorphic critical thickness for growth of Ge on Si with strain due to lattice mismatch is less than 1 nm, a Ge layer that is grown with a thickness that is substantially larger than this limit will relax through the formation of misfit dislocations [7,10].

However, the difference in thermal expansion coefficients between the layers can also play a significant role in the development of strain following epitaxial growth. Since Ge has a larger thermal expansion coefficient than Si, when the temperature cools to RT after growth the consequent reduction in the lattice constant of a deposited Ge/SiGe layer will be suppressed by

normally within the range of 0.15-0.30% [9,66]. The changes in band gap energy and absorption that occur with the introduction of strain are depicted in Figure 15(a) and (b), respectively.

**Figure 15.** (a) Calculated change in direct band gap energy as a function of strain in Ge [65]. (b) Absorption spectra of bulk Ge, and 0.20% and 0.25% tensile **Figure 15.** (a) Calculated change in direct band gap energy as a function of strain in Ge [65]. (b) Absorption spectra of bulk Ge, and 0.20% and 0.25% tensile strained Ge [53].

23 The presence of this biaxial tensile stress in Ge causes the valence subbands to split, where the top of the valence band comprises the light hole band. The light hole band energy increases and consequently both the direct and indirect gaps shrink, with the direct gap shrinking more rapidly. Thus, with the increase of tensile strain, Ge transforms from an indirect gap material towards a direct gap material. This stress-induced shift in valence subbands is depicted in Figure 16(a). The presence of this biaxial tensile stress in Ge causes the valence subbands to split, where the top of the valence band comprises the light hole band. The light hole band energy increases and consequently both the direct and indirect gaps shrink, with the direct gap shrinking more rapidly.

Upon application of tensile strain, e.g., of 0.2%, the direct band gap of Ge reduces from 0.80 eV for unstrained material to ~0.77 eV, which effectively increases the corresponding cutoff wavelength from 1550 to 1610 nm [15,65]. As shown in Figure 16(b), this provides greater sensitivity for sensor operation at NIR wavelengths of 1600 nm and above due to the higher absorption coefficient (~5X) and recombination rates of the strained Ge over this range [9]. This extended operational range is very useful for telecommunications, since strained layer SiGe based sensors can operate over most or all of the L band spanning 1560-1620 nm, as well as for other applications requiring detection of longer wavelengths in the NIR regime. Thus, with the increase of tensile strain, Ge transforms from an indirect gap material towards a direct gap material. This stress-induced shift in valence subbands is depicted in Figure 16(a). Upon application of tensile strain, e.g., of 0.2%, the direct band gap of Ge reduces from 0.80 eV for unstrained material to ~0.77 eV, which effectively increases the corresponding cutoff wavelength from 1550 to 1610 nm [15,65]. As shown in Figure 16(b), this provides greater sensitivity for sensor operation at NIR wavelengths of 1600 nm and above due to the higher absorption coefficient (~5X) and recombination rates of the strained Ge over this range [9]. This extended operational range is very useful for telecommunications, since strained layer SiGe based sensors can operate over most or all of the L band spanning 1560-1620 nm, as well as for

other applications requiring detection of longer wavelengths in the NIR regime.

photodetectors having unstrained and strained Ge layers [67].

**Figure 16.** (a) Shift of Ge from indirect gap toward direct gap material with application of tensile stain [10]. (b) Comparison of responsivity spectra for *pin* **Figure 16.** (a) Shift of Ge from indirect gap toward direct gap material with application of tensile strain [10]. (b) Com‐ parison of responsivity spectra for *pin* photodetectors having unstrained and strained Ge layers [67].

The growth of Ge on Si can be characterized as Stranski-Krastanov growth, an example of which is shown in Figure 17(a). For film thicknesses below the critical thickness, a 2D wetting layer is formed, beyond which a transition to 3D islanding growth mode occurs to relieve the built-in strain in the Ge layers [66]. Defects and threading dislocations arising during Stranski-Krastanov growth typically form recombination centers. At RT, dark current in *pin* photodetectors, i.e., the current measured under reverse bias with no illumination, is mainly due to generation current through such traps [68]. Higher levels of dark current result in increased power consumption that reduces detector performance, and shot noise associated with this leakage current can also degrade the SNR [5] and lower sensitivity for NIR systems [1]. Figure 17(b) shows typical I-V characteristics SiGe devices where the dark current at negative bias

24

#### **5.3. Reducing dark current**

fabrication [63].

23

The presence of this biaxial tensile stress in Ge causes the valence subbands to split, where the top of the valence band comprises the light hole band. The light hole band energy increases and consequently both the direct and indirect gaps shrink, with the direct gap shrinking more rapidly. Thus, with the increase of tensile strain, Ge transforms from an indirect gap material towards a direct gap material. This stress-induced shift in valence subbands is depicted in Figure 16(a).

Upon application of tensile strain, e.g., of 0.2%, the direct band gap of Ge reduces from 0.80 eV for unstrained material to ~0.77 eV, which effectively increases the corresponding cutoff wavelength from 1550 to 1610 nm [15,65]. As shown in Figure 16(b), this provides greater sensitivity for sensor operation at NIR wavelengths of 1600 nm and above due to the higher absorption coefficient (~5X) and recombination rates of the strained Ge over this range [9]. This extended operational range is very useful for telecommunications, since strained layer SiGe based sensors can operate over most or all of the L band spanning 1560-1620 nm, as well as for

Upon application of tensile strain, e.g., of 0.2%, the direct band gap of Ge reduces from 0.80 eV for unstrained material to ~0.77 eV, which effectively increases the corresponding cutoff wavelength from 1550 to 1610 nm [15,65]. As shown in Figure 16(b), this provides greater sensitivity for sensor operation at NIR wavelengths of 1600 nm and above due to the higher absorption coefficient (~5X) and recombination rates of the strained Ge over this range [9]. This extended operational range is very useful for telecommunications, since strained layer SiGe based sensors can operate over most or all of the L band spanning 1560-1620 nm, as well as for

**Figure 16.** (a) Shift of Ge from indirect gap toward direct gap material with application of tensile stain [10]. (b) Comparison of responsivity spectra for *pin*

**Figure 16.** (a) Shift of Ge from indirect gap toward direct gap material with application of tensile strain [10]. (b) Com‐

The growth of Ge on Si can be characterized as Stranski-Krastanov growth, an example of which is shown in Figure 17(a). For film thicknesses below the critical thickness, a 2D wetting layer is formed, beyond which a transition to 3D islanding growth mode occurs to relieve the built-in strain in the Ge layers [66]. Defects and threading dislocations arising during Stranski-Krastanov growth typically form recombination centers. At RT, dark current in *pin* photodetectors, i.e., the current measured under reverse bias with no illumination, is mainly due to generation current through such traps [68]. Higher levels of dark current result in increased power consumption that reduces detector performance, and shot noise associated with this leakage current can also degrade the SNR [5] and lower sensitivity for NIR systems [1]. Figure 17(b) shows typical I-V characteristics SiGe devices where the dark current at negative bias

24

other applications requiring detection of longer wavelengths in the NIR regime.

other applications requiring detection of longer wavelengths in the NIR regime.

(a) (b)

photodetectors having unstrained and strained Ge layers [67].

parison of responsivity spectra for *pin* photodetectors having unstrained and strained Ge layers [67].

**Figure 15.** (a) Calculated change in direct band gap energy as a function of strain in Ge [65]. (b) Absorption spectra of bulk Ge, and 0.20% and 0.25% tensile

**Figure 15.** (a) Calculated change in direct band gap energy as a function of strain in Ge [65]. (b) Absorption spectra of

The presence of this biaxial tensile stress in Ge causes the valence subbands to split, where the top of the valence band comprises the light hole band. The light hole band energy increases and consequently both the direct and indirect gaps shrink, with the direct gap shrinking more rapidly. Thus, with the increase of tensile strain, Ge transforms from an indirect gap material towards a direct gap material. This stress-induced shift in valence subbands is depicted in

strained Ge [53].

**5.3 Reducing Dark Current** 

increases proportionally to devices size.

Figure 16(a).

bulk Ge, and 0.20% and 0.25% tensile strained Ge [53].

**Figure 14.** Relationship between lattice mismatch of Si and Ge and misfit

Since the lattice constant of Ge exceeds of that of Si by 4.18%, very thin Si1-*x*Ge*x* (*x* > 0) layers grown on a Si substrates are initially compressively strained. Near perfect epitaxial growth of such a strained heteroepitaxial layer can be achieved if its thickness does not exceed a critical thickness for stability. Since the pseudomorphic critical thickness for growth of Ge on Si with strain due to lattice mismatch is less than 1 nm, a Ge layer that is grown with a thickness that is substantially larger than this limit will relax through the formation of misfit dislocations [7,10].

However, the difference in thermal expansion coefficients between the layers can also play a significant role in the development of strain following epitaxial growth. Since Ge has a larger thermal expansion coefficient than Si, when the temperature cools to RT after growth the consequent reduction in the lattice constant of a deposited Ge/SiGe layer will be suppressed by the Si substrate [65]. This results in the generation of residual tensile strain in the Ge/SiGe layer normally within the range of 0.15-0.30% [9,66]. The changes in band gap energy and absorption that occur with the introduction of strain are depicted in Figure 15(a) and (b), respectively.

dislocations that degrade detector performance [18].

(a) (b)

338 Advances in Optical Fiber Technology: Fundamental Optical Phenomena and Applications

The growth of Ge on Si can be characterized as Stranski-Krastanov growth, an example of which is shown in Figure 17(a). For film thicknesses below the critical thickness, a 2D wetting layer is formed, beyond which a transition to 3D islanding growth mode occurs to relieve the built-in strain in the Ge layers [66]. Defects and threading dislocations arising during Stranski-Krastanov growth typically form recombination centers. At RT, dark current in *pin* photode‐ tectors, i.e., the current measured under reverse bias with no illumination, is mainly due to generation current through such traps [68]. Higher levels of dark current result in increased power consumption that reduces detector performance, and shot noise associated with this leakage current can also degrade the SNR [5] and lower sensitivity for NIR systems [1]. Figure 17(b) shows typical I-V characteristics SiGe devices where the dark current at negative bias increases proportionally to device size.

**Figure 17.** (a) Ge-on-Si Stranski-Krastanov epitaxial growth [10]. (b) Measured RT I-V characteristics for large area diodes with 20, 50 and 200 µm unit cells; the inset shows a schematic of the device cross-section [24]. **Figure 17.** (a) Ge-on-Si Stranski-Krastanov epitaxial growth [10]. (b) Measured RT I-V characteristics for large area di‐ odes with 20, 50 and 200 μm unit cells; the inset shows a schematic of the device cross-section [24].

Since dark current can be particularly high in SiGe based photodetectors, a major research thrust has been to reduce the dark current to the greatest extent possible in order to enhance sensitivity and boost overall device performance. (It is noted that in SiGe *pin* photodetectors dark current increases with applied electric field and does not saturate, and thus the measured dark current is usually specified at a given reverse bias, e.g., -1 V.) The goal is to limit the dark current to levels acceptable for high-speed operation usually considered to be not more than 1 µA [54] (or dark current densities of 1-10 mA/cm2 ), above which the transimpedance amplifier noise will be exceeded [35] and the SNR reduced [1]. However, a precise value of the required dark current is dependent upon the particular speed of operation and the amplifier design. Thermionic emission limits the dark current density in SiGe photodetectors down to ~10-2 mA/cm2 at RT, which is around two orders of magnitude higher than that of standard InGaAs based photodetectors [10]. Various approaches have been proposed to further reduce the dark current in SiGe detectors by Since dark current can be particularly high in SiGe based photodetectors, a major research thrust has been to reduce the dark current to the greatest extent possible in order to enhance sensitivity and boost overall device performance. (It is noted that in SiGe *pin* photodetectors dark current increases with applied electric field and does not saturate, and thus the measured dark current is usually specified at a given reverse bias, e.g.,-1 V.) The goal is to limit the dark current to levels acceptable for high-speed operation usually considered to be not more than 1 μA [54] (or dark current densities of 1-10 mA/cm2 ), above which the transimpedance amplifier noise will be exceeded [35] and the SNR reduced [1]. However, a precise value of the required dark current is dependent upon the particular speed of operation and the amplifier design. Thermionic emission limits the dark current density in SiGe photodetectors down to ~10-2 mA/cm2 at RT, which is around two orders of magnitude higher than that of standard InGaAs based photodetectors [10].

several orders of magnitude, including superlattice structures [24], incorporation of quantum dots [63], use of buried junctions [69], and graded compositional layer designs [68]. Dark current generally scales with device area, so reducing the overall size of SiGe detector devices is one means of limiting leakage current for a given photodetector design. For the fabrication of SiGe *pin* detectors, a two-step growth process and high temperature anneal (which will be covered in Section 6) can reduce threading dislocations and thus resultant dark current and dark current density [43,70]. The effects of a buffer layer grown by two-step growth and high temperature annealing on dark current density are shown in Figure 18(a) and (b), respectively. The splitting of the valence bands in Ge due to the presence of tensile strain also lowers the density of states for holes, leading to reduction of intrinsic carrier density that can likewise contribute to reduced reverse dark current in devices [65]. Further methods to effect reductions in dark current include improving surface passivation and/or utilizing smaller selective growth regions during device

25

Various approaches have been proposed to further reduce the dark current in SiGe detectors by several orders of magnitude, including superlattice structures [24], incorporation of quantum dots [63], use of buried junctions [69], and graded compositional layer designs [68]. Dark current generally scales with device area, so reducing the overall size of SiGe detector devices is one means of limiting leakage current for a given photodetector design. For the fabrication of SiGe *pin* detectors, a two-step growth process and high temperature anneal (which will be covered in Section 6) can reduce threading dislocations and thus resultant dark current and dark current density [43,70]. The effects of a buffer layer grown by two-step growth and high temperature annealing on dark current density are shown in Figure 18(a) and (b), respectively. The splitting of the valence bands in Ge due to the presence of tensile strain also lowers the density of states for holes, leading to reduction of intrinsic carrier density that can likewise contribute to reduced reverse dark current in devices [65]. Further methods to effect reductions in dark current include improving surface passivation and/or utilizing smaller selective growth regions during device fabrication [63].

**Figure 18.** Effect of (a) buffer layer grown by two-step growth, and (b) high temperature annealing, on dark current density characteristics [68]. **Figure 18.** Effect of (a) buffer layer grown by two-step growth, and (b) high temperature annealing, on dark current density characteristics [68].

#### **6.0 Fabrication of SiGe** *pin* **Photodetectors 6. Fabrication of SiGe** *pin* **photodetectors**

#### **6.1 SiGe Detector Growth Methods 6.1. SiGe detector growth methods**

**6.2 Two-step Growth Process Overview** 

Epitaxial growth of Si/SiGe using gas precursors has been utilized for the past three decades [10]. Selective growth of Ge/SiGe epitaxial films, using mask layers such as SiO2 and Si3N4, generally requires the formation of vertical sidewalls [usually by reactive ion etching (RIE)] to minimize faceting and enhance trench filling [9]. An early method for growing Ge on Si, first proposed by Luryi *et al.* in 1984 [71] and later optimized by other groups, involved using graded SiGe buffer layers to reduce the density of threading dislocations arising in the Ge layer. Such graded structures lead to an optimized relaxation of the graded layers, where existing threading dislocations are more effectively utilized to relieve stress [43]. However, this method requires significant time and resources as well as necessitates films at least 6 µm thick that are associated with large residual surface roughness, which are problematic for the fabrication of practical, cost effective-devices [4,72]. Epitaxial growth of Si/SiGe using gas precursors has been utilized for the past three decades [10]. Selective growth of Ge/SiGe epitaxial films, using mask layers such as SiO2 and Si3N4, generally requires the formation of vertical sidewalls [usually by reactive ion etching (RIE)] to minimize faceting and enhance trench filling [9]. An early method for growing Ge on Si, first proposed by Luryi *et al.* in 1984 [71] and later optimized by other groups, involved using graded SiGe buffer layers to reduce the density of threading dislocations arising in the Ge layer. Such graded structures lead to an optimized relaxation of the graded layers, where existing threading dislocations are more effectively utilized to relieve stress [43]. However, this method requires significant time and resources as well as necessitates films at least 6 μm

In recent years the most prevalent and useful method to deposit Ge/SiGe layers to form functional *pin* detector devices has involved a two-step growth process where the growth temperature is ramped up between the growth steps. This technique was first applied to epitaxial grown Ge on Si by Colace *et al*. in 1998 [73], and it has since been commonly adopted for Ge epitaxial growth. This method most often involves deposition of Ge/SiGe on intrinsic Si, but

growth of Ge on silicon-on-insulator (SOI) surfaces has also been demonstrated [20].

26

The two-step growth process commonly used for fabricating NI *pin* detectors consists of initial low temperature (LT) epitaxial growth of Ge/SiGe to form a thin strain-relaxed layer, followed by relatively high temperature (HT) growth to form the thicker absorbing film, and a subsequent HT anneal [16,70,74]. In general, the growth steps are primarily designed to prevent islanding. The first LT growth step is crucial in governing the film crystalline quality and the surface thick that are associated with large residual surface roughness, which are problematic for the fabrication of practical, cost effective-devices [4,72].

In recent years the most prevalent and useful method to deposit Ge/SiGe layers to form functional *pin* detector devices has involved a two-step growth process where the growth temperature is ramped up between the growth steps. This technique was first applied to epitaxial grown Ge on Si by Colace *et al*. in 1998 [73], and it has since been commonly adopted for Ge epitaxial growth. This method most often involves deposition of Ge/SiGe on intrinsic Si, but growth of Ge on silicon-on-insulator (SOI) surfaces has also been demonstrated [20].

#### **6.2. Two-step growth process overview**

profiles [1].

**6.3 LT Growth** 

Various approaches have been proposed to further reduce the dark current in SiGe detectors by several orders of magnitude, including superlattice structures [24], incorporation of quantum dots [63], use of buried junctions [69], and graded compositional layer designs [68]. Dark current generally scales with device area, so reducing the overall size of SiGe detector devices is one means of limiting leakage current for a given photodetector design. For the fabrication of SiGe *pin* detectors, a two-step growth process and high temperature anneal (which will be covered in Section 6) can reduce threading dislocations and thus resultant dark current and dark current density [43,70]. The effects of a buffer layer grown by two-step growth and high temperature annealing on dark current density are shown in Figure 18(a) and (b), respectively. The splitting of the valence bands in Ge due to the presence of tensile strain also lowers the density of states for holes, leading to reduction of intrinsic carrier density that can likewise contribute to reduced reverse dark current in devices [65]. Further methods to effect reductions in dark current include improving surface passivation and/or utilizing smaller

**Figure 18.** Effect of (a) buffer layer grown by two-step growth, and (b) high

**Figure 18.** Effect of (a) buffer layer grown by two-step growth, and (b) high temperature annealing, on dark current

Epitaxial growth of Si/SiGe using gas precursors has been utilized for the past three decades [10]. Selective growth of Ge/SiGe epitaxial films, using mask layers such as SiO2 and Si3N4, generally requires the formation of vertical sidewalls [usually by reactive ion etching (RIE)] to minimize faceting and enhance trench filling [9]. An early method for growing Ge on Si, first proposed by Luryi *et al.* in 1984 [71] and later optimized by other groups, involved using graded SiGe buffer layers to reduce the density of threading dislocations arising in the Ge layer. Such graded structures lead to an optimized relaxation of the graded layers, where existing threading dislocations are more effectively utilized to relieve stress [43]. However, this method requires significant time and resources as well as necessitates films at least 6 µm thick that are associated with large residual surface roughness, which are problematic for the fabrication of practical, cost

Epitaxial growth of Si/SiGe using gas precursors has been utilized for the past three decades [10]. Selective growth of Ge/SiGe epitaxial films, using mask layers such as SiO2 and Si3N4, generally requires the formation of vertical sidewalls [usually by reactive ion etching (RIE)] to minimize faceting and enhance trench filling [9]. An early method for growing Ge on Si, first proposed by Luryi *et al.* in 1984 [71] and later optimized by other groups, involved using graded SiGe buffer layers to reduce the density of threading dislocations arising in the Ge layer. Such graded structures lead to an optimized relaxation of the graded layers, where existing threading dislocations are more effectively utilized to relieve stress [43]. However, this method requires significant time and resources as well as necessitates films at least 6 μm

In recent years the most prevalent and useful method to deposit Ge/SiGe layers to form functional *pin* detector devices has involved a two-step growth process where the growth temperature is ramped up between the growth steps. This technique was first applied to epitaxial grown Ge on Si by Colace *et al*. in 1998 [73], and it has since been commonly adopted for Ge epitaxial growth. This method most often involves deposition of Ge/SiGe on intrinsic Si, but

growth of Ge on silicon-on-insulator (SOI) surfaces has also been demonstrated [20].

temperature annealing, on dark current density characteristics [68].

(a) (b)

26

The two-step growth process commonly used for fabricating NI *pin* detectors consists of initial low temperature (LT) epitaxial growth of Ge/SiGe to form a thin strain-relaxed layer, followed by relatively high temperature (HT) growth to form the thicker absorbing film, and a subsequent HT anneal [16,70,74]. In general, the growth steps are primarily designed to prevent islanding. The first LT growth step is crucial in governing the film crystalline quality and the surface

selective growth regions during device fabrication [63].

340 Advances in Optical Fiber Technology: Fundamental Optical Phenomena and Applications

**6.0 Fabrication of SiGe** *pin* **Photodetectors** 

**6. Fabrication of SiGe** *pin* **photodetectors**

**6.1 SiGe Detector Growth Methods** 

**6.1. SiGe detector growth methods**

density characteristics [68].

effective-devices [4,72].

**6.2 Two-step Growth Process Overview** 

The two-step growth process commonly used for fabricating NI *pin* detectors consists of initial low temperature (LT) epitaxial growth of Ge/SiGe to form a thin strain-relaxed layer, followed by relatively high temperature (HT) growth to form the thicker absorbing film, and a subse‐ quent HT anneal [16,70,74]. In general, the growth steps are primarily designed to prevent islanding. The first LT growth step is crucial in governing the film crystalline quality and the surface morphology and also the final strain state in the Ge films [66]. Ge/SiGe films grown using this process have been shown to have reduced rms surface roughness of less than 1 nm [15,70]. In addition, the HT anneal reduces threading dislocations arising from lattice mismatch between the Si and Ge to enable a higher quality Ge film with reduced dark current [9]. Figure 19(a) shows a cross-sectional view of a Ge layer grown on Si with a close-up view of the Ge-Si interface, while Figure 19(b) comprises a top view of the fabricated *pin* photodetector. morphology and also the final strain state in the Ge films [66]. Ge/SiGe films grown using this process have been shown to have reduced rms surface roughness of less than 1 nm [15,70]. In addition, the HT anneal reduces threading dislocations arising from lattice mismatch between the Si and Ge to enable a higher quality Ge film with reduced dark current [9]. Figure 19(a) shows a cross-sectional view of a Ge layer grown on Si with a close-up view of the Ge-Si interface, while

Figure 19(b) comprises a top view of the fabricated *pin* photodetector.

**Figure 19.** (a) Cross-sectional transmission electron microscope (TEM) image of Ge grown on Si substrate, where the inset shows Ge atoms coherently matched up to the Si substrate on a lattice scale; and (b) top view SEM image of fabricated Ge **Figure 19.** (a) Cross-sectional transmission electron microscope (TEM) image of Ge grown on Si substrate, where the inset shows Ge atoms coherently matched up to the Si substrate on a lattice scale; and (b) top view SEM image of fabri‐ cated Ge *pin* photodetector device [51].

*pin* photodetector device [51]. The epitaxial growth in this two-step process is usually performed using a variant of the chemical vapor deposition (CVD) method. The most commonly employed variant is ultrahigh vacuum CVD (UHV-CVD) [53,75], in which the operating pressures are high enough to control oxygen background contamination levels. However, SiGe based devices have also been grown The epitaxial growth in this two-step process is usually performed using a variant of the chemical vapor deposition (CVD) method. The most commonly employed variant is ultrahigh vacuum CVD (UHV-CVD) [53,75], in which the operating pressures are high enough to control oxygen background contamination levels. However, SiGe based devi‐

using low-pressure CVD (LP-CVD) [74] more broadly utilized by industry [7], low-energy plasma-enhanced CVD (LEPE-CVD) [48], reduced pressure CVD (RP-CVD) [46], and rapid thermal CVD (RT-CVD) [40]. These CVD based methods enable high control of layer and multi-layer thickness and suitability for future large wafer-scale fabrication. The two-step process is likewise compatible with the molecular beam epitaxy (MBE) method, which has been employed in fewer but still a considerable number of instances [37,45,70,76]. Primary advantages of MBE are allowance of lower thermal budgets [66] and tight control over doping

27

In the first LT (slower growth rate) step of this low/high temperature growth process, fully planar homoepitaxial deposition of a thin Ge/SiGe seed or buffer layer on a Si wafer is performed to ensure smooth surface morphology and to avoid islanding of the film [10]. Si wafers with (100) orientation are associated with lower leakage currents than (001) oriented wafers [1]. The Ge seed layer is deposited on the surface of the substrate, which is often highly doped to facilitate the future requirement of low resistance ohmic contacts. This seed layer is designed to prevent

ces have also been grown using low-pressure CVD (LP-CVD) [74] more broadly utilized by industry [7], low-energy plasma-enhanced CVD (LEPE-CVD) [48], reduced pressure CVD (RP-CVD) [46], and rapid thermal CVD (RT-CVD) [40]. These CVD based methods enable high control of layer and multi-layer thickness and suitability for future large wafer-scale fabrication. The two-step process is likewise compatible with the molecular beam epitaxy (MBE) method, which has been employed in fewer but still a considerable number of instances [37,45,70,76]. Primary advantages of MBE are allowance of lower thermal budgets [66] and tight control over doping profiles [1].

#### **6.3. LT growth**

In the first LT (slower growth rate) step of this low/high temperature growth process, fully planar homoepitaxial deposition of a thin Ge/SiGe seed or buffer layer on a Si wafer is performed to ensure smooth surface morphology and to avoid islanding of the film [10]. Si wafers with (100) orientation are associated with lower leakage currents than (001) oriented wafers [1]. The Ge seed layer is deposited on the surface of the substrate, which is often highly doped to facilitate the future requirement of low resistance ohmic con‐ tacts. This seed layer is designed to prevent strain release from undesirable 3D island growth, reduce surface roughness, and enhance the migration of threading dislocations (Figure 20) to decrease their proliferation. Buffer/seed layer thicknesses in the range of 30-75 nm are most optimal to withstand the temperature ramp and homoepitaxially grow Ge films with smooth surface morphologies [77] with reduced threading dislocation densities [68]; for layers less than 30 nm thick, islanded surfaces have a tendency to form [74]. The first ~0.7 nm (i.e., below the critical thickness) of the buffer layer will be strained due to the 4.18% lattice mismatch between it and the underlying Si substrate, after which a progressive strain relaxation takes place, and a fully strain-relaxed Ge epilayer is pro‐ duced for growth beyond a few additional nanometers [66]. Therefore, this layer, assum‐ ing it is of sufficient thickness, is initially predominately relaxed.

The seed layer growth temperature influences adatom processes on the surface, crystalline growth, surface morphology, abruptness of doping transitions, and relaxation processes [68]. Temperatures employed for seed layer deposition are predominately in the 300-400°C range, and usually from 320-360°C [9]. Depositing seed layers at temperatures below 300°C can lead to crystallographic defect formation, while temperatures above 400°C have been found to produce surface roughening due to increased surface mobility of Ge [7]. At such relatively low growth temperatures, the low surface diffusivity of Ge kinetically suppresses undesired islanding that can otherwise result [10].

*In situ* doping (e.g., with boron) of this layer can be utilized to enhance the seed growth rate and lower the Ge/Si interfacial oxygen level [7]. Seed layer doping has been found to scale linearly with boron doping levels up to 1020 cm-3 [74]. It has also been determined to reduce series resistance under forward bias and lower dark current under reverse bias [63].

strain release from undesirable 3D island growth, reduce surface roughness, and enhance the migration of threading dislocations (Figure 20) to decrease their proliferation. Buffer/seed layer thicknesses in the range of 30-75 nm are most optimal to withstand the temperature ramp and homoepitaxially grow Ge films with smooth surface morphologies [77] with reduced threading dislocation densities [68]; for layers less than 30 nm thick, islanded surfaces have a tendency to form [74]. The first ~0.7 nm (i.e., below the critical thickness) of the buffer layer will be strained due to the 4.18% lattice mismatch between it and the underlying Si substrate, after which a progressive strain relaxation takes place, and a fully strain-relaxed Ge epilayer is produced for growth beyond a few additional nanometers [66]. Therefore, this layer, assuming

The seed layer growth temperature influences adatom processes on the surface, crystalline growth, surface morphology, abruptness of doping transitions, and relaxation processes [68]. Temperatures employed for seed layer deposition are predominately in the 300-400°C range, and usually from 320-360°C) [9]. Depositing seed layers at temperatures below 300°C can lead to

its final thickness is ~30 nm or greater, is initially predominately relaxed.

**Figure 20.** Cross-sectional TEM image of Ge layer grown on Si; (b) Enlargement of layer in (a) near the interface region, showing a high density of misfit dislocations; and (c) TEM image of the Ge layer grown following a two-step **Figure 20.** (a) Cross-sectional TEM image of Ge layer grown on Si; (b) enlargement of layer in (a) near the interface region, showing a high density of misfit dislocations; and (c) TEM image of the Ge layer grown following a two-step growth process, where threading dislocations are less evident [66].

growth process, where threading dislocations are less evident [66].

#### *In situ* doping (e.g., with boron) of this layer can be utilized to enhance the seed growth rate and **6.4. HT growth**

can otherwise result [10].

ces have also been grown using low-pressure CVD (LP-CVD) [74] more broadly utilized by industry [7], low-energy plasma-enhanced CVD (LEPE-CVD) [48], reduced pressure CVD (RP-CVD) [46], and rapid thermal CVD (RT-CVD) [40]. These CVD based methods enable high control of layer and multi-layer thickness and suitability for future large wafer-scale fabrication. The two-step process is likewise compatible with the molecular beam epitaxy (MBE) method, which has been employed in fewer but still a considerable number of instances [37,45,70,76]. Primary advantages of MBE are allowance of lower thermal budgets

In the first LT (slower growth rate) step of this low/high temperature growth process, fully planar homoepitaxial deposition of a thin Ge/SiGe seed or buffer layer on a Si wafer is performed to ensure smooth surface morphology and to avoid islanding of the film [10]. Si wafers with (100) orientation are associated with lower leakage currents than (001) oriented wafers [1]. The Ge seed layer is deposited on the surface of the substrate, which is often highly doped to facilitate the future requirement of low resistance ohmic con‐ tacts. This seed layer is designed to prevent strain release from undesirable 3D island growth, reduce surface roughness, and enhance the migration of threading dislocations (Figure 20) to decrease their proliferation. Buffer/seed layer thicknesses in the range of 30-75 nm are most optimal to withstand the temperature ramp and homoepitaxially grow Ge films with smooth surface morphologies [77] with reduced threading dislocation densities [68]; for layers less than 30 nm thick, islanded surfaces have a tendency to form [74]. The first ~0.7 nm (i.e., below the critical thickness) of the buffer layer will be strained due to the 4.18% lattice mismatch between it and the underlying Si substrate, after which a progressive strain relaxation takes place, and a fully strain-relaxed Ge epilayer is pro‐ duced for growth beyond a few additional nanometers [66]. Therefore, this layer, assum‐

The seed layer growth temperature influences adatom processes on the surface, crystalline growth, surface morphology, abruptness of doping transitions, and relaxation processes [68]. Temperatures employed for seed layer deposition are predominately in the 300-400°C range, and usually from 320-360°C [9]. Depositing seed layers at temperatures below 300°C can lead to crystallographic defect formation, while temperatures above 400°C have been found to produce surface roughening due to increased surface mobility of Ge [7]. At such relatively low growth temperatures, the low surface diffusivity of Ge kinetically suppresses undesired

*In situ* doping (e.g., with boron) of this layer can be utilized to enhance the seed growth rate and lower the Ge/Si interfacial oxygen level [7]. Seed layer doping has been found to scale linearly with boron doping levels up to 1020 cm-3 [74]. It has also been determined to reduce

series resistance under forward bias and lower dark current under reverse bias [63].

[66] and tight control over doping profiles [1].

342 Advances in Optical Fiber Technology: Fundamental Optical Phenomena and Applications

ing it is of sufficient thickness, is initially predominately relaxed.

islanding that can otherwise result [10].

**6.3. LT growth**

28 lower the Ge/Si interfacial oxygen level [7]. Seed layer doping has been found to scale linearly with boron doping levels up to 1020 cm-3 [74]. It has also been determined to reduce series resistance under forward bias and lower dark current under reverse bias [63]. **6.4 HT Growth**  In the subsequent HT step of the growth process, a layer of intrinsic Ge or SiGe serving as the *pin* detector absorption region is grown in the temperature range of 500-800°C above the relaxed buffer/seed layer. The growth temperatures utilized are most commonly in the 600-700°C range, which has been found to produce a satisfactory growth rate and sufficient degree of tensile strain while also providing a smooth high crystal quality Ge/SiGe film [10]. Using a layer composed In the subsequent HT step of the growth process, a layer of intrinsic Ge or SiGe serving as the *pin* detector absorption region is grown in the temperature range of 500-800°C above the relaxed buffer/seed layer. The growth temperatures utilized are most commonly in the 600-700°C range, which has been found to produce a satisfactory growth rate and sufficient degree of tensile strain while also providing a smooth high crystal quality Ge/SiGe film [10]. Using a layer composed of Ge (rather than SiGe) maximizes the potential cutoff wavelength of device, but high Ge content Si1-*x*Ge*x* (*x* ≥ 0.8) can likewise be effective. In general, as this *i*-Ge/SiGe layer is made thicker, the transit time increases which reduces the device bandwidth, while the responsivity rises due to higher absorption and junction capacitance is reduced [15]. However, topological and defect density concerns limit the *i*-layer thickness for practical *pin* devices to 2 μm or less [64]. The doping level of this intrinsic SiGe layer is typically three to four orders of magnitude lower than that of the highly doped *n*<sup>+</sup> and *p*<sup>+</sup> layers of a *pin* detector [76]. Upon cooling following the HT growth, this layer becomes strained due to the difference in the thermal expansion coefficients between the Ge/SiGe layer material and the Si substrate. In one instance the level of strain present after cooling was found to rise as the layer thickness increased up to ~150 nm, and then remain essentially constant as its thickness grew further [66].

#### **6.5. HT anneal**

Following the LT/HT growth steps, HT *in situ* annealing, often cyclic in nature, is usually performed. The cyclic annealing process enables a reduction in sessile threading dislocation density by transforming sessile threading dislocations to glissile ones, which due to thermal stress glide effectively annihilate dislocations [78]. This annealing process is intended to reduce the threading dislocation density by up to two orders of magnitude (e.g., from 109 to 107 cm-2 [9]) and thereby diminish resultant dark/leakage currents, and also to enhance the strain/stress of the *i*-Ge layer [48]. To have an optimal effect, the high anneal temperature is usually chosen to be marginally less than the Ge melting temperature (939°C), with the low temperature at least 50°C below high anneal temperature and above ambient [78]. Typical cyclic anneal temperatures span the 700-900°C range.

Cyclic annealing for up to 10 cycles compared to a single cycle was found in multiple cases to further reduce the dislocation density by a significant degree [70]. On the other hand, a single anneal cycle can result in lower boron diffusion out from the p+ SiGe layer while still main‐ taining acceptably low dislocation density [47]. High and low cyclic annealing durations are most commonly 10 min; however, a single anneal lasting up to 2 h has been found to be equally effective in certain cases [68]. As the anneal time increases, Ge/Si interdiffusion can become an issue and limit tensile strain [66]. An alternate approach involves a hydrogen ambient, by which annealing at ~800ºC for 30 min can effectively reduce surface roughness and threading dislocation density attributed to enhanced atomic mobility from the annealing [79].

#### **6.6. Subsequent fabrication steps**

degrading detector performance.

21(b).

**7.1 IR FPA and ROIC Technology**

**Figure 21.** (a) I-V characteristics for 10×10 μm<sup>2</sup>

Following selective two-step LT/HT growth and annealing, additional processing steps are required in the development of a practical Ge/SiGe *pin* photodetector device. The top contact of the detector can comprise a thin (100-200 nm) layer of polysilicon deposited on the intrinsic Ge/SiGe layer, *in situ* doped with phosphorus [53]. This forms the *n*<sup>+</sup> layer that provides a conductive path to the opposite site of the detector. Free-carrier absorption, which can be significant in Si at NIR wavelengths, was modeled using the Drude equation [18] for a polysilicon layer of 200 nm thickness with dopant concentration of 1019 cm-3, and was found to have an acceptably minor impact on performance. However, if the doping level is increased significantly the layer thickness will need to be reduced, and vice versa, in order to prevent free-carrier absorption from significantly degrading detector performance. thickness will need to be reduced, and vice versa, in order to prevent free‐carrier absorption from significantly

metallization anneal in N2; at -1 V, the dark current is reduced by ~1000X with 400°C by the annealing [24]. (b) Schematic showing composition of a prospective SiGe *pin* photodetector device after fabrication. Following deposition of the polysilicon layer, an activation anneal can be performed, which **Figure 21.** (a) I-V characteristics for 10×10 μm2 SiGe *pin* detector devices with and without 400°C post-metallization anneal in N2; at-1 V, the dark current is reduced by ~1000X with 400°C by the annealing [24]. (b) Schematic showing composition of a prospective SiGe *pin* photodetector device after fabrication.

SiGe *pin* detector devices with and without 400°C post-

serves to out-diffuse dopant atoms from the polysilicon layer into the underlying Ge/SiGe to form a vertical *pin* junction [63]. A passivation layer (e.g., of SiO2) may then be deposited at relatively low temperatures using a CVD based process, which serves to reduce leakage currents and isolate active elements [1]. This oxide layer can be patterned using a Following deposition of the polysilicon layer, an activation anneal can be performed, which serves to out-diffuse dopant atoms from the polysilicon layer into the underlying Ge/SiGe to form a vertical *pin* junction [63]. A passivation layer (e.g., of SiO2) may then be deposited at

photolithographic process to open a window to the underlying Si1-*x*Ge*x* surface. The next prospective step in this process, nearly completing the photodetector design, involves sputter depositing metal (e.g., aluminum or titanium) to form low resistance top and bottom contacts. Silicidation annealing may subsequently be performed at temperatures in the 600-900°C range to ensure highly conductive ohmic contacts enabling higher photocurrent [53]; this has also been observed to marginally increase the tensile strain in the Ge/SiGe layer [16]. Following this metallization process, the samples may be annealed in nitrogen, as shown in Figure 21(a), which has been found reduce dark current by up to three orders of magnitude for small area Ge/SiGe *pin* photodetectors [24]. A potential design layout of a fabricated SiGe *pin* photodetector device having undergone these processing steps is depicted in Figure

Because of the compatibility of Ge growth methods with standard silicon based CMOS processes, photodetectors developed through selective epitaxial growth of Ge/SiGe can be heterogeneously integrated with CMOS circuitry using manufacturing infrastructure already widely installed for the production of BiCMOS and CMOS integrated circuits. In addition, unlike charge‐coupled device (CCD) based imagers that require specialized and relatively complicated processing techniques, CMOS based imagers can be built on fabrication lines designed for commercial microprocessors. This has enabled the resolution of CMOS imagers to continue to increase rapidly due to the ongoing transition to finer lithographies as predicted by Moore's Law. This in turn has led to higher circuit density and levels of integration, better image quality, lower voltages, and lower overall system costs for

**7.0 Practical Integration SiGe Detectors for Imaging Arrays**

CMOS devices in comparison with traditional CCD based solutions [80].

relatively low temperatures using a CVD based process, which serves to reduce leakage currents and isolate active elements [1]. This oxide layer can be patterned using a photolitho‐ graphic process to open a window to the underlying Si1-*x*Ge*x* surface. The next prospective step in this process, nearly completing the photodetector design, involves sputter depositing metal (e.g., aluminum or titanium) to form low resistance top and bottom contacts. Silicidation annealing may subsequently be performed at temperatures in the 600-900°C range to ensure highly conductive ohmic contacts enabling higher photocurrent [53]; this has also been observed to marginally increase the tensile strain in the Ge/SiGe layer [16]. Following this metallization process, the samples may be annealed in nitrogen, as shown in Figure 21(a), which has been found reduce dark current by up to three orders of magnitude for small area Ge/SiGe *pin* photodetectors [24]. A potential design layout of a fabricated SiGe *pin* photode‐ tector device having undergone these processing steps is depicted in Figure 21(b).
