**7. Practical integration SiGe detectors for imaging arrays**

## **7.1. IR FPA and ROIC technology**

Cyclic annealing for up to 10 cycles compared to a single cycle was found in multiple cases to further reduce the dislocation density by a significant degree [70]. On the other hand, a single

taining acceptably low dislocation density [47]. High and low cyclic annealing durations are most commonly 10 min; however, a single anneal lasting up to 2 h has been found to be equally effective in certain cases [68]. As the anneal time increases, Ge/Si interdiffusion can become an issue and limit tensile strain [66]. An alternate approach involves a hydrogen ambient, by which annealing at ~800ºC for 30 min can effectively reduce surface roughness and threading

Following selective two-step LT/HT growth and annealing, additional processing steps are required in the development of a practical Ge/SiGe *pin* photodetector device. The top contact of the detector can comprise a thin (100-200 nm) layer of polysilicon deposited on the intrinsic

conductive path to the opposite site of the detector. Free-carrier absorption, which can be significant in Si at NIR wavelengths, was modeled using the Drude equation [18] for a polysilicon layer of 200 nm thickness with dopant concentration of 1019 cm-3, and was found to have an acceptably minor impact on performance. However, if the doping level is increased significantly the layer thickness will need to be reduced, and vice versa, in order to prevent free-carrier absorption from significantly degrading detector performance. thickness will need to be reduced, and vice versa, in order to prevent free‐carrier absorption from significantly

metallization anneal in N2; at -1 V, the dark current is reduced by ~1000X with 400°C by the annealing [24]. (b) Schematic showing composition of a prospective SiGe *pin* photodetector device after

Following deposition of the polysilicon layer, an activation anneal can be performed, which serves to out-diffuse dopant atoms from the polysilicon layer into the underlying Ge/SiGe to form a vertical *pin* junction [63]. A passivation layer (e.g., of SiO2) may then be deposited at relatively low temperatures using a CVD based process, which serves to reduce leakage currents and isolate active elements [1]. This oxide layer can be patterned using a photolithographic process to open a window to the underlying Si1-*x*Ge*x* surface. The next prospective step in this process, nearly completing the photodetector design, involves sputter depositing metal (e.g., aluminum or titanium) to form low resistance top and bottom contacts. Silicidation annealing may subsequently be performed at temperatures in the 600-900°C range to ensure highly conductive ohmic contacts enabling higher photocurrent [53]; this has also been observed to marginally increase the tensile strain in the Ge/SiGe layer [16]. Following this metallization process, the samples may be annealed in nitrogen, as shown in Figure 21(a), which has been found reduce dark current by up to three orders of magnitude for small area Ge/SiGe *pin* photodetectors [24]. A potential design layout of a fabricated SiGe *pin* photodetector device having undergone these processing steps is depicted in Figure

anneal in N2; at-1 V, the dark current is reduced by ~1000X with 400°C by the annealing [24]. (b) Schematic showing

Following deposition of the polysilicon layer, an activation anneal can be performed, which serves to out-diffuse dopant atoms from the polysilicon layer into the underlying Ge/SiGe to form a vertical *pin* junction [63]. A passivation layer (e.g., of SiO2) may then be deposited at

**7.0 Practical Integration SiGe Detectors for Imaging Arrays**

CMOS devices in comparison with traditional CCD based solutions [80].

Because of the compatibility of Ge growth methods with standard silicon based CMOS processes, photodetectors developed through selective epitaxial growth of Ge/SiGe can be heterogeneously integrated with CMOS circuitry using manufacturing infrastructure already widely installed for the production of BiCMOS and CMOS integrated circuits. In addition, unlike charge‐coupled device (CCD) based imagers that require specialized and relatively complicated processing techniques, CMOS based imagers can be built on fabrication lines designed for commercial microprocessors. This has enabled the resolution of CMOS imagers to continue to increase rapidly due to the ongoing transition to finer lithographies as predicted by Moore's Law. This in turn has led to higher circuit density and levels of integration, better image quality, lower voltages, and lower overall system costs for

SiGe *pin* detector devices with and without 400°C post-

SiGe *pin* detector devices with and without 400°C post-metallization

dislocation density attributed to enhanced atomic mobility from the annealing [79].

Ge/SiGe layer, *in situ* doped with phosphorus [53]. This forms the *n*<sup>+</sup>

SiGe layer while still main‐

layer that provides a

anneal cycle can result in lower boron diffusion out from the p+

344 Advances in Optical Fiber Technology: Fundamental Optical Phenomena and Applications

**6.6. Subsequent fabrication steps**

degrading detector performance.

fabrication.

21(b).

**7.1 IR FPA and ROIC Technology**

**Figure 21.** (a) I-V characteristics for 10×10 μm<sup>2</sup>

composition of a prospective SiGe *pin* photodetector device after fabrication.

**Figure 21.** (a) I-V characteristics for 10×10 μm2

(a) (b)

Because of the compatibility of Ge growth methods with standard silicon based CMOS processes, photodetectors developed through selective epitaxial growth of Ge/SiGe can be heterogeneously integrated with CMOS circuitry using manufacturing infrastructure already widely installed for the production of BiCMOS and CMOS integrated circuits. In addition, unlike charge-coupled device (CCD) based imagers that require specialized and relatively complicated processing techniques, CMOS based imagers can be built on fabrication lines designed for commercial microprocessors. This has enabled the resolution of CMOS imagers to continue to increase rapidly due to the ongoing transition to finer lithographies as predicted by Moore's Law. This in turn has led to higher circuit density and levels of integration, better image quality, lower voltages, and lower overall system costs for CMOS devices in comparison with traditional CCD based solutions [80].

The term *focal plane array* (FPA) refers to a 2D assemblage of individual detector pixels located at the focal plane of an imaging system [21]. FPAs convert optical images into electrical signals that can then be read out and processed and/or stored in digital format. Staring array FPAs, in which the associated optics serve solely to focus the visual image onto the detectors in the array, are scanned electronically usually using circuits integrated with the arrays. The electrical output from the array can be either an analog or digital signal, which in the latter case requires the inclusion of analog-to-digital conversion electronics. CMOS based silicon addressing circuits, the dominant technology for large scale arrays, are mature with respect to fabrication yield and attainment of near-theoretical sensitivity.

Readout integrated circuits (ROICs) enable a FPA to be fully functional by accumulating photocurrent from each pixel to provide parallel signal processing circuitry for readout. ROIC functions include pixel deselecting, antiblooming on each pixel, subframe imaging, and output preamplification [80]. In monolithically integrated ROICs, both detection of light and signal readout (multiplexing) is performed in the detector material in the spacing between the pixels rather than in an external readout circuit [75]. Advantages of this approach include reduced number of processing steps, increased yields, and reduced costs. Another common architecture for IR FPAs uses a hybrid based approach, in which the individual pixels are directly connected with readout electronics providing for multiplexing [21]. Some benefits of this method are the potential for near 100% fill factor, increased signal processing area, and the ability to optimize the detector and multiplexer independently.

**Figure 22.** Photograph and schematic of a focal plane array (FPA) consisting of a hybridized chip stack with readout integrated circuit (ROIC), pixel array, and microlens array [81].

ROICs comprise input cells or unit cells, which in the case of hybrid FPAs consist of the areas located directly under each pixel that are connected to the pixels through indium bumps that bond the aligned FPA and ROIC together [82]. This procedure allows multiplexing the signals from thousands of pixels onto a few output lines. FPAs can utilize either frontside illumination, where photons pass through the ROIC, or backside illumination, where photons pass through a transparent detector array substrate; the latter is often the most advantageous since ROICs typically have areas of metallization and other opaque regions that effectively reduce optical area of the structure [21]. ROICs are processed in standard commercial foundries, and can be custom designed to feature any type of circuit that will fit in the unit cells, though this space is often quite limited. Microlenses deposited above each pixel arrays concentrate incoming light into photosensitive regions, and thus offer a means of further improving sensitivity for devices having relatively low fill factors. A typical indium bonded hybrid architecture FPA utilizing a microlens array is depicted in Figure 22.

#### **7.2. Integration of SiGe technology in CMOS processes**

The progressing technological development of low dark current SiGe detector arrays has made possible the fabrication of high density large format SiGe NIR FPAs. The frontside illumination process flow shown sequentially in Figure 23 was developed by DRS Technologies and provides various potential steps for the processes for fabrication and integration of FPA pixels with SOI wafers [63]. In this process, the SOI wafers have a thin, high quality Si layer on top, and a buried oxide layer below. The detector *p*<sup>+</sup> base layer and intrinsic (*i*) layer are deposited by SiGe epitaxy (*Step 1*). Vias into SiGe are then etched by RIE, where the buried oxide layer provides the etch stop (*Step 2*). Next, an oxide layer is deposited to provide dielectric isolation for the via structure. Doped polysilicon deposition completes the top *n*<sup>+</sup> layer of the *pin* photodiode structure and provides a conductive path to the opposite site of the detector (*Step 3*). A Si handle is bonded to the detector wafer (*Step 4*) to provide support during the etching and thinning. The Si wafer is then etched (*Step 5*), where the buried oxide layer again provides an etch stop (selectivity > 1000:1). Next, vias are opened though the oxide to access the top *n* + detector layer and the *p*<sup>+</sup> base layer (*Step 6*). This step is followed by via metal fill. The detector wafer will then be ready for direct CMOS bonding to interconnects (*Step 7*); this enabling technology is associated with low temperatures, high density, ultra-small pitch, and pixel scale reductions. Following bonding, the handle wafer is removed (*Step 8*). Finally, a pixel isolation etch completes the detector array (*Step 9*).


rather than in an external readout circuit [75]. Advantages of this approach include reduced number of processing steps, increased yields, and reduced costs. Another common architecture for IR FPAs uses a hybrid based approach, in which the individual pixels are directly connected with readout electronics providing for multiplexing [21]. Some benefits of this method are the potential for near 100% fill factor, increased signal processing area, and the ability to optimize

**Figure 22.** Photograph and schematic of a focal plane array (FPA) consisting of a hybridized chip stack with readout

ROICs comprise input cells or unit cells, which in the case of hybrid FPAs consist of the areas located directly under each pixel that are connected to the pixels through indium bumps that bond the aligned FPA and ROIC together [82]. This procedure allows multiplexing the signals from thousands of pixels onto a few output lines. FPAs can utilize either frontside illumination, where photons pass through the ROIC, or backside illumination, where photons pass through a transparent detector array substrate; the latter is often the most advantageous since ROICs typically have areas of metallization and other opaque regions that effectively reduce optical area of the structure [21]. ROICs are processed in standard commercial foundries, and can be custom designed to feature any type of circuit that will fit in the unit cells, though this space is often quite limited. Microlenses deposited above each pixel arrays concentrate incoming light into photosensitive regions, and thus offer a means of further improving sensitivity for devices having relatively low fill factors. A typical indium bonded hybrid architecture FPA

The progressing technological development of low dark current SiGe detector arrays has made possible the fabrication of high density large format SiGe NIR FPAs. The frontside illumination process flow shown sequentially in Figure 23 was developed by DRS Technologies and provides various potential steps for the processes for fabrication and integration of FPA pixels with SOI wafers [63]. In this process, the SOI wafers have a thin, high quality Si layer on top,

base layer and intrinsic (*i*) layer are deposited

the detector and multiplexer independently.

346 Advances in Optical Fiber Technology: Fundamental Optical Phenomena and Applications

integrated circuit (ROIC), pixel array, and microlens array [81].

utilizing a microlens array is depicted in Figure 22.

and a buried oxide layer below. The detector *p*<sup>+</sup>

**7.2. Integration of SiGe technology in CMOS processes**

**Figure 23.** Process flow for fabrication of NIR front side illuminated SiGe FPA and CMOS ROIC for SiGe detection and imaging applications [63].

The first monolithic integration of Ge NIR photodetectors in a CMOS process that produced multichannel, high-speed optical receivers was reported by Masini *et al*. in 2007 [83]. With this approach, the Ge epitaxy step was integrated at the end of the frontend processing and before the contact module. RP-CVD deposition of Ge at a temperature of 350ºC without HT annealing was performed to avoid potential damage resulting from high temperature epitaxy. Since high temperatures are necessary for gate oxide growth, the Ge module was inserted after the gate processing. The integrated WC *pin* detectors, which are depicted with the Si CMOS circuit in Figure 24, operated at 1550 nm at a bandwidth of 10 Gb/s with sensitivity greater than-14 dBm.

**Figure 24.** Integration approach for monolithic fabrication of a Ge pin photodetector and Si CMOS circuit on a com‐ mon SOI platform [83].

In 2010, Ang *et al*. [19] developed and monolithically integrated highly efficient WC *pin* Geon-SOI photodetectors with a CMOS circuits. They utilized an "electronic-first, photonic-last" approach to avoid Ge degradation and cross contamination to fabricate both vertical and lateral devices, where the former were found to offer superior performance in relation to bandwidth and dark current density. A closely matched integrated CMOS inverter circuit was demon‐ strated capable of performing logic functions. A high temperature (800°C) prebake treatment was used before the Ge epitaxy growth, which was found to not have any observable detri‐ mental impact on the operation of the CMOS devices. The vertical *pin* detectors achieved a responsivity of 0.92 A/W at 1550 nm, QE of 73%, bandwidth of 11.3 GHz, and dark current of 0.57 μA. Figure 25(a) and (b) show the design of the evanescent coupled Ge photodetectors in vertical and lateral *pin* configurations, respectively, while Figure 25(c) shows the integration approach for monolithically fabricating the Ge *pin* photodetector and Si CMOS circuit.

detrimental impact on the operation of the CMOS devices. The vertical *pin* detectors achieved a responsivity of 0.92 A/W at 1550 nm, QE of 73%, bandwidth of 11.3 GHz, and dark current of 0.57 μA. Figure 25(a) and (b) show SiGe Based Visible-NIR Photodetector Technology for Optoelectronic Applications http://dx.doi.org/10.5772/59065 349

**Figure 24.** Integration approach for monolithic fabrication of a Ge *pin* photodetector and Si CMOS

In 2010, Ang *et al*. [19] developed and monolithically integrated highly efficient WC *pin* Ge‐on‐SOI photodetectors with a CMOS circuits. They utilized an "electronic‐first, photonic‐last" approach to avoid Ge degradation and cross contamination to fabricate both vertical and lateral devices, where the former were found to offer superior performance in relation to bandwidth and dark current density. A closely matched integrated CMOS inverter circuit was demonstrated capable of performing logic functions. A high temperature (800°C) prebake treatment was used before the Ge epitaxy growth, which was found to not have any observable

the design of the evanescent coupled Ge photodetectors in vertical and lateral *pin* configurations, respectively, while Figure

circuit on a common SOI platform [83].

**Figure 25.** (a) SEM micrograph showing design of evanescent coupled Ge photodetector featuring vertical *pin* configuration; (b) Ge photodetector design with lateral *pin* configuration; and (c) schematic showing "electronic-first and photonic-last" integration approach for monolithically fabricating the WC Ge *pin* photodetector and Si CMOS circuit on a common SOI platform [19]. **Figure 25.** (a) SEM micrograph showing design of evanescent coupled Ge photodetector featuring vertical *pin* configu‐ ration; (b) Ge photodetector design with lateral *pin* configuration; and (c) schematic showing "electronic-first and pho‐ tonic-last" integration approach for monolithically fabricating the WC Ge *pin* photodetector and Si CMOS circuit on a common SOI platform [19].

#### **7.3 Development of SiGe Detector Arrays for Imaging 7.3. Development of SiGe detector arrays for imaging**

The first monolithic integration of Ge NIR photodetectors in a CMOS process that produced multichannel, high-speed optical receivers was reported by Masini *et al*. in 2007 [83]. With this approach, the Ge epitaxy step was integrated at the end of the frontend processing and before the contact module. RP-CVD deposition of Ge at a temperature of 350ºC without HT annealing was performed to avoid potential damage resulting from high temperature epitaxy. Since high temperatures are necessary for gate oxide growth, the Ge module was inserted after the gate processing. The integrated WC *pin* detectors, which are depicted with the Si CMOS circuit in Figure 24, operated at 1550 nm at a bandwidth of 10 Gb/s with sensitivity greater than-14 dBm.

348 Advances in Optical Fiber Technology: Fundamental Optical Phenomena and Applications

**Figure 24.** Integration approach for monolithic fabrication of a Ge pin photodetector and Si CMOS circuit on a com‐

In 2010, Ang *et al*. [19] developed and monolithically integrated highly efficient WC *pin* Geon-SOI photodetectors with a CMOS circuits. They utilized an "electronic-first, photonic-last" approach to avoid Ge degradation and cross contamination to fabricate both vertical and lateral devices, where the former were found to offer superior performance in relation to bandwidth and dark current density. A closely matched integrated CMOS inverter circuit was demon‐ strated capable of performing logic functions. A high temperature (800°C) prebake treatment was used before the Ge epitaxy growth, which was found to not have any observable detri‐ mental impact on the operation of the CMOS devices. The vertical *pin* detectors achieved a responsivity of 0.92 A/W at 1550 nm, QE of 73%, bandwidth of 11.3 GHz, and dark current of 0.57 μA. Figure 25(a) and (b) show the design of the evanescent coupled Ge photodetectors in vertical and lateral *pin* configurations, respectively, while Figure 25(c) shows the integration approach for monolithically fabricating the Ge *pin* photodetector and Si CMOS circuit.

mon SOI platform [83].

IR FPAs have traditionally been based on conventional materials utilized for IR detection including HgCdTe, InSb, InGaAs, and VOx [64]. SiGe FPAs for NIR detection are relatively new to the scene. SiGe based FPAs with associated ROICs can leverage low-voltage, deeply scaled, nanometer class IC processes that enable high yield of lowpower, high-component density designs with large dynamic, on-chip digital image processing (for SWaP-efficient sensor designs) and high-speed readouts. A common objective is to produce large format NIR FPAs that are very compact. Colace *et al*. in 2007 [6] demonstrated an optoelectronic chip incorporating a fully functional 2D array of 512 polycrystalline heterojunction Ge pixels integrated on CMOS electronics and operating in the NIR. The ROIC was serial and made use of an 8-bit data bus and 9-bit address bus. In order to compensate for a significant level of dark current, the chip was equipped with offset control and a dark current cancellation circuit. It also featured addressing and signal processing electronics IR FPAs have traditionally been based on conventional materials utilized for IR detection including HgCdTe, InSb, InGaAs, and VOx [64]. SiGe FPAs for NIR detection are relatively new to the scene. SiGe based FPAs with associated ROICs can leverage low-voltage, deeply scaled, nanometer class IC processes that enable high yield of low-power, high-component density designs with large dynamic, on-chip digital image processing (for SWaP-efficient sensor designs) and high-speed readouts. A common objective is to produce large format NIR FPAs that are very compact.

including 64 analog-to-digital converters. This integrated circuit, which operated up to and above 1550 nm, was found to exhibit good photoresponse and could acquire simple images. The chip, its architecture, and its cross-section are illustrated in Figure 26. Colace *et al*. in 2007 [6] demonstrated an optoelectronic chip incorporating a fully functional 2D array of 512 polycrystalline heterojunction Ge pixels integrated on CMOS electronics and operating in the NIR. The ROIC was serial and made use of an 8-bit data bus and 9-bit address bus. In order to compensate for a significant level of dark current, the chip was equipped with offset control and a dark current cancellation circuit. It also featured addressing and signal processing electronics including 64 analog-to-digital converters. This integrated circuit, which operated up to and above 1550 nm, was found to exhibit good photoresponse and could acquire simple images. The chip, its architecture, and its cross-section are illustrated in Figure 26.

**Figure 26.** (a) Photograph of optoelectronic chip featuring 2D Ge photodetector array, showing zoomedin images of a portion of the array; (b) chip architecture, comprising readout electronics; and (c) photograph of individual pixel [6]. In 2010 Vu *et al*. [75] developed arrays of both vertical and lateral *pin* photodetectors that were integrated into **Figure 26.** (a) Photograph of optoelectronic chip featuring 2D Ge photodetector array, showing zoomed-in image of a portion of the array; (b) chip architecture, comprising readout electronics; and (c) photograph of individual pixel [6]. (b)

electronic‐photonic FPAs. Layers of metal were employed to connect the detector electrodes to transimpedance amplifiers and CMOS circuits, and light signals were then coupled from waveguides or inserted directly into the side of the Ge intrinsic layer via optical fibers. A responsivity of 1.11 A/W at 1550 nm, bandwidth of 15 GHz, and dark current density on the order of 100 nA/cm2 were achieved for the NI photodetectors. The integrated chips were produced in a standard CMOS foundry, where the fabrication processes was optimized for manufacturability. In 2010 Vu *et al*. [75] developed arrays of both vertical and lateral *pin* photodetectors that were integrated into electronic-photonic FPAs. Layers of metal were employed to connect the detector electrodes to transimpedance amplifiers and CMOS circuits, and light signals were then coupled from waveguides or inserted directly into the side of the Ge intrinsic layer via optical fibers. A responsivity of 1.11 A/W at 1550 nm, bandwidth of 15 GHz, and dark current density on the order of 100 nA/cm2 were achieved for the NI photodetectors. The integrated chips were produced in a standard CMOS foundry, where the fabrication processes was optimized for manufacturability. **Figure 26.** (a) Photograph of optoelectronic chip featuring 2D Ge photodetector array, showing zoomedin images of a portion of the array; (b) chip architecture, comprising readout electronics; and (c) photograph of individual pixel [6]. In 2010 Vu *et al*. [75] developed arrays of both vertical and lateral *pin* photodetectors that were integrated into electronic‐photonic FPAs. Layers of metal were employed to connect the detector electrodes to transimpedance amplifiers and CMOS circuits, and light signals were then coupled from waveguides or inserted directly into the side of the Ge intrinsic layer via optical fibers. A responsivity of 1.11 A/W at 1550 nm, bandwidth of 15 GHz, and dark current density on the order of 100 nA/cm2 were achieved for the NI photodetectors. The integrated chips were produced in a standard CMOS foundry, where the fabrication processes was optimized for

**8.0 Optoelectronic Properties of Si/Ge Based Nanostructures Figure 27.** (a) Schematic cross-section, and (b) top view, of a linear photodetector array consisting of 16 detectors [84]. In 2014, Chong *et al.* [84] reported a parallel system of 16 element *pin* photodetector arrays, shown in Figure 27, for parallel optical interconnect applications. The detectors comprised Ge absorption layers epitaxially grown on **Figure 27.** (a) Schematic cross-section, and (b) top view, of a linear photodetector array consisting of 16 detectors [84].

a SOI substrate by UHV‐CVD using the two‐step LT/HT growth process, and incorporated a plasma etched double mesa vertical structure to reduce parasitic capacitance. The array featured responsivities of 0.38 and 0.23 A/W at 1310 and 1550 nm, respectively, with a very low dark current density of ~5 mA/cm2 with no applied bias

**8.1 Quantum Confinement and Strain in Si/Ge Nanostructures**

**8.0 Optoelectronic Properties of Si/Ge Based Nanostructures**

**8.1 Quantum Confinement and Strain in Si/Ge Nanostructures**

and a bandwidth of up to 8 GHz.

(a)

In 2014, Chong *et al.* [84] reported a parallel system of 16 element *pin* photodetector arrays, shown in Figure 27, for parallel optical interconnect applications. The detectors comprised Ge absorption layers epitaxially grown on a SOI substrate by UHV-CVD using the two-step LT/HT growth process, and incorporated a plasma etched double mesa vertical structure to reduce parasitic capacitance. The array featured responsivities of 0.38 and 0.23 A/W at 1310 and 1550 nm, respectively, with a very low dark current density of ~5 mA/cm2 with no applied bias and a bandwidth of up to 8 GHz.
