**Code Generation From MATLAB – Simulink Models**

Tiago da Silva Almeida, Ian Andrew Grout and Alexandre César Rodrigues da Silva

Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/57575

**1. Introduction**

[2] Mauderer A., Oetjens J.H. System-level design of mixed-signal ASICs using Simu‐ link: Efficient transitions to EDA environments. EETimes; 2012. http://

[3] Erkkinen T., Breiner S. Automatic Code Generation–Technology Adoption Lessons Learned from Commercial Vehicle Case Studies. The MathWorks; 08AE-22; 2007.

[7] Meyer-Baese U. Digital Signal Processing with Field Programmable Gate Arrays.

[8] Harris F.J. Multirate Signal Processing for Communication Systems. Prentice Hall;

[9] Newbold R. Practical applications in digital signal processing. Prentice Hall; 2013.

[10] Hogenauer E.B. An Economical Class of Digital Filters for Decimation and Interpola‐ tion. IEEE Transactions on Acoustics, Speech and Signal Processing, ASSP-29(2);

[4] MathWorks. DSP System Toolbox Reference. The MathWorks; 2012.

[5] MathWorks. Simulink User's Guide. The MathWorks; 2012.

[6] MathWorks. HDL Coder User's Guide. The MathWorks; 2012.

[11] Higgins J.H. Digital signal processing in VLSI. Prentice Hall; 1990.

www.eetimes.com/General/PrintView/4373903

Springer; 2001.

418 MATLAB Applications for the Practical Engineer

1981. 155–162.

2004.

Nowadays, computational tools are indispensable in the design of electronic circuits due to the increase in complexity of electronic circuits and the need to manage large amounts of related data to design. The development of new methodologies and tools has become a strategic area in the development of new technologies, in particular the development of CAD (Computer Aided Design) tools. CAD tools can be best understood as design information management systems, along with the creation of graphic based input and simulations of the designs are created. These simulations can be used, shared, published, republished and reused in different formats, scales and levels of detail.

But with so many studies involving different methodologies and computational tools, in [1], it was proposed to form a classification model for design and tools at the Electronic System Level (ESL) of design abstraction. This chapter details the characteristics and approaches that differ between computational tools of design, for modeling at level hardware and software. Figure 1 illustrates the design flow in different levels of abstraction. The design flow, called the Double Roof Model, is considered by [1] as an extended version of the Y diagram presented by [2][3]. However, there are still problems of incompatibility between designs the tools and this identifies a number of weaknesses.

Figure 1 shows the process of designing the top-down methodology in an ideal way. The left side corresponds to the process of software creation, while the right side corresponds to the process of hardware creation. Each side is divided into different levels of abstraction, e.g., Task and Instruction (software) or Components and Logic (hardware). There is a common level of abstraction, named ESL. In this level, we cannot distinguish between hardware and software. At each level, we can run a synthesis step (continuous vertical arrow) and the specification is transformed into an implementation. Horizontal dotted arrows indicate the steps which we

© 2014 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

can change the models of individual elements in the implementation directly to the next level of abstraction (lower level abstraction).

As case study designs, the digital-to-analog converters (DAC) design was used to explain the

another. The ADC (analog to digital converter) is used to convert analog signals to digital data. The digital to analogue converter works in the opposite manner to the ADC, converting digital

Considering the DAC operation, *n* binary input bits (which can be considered as representing the binary code of a decimal value) are received and there are 2n possible combinations of binary input. There is also an additional input to the circuit design that is used as a reference signal, represented by Vref and the reference is a voltage level, which is used to determine the maximum value that converter can generate on its output. The analog value is generated by the weighted sum of *n* inputs, multiplied by the reference voltage. Inputs are weighted according to magnitude of each bit, where *n* is the magnitude of input bit, *x* is total number of inputs, and *b* is DAC input value contained in the bit of *n* magnitude, where bn ∈ {0,1}, as

> 1 1 2

multiplying the result of Equation (1) by the reference voltage to obtain:

on positions of switches that are controlled by inputs [5].

determined by the output set of variables *{M1, M2, …,Mm}*.

HDL and SF2

Using Equation (1), the analogue output voltage from the data converter is obtained by

There are several methods possible to implement the DAC operation (i.e., there are several different DAC design architectures possible). One common method used is R/2R ladder circuit, where only two values for resistors in circuit are used (R and 2R), and output current depends

state machine [6]. HDB3 line code, which is a technique for detecting synchronism with bipolar signaling, and it has been used over the years in digital systems. A finite state machine can be represented by state diagrams. State diagrams are used to graphically represent a state transition functions set. Having an input event set, the output event set and the next state set

There are also several other forms to represent finite state machine that differ slightly and have different semantic. The State Transition Table and Petri Net are two examples. Figure 2 shows generic schematic of a finite state machine. The circuit has a finite number of inputs, repre‐ senting all input variable set *{N1, N2, …,Nn}*. Thus, the circuit has a finite number *m* of outputs,

*x P n <sup>n</sup> <sup>n</sup> V b* =

data input to analogue signal output proportional to value of input digital.

XML. Data converters are circuits that transform a given representation to

<sup>=</sup> å (1)

Code Generation From MATLAB – Simulink Models

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421

*V VV out P ref* = ´ (2)

XML, we used a HDB3 (High Density Bipolar 3) finite

MS2

SV and BD2

described in:

To explain the use of SF2

can be determined.

**Figure 1.** Flow design of electronic systems, also known as Double Roof Model.

In this chapter, we present a methodology for ESL designs based in four computational tools. The first one is the SF2 HDL tool (Stateflow to Hardware Description Language or transition states table). The SF2 HDL has the ability to convert models of finite state machine (FSM) in Stateflow / Simulink in a corresponding description in VHDL, Verilog or even a text file with a state transition table. The descriptions in the VHDL and Verilog languages are generated at the behavioral abstraction level for the finite state machine. The second computational tool, called MS2 SV (MATLAB / Simulink to SystemVision), is able to generate descriptions in VHDL-AMS from models described in Simulink and all of model structure design for simulation in SystemVision environment from Mentor Graphics. The descriptions are generated in VHDL-AMS since even in the standard Simulink toolbox. there are many components with different signal representations of a purely digital representation. The third computational tool developed, called BD2 XML (Block Diagram to XML), is able to generate a textual representation of the architecture of this model in XML markup language, also from models described in Simulink. XML was chosen for its applicability and it can be used as object code by other tools. The fourth and last computational tool described works together with BD2 XML and it is similar to SF2 HDL. The tool, called SF2 XML (Stateflow to XML), is able to capture the relevant information in the Stateflow file and generate a corresponding description in XML. The file resulting from the conversion is according to the standard of XML structure called SCXML (StateChart XML) proposed by the W3C [4].

For acceptance in the community of software development, maintainability and practicality, we chose to develop the translation environment using an object-oriented approach. For robustness, the C++language was chosen. With C++ language is possible create linear and nonlinear data structure, and languages like Java, it is not possible do it. In our tools, we used liner lists to store dynamically the data in memory. Thus, C++language is a better choice for programming language. Another reason for this choice, it is the common features between methods were coupled to objects, so there was created a logical interaction with low repre‐ sentational gap.

As case study designs, the digital-to-analog converters (DAC) design was used to explain the MS2 SV and BD2 XML. Data converters are circuits that transform a given representation to another. The ADC (analog to digital converter) is used to convert analog signals to digital data. The digital to analogue converter works in the opposite manner to the ADC, converting digital data input to analogue signal output proportional to value of input digital.

can change the models of individual elements in the implementation directly to the next level

In this chapter, we present a methodology for ESL designs based in four computational tools.

Stateflow / Simulink in a corresponding description in VHDL, Verilog or even a text file with a state transition table. The descriptions in the VHDL and Verilog languages are generated at the behavioral abstraction level for the finite state machine. The second computational tool,

AMS from models described in Simulink and all of model structure design for simulation in SystemVision environment from Mentor Graphics. The descriptions are generated in VHDL-AMS since even in the standard Simulink toolbox. there are many components with different signal representations of a purely digital representation. The third computational tool

of the architecture of this model in XML markup language, also from models described in Simulink. XML was chosen for its applicability and it can be used as object code by other tools.

information in the Stateflow file and generate a corresponding description in XML. The file resulting from the conversion is according to the standard of XML structure called SCXML

For acceptance in the community of software development, maintainability and practicality, we chose to develop the translation environment using an object-oriented approach. For robustness, the C++language was chosen. With C++ language is possible create linear and nonlinear data structure, and languages like Java, it is not possible do it. In our tools, we used liner lists to store dynamically the data in memory. Thus, C++language is a better choice for programming language. Another reason for this choice, it is the common features between methods were coupled to objects, so there was created a logical interaction with low repre‐

The fourth and last computational tool described works together with BD2

SV (MATLAB / Simulink to SystemVision), is able to generate descriptions in VHDL-

HDL tool (Stateflow to Hardware Description Language or transition

HDL has the ability to convert models of finite state machine (FSM) in

XML (Block Diagram to XML), is able to generate a textual representation

XML (Stateflow to XML), is able to capture the relevant

XML and it is similar

of abstraction (lower level abstraction).

420 MATLAB Applications for the Practical Engineer

The first one is the SF2

states table). The SF2

developed, called BD2

HDL. The tool, called SF2

(StateChart XML) proposed by the W3C [4].

called MS2

to SF2

sentational gap.

**Figure 1.** Flow design of electronic systems, also known as Double Roof Model.

Considering the DAC operation, *n* binary input bits (which can be considered as representing the binary code of a decimal value) are received and there are 2n possible combinations of binary input. There is also an additional input to the circuit design that is used as a reference signal, represented by Vref and the reference is a voltage level, which is used to determine the maximum value that converter can generate on its output. The analog value is generated by the weighted sum of *n* inputs, multiplied by the reference voltage. Inputs are weighted according to magnitude of each bit, where *n* is the magnitude of input bit, *x* is total number of inputs, and *b* is DAC input value contained in the bit of *n* magnitude, where bn ∈ {0,1}, as described in:

$$V\_p = \sum\_{n=1}^{\infty} \frac{1}{2^n} b\_n \tag{1}$$

Using Equation (1), the analogue output voltage from the data converter is obtained by multiplying the result of Equation (1) by the reference voltage to obtain:

$$V\_{out} = V\_P \times V\_{ref} \tag{2}$$

There are several methods possible to implement the DAC operation (i.e., there are several different DAC design architectures possible). One common method used is R/2R ladder circuit, where only two values for resistors in circuit are used (R and 2R), and output current depends on positions of switches that are controlled by inputs [5].

To explain the use of SF2 HDL and SF2 XML, we used a HDB3 (High Density Bipolar 3) finite state machine [6]. HDB3 line code, which is a technique for detecting synchronism with bipolar signaling, and it has been used over the years in digital systems. A finite state machine can be represented by state diagrams. State diagrams are used to graphically represent a state transition functions set. Having an input event set, the output event set and the next state set can be determined.

There are also several other forms to represent finite state machine that differ slightly and have different semantic. The State Transition Table and Petri Net are two examples. Figure 2 shows generic schematic of a finite state machine. The circuit has a finite number of inputs, repre‐ senting all input variable set *{N1, N2, …,Nn}*. Thus, the circuit has a finite number *m* of outputs, determined by the output set of variables *{M1, M2, …,Mm}*.

**Figure 2.** Schematic of a Finite State Machine.

The value in each memory element is called a state variable, and the set denoted by *{K1, K2, …,Kk}* form the state variable set. The values contained in *k* memory elements define the internal state of finite state machine. The outputs *{M1, M2 …,Mm}* and internal transition functions *{S1, S2, …, Ss}* depend on external inputs (input functions) and internal states (state functions) of state machine and they are defined by combinational circuits. The values *S*, which appear in the role of state transitions of machine at time *t*, determine values of state variables at time *t +1* and therefore define the next state of machine.

The state transition diagram or the state transition table makes the relationship between present state, next state, input and output.

The finite state machines that determine the next state *K(t+1)* only in the present state *K(t)* and present input *N(t)* are called deterministic machines or Markovian. Deterministic machines can be represented by the following equation:

$$K(t+1) = f[K(t), N(t)] \tag{3}$$

of memory to store and to identify four successive 0. After this, it was necessary to use a flipflop to store the polarity of the pulse (0 for+or 1 for-), and finally other flip-flop to store the polarity of the violation. The encoder requests a minimum of 25=32 states. The state 00 represents the initial state of the machine, and the two pairs of state 07 and 0F (in the left) and 1F and 17 (in the right) represent the description AMI, what causes the alternate code between

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423

Project-level electronic systems, also known as ESL (Electronic System Level), require much effort designer. The first work to classify the steps involved in system design at a high level of

Some studies deal with design optimization or minimization, for example the work in paper [8]. This work explored the computational complexity of logic minimization problem on two levels for digital circuit designs. In [9] was developed a genetic algorithm for synthesis of multicore architectures. The target system was an implementation of Petri net. In [10] was presented a method of re-engineering the FSM by rebuilding it with a different topology, but with equivalent functionality. The method is mainly concerned with power consumption of the finite state machine and uses a genetic algorithm to find the best solution. This approach

The representation of electronic systems by means of the FSM facilitates verification of the system and formal methodologies can be developed to assist in the synthesis process. In [11] was presented a tool capable to translate a FSM described in the VHDL. The focus of the work was modeling and the verification. In [12] was developed a conceptual mathematical model

facilitates the process of synthesis for optimal implementations of the system.

abstraction [2] subsequently refined to a more current [1] and [3].

**Figure 3.** State transition diagram for HDB3 line code.

+1 and-1 [6].

**2. Related research**

Where, *f* is a state transition function. The value of output M(t) is obtained through of two ways:

$$M(t) = \mathbb{S}[K(t)] \tag{4}$$

or,

$$M(t) = \mathcal{g}[K(t), N(t)] \tag{5}$$

where, *g* is an output function.

A finite state machine with properties described in Equations (3) and (4) is called Moore model and a machine described by equations (3) and (5) is called Mealy model [7].

To illustrate the state transition diagram, Figure 3 shows a state transition diagram of HDB3 code line, in hexadecimal representation as proposed in [6]. The encoder needed three parts of memory to store and to identify four successive 0. After this, it was necessary to use a flipflop to store the polarity of the pulse (0 for+or 1 for-), and finally other flip-flop to store the polarity of the violation. The encoder requests a minimum of 25=32 states. The state 00 represents the initial state of the machine, and the two pairs of state 07 and 0F (in the left) and 1F and 17 (in the right) represent the description AMI, what causes the alternate code between +1 and-1 [6].

### **2. Related research**

**Figure 2.** Schematic of a Finite State Machine.

422 MATLAB Applications for the Practical Engineer

*+1* and therefore define the next state of machine.

present state, next state, input and output.

can be represented by the following equation:

ways:

or,

where, *g* is an output function.

The value in each memory element is called a state variable, and the set denoted by *{K1, K2, …,Kk}* form the state variable set. The values contained in *k* memory elements define the internal state of finite state machine. The outputs *{M1, M2 …,Mm}* and internal transition functions *{S1, S2, …, Ss}* depend on external inputs (input functions) and internal states (state functions) of state machine and they are defined by combinational circuits. The values *S*, which appear in the role of state transitions of machine at time *t*, determine values of state variables at time *t*

The state transition diagram or the state transition table makes the relationship between

The finite state machines that determine the next state *K(t+1)* only in the present state *K(t)* and present input *N(t)* are called deterministic machines or Markovian. Deterministic machines

Where, *f* is a state transition function. The value of output M(t) is obtained through of two

A finite state machine with properties described in Equations (3) and (4) is called Moore model

To illustrate the state transition diagram, Figure 3 shows a state transition diagram of HDB3 code line, in hexadecimal representation as proposed in [6]. The encoder needed three parts

and a machine described by equations (3) and (5) is called Mealy model [7].

*Kt f Kt Nt* ( 1) [ ( ), ( )] + = (3)

*Mt gKt* ( ) [ ( )] = (4)

*Mt gKt Nt* ( ) [ ( ), ( )] = (5)

Project-level electronic systems, also known as ESL (Electronic System Level), require much effort designer. The first work to classify the steps involved in system design at a high level of abstraction [2] subsequently refined to a more current [1] and [3].

**Figure 3.** State transition diagram for HDB3 line code.

Some studies deal with design optimization or minimization, for example the work in paper [8]. This work explored the computational complexity of logic minimization problem on two levels for digital circuit designs. In [9] was developed a genetic algorithm for synthesis of multicore architectures. The target system was an implementation of Petri net. In [10] was presented a method of re-engineering the FSM by rebuilding it with a different topology, but with equivalent functionality. The method is mainly concerned with power consumption of the finite state machine and uses a genetic algorithm to find the best solution. This approach facilitates the process of synthesis for optimal implementations of the system.

The representation of electronic systems by means of the FSM facilitates verification of the system and formal methodologies can be developed to assist in the synthesis process. In [11] was presented a tool capable to translate a FSM described in the VHDL. The focus of the work was modeling and the verification. In [12] was developed a conceptual mathematical model for automatic checking of the FSM by observing the outputs of this particular FSM, allowing checking faulty behavior.

the expression representation and inference using multiple inputs can reduce the computation

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425

In [24] was proposed an algorithm for identifying flowcharts structure. Twelve structures were identified and then the algorithm was used to generate the code flowchart identified using recursion. The technologies and algorithms were used in an integrated development platform. [25] presented an approach of output bit selection based on counter for output response compaction in test systems observable. The hardware implementation requires only a counter and a multiplexer. Thus, the complexity was reduced and the control area was simplified. Furthermore, a change in the ATPG (Automatic Test Pattern Generation) tool was not required. Two output selection algorithms have been developed in several operations which counters

In [26] was discussed some work and the importance of developing CAD tools for the synthesis and design of systems and multi-core architectures, highlighting the importance of multi-core optimized and efficient resource allocation. [27] presented revised performance measures of some data type converters ADC (Analog-to-Digital Converter), such as SNR (Signal to Noise Ratio), SINAD (Signal to Noise Ratio and Distortion), SFDR (Spurious free Dynamic Range), THD (Total Harmonic Distortion) and ENOB (Effective Number of Bits). These metrics were analyzed with the case study of an ideal 14-bit converter in MATLAB and a converter with 12-

In [28] was presented a methodology for genetic optimization based on VHDL-AMS for Fuzzy Logic controllers. The fuzzy logic controller was used for modeling work in automotive systems in mixed physical domain. A genetic algorithm was developed and simulated in

**HDL**

HDL tool is a simplified graphical interface that allows

HDL is a computational tool capable to convert a state transition diagram into a

hardware description language description. This diagram is described in the Stateflow environment [29]. The Stateflow is toolbox inside Simulink is used to simulate finite state

the user to select between generate (i) an input file to be processed by TABELA program and (ii) a.*vhd* file with a behavioral VHDL description obtained directly from state transition

The TABELA program was developed for synthesize of a finite state machine and was implemented in Pascal language by researchers from UNICAMP [7] (Universidade Estadual de Campinas-Brazil). The program generates combinational functions that implement the finite machine described by state transition table. The transition functions and output functions are minimized and the cost of minimization using minterms and maxterms [7]. The transitions are specified on table form using one line per state transition, so: present state, next state, input, output. The description end is represented by notation "-100". Figure 4 shows the standard file

SystemVision environment, is employed in the generation of rough fuzzy sets.

of memristor implementation.

bit commercial manufactured by Analog Devices.

**3. Generation code methodology of SF2**

machines in different contexts. The SF2

for TABELA program input.

can be employed.

The SF2

diagram.

Hardware description languages (HDLs) are widely used in the design of electronic systems and also represent a major means for simulation and project documentation. In [13] was developed an algorithm for automatic generation of analog circuit models for modeling faults in the circuit at a high level. In [14] was developed a methodology for implementing FFT (Fast Fourier Transform) processors in reprogrammable devices using VHDL. In [15] was developed the architecture for implementing a SPICE (Simulation Program with Integrated Circuit Emphasis) simulator using an FPGA (Field Programmable Gate Array)

In [16] the authors proposed a simulator for the VHDL-AMS (Analog and Mixed Signal) language developed in the MATLAB environment. The tool was compared with others simulators available commercially. Another example that can be cited is the tool called SF2VHD, presented in [17]. That tool is capable to translate hierarchical models of finite states machine, modeled in the Stateflow environment, in a code corresponding structural VHDL.

In the work described in [18] was developed a tool called Sim2HDL, which accomplishes the automatic translation of Simulink models in a hardware description language in the attempt to drastically reduce the project time. The generated language can be VHDL or Verilog, at a behavioral level description, and the system can be implemented in FPGAs using commercial synthesizers.

Some commercial modeling tools incorporate the translation need for different forms of modeling. An example is a MATLAB C Compiler tool, developed by Mathworks. That tool translates programs written in MATLAB for a corresponding program in the C language. The functionality and main advantages of these tools are described in [19].

In [20] was proposed an approach to automatic synthesis of additional decoders. The method attempts to find and remove cases where there are no equivalent decoders. To discover all decoders that can exist simultaneously, an algorithm based on functional dependency has also been proposed. To select the correct decoder another algorithm is used to infer formula of each decoder precondition.

In [21] was developed a framework for the synthesis of electronic systems at a high level based on abstract finite state machines. The framework called synASM is capable of generating a CDFG (Control Data Flow Graph) from hardware descriptions based on C language. The authors extended the definitions of abstract state machines to support the parallelism and timing. After generating the CDFG extended, it was possible the automatic generation of optimizable hardware descriptions in VHDL and implementation in a FPGA.

In [22] was presented a complete approach decoder for communication systems. The model‐ ling was based on finite state machines and the method was capable of identifying whether decode exists or not, by observing the input sequence and output of encoder. [23] presented a method of representation and synthesis of Boolean expressions recursively. The method performs a sequence of operations with denial implications using two memristors. With the method, it was proved that it was possible to reduce the number of necessary implications for the expression representation and inference using multiple inputs can reduce the computation of memristor implementation.

In [24] was proposed an algorithm for identifying flowcharts structure. Twelve structures were identified and then the algorithm was used to generate the code flowchart identified using recursion. The technologies and algorithms were used in an integrated development platform. [25] presented an approach of output bit selection based on counter for output response compaction in test systems observable. The hardware implementation requires only a counter and a multiplexer. Thus, the complexity was reduced and the control area was simplified. Furthermore, a change in the ATPG (Automatic Test Pattern Generation) tool was not required. Two output selection algorithms have been developed in several operations which counters can be employed.

In [26] was discussed some work and the importance of developing CAD tools for the synthesis and design of systems and multi-core architectures, highlighting the importance of multi-core optimized and efficient resource allocation. [27] presented revised performance measures of some data type converters ADC (Analog-to-Digital Converter), such as SNR (Signal to Noise Ratio), SINAD (Signal to Noise Ratio and Distortion), SFDR (Spurious free Dynamic Range), THD (Total Harmonic Distortion) and ENOB (Effective Number of Bits). These metrics were analyzed with the case study of an ideal 14-bit converter in MATLAB and a converter with 12 bit commercial manufactured by Analog Devices.

In [28] was presented a methodology for genetic optimization based on VHDL-AMS for Fuzzy Logic controllers. The fuzzy logic controller was used for modeling work in automotive systems in mixed physical domain. A genetic algorithm was developed and simulated in SystemVision environment, is employed in the generation of rough fuzzy sets.

#### **3. Generation code methodology of SF2 HDL**

for automatic checking of the FSM by observing the outputs of this particular FSM, allowing

Hardware description languages (HDLs) are widely used in the design of electronic systems and also represent a major means for simulation and project documentation. In [13] was developed an algorithm for automatic generation of analog circuit models for modeling faults in the circuit at a high level. In [14] was developed a methodology for implementing FFT (Fast Fourier Transform) processors in reprogrammable devices using VHDL. In [15] was developed the architecture for implementing a SPICE (Simulation Program with Integrated Circuit

In [16] the authors proposed a simulator for the VHDL-AMS (Analog and Mixed Signal) language developed in the MATLAB environment. The tool was compared with others simulators available commercially. Another example that can be cited is the tool called SF2VHD, presented in [17]. That tool is capable to translate hierarchical models of finite states machine, modeled in the Stateflow environment, in a code corresponding structural VHDL.

In the work described in [18] was developed a tool called Sim2HDL, which accomplishes the automatic translation of Simulink models in a hardware description language in the attempt to drastically reduce the project time. The generated language can be VHDL or Verilog, at a behavioral level description, and the system can be implemented in FPGAs using commercial

Some commercial modeling tools incorporate the translation need for different forms of modeling. An example is a MATLAB C Compiler tool, developed by Mathworks. That tool translates programs written in MATLAB for a corresponding program in the C language. The

In [20] was proposed an approach to automatic synthesis of additional decoders. The method attempts to find and remove cases where there are no equivalent decoders. To discover all decoders that can exist simultaneously, an algorithm based on functional dependency has also been proposed. To select the correct decoder another algorithm is used to infer formula of each

In [21] was developed a framework for the synthesis of electronic systems at a high level based on abstract finite state machines. The framework called synASM is capable of generating a CDFG (Control Data Flow Graph) from hardware descriptions based on C language. The authors extended the definitions of abstract state machines to support the parallelism and timing. After generating the CDFG extended, it was possible the automatic generation of

In [22] was presented a complete approach decoder for communication systems. The model‐ ling was based on finite state machines and the method was capable of identifying whether decode exists or not, by observing the input sequence and output of encoder. [23] presented a method of representation and synthesis of Boolean expressions recursively. The method performs a sequence of operations with denial implications using two memristors. With the method, it was proved that it was possible to reduce the number of necessary implications for

optimizable hardware descriptions in VHDL and implementation in a FPGA.

Emphasis) simulator using an FPGA (Field Programmable Gate Array)

functionality and main advantages of these tools are described in [19].

checking faulty behavior.

424 MATLAB Applications for the Practical Engineer

synthesizers.

decoder precondition.

The SF2 HDL is a computational tool capable to convert a state transition diagram into a hardware description language description. This diagram is described in the Stateflow environment [29]. The Stateflow is toolbox inside Simulink is used to simulate finite state machines in different contexts. The SF2 HDL tool is a simplified graphical interface that allows the user to select between generate (i) an input file to be processed by TABELA program and (ii) a.*vhd* file with a behavioral VHDL description obtained directly from state transition diagram.

The TABELA program was developed for synthesize of a finite state machine and was implemented in Pascal language by researchers from UNICAMP [7] (Universidade Estadual de Campinas-Brazil). The program generates combinational functions that implement the finite machine described by state transition table. The transition functions and output functions are minimized and the cost of minimization using minterms and maxterms [7]. The transitions are specified on table form using one line per state transition, so: present state, next state, input, output. The description end is represented by notation "-100". Figure 4 shows the standard file for TABELA program input.

The states, the inputs and outputs must be in decimal notation. The finite state machines can be completely or incompletely specified.

Thus, from all the information found in the.*mdl* (Simulink file) file, it is possible to determine the present state, the next state, the input and output of the finite state machine. According to the structure of each file, all the information is grouped and then is generated the input file for TABELA program and/or the corresponding behavioral VHDL. Figure 6 presents the func‐

> File (Stateflow)

Find Transitions

List of Transition s

List of Input Conditions

> List of Outputs

HDL initially reads the file containing finite state machine, simulated in the Stateflow environment. Then, the program finds the state machine structure and it makes a temporary storage of this information. After that, the state location list for all states is generated and through the transition locations is generated a transitions list, identifying the conditions for the inputs and outputs. When the user selects to generate the input file for the TABELA program, there is the need to choose what type of memory element (flip-flop) will be used in

the generated file. The memory element type must be put manually by the user.

HDL program with all necessary steps to perform the translation, as

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SF<sup>2</sup>HDL initially reads the file containing finite state machine, simulated in the Stateflow environment. Then, the program finds the state machine structure and it makes a temporary storage of this information. After that, the state location list for all states is generated and through the transition locations is generated a transitions list, identifying the conditions for the inputs and outputs. When the user selects to generate the input file for the TABELA program, there is the need to choose what type of memory element (flip-flop) will be used in the generated file. The memory element type

File .vhd (VHDL)

File .tab (TABELA)

File .v (Verilog)

Obtain Flip-Flop

Figure 7 shows the class diagram of SF<sup>2</sup>HDL. The SF<sup>2</sup>HDL was built with many inheritances between the classes. There are two objects to store the structure found in the .mdl file; the state information and transition information. This distinction is considered because the differences between a Mealy machine and Moore machine described in Equations (3), (4) and (5). SF<sup>2</sup>HDL is capable of recognizing which machine is used in the model. The fsm object is responsible to read the .mdl file and to save this information. The misc has some operations used many times during running of SF<sup>2</sup>HDL. The create\_files object is responsible to create the file that was chosen by user, as illustrate in Figure 7. As

For modeling the state transition diagram on Stateflow environment, some rules must be obeyed, such as the name of the state contained within the symbol should never begin with numeric character (0, 1, 2, 3, 4, 5, 6, 7 , 8 or 9), and the

where e represents the variable that will receive input value, t is a variable that represents a discrete time and s is an output variable. The external bracket represents the input condition in the transition from one state to another to obtain an output. The double equal signs (==) represent the verification of a condition and the equal sign alone (=) represents

SF<sup>2</sup>HDL can create three files at the same time, the main class call the create\_files more than once, if it is the case.

3.1. Simulation results of HDB3 line code and conversion results

condition in the transition to the Mealy model must meet the following syntax:

7

tional diagram of SF2

previously reviewed.

Read File

Find State Machine

Find State

List of States

Figure 6. Block diagram of SF<sup>2</sup>HDL.

**Figure 6.** Block diagram of SF2HDL.

SF2

Create File Selected

must be put manually by the user.

[ [ ] 0]{ 0;} et s == = (6)

the allocation of value [30].

**Figure 4.** Input file for TABELA program.

The TABELA program assembles a state transition table and stores it in output file. From this table are obtained minterms, maxterms and don't care states of transition functions of all internal flip-flops and circuit output functions. Using Quine-McCluskey algorithm, is made the minimization of Boolean functions.

Figure 5 illustrates the main interface of SF2 HDL program. The SF2 HDL has a menu called **Ferramentas** (Tools) with the following options: a) **Nova Tradução** (Translation), used to open the file with a finite state machine modeled in Stateflow environment, b) **Traduzir** (Translate), which performs the model translation into one of language was chosen, c) **Sair** (Quit), which terminates the program, and d) **Sobre** (About) option that displays a screen with a brief comment on the tool developed.

**Figure 5.** Main interface of SF2HDL program.

Figure 7 shows the class diagram of SF<sup>2</sup>HDL. The SF<sup>2</sup>HDL was built with many inheritances between the classes. There are two objects to store the structure found in the .mdl file; the state information and transition information. This distinction is considered because the differences between a Mealy machine and Moore machine described in Equations (3), (4) and (5). SF<sup>2</sup>HDL is capable of recognizing which machine is used in the model. The fsm object is responsible to read the .mdl file and to save this information. The misc has some operations used many times during running of SF<sup>2</sup>HDL. The create\_files object is responsible to create the file that was chosen by user, as illustrate in Figure 7. As

For modeling the state transition diagram on Stateflow environment, some rules must be obeyed, such as the name of the state contained within the symbol should never begin with numeric character (0, 1, 2, 3, 4, 5, 6, 7 , 8 or 9), and the

where e represents the variable that will receive input value, t is a variable that represents a discrete time and s is an output variable. The external bracket represents the input condition in the transition from one state to another to obtain an output. The double equal signs (==) represent the verification of a condition and the equal sign alone (=) represents

SF<sup>2</sup>HDL can create three files at the same time, the main class call the create\_files more than once, if it is the case.

3.1. Simulation results of HDB3 line code and conversion results

condition in the transition to the Mealy model must meet the following syntax:

7

Thus, from all the information found in the.*mdl* (Simulink file) file, it is possible to determine the present state, the next state, the input and output of the finite state machine. According to the structure of each file, all the information is grouped and then is generated the input file for TABELA program and/or the corresponding behavioral VHDL. Figure 6 presents the func‐ tional diagram of SF2 HDL program with all necessary steps to perform the translation, as previously reviewed.

Figure 6. Block diagram of SF<sup>2</sup>HDL. **Figure 6.** Block diagram of SF2HDL.

[ [ ] 0]{ 0;} et s == = (6)

the allocation of value [30].

The states, the inputs and outputs must be in decimal notation. The finite state machines can

The TABELA program assembles a state transition table and stores it in output file. From this table are obtained minterms, maxterms and don't care states of transition functions of all internal flip-flops and circuit output functions. Using Quine-McCluskey algorithm, is made

**Ferramentas** (Tools) with the following options: a) **Nova Tradução** (Translation), used to open the file with a finite state machine modeled in Stateflow environment, b) **Traduzir** (Translate), which performs the model translation into one of language was chosen, c) **Sair** (Quit), which terminates the program, and d) **Sobre** (About) option that displays a screen with a brief

HDL program. The SF2

HDL has a menu called

be completely or incompletely specified.

426 MATLAB Applications for the Practical Engineer

**Figure 4.** Input file for TABELA program.

the minimization of Boolean functions.

comment on the tool developed.

**Figure 5.** Main interface of SF2HDL program.

Figure 5 illustrates the main interface of SF2

SF<sup>2</sup>HDL initially reads the file containing finite state machine, simulated in the Stateflow environment. Then, the program finds the state machine structure and it makes a temporary storage of this information. After that, the state location list for all states is generated and through the transition locations is generated a transitions list, identifying the conditions for the inputs and outputs. When the user selects to generate the input file for the TABELA program, there is the need to choose what type of memory element (flip-flop) will be used in the generated file. The memory element type must be put manually by the user. SF2 HDL initially reads the file containing finite state machine, simulated in the Stateflow environment. Then, the program finds the state machine structure and it makes a temporary storage of this information. After that, the state location list for all states is generated and through the transition locations is generated a transitions list, identifying the conditions for the inputs and outputs. When the user selects to generate the input file for the TABELA program, there is the need to choose what type of memory element (flip-flop) will be used in the generated file. The memory element type must be put manually by the user.

Figure 7 shows the class diagram of SF2 HDL. The SF2 HDL was built with many inheritances between the classes. There are two objects to store the structure found in the.*mdl* file; the state information and transition information. This distinction is considered because the differences between a Mealy machine and Moore machine described in Equations (3), (4) and (5). SF2 HDL is capable of recognizing which machine is used in the model. The **fsm** object is responsible to read the.*mdl* file and to save this information. The **misc** has some operations used many times during running of SF2 HDL. The **create\_files** object is responsible to create the file that was chosen by user, as illustrate in Figure 7. As SF2 HDL can create three files at the same time, the **main** class call the **create\_files** more than once, if it is the case.

#### **3.1. Simulation results of HDB3 line code and conversion results**

For modeling the state transition diagram on Stateflow environment, some rules must be obeyed, such as the name of the state contained within the symbol should never begin with numeric character (0, 1, 2, 3, 4, 5, 6, 7, 8 or 9), and the condition in the transition to the Mealy model must meet the following syntax:

$$[\mathbf{e}[t] == \mathbf{0}] \text{(s = 0;)}\tag{6}$$

**Figure 7.** Class diagram of SF2HDL.

Code Generation From MATLAB – Simulink Models

http://dx.doi.org/10.5772/57575

429

**Figure 8.** Description of HDB3 code on Stateflow.

where *e* represents the variable that will receive input value, *t* is a variable that represents a discrete time and *s* is an output variable. The external bracket represents the input condition in the transition from one state to another to obtain an output. The double equal signs (==) represent the verification of a condition and the equal sign alone (=) represents the allocation of value [30].

For proper functionality of the SF2 HDL program, is necessary that the values in the transition of model in Stateflow environment, both at input and output, are decimal representations. Figure 8 presents the state diagram of HDB3 code on Stateflow environment.

In simulation are used several words with signs and bits from varying sizes. However, it was standardized in using an input word in the simulation of 24 bits being formed by the following bits: 000100110000110101000100. We used this bit stream because with it we can simulate both characteristics of signal encoder, AMI and HDB3, in a real situation. The result of the simulation is presented in the Figure 9.

The TABELA program creates a new file, containing a description of Boolean functions from the circuit already minimized.

Listing 1 was reduced and is shown only important parts of minimization. Each Boolean function in the finite state machine is minimized. As HDB3 has five flip-flops and two output bits, it is possible to see seven functions in Listing 1 (lines 1, 11, 21, 28, 34, 40 and 51). In each function are described the function minterms in decimal, e.g. line 3. The function prime implicants and essentials are shown too, e.g. lines 4-9. And the function cost is shown in lines 10, 20, 27, 33, 39, 50 and 58. The total cost of the circuit is shown in lie 59, for HDB3 case is 95. It is important to highlight that the cost is expressed like sum of product by TABELA.

**Figure 7.** Class diagram of SF2HDL.

Figure 7 shows the class diagram of SF2

428 MATLAB Applications for the Practical Engineer

chosen by user, as illustrate in Figure 7. As SF2

model must meet the following syntax:

For proper functionality of the SF2

is presented in the Figure 9.

the circuit already minimized.

**main** class call the **create\_files** more than once, if it is the case.

**3.1. Simulation results of HDB3 line code and conversion results**

during running of SF2

of value [30].

HDL. The SF2

between the classes. There are two objects to store the structure found in the.*mdl* file; the state information and transition information. This distinction is considered because the differences between a Mealy machine and Moore machine described in Equations (3), (4) and (5). SF2

is capable of recognizing which machine is used in the model. The **fsm** object is responsible to read the.*mdl* file and to save this information. The **misc** has some operations used many times

For modeling the state transition diagram on Stateflow environment, some rules must be obeyed, such as the name of the state contained within the symbol should never begin with numeric character (0, 1, 2, 3, 4, 5, 6, 7, 8 or 9), and the condition in the transition to the Mealy

where *e* represents the variable that will receive input value, *t* is a variable that represents a discrete time and *s* is an output variable. The external bracket represents the input condition in the transition from one state to another to obtain an output. The double equal signs (==) represent the verification of a condition and the equal sign alone (=) represents the allocation

of model in Stateflow environment, both at input and output, are decimal representations.

In simulation are used several words with signs and bits from varying sizes. However, it was standardized in using an input word in the simulation of 24 bits being formed by the following bits: 000100110000110101000100. We used this bit stream because with it we can simulate both characteristics of signal encoder, AMI and HDB3, in a real situation. The result of the simulation

The TABELA program creates a new file, containing a description of Boolean functions from

Listing 1 was reduced and is shown only important parts of minimization. Each Boolean function in the finite state machine is minimized. As HDB3 has five flip-flops and two output bits, it is possible to see seven functions in Listing 1 (lines 1, 11, 21, 28, 34, 40 and 51). In each function are described the function minterms in decimal, e.g. line 3. The function prime implicants and essentials are shown too, e.g. lines 4-9. And the function cost is shown in lines 10, 20, 27, 33, 39, 50 and 58. The total cost of the circuit is shown in lie 59, for HDB3 case is 95. It is important to highlight that the cost is expressed like sum of product by TABELA.

Figure 8 presents the state diagram of HDB3 code on Stateflow environment.

HDL. The **create\_files** object is responsible to create the file that was

HDL was built with many inheritances

HDL can create three files at the same time, the

[ [ ] 0]{ 0;} *et s* == = (6)

HDL program, is necessary that the values in the transition

HDL

**Figure 8.** Description of HDB3 code on Stateflow.

After the minimization by TABELA was used the TAB2VHDL program [31] which generated VHDL code in RTL (Register Transfer Level) that is shown in Listing 2. The TAB2VHDL is a tool developed by researchers in UNESP (Universidade Estadual Paulista-Brazil) in C lan‐ guage. The only task TAB2VHDL is generated the VHDL code from TABELA output. <sup>10</sup>

Code Generation From MATLAB – Simulink Models

http://dx.doi.org/10.5772/57575

431

22. D4 <= ((VE4) AND (VE2)) OR ((VE4) AND (VE1)) OR ((VE4) AND (VE0)) OR ((X0) AND (VE4)) OR (NOT(X0) AND NOT (VE4) AND NOT (VE2) AND NOT (VE1) AND NOT(VE0)); 23. D3 <= ( NOT(X0) AND (VE4) AND NOT(VE2) AND NOT(VE1) AND NOT(VE0)) OR (NOT(X0) AND (VE3) AND (VE2)) OR (NOT(X0) AND (VE3) AND (VE1)) OR (NOT(X0) AND (VE3) AND (VE0)) OR ((X0) AND

26. D0 <= ( (VE1)); 27. Z1 <= ( (VE3) AND (VE2) AND NOT(VE1) AND (VE0)) OR ((VE3) AND NOT(VE2) AND (VE1) AND (VE0)) OR (NOT(X0) AND NOT(VE4) AND (VE3) AND NOT(VE2) AND NOT(VE1) AND NOT(VE0)) OR (NOT(VE3) AND (VE2) AND (VE1) AND (VE0)) OR (NOT(VE3) AND NOT(VE2) AND NOT(VE1) AND (VE0)); 28. Z0 <= ( (VE3) AND (VE2) AND NOT(VE1) AND (VE0)) OR ((VE3) AND NOT(VE2) AND (VE1) AND (VE0)) OR (NOT(X0) AND NOT(VE4) AND (VE3) AND NOT(VE2) AND NOT(VE1) AND NOT(VE0)) OR (NOT(VE3) AND

(VE2) AND (VE1) AND (VE0)) OR (NOT(VE3) AND NOT(VE2) AND NOT(VE1) AND (VE0));

In Listing 2, there is clear distinction in architecture between the flip-flops and the Boolean function to describe the behavior of HDB3. In lines 15-22 are described the flip-flop used (noting that this listing was reduced to presentation in this chapter). Lines 25-31 show the Boolean function of HDB3. This kind of abstraction has better results for synthesis in

The other option is to generate the behavioral VHDL directly without using TABELA program. In Listing 3 is shown the

In Listing 2, there is clear distinction in architecture between the flip-flops and the Boolean function to describe the behavior of HDB3. In lines 15-22 are described the flip-flop used (noting that this listing was reduced to presentation in this chapter). Lines 25-31 show the Boolean function of HDB3. This kind of abstraction has better results for synthesis in order to

The other option is to generate the behavioral VHDL directly without using TABELA program.

This description is different between Listing 2 as it is expressed at a behavioral level of abstraction for HDB3. In lines 3 and 4 in the entity, the signal representation is in decimal instead binary. This is a different way that VHDL can support the representation of input and output signals. Lines 14-41 express the behavior of the finite state machine. The reset signal is

the same label used in Stateflow, such as Figure 8. This case study coincidentally is the same (decimal representation instead hexadecimal), but in other cases then this label will be changed. The last process in description, lines 43-47, describes the update of state by clock

HDL does not use

HDL is a behavioral Verilog code [32], which

1. ENTITY HDB3 IS 2. PORT(

11. BEGIN

13. BEGIN 14. IF CLR = '0' THEN

17. VE0 <= D0; 18. END IF; 19. END PROCESS; 20. ... 21. ...

25. D1 <= ( (VE2));

file with behavioral VHDL code generated. 1. ENTITY Mealy\_HD IS

> 5. clk, clr: IN BIT 6. ); 7. END Mealy\_HD;

14. nxtstate <= state; 15. output <= 0; 16. IF reset = '0' THEN 17. nxtstate <= S14; 18. ELSE 19. CASE state IS 20. WHEN S0 => 21. IF (input = 1) THEN 22. output <= 1; 23. nxtstate <= S12;

11. BEGIN

24. ELSE 25. output <= 1; 26. nxtstate <= S2; 27. END IF; 28. WHEN S1 => 29. IF (input = 1) THEN 30. output <= 0; 31. nxtstate <= S12;

32. ELSE

it is shown in Listing 4.

signal.

33. output <= 0; 34. nxtstate <= S2;

The third description language generated by SF2

2. PORT( 3. ent: IN INTEGER RANGE 0 TO 1; 4. sai: OUT INTEGER RANGE 0 TO 3;

8. ARCHITECTURE lpssd OF Mealy\_HD IS 9. TYPE tipo\_est IS (S0, S1, S2... S31); 10. SIGNAL est\_atual, prox\_est: tipo\_est;

12. behavior: PROCESS (reset, input, state) 13. BEGIN

29. END RTL;

3. CLK, CLR: IN BIT; 4. X0: IN BIT; 5. Z0, Z1: OUT BIT 6. ); 7. END HDB3;

12. PROCESS (CLK, CLR)

8. ARCHITECTURE RTL OF HDB3 IS 9. SIGNAL VE0, VE1, VE2, VE3, VE4: BIT; 10. SIGNAL D4, D3, D2, D1, D0: BIT;

15. VE0 <= '0'; 16. ELSIF CLK'EVENT and CLK = '1' THEN

NOT(VE3)); 24. D2 <= ( (X0)) OR (NOT(VE2) AND NOT(VE1) AND NOT(VE0));

Listing 2. VHDL code generate by TAB2VHDL program for HDB3 study case.

**Listing 2.** VHDL code generate by TAB2VHDL program for HDB3 study case.

order to implement the circuit, e.g. in a FPGA (Field Programming Gate Array).

implement the circuit, e.g. in a FPGA (Field Programming Gate Array).

In Listing 3 is shown the file with behavioral VHDL code generated.

shown in line 18 and 19 and lines 21-40 show the transitions of HDB3. SF2

**Figure 9.** Results of simulation of HDB3on Stateflow.

```
1. FUNCAO D4 
2. ========= 3. MINTERMOS : 0; 8; 48; 17; 49; 18; 50; 19; 51; 20; 52; 21; 53; 22; 54; 23; 55; 25; 57; 26; 
58; 27; 59; 28; 60; 29; 61; 30; 62; 31; 63; 4. IMPLICANTES PRIMOS ESSENCIAIS : 5. ESSENCIAL: 20 REDUNDANCIA: 43 -> X1X1XX 
6. ESSENCIAL: 18 REDUNDANCIA: 45 -> X1XX1X 7. ESSENCIAL: 17 REDUNDANCIA: 46 -> X1XXX1 8. ESSENCIAL: 48 REDUNDANCIA: 15 -> 11XXXX 9. ESSENCIAL: 0 REDUNDANCIA: 8 -> 00X000 
10. CUSTO FINAL DE D4 = 18 11. FUNCAO D3 
12. ========= 
13. MINTERMOS : 32; 33; 34; 35; 36; 37; 38; 39; 9; 10; 11; 12; 13; 14; 15; 48; 16; 49; 50; 51; 
      52; 53; 54; 55; 24; 25; 26; 27; 28; 29; 30; 31; 
14. IMPLICANTES PRIMOS ESSENCIAIS : 
15. ESSENCIAL: 16 REDUNDANCIA: 8 -> 01X000 16. ESSENCIAL: 12 REDUNDANCIA: 19 -> 0X11XX 
17. ESSENCIAL: 10 REDUNDANCIA: 21 -> 0X1X1X 
18. ESSENCIAL: 9 REDUNDANCIA: 22 -> 0X1XX1 19. ESSENCIAL: 32 REDUNDANCIA: 23 -> 1X0XXX 20. CUSTO FINAL DE D3 = 21 
21. FUNCAO D2 22. ========= 
23. MINTERMOS : 32; 0; 33; 34; 35; 36; 37; 38; 39; 40; 8; 41; 42; 43; 44; 45; 46; 47; 48; 16; 
49; 50; 51; 52; 53; 54; 55; 56; 24; 57; 58; 59; 60; 61; 62; 63; 24. IMPLICANTES PRIMOS ESSENCIAIS : 25. ESSENCIAL: 32 REDUNDANCIA: 31 -> 1XXXXX 26. ESSENCIAL: 0 REDUNDANCIA: 56 -> XXX000 27. CUSTO FINAL DE D2 = 6 28. FUNCAO D1 
29. ========= 30. MINTERMOS : 4; 36; 5; 37; 6; 38; 39; 7; 44; 12; 13; 45; 46; 14; 47; 15; 20; 52; 21; 53; 22; 
      54; 55; 23; 60; 28; 61; 29; 62; 30; 63; 31; 
31. IMPLICANTES PRIMOS ESSENCIAIS : 32. ESSENCIAL: 4 REDUNDANCIA: 59 -> XXX1XX 
33. CUSTO FINAL DE D1 = 1 34. FUNCAO D0 35. ========= 36. MINTERMOS : 34; 2; 3; 35; 6; 38; 39; 7; 42; 10; 11; 43; 46; 14; 47; 15; 18; 50; 51; 19; 22; 
54; 55; 23; 26; 58; 59; 27; 62; 30; 63; 31; 37. IMPLICANTES PRIMOS ESSENCIAIS : 38. ESSENCIAL: 2 REDUNDANCIA: 61 -> XXXX1X 39. CUSTO FINAL DE D0 = 1 40. FUNCAO Z1 
41. ========= 42. MINTERMOS : 33; 39; 7; 8; 11; 43; 13; 45; 17; 49; 55; 23; 59; 27; 61; 29; 43. IMPLICANTES PRIMOS ESSENCIAIS : 
44. ESSENCIAL: 17 REDUNDANCIA: 32 -> X10001 
45. ESSENCIAL: 13 REDUNDANCIA: 48 -> XX1101 46. ESSENCIAL: 11 REDUNDANCIA: 48 -> XX1011 
47. ESSENCIAL: 8 REDUNDANCIA: 0 -> 001000 
48. ESSENCIAL: 7 REDUNDANCIA: 48 -> XX0111 49. ESSENCIAL: 33 REDUNDANCIA: 16 -> 1X0001 
50. CUSTO FINAL DE Z1 = 34 
51. FUNCAO Z0 52. ========= 
53. MINTERMOS : 1; 33; 3; 35; 5; 37; 39; 7; 8; 41; 9; 11; 43; 13; 45; 47; 15; 16; 17; 49; 51; 
19; 21; 53; 55; 23; 57; 25; 59; 27; 61; 29; 63; 31; 54. IMPLICANTES PRIMOS ESSENCIAIS : 
55. ESSENCIAL: 16 REDUNDANCIA: 1 -> 01000X 56. ESSENCIAL: 8 REDUNDANCIA: 1 -> 00100X 57. ESSENCIAL: 1 REDUNDANCIA: 62 -> XXXXX1 58. CUSTO FINAL DE Z0 = 14 
59. CUSTO TOTAL DAS 7 FUNCOES = 95
```
**Listing 1.** Minimization generate by TABELA program for HDB3 study case

Listing 1. Minimization generate by TABELA program for HDB3 study case.

After the minimization by TABELA was used the TAB2VHDL program [31] which generated VHDL code in RTL (Register Transfer Level) that is shown in Listing 2. The TAB2VHDL is a tool developed by researchers in UNESP (Universidade Estadual Paulista-Brazil) in C lan‐ guage. The only task TAB2VHDL is generated the VHDL code from TABELA output. <sup>10</sup>

In Listing 2, there is clear distinction in architecture between the flip-flops and the Boolean function to describe the behavior of HDB3. In lines 15-22 are described the flip-flop used (noting that this listing was reduced to presentation in **Listing 2.** VHDL code generate by TAB2VHDL program for HDB3 study case.

Listing 2. VHDL code generate by TAB2VHDL program for HDB3 study case.

10

1. FUNCAO D4

430 MATLAB Applications for the Practical Engineer

12. =========

21. FUNCAO D2 22. =========

10. CUSTO FINAL DE D4 = 18 11. FUNCAO D3

**Figure 9.** Results of simulation of HDB3on Stateflow.

14. IMPLICANTES PRIMOS ESSENCIAIS :

58; 27; 59; 28; 60; 29; 61; 30; 62; 31; 63; 4. IMPLICANTES PRIMOS ESSENCIAIS : 5. ESSENCIAL: 20 REDUNDANCIA: 43 -> X1X1XX 6. ESSENCIAL: 18 REDUNDANCIA: 45 -> X1XX1X 7. ESSENCIAL: 17 REDUNDANCIA: 46 -> X1XXX1 8. ESSENCIAL: 48 REDUNDANCIA: 15 -> 11XXXX 9. ESSENCIAL: 0 REDUNDANCIA: 8 -> 00X000

15. ESSENCIAL: 16 REDUNDANCIA: 8 -> 01X000 16. ESSENCIAL: 12 REDUNDANCIA: 19 -> 0X11XX 17. ESSENCIAL: 10 REDUNDANCIA: 21 -> 0X1X1X 18. ESSENCIAL: 9 REDUNDANCIA: 22 -> 0X1XX1 19. ESSENCIAL: 32 REDUNDANCIA: 23 -> 1X0XXX 20. CUSTO FINAL DE D3 = 21

54; 55; 23; 60; 28; 61; 29; 62; 30; 63; 31; 31. IMPLICANTES PRIMOS ESSENCIAIS : 32. ESSENCIAL: 4 REDUNDANCIA: 59 -> XXX1XX

54; 55; 23; 26; 58; 59; 27; 62; 30; 63; 31; 37. IMPLICANTES PRIMOS ESSENCIAIS : 38. ESSENCIAL: 2 REDUNDANCIA: 61 -> XXXX1X 39. CUSTO FINAL DE D0 = 1 40. FUNCAO Z1

44. ESSENCIAL: 17 REDUNDANCIA: 32 -> X10001 45. ESSENCIAL: 13 REDUNDANCIA: 48 -> XX1101 46. ESSENCIAL: 11 REDUNDANCIA: 48 -> XX1011 47. ESSENCIAL: 8 REDUNDANCIA: 0 -> 001000 48. ESSENCIAL: 7 REDUNDANCIA: 48 -> XX0111 49. ESSENCIAL: 33 REDUNDANCIA: 16 -> 1X0001

55. ESSENCIAL: 16 REDUNDANCIA: 1 -> 01000X 56. ESSENCIAL: 8 REDUNDANCIA: 1 -> 00100X 57. ESSENCIAL: 1 REDUNDANCIA: 62 -> XXXXX1 58. CUSTO FINAL DE Z0 = 14

59. CUSTO TOTAL DAS 7 FUNCOES = 95

19; 21; 53; 55; 23; 57; 25; 59; 27; 61; 29; 63; 31; 54. IMPLICANTES PRIMOS ESSENCIAIS :

Listing 1. Minimization generate by TABELA program for HDB3 study case. **Listing 1.** Minimization generate by TABELA program for HDB3 study case

50. CUSTO FINAL DE Z1 = 34

51. FUNCAO Z0 52. =========

52; 53; 54; 55; 24; 25; 26; 27; 28; 29; 30; 31;

49; 50; 51; 52; 53; 54; 55; 56; 24; 57; 58; 59; 60; 61; 62; 63; 24. IMPLICANTES PRIMOS ESSENCIAIS : 25. ESSENCIAL: 32 REDUNDANCIA: 31 -> 1XXXXX 26. ESSENCIAL: 0 REDUNDANCIA: 56 -> XXX000 27. CUSTO FINAL DE D2 = 6 28. FUNCAO D1

41. ========= 42. MINTERMOS : 33; 39; 7; 8; 11; 43; 13; 45; 17; 49; 55; 23; 59; 27; 61; 29; 43. IMPLICANTES PRIMOS ESSENCIAIS :

2. ========= 3. MINTERMOS : 0; 8; 48; 17; 49; 18; 50; 19; 51; 20; 52; 21; 53; 22; 54; 23; 55; 25; 57; 26;

13. MINTERMOS : 32; 33; 34; 35; 36; 37; 38; 39; 9; 10; 11; 12; 13; 14; 15; 48; 16; 49; 50; 51;

23. MINTERMOS : 32; 0; 33; 34; 35; 36; 37; 38; 39; 40; 8; 41; 42; 43; 44; 45; 46; 47; 48; 16;

29. ========= 30. MINTERMOS : 4; 36; 5; 37; 6; 38; 39; 7; 44; 12; 13; 45; 46; 14; 47; 15; 20; 52; 21; 53; 22;

33. CUSTO FINAL DE D1 = 1 34. FUNCAO D0 35. ========= 36. MINTERMOS : 34; 2; 3; 35; 6; 38; 39; 7; 42; 10; 11; 43; 46; 14; 47; 15; 18; 50; 51; 19; 22;

53. MINTERMOS : 1; 33; 3; 35; 5; 37; 39; 7; 8; 41; 9; 11; 43; 13; 45; 47; 15; 16; 17; 49; 51;

order to implement the circuit, e.g. in a FPGA (Field Programming Gate Array). The other option is to generate the behavioral VHDL directly without using TABELA program. In Listing 3 is shown the file with behavioral VHDL code generated. 1. ENTITY Mealy\_HD IS 2. PORT( 3. ent: IN INTEGER RANGE 0 TO 1; 4. sai: OUT INTEGER RANGE 0 TO 3; 5. clk, clr: IN BIT 6. ); 7. END Mealy\_HD; 8. ARCHITECTURE lpssd OF Mealy\_HD IS In Listing 2, there is clear distinction in architecture between the flip-flops and the Boolean function to describe the behavior of HDB3. In lines 15-22 are described the flip-flop used (noting that this listing was reduced to presentation in this chapter). Lines 25-31 show the Boolean function of HDB3. This kind of abstraction has better results for synthesis in order to implement the circuit, e.g. in a FPGA (Field Programming Gate Array).

this chapter). Lines 25-31 show the Boolean function of HDB3. This kind of abstraction has better results for synthesis in

9. TYPE tipo\_est IS (S0, S1, S2... S31); 10. SIGNAL est\_atual, prox\_est: tipo\_est; 11. BEGIN 12. behavior: PROCESS (reset, input, state) 13. BEGIN 14. nxtstate <= state; The other option is to generate the behavioral VHDL directly without using TABELA program. In Listing 3 is shown the file with behavioral VHDL code generated.

15. output <= 0; 16. IF reset = '0' THEN 17. nxtstate <= S14; 18. ELSE 19. CASE state IS 20. WHEN S0 => 21. IF (input = 1) THEN 22. output <= 1; 23. nxtstate <= S12; 24. ELSE 25. output <= 1; 26. nxtstate <= S2; 27. END IF; 28. WHEN S1 => 29. IF (input = 1) THEN 30. output <= 0; 31. nxtstate <= S12; 32. ELSE 33. output <= 0; 34. nxtstate <= S2; This description is different between Listing 2 as it is expressed at a behavioral level of abstraction for HDB3. In lines 3 and 4 in the entity, the signal representation is in decimal instead binary. This is a different way that VHDL can support the representation of input and output signals. Lines 14-41 express the behavior of the finite state machine. The reset signal is shown in line 18 and 19 and lines 21-40 show the transitions of HDB3. SF2 HDL does not use the same label used in Stateflow, such as Figure 8. This case study coincidentally is the same (decimal representation instead hexadecimal), but in other cases then this label will be changed. The last process in description, lines 43-47, describes the update of state by clock signal.

The third description language generated by SF2 HDL is a behavioral Verilog code [32], which it is shown in Listing 4.

file with behavioral VHDL code generated.

TABELA output.

cost is expressed like sum of product by TABELA.

Figure 11.Listing 2. VHDL code generate by TAB2VHDL program for HDB3 study case.

```
1. ENTITY Mealy_HD IS 2. PORT( 3. ent: IN INTEGER RANGE 0 TO 1; 
4. sai: OUT INTEGER RANGE 0 TO 3; 5. clk, clr: IN BIT
6. ); 7. END Mealy_HD; 8. ARCHITECTURE lpssd OF Mealy_HD IS
9. TYPE tipo_est IS (S0, S1, S2... S31); 
10. SIGNAL est_atual, prox_est: tipo_est; 11. BEGIN 
12. behavior: PROCESS (reset, input, state) 
13. BEGIN 14. nxtstate <= state; 
15. output <= 0; 
16. IF reset = '0' THEN 17. nxtstate <= S14; 
18. ELSE 
19. CASE state IS 20. WHEN S0 => 
21. IF (input = 1) THEN
22. output <= 1; 23. nxtstate <= S12; 
24. ELSE 25. output <= 1; 26. nxtstate <= S2; 
27. END IF; 
28. WHEN S1 => 29. IF (input = 1) THEN 30. output <= 0; 
31. nxtstate <= S12; 32. ELSE
33. output <= 0; 
34. nxtstate <= S2; 35. END IF;
36. ... 
37. ... 38. END CASE; 
39. END PROCESS; 
40. clock: PROCESS 41. BEGIN 
42. WAIT UNTIL clk'EVENT AND clk = '1';
43. state <= nxtstate; 44. END PROCESS clock; 
45. END lpssd;
```
**Listing 3.** Behavioral VHDL code generate by SF2HDL for HDB3 study case.

Listing 3. Behavioral VHDL code generate by SF<sup>2</sup>HDL for HDB3 study case.

Listing 4 is very similar to Listing 3, with the difference in the syntax between both languages, VHDL and Verilog. In the same way, lines 18-48 express the behavioral of the finite state machine, the reset signal is shown in line 21 and 23, lines 25-46 is shown the transitions and lines 50-52 describe the update of state by clock signal.

(lines 1, 11, 21, 28, 34, 40 and 51). In each function are described the function minterms in decimal, e.g. line 3. The function prime implicants and essentials are shown too, e.g. lines 4-9. And the function cost is shown in lines 10, 20, 27, 33, 39, 50 and 58. The total cost of the circuit is shown in lie 59, for HDB3 case is 95. It is important to highlight that the

After the minimization by TABELA was used the TAB2VHDL program [31] which generated VHDL code in RTL (Register Transfer Level) that is shown in Listing 2. The TAB2VHDL is a tool developed by researchers in UNESP (Universidade Estadual Paulista - Brazil) in C language. The only task TAB2VHDL is generated the VHDL code from

In Listing 2, there is clear distinction in architecture between the flip-flops and the Boolean function to describe the behavior of HDB3. In lines 15-22 are described the flip-flop used (noting that this listing was reduced to presentation in

The other option is to generate the behavioral VHDL directly without using TABELA program. In Listing 3 is shown the

9

1. module Mealy\_HD (clk, in, reset, out); 2. input clk, reset;

14. always @ (in or reset or state) begin

3. input [0:0] in; 4. output out; 5. reg [1:0] out; 6. reg [4:0] state; 7. reg [4:0] nxtstate; 8. parameter [4:0] 9. S0 = 0, 10. S1 = 1, 11. ... 12. ... 13. S31 = 31;

15. nxtstate = state; 16. out = 0; 17. if (reset) begin 18. nxtstate = S14; 19. end 20. else begin 21. case (state) 22. S0: 23. if (in == 1) begin 24. nxtstate = S12; 25. out = 1;

27. else begin 28. nxtstate = S2; 29. out = 1; 30. end 31. S1:

32. if (in == 1) begin 33. nxtstate = S12; 34. out = 0;

36. else begin 37. nxtstate = S2; 38. out = 0; 39. end 40. ... 41. ... 42. endcase 43. end 44. end

HDB3 code too in the Quartus II.

Cyclone II EP2C20F484C7 FPGA.

**Figure 11.** HDB3 line code Simulation in RTL VHDL.

45. always @ (posedge clk) begin 46. state = nxtstate;

Figure 10. HDB3 line code Simulation in behavioral VHDL.

**Figure 10.** HDB3 line code Simulation in behavioral VHDL.

Listing 4. Behavioral Verilog code generate by SF<sup>2</sup>HDL for HDB3 study case.

**Listing 4.** Behavioral Verilog code generate by SF2HDL for HDB3 study case.

25-46 is shown the transitions and lines 50-52 describe the update of state by clock signal.

Listing 4 is very similar to Listing 3, with the difference in the syntax between both languages, VHDL and Verilog. In the same way, lines 18-48 express the behavioral of the finite state machine, the reset signal is shown in line 21 and 23, lines

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In Figure 10 is shown the simulation of behavioral VHDL code generated by SF<sup>2</sup>HDL on Quartus II environment [33], using the same word of data in the simulation as that in the Stateflow environment to verify accuracy and violation of

There is a short delay in output least significant in Figure 10. But the delay does not disrupt the behavioral of the HDB3 encoder. The behavioral VHDL, RTL VHDL and behavioral Verilog codes were synthesized and implemented on the

Figure 11 shows the simulation waveform of code generated by TAB2VHDL, i.e., using a RTL VHDL code. This is different from Figure 10 and in Figure 11 is possible to see a stranger behavioral of the code. Possibly this is due to some

26. end

35. end

47. end 48. endmodule

In Figure 10 is shown the simulation of behavioral VHDL code generated by SF2 HDL on Quartus II environment [33], using the same word of data in the simulation as that in the Stateflow environment to verify accuracy and violation of HDB3 code too in the Quartus II.

There is a short delay in output least significant in Figure 10. But the delay does not disrupt the behavioral of the HDB3 encoder. The behavioral VHDL, RTL VHDL and behavioral Verilog codes were synthesized and implemented on the Cyclone II EP2C20F484C7 FPGA.

Figure 11 shows the simulation waveform of code generated by TAB2VHDL, i.e., using a RTL VHDL code. This is different from Figure 10 and in Figure 11 is possible to see a stranger behavioral of the code. Possibly this is due to some mistakes in TABELA program as the RTL VHDL is same of the optimization realized by TABELA program. Or even, possibly the results of synthesis of Quartus II. At the moment we do not know the cause of the problem.

Figure 12 illustrates the simulation results for behavioral Verilog code. The simulation waveform of Figure 12 is the same waveform in Figure 10, proving that this representation in behavioral Verilog and VHDL, because the level of abstraction in the same too. The synthesis result in FPGA Cyclone II is another equal result.

```
1. module Mealy_HD (clk, in, reset, out); 2. input clk, reset; 
3. input [0:0] in; 4. output out; 
5. reg [1:0] out; 6. reg [4:0] state; 7. reg [4:0] nxtstate; 
8. parameter [4:0] 
9. S0 = 0, 10. S1 = 1, 
11. ... 
12. ... 13. S31 = 31; 
14. always @ (in or reset or state) begin
15. nxtstate = state; 16. out = 0; 
17. if (reset) begin
18. nxtstate = S14; 19. end 
20. else begin 
21. case (state) 22. S0: 
23. if (in == 1) begin
24. nxtstate = S12; 25. out = 1; 
26. end 
27. else begin 28. nxtstate = S2; 
29. out = 1; 
30. end 31. S1: 
32. if (in == 1) begin
33. nxtstate = S12; 34. out = 0; 
35. end 
36. else begin 37. nxtstate = S2; 
38. out = 0; 
39. end 40. ... 
41. ... 
42. endcase 43. end 
44. end 
45. always @ (posedge clk) begin 46. state = nxtstate; 
47. end 
48. endmodule
```
Listing 4. Behavioral Verilog code generate by SF<sup>2</sup>HDL for HDB3 study case. Listing 4 is very similar to Listing 3, with the difference in the syntax between both languages, VHDL and Verilog. In the same way, lines 18-48 express the behavioral of the finite state machine, the reset signal is shown in line 21 and 23, lines **Listing 4.** Behavioral Verilog code generate by SF2HDL for HDB3 study case.

25-46 is shown the transitions and lines 50-52 describe the update of state by clock signal.


In Figure 10 is shown the simulation of behavioral VHDL code generated by SF<sup>2</sup>HDL on Quartus II environment [33],

Figure 10. HDB3 line code Simulation in behavioral VHDL. **Figure 10.** HDB3 line code Simulation in behavioral VHDL.

Listing 4 is very similar to Listing 3, with the difference in the syntax between both languages, VHDL and Verilog. In the same way, lines 18-48 express the behavioral of the finite state machine, the reset signal is shown in line 21 and 23, lines 25-46 is shown the transitions and

(lines 1, 11, 21, 28, 34, 40 and 51). In each function are described the function minterms in decimal, e.g. line 3. The function prime implicants and essentials are shown too, e.g. lines 4-9. And the function cost is shown in lines 10, 20, 27, 33, 39, 50 and 58. The total cost of the circuit is shown in lie 59, for HDB3 case is 95. It is important to highlight that the

After the minimization by TABELA was used the TAB2VHDL program [31] which generated VHDL code in RTL (Register Transfer Level) that is shown in Listing 2. The TAB2VHDL is a tool developed by researchers in UNESP (Universidade Estadual Paulista - Brazil) in C language. The only task TAB2VHDL is generated the VHDL code from

In Listing 2, there is clear distinction in architecture between the flip-flops and the Boolean function to describe the behavior of HDB3. In lines 15-22 are described the flip-flop used (noting that this listing was reduced to presentation in this chapter). Lines 25-31 show the Boolean function of HDB3. This kind of abstraction has better results for synthesis in

The other option is to generate the behavioral VHDL directly without using TABELA program. In Listing 3 is shown the

cost is expressed like sum of product by TABELA.

file with behavioral VHDL code generated. 1. ENTITY Mealy\_HD IS

> 2. PORT( 3. ent: IN INTEGER RANGE 0 TO 1; 4. sai: OUT INTEGER RANGE 0 TO 3; 5. clk, clr: IN BIT 6. ); 7. END Mealy\_HD; 8. ARCHITECTURE lpssd OF Mealy\_HD IS 9. TYPE tipo\_est IS (S0, S1, S2... S31); 10. SIGNAL est\_atual, prox\_est: tipo\_est; 11. BEGIN 12. behavior: PROCESS (reset, input, state)

Figure 11.Listing 2. VHDL code generate by TAB2VHDL program for HDB3 study case.

order to implement the circuit, e.g. in a FPGA (Field Programming Gate Array).

TABELA output.

13. BEGIN

18. ELSE 19. CASE state IS 20. WHEN S0 => 21. IF (input = 1) THEN 22. output <= 1; 23. nxtstate <= S12;

24. ELSE

36. ... 37. ... 38. END CASE; 39. END PROCESS; 40. clock: PROCESS 41. BEGIN

14. nxtstate <= state; 15. output <= 0; 16. IF reset = '0' THEN 17. nxtstate <= S14;

25. output <= 1; 26. nxtstate <= S2; 27. END IF; 28. WHEN S1 => 29. IF (input = 1) THEN 30. output <= 0; 31. nxtstate <= S12; 32. ELSE 33. output <= 0; 34. nxtstate <= S2; 35. END IF;

43. state <= nxtstate; 44. END PROCESS clock; 45. END lpssd;

Quartus II environment [33], using the same word of data in the simulation as that in the Stateflow environment to verify accuracy and violation of HDB3 code too in the Quartus II.

There is a short delay in output least significant in Figure 10. But the delay does not disrupt the behavioral of the HDB3 encoder. The behavioral VHDL, RTL VHDL and behavioral Verilog

Figure 11 shows the simulation waveform of code generated by TAB2VHDL, i.e., using a RTL VHDL code. This is different from Figure 10 and in Figure 11 is possible to see a stranger behavioral of the code. Possibly this is due to some mistakes in TABELA program as the RTL VHDL is same of the optimization realized by TABELA program. Or even, possibly the results

Figure 12 illustrates the simulation results for behavioral Verilog code. The simulation waveform of Figure 12 is the same waveform in Figure 10, proving that this representation in behavioral Verilog and VHDL, because the level of abstraction in the same too. The synthesis

HDL on

9

In Figure 10 is shown the simulation of behavioral VHDL code generated by SF2

codes were synthesized and implemented on the Cyclone II EP2C20F484C7 FPGA.

of synthesis of Quartus II. At the moment we do not know the cause of the problem.

lines 50-52 describe the update of state by clock signal.

42. WAIT UNTIL clk'EVENT AND clk = '1';

Listing 3. Behavioral VHDL code generate by SF<sup>2</sup>HDL for HDB3 study case. **Listing 3.** Behavioral VHDL code generate by SF2HDL for HDB3 study case.

result in FPGA Cyclone II is another equal result.


There is a short delay in output least significant in Figure 10. But the delay does not disrupt the behavioral of the HDB3 encoder. The behavioral VHDL, RTL VHDL and behavioral Verilog codes were synthesized and implemented on the

**Figure 11.** HDB3 line code Simulation in RTL VHDL.

Cyclone II EP2C20F484C7 FPGA.

In the main interface, there is the menu containing the following options: a) **Arquivo** (File): In this option, there are two possible actions. With the first action, the user selects the Simulink model to be translated. When this action is selected, the status bar appears on the file name to be translated. The second action is a button to end execution of the tool, b) **Ferramentas** (Tools): In this option, the user is able to select the project location. The process of translation is then initiated. If there are unknown models that the tool is not able to recognize, it will display a message reporting the fact, c) **Configuração** (Configuration): In this option, there is an action called "Adicionar / Remover Componentes (Add / Remove Components)" and another called "Adicionar / Remover Bibliotecas (Add / Remove Libraries)". These options are used to add / remove elements of toolboxes and Simulink libraries developed by the designer, respectively. If there is not a model configuration to be translated, the tool is not able to recognize it and

The translation of the model starts with reading a Simulink generated file with an.**mdl** extension. Initially, a check is made of elements and libraries used in model. If there are no unknown libraries or elements, the translation process starts. The tool stores a list of compo‐ nents in model, the list of connections between these components and other important information for generation of circuit netlist. Then, project structure required for simulation and analysis in SystemVision is generated too [35][36]. Finally, all descriptions in VHDL-AMS and files for debugging for project needs are generated. Figure 14 shows the functional diagram

If subsystems are used, a VHDL-AMS model for each subsystem used is generated. The

15, only the classes **Main**, **Save** and **VHDL** are in the interface layer. The others class makes the translation inference engine. The **SystemFile** class is responsible to generate all project structure to simulate in SytemVision environment. The **TranslateCode** is responsible to generate all VHDL-AMS files. This class inherits the features of **Checking** class, and **Check‐ ing** class checks if there is any primitive of Simulink, user libraries or subsystems. **Checking** inherits the features of **Lib** class and **Lib** class is responsible to catch the models into libraries. Last one, **Lib** inherits the features of **ReadMDL**, it responsible to reads the models in MAT‐

The translation process using elements of Simulink toolboxes is started with a verification of elements inside the model using **Checking** class operation. The **Checking** class uses the operation of **ReadMDL** class to read the Simulink file. The reading the Simulink file is done more than once because the interface that controls the inference engine allowing different file being loaded without translation. The process translate of elements inside libraries created by designer is quite similar to elements of Simulink toolboxes, but it includes the Lib class. Lib

SV enables the relationship between elements in the same library by creating hierarchical

SV in a software perspective. All interface

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SV functionality. In Figure

SV to represent libraries

translate it.

of the MS2

MS2

models.

LAB / Simulink.

described by designer.

SV tool.

Figure 15 represents the class diagram of tool MS2

layers are represented since some aspects do not change the MS2

class copy the descriptions saved into internal libraries in tool MS2

**Figure 13.** Directory structure and files that are used in configuration and the translation of models in MATLAB / Si‐ mulink.

#### **4. Generation code methodology of MS2 SV**

The MS2 SV is capable to convert a simulation model in Simulink to a description in VHDL-AMS [34]. This time, we used a VHDL-AMS description since the models can use different kinds of signals such as electrical, mechanical, hydraulic, etc. MS2 SV has two key features:

1. The designer is able to add new components from the Simulink libraries. With this feature, the designer can use different elements previously defined in the standard Simulink libraries.

2. The addition of new Simulink libraries developed by the designer with more complex models, or to change the library named LIB\_MS2SV also used in previously paper [36].

**Figure 12.** HDB3 line code Simulation in behavioral Verilog.

This added flexibility is made possible by creating a directory structure and configuration as shown Figure 13. From the root directory **bin** configuration files are split between configura‐ tions of elements from libraries of MATLAB / Simulink (**lib** directory) and elements of toolbox Simulink (**blk** directory) subject to translation. The pseudo-code concerning the VHDL-AMS models are also arranged between directories.

In the main interface, there is the menu containing the following options: a) **Arquivo** (File): In this option, there are two possible actions. With the first action, the user selects the Simulink model to be translated. When this action is selected, the status bar appears on the file name to be translated. The second action is a button to end execution of the tool, b) **Ferramentas** (Tools): In this option, the user is able to select the project location. The process of translation is then initiated. If there are unknown models that the tool is not able to recognize, it will display a message reporting the fact, c) **Configuração** (Configuration): In this option, there is an action called "Adicionar / Remover Componentes (Add / Remove Components)" and another called "Adicionar / Remover Bibliotecas (Add / Remove Libraries)". These options are used to add / remove elements of toolboxes and Simulink libraries developed by the designer, respectively. If there is not a model configuration to be translated, the tool is not able to recognize it and translate it.

The translation of the model starts with reading a Simulink generated file with an.**mdl** extension. Initially, a check is made of elements and libraries used in model. If there are no unknown libraries or elements, the translation process starts. The tool stores a list of compo‐ nents in model, the list of connections between these components and other important information for generation of circuit netlist. Then, project structure required for simulation and analysis in SystemVision is generated too [35][36]. Finally, all descriptions in VHDL-AMS and files for debugging for project needs are generated. Figure 14 shows the functional diagram of the MS2 SV tool.

**4. Generation code methodology of MS2**

434 MATLAB Applications for the Practical Engineer

**Figure 12.** HDB3 line code Simulation in behavioral Verilog.

models are also arranged between directories.

kinds of signals such as electrical, mechanical, hydraulic, etc. MS2

The MS2

mulink.

**SV**

SV has two key features:

SV is capable to convert a simulation model in Simulink to a description in VHDL-

AMS [34]. This time, we used a VHDL-AMS description since the models can use different

**Figure 13.** Directory structure and files that are used in configuration and the translation of models in MATLAB / Si‐

1. The designer is able to add new components from the Simulink libraries. With this feature, the designer can use different elements previously defined in the standard Simulink libraries.

2. The addition of new Simulink libraries developed by the designer with more complex models, or to change the library named LIB\_MS2SV also used in previously paper [36].

This added flexibility is made possible by creating a directory structure and configuration as shown Figure 13. From the root directory **bin** configuration files are split between configura‐ tions of elements from libraries of MATLAB / Simulink (**lib** directory) and elements of toolbox Simulink (**blk** directory) subject to translation. The pseudo-code concerning the VHDL-AMS

If subsystems are used, a VHDL-AMS model for each subsystem used is generated. The MS2 SV enables the relationship between elements in the same library by creating hierarchical models.

Figure 15 represents the class diagram of tool MS2 SV in a software perspective. All interface layers are represented since some aspects do not change the MS2 SV functionality. In Figure 15, only the classes **Main**, **Save** and **VHDL** are in the interface layer. The others class makes the translation inference engine. The **SystemFile** class is responsible to generate all project structure to simulate in SytemVision environment. The **TranslateCode** is responsible to generate all VHDL-AMS files. This class inherits the features of **Checking** class, and **Check‐ ing** class checks if there is any primitive of Simulink, user libraries or subsystems. **Checking** inherits the features of **Lib** class and **Lib** class is responsible to catch the models into libraries. Last one, **Lib** inherits the features of **ReadMDL**, it responsible to reads the models in MAT‐ LAB / Simulink.

The translation process using elements of Simulink toolboxes is started with a verification of elements inside the model using **Checking** class operation. The **Checking** class uses the operation of **ReadMDL** class to read the Simulink file. The reading the Simulink file is done more than once because the interface that controls the inference engine allowing different file being loaded without translation. The process translate of elements inside libraries created by designer is quite similar to elements of Simulink toolboxes, but it includes the Lib class. Lib class copy the descriptions saved into internal libraries in tool MS2 SV to represent libraries described by designer.

**Figure 14.** Functional diagram of the MS2SV tool illustrating the steps involved in translating the model to generate input file structure in SystemVision environment.

Based on the specifications found in the datasheet of DAC08 converter [37], it was possible to model it in MATLAB / Simulink. Other details of the implementation on a physical level, such as compatibility with TTL (Transistor-Transistor Logic) and CMOS (Complementary Metal Oxide Semiconductor) technology were not considered since the focus of this work was on

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The creation of the R/2R Ladder subsystems involved the use of Equations (1) and (2) in order to adjust the weights of each bit, as shown in Figure 16 [38]. In Figure 16, the Ladder R/2R subsystem was constructed using basic components available in the Simulink libraries. The multiplication between the digital input and weights of each input was made with the "Gain components", the sum with seven "Sum components" of two values and multiplying the result by the reference voltage using "Product component". In this system there are two outputs, the

analog signal and the difference between the output and the reference voltage.

modelling at high level of abstraction.

**Figure 15.** Class diagram of translations rules of MS2SV.

#### **5. Case study of MS2 SV and BD2 XML**

The DAC08, AD7524 and AD7528 DAC were chosen to model and simulate to evaluate the proposed methodology. All of them are monolithic data converter with 8 bit resolution used in applications such gain control circuit and stereo audio.

#### **5.1. DAC08**

DAC08 is a simpler operating model consisting basically of a converter with a resolution of 8 bit parallel input, which performs the digital to analogue conversion. The conversion of digital data into analog is done using the ladder R/2R where the binary inputs control the switching between the current arrival of resistors and current coming directly from the reference voltage.

**Figure 15.** Class diagram of translations rules of MS2SV.

**Figure 14.** Functional diagram of the MS2SV tool illustrating the steps involved in translating the model to generate

**XML**

The DAC08, AD7524 and AD7528 DAC were chosen to model and simulate to evaluate the proposed methodology. All of them are monolithic data converter with 8 bit resolution used

DAC08 is a simpler operating model consisting basically of a converter with a resolution of 8 bit parallel input, which performs the digital to analogue conversion. The conversion of digital data into analog is done using the ladder R/2R where the binary inputs control the switching between the current arrival of resistors and current coming directly from the reference voltage.

**SV and BD2**

in applications such gain control circuit and stereo audio.

input file structure in SystemVision environment.

436 MATLAB Applications for the Practical Engineer

**5. Case study of MS2**

**5.1. DAC08**

Based on the specifications found in the datasheet of DAC08 converter [37], it was possible to model it in MATLAB / Simulink. Other details of the implementation on a physical level, such as compatibility with TTL (Transistor-Transistor Logic) and CMOS (Complementary Metal Oxide Semiconductor) technology were not considered since the focus of this work was on modelling at high level of abstraction.

The creation of the R/2R Ladder subsystems involved the use of Equations (1) and (2) in order to adjust the weights of each bit, as shown in Figure 16 [38]. In Figure 16, the Ladder R/2R subsystem was constructed using basic components available in the Simulink libraries. The multiplication between the digital input and weights of each input was made with the "Gain components", the sum with seven "Sum components" of two values and multiplying the result by the reference voltage using "Product component". In this system there are two outputs, the analog signal and the difference between the output and the reference voltage.

mode, that is, the analog output representing the binary value at input bus DB0-DB7. But when CSB or WRB assumes a logic high (1), AD7524 is in hold mode, analog output has the value corresponding to last input in DB0-DB7 before WRB or CSB assume logic high. Table 1 shows

0 0 Write The output corresponds to activity on the input bus (DB0 to DB7).

Figure 17 represents the buffers used by the AD7524 to store last valid digital input. This component is basically formed by a set of latches and an input common to all latches to enable

Figure 18 illustrates the circuit capable to represent a selection mode in Table 1. This circuit is minimum using only three logic gates (two NOTs and one AND) and Figure 19 shows a complete AD7524 with a circuit of selection mode, a latch buffer to store last input and Ladder

AD7528 is equivalent to two AD7524 converters in a single IC (integrated circuit). The data bus of the AD7528 is also numbered from DB0 to DB7. Each internal converter (DAC A and DAC B) has an individual reference pin. Both can vary ± 25 V. The AD7528 has only three control pins called DACA/DACB, CSB and WRB. The relationship between control pins is illustrated in the Table 2. At a moment when the AD7528 is in hold mode the last valid input

**DACA/DACB WRB CSB DAC A DAC B**

0 0 0 Write Hold

1 0 0 Hold Write

X 1 X Hold Hold

X X 1 Hold Hold

**Table 2.** Selection mode pin to control the AD7528 indicating write mode of the DAC A with all pins active low logic level or in write mode DAC B only with pin in DACA/DACB active-high level, any change in the CSB pin or WRB both

The output corresponds to the last valid entry, stored in flip-flops.

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the relationship of control inputs and selection mode of AD7524 [39].

Hold

is stored in buffers individually in each internal converter [35].

**Table 1.** Selection mode pins to control the AD7524.

1 X

X 1

the output.

R/2R.

**5.3. AD7528**

converters are in hold mode.

**CSB WRB Selection mode Comments**

**Figure 16.** Subsystem in Simulink that represents the R/2R ladder using basic components of the Simulink toolbox, such as Product, Sum, Gain and Data Type Conversion.

An aspect that is important to emphasize in the creation of the R/2R ladder model shown in Figure 16 is that there are "Data Type Conversion components". These components are used to change the way representation of the binary signal (logic 0 or 1) for decimal representation (0 V or 1 V) and subsequent multiplication by weight. In MATLAB / Simulink, this component is not necessary. However, in VHDL-AMS, this component becomes important due to different ways of representing a signal in this language (i.e. the signal types used in VHDL and VHDL-AMS).

#### **5.2. AD7524**

The AD7524 has internally flip-flops of a latch type capable of storing last digital input, and a logic interface capable of controlling reading and storing digital input. The mode selection is controlled by CSB and WRB inputs. When CSB and WRB are at logic low (0) is enabled writing mode, that is, the analog output representing the binary value at input bus DB0-DB7. But when CSB or WRB assumes a logic high (1), AD7524 is in hold mode, analog output has the value corresponding to last input in DB0-DB7 before WRB or CSB assume logic high. Table 1 shows the relationship of control inputs and selection mode of AD7524 [39].


**Table 1.** Selection mode pins to control the AD7524.

Figure 17 represents the buffers used by the AD7524 to store last valid digital input. This component is basically formed by a set of latches and an input common to all latches to enable the output.

Figure 18 illustrates the circuit capable to represent a selection mode in Table 1. This circuit is minimum using only three logic gates (two NOTs and one AND) and Figure 19 shows a complete AD7524 with a circuit of selection mode, a latch buffer to store last input and Ladder R/2R.

#### **5.3. AD7528**

**Figure 16.** Subsystem in Simulink that represents the R/2R ladder using basic components of the Simulink toolbox,

An aspect that is important to emphasize in the creation of the R/2R ladder model shown in Figure 16 is that there are "Data Type Conversion components". These components are used to change the way representation of the binary signal (logic 0 or 1) for decimal representation (0 V or 1 V) and subsequent multiplication by weight. In MATLAB / Simulink, this component is not necessary. However, in VHDL-AMS, this component becomes important due to different ways of representing a signal in this language (i.e. the signal types used in VHDL and VHDL-

The AD7524 has internally flip-flops of a latch type capable of storing last digital input, and a logic interface capable of controlling reading and storing digital input. The mode selection is controlled by CSB and WRB inputs. When CSB and WRB are at logic low (0) is enabled writing

such as Product, Sum, Gain and Data Type Conversion.

438 MATLAB Applications for the Practical Engineer

AMS).

**5.2. AD7524**

AD7528 is equivalent to two AD7524 converters in a single IC (integrated circuit). The data bus of the AD7528 is also numbered from DB0 to DB7. Each internal converter (DAC A and DAC B) has an individual reference pin. Both can vary ± 25 V. The AD7528 has only three control pins called DACA/DACB, CSB and WRB. The relationship between control pins is illustrated in the Table 2. At a moment when the AD7528 is in hold mode the last valid input is stored in buffers individually in each internal converter [35].


**Table 2.** Selection mode pin to control the AD7528 indicating write mode of the DAC A with all pins active low logic level or in write mode DAC B only with pin in DACA/DACB active-high level, any change in the CSB pin or WRB both converters are in hold mode.

**Figure 17.** Subsystem that represents internal buffers converter AD7524, being formed by components Terminator and Latch output (the Qb output from each latch is not used in this work).

**Figure 19.** Complete system AD7524 with all subsystems in Figure 16, 17 and 18.

each block of the AD7528 internal converter (DAC A and DAC B).

Simulink as basic primitive [38].

DACA/DACB, CSB and WRB).

According to the approach described in [40], we created two identical blocks to represent the R/2R ladder, one for the DAC A and one for the DAC B. Similar to the R/2R ladder subsystem of Figure 16, the subsystem of Figure 16 was used twice in the complete system, i.e. one for

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441

Figure 20 represents the logic controller responsible for the selection of which internal drive will be chosen and if converter is in hold or write mode representing behaviour described in Table 2. This subsystem is basically formed by simple logic gates available in toolbox of

Figure 21 shows the complete AD7528 converter model created in MATLAB / Simulink. In each converter, there are two separate outputs, first one is analog output signal generated by the converter and second one is the difference between analog output and reference voltage. Based on [38] and in order to generate a sine wave signal, MATLAB was able to send the signal to each bit according to its magnitude of the pins of the AD7528 with the "From Workspace" component. Subsequently, the outputs were captured and sent back to MATLAB with the "To Workspace" component to generate the graphic simulation. The reference voltage and the pin configuration for each internal converter were created using "Constant" components (pins

**Figure 18.** Subsystem that represents the logic controller of AD7524 and formed only by using AND and NOT gates.

**Figure 19.** Complete system AD7524 with all subsystems in Figure 16, 17 and 18.

**Figure 17.** Subsystem that represents internal buffers converter AD7524, being formed by components Terminator

**Figure 18.** Subsystem that represents the logic controller of AD7524 and formed only by using AND and NOT gates.

and Latch output (the Qb output from each latch is not used in this work).

440 MATLAB Applications for the Practical Engineer

According to the approach described in [40], we created two identical blocks to represent the R/2R ladder, one for the DAC A and one for the DAC B. Similar to the R/2R ladder subsystem of Figure 16, the subsystem of Figure 16 was used twice in the complete system, i.e. one for each block of the AD7528 internal converter (DAC A and DAC B).

Figure 20 represents the logic controller responsible for the selection of which internal drive will be chosen and if converter is in hold or write mode representing behaviour described in Table 2. This subsystem is basically formed by simple logic gates available in toolbox of Simulink as basic primitive [38].

Figure 21 shows the complete AD7528 converter model created in MATLAB / Simulink. In each converter, there are two separate outputs, first one is analog output signal generated by the converter and second one is the difference between analog output and reference voltage. Based on [38] and in order to generate a sine wave signal, MATLAB was able to send the signal to each bit according to its magnitude of the pins of the AD7528 with the "From Workspace" component. Subsequently, the outputs were captured and sent back to MATLAB with the "To Workspace" component to generate the graphic simulation. The reference voltage and the pin configuration for each internal converter were created using "Constant" components (pins DACA/DACB, CSB and WRB).

**5.4. Simulation results of DAC and MS2**

VHDL-AMS codes and MS2

1. library IEEE;

7. port (

17. );

22. ... 23. begin

26. VLOW => 0.0 ) 27. port map ( 28. D => D1\_D, 29. A => \1\$N0\ 30. );

34. port map ( 35. INPUT => \1\$N0\, 36. OUTPUT => \1\$N8\

40. port map ( 41. IN1 => \1\$N8\, 42. IN2 => \1\$N9\, 43. OUTPUT => \1\$N16\

EDULIB (Educational Library).

converters, as listed in Listing 6. 1. use std.textio.all; 2. library IEEE;

5. entity lerarqp is

11. testing: process

13. variable L: LINE;

20. saida <= L\_BIT; 21. end loop;

22. end process testing; 23. end architecture behavior;

10. begin

in Listing 6.

15. begin

8. end entity lerarqp;

37. );

44. ); 45. ...

4. library EduLib; 5. use WORK.all; 6. entity Ladder\_R2R is

5 is part of code generated by MS2

description is listed in Appendix A.

2. use ieee.std\_logic\_1164.all; 3. use ieee.electrical\_systems.all;

8. signal D1\_D: in std\_logic; 9. signal D2\_D: in std\_logic; 10. signal D3\_D: in std\_logic; 11. signal D4\_D: in std\_logic; 12. signal D5\_D: in std\_logic; 13. signal D6\_D: in std\_logic; 14. signal D7\_D: in std\_logic; 15. signal D8\_D: in std\_logic; 16. terminal A1: electrical

18. end entity Ladder\_R2R;

20. terminal \1\$N0\: electrical; 21. terminal \1\$N1\: electrical;

25. generic map ( VHIGH => 1.0,

33. generic map ( K => 0.5 )

38. ... 39. E\_Sum: entity EDULIB.E\_SUM

46. end architecture arch\_Ladder\_R2R; Listing 5. Structural VHDL-AMS code generated by MS<sup>2</sup>SV.

**Listing 5.** Structural VHDL-AMS code generated by MS2SV.

3. use ieee.std\_logic\_1164.all; 4. use IEEE.std\_logic\_textio.all;

named EDULIB (Educational Library).

6. port (relogio: in std\_logic;

16. while not endfile(f\_in) loop 17. readline (f\_in,L); 18. hread (L,L\_BIT);

9. architecture behavior of lerarqp is

7. saida: out std\_ulogic\_vector (8 downto 1));

12. file f\_in: text open READ\_MODE is "input.dat";

14. variable L\_BIT: std\_ulogic\_vector (8 downto 1);

19. wait until (relogio'event) and (relogio='1');

19. architecture arch\_Ladder\_R2R of Ladder\_R2R is

24. DataType: entity EDULIB.D2A\_BIT(IDEAL)

31. ... 32. E\_Gain: entity EDULIB.E\_GAIN(BEHAVIORAL)

After construction and simulation in MATLAB / Simulink, the MS2

**SV conversion results**

SV generated the same configuration of components. The Listing

SV using ladder R/2R in Figure 16. The remains VHDL-AMS

SystemVision environment. The hierarchy structure of model in Simulink was maintained in

This VHDL-AMS code in Listing 5 has a structural abstraction. It represent the linkage between the components which it has all DAC system, e.g. lines 34-39 represent the ports for Gain block and the linkage between Sum block in lines 41-46 and Data Type Converter block in lines 26-32. The exactly behavior of components are in internal libraries in SystemVision environment named

To perform the simulation, SystemVision was used the same input used in MATLAB / Simulink. Thus was created an input file with the extension .dat. It was created to an additional VHDL-AMS code to read this file and send the signal each bit input to the

This VHDL-AMS code in Listing 5 has a structural abstraction. It represent the linkage between the components which it has all DAC system, e.g. lines 34-39 represent the ports for Gain block and the linkage between Sum block in lines 41-46 and Data Type Converter block in lines 26-32. The exactly behavior of components are in internal libraries in SystemVision environment

To perform the simulation, SystemVision was used the same input used in MATLAB / Simulink. Thus was created an input file with the extension.*dat*. It was created to an additional VHDL-AMS code to read this file and send the signal each bit input to the converters, as listed

SV translates model to the

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17

443

**Figure 20.** Subsystem that represents logic controller of AD7528 and formed only by using AND and NOT gates.

**Figure 21.** Complete model of AD7528 converter in Simulink with components From Workspace that receive digital signals from MATLAB and sends output back to MATLAB after simulation through To Workspace component.

The DACA/DACB pin could have been used to carry out switching between two converters internally creating two different waveforms from one input. However, as the converters are exactly the same, the kind of simulation does not alter the analysis of signal generated.

#### **5.4. Simulation results of DAC and MS2 SV conversion results**

After construction and simulation in MATLAB / Simulink, the MS2 SV translates model to the SystemVision environment. The hierarchy structure of model in Simulink was maintained in VHDL-AMS codes and MS2 SV generated the same configuration of components. The Listing 5 is part of code generated by MS2 SV using ladder R/2R in Figure 16. The remains VHDL-AMS description is listed in Appendix A. 17

```
1. library IEEE; 
2. use ieee.std_logic_1164.all; 
3. use ieee.electrical_systems.all; 
4. library EduLib; 
5. use WORK.all; 
6. entity Ladder_R2R is 
7. port ( 
8. signal D1_D: in std_logic; 
9. signal D2_D: in std_logic; 
10. signal D3_D: in std_logic; 
11. signal D4_D: in std_logic; 
12. signal D5_D: in std_logic; 
13. signal D6_D: in std_logic; 
14. signal D7_D: in std_logic; 
15. signal D8_D: in std_logic; 
16. terminal A1: electrical 
17. ); 
18. end entity Ladder_R2R; 
19. architecture arch_Ladder_R2R of Ladder_R2R is 
20. terminal \1$N0\: electrical; 
21. terminal \1$N1\: electrical; 
22. ... 
23. begin 
24. DataType: entity EDULIB.D2A_BIT(IDEAL) 
25. generic map ( VHIGH => 1.0, 
26. VLOW => 0.0 ) 
27. port map ( 
28. D => D1_D, 
29. A => \1$N0\ 
30. ); 
31. ... 32. E_Gain: entity EDULIB.E_GAIN(BEHAVIORAL) 
33. generic map ( K => 0.5 ) 
34. port map ( 
35. INPUT => \1$N0\, 
36. OUTPUT => \1$N8\ 
37. ); 
38. ... 39. E_Sum: entity EDULIB.E_SUM 
40. port map ( 
41. IN1 => \1$N8\, 
42. IN2 => \1$N9\, 
43. OUTPUT => \1$N16\ 
44. ); 
45. ... 
46. end architecture arch_Ladder_R2R;
```
Listing 5. Structural VHDL-AMS code generated by MS<sup>2</sup>SV. This VHDL-AMS code in Listing 5 has a structural abstraction. It represent the linkage between the components which it has all DAC system, e.g. lines 34-39 represent the ports for Gain block and the linkage between Sum block in lines 41-46 and Data Type **Listing 5.** Structural VHDL-AMS code generated by MS2SV.

14. variable L\_BIT: std\_ulogic\_vector (8 downto 1);

19. wait until (relogio'event) and (relogio='1');

16. while not endfile(f\_in) loop 17. readline (f\_in,L); 18. hread (L,L\_BIT);

20. saida <= L\_BIT; 21. end loop;

22. end process testing; 23. end architecture behavior;

15. begin

**Figure 21.** Complete model of AD7528 converter in Simulink with components From Workspace that receive digital signals from MATLAB and sends output back to MATLAB after simulation through To Workspace component.

**Figure 20.** Subsystem that represents logic controller of AD7528 and formed only by using AND and NOT gates.

442 MATLAB Applications for the Practical Engineer

The DACA/DACB pin could have been used to carry out switching between two converters internally creating two different waveforms from one input. However, as the converters are exactly the same, the kind of simulation does not alter the analysis of signal generated.

Converter block in lines 26-32. The exactly behavior of components are in internal libraries in SystemVision environment named EDULIB (Educational Library). To perform the simulation, SystemVision was used the same input used in MATLAB / Simulink. Thus was created an input file with the extension .dat. It was created to an additional VHDL-AMS code to read this file and send the signal each bit input to the converters, as listed in Listing 6. 1. use std.textio.all; 2. library IEEE; 3. use ieee.std\_logic\_1164.all; 4. use IEEE.std\_logic\_textio.all; This VHDL-AMS code in Listing 5 has a structural abstraction. It represent the linkage between the components which it has all DAC system, e.g. lines 34-39 represent the ports for Gain block and the linkage between Sum block in lines 41-46 and Data Type Converter block in lines 26-32. The exactly behavior of components are in internal libraries in SystemVision environment named EDULIB (Educational Library).

5. entity lerarqp is 6. port (relogio: in std\_logic; 7. saida: out std\_ulogic\_vector (8 downto 1)); 8. end entity lerarqp; 9. architecture behavior of lerarqp is 10. begin 11. testing: process 12. file f\_in: text open READ\_MODE is "input.dat"; 13. variable L: LINE; To perform the simulation, SystemVision was used the same input used in MATLAB / Simulink. Thus was created an input file with the extension.*dat*. It was created to an additional VHDL-AMS code to read this file and send the signal each bit input to the converters, as listed in Listing 6.

1. library IEEE;

7. port (

17. );

22. ... 23. begin

26. VLOW => 0.0 ) 27. port map ( 28. D => D1\_D, 29. A => \1\$N0\ 30. );

34. port map ( 35. INPUT => \1\$N0\, 36. OUTPUT => \1\$N8\

40. port map ( 41. IN1 => \1\$N8\, 42. IN2 => \1\$N9\, 43. OUTPUT => \1\$N16\

EDULIB (Educational Library).

converters, as listed in Listing 6.

37. );

44. );

4. library EduLib; 5. use WORK.all; 6. entity Ladder\_R2R is

2. use ieee.std\_logic\_1164.all; 3. use ieee.electrical\_systems.all;

8. signal D1\_D: in std\_logic; 9. signal D2\_D: in std\_logic; 10. signal D3\_D: in std\_logic; 11. signal D4\_D: in std\_logic; 12. signal D5\_D: in std\_logic; 13. signal D6\_D: in std\_logic; 14. signal D7\_D: in std\_logic; 15. signal D8\_D: in std\_logic; 16. terminal A1: electrical

18. end entity Ladder\_R2R;

20. terminal \1\$N0\: electrical; 21. terminal \1\$N1\: electrical;

25. generic map ( VHIGH => 1.0,

33. generic map ( K => 0.5 )

38. ... 39. E\_Sum: entity EDULIB.E\_SUM

45. ... 46. end architecture arch\_Ladder\_R2R;

Listing 5. Structural VHDL-AMS code generated by MS<sup>2</sup>SV.

19. architecture arch\_Ladder\_R2R of Ladder\_R2R is

24. DataType: entity EDULIB.D2A\_BIT(IDEAL)

31. ... 32. E\_Gain: entity EDULIB.E\_GAIN(BEHAVIORAL)

```
1. use std.textio.all; 
2. library IEEE; 
3. use ieee.std_logic_1164.all; 
4. use IEEE.std_logic_textio.all; 
5. entity lerarqp is
6. port (relogio: in std_logic; 
7. saida: out std_ulogic_vector (8 downto 1)); 
8. end entity lerarqp; 
9. architecture behavior of lerarqp is
10. begin 
11. testing: process
12. file f_in: text open READ_MODE is "input.dat"; 
13. variable L: LINE; 
14. variable L_BIT: std_ulogic_vector (8 downto 1); 
15. begin 
16. while not endfile(f_in) loop 
17. readline (f_in,L); 
18. hread (L,L_BIT); 
19. wait until (relogio'event) and (relogio='1'); 
20. saida <= L_BIT; 
21. end loop; 22. end process testing; 
23. end architecture behavior;
```
**Listing 6.** Behavioral VHDL code to read the input simulation file.

analysis the signal generated also in MATLAB, as listed Listing 7.

In Listing 6 was needed to use a library in order to manipulate files (line 4). It was used for a vector to represent the output which was linked to DAC (line 8). After it was built, a process to read the file and put it into output in lines 13-24 is used.

This VHDL-AMS code in Listing 5 has a structural abstraction. It represent the linkage between the components which it has all

To perform the simulation, SystemVision was used the same input used in MATLAB / Simulink. Thus was created an input file with the extension .dat. It was created to an additional VHDL-AMS code to read this file and send the signal each bit input to the

17

results for 1 second. The different voltages were used to create a better view waveform in Figure 21. However in the SystemVision environment, only 10V was used for all converters and only one waveform is plotted in Figure 21 as all converters presented the same simulation results. In MATLAB / Simulink, the AD7524, AD7528 A and AD7528 B presented noise in

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445

**Figure 22.** Result of simulation of all case studies in Simulink and signal from SystemVision in simulation total time of

Another difference noted in Figure 22 is low simulation time in SystemVision environment compared with simulation MATLAB / Simulink. This was due to the way in which VHDL-AMS sees the frequency inside the SystemVision environment which is different to MATLAB /

To verify the quality of signal generated, it was made an analysis of signal obtained through simulation. This analysis was performed through power spectral analysis of the signal obtained from discrete Fourier transform (DFT). Figure 23 illustrates amplitude spectrum of *y(t)* for all case studies, in MATLAB / Simulink and VHDL-AMS. The graph was generated

**5.5. Analysis of simulation in MATLAB / Simulink and VHDL-AMS**

using the discrete Fourier transform described as [41]:

output because the delays in flip-flop of type latch.

1 second.

Simulink.

It was used to save the simulation results in SystemVision in another file with the extension.*dat* so that was possible to analysis the signal generated also in MATLAB, as listed Listing 7. 17 It was used to save the simulation results in SystemVision in another file with the extension .dat so that was possible to

```
1. use std.textio.all; 
2. library IEEE; 
3. use IEEE.std_logic_1164.all; 
4. use IEEE.std_logic_textio.all; 
5. entity writewaveform is
6. port ( 
7. signal relogio: in std_logic; 
8. entrada: in real); 
9. end entity writewaveform; 
10. architecture behavior of writewaveform is
11. file f_out: text open WRITE_MODE is "C:\Mentor_Projects\DAC08_Test\hdl\output.dat"; 
12. --quantity escreve_sinal across entrada to ref; 
13. begin 
14. writying: process
15. variable L: LINE; 
16. begin
17. write(L,REAL'(entrada)); 
18. writeline(f_out,L); 
19. wait until (relogio'event) and (relogio='1'); 
20. end process writying; 
21. end architecture behavior;
```
Listing 7. Behavioral VHDL code to write the output simulation file. Listing 7 follow the same logic in Listing 6, using the library to manipulate file (line 4), a real signal to represent the input which was linked to DAC (line 9) and a process to read from input and write the file in lines 16-22. By space limits, the remains VHDL-AMS **Listing 7.** Behavioral VHDL code to write the output simulation file.

1.1. Analysis of simulation in MATLAB / Simulink and VHDL-AMS

to MATLAB / Simulink.

description for AD7524 and AD7528 are listed in Appendix B and C, respectively. For each case study was used a different reference voltage in simulation: 10V, 8V, 6V and 4V, for DAC08, AD7524, AD7528 A and AD7528 B, respectively. Figure 22 shows the simulation results for 1 second. The different voltages were used to create a better view waveform in Figure 21. However in the SystemVision environment, only 10V was used for all converters and only one waveform is plotted in Figure 21 as all converters presented the same simulation results. In MATLAB / Simulink, the AD7524, AD7528 A and AD7528 B presented noise in output because the delays in flip-flop of type latch. Listing 7 follow the same logic in Listing 6, using the library to manipulate file (line 4), a real signal to represent the input which was linked to DAC (line 9) and a process to read from input and write the file in lines 16-22. By space limits, the remains VHDL-AMS description for AD7524 and AD7528 are listed in Appendix B and C, respectively.

For each case study was used a different reference voltage in simulation: 10V, 8V, 6V and 4V, for DAC08, AD7524, AD7528 A and AD7528 B, respectively. Figure 22 shows the simulation

Figure 22. Result of simulation of all case studies in Simulink and signal from SystemVision in simulation total time of 1 second. Another difference noted in Figure 22 is low simulation time in SystemVision environment compared with simulation MATLAB / Simulink. This was due to the way in which VHDL-AMS sees the frequency inside the SystemVision environment which is different

To verify the quality of signal generated, it was made an analysis of signal obtained through simulation. This analysis was performed through power spectral analysis of the signal obtained from discrete Fourier transform (DFT). Figure 23 illustrates amplitude results for 1 second. The different voltages were used to create a better view waveform in Figure 21. However in the SystemVision environment, only 10V was used for all converters and only one waveform is plotted in Figure 21 as all converters presented the same simulation results. In MATLAB / Simulink, the AD7524, AD7528 A and AD7528 B presented noise in output because the delays in flip-flop of type latch.

17

17

1. library IEEE;

7. port (

17. );

22. ... 23. begin

26. VLOW => 0.0 ) 27. port map ( 28. D => D1\_D, 29. A => \1\$N0\ 30. );

34. port map ( 35. INPUT => \1\$N0\, 36. OUTPUT => \1\$N8\

40. port map ( 41. IN1 => \1\$N8\, 42. IN2 => \1\$N9\, 43. OUTPUT => \1\$N16\

EDULIB (Educational Library).

converters, as listed in Listing 6. 1. use std.textio.all; 2. library IEEE;

5. entity lerarqp is

11. testing: process

13. variable L: LINE;

20. saida <= L\_BIT; 21. end loop; 22. end process testing; 23. end architecture behavior;

10. begin

15. begin

listed Listing 7.

6. port (

13. begin

16. begin

to MATLAB / Simulink.

1. use std.textio.all; 2. library IEEE;

8. entrada: in real); 9. end entity writewaveform;

14. writying: process 15. variable L: LINE;

3. use IEEE.std\_logic\_1164.all; 4. use IEEE.std\_logic\_textio.all; 5. entity writewaveform is

7. signal relogio: in std\_logic;

17. write(L,REAL'(entrada)); 18. writeline(f\_out,L);

20. end process writying; 21. end architecture behavior;

8. end entity lerarqp;

37. );

44. );

4. library EduLib; 5. use WORK.all; 6. entity Ladder\_R2R is

2. use ieee.std\_logic\_1164.all; 3. use ieee.electrical\_systems.all;

8. signal D1\_D: in std\_logic; 9. signal D2\_D: in std\_logic; 10. signal D3\_D: in std\_logic; 11. signal D4\_D: in std\_logic; 12. signal D5\_D: in std\_logic; 13. signal D6\_D: in std\_logic; 14. signal D7\_D: in std\_logic; 15. signal D8\_D: in std\_logic; 16. terminal A1: electrical

18. end entity Ladder\_R2R;

20. terminal \1\$N0\: electrical; 21. terminal \1\$N1\: electrical;

25. generic map ( VHIGH => 1.0,

33. generic map ( K => 0.5 )

38. ... 39. E\_Sum: entity EDULIB.E\_SUM

45. ... 46. end architecture arch\_Ladder\_R2R;

3. use ieee.std\_logic\_1164.all; 4. use IEEE.std\_logic\_textio.all;

444 MATLAB Applications for the Practical Engineer

6. port (relogio: in std\_logic;

16. while not endfile(f\_in) loop 17. readline (f\_in,L); 18. hread (L,L\_BIT);

9. architecture behavior of lerarqp is

7. saida: out std\_ulogic\_vector (8 downto 1));

12. file f\_in: text open READ\_MODE is "input.dat";

14. variable L\_BIT: std\_ulogic\_vector (8 downto 1);

19. wait until (relogio'event) and (relogio='1');

**Listing 6.** Behavioral VHDL code to read the input simulation file.

analysis the signal generated also in MATLAB, as listed Listing 7.

10. architecture behavior of writewaveform is

12. --quantity escreve\_sinal across entrada to ref;

19. wait until (relogio'event) and (relogio='1');

description for AD7524 and AD7528 are listed in Appendix B and C, respectively.

**Listing 7.** Behavioral VHDL code to write the output simulation file.

AD7528 B presented noise in output because the delays in flip-flop of type latch.

AD7524 and AD7528 are listed in Appendix B and C, respectively.

1.1. Analysis of simulation in MATLAB / Simulink and VHDL-AMS

Listing 7. Behavioral VHDL code to write the output simulation file.

to read the file and put it into output in lines 13-24 is used.

Listing 5. Structural VHDL-AMS code generated by MS<sup>2</sup>SV.

This VHDL-AMS code in Listing 5 has a structural abstraction. It represent the linkage between the components which it has all DAC system, e.g. lines 34-39 represent the ports for Gain block and the linkage between Sum block in lines 41-46 and Data Type Converter block in lines 26-32. The exactly behavior of components are in internal libraries in SystemVision environment named

To perform the simulation, SystemVision was used the same input used in MATLAB / Simulink. Thus was created an input file with the extension .dat. It was created to an additional VHDL-AMS code to read this file and send the signal each bit input to the

In Listing 6 was needed to use a library in order to manipulate files (line 4). It was used for a vector to represent the output which was linked to DAC (line 8). After it was built, a process

It was used to save the simulation results in SystemVision in another file with the extension.*dat* so that was possible to analysis the signal generated also in MATLAB, as

It was used to save the simulation results in SystemVision in another file with the extension .dat so that was possible to

11. file f\_out: text open WRITE\_MODE is "C:\Mentor\_Projects\DAC08\_Test\hdl\output.dat";

Listing 7 follow the same logic in Listing 6, using the library to manipulate file (line 4), a real signal to represent the input which was linked to DAC (line 9) and a process to read from input and write the file in lines 16-22. By space limits, the remains VHDL-AMS

For each case study was used a different reference voltage in simulation: 10V, 8V, 6V and 4V, for DAC08, AD7524, AD7528 A and AD7528 B, respectively. Figure 22 shows the simulation results for 1 second. The different voltages were used to create a better view waveform in Figure 21. However in the SystemVision environment, only 10V was used for all converters and only one waveform is plotted in Figure 21 as all converters presented the same simulation results. In MATLAB / Simulink, the AD7524, AD7528 A and

Listing 7 follow the same logic in Listing 6, using the library to manipulate file (line 4), a real signal to represent the input which was linked to DAC (line 9) and a process to read from input and write the file in lines 16-22. By space limits, the remains VHDL-AMS description for

For each case study was used a different reference voltage in simulation: 10V, 8V, 6V and 4V, for DAC08, AD7524, AD7528 A and AD7528 B, respectively. Figure 22 shows the simulation

Figure 22. Result of simulation of all case studies in Simulink and signal from SystemVision in simulation total time of 1 second. Another difference noted in Figure 22 is low simulation time in SystemVision environment compared with simulation MATLAB / Simulink. This was due to the way in which VHDL-AMS sees the frequency inside the SystemVision environment which is different

To verify the quality of signal generated, it was made an analysis of signal obtained through simulation. This analysis was performed through power spectral analysis of the signal obtained from discrete Fourier transform (DFT). Figure 23 illustrates amplitude

19. architecture arch\_Ladder\_R2R of Ladder\_R2R is

24. DataType: entity EDULIB.D2A\_BIT(IDEAL)

31. ... 32. E\_Gain: entity EDULIB.E\_GAIN(BEHAVIORAL)

**Figure 22.** Result of simulation of all case studies in Simulink and signal from SystemVision in simulation total time of 1 second.

Another difference noted in Figure 22 is low simulation time in SystemVision environment compared with simulation MATLAB / Simulink. This was due to the way in which VHDL-AMS sees the frequency inside the SystemVision environment which is different to MATLAB / Simulink.

#### **5.5. Analysis of simulation in MATLAB / Simulink and VHDL-AMS**

To verify the quality of signal generated, it was made an analysis of signal obtained through simulation. This analysis was performed through power spectral analysis of the signal obtained from discrete Fourier transform (DFT). Figure 23 illustrates amplitude spectrum of *y(t)* for all case studies, in MATLAB / Simulink and VHDL-AMS. The graph was generated using the discrete Fourier transform described as [41]:

$$X(k) = \sum\_{j=1}^{N} x(j)\alpha\_N^{(j-1)(k-1)}\tag{7}$$

which points of adjacent samples are connected by a straight line. The system output *xr(t)* is

At the same time, the system has unity gain and linear phase. Systems with this frequency response features produce an output that is a shift in the time of input [41]. Importantly, this is a pseudo-conversion to analog, as the conversion happens only while *Vref* is constant.

In Figure 23, it is possible to note difference in AD7524, AD7528 A and AD7528 B because of noise in signal. The signal from DAC08 and AD7524 presented a distortion in sine wave showed in Figure 23 too. At the end, the most perfect signal presented by amplitude spectral

Simulink and generate a corresponding textual description in XML [42]. A key point of the working methodology is to use a configuration file that allows the user to identify MATLAB /

characteristics that are relevant to operation of the blocks. All this information can be extracted by the user from their own MATLAB / Simulink file through the block properties. The file has tokens that are the key point of interpretation. For example, the token **&** is responsible for the identification of a new block, which has characteristics between the tokens **{** and **}**. Since the token **#** works as a comment in regular language, i.e., every line that has the # is disregarded.

in memory. Next is read the configuration file. All of blocks are loaded in memory to compare with the blocks in.*mdl* file. Only afterwards begins the reading of the.*mdl* file. Relevant information is inside.*mdl* file, such as the type of block, values inside the block, linkage between the blocks and some other information is important to create a netlist of circuit. From this point, it is possible to create an XML file with the circuit that can used, and reused in many contexts.

XML was developed according to class diagram showed in Figure 25. The classes respon‐ sible for creating a logical structure in memory are inherited by classes responsible for read the configuration file and the block diagram file of the MATLAB / Simulink. The **misc** class

Others instances of classes are composition. This facilitates the creation of threads structure in future to speeding of codes performance for generations of multiple objects codes simultane‐ ously. The designer starts the process specifying the diagram which is the target of BD2

Simulink block to use. This file contains all the blocks readable by the BD2

If the token # is used before the token **&** all block is disregarded.

with routines common to other classes is also inherited by other classes.

**XML**

<sup>=</sup> å - (10)

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447

XML, is able to read a file block diagram in MATLAB /

XML. Initially begins the reading of.*mdl* file

XML and the

XML.

() ( ) ( ) *<sup>r</sup>*

*x t x nT h t nT* +¥

*n*

was the signal from SystemVision environment.

**6. Generation code methodology of BD2**

Figure 24 illustrates the functional diagram of BD2

The computational tool, called BD2

=-¥

given by:

BD2

$$\mathbf{x}(j) = (\mathbf{1} / \mathbf{N}) \sum\_{k=1}^{N} \mathbf{X}(k) o\_{\mathbf{B}}^{-(j-1)(k-1)} \tag{8}$$

$$
\rho\_N = e^{(-2\pi i)/N} \tag{9}
$$

**Figure 23.** Graph of spectral power all output signals in Simulink and SystemVision with peak in frequency at 2.9297 Hz.

The DC (Direct Current) level of the signal was extracted through shifting the signal along the *y* axis at zero. This resulted in a sine wave signal ranging from-5 to 5 for 10V,-4 to 4 for 8V,-3 to 4 for 6V and-2 to 2 for 4V.

The process of conversion digital to analog represents an interpolation between values of samples provided as inputs, for 20001 points. In this case studies are used linear interpolation, which points of adjacent samples are connected by a straight line. The system output *xr(t)* is given by:

$$\chi\_r(t) = \sum\_{n=-\infty}^{+\infty} \chi(nT)h(t-nT) \tag{10}$$

At the same time, the system has unity gain and linear phase. Systems with this frequency response features produce an output that is a shift in the time of input [41]. Importantly, this is a pseudo-conversion to analog, as the conversion happens only while *Vref* is constant.

In Figure 23, it is possible to note difference in AD7524, AD7528 A and AD7528 B because of noise in signal. The signal from DAC08 and AD7524 presented a distortion in sine wave showed in Figure 23 too. At the end, the most perfect signal presented by amplitude spectral was the signal from SystemVision environment.

#### **6. Generation code methodology of BD2 XML**

( 1)( 1)

( 1)( 1)

*j k B*

<sup>=</sup> å (7)

<sup>=</sup> å (8)


*j k N*

> w-- -

( 2 )/ *i N*

**Figure 23.** Graph of spectral power all output signals in Simulink and SystemVision with peak in frequency at 2.9297

The DC (Direct Current) level of the signal was extracted through shifting the signal along the *y* axis at zero. This resulted in a sine wave signal ranging from-5 to 5 for 10V,-4 to 4 for 8V,-3

The process of conversion digital to analog represents an interpolation between values of samples provided as inputs, for 20001 points. In this case studies are used linear interpolation,

Hz.

to 4 for 6V and-2 to 2 for 4V.

p

w- -

1 () () *N*

1 ( ) (1 / ) ( ) *N*

=

*k xj N Xk*

*<sup>N</sup> e*

w

*j Xk xj*

446 MATLAB Applications for the Practical Engineer

=

The computational tool, called BD2 XML, is able to read a file block diagram in MATLAB / Simulink and generate a corresponding textual description in XML [42]. A key point of the working methodology is to use a configuration file that allows the user to identify MATLAB / Simulink block to use. This file contains all the blocks readable by the BD2 XML and the characteristics that are relevant to operation of the blocks. All this information can be extracted by the user from their own MATLAB / Simulink file through the block properties. The file has tokens that are the key point of interpretation. For example, the token **&** is responsible for the identification of a new block, which has characteristics between the tokens **{** and **}**. Since the token **#** works as a comment in regular language, i.e., every line that has the # is disregarded. If the token # is used before the token **&** all block is disregarded.

Figure 24 illustrates the functional diagram of BD2 XML. Initially begins the reading of.*mdl* file in memory. Next is read the configuration file. All of blocks are loaded in memory to compare with the blocks in.*mdl* file. Only afterwards begins the reading of the.*mdl* file. Relevant information is inside.*mdl* file, such as the type of block, values inside the block, linkage between the blocks and some other information is important to create a netlist of circuit. From this point, it is possible to create an XML file with the circuit that can used, and reused in many contexts.

BD2 XML was developed according to class diagram showed in Figure 25. The classes respon‐ sible for creating a logical structure in memory are inherited by classes responsible for read the configuration file and the block diagram file of the MATLAB / Simulink. The **misc** class with routines common to other classes is also inherited by other classes.

Others instances of classes are composition. This facilitates the creation of threads structure in future to speeding of codes performance for generations of multiple objects codes simultane‐ ously. The designer starts the process specifying the diagram which is the target of BD2 XML. At first, the configuration file is read into a structure and then the block diagram of the MATLAB / Simulink is read into another structure. A comparison is done block by block to check whether the target block is identifiable. Every block of the configuration file has its own characteristics and the default values for these characteristics. In the case of not being identified in some of the characteristics relevant target block are considered the default values of the configuration file to generate the XML. If any block is not identifiable, XML is generated in the same way discarding that particular block.

The data blocks are specified by the tag **<data type="..." value="..." />**. Even in the case of gain, the first tag **data** specifies the kind of signal is used by the block (line 31), e.g., analog. The next

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449

In the configuration file, the blocks of gain are represented in accordance with the Listing 9 (lines 11-14). The block gain has no specification of input and output ports, because by default

The connections between the blocks are made through the tags **<Link>** and **</Link>** (Listing 8, lines 15-20). Inside these tags are two tags named **<OutputPort>** and **</OutputPort>**, that specify the output ports of the block owned by **as="source"** and indicating which is the block

The property **id** is understood as the property **name** of the tag **BasicBlock**. Similarly, the entry

If there are subsystems in the block diagram, they are identified by the tags **<SubSystem name="...">** and **</SubSystem>**, according to the Listing 8 (lines 7-22, 23-40 and 51-55). All configuration of the subsystem is between two tags and their description is the same as already

are specified by the tags **<InputPort>** and **</InputPort>**, and property **as="target"**.

type of data (line 32) specifies the gain value that block has.

a gain always has an input and an output.

**Figure 25.** Class diagram of the BD2XML tool.

output **id="..."**.

explained.

**Figure 24.** Class diagram of the BD2XML tool.

#### **6.1. Conversion results using AD7528**

To demonstrate the BD2 XML, we used the Ladder R/2R case study in Figure 16. Listing 8 is shown a partial description in XML generated by the BD2 XML from the Ladder R/2R.

The tags **<Diagram>** and **</Diagram>** (lines 2-57) identifying the block diagram. The blocks are identified by tags **<BasicBlock type="..." name="...">** and **</BasicBlock>**, being specified block type and the name used in MATLAB / Simulink, for example, the gain block (lines 30-33).

**Figure 25.** Class diagram of the BD2XML tool.

At first, the configuration file is read into a structure and then the block diagram of the MATLAB / Simulink is read into another structure. A comparison is done block by block to check whether the target block is identifiable. Every block of the configuration file has its own characteristics and the default values for these characteristics. In the case of not being identified in some of the characteristics relevant target block are considered the default values of the configuration file to generate the XML. If any block is not identifiable, XML is generated in the

XML, we used the Ladder R/2R case study in Figure 16. Listing 8 is

The tags **<Diagram>** and **</Diagram>** (lines 2-57) identifying the block diagram. The blocks are identified by tags **<BasicBlock type="..." name="...">** and **</BasicBlock>**, being specified block type and the name used in MATLAB / Simulink, for example, the gain block (lines 30-33).

XML from the Ladder R/2R.

same way discarding that particular block.

448 MATLAB Applications for the Practical Engineer

**Figure 24.** Class diagram of the BD2XML tool.

**6.1. Conversion results using AD7528**

shown a partial description in XML generated by the BD2

To demonstrate the BD2

The data blocks are specified by the tag **<data type="..." value="..." />**. Even in the case of gain, the first tag **data** specifies the kind of signal is used by the block (line 31), e.g., analog. The next type of data (line 32) specifies the gain value that block has.

In the configuration file, the blocks of gain are represented in accordance with the Listing 9 (lines 11-14). The block gain has no specification of input and output ports, because by default a gain always has an input and an output.

The connections between the blocks are made through the tags **<Link>** and **</Link>** (Listing 8, lines 15-20). Inside these tags are two tags named **<OutputPort>** and **</OutputPort>**, that specify the output ports of the block owned by **as="source"** and indicating which is the block output **id="..."**.

The property **id** is understood as the property **name** of the tag **BasicBlock**. Similarly, the entry are specified by the tags **<InputPort>** and **</InputPort>**, and property **as="target"**.

If there are subsystems in the block diagram, they are identified by the tags **<SubSystem name="...">** and **</SubSystem>**, according to the Listing 8 (lines 7-22, 23-40 and 51-55). All configuration of the subsystem is between two tags and their description is the same as already explained.

```
1. <?xml version="1.0" encoding="ISO-8859-1"?> 
2. <Diagram> 
3. <InBlock name="in1_d"> 
4. <data type="mixed"/> 
5. </InBlock> 
6. ... 7. <SubSystem name="datalatch_d"> 
8. <data type="mixed"/> 
9. <data type="ports" value="9, 8"/> 
10. ... 
11. <OutBlock name="r7_d"> 
12. <data type="mixed"/> 
13. </OutBlock> 
14. ... 15. <Link> 
16. <OutputPort as="source" id="q1_d"/> 
17. </OutputPort> 
18. <InputPort as="target" id="latch1"/> 
19. </InputPort> 
20. </Link> 
21. ... 22. </SubSystem> 
23. <SubSystem name="ladderr2r"> 
24. <data type="mixed"/> 
25. <data type="ports" value="8, 1"/> 
26. <InBlock name="d1_d"> 
27. <data type="mixed"/> 
28. </InBlock> 
29. ... 
30. <BasicBlock type="gain" name="gain"> 
31. <data type="analog"/> 
32. <data type="gain" value="0.5"/> 
33. </BasicBlock> 
34. ... 
35. <BasicBlock type="sum" name="sum1"> 
36. <data type="analog"/> 
37. <data type="ports" value="2, 1"/> 
38. </BasicBlock> 
39. ... 40. </SubSystem> 
41. <BasicBlock type="product" name="mult"> 
42. <data type="analog"/> 
43. <data type="ports" value="2, 1"/> 
44. </BasicBlock> 
45. <SubSystem name="snor_d"> 
46. <data type="mixed"/> 
47. <data type="ports" value="2, 1"/> 
48. ... 49. <BasicBlock type="logic" name="and1"> 
50. <data type="digital"/> 
51. <data type="ports" value="2, 1"/> 
52. <data type="operator" value="and"/> 
53. </BasicBlock> 
54. ... 55. </SubSystem> 
56. ... 
57. </Diagram>
```
Listing 8. XML description of Ladder R/2R. The tags <Diagram> and </Diagram> (lines 2-57) identifying the block diagram. The blocks are identified by tags <BasicBlock type="..." name="..."> and </BasicBlock>, being specified block type and the name used in MATLAB / **Listing 8.** XML description of Ladder R/2R.

8. analog;

Tags to indicate input and output ports of the block diagram are used most commonly in subsystems and they are in accordance with Listing 8 (lines 3-5, 11-13 and 26-28). Tags to represent input ports are specified by **<InBlock name="...">** and **</InBlock>** (lines 3-5). Simulink, for example, the gain block (lines 30-33). The data blocks are specified by the tag <data type="..." value="..." />. Even in the case of gain, the first tag data specifies the kind of signal is used by the block (line 31), e.g., analog. The next type of data (line 32) specifies the gain value that block has. In the configuration file, the blocks of gain are represented in accordance with the Listing 9 (lines 11-14). The block gain

21

**7. Generation code methodology of SF2**

as="source" and indicating which is the block output id="...".

<InputPort> and </InputPort>, and property as="target".

Listing 9. Representation of the blocks in the configuration file used by BD<sup>2</sup>XML.

**Listing 9.** Representation of the blocks in the configuration file used by BD2XML.

file in case the SCXML proposed by W3C [4].

XM apart from the files generated.

files for different finite state machines. SF2

HDL:

1) Read the MATLAB / Simulink file and identify the FSM;

make interfacing with the user. The class diagram to SF2

type, since both blocks can be an input or an output of digital and analog blocks.

of code and maintenance. There is this feature inside SF2

generate instable behavioral in a same file. It could better if SF2

with international standards of default file in case the SCXML proposed by W3C [4].

**1.** Read the MATLAB / Simulink file and identify the FSM;

**2.** Store the state or transitions and its information;

figure, it is possible to see that the only difference between SF2

XML

The in this section, the tool called SF2

description is the same as already explained.

name="..."> and </InBlock> (lines 3-5).

Datalatch B and Control Logic. 1. Generation code methodology of SF<sup>2</sup>

The SF2

1. &inport { 2. mixed; 3. } 4. &outport { 5. mixed; 6. } 7. &sum { 8. analog; 9. ports "2,1";

10. } 11. &gain { 12. analog; 13. gain "1";

14. } 15. &logic { 16. digital; 17. ports "2,1"; 18. operator "and";

19. }

21. # 22. }

24. # 25. }

29. }

20. &toworkspace {

23. &fromworkspace {

26. &subsystem { 27. mixed; 28. ports "1,1";

SF2

SF2

SF<sup>2</sup>HDL:

understood for SF2

step 2(b).

**XML**

information in the Stateflow environment and generate a corresponding description in XML [43]. The resulting file conversion is also in accordance with international standards of default

The connections between the blocks are made through the tags <Link> and </Link> (Listing 8, lines 15-20). Inside these tags are two tags named <OutputPort> and </OutputPort>, that specify the output ports of the block owned by

The property id is understood as the property name of the tag BasicBlock. Similarly, the entry are specified by the tags

If there are subsystems in the block diagram, they are identified by the tags <SubSystem name="..."> and </SubSystem>, according to the Listing 8 (lines 7-22, 23-40 and 51-55). All configuration of the subsystem is between two tags and their

Tags to indicate input and output ports of the block diagram are used most commonly in subsystems and they are in accordance with Listing 8 (lines 3-5, 11-13 and 26-28). Tags to represent input ports are specified by <InBlock

Similarly, the output ports are specified by the tags <OutBlock name="..."> and </OutBlock> (Listing 8, lines 11-13). In both the tag property name identify the block. Also in either case the tag <data ... /> (Listing 8, lines 4 and 8) are of mixed

All the representation was generated with perfection in one complete file containing all the blocks and subsystems. In this case study AD7528, there are five subsystems representing: the block Ladder R/2R A, Ladder R/2R B, Datalatch A,

memory at runtime, an object of reading the file MATLAB / Simulink and extraction of relevant information, an object to generate the syntactic and semantic file XML and other objects to

highlighted **xml\_file** object. Similarly, the functional diagram in Figure 5, is the same to

The in this section, the tool called SF<sup>2</sup>XML is presented which is capable to capture relevant information in the Stateflow environment and generate a corresponding description in XML [43]. The resulting file conversion is also in accordance

The SF<sup>2</sup>XML has four classes of objects, an object that makes up the logical structure of storage memory at runtime, an object of reading the file MATLAB / Simulink and extraction of relevant information, an object to generate the syntactic and semantic file XML and other objects to make interfacing with the user. The class diagram to SF<sup>2</sup>XML is shown in Figure 26. In this figure, it is possible to see that the only difference between SF<sup>2</sup>XML and SF<sup>2</sup>HDL is the highlighted xml\_file object. Similarly, the functional diagram in Figure 5, is the same to SF<sup>2</sup>XM apart from the files generated. SF<sup>2</sup>XML is also able to identify sub-finite state machine, so it has recursive methods for hierarchical finite state machine clustering automatically, which generates a certain economy of code and maintenance. There is this feature inside SF<sup>2</sup>HDL too, but a hierarchical FSM can generate instable behavioral in a same file. It could better if SF<sup>2</sup>HDL would generate different files for different finite state machines. SF<sup>2</sup>XML has the follow algorithm, which can be understood for

XML is also able to identify sub-finite state machine, so it has recursive methods for hierarchical finite state machine clustering automatically, which generates a certain economy

**a.** If the state has a sub-FSM store the first transition in this sub-FSM, otherwise go to

XML has four classes of objects, an object that makes up the logical structure of storage

XML is presented which is capable to capture relevant

XML is shown in Figure 26. In this

HDL is the

21

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XML and SF2

HDL too, but a hierarchical FSM can

XML has the follow algorithm, which can be

HDL would generate different

Similarly, the output ports are specified by the tags **<OutBlock name="...">** and **</ OutBlock>** (Listing 8, lines 11-13). In both the tag property **name** identify the block. Also in either case the tag **<data... />** (Listing 8, lines 4 and 8) are of mixed type, since both blocks can be an input or an output of digital and analog blocks. has no specification of input and output ports, because by default a gain always has an input and an output. 1. &inport { 2. mixed; 3. } 4. &outport { 5. mixed; 6. } 7. &sum {

All the representation was generated with perfection in one complete file containing all the blocks and subsystems. In this case study AD7528, there are five subsystems representing: the block **Ladder R/2R A**, **Ladder R/2R B**, **Datalatch A**, **Datalatch B** and **Control Logic**. 9. ports "2,1"; 10. }

```
1. &inport { 
2. mixed; 
3. } 
4. &outport { 
5. mixed; 
6. } 
7. &sum { 
8. analog; 
9. ports "2,1"; 
10. } 
11. &gain { 
12. analog; 
13. gain "1"; 
14. } 
15. &logic { 
16. digital; 
17. ports "2,1"; 
18. operator "and"; 
19. } 
20. &toworkspace { 
21. # 
22. } 
23. &fromworkspace { 
24. # 
25. } 
26. &subsystem { 
27. mixed; 
28. ports "1,1"; 
29. }
```
Tags to indicate input and output ports of the block diagram are used most commonly in subsystems and they are in accordance with Listing 8 (lines 3-5, 11-13 and 26-28). Tags to represent input ports are specified by **<InBlock name="...">** and **</InBlock>** (lines 3-5).

The tags <Diagram> and </Diagram> (lines 2-57) identifying the block diagram. The blocks are identified by tags <BasicBlock type="..." name="..."> and </BasicBlock>, being specified block type and the name used in MATLAB /

The data blocks are specified by the tag <data type="..." value="..." />. Even in the case of gain, the first tag data specifies the kind of signal is used by the block (line 31), e.g., analog. The next type of data (line 32) specifies the gain value that

In the configuration file, the blocks of gain are represented in accordance with the Listing 9 (lines 11-14). The block gain

has no specification of input and output ports, because by default a gain always has an input and an output.

Similarly, the output ports are specified by the tags **<OutBlock name="...">** and **</ OutBlock>** (Listing 8, lines 11-13). In both the tag property **name** identify the block. Also in either case the tag **<data... />** (Listing 8, lines 4 and 8) are of mixed type, since both blocks can

All the representation was generated with perfection in one complete file containing all the blocks and subsystems. In this case study AD7528, there are five subsystems representing: the

block **Ladder R/2R A**, **Ladder R/2R B**, **Datalatch A**, **Datalatch B** and **Control Logic**.

be an input or an output of digital and analog blocks.

1. <?xml version="1.0" encoding="ISO-8859-1"?>

2. <Diagram>

5. </InBlock>

17. </OutputPort>

19. </InputPort> 20. </Link> 21. ... 22. </SubSystem>

28. </InBlock> 29. ...

33. </BasicBlock>

38. </BasicBlock> 39. ... 40. </SubSystem>

44. </BasicBlock>

53. </BasicBlock> 54. ... 55. </SubSystem> 56. ... 57. </Diagram>

block has.

10. }

1. &inport { 2. mixed; 3. } 4. &outport { 5. mixed; 6. } 7. &sum { 8. analog; 9. ports "2,1";

34. ...

10. ...

3. <InBlock name="in1\_d"> 4. <data type="mixed"/>

450 MATLAB Applications for the Practical Engineer

8. <data type="mixed"/>

11. <OutBlock name="r7\_d"> 12. <data type="mixed"/> 13. </OutBlock> 14. ... 15. <Link>

6. ... 7. <SubSystem name="datalatch\_d">

9. <data type="ports" value="9, 8"/>

16. <OutputPort as="source" id="q1\_d"/>

18. <InputPort as="target" id="latch1"/>

23. <SubSystem name="ladderr2r"> 24. <data type="mixed"/>

26. <InBlock name="d1\_d"> 27. <data type="mixed"/>

31. <data type="analog"/>

36. <data type="analog"/>

42. <data type="analog"/>

45. <SubSystem name="snor\_d"> 46. <data type="mixed"/>

50. <data type="digital"/>

Listing 8. XML description of Ladder R/2R.

**Listing 8.** XML description of Ladder R/2R.

Simulink, for example, the gain block (lines 30-33).

25. <data type="ports" value="8, 1"/>

30. <BasicBlock type="gain" name="gain">

35. <BasicBlock type="sum" name="sum1">

41. <BasicBlock type="product" name="mult">

37. <data type="ports" value="2, 1"/>

43. <data type="ports" value="2, 1"/>

47. <data type="ports" value="2, 1"/> 48. ... 49. <BasicBlock type="logic" name="and1">

51. <data type="ports" value="2, 1"/> 52. <data type="operator" value="and"/>

32. <data type="gain" value="0.5"/>

The connections between the blocks are made through the tags <Link> and </Link> (Listing 8, lines 15-20). Inside these **Listing 9.** Representation of the blocks in the configuration file used by BD2XML.

Listing 9. Representation of the blocks in the configuration file used by BD<sup>2</sup>XML.

#### **7. Generation code methodology of SF2 XML** as="source" and indicating which is the block output id="...". The property id is understood as the property name of the tag BasicBlock. Similarly, the entry are specified by the tags

<InputPort> and </InputPort>, and property as="target".

The in this section, the tool called SF2 XML is presented which is capable to capture relevant information in the Stateflow environment and generate a corresponding description in XML [43]. The resulting file conversion is also in accordance with international standards of default file in case the SCXML proposed by W3C [4]. If there are subsystems in the block diagram, they are identified by the tags <SubSystem name="..."> and </SubSystem>, according to the Listing 8 (lines 7-22, 23-40 and 51-55). All configuration of the subsystem is between two tags and their description is the same as already explained. Tags to indicate input and output ports of the block diagram are used most commonly in subsystems and they are in accordance with Listing 8 (lines 3-5, 11-13 and 26-28). Tags to represent input ports are specified by <InBlock name="..."> and </InBlock> (lines 3-5).

tags are two tags named <OutputPort> and </OutputPort>, that specify the output ports of the block owned by

The SF2 XML has four classes of objects, an object that makes up the logical structure of storage memory at runtime, an object of reading the file MATLAB / Simulink and extraction of relevant information, an object to generate the syntactic and semantic file XML and other objects to make interfacing with the user. The class diagram to SF2 XML is shown in Figure 26. In this figure, it is possible to see that the only difference between SF2 XML and SF2 HDL is the highlighted **xml\_file** object. Similarly, the functional diagram in Figure 5, is the same to SF2 XM apart from the files generated. Similarly, the output ports are specified by the tags <OutBlock name="..."> and </OutBlock> (Listing 8, lines 11-13). In both the tag property name identify the block. Also in either case the tag <data ... /> (Listing 8, lines 4 and 8) are of mixed type, since both blocks can be an input or an output of digital and analog blocks. All the representation was generated with perfection in one complete file containing all the blocks and subsystems. In this case study AD7528, there are five subsystems representing: the block Ladder R/2R A, Ladder R/2R B, Datalatch A, Datalatch B and Control Logic. 1. Generation code methodology of SF<sup>2</sup> XML The in this section, the tool called SF<sup>2</sup>XML is presented which is capable to capture relevant information in the Stateflow

SF2 XML is also able to identify sub-finite state machine, so it has recursive methods for hierarchical finite state machine clustering automatically, which generates a certain economy of code and maintenance. There is this feature inside SF2 HDL too, but a hierarchical FSM can generate instable behavioral in a same file. It could better if SF2 HDL would generate different files for different finite state machines. SF2 XML has the follow algorithm, which can be understood for SF2 HDL: environment and generate a corresponding description in XML [43]. The resulting file conversion is also in accordance with international standards of default file in case the SCXML proposed by W3C [4]. The SF<sup>2</sup>XML has four classes of objects, an object that makes up the logical structure of storage memory at runtime, an object of reading the file MATLAB / Simulink and extraction of relevant information, an object to generate the syntactic and semantic file XML and other objects to make interfacing with the user. The class diagram to SF<sup>2</sup>XML is shown in Figure 26. In this figure, it is possible to see that the only difference between SF<sup>2</sup>XML and SF<sup>2</sup>HDL is the highlighted xml\_file object. Similarly, the functional diagram in Figure 5, is the same to SF<sup>2</sup>XM apart from the files generated. SF<sup>2</sup>XML is also able to identify sub-finite state machine, so it has recursive methods for hierarchical finite state machine clustering automatically, which generates a certain economy of code and maintenance. There is this feature inside

	- **a.** If the state has a sub-FSM store the first transition in this sub-FSM, otherwise go to step 2(b).
	- **a.** a. Seeking relationship between states of the same hierarchical level and which state is the first in highest level;

6. Return the XML file.

by SF<sup>2</sup>XML.

7.1. Conversion results of HDB3 line code

Figure 26.Figure 46. Class diagram of the SF<sup>2</sup>XML tool.

4. <transition event="INPUT=1"> 5. <target next="1" /> 6. <assign expr="OUTPUT=1" />

8. <transition event="INPUT=0"> 9. <target next="0" /> 10. <assign expr="OUTPUT=0" />

14. <transition event="INPUT=0"> 15. <target next="2" /> 16. <assign expr="OUTPUT=0" />

3. <state id="0">

7. </transition>

11. </transition> 12. </state> 13. <state id="1">

17. </transition> 18. </state> 19. ... 20. </scxml>

within another state or not.

**8. Conclusion**

The SF2

The SF2

1. <?xml version="1.0" encoding="ISO-8859-1"?>

Listing 10. XML code representing the finite state machine of HDB3.

**Listing 10.** XML code representing the finite state machine of HDB3.

regardless of whether the state is within another state or not.

and **</initial>** within a transition indicating to the initial state.

program that is able to perform this work.

2. <scxml version="1.0" xmlns="http://www.w3.org/2005/07/scxml" initialstate="0">

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453

It is important to highlight that states assumed a decimal representation continuously, regardless of whether the state is

Line 1 of Listing 10 specifies that it is an XML file, the XML version and encoding used. The tags of lines 2 and 20, specify the start and end of the finite state machine. In line 2 is also specified the version of SCXML used, the name for the XML document (xmlns) and the initial state of the finite state machine (initialstate="0"). The tag <state id="..."> and </state>

It is important to highlight that states assumed a decimal representation continuously,

Line 1 of Listing 10 specifies that it is an XML file, the XML version and encoding used. The tags of lines 2 and 20, specify the start and end of the finite state machine. In line 2 is also specified the version of SCXML used, the name for the XML document (xmlns) and the initial state of the finite state machine (**initialstate="0"**). The tag **<state id="...">** and **</state>** specifies the state and its identifier (lines 3, 12, 13, 18). The tags **<transition event="...">** and **</transi‐ tion>** to specify a transition that will occur according to a particular event, e.g. **" INPUT=1"** (line 4). If the transition occurs, the tag **<target next="..." />** specifies the next state of the FSM according to its identifier. The tag **<assign expr="OUTPUT=..." />** assigns a new value to the output attribute **expr**. If there are hierarchically nested state, states are chained between the tags **<state id="...">** and **</state>**. However, the initial state is specified by internal tags **<initial>**

HDL program makes the translation of finite state machine, but it does not perform

HDL program does not make optimal state assignment to the state machine as well.

circuit optimization. Hence, it also needs a translation into a file that serves as input to TABELA

Thus, it is necessary to use another tool to do that task. In this way circuit synthesis can be really optimize using all the potentialities of developed tools. Future work will extend this tool to also realize the translation of finite state machines for the structural VHDL and Verilog code. The use of CAD tools and a top-down methodology is a reality that is present in the most electronic circuit design projects, and the development of new computational tools to aid in

The tool was able to accurately generate an XML representation corresponding to the diagram shown in Figure 3. Every XML description is according to SCXML specification. Listing 10 below displays the entire description in XML generated


#### **7.1. Conversion results of HDB3 line code**

The tool was able to accurately generate an XML representation corresponding to the diagram shown in Figure 3. Every XML description is according to SCXML specification. Listing 10 below displays the entire description in XML generated by SF2 XML.

**Figure 26.** Class diagram of the SF2XML tool.

```
1. <?xml version="1.0" encoding="ISO-8859-1"?> 
2. <scxml version="1.0" xmlns="http://www.w3.org/2005/07/scxml" initialstate="0"> 
3. <state id="0"> 
4. <transition event="INPUT=1"> 
5. <target next="1" /> 
6. <assign expr="OUTPUT=1" /> 
7. </transition> 
8. <transition event="INPUT=0"> 
9. <target next="0" /> 
10. <assign expr="OUTPUT=0" /> 
11. </transition> 
12. </state> 
13. <state id="1"> 
14. <transition event="INPUT=0"> 
15. <target next="2" /> 
16. <assign expr="OUTPUT=0" /> 
17. </transition> 
18. </state> 
19. ... 
20. </scxml>
```
The tool was able to accurately generate an XML representation corresponding to the diagram shown in Figure 3. Every XML description is according to SCXML specification. Listing 10 below displays the entire description in XML generated

within another state or not. Line 1 of Listing 10 specifies that it is an XML file, the XML version and encoding used. The tags of lines 2 and 20, specify **Listing 10.** XML code representing the finite state machine of HDB3.

Listing 10. XML code representing the finite state machine of HDB3.

the start and end of the finite state machine. In line 2 is also specified the version of SCXML used, the name for the XML document (xmlns) and the initial state of the finite state machine (initialstate="0"). The tag <state id="..."> and </state> It is important to highlight that states assumed a decimal representation continuously, regardless of whether the state is within another state or not.

It is important to highlight that states assumed a decimal representation continuously, regardless of whether the state is

Line 1 of Listing 10 specifies that it is an XML file, the XML version and encoding used. The tags of lines 2 and 20, specify the start and end of the finite state machine. In line 2 is also specified the version of SCXML used, the name for the XML document (xmlns) and the initial state of the finite state machine (**initialstate="0"**). The tag **<state id="...">** and **</state>** specifies the state and its identifier (lines 3, 12, 13, 18). The tags **<transition event="...">** and **</transi‐ tion>** to specify a transition that will occur according to a particular event, e.g. **" INPUT=1"** (line 4). If the transition occurs, the tag **<target next="..." />** specifies the next state of the FSM according to its identifier. The tag **<assign expr="OUTPUT=..." />** assigns a new value to the output attribute **expr**. If there are hierarchically nested state, states are chained between the tags **<state id="...">** and **</state>**. However, the initial state is specified by internal tags **<initial>** and **</initial>** within a transition indicating to the initial state.

#### **8. Conclusion**

6. Return the XML file.

by SF<sup>2</sup>XML.

7.1. Conversion results of HDB3 line code

Figure 26.Figure 46. Class diagram of the SF<sup>2</sup>XML tool.

**b.** Verify which type this FSM is (Mealy or Moore);

**b.** Write the state tags, the transition related to this states;

below displays the entire description in XML generated by SF2

**a.** a. Seeking relationship between states of the same hierarchical level and which state

**c.** If there is a sub-FSM decrease the level hierarchical and go to step 3(a), otherwise go

**d.** While there is a state such that is associated with a transition go to step 3(a).

The tool was able to accurately generate an XML representation corresponding to the diagram shown in Figure 3. Every XML description is according to SCXML specification. Listing 10

XML.

**3.** Start write XML file;

452 MATLAB Applications for the Practical Engineer

to step 3(d);

**4.** Return the XML file.

is the first in highest level;

**7.1. Conversion results of HDB3 line code**

**Figure 26.** Class diagram of the SF2XML tool.

The SF2 HDL program makes the translation of finite state machine, but it does not perform circuit optimization. Hence, it also needs a translation into a file that serves as input to TABELA program that is able to perform this work.

The SF2 HDL program does not make optimal state assignment to the state machine as well. Thus, it is necessary to use another tool to do that task. In this way circuit synthesis can be really optimize using all the potentialities of developed tools. Future work will extend this tool to also realize the translation of finite state machines for the structural VHDL and Verilog code.

The use of CAD tools and a top-down methodology is a reality that is present in the most electronic circuit design projects, and the development of new computational tools to aid in project implementation is highly desirable, because the range of CAD tools used introduces incompatibilities that can be time consuming and costly in translating between them. Hence, there is the need for suitable tools to be able to translate models between different represen‐ tations.

**Appendix A– DAC08 converter description in structural VHDL-AMS**

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455

22. Ladder\_R2R: entity WORK.Ladder\_R2R(arch\_Ladder\_R2R)

The complete VHDL-AMS code is listed below for DAC08 case.

8. architecture arch\_DAC08 of DAC08 is 9. terminal \1\$N39\: electrical; 10. terminal \1\$N41\: electrical; 11. signal DIn1\_D: std\_logic; 12. signal DIn2\_D: std\_logic; 13. signal DIn3\_D: std\_logic; 14. signal DIn4\_D: std\_logic; 15. signal DIn5\_D: std\_logic; 16. signal DIn6\_D: std\_logic; 17. signal DIn7\_D: std\_logic; 18. signal DIn8\_D: std\_logic; 19. terminal Vref: electrical; 20. terminal Out1: electrical;

2. use ieee.std\_logic\_1164.all; 3. use ieee.electrical\_systems.all;

1. library IEEE;

21. begin

23. port map (

34. port map (

35. IN1 => \1\$N39\, 36. IN2 => Vref,

37. OUTPUT => Out1 );

39. generic map ( LEVEL => 10.0 ) 40. port map ( POS => Vref, 41. NEG => ELECTRICAL\_REF); 42. end architecture arch\_DAC08;

38. V\_VREF: entity EDULIB.V\_CONSTANT(IDEAL)

24. D1\_D => DIn1\_D, 25. D2\_D => DIn2\_D, 26. D3\_D => DIn3\_D, 27. D4\_D => DIn4\_D, 28. D5\_D => DIn5\_D, 29. D6\_D => DIn6\_D, 30. D7\_D => DIn7\_D, 31. D8\_D => DIn8\_D, 32. A1 => \1\$N39\ ); 33. E\_MULT: entity EDULIB.E\_MULT

4. library EduLib; 5. use WORK.all; 6. entity DAC08 is 7. end entity DAC08;

The SF2 HDL tool was tested in several cases of finite state machines and all have been simulated and synthesized in Quartus II environment and Cyclone II FPGA model EP2C20F484C7, respectively.

For the case study of HDB3 code described in this chapter, SF2 HDL program was very effective for translation code modeled on Stateflow, a computational low cost, being accurate in VHDL generation code and the input file for TABELA program corresponding with another pro‐ grams.

Thus, this research generated a tool that allows to the designers to model a finite state machine at high level of abstraction and obtain a corresponding VHDL model which can be synthesized on synthesis tools available commercially. It is also important to say this new translation tools interact with several other tools developed by research group with TABELA program, creating this way a digital synthesis environment.

The MS2 SV tool proved convenient to use as it allows for the creation of multiple libraries for different projects and also recycle the libraries for use in others projects. This allows a signif‐ icant savings of time and hence costs.

By analysing power spectral of a discrete-time signal, one can say that the output signals in MATLAB / Simulink and VHDL-AMS are almost identical. This fact allows us to change our vision about the abstraction levels and details in modelling. Even in the same environment (MATLAB / Simulink) we have difference in spectral signal. If the system be simulating in another environment, we will also have different simulations.

The conversion to XML (using BD2 XML) is convenient because the portability of the language allows a wide applicability of the proposed methodology, e.g., documentation, level synthesis of hardware or software, web publishing, use of XML simulators and as object code for future work. This is the same when using SF2 XML, which it use a standardized description in SCXML.

The use of the intermediate code (like XML) is very important since it can be used in frame‐ works generation and optimization of other types of coding. As an example, hardware description languages like VHDL-AMS, Verilog-AMS, SystemC, etc. Or even reprogrammable devices that have analog and digital blocks and PSoC (Programmable System-on-Chip).

This point highlights the importance to explore more alternatives and standard methodologies of electronic circuit design. Nevertheless, our methodology and tools need further investiga‐ tion and analysis to consider the need for the development of larger and more complex systems.

#### **Appendix A– DAC08 converter description in structural VHDL-AMS**

The complete VHDL-AMS code is listed below for DAC08 case.

project implementation is highly desirable, because the range of CAD tools used introduces incompatibilities that can be time consuming and costly in translating between them. Hence, there is the need for suitable tools to be able to translate models between different represen‐

and synthesized in Quartus II environment and Cyclone II FPGA model EP2C20F484C7,

for translation code modeled on Stateflow, a computational low cost, being accurate in VHDL generation code and the input file for TABELA program corresponding with another pro‐

Thus, this research generated a tool that allows to the designers to model a finite state machine at high level of abstraction and obtain a corresponding VHDL model which can be synthesized on synthesis tools available commercially. It is also important to say this new translation tools interact with several other tools developed by research group with TABELA program, creating

different projects and also recycle the libraries for use in others projects. This allows a signif‐

By analysing power spectral of a discrete-time signal, one can say that the output signals in MATLAB / Simulink and VHDL-AMS are almost identical. This fact allows us to change our vision about the abstraction levels and details in modelling. Even in the same environment (MATLAB / Simulink) we have difference in spectral signal. If the system be simulating in

allows a wide applicability of the proposed methodology, e.g., documentation, level synthesis of hardware or software, web publishing, use of XML simulators and as object code for future

The use of the intermediate code (like XML) is very important since it can be used in frame‐ works generation and optimization of other types of coding. As an example, hardware description languages like VHDL-AMS, Verilog-AMS, SystemC, etc. Or even reprogrammable devices that have analog and digital blocks and PSoC (Programmable System-on-Chip).

This point highlights the importance to explore more alternatives and standard methodologies of electronic circuit design. Nevertheless, our methodology and tools need further investiga‐ tion and analysis to consider the need for the development of larger and more complex

SV tool proved convenient to use as it allows for the creation of multiple libraries for

XML) is convenient because the portability of the language

XML, which it use a standardized description in SCXML.

For the case study of HDB3 code described in this chapter, SF2

another environment, we will also have different simulations.

this way a digital synthesis environment.

icant savings of time and hence costs.

The conversion to XML (using BD2

work. This is the same when using SF2

HDL tool was tested in several cases of finite state machines and all have been simulated

HDL program was very effective

tations.

The SF2

grams.

The MS2

systems.

respectively.

454 MATLAB Applications for the Practical Engineer

```
1. library IEEE;
2. use ieee.std_logic_1164.all;
3. use ieee.electrical_systems.all;
4. library EduLib;
5. use WORK.all;
6. entity DAC08 is
7. end entity DAC08;
8. architecture arch_DAC08 of DAC08 is
9. terminal \1$N39\: electrical;
10. terminal \1$N41\: electrical;
11. signal DIn1_D: std_logic;
12. signal DIn2_D: std_logic;
13. signal DIn3_D: std_logic;
14. signal DIn4_D: std_logic;
15. signal DIn5_D: std_logic;
16. signal DIn6_D: std_logic;
17. signal DIn7_D: std_logic;
18. signal DIn8_D: std_logic;
19. terminal Vref: electrical;
20. terminal Out1: electrical;
21. begin
22. Ladder_R2R: entity WORK.Ladder_R2R(arch_Ladder_R2R)
23. port map (
24. D1_D => DIn1_D,
25. D2_D => DIn2_D,
26. D3_D => DIn3_D,
27. D4_D => DIn4_D,
28. D5_D => DIn5_D,
29. D6_D => DIn6_D,
30. D7_D => DIn7_D,
31. D8_D => DIn8_D,
32. A1 => \1$N39\ );
33. E_MULT: entity EDULIB.E_MULT
34. port map (
35. IN1 => \1$N39\,
36. IN2 => Vref,
37. OUTPUT => Out1 );
38. V_VREF: entity EDULIB.V_CONSTANT(IDEAL)
39. generic map ( LEVEL => 10.0 )
40. port map ( POS => Vref,
41. NEG => ELECTRICAL_REF);
42. end architecture arch_DAC08;
```
### **Appendix B– AD7524 converter descriptions in structural VHDL-AMS**

45. CLK => Enable\_D, 46. Q => R2\_D, 47. QN => \1\$N5\);

59. QN => \1\$N11\ );

65. QN => \1\$N23\ );

77. QN => \1\$N19\ );

83. QN => \1\$N22\ ); 84. end architecture arch\_DataLatch\_D;

2. USE ieee.std\_logic\_1164.all; 3. USE ieee.electrical\_systems.all;

8. signal D: in std\_logic; 9. signal CLK: in std\_logic;

49. port map ( 50. D => Q3\_D, 51. CLK => Enable\_D, 52. Q => R3\_D, 53. QN => \1\$N8\);

55. port map ( 56. D => Q4\_D, 57. CLK => Enable\_D, 58. Q => R4\_D,

61. port map ( 62. D => Q5\_D, 63. CLK => Enable\_D, 64. Q => R5\_D,

67. port map ( 68. D => Q6\_D, 69. CLK => Enable\_D, 70. Q => R6\_D, 71. QN => \1\$N16\);

73. port map ( 74. D => Q7\_D, 75. CLK => Enable\_D, 76. Q => R7\_D,

79. port map ( 80. D => Q8\_D, 81. CLK => Enable\_D, 82. Q => R8\_D,

1. LIBRARY IEEE;

7. port (

4. LIBRARY edulib; 5. USE work.all; 6. entity DLatch is

**•** D Latch

48. DLatch2: entity WORK.DLatch(arch\_DLatch)

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457

54. DLatch3: entity WORK.DLatch(arch\_DLatch)

60. DLatch4: entity WORK.DLatch(arch\_DLatch)

66. DLatch5: entity WORK.DLatch(arch\_DLatch)

72. DLatch6: entity WORK.DLatch(arch\_DLatch)

78. DLatch7: entity WORK.DLatch(arch\_DLatch)

The complete VHDL-AMS code is listed below for Data\_Latch subsystem, SNOR subsystem and AD7524 converter.

**•** Data\_Latch

```
1. library IEEE;
2. use ieee.std_logic_1164.all;
3. use ieee.electrical_systems.all;
4. library EduLib;
5. use WORK.all;
6. entity DataLatch_D is
7. port (
8. signal Q1_D: in std_logic;
9. signal Q2_D: in std_logic;
10. signal Q3_D: in std_logic;
11. signal Q4_D: in std_logic;
12. signal Q5_D: in std_logic;
13. signal Q6_D: in std_logic;
14. signal Q7_D: in std_logic;
15. signal Q8_D: in std_logic;
16. signal Enable_D: in std_logic;
17. signal R1_D: out std_logic;
18. signal R2_D: out std_logic;
19. signal R3_D: out std_logic;
20. signal R4_D: out std_logic;
21. signal R5_D: out std_logic;
22. signal R6_D: out std_logic;
23. signal R7_D: out std_logic;
24. signal R8_D: out std_logic );
25. end entity DataLatch_D;
26. architecture arch_DataLatch_D of DataLatch_D is
27. signal \1$N2\: std_logic;
28. signal \1$N5\: std_logic;
29. signal \1$N8\: std_logic;
30. signal \1$N11\: std_logic;
31. signal \1$N23\: std_logic;
32. signal \1$N16\: std_logic;
33. signal \1$N19\: std_logic;
34. signal \1$N22\: std_logic;
35. begin
36. DLatch: entity WORK.DLatch(arch_DLatch)
37. port map (
38. D => Q1_D,
39. CLK => Enable_D,
40. Q => R1_D,
41. QN => \1$N2\);
42. DLatch1: entity WORK.DLatch(arch_DLatch)
43. port map (
44. D => Q2_D,
```

```
45. CLK => Enable_D,
46. Q => R2_D,
47. QN => \1$N5\);
48. DLatch2: entity WORK.DLatch(arch_DLatch)
49. port map (
50. D => Q3_D,
51. CLK => Enable_D,
52. Q => R3_D,
53. QN => \1$N8\);
54. DLatch3: entity WORK.DLatch(arch_DLatch)
55. port map (
56. D => Q4_D,
57. CLK => Enable_D,
58. Q => R4_D,
59. QN => \1$N11\ );
60. DLatch4: entity WORK.DLatch(arch_DLatch)
61. port map (
62. D => Q5_D,
63. CLK => Enable_D,
64. Q => R5_D,
65. QN => \1$N23\ );
66. DLatch5: entity WORK.DLatch(arch_DLatch)
67. port map (
68. D => Q6_D,
69. CLK => Enable_D,
70. Q => R6_D,
71. QN => \1$N16\);
72. DLatch6: entity WORK.DLatch(arch_DLatch)
73. port map (
74. D => Q7_D,
75. CLK => Enable_D,
76. Q => R7_D,
77. QN => \1$N19\ );
78. DLatch7: entity WORK.DLatch(arch_DLatch)
79. port map (
80. D => Q8_D,
81. CLK => Enable_D,
82. Q => R8_D,
83. QN => \1$N22\ );
84. end architecture arch_DataLatch_D;
```
#### **•** D Latch

**Appendix B– AD7524 converter descriptions in structural VHDL-AMS**

and AD7524 converter.

456 MATLAB Applications for the Practical Engineer

1. library IEEE;

7. port (

4. library EduLib; 5. use WORK.all;

6. entity DataLatch\_D is

25. end entity DataLatch\_D;

35. begin

37. port map ( 38. D => Q1\_D, 39. CLK => Enable\_D, 40. Q => R1\_D, 41. QN => \1\$N2\);

43. port map ( 44. D => Q2\_D,

27. signal \1\$N2\: std\_logic; 28. signal \1\$N5\: std\_logic; 29. signal \1\$N8\: std\_logic; 30. signal \1\$N11\: std\_logic; 31. signal \1\$N23\: std\_logic; 32. signal \1\$N16\: std\_logic; 33. signal \1\$N19\: std\_logic; 34. signal \1\$N22\: std\_logic;

26. architecture arch\_DataLatch\_D of DataLatch\_D is

36. DLatch: entity WORK.DLatch(arch\_DLatch)

42. DLatch1: entity WORK.DLatch(arch\_DLatch)

2. use ieee.std\_logic\_1164.all; 3. use ieee.electrical\_systems.all;

8. signal Q1\_D: in std\_logic; 9. signal Q2\_D: in std\_logic; 10. signal Q3\_D: in std\_logic; 11. signal Q4\_D: in std\_logic; 12. signal Q5\_D: in std\_logic; 13. signal Q6\_D: in std\_logic; 14. signal Q7\_D: in std\_logic; 15. signal Q8\_D: in std\_logic; 16. signal Enable\_D: in std\_logic; 17. signal R1\_D: out std\_logic; 18. signal R2\_D: out std\_logic; 19. signal R3\_D: out std\_logic; 20. signal R4\_D: out std\_logic; 21. signal R5\_D: out std\_logic; 22. signal R6\_D: out std\_logic; 23. signal R7\_D: out std\_logic; 24. signal R8\_D: out std\_logic );

**•** Data\_Latch

The complete VHDL-AMS code is listed below for Data\_Latch subsystem, SNOR subsystem

1. LIBRARY IEEE; 2. USE ieee.std\_logic\_1164.all; 3. USE ieee.electrical\_systems.all; 4. LIBRARY edulib; 5. USE work.all; 6. entity DLatch is 7. port ( 8. signal D: in std\_logic; 9. signal CLK: in std\_logic;

```
10. signal Q: out std_logic;
11. signal QN: out std_logic );
12. end entity DLatch;
13. architecture arch_DLatch of DLatch is
14. begin
15. process(D,CLK)
16. begin
17. if clk = '1' then
18. Q <= D;
19. QN <= not D;
20. end if;
21. end process;
22. end architecture arch_DLatch;
```
5. library EduLib; 6. use WORK.all; 7. entity AD7524 is 8. end entity AD7524;

35. begin

37. port map (

56. port map (

38. Q1\_D => IN1\_D, 39. Q2\_D => IN2\_D, 40. Q3\_D => IN3\_D, 41. Q4\_D => IN4\_D, 42. Q5\_D => IN5\_D, 43. Q6\_D => IN6\_D, 44. Q7\_D => IN7\_D, 45. Q8\_D => IN8\_D, 46. Enable\_D => \1\$N92\, 47. R1\_D => \1\$N68\, 48. R2\_D => \1\$N69\, 49. R3\_D => \1\$N70\, 50. R4\_D => \1\$N71\, 51. R5\_D => \1\$N72\, 52. R6\_D => \1\$N73\, 53. R7\_D => \1\$N74\, 54. R8\_D => \1\$N75\);

9. architecture arch\_AD7524 of AD7524 is

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36. DataLatch\_D: entity WORK.DataLatch\_D(arch\_DataLatch\_D)

55. LadderR2R: entity WORK.LadderR2R(arch\_LadderR2R)

10. signal IN1\_D: std\_logic; 11. signal IN2\_D: std\_logic; 12. signal IN3\_D: std\_logic; 13. signal IN4\_D: std\_logic; 14. signal IN5\_D: std\_logic; 15. signal IN6\_D: std\_logic; 16. signal IN7\_D: std\_logic; 17. signal IN8\_D: std\_logic; 18. signal CS\_D: std\_logic; 19. signal WR\_D: std\_logic; 20. terminal VREF: electrical; 21. terminal OUT1: electrical; 22. terminal OUT2: electrical; 23. signal \1\$N68\: std\_logic; 24. signal \1\$N69\: std\_logic; 25. signal \1\$N70\: std\_logic; 26. signal \1\$N71\: std\_logic; 27. signal \1\$N72\: std\_logic; 28. signal \1\$N73\: std\_logic; 29. signal \1\$N74\: std\_logic; 30. signal \1\$N75\: std\_logic; 31. terminal \1\$N78\: electrical; 32. terminal WR: electrical; 33. terminal CS: electrical; 34. signal \1\$N92\: std\_logic;

#### **•** SNOR

```
1. library IEEE;
2. use ieee.std_logic_1164.all;
3. use ieee.electrical_systems.all;
4. library EduLib;
5. use WORK.all;
6. entity SNOR_D is
7. port (
8. signal IN1_D: in std_logic;
9. signal IN2_D: in std_logic;
10. signal OUT_D: out std_logic );
11. end entity SNOR_D;
12. architecture arch_SNOR_D of SNOR_D is
13. signal \1$N63\: std_logic;
14. signal \1$N64\: std_logic;
15. begin
16. G_AND1: entity EDULIB.AND2
17. port map (
18. IN1 => \1$N63\,
19. IN2 => \1$N64\,
20. OUTPUT => OUT_D);
21. G_NOT1: entity EDULIB.INVERTER
22. port map (
23. INPUT => IN1_D,
24. OUTPUT => \1$N63\);
25. G_NOT2: entity EDULIB.INVERTER
26. port map (
27. INPUT => IN2_D,
28. OUTPUT => \1$N64\);
29. end architecture arch_SNOR_D;
```
#### **•** AD7524

1. library IEEE; 2. use ieee.std\_logic\_1164.all; 3. use ieee.electrical\_systems.all; 4. use ieee.radiant\_systems.all;

```
5. library EduLib;
6. use WORK.all;
7. entity AD7524 is
8. end entity AD7524;
9. architecture arch_AD7524 of AD7524 is
10. signal IN1_D: std_logic;
11. signal IN2_D: std_logic;
12. signal IN3_D: std_logic;
13. signal IN4_D: std_logic;
14. signal IN5_D: std_logic;
15. signal IN6_D: std_logic;
16. signal IN7_D: std_logic;
17. signal IN8_D: std_logic;
18. signal CS_D: std_logic;
19. signal WR_D: std_logic;
20. terminal VREF: electrical;
21. terminal OUT1: electrical;
22. terminal OUT2: electrical;
23. signal \1$N68\: std_logic;
24. signal \1$N69\: std_logic;
25. signal \1$N70\: std_logic;
26. signal \1$N71\: std_logic;
27. signal \1$N72\: std_logic;
28. signal \1$N73\: std_logic;
29. signal \1$N74\: std_logic;
30. signal \1$N75\: std_logic;
31. terminal \1$N78\: electrical;
32. terminal WR: electrical;
33. terminal CS: electrical;
34. signal \1$N92\: std_logic;
35. begin
36. DataLatch_D: entity WORK.DataLatch_D(arch_DataLatch_D)
37. port map (
38. Q1_D => IN1_D,
39. Q2_D => IN2_D,
40. Q3_D => IN3_D,
41. Q4_D => IN4_D,
42. Q5_D => IN5_D,
43. Q6_D => IN6_D,
44. Q7_D => IN7_D,
45. Q8_D => IN8_D,
46. Enable_D => \1$N92\,
47. R1_D => \1$N68\,
48. R2_D => \1$N69\,
49. R3_D => \1$N70\,
50. R4_D => \1$N71\,
51. R5_D => \1$N72\,
52. R6_D => \1$N73\,
53. R7_D => \1$N74\,
54. R8_D => \1$N75\);
55. LadderR2R: entity WORK.LadderR2R(arch_LadderR2R)
56. port map (
```
10. signal Q: out std\_logic; 11. signal QN: out std\_logic );

22. end architecture arch\_DLatch;

2. use ieee.std\_logic\_1164.all; 3. use ieee.electrical\_systems.all;

8. signal IN1\_D: in std\_logic; 9. signal IN2\_D: in std\_logic; 10. signal OUT\_D: out std\_logic );

16. G\_AND1: entity EDULIB.AND2

18. IN1 => \1\$N63\, 19. IN2 => \1\$N64\, 20. OUTPUT => OUT\_D); 21. G\_NOT1: entity EDULIB.INVERTER

23. INPUT => IN1\_D, 24. OUTPUT => \1\$N63\); 25. G\_NOT2: entity EDULIB.INVERTER

27. INPUT => IN2\_D, 28. OUTPUT => \1\$N64\); 29. end architecture arch\_SNOR\_D;

2. use ieee.std\_logic\_1164.all; 3. use ieee.electrical\_systems.all; 4. use ieee.radiant\_systems.all;

12. architecture arch\_SNOR\_D of SNOR\_D is 13. signal \1\$N63\: std\_logic; 14. signal \1\$N64\: std\_logic;

13. architecture arch\_DLatch of DLatch is

12. end entity DLatch;

17. if clk = '1' then

15. process(D,CLK)

14. begin

458 MATLAB Applications for the Practical Engineer

16. begin

**•** SNOR

**•** AD7524

18. Q <= D; 19. QN <= not D; 20. end if; 21. end process;

1. library IEEE;

4. library EduLib; 5. use WORK.all; 6. entity SNOR\_D is

11. end entity SNOR\_D;

17. port map (

22. port map (

26. port map (

1. library IEEE;

7. port (

15. begin

```
57. D1_D => \1$N68\,
58. D2_D => \1$N69\,
59. D3_D => \1$N70\,
60. D4_D => \1$N71\,
61. D5_D => \1$N72\,
62. D6_D => \1$N73\,
63. D7_D => \1$N74\,
64. D8_D => \1$N75\,
65. Out1 => \1$N78\);
66. E_MULT: entity EDULIB.E_MULT
67. port map (
68. IN1 => \1$N78\,
69. IN2 => VREF,
70. OUTPUT => OUT1 );
71. SNOR_D: entity WORK.SNOR_D(arch_SNOR_D)
72. port map (
73. IN1_D => CS_D,
74. IN2_D => WR_D,
75. OUT_D => \1$N92\);
76. E_SUM: entity EDULIB.E_SUM
77. port map (
78. IN1 => \1$N78\,
79. IN2 => VREF,
80. OUTPUT => OUT2 );
81. V_CONT1: entity EDULIB.V_CONSTANT(IDEAL)
82. generic map ( LEVEL => 0.0 )
83. port map ( POS => CS,
84. NEG => ELECTRICAL_REF);
85.
86. A2D_BIT1: entity EDULIB.A2D_BIT(IDEAL)
87. --generic map ( LEVEL => 1.0 )
88. port map (A => CS,
89. D => CS_D);
90. V_CONT2: entity EDULIB.V_CONSTANT(IDEAL)
91. generic map ( LEVEL => 0.0 )
92. port map ( POS => WR,
93. NEG => ELECTRICAL_REF);
94. A2D_BIT2: entity EDULIB.A2D_BIT(IDEAL)
95. --generic map ( LEVEL => 1.0 )
96. port map (A => WR,
97. D => WR_D);
98. V_REF: entity EDULIB.V_CONSTANT(IDEAL)
99. generic map ( LEVEL => 10.0 )
100. port map ( POS => VREF,
101. NEG => ELECTRICAL_REF);
102. end architecture arch_AD7524;
```
**•** Control\_Logic

1. library IEEE;

4. library EduLib; 5. use WORK.all;

7. port (

19. begin

2. use ieee.std\_logic\_1164.all; 3. use ieee.electrical\_systems.all;

8. signal DADB\_D: in std\_logic; 9. signal WR\_D: in std\_logic; 10. signal CS\_D: in std\_logic; 11. signal EnA\_D: out std\_logic; 12. signal EnB\_D: out std\_logic );

14. architecture arch\_ControlLogic\_D of ControlLogic\_D is

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6. entity ControlLogic\_D is

13. end entity ControlLogic\_D;

15. signal \1\$N9\: std\_logic; 16. signal \1\$N2\: std\_logic; 17. signal \1\$N3\: std\_logic; 18. signal \1\$N4\: std\_logic;

20. G\_AND1: entity EDULIB.AND2

22. IN1 => \1\$N2\, 23. IN2 => \1\$N3\, 24. OUTPUT => \1\$N9\); 25. G\_AND2: entity EDULIB.AND2

27. IN1 => \1\$N4\, 28. IN2 => \1\$N9\, 29. OUTPUT => EnA\_D); 30. G\_AND3: entity EDULIB.AND2

32. IN1 => DADB\_D, 33. IN2 => \1\$N9\, 34. OUTPUT => EnB\_D); 35. G\_NOT1: entity EDULIB.INVERTER

37. INPUT => WR\_D, 38. OUTPUT => \1\$N2\); 39. G\_NOT2: entity EDULIB.INVERTER

41. INPUT => CS\_D, 42. OUTPUT => \1\$N3\); 43. G\_NOT3: entity EDULIB.INVERTER

45. INPUT => DADB\_D, 46. OUTPUT => \1\$N4\ ); 47. end architecture arch\_ControlLogic\_D;

21. port map (

26. port map (

31. port map (

36. port map (

40. port map (

44. port map (

**•** AD7528

#### **Appendix C– AD7528 converter descriptions in structural VHDL-AMS**

The complete VHDL-MAS code is listed for Control\_Logic and AD7528 converter.

#### **•** Control\_Logic

57. D1\_D => \1\$N68\, 58. D2\_D => \1\$N69\, 59. D3\_D => \1\$N70\, 60. D4\_D => \1\$N71\, 61. D5\_D => \1\$N72\, 62. D6\_D => \1\$N73\, 63. D7\_D => \1\$N74\, 64. D8\_D => \1\$N75\, 65. Out1 => \1\$N78\); 66. E\_MULT: entity EDULIB.E\_MULT

67. port map (

460 MATLAB Applications for the Practical Engineer

72. port map (

77. port map (

85.

68. IN1 => \1\$N78\, 69. IN2 => VREF,

73. IN1\_D => CS\_D, 74. IN2\_D => WR\_D, 75. OUT\_D => \1\$N92\); 76. E\_SUM: entity EDULIB.E\_SUM

78. IN1 => \1\$N78\, 79. IN2 => VREF,

88. port map (A => CS, 89. D => CS\_D);

96. port map (A => WR, 97. D => WR\_D);

80. OUTPUT => OUT2 );

82. generic map ( LEVEL => 0.0 ) 83. port map ( POS => CS,

84. NEG => ELECTRICAL\_REF);

91. generic map ( LEVEL => 0.0 ) 92. port map ( POS => WR,

93. NEG => ELECTRICAL\_REF); 94. A2D\_BIT2: entity EDULIB.A2D\_BIT(IDEAL) 95. --generic map ( LEVEL => 1.0 )

70. OUTPUT => OUT1 );

71. SNOR\_D: entity WORK.SNOR\_D(arch\_SNOR\_D)

81. V\_CONT1: entity EDULIB.V\_CONSTANT(IDEAL)

86. A2D\_BIT1: entity EDULIB.A2D\_BIT(IDEAL) 87. --generic map ( LEVEL => 1.0 )

90. V\_CONT2: entity EDULIB.V\_CONSTANT(IDEAL)

98. V\_REF: entity EDULIB.V\_CONSTANT(IDEAL) 99. generic map ( LEVEL => 10.0 ) 100. port map ( POS => VREF, 101. NEG => ELECTRICAL\_REF); 102. end architecture arch\_AD7524;

**Appendix C– AD7528 converter descriptions in structural VHDL-AMS**

The complete VHDL-MAS code is listed for Control\_Logic and AD7528 converter.

```
1. library IEEE;
2. use ieee.std_logic_1164.all;
3. use ieee.electrical_systems.all;
4. library EduLib;
5. use WORK.all;
6. entity ControlLogic_D is
7. port (
8. signal DADB_D: in std_logic;
9. signal WR_D: in std_logic;
10. signal CS_D: in std_logic;
11. signal EnA_D: out std_logic;
12. signal EnB_D: out std_logic );
13. end entity ControlLogic_D;
14. architecture arch_ControlLogic_D of ControlLogic_D is
15. signal \1$N9\: std_logic;
16. signal \1$N2\: std_logic;
17. signal \1$N3\: std_logic;
18. signal \1$N4\: std_logic;
19. begin
20. G_AND1: entity EDULIB.AND2
21. port map (
22. IN1 => \1$N2\,
23. IN2 => \1$N3\,
24. OUTPUT => \1$N9\);
25. G_AND2: entity EDULIB.AND2
26. port map (
27. IN1 => \1$N4\,
28. IN2 => \1$N9\,
29. OUTPUT => EnA_D);
30. G_AND3: entity EDULIB.AND2
31. port map (
32. IN1 => DADB_D,
33. IN2 => \1$N9\,
34. OUTPUT => EnB_D);
35. G_NOT1: entity EDULIB.INVERTER
36. port map (
37. INPUT => WR_D,
38. OUTPUT => \1$N2\);
39. G_NOT2: entity EDULIB.INVERTER
40. port map (
41. INPUT => CS_D,
42. OUTPUT => \1$N3\);
43. G_NOT3: entity EDULIB.INVERTER
44. port map (
45. INPUT => DADB_D,
46. OUTPUT => \1$N4\ );
47. end architecture arch_ControlLogic_D;
```
**•** AD7528

```
1. library IEEE;
2. use ieee.std_logic_1164.all;
3. use ieee.electrical_systems.all;
4. library EduLib;
5. use WORK.all;
6. entity AD7528 is
7. end entity AD7528;
8. architecture arch_AD7528 of AD7528 is
9. signal IN1_D: std_logic;
10. signal IN2_D: std_logic;
11. signal IN3_D: std_logic;
12. signal IN4_D: std_logic;
13. signal IN5_D: std_logic;
14. signal IN6_D: std_logic;
15. signal IN7_D: std_logic;
16. signal IN8_D: std_logic;
17. signal DA_DB_D: std_logic;
18. signal WR_D: std_logic;
19. signal CS_D: std_logic;
20. terminal CS: electrical;
21. terminal WR: electrical;
22. terminal DA_DB: electrical;
23. terminal VrefA: electrical;
24. terminal VrefB: electrical;
25. terminal Out1A: electrical;
26. terminal Out1B: electrical;
27. signal \1$N204\: std_logic;
28. signal \1$N205\: std_logic;
29. begin
30. ControlLogic_D: entity WORK.ControlLogic_D(arch_ControlLogic_D)
31. port map (
32. DADB_D => DA_DB_D,
33. WR_D => WR_D,
34. CS_D => CS_D,
35. EnA_D => \1$N204\,
36. EnB_D => \1$N205\ );
37. DAC_A: entity WORK.DAC_A(arch_DAC_A)
38. port map (
39. A1_D => IN1_D,
40. A2_D => IN2_D,
41. A3_D => IN3_D,
42. A4_D => IN4_D,
43. A5_D => IN5_D,
44. A6_D => IN6_D,
45. A7_D => IN7_D,
46. A8_D => IN8_D,
47. VrefA_I => VrefA,
48. EnA_D => \1$N204\,
49. OutA => Out1A );
50. DAC_B: entity WORK.DAC_B(arch_DAC_B)
51. port map (
52. B1_D => IN1_D,
```
53. B2\_D => IN2\_D, 54. B3\_D => IN3\_D, 55. B4\_D => IN4\_D, 56. B5\_D => IN5\_D, 57. B6\_D => IN6\_D, 58. B7\_D => IN7\_D, 59. B8\_D => IN8\_D, 60. VrefB\_I => VrefB, 61. EnB\_D => \1\$N205\, 62. OutB => Out1B );

63. V\_CONST1: entity EDULIB.V\_CONSTANT(IDEAL)

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71. V\_CONST2: entity EDULIB.V\_CONSTANT(IDEAL)

79. V\_CONST3: entity EDULIB.V\_CONSTANT(IDEAL)

87. V\_REFA: entity EDULIB.V\_CONSTANT(IDEAL)

91. V\_REFB: entity EDULIB.V\_CONSTANT(IDEAL)

The authors would like to thank to National Council for Scientific and Technological Devel‐

64. generic map ( LEVEL => 0.0 ) 65. port map ( POS => CS,

66. NEG => ELECTRICAL\_REF); 67. A2D\_BIT1: entity EDULIB.A2D\_BIT(IDEAL) 68. --generic map ( LEVEL => 1.0 )

72. generic map ( LEVEL => 0.0 ) 73. port map ( POS => WR,

74. NEG => ELECTRICAL\_REF); 75. A2D\_BIT2: entity EDULIB.A2D\_BIT(IDEAL) 76. --generic map ( LEVEL => 1.0 )

80. generic map ( LEVEL => 0.0 ) 81. port map ( POS => DA\_DB, 82. NEG => ELECTRICAL\_REF); 83. A2D\_BIT3: entity EDULIB.A2D\_BIT(IDEAL) 84. --generic map ( THRES => 1.0 )

88. generic map ( LEVEL => 16.0 ) 89. port map ( POS => VrefA, 90. NEG => ELECTRICAL\_REF);

92. generic map ( LEVEL => 10.0 ) 93. port map ( POS => VrefB, 94. NEG => ELECTRICAL\_REF 95. end architecture arch\_AD7528;

opment (CNPq, process: 141744/2010-3 and 309023/2012-2).

**Acknowledgements**

85. port map (A => DA\_DB, 86. D => DA\_DB\_D);

69. port map (A => CS, 70. D => CS\_D);

77. port map (A => WR, 78. D => WR\_D);


#### **Acknowledgements**

1. library IEEE;

462 MATLAB Applications for the Practical Engineer

4. library EduLib; 5. use WORK.all; 6. entity AD7528 is 7. end entity AD7528;

29. begin

31. port map (

38. port map (

51. port map (

52. B1\_D => IN1\_D,

39. A1\_D => IN1\_D, 40. A2\_D => IN2\_D, 41. A3\_D => IN3\_D, 42. A4\_D => IN4\_D, 43. A5\_D => IN5\_D, 44. A6\_D => IN6\_D, 45. A7\_D => IN7\_D, 46. A8\_D => IN8\_D, 47. VrefA\_I => VrefA, 48. EnA\_D => \1\$N204\, 49. OutA => Out1A );

50. DAC\_B: entity WORK.DAC\_B(arch\_DAC\_B)

32. DADB\_D => DA\_DB\_D, 33. WR\_D => WR\_D, 34. CS\_D => CS\_D, 35. EnA\_D => \1\$N204\, 36. EnB\_D => \1\$N205\ ); 37. DAC\_A: entity WORK.DAC\_A(arch\_DAC\_A)

2. use ieee.std\_logic\_1164.all; 3. use ieee.electrical\_systems.all;

9. signal IN1\_D: std\_logic; 10. signal IN2\_D: std\_logic; 11. signal IN3\_D: std\_logic; 12. signal IN4\_D: std\_logic; 13. signal IN5\_D: std\_logic; 14. signal IN6\_D: std\_logic; 15. signal IN7\_D: std\_logic; 16. signal IN8\_D: std\_logic; 17. signal DA\_DB\_D: std\_logic; 18. signal WR\_D: std\_logic; 19. signal CS\_D: std\_logic; 20. terminal CS: electrical; 21. terminal WR: electrical; 22. terminal DA\_DB: electrical; 23. terminal VrefA: electrical; 24. terminal VrefB: electrical; 25. terminal Out1A: electrical; 26. terminal Out1B: electrical; 27. signal \1\$N204\: std\_logic; 28. signal \1\$N205\: std\_logic;

8. architecture arch\_AD7528 of AD7528 is

30. ControlLogic\_D: entity WORK.ControlLogic\_D(arch\_ControlLogic\_D)

The authors would like to thank to National Council for Scientific and Technological Devel‐ opment (CNPq, process: 141744/2010-3 and 309023/2012-2).

#### **Author details**

Tiago da Silva Almeida1 , Ian Andrew Grout2 and Alexandre César Rodrigues da Silva1 [12] Matrosova A, Ostanin S. Self-cheking FSM design with observing only FSM output. In: IEEE On-Line Testing Workshop, 2000, Palma de Mallorca, Spain; 2000.

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[13] Xia L, Bell I M, Wilkison A J. Automated model generation algorithm for high-level fault modeling. IEEE Transaction on Computer-Aided Design of Integrated Circuits

[14] Correa I S et al. VHDL Implementation of a Flexible and Synthesizable FFT Process‐

[15] Kapre N, Dehon A. SPICE2: Spatial Processors Interconnected for Concurrent Execu‐ tion for Accelerating the SPICE Circuit Simulator Using an FPGA. IEEE Transactions On Computer-aided Design of Integrated Circuits and Systems 2012; 31(1) 9-22.

[16] Zorzi M, Franzè F, Speciale N. Construction of VHDL-AMS simulator in MatlabTM. In: Proceedings Of The 2003 International Workshop On Behavioral Modeling, 2003,

[17] Camera K. SF2VHD: A Stateflow to VHDL Translator. Master degrees. University of

[18] Sbarcea B, Nicula D. Automatic Conversion of MATLAB/Simulink Models to HDL Models. http://www.fcd.co.il/doc/optim2004.pdf (accessed 20 September 2012).

[19] Mirotznik M S. Translating MATLAB programs into C code. IEEE Spectrum 1996;

[20] Shen S et al. Inferring Assertion for Complementary Synthesis. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2012; 31(8) 1288-1292.

[21] Sinha R, Patel H D. synASM: A High-Level Synthesis Framework With Support for Parallel and Timed Constructs. IEEE Transactions on Computer-Aided Design of In‐

[22] Liu H et al. Automatic Decoder Synthesis: Methods and Case Studies. IEEE Transac‐ tions on Computer-Aided Design of Integrated Circuits and Systems 2001; 31(9)

[23] Poikonen J H, Lehtonen E, Laiho M. On Synthesis of Boolean Expressions for Mem‐ ristive Devices Using Sequential Implication Logic. IEEE Transactions on Computer-

[24] Wu X et al. Research and Application of Code Automatic Generation Algorithm Based on Structured Flowchar. Journal of Software Engineering and Applications

[25] Lien W et al. Counter-Based Output Selection for Test Response Compaction. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 2013;

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1 Univ Estadual Paulista, UNESP, Brazil

2 University of Limerik, UL, Ireland

#### **References**


[12] Matrosova A, Ostanin S. Self-cheking FSM design with observing only FSM output. In: IEEE On-Line Testing Workshop, 2000, Palma de Mallorca, Spain; 2000.

**Author details**

**References**

11-14.

Tiago da Silva Almeida1

464 MATLAB Applications for the Practical Engineer

1 Univ Estadual Paulista, UNESP, Brazil

2 University of Limerik, UL, Ireland

, Ian Andrew Grout2

[1] Gerstlauer A, Haubelt C, Pimentel A D, Stefanov T P, Gajski D D, Teich J. Electronic System-Level Synthesis Methodologies. Computer-Aided Design of Integrated Cir‐

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[3] Riesgo T, Torroja Y, Torre E. Design methodologies based on hardware description

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[5] Tocci R J, Widmer N S, Moss G L. Digital Systems: Principles and Applications. New

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2002.


**Chapter 16**

**Provisional chapter**

**DC/DC Boost-Boost power converter as a didactic**

**DC/DC Boost-Boost power converter as a didactic**

**current and voltage probes**

R. Silva-Ortigoza, M. Antonio-Cruz,

A. Merlo-Zapata1 and P. Pérez-Romero1

http://dx.doi.org/10.5772/58243

10.5772/58243

**1. Introduction**

M. Marcelino-Aranda, G. Saldaña-González, C. A. Merlo-Zapata and P. Pérez-Romero

**via current and voltage probes**

Additional information is available at the end of the chapter

Additional information is available at the end of the chapter

their importance and multiple applications [9–13].

**system: Experimental results with Matlab/Simulink via**

R. Silva-Ortigoza1, M. Antonio-Cruz1, M. Marcelino-Aranda2, G. Saldaña-González3, C.

Great efforts have been made by undergraduate and postgraduate educators in the field of theory validation through experimentation, with the purpose of students gaining better skills during their academic training, motivating the development of didactic prototypes that contribute to this goal. The importance of using such didactic materials can be seen in papers published in journals indexed in Journal Citation Reports [1], the main intention of which is

Theoretical learning about electric circuit analysis at bachelor level, in specialized engineering (such as electronics, electrical, automatic control, bionics, robotics, mechatronics, etc.) and basic sciences (such as physics and mathematics), can be easily grasped by students if they are able to validate this knowledge experimentally. Herein, this fact represents the main motivation for developing a didactic material where power electronics advances are considered, particularly the ones related to the DC/DC Boost-Boost power converter, due to

Educational contributions have been reported in the field of analysis, design, modeling, simulation, construction or control of DC/DC power converters as follows. In 2007, Sandoval-Ibarra *et al.* [14] proposed a DC/DC Boost converter design as well as power electronics definitions associated with simple electrical networks. Additionally, in the same year, Sandoval-Ibarra *et al.* [15] introduced an alternative analysis of switched circuits in order to design square wave generators for DC/DC and DC/AC converters. Dudrik and Bauer in 2008 [16] described techniques in the teaching of power electronics converters and devices for undergraduate students through e-learning methods. In 2010, in the

> ©2012 Silva-Ortigoza et al., licensee InTech. This is an open access chapter distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. © 2014 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

to spread research of this nature, from engineering [2–6] to physics [7, 8].

**system: Experimental results with Matlab/Simulink**

**Provisional chapter**

#### **DC/DC Boost-Boost power converter as a didactic system: Experimental results with Matlab/Simulink via current and voltage probes DC/DC Boost-Boost power converter as a didactic system: Experimental results with Matlab/Simulink via current and voltage probes**

R. Silva-Ortigoza, M. Antonio-Cruz, M. Marcelino-Aranda, G. Saldaña-González, C. A. Merlo-Zapata and P. Pérez-Romero R. Silva-Ortigoza1, M. Antonio-Cruz1, M. Marcelino-Aranda2, G. Saldaña-González3, C. A. Merlo-Zapata1 and P. Pérez-Romero1

Additional information is available at the end of the chapter

Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/58243 10.5772/58243

#### **1. Introduction**

Great efforts have been made by undergraduate and postgraduate educators in the field of theory validation through experimentation, with the purpose of students gaining better skills during their academic training, motivating the development of didactic prototypes that contribute to this goal. The importance of using such didactic materials can be seen in papers published in journals indexed in Journal Citation Reports [1], the main intention of which is to spread research of this nature, from engineering [2–6] to physics [7, 8].

Theoretical learning about electric circuit analysis at bachelor level, in specialized engineering (such as electronics, electrical, automatic control, bionics, robotics, mechatronics, etc.) and basic sciences (such as physics and mathematics), can be easily grasped by students if they are able to validate this knowledge experimentally. Herein, this fact represents the main motivation for developing a didactic material where power electronics advances are considered, particularly the ones related to the DC/DC Boost-Boost power converter, due to their importance and multiple applications [9–13].

Educational contributions have been reported in the field of analysis, design, modeling, simulation, construction or control of DC/DC power converters as follows. In 2007, Sandoval-Ibarra *et al.* [14] proposed a DC/DC Boost converter design as well as power electronics definitions associated with simple electrical networks. Additionally, in the same year, Sandoval-Ibarra *et al.* [15] introduced an alternative analysis of switched circuits in order to design square wave generators for DC/DC and DC/AC converters. Dudrik and Bauer in 2008 [16] described techniques in the teaching of power electronics converters and devices for undergraduate students through e-learning methods. In 2010, in the

Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. © 2014 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

©2012 Silva-Ortigoza et al., licensee InTech. This is an open access chapter distributed under the terms of the

study of Pejovi´c [17], expressions for the discontinuous conduction mode of basic power converters were inferred, relating the output current and output voltage independently to the load type. Likewise, it was mentioned that the method was verified in teaching practice. Campos-Delgado and Espinoza-Trejo in 2010 [18] presented the analysis and construction of the DC/DC Buck, Boost and Buck-Boost power converters. In addition, the design and experimental implementation of proportional integral (PI) controllers for these converters were accomplished. Thus, Altintas in 2011 [19] elaborated an educational graphical user interface (GUI) for the simulation of various topologies of power electronic converters which students can use in order to explore their behavior. The GUI was developed by using Matlab/Simulink, SimPowerSystems, and the GUIDE tool of Matlab, which acts as a front-end that can be used for teaching as well as learning of power converters theory. Also, Abramovitz in 2011 [20] suggested a pedagogical approach to teaching the subject of average modeling of PWM switched-mode power electronics systems through simulation by general-purpose electronic circuit simulators. In 2011, in the work of Deblecker [21] a pre-processing approach was considered. It was based on the Σ − ∆ technique for increasing the effective resolution of a digital pulse-width modulator in a voltage-mode controlled Buck converter. Numerical simulations by using Matlab/Simulink allowed the effectiveness of that approach to be verified, and a low-cost development board showed its real behavior. On the other hand, in 2011 Zumel *et al.* [22] designed and implemented, step-by-step, a linear compensator based on a field programmable gate array for a DC/DC Buck power converter. This contribution was oriented to power electronics introductory courses for undergraduate or graduate levels. Recently, in 2012, Liao *et al.* [23] reported a modeling technique for designing switched-mode power supplies (SMPS) aided by Matlab/Simulink. Experimental validation of that technique for the DC/DC Buck power converter, and other SMPS topologies, was realized. Further, in 2012 Lamar *et al.* [24] introduced a problem-based learning method included in a SMPS course, by means of two practical projects: the design and construction of a SMPS prototype (Boost converter), and the static study of a DC/DC power converter topology. Another important contribution that was provided by Silva-Ortigoza *et al.* [25] in 2012 described the model, simulation, construction, and the experimental verifying associated with a DC/DC Boost power converter, as a didactic material intended to support courses on electric circuit analysis. In contrast with this previous work, Choi and Saeedifard [26] in 2012 showed a description of the set of hardware and software tools installed in the power electronics laboratory, constructed at Purdue University, West Lafayette, IN., which was developed primarily to reinforce, experimentally, the fundamental concepts presented in a power electronics course. This facility is used for the design, simulation, control, construction, and verification of power electronic circuits. Finally, work associated with the synthesis or control of DC/DC power converters has been reported [9–11, 27–31].

10.5772/58243

471

voltage probes

http://dx.doi.org/10.5772/58243

representation is more appropriate as the one to be presented for the Boost-Boost converter

DC/DC Boost-Boost power converter as a didactic system: Experimental results with Matlab/Simulink via current and

Thus, the main aim of this work is the modeling, design, simulation, and construction of a prototype associated with a DC/DC Boost-Boost converter to validate its mathematical model, using Kirchhoff current and voltage laws, via experimental tests. This, with the intention of enhancing the acquired theoretical knowledge for students in electric circuit analysis courses. Finally, the simulations are performed using Matlab/Simulink as Simulink provides a graphical environment to the user that facilitates the analysis, design and construction of dynamic systems. Several examples of this software's applications have been presented [9, 11, 19, 21, 23, 26]. Also, books associated with theory, real-world examples, and exercises using either MATLAB or Simulink (MathWorks products) can be found in [32]. On the other hand, the experimental results are obtained using some software tools and laboratory equipment, such as: Matlab/Simulink, a dSPACE DS1104 board [33], current and

The work is structured as follows. In Section 2 the mathematical model of the DC/DC Boost-Boost power converter is developed. Matlab/Simulink simulations associated with such a converter are presented in Section 3. The construction of the converter prototype is described in Section 4. Moreover, the experimental validation is developed and analyzed in

This section is divided into two parts: the first one deals with the mathematical model deduction via Kirchhoff voltage and current laws for the Boost-Boost power converter, and the second part is related to obtaining the properties of such a converter in steady-state using

On the one hand, the Boost-Boost converter is composed of two DC/DC Boost power converters connected in cascade. As a consequence, the ideal circuit representation of the DC/DC Boost-Boost power converter, that is, the converter synthesized with switches, is the one shown in Figure 1. On the other hand, herein is presented an alternative circuit representation for the converter under study, using MOSFET transistors as switches, as

In the system shown in Figure 1, inputs *u*<sup>1</sup> and *u*<sup>2</sup> can take values in the discrete set {0, 1}, corresponding to the positions of the switches *S*<sup>1</sup> and *S*2, respectively. These positions are set in practice by using transistors (*Q*<sup>1</sup> and *Q*2) in on/off operating mode. The transistors in

Section 5. Finally, Section 6 is devoted to the conclusions and future research.

**2. Modeling and analysis of a DC/DC Boost-Boost power converter**

voltage probes, a power supply, and a function generator.

**2.1. Boost-Boost power converter modeling**

**Figure 1.** DC/DC Boost-Boost power converter ideal circuit.

in this work.

its average model.

shown in Figure 2.

Having undertaken the educational literature review associated with DC/DC power electronic converters, on the one hand, it was found that the modeling of such converters, generally, was based on equivalent models, validated by specialized software, without deducing the corresponding mathematical models. Also, usually numerical simulations were introduced instead of using experimental implementation. On the other hand, even though the DC/DC power converters, essentially nonlinear, have been controlled via classic control techniques, in the educational literature, generally, modern control techniques have not been proposed for them. For such an aim, the converter models based on state-space representation is more appropriate as the one to be presented for the Boost-Boost converter in this work.

Thus, the main aim of this work is the modeling, design, simulation, and construction of a prototype associated with a DC/DC Boost-Boost converter to validate its mathematical model, using Kirchhoff current and voltage laws, via experimental tests. This, with the intention of enhancing the acquired theoretical knowledge for students in electric circuit analysis courses. Finally, the simulations are performed using Matlab/Simulink as Simulink provides a graphical environment to the user that facilitates the analysis, design and construction of dynamic systems. Several examples of this software's applications have been presented [9, 11, 19, 21, 23, 26]. Also, books associated with theory, real-world examples, and exercises using either MATLAB or Simulink (MathWorks products) can be found in [32]. On the other hand, the experimental results are obtained using some software tools and laboratory equipment, such as: Matlab/Simulink, a dSPACE DS1104 board [33], current and voltage probes, a power supply, and a function generator.

The work is structured as follows. In Section 2 the mathematical model of the DC/DC Boost-Boost power converter is developed. Matlab/Simulink simulations associated with such a converter are presented in Section 3. The construction of the converter prototype is described in Section 4. Moreover, the experimental validation is developed and analyzed in Section 5. Finally, Section 6 is devoted to the conclusions and future research.

### **2. Modeling and analysis of a DC/DC Boost-Boost power converter**

This section is divided into two parts: the first one deals with the mathematical model deduction via Kirchhoff voltage and current laws for the Boost-Boost power converter, and the second part is related to obtaining the properties of such a converter in steady-state using its average model.

#### **2.1. Boost-Boost power converter modeling**

2

reported [9–11, 27–31].

study of Pejovi´c [17], expressions for the discontinuous conduction mode of basic power converters were inferred, relating the output current and output voltage independently to the load type. Likewise, it was mentioned that the method was verified in teaching practice. Campos-Delgado and Espinoza-Trejo in 2010 [18] presented the analysis and construction of the DC/DC Buck, Boost and Buck-Boost power converters. In addition, the design and experimental implementation of proportional integral (PI) controllers for these converters were accomplished. Thus, Altintas in 2011 [19] elaborated an educational graphical user interface (GUI) for the simulation of various topologies of power electronic converters which students can use in order to explore their behavior. The GUI was developed by using Matlab/Simulink, SimPowerSystems, and the GUIDE tool of Matlab, which acts as a front-end that can be used for teaching as well as learning of power converters theory. Also, Abramovitz in 2011 [20] suggested a pedagogical approach to teaching the subject of average modeling of PWM switched-mode power electronics systems through simulation by general-purpose electronic circuit simulators. In 2011, in the work of Deblecker [21] a pre-processing approach was considered. It was based on the Σ − ∆ technique for increasing the effective resolution of a digital pulse-width modulator in a voltage-mode controlled Buck converter. Numerical simulations by using Matlab/Simulink allowed the effectiveness of that approach to be verified, and a low-cost development board showed its real behavior. On the other hand, in 2011 Zumel *et al.* [22] designed and implemented, step-by-step, a linear compensator based on a field programmable gate array for a DC/DC Buck power converter. This contribution was oriented to power electronics introductory courses for undergraduate or graduate levels. Recently, in 2012, Liao *et al.* [23] reported a modeling technique for designing switched-mode power supplies (SMPS) aided by Matlab/Simulink. Experimental validation of that technique for the DC/DC Buck power converter, and other SMPS topologies, was realized. Further, in 2012 Lamar *et al.* [24] introduced a problem-based learning method included in a SMPS course, by means of two practical projects: the design and construction of a SMPS prototype (Boost converter), and the static study of a DC/DC power converter topology. Another important contribution that was provided by Silva-Ortigoza *et al.* [25] in 2012 described the model, simulation, construction, and the experimental verifying associated with a DC/DC Boost power converter, as a didactic material intended to support courses on electric circuit analysis. In contrast with this previous work, Choi and Saeedifard [26] in 2012 showed a description of the set of hardware and software tools installed in the power electronics laboratory, constructed at Purdue University, West Lafayette, IN., which was developed primarily to reinforce, experimentally, the fundamental concepts presented in a power electronics course. This facility is used for the design, simulation, control, construction, and verification of power electronic circuits. Finally, work associated with the synthesis or control of DC/DC power converters has been

Having undertaken the educational literature review associated with DC/DC power electronic converters, on the one hand, it was found that the modeling of such converters, generally, was based on equivalent models, validated by specialized software, without deducing the corresponding mathematical models. Also, usually numerical simulations were introduced instead of using experimental implementation. On the other hand, even though the DC/DC power converters, essentially nonlinear, have been controlled via classic control techniques, in the educational literature, generally, modern control techniques have not been proposed for them. For such an aim, the converter models based on state-space On the one hand, the Boost-Boost converter is composed of two DC/DC Boost power converters connected in cascade. As a consequence, the ideal circuit representation of the DC/DC Boost-Boost power converter, that is, the converter synthesized with switches, is the one shown in Figure 1. On the other hand, herein is presented an alternative circuit representation for the converter under study, using MOSFET transistors as switches, as shown in Figure 2.

**Figure 1.** DC/DC Boost-Boost power converter ideal circuit.

In the system shown in Figure 1, inputs *u*<sup>1</sup> and *u*<sup>2</sup> can take values in the discrete set {0, 1}, corresponding to the positions of the switches *S*<sup>1</sup> and *S*2, respectively. These positions are set in practice by using transistors (*Q*<sup>1</sup> and *Q*2) in on/off operating mode. The transistors in

10.5772/58243

473

voltage probes

http://dx.doi.org/10.5772/58243

(a) Equivalent circuit I: *u*<sup>1</sup> = 1 and *u*<sup>2</sup> = 1.

DC/DC Boost-Boost power converter as a didactic system: Experimental results with Matlab/Simulink via current and

(b) Equivalent circuit II: *u*<sup>1</sup> = 1 and *u*<sup>2</sup> = 0.

(c) Equivalent circuit III: *u*<sup>1</sup> = 0 and *u*<sup>2</sup> = 1.

(d) Equivalent circuit IV: *u*<sup>1</sup> = 0 and *u*<sup>2</sup> = 0.

Moreover, applying KCL for nodes A and B in Figure 3(a), the differential equations

*dt* <sup>=</sup> <sup>−</sup> *<sup>υ</sup>*<sup>2</sup>

b) *Equivalent circuit II* is generated when *Q*<sup>1</sup> conducts and *Q*<sup>2</sup> does not conduct, that is, *u*<sup>1</sup> = 1 and *u*<sup>2</sup> = 0, then the diode *D*<sup>1</sup> is reverse biased and diode *D*<sup>2</sup> is forward biased. Thus, the corresponding equivalent circuit is shown in Figure 3(b). Applying KVL to

*R*1

*RL*

− *i*2, (3)

. (4)

*C*1 *dυ*<sup>1</sup> *dt* <sup>=</sup> <sup>−</sup> *<sup>υ</sup>*<sup>1</sup>

*C*2 *dυ*<sup>2</sup>

**Figure 3.** DC/DC Boost-Boost power converter operating modes.

related to voltages *υ*<sup>1</sup> and *υ*<sup>2</sup> are obtained by

**Figure 2.** DC/DC Boost-Boost power converter circuit implemented with transistors.

the on-state are equivalent to the positions *u*<sup>1</sup> = 1 and *u*<sup>2</sup> = 1, and the off-states correspond to the positions *u*<sup>1</sup> = 0 and *u*<sup>2</sup> = 0. In the derivation of the mathematical model for the converter it is assumed that the circuit operates in continuous conduction mode, that is, the average value of the inductors currents are never lower than zero [29]. The variables *i*1, *υ*1, *i*2, and *υ*<sup>2</sup> correspond to the currents and voltages associated to *L*1, *C*1, *L*2, and *C*2, respectively. The loads are represented by *R*<sup>1</sup> and *RL*, which correspond to each output stage of the Boost converters that compose the Boost-Boost converter. Finally, *E* denotes the power converter primary supply source.

An important feature of the Boost-Boost converter output voltage *υ*2, is that it satisfies the following condition:

$$v\_2 \ge E\_{\prime\prime}$$

which can be shown by analyzing such a converter in steady-state. This is the reason why this converter is also known as a double step-up converter.

From Figure 1 and the Kirchhoff voltage and current laws (abbreviated to KVL and KCL, respectively), the switched model, which describes the Boost-Boost converter dynamic evolution, is obtained as follows.


The aforementioned process is accomplished as follows:

a) *Equivalent Circuit I* occurs when transistors *Q*<sup>1</sup> and *Q*<sup>2</sup> conduct, that is, *u*<sup>1</sup> = 1 and *u*<sup>2</sup> = 1, and diodes *D*<sup>1</sup> and *D*<sup>2</sup> are reverse biased. Then, the equivalent circuit is shown in Figure 3(a). Applying KVL to meshes I and II, the following equations for the currents *i*<sup>1</sup> and *i*2, respectively, are obtained:

$$L\_1 \frac{di\_1}{dt} = E\_\prime \tag{1}$$

$$L\_2 \frac{di\_2}{dt} = v\_1. \tag{2}$$

<sup>472</sup> MATLAB Applications for the Practical Engineer DC/DC Boost-Boost power converter as a didactic system: Experimental results with Matlab/Simulink via current and voltage probes 10.5772/58243 DC/DC Boost-Boost power converter as a didactic system: Experimental results with Matlab/Simulink via current and voltage probes http://dx.doi.org/10.5772/58243 473

(b) Equivalent circuit II: *u*<sup>1</sup> = 1 and *u*<sup>2</sup> = 0.

(c) Equivalent circuit III: *u*<sup>1</sup> = 0 and *u*<sup>2</sup> = 1.

(d) Equivalent circuit IV: *u*<sup>1</sup> = 0 and *u*<sup>2</sup> = 0.

**Figure 3.** DC/DC Boost-Boost power converter operating modes.

**Figure 2.** DC/DC Boost-Boost power converter circuit implemented with transistors.

this converter is also known as a double step-up converter.

equations, which describes the converter's nonlinear dynamics.

The aforementioned process is accomplished as follows:

primary supply source.

evolution, is obtained as follows.

respectively, are obtained:

following condition:

generated.

the on-state are equivalent to the positions *u*<sup>1</sup> = 1 and *u*<sup>2</sup> = 1, and the off-states correspond to the positions *u*<sup>1</sup> = 0 and *u*<sup>2</sup> = 0. In the derivation of the mathematical model for the converter it is assumed that the circuit operates in continuous conduction mode, that is, the average value of the inductors currents are never lower than zero [29]. The variables *i*1, *υ*1, *i*2, and *υ*<sup>2</sup> correspond to the currents and voltages associated to *L*1, *C*1, *L*2, and *C*2, respectively. The loads are represented by *R*<sup>1</sup> and *RL*, which correspond to each output stage of the Boost converters that compose the Boost-Boost converter. Finally, *E* denotes the power converter

An important feature of the Boost-Boost converter output voltage *υ*2, is that it satisfies the

*υ*<sup>2</sup> ≥ *E*,

which can be shown by analyzing such a converter in steady-state. This is the reason why

From Figure 1 and the Kirchhoff voltage and current laws (abbreviated to KVL and KCL, respectively), the switched model, which describes the Boost-Boost converter dynamic

1/2. –The on/off states of transistors *Q*<sup>1</sup> and *Q*<sup>2</sup> are considered to generate the four equivalent circuits shown in Figure 3, each circuit is represented by a fourth-order-differential equations subsystem. Thus, four mathematical subsystems are

2/2. –These four subsystems are integrated only in a system of fourth-order differential

a) *Equivalent Circuit I* occurs when transistors *Q*<sup>1</sup> and *Q*<sup>2</sup> conduct, that is, *u*<sup>1</sup> = 1 and *u*<sup>2</sup> = 1, and diodes *D*<sup>1</sup> and *D*<sup>2</sup> are reverse biased. Then, the equivalent circuit is shown in Figure 3(a). Applying KVL to meshes I and II, the following equations for the currents *i*<sup>1</sup> and *i*2,

> *L*1 *di*<sup>1</sup>

> *L*2 *di*<sup>2</sup>

*dt* <sup>=</sup> *<sup>E</sup>*, (1)

*dt* <sup>=</sup> *<sup>υ</sup>*1. (2)

Moreover, applying KCL for nodes A and B in Figure 3(a), the differential equations related to voltages *υ*<sup>1</sup> and *υ*<sup>2</sup> are obtained by

$$C\_1 \frac{dv\_1}{dt} = -\frac{v\_1}{R\_1} - i\_{2\prime} \tag{3}$$

$$C\_2 \frac{dv\_2}{dt} = -\frac{v\_2}{R\_L}.\tag{4}$$

b) *Equivalent circuit II* is generated when *Q*<sup>1</sup> conducts and *Q*<sup>2</sup> does not conduct, that is, *u*<sup>1</sup> = 1 and *u*<sup>2</sup> = 0, then the diode *D*<sup>1</sup> is reverse biased and diode *D*<sup>2</sup> is forward biased. Thus, the corresponding equivalent circuit is shown in Figure 3(b). Applying KVL to meshes I and II the equations for *i*<sup>1</sup> and *i*2, respectively, are obtained:

$$L\_1 \frac{di\_1}{dt} = E\_\prime \tag{5}$$

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Equations related to *i*1, (1), (5), (9), and (13), can be associated, using *u*1, producing (17). The dynamics associated with *υ*<sup>1</sup> is obtained from a combination of (3), (7), (11), and (15) through *u*1, generating (18). The unification of (2), (6), (10), and (14) through *u*2, produces the dynamics associated to *i*2, determined by (19). Following a similar process for *υ*2, associating (4), (8), (12), and (16), (20) is produced. Thus, the Boost-Boost converter dynamics

DC/DC Boost-Boost power converter as a didactic system: Experimental results with Matlab/Simulink via current and

*dt* <sup>=</sup> (<sup>1</sup> <sup>−</sup> *<sup>u</sup>*1)*i*<sup>1</sup> <sup>−</sup> *<sup>υ</sup>*<sup>1</sup>

*dt* <sup>=</sup> (<sup>1</sup> <sup>−</sup> *<sup>u</sup>*2)*i*<sup>2</sup> <sup>−</sup> *<sup>υ</sup>*<sup>2</sup>

This is called the converter *switched model* referring to the binary values associated with the

In order to know the Boost-Boost converter properties in steady-state its average model is

*dt* <sup>=</sup> (<sup>1</sup> <sup>−</sup> *<sup>u</sup>*1*av*)*i*<sup>1</sup> <sup>−</sup> *<sup>υ</sup>*<sup>1</sup>

*dt* <sup>=</sup> (<sup>1</sup> <sup>−</sup> *<sup>u</sup>*2*av*)*i*<sup>2</sup> <sup>−</sup> *<sup>υ</sup>*<sup>2</sup>

where *i*1, *υ*1, *i*2, and *υ*<sup>2</sup> now denote average currents and voltages associated with *L*1, *C*1, *L*2, and *C*2, respectively, whereas *u*1*av* and *u*2*av* represent average position functions of the

No distinction is made between the variables of the average model (21)–(24) and the switched model (17)–(20). However, in order to distinguish one model from the other, the inputs to the average model are denoted by *u*1*av* and *u*2*av*, and the inputs of the switched model are denoted by *u*<sup>1</sup> and *u*2. This difference is used in the rest of the work. Furthermore, it is important to note that theoretical justification of the average models has been extensively

*dt* <sup>=</sup> <sup>−</sup> (<sup>1</sup> <sup>−</sup> *<sup>u</sup>*1) *<sup>υ</sup>*<sup>1</sup> <sup>+</sup> *<sup>E</sup>*, (17)

*dt* <sup>=</sup> *<sup>υ</sup>*<sup>1</sup> <sup>−</sup> (<sup>1</sup> <sup>−</sup> *<sup>u</sup>*2) *<sup>υ</sup>*2, (19)

*dt* <sup>=</sup> <sup>−</sup> (<sup>1</sup> <sup>−</sup> *<sup>u</sup>*1*av*) *<sup>υ</sup>*<sup>1</sup> <sup>+</sup> *<sup>E</sup>*, (21)

*dt* <sup>=</sup> *<sup>υ</sup>*<sup>1</sup> <sup>−</sup> (<sup>1</sup> <sup>−</sup> *<sup>u</sup>*2*av*) *<sup>υ</sup>*2, (23)

*R*1

*RL*

− *i*2, (18)

. (20)

− *i*2, (22)

, (24)

*R*1

*RL*

is determined by the following nonlinear differential equations system:

*L*1 *di*1

*C*1 *dυ*<sup>1</sup>

> *L*2 *di*2

*C*2 *dυ*<sup>2</sup>

*L*1 *di*1

*C*1 *dυ*<sup>1</sup>

> *L*2 *di*2

*C*2 *dυ*<sup>2</sup>

switches or duty cycles [9, 29], taking values in the interval [0, 1).

dealt with since the beginning of power electronics [27].

switches positions, that is, *u*<sup>1</sup> ∈ {0, 1} and *u*<sup>2</sup> ∈ {0, 1}.

**2.2. Converter steady-state analysis**

used [11], which is determined by

$$L\_2 \frac{di\_2}{dt} = \upsilon\_1 - \upsilon\_2. \tag{6}$$

Applying KCL to nodes A and B in Figure 3(b), the dynamics associated to *υ*<sup>1</sup> and *υ*2, respectively, are obtained:

$$C\_1 \frac{dv\_1}{dt} = -\frac{v\_1}{R\_1} - i\_{2\prime} \tag{7}$$

$$C\_2 \frac{dv\_2}{dt} = i\_2 - \frac{v\_2}{R\_L}.\tag{8}$$

c) *Equivalent circuit III* is presented when *Q*<sup>1</sup> does not conduct and *Q*<sup>2</sup> conducts, that is, *u*<sup>1</sup> = 0 and *u*<sup>2</sup> = 1, *D*<sup>1</sup> is forward biased and *D*<sup>2</sup> is reverse biased. Then, the resultant circuit is as shown in Figure 3(c). Applying KVL to meshes I and II, and the KCL to nodes A and B in Figure 3(c), the equations for *i*1, *i*2, *υ*1, and *υ*2, respectively, are obtained:

$$L\_1 \frac{di\_1}{dt} = -v\_1 + E\_\prime \tag{9}$$

$$L\_2 \frac{di\_2}{dt} = v\_{1\prime} \tag{10}$$

$$\mathbf{C}\_{1}\frac{dv\_{1}}{dt} = i\_{1} - \frac{v\_{1}}{R\_{1}} - i\_{2} \tag{11}$$

$$\mathbf{C}\_{2}\frac{d\upsilon\_{2}}{dt} = -\frac{\upsilon\_{2}}{R\_{L}}.\tag{12}$$

d) *Equivalent circuit IV* occurs when transistors *Q*<sup>1</sup> and *Q*<sup>2</sup> do not conduct, that is, *u*<sup>1</sup> = 0 and *u*<sup>2</sup> = 0, *D*<sup>1</sup> and *D*<sup>2</sup> are forward biased. The equivalent circuit is shown in Figure 3(d). In order to achieve the equations that govern *i*1, *i*2, *υ*1, and *υ*2, KVL and KCL are applied, obtaining the following:

$$L\_1 \frac{di\_1}{dt} = -\upsilon\_1 + E\_\prime \tag{13}$$

$$L\_2 \frac{di\_2}{dt} = v\_1 - v\_2 \tag{14}$$

$$C\_1 \frac{dv\_1}{dt} = i\_1 - \frac{v\_1}{R\_1} - i\_{2\prime} \tag{15}$$

$$C\_2 \frac{dv\_2}{dt} = i\_2 - \frac{v\_2}{R\_L}.\tag{16}$$

Equations related to *i*1, (1), (5), (9), and (13), can be associated, using *u*1, producing (17). The dynamics associated with *υ*<sup>1</sup> is obtained from a combination of (3), (7), (11), and (15) through *u*1, generating (18). The unification of (2), (6), (10), and (14) through *u*2, produces the dynamics associated to *i*2, determined by (19). Following a similar process for *υ*2, associating (4), (8), (12), and (16), (20) is produced. Thus, the Boost-Boost converter dynamics is determined by the following nonlinear differential equations system:

$$L\_1 \frac{di\_1}{dt} = -\left(1 - \mu\_1\right)v\_1 + E\_\prime \tag{17}$$

$$\mathcal{C}\_1 \frac{d\upsilon\_1}{dt} = \left(1 - \mu\_1\right)i\_1 - \frac{\upsilon\_1}{R\_1} - i\_{2\prime} \tag{18}$$

$$L\_2 \frac{di\_2}{dt} = \upsilon\_1 - \left(1 - \mu\_2\right)\upsilon\_2. \tag{19}$$

$$C\_2 \frac{d\upsilon\_2}{dt} = \left(1 - \mu\_2\right)\dot{\iota}\_2 - \frac{\upsilon\_2}{R\_L}.\tag{20}$$

This is called the converter *switched model* referring to the binary values associated with the switches positions, that is, *u*<sup>1</sup> ∈ {0, 1} and *u*<sup>2</sup> ∈ {0, 1}.

#### **2.2. Converter steady-state analysis**

6

respectively, are obtained:

obtaining the following:

meshes I and II the equations for *i*<sup>1</sup> and *i*2, respectively, are obtained:

*L*1 *di*<sup>1</sup>

*L*2 *di*<sup>2</sup>

*C*1 *dυ*<sup>1</sup> *dt* <sup>=</sup> <sup>−</sup> *<sup>υ</sup>*<sup>1</sup>

*C*2 *dυ*<sup>2</sup>

*L*1 *di*<sup>1</sup>

*L*2 *di*<sup>2</sup>

*C*1 *dυ*<sup>1</sup>

*C*2 *dυ*<sup>2</sup>

> *L*1 *di*<sup>1</sup>

> *L*2 *di*<sup>2</sup>

*C*1 *dυ*<sup>1</sup>

*C*2 *dυ*<sup>2</sup>

Applying KCL to nodes A and B in Figure 3(b), the dynamics associated to *υ*<sup>1</sup> and *υ*2,

*dt* <sup>=</sup> *<sup>i</sup>*<sup>2</sup> <sup>−</sup> *<sup>υ</sup>*<sup>2</sup>

c) *Equivalent circuit III* is presented when *Q*<sup>1</sup> does not conduct and *Q*<sup>2</sup> conducts, that is, *u*<sup>1</sup> = 0 and *u*<sup>2</sup> = 1, *D*<sup>1</sup> is forward biased and *D*<sup>2</sup> is reverse biased. Then, the resultant circuit is as shown in Figure 3(c). Applying KVL to meshes I and II, and the KCL to nodes A and B in Figure 3(c), the equations for *i*1, *i*2, *υ*1, and *υ*2, respectively, are obtained:

*dt* <sup>=</sup> *<sup>i</sup>*<sup>1</sup> <sup>−</sup> *<sup>υ</sup>*<sup>1</sup>

*dt* <sup>=</sup> <sup>−</sup> *<sup>υ</sup>*<sup>2</sup>

d) *Equivalent circuit IV* occurs when transistors *Q*<sup>1</sup> and *Q*<sup>2</sup> do not conduct, that is, *u*<sup>1</sup> = 0 and *u*<sup>2</sup> = 0, *D*<sup>1</sup> and *D*<sup>2</sup> are forward biased. The equivalent circuit is shown in Figure 3(d). In order to achieve the equations that govern *i*1, *i*2, *υ*1, and *υ*2, KVL and KCL are applied,

*dt* <sup>=</sup> *<sup>i</sup>*<sup>1</sup> <sup>−</sup> *<sup>υ</sup>*<sup>1</sup>

*dt* <sup>=</sup> *<sup>i</sup>*<sup>2</sup> <sup>−</sup> *<sup>υ</sup>*<sup>2</sup>

*R*1

*RL*

*R*1

*RL*

*R*1

*RL*

*dt* <sup>=</sup> *<sup>E</sup>*, (5)

*dt* <sup>=</sup> *<sup>υ</sup>*<sup>1</sup> <sup>−</sup> *<sup>υ</sup>*2. (6)

*dt* <sup>=</sup> <sup>−</sup>*υ*<sup>1</sup> <sup>+</sup> *<sup>E</sup>*, (9)

*dt* <sup>=</sup> *<sup>υ</sup>*1, (10)

*dt* <sup>=</sup> <sup>−</sup>*υ*<sup>1</sup> <sup>+</sup> *<sup>E</sup>*, (13)

*dt* <sup>=</sup> *<sup>υ</sup>*<sup>1</sup> <sup>−</sup> *<sup>υ</sup>*2, (14)

− *i*2, (15)

. (16)

− *i*2, (7)

. (8)

− *i*2, (11)

. (12)

In order to know the Boost-Boost converter properties in steady-state its average model is used [11], which is determined by

$$L\_1 \frac{di\_1}{dt} = -\left(1 - u\_{1av}\right)\upsilon\_1 + E\_\prime \tag{21}$$

$$C\_1 \frac{d\upsilon\_1}{dt} = \left(1 - \mu\_{1av}\right)\dot{\iota}\_1 - \frac{\upsilon\_1}{R\_1} - \dot{\iota}\_2. \tag{22}$$

$$L\_2 \frac{di\_2}{dt} = \upsilon\_1 - \left(1 - \mu\_{2av}\right)\upsilon\_2. \tag{23}$$

$$C\_2 \frac{dv\_2}{dt} = \left(1 - u\_{2\text{av}}\right) i\_2 - \frac{v\_2}{R\_L} \,\text{}\tag{24}$$

where *i*1, *υ*1, *i*2, and *υ*<sup>2</sup> now denote average currents and voltages associated with *L*1, *C*1, *L*2, and *C*2, respectively, whereas *u*1*av* and *u*2*av* represent average position functions of the switches or duty cycles [9, 29], taking values in the interval [0, 1).

No distinction is made between the variables of the average model (21)–(24) and the switched model (17)–(20). However, in order to distinguish one model from the other, the inputs to the average model are denoted by *u*1*av* and *u*2*av*, and the inputs of the switched model are denoted by *u*<sup>1</sup> and *u*2. This difference is used in the rest of the work. Furthermore, it is important to note that theoretical justification of the average models has been extensively dealt with since the beginning of power electronics [27].

Based on the average model (21)–(24), the evaluation of the converter equilibrium point proceeded, denoted by (*i*1, *υ*1, *i*2, *υ*2), that is, the values of *i*1, *υ*1, *i*2, and *υ*<sup>2</sup> in steady-state as a response to the constant average inputs *u*1*av* and *u*2*av*. Thus, (21)–(24) in equilibrium satisfies the following algebraic equations system:

$$0 = -\left(1 - \overline{u}\_{1av}\right)\overline{v}\_1 + E\_\prime \tag{25}$$

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**Figure 4.** Diagram developed in Matlab/Simulink to perform simulations.

ciclo=uav1(1); t=uav1(2);

A=1; fp=50000;

sal=u1;

associated with this function is presented in Table 2.

block PWM2 is shown in Table 1.

**Table 1.** Code for the block PWM1 or block PWM2.

• *Inputs*. The inputs associated with this block correspond to the constant average values *u*1*av* and *u*2*av*, which represent the inputs to blocks PWM1 and PWM2. Each PWM block is constructed with a Matlab embedded function [34], the outputs of which deliver the switched signals *u*<sup>1</sup> and *u*2, respectively. The code associated with the block PWM1 or

DC/DC Boost-Boost power converter as a didactic system: Experimental results with Matlab/Simulink via current and

u1=A\*((square(2\*pi\*fp\*t,ciclo)+1)/2;

• *Boost-Boost system*. In this block the switched model (17)–(20) is programmed. For this purpose an embedded function of Matlab is used (see Figure 5), whereas, the code

• *Outputs*. This block delivers the dynamic evolution of the variables *i*1, *υ*1, *i*2, and *υ*<sup>2</sup> and the values in steady-state *i*1, *υ*1, *i*2, and *υ*2, respectively, obtained via simulation.

function sal=DUTY\_CYCLE(uav1)

$$0 = \left(1 - \overline{u}\_{1av}\right)\overline{i}\_1 - \frac{\overline{v}\_1}{R\_1} - \overline{i}\_{2\prime} \tag{26}$$

$$0 = \overline{v}\_1 - \left(1 - \overline{u}\_{2av}\right)\overline{v}\_{2\prime} \tag{27}$$

$$0 = \left(1 - \overline{u}\_{2av}\right)\overline{i}\_2 - \frac{\overline{v}\_2}{R\_L},\tag{28}$$

which is represented as a matrix equation by

$$
\begin{bmatrix}
0 & -\left(1-\overline{u}\_{1av}\right) & 0 & 0 \\
\left(1-\overline{u}\_{1av}\right) & -\frac{1}{\overline{\mathcal{R}\_1}} & -1 & 0 \\
0 & 1 & 0 & -\left(1-\overline{u}\_{2av}\right) \\
0 & 0 & \left(1-\overline{u}\_{2av}\right) & -\frac{1}{\overline{\mathcal{R}\_1}}
\end{bmatrix}
\begin{bmatrix}
\dot{\overline{t}}\_1 \\
\overline{v}\_1 \\
\overline{t}\_2 \\
\overline{v}\_2
\end{bmatrix} = \begin{bmatrix}
0 \\
0 \\
0
\end{bmatrix}.\tag{29}
$$

By solving (29) for *i*1, *υ*1, *i*2, and *υ*<sup>2</sup> the following is obtained:

$$
\begin{bmatrix}
\overline{I}\_1\\\overline{\upsilon}\_1\\\overline{I}\_2\\\overline{\upsilon}\_2
\end{bmatrix} = \begin{bmatrix}
\frac{E}{R\_1\overline{R}\_L}\frac{R\_1 + R\_L(1-\overline{\upsilon}\_{2\text{av}})^2}{(1-\overline{\upsilon}\_{1\text{av}})^2(1-\overline{\upsilon}\_{2\text{av}})^2}\\\frac{E}{R\_L}\frac{E}{(1-\overline{\upsilon}\_{1\text{av}})(1-\overline{\upsilon}\_{2\text{av}})^2}\\\frac{E}{(1-\overline{\upsilon}\_{1\text{av}})(1-\overline{\upsilon}\_{2\text{av}})}\\\frac{E}{(1-\overline{\upsilon}\_{1\text{av}})(1-\overline{\upsilon}\_{2\text{av}})}
\end{bmatrix}.
\tag{30}
$$

Therefore, (30) provides the average value of the variables *i*1, *υ*1, *i*2, and *υ*<sup>2</sup> in steady-state. Furthermore, from the relation of *υ*<sup>2</sup> with *u*1*av* and *u*2*av* it can be seen that the output of this converter satisfies the inequality *υ*<sup>2</sup> ≥ *E*, as initially stated, since *u*1*av* and *u*2*av* ∈ [0, 1).

#### **3. Converter numerical simulations with Matlab/Simulink**

In this section, numerical simulations of the Boost-Boost converter switched model (17)–(20) are performed, by using Matlab/Simulink. This will enable the dynamic evolution of the system variables *i*1, *υ*1, *i*2, and *υ*<sup>2</sup> to be known in response to different switched inputs *u*<sup>1</sup> and *u*2, generated via the constant average inputs *u*1*av* and *u*2*av* belonging to the interval [0, 1).

#### **3.1. Simulink blocks for simulations**

The developed diagram for the converter's numerical simulations consists of three blocks, namely, *inputs*, *Boost-Boost system*, and *outputs*, (see Figure 4). The description associated with the block diagram shown in the Figure 4 is as follows:

<sup>476</sup> MATLAB Applications for the Practical Engineer DC/DC Boost-Boost power converter as a didactic system: Experimental results with Matlab/Simulink via current and voltage probes 10.5772/58243 DC/DC Boost-Boost power converter as a didactic system: Experimental results with Matlab/Simulink via current and voltage probes http://dx.doi.org/10.5772/58243 477

**Figure 4.** Diagram developed in Matlab/Simulink to perform simulations.

8

Based on the average model (21)–(24), the evaluation of the converter equilibrium point proceeded, denoted by (*i*1, *υ*1, *i*2, *υ*2), that is, the values of *i*1, *υ*1, *i*2, and *υ*<sup>2</sup> in steady-state as a response to the constant average inputs *u*1*av* and *u*2*av*. Thus, (21)–(24) in equilibrium

<sup>0</sup> <sup>=</sup> (<sup>1</sup> <sup>−</sup> *<sup>u</sup>*1*av*)*i*<sup>1</sup> <sup>−</sup> *<sup>υ</sup>*<sup>1</sup>

<sup>0</sup> <sup>=</sup> (<sup>1</sup> <sup>−</sup> *<sup>u</sup>*2*av*)*i*<sup>2</sup> <sup>−</sup> *<sup>υ</sup>*<sup>2</sup>

*<sup>R</sup>*<sup>1</sup> <sup>−</sup>1 0 010 − (1 − *u*2*av*) 0 0 (1 − *u*2*av*) − <sup>1</sup>

0 − (1 − *u*1*av*) 0 0

By solving (29) for *i*1, *υ*1, *i*2, and *υ*<sup>2</sup> the following is obtained:

 

*i*1 *υ*1 *i*2 *υ*2  =

**3. Converter numerical simulations with Matlab/Simulink**

 

*E R*1*RL*

*RL*

Therefore, (30) provides the average value of the variables *i*1, *υ*1, *i*2, and *υ*<sup>2</sup> in steady-state. Furthermore, from the relation of *υ*<sup>2</sup> with *u*1*av* and *u*2*av* it can be seen that the output of this converter satisfies the inequality *υ*<sup>2</sup> ≥ *E*, as initially stated, since *u*1*av* and *u*2*av* ∈ [0, 1).

In this section, numerical simulations of the Boost-Boost converter switched model (17)–(20) are performed, by using Matlab/Simulink. This will enable the dynamic evolution of the system variables *i*1, *υ*1, *i*2, and *υ*<sup>2</sup> to be known in response to different switched inputs *u*<sup>1</sup> and *u*2, generated via the constant average inputs *u*1*av* and *u*2*av* belonging to the interval

The developed diagram for the converter's numerical simulations consists of three blocks, namely, *inputs*, *Boost-Boost system*, and *outputs*, (see Figure 4). The description associated

*R*1

*RL*

*RL*

*R*1+*RL*(1−*u*2*av* )<sup>2</sup> (1−*u*1*av* )<sup>2</sup>(1−*u*2*av* )<sup>2</sup> *E* <sup>1</sup>−*u*1*av <sup>E</sup>*

1 (1−*u*1*av* )(1−*u*2*av* )<sup>2</sup> *E* (1−*u*1*av* )(1−*u*2*av* )

0 = − (1 − *u*1*av*) *υ*<sup>1</sup> + *E*, (25)

0 = *υ*<sup>1</sup> − (1 − *u*2*av*) *υ*2, (27)

 

   

*i*1 *υ*1 *i*2 *υ*2  =

− *i*2, (26)

, (28)

 

 

. (30)

. (29)

satisfies the following algebraic equations system:

which is represented as a matrix equation by

(1 − *u*1*av*) − <sup>1</sup>

**3.1. Simulink blocks for simulations**

with the block diagram shown in the Figure 4 is as follows:

 

[0, 1).

• *Inputs*. The inputs associated with this block correspond to the constant average values *u*1*av* and *u*2*av*, which represent the inputs to blocks PWM1 and PWM2. Each PWM block is constructed with a Matlab embedded function [34], the outputs of which deliver the switched signals *u*<sup>1</sup> and *u*2, respectively. The code associated with the block PWM1 or block PWM2 is shown in Table 1.

```
function sal=DUTY_CYCLE(uav1)
ciclo=uav1(1);
t=uav1(2);
A=1;
fp=50000;
u1=A*((square(2*pi*fp*t,ciclo)+1)/2;
sal=u1;
```
**Table 1.** Code for the block PWM1 or block PWM2.


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479

for the cases in which *E* takes values of 6 V and 12 V, respectively. The justification of the parameters is shown in next section, whereas, the simulation results associated with the

DC/DC Boost-Boost power converter as a didactic system: Experimental results with Matlab/Simulink via current and

• *Simulation I* considers that *E* = 6 V and the system inputs take the average values *u*1*av* = 0.60 and *u*2*av* = 0.60. In steady-state, according to (30), (*i*1, *υ*1, *i*2, *υ*2)=(931 mA, 15 V,

• *Simulation II* considers that *E* = 12 V and the inputs are *u*1*av* = 0.55 and *u*2*av* = 0.55. According to (30) it is found that (*i*1, *υ*1, *i*2, *υ*2)=(1.19 A, 26.67 V, 480 mA, 59.26 V). The

0.5

30

capacitor *C*2.

x 10−4

x 10−4

t [s]

t [s]

[V]

0 0.2 0.4 0.6 0.8 1

u1

u2

0 0.2 0.4 0.6 0.8 1

(c) Inputs *u*<sup>1</sup> = 60% and *u*<sup>2</sup> = 60%.

It can be observed that the simulation results validate the converter mathematical model and that the steady-state values of the system variables behave according to (30). Also, it was verified that this converter operates as a voltage amplifier with respect to *E*, when

60

[A]

1

<sup>0</sup> 0.02 0.04 0.06 <sup>0</sup>

υ<sup>2</sup> υ¯<sup>2</sup>

<sup>0</sup> 0.02 0.04 0.06 <sup>0</sup>

(b) Current through the inductor *L*<sup>2</sup> and voltage at

i<sup>2</sup> ¯i<sup>2</sup>

t [s]

voltage probes

http://dx.doi.org/10.5772/58243

t [s]

340 mA, 37.5 V). For this case, the simulation results are shown in Figure 6.

corresponding simulation results can be seen in Figure 7.

t [s]

t [s]

converter under study are presented as follows:

<sup>0</sup> 0.02 0.04 0.06 <sup>0</sup>

υ<sup>1</sup> υ¯<sup>1</sup>

<sup>0</sup> 0.02 0.04 0.06 <sup>0</sup>

(a) Current through the inductor *L*<sup>1</sup> and voltage at

**Figure 6.** Dynamic response obtained from *simulation I*.

*u*1*av* ∈ (0, 1) and *u*2*av* ∈ (0, 1).

i<sup>1</sup> ¯i<sup>1</sup>

1 2

10 20

capacitor *C*1.

[V]

[A]

**Figure 5.** Block *Boost-Boost system.*

```
function y=Boost_Boost(u1,u2,i1,i2,v1,v2)
E=12;L1=4.94e-3;C1=12.2e-6;L2=3e-3;C2=12.2e-6;R1=474;
RL=275;a1=0.55;a2=0.55;
di1=(-(1-u1)*(v1/L1))+(E/L1);
dv1=((1-u1)*(i1/C1))-(v1/(R1*C1))-(i2/C1);
di2=(v1/L2)-((1-u2)*(v2/L2));
dv2=((1-u2)*(i2/C2))-(v2/(RL*C2));
v1d=(E/(1-a1));
i1d=((E/(R1*RL))*((R1+((RL)*((1-a2)^2)))/(((1-a1)^2)*((1-a2)^2))));
v2d=(E/((1-a1)*(1-a2)));
i2d=((E/RL)*(1/((1-a1)*((1-a2)^2))));
y=[di1;dv1;di2;dv2];
```
**Table 2.** *Boost-Boost system* code.

#### **3.2. Simulation results**

In the numerical simulations implementation, the following values for the parameters associated with (17)–(20) were considered:

$$L\_1 = 4.94 \text{ mH}, \ C\_1 = 12.2 \text{ } \mu\text{F}, \ L\_2 = 3 \text{ mH}, \ C\_2 = 12.2 \text{ } \mu\text{F}, \ R\_1 = 474 \text{ } \Omega, \ R\_L = 275 \text{ } \Omega\_L$$

for the cases in which *E* takes values of 6 V and 12 V, respectively. The justification of the parameters is shown in next section, whereas, the simulation results associated with the converter under study are presented as follows:


10

**Figure 5.** Block *Boost-Boost system.*

v1d=(E/(1-a1));

RL=275;a1=0.55;a2=0.55;

v2d=(E/((1-a1)\*(1-a2)));

y=[di1;dv1;di2;dv2];

**Table 2.** *Boost-Boost system* code.

**3.2. Simulation results**

di1=(-(1-u1)\*(v1/L1))+(E/L1);

di2=(v1/L2)-((1-u2)\*(v2/L2)); dv2=((1-u2)\*(i2/C2))-(v2/(RL\*C2));

associated with (17)–(20) were considered:

function y=Boost\_Boost(u1,u2,i1,i2,v1,v2)

dv1=((1-u1)\*(i1/C1))-(v1/(R1\*C1))-(i2/C1);

i2d=((E/RL)\*(1/((1-a1)\*((1-a2)^2))));

E=12;L1=4.94e-3;C1=12.2e-6;L2=3e-3;C2=12.2e-6;R1=474;

i1d=((E/(R1\*RL))\*((R1+((RL)\*((1-a2)^2)))/(((1-a1)^2)\*((1-a2)^2))));

In the numerical simulations implementation, the following values for the parameters

*L*<sup>1</sup> = 4.94 mH, *C*<sup>1</sup> = 12.2 *µ*F, *L*<sup>2</sup> = 3 mH, *C*<sup>2</sup> = 12.2 *µ*F, *R*<sup>1</sup> = 474 Ω, *RL* = 275 Ω,

(a) Current through the inductor *L*<sup>1</sup> and voltage at capacitor *C*1.

(b) Current through the inductor *L*<sup>2</sup> and voltage at capacitor *C*2.

(c) Inputs *u*<sup>1</sup> = 60% and *u*<sup>2</sup> = 60%.

**Figure 6.** Dynamic response obtained from *simulation I*.

It can be observed that the simulation results validate the converter mathematical model and that the steady-state values of the system variables behave according to (30). Also, it was verified that this converter operates as a voltage amplifier with respect to *E*, when *u*1*av* ∈ (0, 1) and *u*2*av* ∈ (0, 1).

(a) Current through the inductor *L*<sup>1</sup> and voltage at capacitor *C*1.

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481

*Case 1 Case 2*

*υ*<sup>2</sup> = 66.67 V *υ*<sup>2</sup> = 59.26 V

and 12% of nominal value for *i*<sup>2</sup>

(50 kHz) (0.05) (2.81 A) <sup>≈</sup> 0.60 mH, (31)

(470.59 <sup>Ω</sup>) (50 kHz) (0.05) (20 V) (20 V) <sup>≈</sup> 0.59 *<sup>µ</sup>*F. (32)

(50 kHz) (0.12) (0.80 A) <sup>≈</sup> 2.92 mH, (33)

, which produces *R*<sup>1</sup> ≈ 470.59 Ω. Similarly, if

*<sup>υ</sup>*<sup>2</sup> <sup>≈</sup> 240 mA. Moreover, according

*<sup>υ</sup>*<sup>1</sup> = 42.5 mA,

voltage probes

http://dx.doi.org/10.5772/58243

Input voltage (*E*) 6 V 12 V

Output voltages (*υ*<sup>1</sup> and *υ*2) *υ*<sup>1</sup> = 20 V *υ*<sup>1</sup> = 26.67 V

DC/DC Boost-Boost power converter as a didactic system: Experimental results with Matlab/Simulink via current and

Output power associated to *PR*<sup>1</sup> = 0.85 W *PR*<sup>1</sup> = 1.48 W *<sup>R</sup>*<sup>1</sup> (*PR*<sup>1</sup> ) and *RL* (*PRL* ) *PRL* = 16 W *PRL* = 12.19 W

Current ripple (∆*i*<sup>1</sup> and ∆*i*2) 5% of nominal value for *i*1,

Voltage ripple (∆*υ*<sup>1</sup> and ∆*υ*2) 5% of nominal value for *υ*<sup>1</sup> and *υ*<sup>1</sup>

Since the desired power in load resistance *R*<sup>1</sup> is 0.85 W, with a voltage of 20 V, then *R*<sup>1</sup>

*PRL* = 16 W and *υ*<sup>2</sup> = 66.67 V, then the load resistance *RL* ≈ 277.81 Ω. On the other hand,

to (30) the currents through the inductors, *L*<sup>1</sup> and *L*2, are *i*<sup>1</sup> ≈ 2.81 A and *i*<sup>2</sup> ≈ 800 mA,

In the calculations of the inductance and capacitance minimum values associated with the first stage, in order to satisfy the converter design specifications, the following relations are

Furthermore, according to [35] the condition *T* << 2*R*1*C*<sup>1</sup> must be satisfied, where *T* = 1/ *f* , which is achieved when *C*1 min is multiplied by 20, generating that *C*<sup>1</sup> is determined by

*C*<sup>1</sup> = 11.8 *µF*.

Now, the minimum values for inductance and capacitance of the second stage can be

<sup>=</sup> (20 V) (0.70)

1 *PR*1

the current *iR*<sup>1</sup> flowing through *<sup>R</sup>*<sup>1</sup> is calculated from the expression *iR*<sup>1</sup> <sup>=</sup> *PR*<sup>1</sup>

<sup>=</sup> (6 V) (0.70)

*<sup>υ</sup>*<sup>1</sup> <sup>=</sup> (0.70)

Switching frequency (*f*) 50 kHz 50 kHz

**Table 3.** Design specifications for the Boost-Boost converter.

is calculated using the expression *<sup>R</sup>*<sup>1</sup> <sup>=</sup> *<sup>υ</sup>*<sup>2</sup>

respectively.

employed [35]:

calculated as follows:

*<sup>L</sup>*1 min <sup>=</sup> *Eu*1*av*

*<sup>C</sup>*1 min <sup>=</sup> *<sup>u</sup>*1*av*

*f*∆*i*<sup>1</sup>

*R*<sup>1</sup> *f*∆*υ*<sup>1</sup>

*<sup>L</sup>*2 min <sup>=</sup> *<sup>υ</sup>*1*u*2*av*

*f*∆*i*<sup>2</sup>

whereas the current through *RL* is defined by *iRL* <sup>=</sup> *PRL*

(b) Current through the inductor *L*<sup>2</sup> and voltage at capacitor *C*2.

(c) Inputs *u*<sup>1</sup> = 55% and *u*<sup>2</sup> = 55%.

**Figure 7.** Dynamic response obtained from *simulation II*.

#### **4. Boost-Boost power converter construction**

In this section, first the process followed to obtain the design parameters of the DC/DC Boost-Boost power converter is described. Subsequently, the construction of such a converter is presented.

#### **4.1. Boost-Boost power converter design**

Table 3 shows the design specifications for the converter construction. Two cases are considered: the first refers to *E* = 6 V and the second to *E* = 12 V.

Here, calculations corresponding to the first case are presented. According to (30) and the converter design specification, the average inputs *u*1*av* and *u*2*av* are defined by

$$\begin{aligned} \overline{u}\_{1av} &= 1 - \frac{E}{\overline{v}\_1} = 1 - \frac{6\,\mathrm{V}}{20\,\mathrm{V}} = 0.70, \\\overline{u}\_{2av} &= 1 - \frac{E}{(1 - \overline{u}\_{1av})\overline{v}\_2} = 1 - \frac{6\,\mathrm{V}}{(1 - 0.70)(66.67)\,\mathrm{V}} \approx 0.70. \end{aligned}$$

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**Table 3.** Design specifications for the Boost-Boost converter.

12

1.5 3

> 20 40

capacitor *C*1.

is presented.

[V]

[A]

<sup>0</sup> 0.02 0.04 0.06 <sup>0</sup>

υ<sup>1</sup> υ¯<sup>1</sup>

<sup>0</sup> 0.02 0.04 0.06 <sup>0</sup>

**4. Boost-Boost power converter construction**

considered: the first refers to *E* = 6 V and the second to *E* = 12 V.

converter design specification, the average inputs *u*1*av* and *u*2*av* are defined by

<sup>=</sup> <sup>1</sup> <sup>−</sup> 6 V

(1 − *u*1*av*)*υ*<sup>2</sup>

(a) Current through the inductor *L*<sup>1</sup> and voltage at

**Figure 7.** Dynamic response obtained from *simulation II*.

**4.1. Boost-Boost power converter design**

*<sup>u</sup>*1*av* <sup>=</sup> <sup>1</sup> <sup>−</sup> *<sup>E</sup>*

*<sup>u</sup>*2*av* <sup>=</sup> <sup>1</sup> <sup>−</sup> *<sup>E</sup>*

*υ*1

i<sup>1</sup> ¯i<sup>1</sup>

t [s]

0.5 1

> 30 60 90

capacitor *C*2.

x 10−4

x 10−4

t [s]

t [s]

[V]

0 0.2 0.4 0.6 0.8 1

0 0.5 1

(c) Inputs *u*<sup>1</sup> = 55% and *u*<sup>2</sup> = 55%.

In this section, first the process followed to obtain the design parameters of the DC/DC Boost-Boost power converter is described. Subsequently, the construction of such a converter

Table 3 shows the design specifications for the converter construction. Two cases are

Here, calculations corresponding to the first case are presented. According to (30) and the

20 V <sup>=</sup> 0.70,

<sup>=</sup> <sup>1</sup> <sup>−</sup> 6 V

(<sup>1</sup> <sup>−</sup> 0.70)(66.67) <sup>V</sup> <sup>≈</sup> 0.70.

u1

u2

[A]

<sup>0</sup> 0.02 0.04 0.06 <sup>0</sup>

υ<sup>2</sup> υ¯<sup>2</sup>

<sup>0</sup> 0.02 0.04 0.06 <sup>0</sup>

(b) Current through the inductor *L*<sup>2</sup> and voltage at

i<sup>2</sup> ¯i<sup>2</sup>

t [s]

t [s]

t [s]

Since the desired power in load resistance *R*<sup>1</sup> is 0.85 W, with a voltage of 20 V, then *R*<sup>1</sup> is calculated using the expression *<sup>R</sup>*<sup>1</sup> <sup>=</sup> *<sup>υ</sup>*<sup>2</sup> 1 *PR*1 , which produces *R*<sup>1</sup> ≈ 470.59 Ω. Similarly, if *PRL* = 16 W and *υ*<sup>2</sup> = 66.67 V, then the load resistance *RL* ≈ 277.81 Ω. On the other hand, the current *iR*<sup>1</sup> flowing through *<sup>R</sup>*<sup>1</sup> is calculated from the expression *iR*<sup>1</sup> <sup>=</sup> *PR*<sup>1</sup> *<sup>υ</sup>*<sup>1</sup> = 42.5 mA, whereas the current through *RL* is defined by *iRL* <sup>=</sup> *PRL <sup>υ</sup>*<sup>2</sup> <sup>≈</sup> 240 mA. Moreover, according to (30) the currents through the inductors, *L*<sup>1</sup> and *L*2, are *i*<sup>1</sup> ≈ 2.81 A and *i*<sup>2</sup> ≈ 800 mA, respectively.

In the calculations of the inductance and capacitance minimum values associated with the first stage, in order to satisfy the converter design specifications, the following relations are employed [35]:

$$L\_{1\,\mathrm{min}} = \frac{E\overline{u}\_{1av}}{f\Delta\overline{i}\_1} = \frac{(6\ \mathrm{V})\,(0.70)}{(50\ \mathrm{kHz})\,(0.05)\,(2.81\ \mathrm{A})} \approx 0.60\ \mathrm{mH},\tag{31}$$

$$\mathcal{C}\_{1\text{ min}} = \frac{\overline{u}\_{1av}}{R\_1 f \Delta \overline{v}\_1} \overline{v}\_1 = \frac{(0.70)}{(470.59\ \Omega)(50\ \text{kHz})\,(0.05)\,(20\ \text{V})}\,(20\ \text{V}) \approx 0.59\ \mu\text{F}.\tag{32}$$

Furthermore, according to [35] the condition *T* << 2*R*1*C*<sup>1</sup> must be satisfied, where *T* = 1/ *f* , which is achieved when *C*1 min is multiplied by 20, generating that *C*<sup>1</sup> is determined by

$$\mathcal{C}\_1 = 11.8 \,\mu F\_\ast$$

Now, the minimum values for inductance and capacitance of the second stage can be calculated as follows:

$$L\_{2\,\mathrm{min}} = \frac{\overline{v}\_1 \overline{u}\_{2w}}{f \Delta \overline{i}\_2} = \frac{(20 \text{ V})\,(0.70)}{(50 \text{ kHz})\,(0.12)\,(0.80 \text{ A})} \approx 2.92 \text{ mH},\tag{33}$$

$$\mathcal{C}\_{2\text{ min}} = \frac{\overline{u}\_{2\text{av}}}{R\_L f \Delta \overline{v}\_2} \overline{v}\_2 = \frac{(0.70)}{(277.81 \,\Omega)(50 \,\text{kHz}) \,(0.05) \,(66.67 \,\text{V})} \,(66.67 \,\text{V}) \approx 1.01 \,\mu\text{F}. \tag{34}$$

Condition *T* << 2*R*2*C*2, can be satisfied multiplying *C*2 min by 12 generating the following:

$$\mathsf{C}\_{2} = 12.12 \,\mu F\_{\ast}$$

Finally, the commercial values employed for the converter components were the following:

$$\begin{aligned} L\_1 &= 4.94 \text{ mH}, \ C\_1 = 12.2 \text{ } \mu\text{F}, \ L\_2 = 3 \text{ mH}, \\ \ C\_2 &= 12.2 \text{ } \mu\text{F}, \ R\_1 = 474 \text{ } \Omega/50 \text{ W}, \ R\_L = 275 \text{ } \Omega/50 \text{ W}. \end{aligned} \tag{35}$$

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*Boost-Boost converter*

i<sup>1</sup> i<sup>2</sup>

u<sup>1</sup> u<sup>2</sup>

*Function generator*

**VOLTAGE PROBE**

DC/DC Boost-Boost power converter as a didactic system: Experimental results with Matlab/Simulink via current and

D<sup>1</sup> D<sup>2</sup>

**P6139A**

**MUR840**

**P6139A**

voltage probes

http://dx.doi.org/10.5772/58243

**VOLTAGE PROBE**

**NTE2984**

**GENERATOR FUNCTION**

Since the Boost-Boost converter is integrated by two Boost converters connected in cascade, they were developed two identical printed circuit boards (PCBs) of a Boost converter that later were interconnected. The PCBs were designed by using a specialized software. In the PCBs design the inductors, transistors, and resistors were replaced by terminal blocks, this with the intent of replacing easily the components associated with the converter whenever

In this section the experimental results related to the dynamic responses of the converter are provided, in order to compare them with the simulation results presented in Section 3. All experiments were performed using the Boost-Boost converter described in Section 4. In order to visualize the system dynamic response Matlab/Simulink and a DS1104 electronic board

The converter dynamic response was tested experimentally for the cases indicated in

from dSPACE, along with commercial current and voltage probes are employed.

**HP 8111A**

v<sup>1</sup> C<sup>1</sup> R<sup>1</sup> v<sup>2</sup> C<sup>2</sup> RL

**CURRENT PROBE A622**

**MUR840**

**NTE2984**

L<sup>1</sup> L<sup>2</sup>

**A622 CURRENT PROBE**

**Figure 8.** Electronic diagram of the Boost-Boost converter.

necessary. The prototype built is shown in Figure 9.

**GENERATOR FUNCTION**

**Figure 9.** Boost-Boost power converter built.

**5.1. Dynamic response of the converter**

**5. Experimental results**

Subsection 3.2.

**HP 8111A**

E

The inductors were built on a ETD49/25/16 core with 3C85 material from Ferroxcube. They were used 110 and 69 turns of 18.5 AWG Litz wire for *L*<sup>1</sup> and *L*2, respectively, with 175 strands. The *L*<sup>1</sup> internal series resistance, *Rs*1, has associated 10.5 Ω, while the *L*<sup>2</sup> internal series resistance, *Rs*2, 6.6 Ω. Furthermore, the *C*<sup>1</sup> and *C*<sup>2</sup> values were obtained by connecting two MKP capacitors from Kemet in parallel: one of 10 *µF* and another one of 2 *µF*, both rated at 275 V.

Following a similar procedure as the one aforementioned, we have found that approach values for *L*1, *C*1, *L*2, *C*2, *R*1, and *RL*, as they are shown in (35), are required for *Case 2* presented in Table 3.

#### **4.2. Experimental prototype**

Figure 8 shows the electronic diagram proposed for the Boost-Boost converter, which is composed of two blocks, namely, *Boost-Boost converter* and *function generator*. The description associated with these blocks is presented as follows:


<sup>482</sup> MATLAB Applications for the Practical Engineer DC/DC Boost-Boost power converter as a didactic system: Experimental results with Matlab/Simulink via current and voltage probes 10.5772/58243 DC/DC Boost-Boost power converter as a didactic system: Experimental results with Matlab/Simulink via current and voltage probes http://dx.doi.org/10.5772/58243 483

**Figure 8.** Electronic diagram of the Boost-Boost converter.

14

*<sup>C</sup>*2 min <sup>=</sup> *<sup>u</sup>*2*av*

rated at 275 V.

presented in Table 3.

**4.2. Experimental prototype**

associated with these blocks is presented as follows:

*RL f*∆*υ*<sup>2</sup>

*<sup>υ</sup>*<sup>2</sup> <sup>=</sup> (0.70)

Condition *T* << 2*R*2*C*2, can be satisfied multiplying *C*2 min by 12 generating the following:

*C*<sup>2</sup> = 12.12 *µF*.

Finally, the commercial values employed for the converter components were the following:

The inductors were built on a ETD49/25/16 core with 3C85 material from Ferroxcube. They were used 110 and 69 turns of 18.5 AWG Litz wire for *L*<sup>1</sup> and *L*2, respectively, with 175 strands. The *L*<sup>1</sup> internal series resistance, *Rs*1, has associated 10.5 Ω, while the *L*<sup>2</sup> internal series resistance, *Rs*2, 6.6 Ω. Furthermore, the *C*<sup>1</sup> and *C*<sup>2</sup> values were obtained by connecting two MKP capacitors from Kemet in parallel: one of 10 *µF* and another one of 2 *µF*, both

Following a similar procedure as the one aforementioned, we have found that approach values for *L*1, *C*1, *L*2, *C*2, *R*1, and *RL*, as they are shown in (35), are required for *Case 2*

Figure 8 shows the electronic diagram proposed for the Boost-Boost converter, which is composed of two blocks, namely, *Boost-Boost converter* and *function generator*. The description

• *Boost-Boost converter*. Figure 8 shows how the variables *i*1, *υ*1, *i*2, and *υ*2, are measured. In order to visualize the converter dynamic response Matlab/Simulink and a DS1104 electronic board from dSPACE are employed, along with two Tektronix A622 AC/DC current probes (for *i*<sup>1</sup> and *i*2), and two Tektronix P6139A voltage probes (for *υ*<sup>1</sup> and *υ*2),

• *Function generator*. This block is implemented using an HP 8111A function generator, which possesses an option to set the pulse width, to produce the input signals *u*<sup>1</sup> and *u*<sup>2</sup> with a 5 V amplitude, which is an appropriate voltage level to trigger the NTE2984 transistors. These transistors have a logic level gate and operate at high speed. Some important parameters of this device are the following: drain–source breakdown voltage BVDSS = 60 V, absolute maximum drain current *I*<sup>D</sup> = 17 A with continuous *V*GS = 5 V to 25 ◦C, rise time *<sup>t</sup>*<sup>r</sup> <sup>=</sup> 110 ns, fall time *<sup>t</sup>*<sup>f</sup> <sup>=</sup> 41 ns, turn-on delay time *td*(on) <sup>=</sup> 11 ns, turn-off delay time *td*(off) = 23 ns, static drain–source on resistance *<sup>R</sup>*DS(on) = 0.14 <sup>Ω</sup> and the maximum operating temperature is 175 ◦C. The visualizing of *<sup>u</sup>*<sup>1</sup> and *<sup>u</sup>*<sup>2</sup> are

whereas, a BK Precision 1795 DC power supply is used to provide *E*.

accomplished with a Tektronic TDS 3034B oscilloscope.

*L*<sup>1</sup> = 4.94 mH, *C*<sup>1</sup> = 12.2 *µF*, *L*<sup>2</sup> = 3 mH,

*<sup>C</sup>*<sup>2</sup> <sup>=</sup> 12.2 *<sup>µ</sup>F*, *<sup>R</sup>*<sup>1</sup> <sup>=</sup> <sup>474</sup> <sup>Ω</sup>/50 W, *RL* <sup>=</sup> <sup>275</sup> <sup>Ω</sup>/50 W. (35)

(277.81 <sup>Ω</sup>) (50 kHz) (0.05) (66.67 V) (66.67 V) <sup>≈</sup> 1.01 *<sup>µ</sup>*F. (34)

Since the Boost-Boost converter is integrated by two Boost converters connected in cascade, they were developed two identical printed circuit boards (PCBs) of a Boost converter that later were interconnected. The PCBs were designed by using a specialized software. In the PCBs design the inductors, transistors, and resistors were replaced by terminal blocks, this with the intent of replacing easily the components associated with the converter whenever necessary. The prototype built is shown in Figure 9.

**Figure 9.** Boost-Boost power converter built.

#### **5. Experimental results**

In this section the experimental results related to the dynamic responses of the converter are provided, in order to compare them with the simulation results presented in Section 3. All experiments were performed using the Boost-Boost converter described in Section 4. In order to visualize the system dynamic response Matlab/Simulink and a DS1104 electronic board from dSPACE, along with commercial current and voltage probes are employed.

#### **5.1. Dynamic response of the converter**

The converter dynamic response was tested experimentally for the cases indicated in Subsection 3.2.

• *Experiment I*. The experimental results associated with the *simulation I* are presented in Figure 10. These results show the dynamic response of *i*1, *υ*1, *i*2, and *υ*<sup>2</sup> as well as the steady-state values *i*1, *υ*1, *i*2, and *υ*2, respectively. Also, Figure 10 presents the input signals *u*<sup>1</sup> = 60% and *u*<sup>2</sup> = 60%. The corresponding experimental numerical values measured in steady-state are (*i*1*m*, *υ*1*m*, *i*2*m*, *υ*2*m*)=(930 mA, 13.96 V, 330 mA, 36.95 V).

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<sup>0</sup> 0.02 0.04 0.06 <sup>0</sup>

υ<sup>1</sup> υ<sup>1</sup>

<sup>0</sup> 0.02 0.04 0.06 <sup>0</sup>

(a) Current through the inductor *L*<sup>1</sup> and voltage at

i<sup>1</sup> i<sup>1</sup>

t [s]

0.5 1

> 30 60 90

at capacitor *C*2.

[V]

(c) Inputs *u*<sup>1</sup> = 55% (upper line) and *u*<sup>2</sup> = 55%

complex, the tools herein used could help in the speedy implementation of controllers in real time, in future research works, as Matlab/Simulink provides a GUI for their fast building. Differences between simulations and experiments in the dynamic responses presented in Figures 6 and 10, on the one hand, and Figures 7 and 11, on the other, are due to the fact that the energy losses are not considered in simulations. This means that the inductors internal resistance is considered to be zero, and the semiconductor devices are assumed to be infinitely fast. Moreover, it has been shown [36] for the DC/DC Boost converter, that oscillations decrease considerably when the simulation model takes into account that the converter components are non-ideal, that is, using the Shockley diode model [37] and the Ebers-Moll transistor model [38], and taking into account the inductors internal resistance. However, it is a challenge to find a fair trade-off between complexity and accuracy; this is because to obtain better accuracy it is necessary to develop a more complex converter model. The advantage of the model used in the simulations presented in this work is simplicity and, at the same time, relatively good accuracy, which is enough for educational proposes.

(bottom line).

**Figure 11.** Dynamic response obtained from *experiment II*.

[A]

DC/DC Boost-Boost power converter as a didactic system: Experimental results with Matlab/Simulink via current and

<sup>0</sup> 0.02 0.04 0.06 <sup>0</sup>

υ<sup>2</sup> υ<sup>2</sup>

<sup>0</sup> 0.02 0.04 0.06 <sup>0</sup>

(b) Current through the inductor *L*<sup>2</sup> and voltage

i<sup>2</sup> i<sup>2</sup>

t [s]

http://dx.doi.org/10.5772/58243

voltage probes

t [s]

t [s]

1.5 3

> 20 40

capacitor *C*1.

[V]

[A]

(a) Current through the inductor *L*<sup>1</sup> and voltage at capacitor *C*1.

(b) Current through the inductor *L*<sup>2</sup> and voltage at capacitor *C*2.

**Figure 10.** Dynamic response obtained from *experiment I*.

(bottom line).

• *Experiment II*. Experimental results corresponding to *simulation II* are presented in Figure 11. Here, the experimental numerical values measured in steady-state are (*i*1*m*, *υ*1*m*, *i*2*m*, *υ*2*m*)=(1.35 A, 25.63 V, 500 mA, 58.5 V).

#### **5.2. Discussion**

The visualization of the converter dynamic response was accomplished via Matlab/Simulink and a DS1104 electronic board, along with current and voltage probes. The experimental results herein obtained are similar to the ones that can be obtained through the use of an oscilloscope. Although the process employed for the acquisition of the signals seems more <sup>484</sup> MATLAB Applications for the Practical Engineer DC/DC Boost-Boost power converter as a didactic system: Experimental results with Matlab/Simulink via current and voltage probes 17 10.5772/58243 DC/DC Boost-Boost power converter as a didactic system: Experimental results with Matlab/Simulink via current and voltage probes http://dx.doi.org/10.5772/58243 485

16

• *Experiment I*. The experimental results associated with the *simulation I* are presented in Figure 10. These results show the dynamic response of *i*1, *υ*1, *i*2, and *υ*<sup>2</sup> as well as the steady-state values *i*1, *υ*1, *i*2, and *υ*2, respectively. Also, Figure 10 presents the input signals *u*<sup>1</sup> = 60% and *u*<sup>2</sup> = 60%. The corresponding experimental numerical values measured in steady-state are (*i*1*m*, *υ*1*m*, *i*2*m*, *υ*2*m*)=(930 mA, 13.96 V, 330 mA, 36.95 V).

0.5

30 60

capacitor *C*2.

[V]

(c) Inputs *u*<sup>1</sup> = 60% (upper line) and *u*<sup>2</sup> = 60%

• *Experiment II*. Experimental results corresponding to *simulation II* are presented in Figure 11. Here, the experimental numerical values measured in steady-state are (*i*1*m*, *υ*1*m*, *i*2*m*,

The visualization of the converter dynamic response was accomplished via Matlab/Simulink and a DS1104 electronic board, along with current and voltage probes. The experimental results herein obtained are similar to the ones that can be obtained through the use of an oscilloscope. Although the process employed for the acquisition of the signals seems more

(bottom line).

[A]

1

<sup>0</sup> 0.02 0.04 0.06 <sup>0</sup>

υ<sup>2</sup> υ<sup>2</sup>

<sup>0</sup> 0.02 0.04 0.06 <sup>0</sup>

(b) Current through the inductor *L*<sup>2</sup> and voltage at

i<sup>2</sup> i<sup>2</sup>

t [s]

t [s]

<sup>0</sup> 0.02 0.04 0.06 <sup>0</sup>

υ<sup>1</sup> υ<sup>1</sup>

<sup>0</sup> 0.02 0.04 0.06 <sup>0</sup>

(a) Current through the inductor *L*<sup>1</sup> and voltage

**Figure 10.** Dynamic response obtained from *experiment I*.

*υ*2*m*)=(1.35 A, 25.63 V, 500 mA, 58.5 V).

i<sup>1</sup> i<sup>1</sup>

t [s]

t [s]

1 2

10 20

at capacitor *C*1.

**5.2. Discussion**

[V]

[A]

(a) Current through the inductor *L*<sup>1</sup> and voltage at capacitor *C*1.

(b) Current through the inductor *L*<sup>2</sup> and voltage at capacitor *C*2.

(c) Inputs *u*<sup>1</sup> = 55% (upper line) and *u*<sup>2</sup> = 55% (bottom line).

**Figure 11.** Dynamic response obtained from *experiment II*.

complex, the tools herein used could help in the speedy implementation of controllers in real time, in future research works, as Matlab/Simulink provides a GUI for their fast building.

Differences between simulations and experiments in the dynamic responses presented in Figures 6 and 10, on the one hand, and Figures 7 and 11, on the other, are due to the fact that the energy losses are not considered in simulations. This means that the inductors internal resistance is considered to be zero, and the semiconductor devices are assumed to be infinitely fast. Moreover, it has been shown [36] for the DC/DC Boost converter, that oscillations decrease considerably when the simulation model takes into account that the converter components are non-ideal, that is, using the Shockley diode model [37] and the Ebers-Moll transistor model [38], and taking into account the inductors internal resistance. However, it is a challenge to find a fair trade-off between complexity and accuracy; this is because to obtain better accuracy it is necessary to develop a more complex converter model. The advantage of the model used in the simulations presented in this work is simplicity and, at the same time, relatively good accuracy, which is enough for educational proposes.

### **6. Conclusions**

In this work, a DC/DC Boost-Boost power converter was presented as a didactic material, which can be used to verify, experimentally, some theoretical concepts about electric circuit analysis studied in undergraduate courses. This work is intended to teach students how to model a practical circuit, how to design and construct, step-by-step, an experimental setup, and how use it in order to verify, experimentally, some features predicted by the model. Also, we have performed some experimental tests whose results are in accordance with predictions of the converter dynamic model. Furthermore, an additional advantage of the experimental setup is that only low-cost electronic components are employed.

**References**

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487

voltage probes

http://dx.doi.org/10.5772/58243

Regarding the measurement and visualization of the variables involved in the converter, Matlab/Simulink, a DS1104 board, and current and voltage probes were used. These tools were employed as together they allow the system variables to be obtained easily and quickly. Moreover, Matlab/Simulink provides a graphical environment that facilitated the analysis, design and construction of the converter under study.

In future works, the Boost-Boost converter model representation based on state-space, as the one herein presented, and the acquired data in real time can be used to develop, step-by-step, different control laws. Such a procedure will be presented from design to experimental implementation, in order to accomplish the tasks of regulation and trajectory tracking associated with the converter output voltage. These tasks will be intended to teach different modern control techniques, which are generally taught at theoretical level, in the areas of electronics, electrical, automatic control, bionics, robotics, mechatronics, and so on.

#### **Acknowledgments**

R. Silva-Ortigoza and M. Marcelino-Aranda acknowledge the financial support from Secretaría de Investigación y Posgrado del Instituto Politécnico Nacional (SIP–IPN), SNI–Mexico, and the programs EDI and COFAA of IPN. The work of M. Antonio-Cruz and C. A. Merlo-Zapata was supported by CONACYT and BEIFI scholarships. Finally, G. Saldaña-González acknowledges to the Fondo Mixto CONACYT, since the publication of this work was partially supported with resources from the Fondo Mixto de Fomento a la Investigación Científica y Tecnológica CONACYT-Gobierno del Estado de Puebla.

#### **Author details**

R. Silva-Ortigoza1, M. Antonio-Cruz1, M. Marcelino-Aranda2, G. Saldaña-González3, C. A. Merlo-Zapata1 and P. Pérez-Romero1

1 Instituto Politécnico Nacional. CIDETEC, Área de Mecatrónica. Unidad Profesional Adolfo López Mateos, 07700 México, DF, Mexico

2 Instituto Politécnico Nacional. UPIICSA, Sección de Estudios de Posgrado e Investigación. México, DF, Mexico

3 Universidad Tecnológica de Puebla, División de Mecatrónica, Puebla, PUE, Mexico

#### **References**

18

**6. Conclusions**

**Acknowledgments**

**Author details**

México, DF, Mexico

Merlo-Zapata1 and P. Pérez-Romero1

López Mateos, 07700 México, DF, Mexico

In this work, a DC/DC Boost-Boost power converter was presented as a didactic material, which can be used to verify, experimentally, some theoretical concepts about electric circuit analysis studied in undergraduate courses. This work is intended to teach students how to model a practical circuit, how to design and construct, step-by-step, an experimental setup, and how use it in order to verify, experimentally, some features predicted by the model. Also, we have performed some experimental tests whose results are in accordance with predictions of the converter dynamic model. Furthermore, an additional advantage of the experimental

Regarding the measurement and visualization of the variables involved in the converter, Matlab/Simulink, a DS1104 board, and current and voltage probes were used. These tools were employed as together they allow the system variables to be obtained easily and quickly. Moreover, Matlab/Simulink provides a graphical environment that facilitated the analysis,

In future works, the Boost-Boost converter model representation based on state-space, as the one herein presented, and the acquired data in real time can be used to develop, step-by-step, different control laws. Such a procedure will be presented from design to experimental implementation, in order to accomplish the tasks of regulation and trajectory tracking associated with the converter output voltage. These tasks will be intended to teach different modern control techniques, which are generally taught at theoretical level, in the areas of electronics, electrical, automatic control, bionics, robotics, mechatronics, and so on.

R. Silva-Ortigoza and M. Marcelino-Aranda acknowledge the financial support from Secretaría de Investigación y Posgrado del Instituto Politécnico Nacional (SIP–IPN), SNI–Mexico, and the programs EDI and COFAA of IPN. The work of M. Antonio-Cruz and C. A. Merlo-Zapata was supported by CONACYT and BEIFI scholarships. Finally, G. Saldaña-González acknowledges to the Fondo Mixto CONACYT, since the publication of this work was partially supported with resources from the Fondo Mixto de Fomento a la

R. Silva-Ortigoza1, M. Antonio-Cruz1, M. Marcelino-Aranda2, G. Saldaña-González3, C. A.

1 Instituto Politécnico Nacional. CIDETEC, Área de Mecatrónica. Unidad Profesional Adolfo

2 Instituto Politécnico Nacional. UPIICSA, Sección de Estudios de Posgrado e Investigación.

3 Universidad Tecnológica de Puebla, División de Mecatrónica, Puebla, PUE, Mexico

Investigación Científica y Tecnológica CONACYT-Gobierno del Estado de Puebla.

setup is that only low-cost electronic components are employed.

design and construction of the converter under study.


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**Chapter 17**

**Using Matlab and Simulink for High – Level Modeling in**

The advances in biology, bioinformatics, programming technologies and computer systems made possible to store and analyze large amount of biological data with the possibility of global exploration and visualization of this data with sequence browsers (the possibility to select features for genomic and proteomic data, the possibility to identifying the transcription factors; to analyze RNA-Sequences data in order to identify specific expressed genes and common bioinformatics workflows, identify copy number variants and SNPs in microarray data). All these advances in bioinformatics are opening the possibility to elaborate different categories of models, with applicability both in deeper understanding of biological phenomena (analyz‐ ing, interpreting, and even predicting the genotype–phenotype relationship), and in the

Beyond the storage and retrieval of biological data, it is important to study and understand the biochemical processes underlying the existence of living organisms, studies that are extremely difficult to achieve due to the high cost of experiments and uniqueness of the

Living systems are characterized through thousands of simultaneous crossover high integrat‐ ed threads of information computation, biochemical reactions and mass transfer processes

High-Level modeling of biological systems allows a better understanding of informational workflows, a deeper understanding of control and regulatory mechanisms generated by the biochemical processes involved in the metabolic and signaling pathways of living systems. MATLAB® and SIMULINK® are perfect tools for describing and modeling existing control processes within biosystems. Therefore, unlike software systems made using programming

> © 2014 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

(metabolic networks, gene regulatory networks, signaling pathways).

**Biosystems**

**1. Introduction**

Cristina-Maria Dabu

http://dx.doi.org/10.5772/58369

practical application of research results.

phenomena that characterize living organisms.

Additional information is available at the end of the chapter
