**3. Static operation**

the ion in the device. The deposited charge is then obtained in each case taking into account the Gaussian distribution of the ion track, the 3-D geometry of the silicon film and the exact location of the ion strike. The deposited carriers are rapidly transported (mainly by drift and diffusion mechanisms [37]) and collected by the drain contact. A part of these carriers can be recombined by carrier recombination mechanisms; the deposited charge can also be amplified by bipolar amplification mechanism. This phenomenon is specific to partially-depleted SOI (PDSOI) devices, but also exists in FDSOI [45]-[46] and double-gate transistors [37]. The charge collected at the drain contact, following the ion strike, results in a drain current transient, which is further used to accurately calculate the collected charge (by integrating the drain current on the duration of the transient). The bipolar amplification of the charge deposited by the ion is

**Figure 1.** Schematic description of the simulated JL-DGFET (a), IM-DGFET (b), and FDSOI (c) structures considered in this work. The doping level distribution in each device is shown and the main geometrical parameters are defined. For a better view, the spacers and isolation oxide are not shown. The position of the ion strike is indicated by the arrow;

<sup>x</sup> <sup>y</sup>

LG

W

**JL-DGFET** Junctionless Double-GateMOSFET

**IM-DGFET** Inversion-Mode Double-GateMOSFET

232 Computational and Numerical Simulations

**FDSOI** Inversion-Mode Single-GateMOSFET

> Silicon Substrate

the ion strikes vertically in the middle of the channel and in a direction parallel to the z axis.

Buried oxide

Siliconfilm

Siliconfilm

VG

VG

Siliconfilm

tSi

(a)

(b)

(c)

VG

z

tBOX

The simulated steady-state drain current characteristics of JL-DGFET, IM-DGFET and FDSOI are plotted in Fig. 2. The three devices have the same off-state current, but different subthres‐ hold swings and on-state currents. While Double-Gate devices (both JL-DGFET and IM-DGFET) have near ideal subthreshold swings (65 mV/dec), FDSOI has a much higher subthreshold swing (90 mV/dec) because the single-gate configuration reduces the control by the gate of the channel potential and increases the parasitic short-channel effects compared to a double-gate configuration. The highest on-state current is obtained in IM-DGFET, due to the combination of a double-gate structure and an intrinsic channel; this structure has the advantage to maximize the carrier mobility. In JL-DGFET the highly-doped silicon film degrades the mobility and then, the on-state current is the lowest in spite of a double-gate configuration. The on-state current in FDSOI is situated between those of IM-DGFET and JL-DGFET: it is lower than in IM-DGFET because only a single gate controls the channel, but it is higher than in JL-DGFET since the channel is intrinsic and the mobility is enhanced.

**Figure 2.** Drain current as a function of gate voltage for JL-DGFET, IM-DGFET and FDSOI. The gate workfunction for each device has been finely tuned to obtain the same off-state current for all devices. Characteristics simulated for VD=0.75 V.
