**2. Flash memory architectures and electrical operation**

This paragraph provides a brief introduction to the architecture and operating principles of floating gate flash memories at both device and circuit levels. Flash memory is an electronic non-volatile storage device that can be electrically erased and reprogrammed; it offers fast read access times, as fast as dynamic RAM, although not as fast as static RAM or ROM. Flash memories are used in a wide variety of electronic devices for general storage, configuration data storage or data transfer. Modern flash memories store logical information in an array of memory cells built from floating-gate transistors. In traditional single-level cell devices, each cell stores only one bit of information. Some newer flash memory, known as multi-level cell devices can store more than one bit per cell by choosing between multiple levels of electrical charge to apply to the floating gates of its cells.

As illustrated in Fig. 1, the memory cell consists of a single n-channel transistor with a controlgate (CG) and an electrically isolated polysilicon floating gate (FG). The two gates are separated by an oxide-nitride-oxide dielectric stack (ONO), often called "inter-poly oxide". Data can be stored in the cell by adding or removing electrons in the FG, which induces changes of the threshold voltage of the cell transistor. Charge injection into the floating-gate through the tunnel oxide (TO) is governed by the electrical signals applied on the control-gate owing to the electrostatic coupling existing between the two gates. Indeed, the electrostatic potential of the FG (VFG, see Fig. 2 left) is directly determined by the potential of the CG and the amount of electrical charge stored in the FG. These operations require high voltage signals produced Computational Modeling and Monte Carlo Simulation of Soft Errors in Flash Memories http://dx.doi.org/10.5772/57220 369

oxide". Data can be stored in the cell by adding or removing electrons in the FG, which induces changes of the threshold voltage of

VT1, see Fig. 2 right) are considered to store one bit of information in the cell. The difference between the two levels, ΔVT, is directly linked to the variation of the charge amount in the FG and to the coupling capacitance between CG and FG electrodes. A reference

soft-errors in flash memories, typically several decades below the soft-error rate (SER) of static

In this context, we recently developed a numerical simulation code capable of computing the SER of floating-gate flash memories. Our simulation platform named TIARA-G4 and described in Ref. [9], has been adapted to flash memory architectures (TIARA-G4 NVM release for "Non-Volatile Memories") by modifying the device/circuit 3D geometries and by implementing a model for charge loss from the floating gates induced by ionizing particles. This chapter presents in detail our modeling and simulation approach as well as the code validation by

The chapter is organized as follows: in Section II, we briefly introduce some basic knowledge about the architecture and electrical operation of floating gate flash memories. Section III also briefly reviews the current comprehension of radiation effects in floating-gate memories. The objective of these two first sections is to introduce for a non-specialist reader the technical background necessary for a good understanding of the second part of this chapter more specifically dedicated to computational modeling and Monte Carlo simulation issues. In Section IV, we detail our modeling and simulation approach based on the adaptation of our TIARA-G4 simulation platform [9] to flash memory architectures. Finally, in Section V, we expose the simulation results and compare them to experimental results obtained on a large

This paragraph provides a brief introduction to the architecture and operating principles of floating gate flash memories at both device and circuit levels. Flash memory is an electronic non-volatile storage device that can be electrically erased and reprogrammed; it offers fast read access times, as fast as dynamic RAM, although not as fast as static RAM or ROM. Flash memories are used in a wide variety of electronic devices for general storage, configuration data storage or data transfer. Modern flash memories store logical information in an array of memory cells built from floating-gate transistors. In traditional single-level cell devices, each cell stores only one bit of information. Some newer flash memory, known as multi-level cell devices can store more than one bit per cell by choosing between multiple levels of electrical

As illustrated in Fig. 1, the memory cell consists of a single n-channel transistor with a controlgate (CG) and an electrically isolated polysilicon floating gate (FG). The two gates are separated by an oxide-nitride-oxide dielectric stack (ONO), often called "inter-poly oxide". Data can be stored in the cell by adding or removing electrons in the FG, which induces changes of the threshold voltage of the cell transistor. Charge injection into the floating-gate through the tunnel oxide (TO) is governed by the electrical signals applied on the control-gate owing to the electrostatic coupling existing between the two gates. Indeed, the electrostatic potential of the FG (VFG, see Fig. 2 left) is directly determined by the potential of the CG and the amount of electrical charge stored in the FG. These operations require high voltage signals produced

comparison of numerical results with experimental data reported in [8].

RAM (SRAM) of comparable technological nodes.

368 Computational and Numerical Simulations

collection of memories exposed to natural radiation.

charge to apply to the floating gates of its cells.

**2. Flash memory architectures and electrical operation**

As illustrated in Fig. 1, the memory cell consists of a single n-channel transistor with a control-gate (CG) and an electrically isolated polysilicon floating gate (FG). The two gates are separated by an oxide-nitride-oxide dielectric stack (ONO), often called "inter-poly Figure 1. Schematic cross-sections of a floating-gate transistor, acting as the elementary memory element in a flash memory circuit, along its length (left) and its width (right). **Figure 1.** Schematic cross-sections of a floating-gate transistor, acting as the elementary memory element in a flash memory circuit, along its length (left) and its width (right).

on-chip using special DC-to-DC converters (charge pumps) that uses capacitors as energy storage elements to create higher voltages from the circuit external supply voltage. Two threshold voltage levels (VT 0 and VT 1 , see Fig. 2 right) are considered to store one bit of information in the cell. The difference between the two levels, ΔVT, is directly linked to the variation of the charge amount in the FG and to the coupling capacitance between CG and FG electrodes. A reference voltage value VT REF, intermediate between VT 0 and VT <sup>1</sup> is considered as a demarcation level between the two logical states "0" and "1" (Fig. 2 right). the cell transistor. Charge injection into the floating-gate through the tunnel oxide (TO) is governed by the electrical signals applied on the control-gate owing to the electrostatic coupling existing between the two gates. Indeed, the electrostatic potential of the FG (VFG, see Fig. 2 left) is directly determined by the potential of the CG and the amount of electrical charge stored in the FG. These operations require high voltage signals produced on-chip using special DC-to-DC converters (charge pumps) that uses capacitors as energy storage elements to create higher voltages from the circuit external supply voltage. Two threshold voltage levels (VT0 and VT1, see Fig. 2 right) are considered to store one bit of information in the cell. The difference between the two levels, ΔVT, is directly linked to the variation of the charge amount in the FG and to the coupling capacitance between CG and FG electrodes. A reference voltage value VTREF, intermediate between VT0 and VT1 is considered as a demarcation level between the two logical states "0" and As illustrated in Fig. 1, the memory cell consists of a single n-channel transistor with a control-gate (CG) and an electrically isolated polysilicon floating gate (FG). The two gates are separated by an oxide-nitride-oxide dielectric stack (ONO), often called "inter-poly oxide". Data can be stored in the cell by adding or removing electrons in the FG, which induces changes of the threshold voltage of the cell transistor. Charge injection into the floating-gate through the tunnel oxide (TO) is governed by the electrical signals applied on the control-gate owing to the electrostatic coupling existing between the two gates. Indeed, the electrostatic potential of the FG (VFG, see Fig. 2 left) is directly determined by the potential of the CG and the amount of electrical charge stored in the FG. These operations require high voltage signals produced on-chip using special DC-to-DC converters (charge pumps) that uses capacitors as energy storage elements to create higher voltages from the circuit external supply voltage. Two threshold voltage levels (VT0 and

"1" (Fig. 2 right).

VSUB

Figure 2. Left: Equivalent capacitance network of the floating-gate transistor with four terminals and definition of the main voltage and capacitance values. Right: Electrical characteristics IDS(VCG) of the floating-gate transistor with two different values of the floating-gate charge corresponding to erased and programmed states. **Figure 2.** Left: Equivalent capacitance network of the floating-gate transistor with four terminals and definition of the main voltage and capacitance values. Right: Electrical characteristics IDS(VCG) of the floating-gate transistor with two different values of the floating-gate charge corresponding to erased and programmed states. VCG VT <sup>0</sup> VT <sup>1</sup> VT REF

To form dense circuits with storage capacities up to several millions or billions of bits, elementary memory cells are arranged in matrix, i.e. in rows and columns. In addition, cells are generally grouped to form a hierarchical organization of increasing size: groups, blocks, pages, etc. Lines, called "wordlines" are connected to the control gates and columns, called "bit-lines", are connected to the drain terminals. Around the matrix memory is the peripheral control circuitry composed of additional circuits for decoding cell addresses, generating high voltage signals (charge pumps), reading cells (sense amplifiers) and managing circuit information. There are two main types of circuit architectures at the memory plan level, called NOR and NAND gate flash memories, each corresponds to a certain manner to associate several cells. The construction and the operation of NOR and NAND flash memories are briefly described in the following. **NOR architecture:** The organization of the NOR gate flash, shown in Fig. 3(a) is the following: several cells are connected to a bit line; each cell has the source terminal connected directly to ground, and the drain terminal is connected directly to a bit line. The drain contacts of individual transistors connected to the bitline are shared between two adjacent cells. This setting of elementary devices is called "NOR flash" because it operates as a NOR gate. The default state of a single-level NOR flash cell is logically equivalent to a binary "1" value: when a suitable voltage is applied on the control gate the current flows through the To form dense circuits with storage capacities up to several millions or billions of bits, elementary memory cells are arranged in matrix, i.e. in rows and columns. In addition, cells are generally grouped to form a hierarchical organization of increasing size: groups, blocks, pages, etc. Lines, called "wordlines" are connected to the control gates and columns, called "bitlines", are connected to the drain terminals. Around the matrix memory is the peripheral control circuitry composed of additional circuits for decoding cell addresses, generating high voltage signals (charge pumps), reading cells (sense amplifiers) and managing circuit infor‐ mation. There are two main types of circuit architectures at the memory plan level, called NOR and NAND gate flash memories, each corresponds to a certain manner to associate several cells. The construction and the operation of NOR and NAND flash memories are briefly described in the following. Figure 2. Left: Equivalent capacitance network of the floating-gate transistor with four terminals and definition of the main voltage and capacitance values. Right: Electrical characteristics IDS(VCG) of the floating-gate transistor with two different values of the floating-gate charge corresponding to erased and programmed states. To form dense circuits with storage capacities up to several millions or billions of bits, elementary memory cells are arranged in matrix, i.e. in rows and columns. In addition, cells are generally grouped to form a hierarchical organization of increasing size: groups, blocks, pages, etc. Lines, called "wordlines" are connected to the control gates and columns, called "bit-lines", are connected to the drain terminals. Around the matrix memory is the peripheral control circuitry composed of additional circuits for decoding cell addresses, generating high voltage signals (charge pumps), reading cells (sense amplifiers) and managing circuit information. There are two main types of circuit architectures at the memory plan level, called NOR and NAND gate flash memories, each corresponds to a certain manner to associate several cells. The construction and the operation of NOR and NAND flash memories are briefly described in the following.

channel and the bitline voltage is pulled down. The programming operation of a NOR flash cell (i.e. setting to a binary "0" value) is done by injection of hot carriers from the channel. The high current, required by this mechanism, limits the parallelism of the operation (only some cells can be programmed in same time) [10]. The programming procedure is the following: a voltage increase (typically > 5 V) is applied to the control gate which turns on the channel and the electrons can flow from source to drain (for an nchannel MOS transistor). The source-drain current is sufficiently high so that a certain number of electrons of high energy are able to pass through the insulating layer on the floating gate by hot electrons injection mechanism. The erasing operation of a NOR flash cell (resetting it to the "1" state) is done by Fowler-Nordheim (FN) mechanism. For this purpose, a large voltage of the opposite polarity is applied between the control gate and the source terminal, pulling out the electrons from the floating gate by FN tunneling. This organization of the NOR flash allows a fast random access (approximately 100 ns). The programming operation is carried out at block level, and is much slower (approximately 5 μs). The erasing operation is carried out on the level of block and is

 **NOR architecture:** The organization of the NOR gate flash, shown in Fig. 3(a) is the following: several cells are connected to a bit line; each cell has the source terminal connected directly to ground, and the drain terminal is connected directly to a bit line. The drain contacts of individual transistors connected to the bitline are shared between two adjacent cells. This setting of elementary devices is called "NOR flash" because it operates as a NOR gate. The default state of a single-level NOR flash cell is logically equivalent to a binary "1" value: when a suitable voltage is applied on the control gate the current flows through the channel and the bitline voltage is pulled down. The programming operation of a NOR flash cell (i.e. setting to a binary "0" value) is done by injection of hot carriers from the channel. The high current, required by this mechanism, limits the parallelism of the operation (only some cells can be programmed in same time) [10]. The programming procedure is the following: a voltage increase (typically > 5 V) is applied to the control gate which turns on the channel and the electrons can flow from source to drain (for an nchannel MOS transistor). The source-drain current is sufficiently high so that a certain number of electrons of high energy are able to pass through the insulating layer on the floating gate by hot electrons injection mechanism. The erasing operation of a NOR flash cell (resetting it to the "1" state) is done by Fowler-Nordheim (FN) mechanism. For this purpose, a large voltage of the opposite polarity is applied between the control gate and the source terminal, pulling out the electrons from the floating gate by FN tunneling. This organization of the NOR flash allows a fast random access (approximately 100 ns). The programming operation is carried out at block level, and is much slower (approximately 5 μs). The erasing operation is carried out on the level of block and is **• NOR architecture:** The organization of the NOR gate flash, shown in Fig. 3(a) is the following: several cells are connected to a bit line; each cell has the source terminal connected directly to ground, and the drain terminal is connected directly to a bit line. The drain contacts of individual transistors connected to the bitline are shared between two adjacent cells. This setting of elementary devices is called "NOR flash" because it operates as a NOR gate. The default state of a single-level NOR flash cell is logically equivalent to a binary "1" value: when a suitable voltage is applied on the control gate the current flows through the channel and the bitline voltage is pulled down. The programming operation of a NOR flash cell (i.e. setting to a binary "0" value) is done by injection of hot carriers from the channel. The high current, required by this mechanism, limits the parallelism of the operation (only some cells can be programmed in same time) [10]. The programming procedure is the following: a voltage increase (typically > 5 V) is applied to the control gate which turns on the channel and the electrons can flow from source to drain (for an n-channel MOS transis‐ tor). The source-drain current is sufficiently high so that a certain number of electrons of high energy are able to pass through the insulating layer on the floating gate by hot electrons injection mechanism. The erasing operation of a NOR flash cell (resetting it to the "1" state) is done by Fowler-Nordheim (FN) mechanism. For this purpose, a large voltage of the opposite polarity is applied between the control gate and the source terminal, pulling out the electrons from the floating gate by FN tunneling. This organization of the NOR flash allows a fast random access (approximately 100 ns). The programming operation is carried out at block level, and is much slower (approximately 5 µs). The erasing operation is carried out on the level of block and is even slower, typically 200 ms [10]. Taking into account these characteristics, the NOR flash is used principally as a read-only memory mainly for code storage, for which the random access time is important, but where the programming/erasing operations are rarely carried out [10]. In the NOR architecture, the manufacturer guarantees that all individual bits are functional and meet retention and endurance specifications, as explained in [10]; no implementation of Error Correction Code (ECC) is needed from the user side. In some cases (e.g., multi-level architecture), an internal ECC, totally transparent to the user, may be present. NOR devices typically have separate buses for addresses and data [10].

few MBytes) and takes about 2 ms [10]. Block erasure is carried out also by FN tunneling, but by using opposite polarity. Thanks to these characteristics flash NAND is adapted better for the data storage, where the problems of latency are minor and the random access time is not very important. In this configuration, the use of external ECC is mandatory (which increases the latency), because the manufacturer does not guarantee each single bit and the

N+ N+ N+ N+ N+ , GND N+, GND N+, GND

**b) NAND Bit Line**

N+ N+ N+ N+ N+ N+ N+ N+ N+

Floating-gate memories are sensitive to ionizing radiation, both to total ionizing dose (TID) and single event effects (SEEs). Very schematically, ionizing radiation induces charge loss in the floating-gate and charge trapping in the different dielectric layers of the transistor stack; it can also generate interface states. The induced current transients and such parasitic charges and defects cause degradation of circuit functionality and/or loss of logical information stored in the FG array in addition to possible global circuit performance degradation. Detailed results of both TID and SEEs in flash memories are available in recent

**WL3**

**WL0 WL1 WL2 WL4 WL5**

**WL0 WL1 WL2 WL3 WL4 WL5**

**a) NOR Bit Line**

devices typically have separate buses for addresses and data [10].

even slower, typically 200 ms [10]. Taking into account these characteristics, the NOR flash is used principally as a read-only memory mainly for code storage, for which the random access time is important, but where the programming/erasing operations are rarely carried out [10]. In the NOR architecture, the manufacturer guarantees that all individual bits are functional and meet retention and endurance specifications, as explained in [10]; no implementation of Error Correction Code (ECC) is needed from the user side. In some cases (e.g., multi-level architecture), an internal ECC, totally transparent to the user, may be present. NOR

 **NAND architecture:** The organization of the NAND gate flash is shown in Fig. 3(b). In this configuration, several groups of floating-gate transistors are connected in series. These groups are then connected via some additional transistors to a NOR-style bit line array in the same way that single transistors are linked in NOR flash. Due to this arrangement, the bit line is pulled low only if all word lines are pulled high (above the threshold voltage of the transistors). This organization of elementary transistors is called NAND flash because transistors are connected in a way which is similar to a NAND gate. Compared to NOR flash, replacing single transistors with serial-linked groups adds an extra level of addressing. As explained in [10], the series arrangement and the great level of parallelism, which is achieved with this organization thanks to the low program/erase currents, give rise to a poor random access time but a very good serial access. Programming of the NAND flash is performed by FN tunneling at the page level (which is typically a few kBytes) and is carried out in about 0.2 ms [10]. The erasing operation is performed at the block level (typically a few MBytes) and takes about 2 ms [10]. Block erasure is carried out also by FN tunneling, but by using opposite polarity. Thanks to these characteristics flash NAND is adapted better for the data storage, where the problems of latency are minor and the random access time is not very important. In this configuration, the use of external ECC is mandatory (which increases the latency), because the manufacturer does not guarantee each single bit and the commercial devices may contain a few

http://dx.doi.org/10.5772/57220

371

Computational Modeling and Monte Carlo Simulation of Soft Errors in Flash Memories

Floating-gate memories are sensitive to ionizing radiation, both to total ionizing dose (TID) and single event effects (SEEs). Very schematically, ionizing radiation induces charge loss in the floating-gate and charge trapping in the different dielectric layers of the transistor stack; it can also generate interface states. The induced current transients and such parasitic charges and defects cause degradation of circuit functionality and/or loss of logical information stored in the FG array in addition to possible global circuit performance degradation. Detailed results of both TID and SEEs in flash memories are available in recent papers or review

**Bit line Select transistor**

**WL6**

In this study, we will exclusively focus on soft-errors induced by atmospheric neutrons in the FG array of flash memories. SEEs in FG memories are due to highly energetic particles that directly (heavy ions) or indirectly (neutrons) induce charge loss from the FG. Other effects may be possible, such as Single Event Functional Interruptions (SEFI) or destructive events (Single Event Gate

commercial devices may contain a few defective blocks [10].

Figure 3. Schematic representations of NOR and NAND architectures.

**3. Radiation effects in floating-gate memories** 

presentations [4-7,10-13].

papers or review presentations [4-7,10-13].

defective blocks [10].

P‐type substrate

**Ground Select transistor**

> P‐type substrate N+

**Figure 3.** Schematic representations of NOR and NAND architectures.

**3. Radiation effects in floating-gate memories**

**• NAND architecture:** The organization of the NAND gate flash is shown in Fig. 3(b). In this configuration, several groups of floating-gate transistors are connected in series. These groups are then connected via some additional transistors to a NOR-style bit line array in the same way that single transistors are linked in NOR flash. Due to this arrangement, the bit line is pulled low only if all word lines are pulled high (above the threshold voltage of the transistors). This organization of elementary transistors is called NAND flash because transistors are connected in a way which is similar to a NAND gate. Compared to NOR flash, replacing single transistors with serial-linked groups adds an extra level of addressing. As explained in [10], the series arrangement and the great level of parallelism, which is achieved with this organization thanks to the low program/erase currents, give rise to a poor random access time but a very good serial access. Programming of the NAND flash is performed by FN tunneling at the page level (which is typically a few kBytes) and is carried out in about 0.2 ms [10]. The erasing operation is performed at the block level (typically a even slower, typically 200 ms [10]. Taking into account these characteristics, the NOR flash is used principally as a read-only memory mainly for code storage, for which the random access time is important, but where the programming/erasing operations are rarely carried out [10]. In the NOR architecture, the manufacturer guarantees that all individual bits are functional and meet retention and endurance specifications, as explained in [10]; no implementation of Error Correction Code (ECC) is needed from the user side. In some cases (e.g., multi-level architecture), an internal ECC, totally transparent to the user, may be present. NOR

**NAND architecture:** The organization of the NAND gate flash is shown in Fig. 3(b). In this configuration, several groups

called NAND flash because transistors are connected in a way which is similar to a NAND gate. Compared to NOR flash, replacing

transistor stack; it can also generate interface states. The induced current transients and such parasitic charges and defects cause

few MBytes) and takes about 2 ms [10]. Block erasure is carried out also by FN tunneling, but by using opposite polarity. Thanks to these characteristics flash NAND is adapted better for the data storage, where the problems of latency are minor and the random access time is not very important. In this configuration, the use of external ECC is mandatory (which increases the latency), because the manufacturer does not guarantee each single bit and the commercial devices may contain a few defective blocks [10]. single transistors with serial-linked groups adds an extra level of addressing. As explained in [10], the series arrangement and the great level of parallelism, which is achieved with this organization thanks to the low program/erase currents, give rise to a poor random access time but a very good serial access. Programming of the NAND flash is performed by FN tunneling at the page level (which is typically a few kBytes) and is carried out in about 0.2 ms [10]. The erasing operation is performed at the block level (typically a few MBytes) and takes about 2 ms [10]. Block erasure is carried out also by FN tunneling, but by using opposite polarity. Thanks to these characteristics flash NAND is adapted better for the data storage, where the problems of latency are minor and the random access time is not very important. In this configuration, the use of external ECC is mandatory (which increases the latency), because the manufacturer does not guarantee each single bit and the commercial devices may contain a few

devices typically have separate buses for addresses and data [10].

Figure 3. Schematic representations of NOR and NAND architectures. **Figure 3.** Schematic representations of NOR and NAND architectures.

defective blocks [10].

**• NOR architecture:** The organization of the NOR gate flash, shown in Fig. 3(a) is the following: several cells are connected to a bit line; each cell has the source terminal connected directly to ground, and the drain terminal is connected directly to a bit line. The drain contacts of individual transistors connected to the bitline are shared between two adjacent cells. This setting of elementary devices is called "NOR flash" because it operates as a NOR gate. The default state of a single-level NOR flash cell is logically equivalent to a binary "1" value: when a suitable voltage is applied on the control gate the current flows through the channel and the bitline voltage is pulled down. The programming operation of a NOR flash cell (i.e. setting to a binary "0" value) is done by injection of hot carriers from the channel. The high current, required by this mechanism, limits the parallelism of the operation (only some cells can be programmed in same time) [10]. The programming procedure is the following: a voltage increase (typically > 5 V) is applied to the control gate which turns on the channel and the electrons can flow from source to drain (for an n-channel MOS transis‐ tor). The source-drain current is sufficiently high so that a certain number of electrons of high energy are able to pass through the insulating layer on the floating gate by hot electrons injection mechanism. The erasing operation of a NOR flash cell (resetting it to the "1" state) is done by Fowler-Nordheim (FN) mechanism. For this purpose, a large voltage of the opposite polarity is applied between the control gate and the source terminal, pulling out the electrons from the floating gate by FN tunneling. This organization of the NOR flash allows a fast random access (approximately 100 ns). The programming operation is carried out at block level, and is much slower (approximately 5 µs). The erasing operation is carried out on the level of block and is even slower, typically 200 ms [10]. Taking into account these characteristics, the NOR flash is used principally as a read-only memory mainly for code storage, for which the random access time is important, but where the programming/erasing operations are rarely carried out [10]. In the NOR architecture, the manufacturer guarantees that all individual bits are functional and meet retention and endurance specifications, as explained in [10]; no implementation of Error Correction Code (ECC) is needed from the user side. In some cases (e.g., multi-level architecture), an internal ECC, totally transparent to the user, may be present. NOR devices typically have separate buses for addresses and

**• NAND architecture:** The organization of the NAND gate flash is shown in Fig. 3(b). In this configuration, several groups of floating-gate transistors are connected in series. These groups are then connected via some additional transistors to a NOR-style bit line array in the same way that single transistors are linked in NOR flash. Due to this arrangement, the bit line is pulled low only if all word lines are pulled high (above the threshold voltage of the transistors). This organization of elementary transistors is called NAND flash because transistors are connected in a way which is similar to a NAND gate. Compared to NOR flash, replacing single transistors with serial-linked groups adds an extra level of addressing. As explained in [10], the series arrangement and the great level of parallelism, which is achieved with this organization thanks to the low program/erase currents, give rise to a poor random access time but a very good serial access. Programming of the NAND flash is performed by FN tunneling at the page level (which is typically a few kBytes) and is carried out in about 0.2 ms [10]. The erasing operation is performed at the block level (typically a

data [10].

370 Computational and Numerical Simulations

#### Floating-gate memories are sensitive to ionizing radiation, both to total ionizing dose (TID) and single event effects (SEEs). Very schematically, ionizing radiation induces charge loss in the floating-gate and charge trapping in the different dielectric layers of the **3. Radiation effects in floating-gate memories**

degradation of circuit functionality and/or loss of logical information stored in the FG array in addition to possible global circuit performance degradation. Detailed results of both TID and SEEs in flash memories are available in recent papers or review presentations [4-7,10-13]. In this study, we will exclusively focus on soft-errors induced by atmospheric neutrons in the FG array of flash memories. SEEs in FG memories are due to highly energetic particles that directly (heavy ions) or indirectly (neutrons) induce charge loss from the FG. Other effects may be possible, such as Single Event Functional Interruptions (SEFI) or destructive events (Single Event Gate Floating-gate memories are sensitive to ionizing radiation, both to total ionizing dose (TID) and single event effects (SEEs). Very schematically, ionizing radiation induces charge loss in the floating-gate and charge trapping in the different dielectric layers of the transistor stack; it can also generate interface states. The induced current transients and such parasitic charges and defects cause degradation of circuit functionality and/or loss of logical information stored in the FG array in addition to possible global circuit performance degradation. Detailed results of both TID and SEEs in flash memories are available in recent papers or review presentations [4-7,10-13].

**3. Radiation effects in floating-gate memories** 

In this study, we will exclusively focus on soft-errors induced by atmospheric neutrons in the FG array of flash memories. SEEs in FG memories are due to highly energetic particles that directly (heavy ions) or indirectly (neutrons) induce charge loss from the FG. Other effects may be possible, such as Single Event Functional Interruptions (SEFI) or destructive events (Single Event Gate Rupture – SEGR) at the level of the FG array or in the peripheral circuitry. Note that SEEs only affect FG cells impacted by at least one particle whereas TID uniformly impacts the programmed FG cells.

The authors summarized these earlier models and underlined theirs strengths and limitations; such classical models include the trap assisted tunneling (TAT), the conductive pipe model, the generation-recombination-transport in oxide and the electron emission. The most impor‐ tant limitation of these approaches is their failure to quantitatively predict the charge loss on the basis of a set of physics-based equations without any fitting parameter and/or phenom‐ enological assumption. The authors have then proposed a new model, called Transient Carrier Flux (TCF) model, which quantitatively explains the observed charge loss in FG memories irradiated with heavy ions. Figure 5 illustrates all these different physical mechanisms and

Computational Modeling and Monte Carlo Simulation of Soft Errors in Flash Memories

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373

**1. Generation/Recombination/Transport in Oxide:** The ion strike produces hot holes in the tunnel oxide or inter-poly dielectric and a certain fraction of these hot holes are not recombined in the prompt recombination phase. This model considers that the notrecombined holes [15] may drift into the floating gate. This may be possible since the negative electron charge stored on the floating gate itself produces an electrical field across the oxide which attracts holes. These holes that drift in FG are recombined with electrons stored in FG and cause a reduction in the negative charge on the floating gate. At the same time, the electrons produced by the ionizing particle are quickly transported to the silicon bulk or to the control gate due to their high mobility. However, this model lacks sufficient experimental validation because it does not agree quantitatively with data loss measured in FG Flash memory cells [16]. Indeed, the number of holes that survive the prompt recombination after a heavy ion strike in a 10 nm tunnel oxide is less than 100, while the

**2. Electron Emission:** This phenomenon was originally proposed by Snyder et al. as one of the main mechanisms of charge loss in FG EEPROM cells under gamma ray irradiation [17]. The charge loss is explained by the fact that electrons stored in the floating gate can gain energy from ionizing radiation and can be emitted over the oxide barrier in the control gate or in the silicon substrate. This mechanism is also called photoemission. The emission over the oxide has been empirically modeled. However, this mechanism has not been physically modeled or extended heavy ions or to other particles [14]. Moreover, in this model, the photoemission is limited only to electrons stored in the floating gate which has no physical justification [14]. In fact, an ionizing particle strike can generate a number of electrons much larger than the net number of electrons stored in the floating gate. Some of the electrons generated by the particle strike may have enough energy to be emitted

**3. Trap Assisted Tunneling (TAT):** This mechanism is one of the most important causes of oxide wear out due to electrical stress of program/erased cycles of a FG cell. When an ionizing particle strikes the cell, defects are created in the tunnel oxide. These defects may provide a percolation path for the electrons which can thus pass by tunneling effect through the tunnel oxide; therefore, this mechanism is called trap assisted tunneling (TAT). It has been shown that TAT is responsible for retention problems in at least a certain percentage of irradiated devices [14]. However, a very long time is required to discharge a FG cell by TAT mechanism (a few hours to a few weeks) [16]. Therefore, the TAT

data show that the charge loss is a few thousand electrons [14].

models, which are shortly detailed in the following.

over the oxide barriers [14].

**Figure 4.** Schematic illustration of the effects of highly ionizing particle irradiation on the threshold voltage distribu‐ tions of a floating gate array. Adapted from Paccagnella et al. [12].

Neutrons are not ionizing (they not directly create e- /h+ pairs in the matter) and specifically due to their neutral character, they can penetrate deeply into the chip atomic structure. Only the resulting products of the neutron-silicon (or other atoms of the circuit, O, W, Al, etc.) collisions are ionizing and, by consequence, only the impact of such secondary products on the FG can result in charge loss. This is the reason why, in the following, we will focus on the underlying physical mechanisms of charge loss induced by ionizing particles, but the link with atmospheric neutrons remains evident.

Figure 4 illustrates the effects of ionizing-particle irradiation on the threshold voltage distri‐ butions of a large array of FG devices. Before irradiation, threshold voltages of individual cells are distributed following a typical Gaussian distribution, sharply centered on the programmed value VT 1 . A secondary peak and a tail appear after irradiation: these structures correspond to all cells that have been hit by incident ionizing particles. The position (VT shift) of the peak with respect to the initial distribution gives the average threshold voltage shift: it is directly linked to the ion Linear Energy Transfer (LET) and to the electric field in the tunnel oxide. The height of the peak is related to the irradiation fluence. Finally, the tail is related to all memory cells for which the VT values are intermediate between the secondary peak and the initial distribution. Of course, all cells, initially programmed at VT <sup>1</sup> and having their post-irradiation VT value below VT REF, have been upset.

In their IRPS 2008 paper [14], Butt and Alam reviewed several models of charge loss due to a radiation particle strike. Different physical mechanisms have been proposed in the literature for the modeling of the charge loss from floating gates after single radiation particles strikes. The authors summarized these earlier models and underlined theirs strengths and limitations; such classical models include the trap assisted tunneling (TAT), the conductive pipe model, the generation-recombination-transport in oxide and the electron emission. The most impor‐ tant limitation of these approaches is their failure to quantitatively predict the charge loss on the basis of a set of physics-based equations without any fitting parameter and/or phenom‐ enological assumption. The authors have then proposed a new model, called Transient Carrier Flux (TCF) model, which quantitatively explains the observed charge loss in FG memories irradiated with heavy ions. Figure 5 illustrates all these different physical mechanisms and models, which are shortly detailed in the following.

In this study, we will exclusively focus on soft-errors induced by atmospheric neutrons in the FG array of flash memories. SEEs in FG memories are due to highly energetic particles that directly (heavy ions) or indirectly (neutrons) induce charge loss from the FG. Other effects may be possible, such as Single Event Functional Interruptions (SEFI) or destructive events (Single Event Gate Rupture – SEGR) at the level of the FG array or in the peripheral circuitry. Note that SEEs only affect FG cells impacted by at least one particle whereas TID uniformly impacts

**Figure 4.** Schematic illustration of the effects of highly ionizing particle irradiation on the threshold voltage distribu‐

due to their neutral character, they can penetrate deeply into the chip atomic structure. Only the resulting products of the neutron-silicon (or other atoms of the circuit, O, W, Al, etc.) collisions are ionizing and, by consequence, only the impact of such secondary products on the FG can result in charge loss. This is the reason why, in the following, we will focus on the underlying physical mechanisms of charge loss induced by ionizing particles, but the link with

Figure 4 illustrates the effects of ionizing-particle irradiation on the threshold voltage distri‐ butions of a large array of FG devices. Before irradiation, threshold voltages of individual cells are distributed following a typical Gaussian distribution, sharply centered on the programmed

all cells that have been hit by incident ionizing particles. The position (VT shift) of the peak with respect to the initial distribution gives the average threshold voltage shift: it is directly linked to the ion Linear Energy Transfer (LET) and to the electric field in the tunnel oxide. The height of the peak is related to the irradiation fluence. Finally, the tail is related to all memory cells for which the VT values are intermediate between the secondary peak and the initial

In their IRPS 2008 paper [14], Butt and Alam reviewed several models of charge loss due to a radiation particle strike. Different physical mechanisms have been proposed in the literature for the modeling of the charge loss from floating gates after single radiation particles strikes.

. A secondary peak and a tail appear after irradiation: these structures correspond to

/h+

pairs in the matter) and specifically

<sup>1</sup> and having their post-irradiation

tions of a floating gate array. Adapted from Paccagnella et al. [12].

Neutrons are not ionizing (they not directly create e-

distribution. Of course, all cells, initially programmed at VT

REF, have been upset.

atmospheric neutrons remains evident.

value VT 1

VT value below VT

the programmed FG cells.

372 Computational and Numerical Simulations


mechanism cannot be responsible for SEU in FG cell taking into account that SEU data are taken immediately after the cell irradiation and then do not change with time [14]. TAT may nevertheless result in hard errors that cause retention problems of FG cell. 3. **Trap Assisted Tunneling (TAT):** This mechanism is one of the most important causes of oxide wear out due to electrical stress of program/erased cycles of a FG cell. When an ionizing particle strikes the cell, defects are created in the tunnel oxide. These defects may provide a percolation path for the electrons which can thus pass by tunneling effect through the tunnel oxide;

**4. Conductive Pipe Model:** This model has been proposed by Cellere et al. to explain the charge loss due to heavy ions strikes [15], [18]. This model assumes that the dense plasma of e-h pairs generated by the ion strike creates a temporary very thin (~ 10 nm) conductive path in the tunnel oxide during a short time (sub picosecond) after the strike. This is accompanied by the local lowering of the oxide energy barrier, which allows the electrons stored in the floating gate to pass through this conducting pipe. This phenomenological model reproduces well the experimental data of charge loss. However, there is a lack of physical explanation of the mechanisms governing both the resistance of the conductive path and the oxide barrier lowering [14]. therefore, this mechanism is called trap assisted tunneling (TAT). It has been shown that TAT is responsible for retention problems in at least a certain percentage of irradiated devices [14]. However, a very long time is required to discharge a FG cell by TAT mechanism (a few hours to a few weeks) [16]. Therefore, the TAT mechanism cannot be responsible for SEU in FG cell taking into account that SEU data are taken immediately after the cell irradiation and then do not change with time [14]. TAT may nevertheless result in hard errors that cause retention problems of FG cell. 4. **Conductive Pipe Model:** This model has been proposed by Cellere et al. to explain the charge loss due to heavy ions strikes [15], [18]. This model assumes that the dense plasma of e-h pairs generated by the ion strike creates a temporary very thin (~ 10 nm) conductive path in the tunnel oxide during a short time (sub picosecond) after the strike. This is accompanied by the local lowering of the oxide energy barrier, which allows the electrons stored in the floating gate to pass through this conducting pipe. This phenomenological model reproduces well the experimental data of charge loss. However, there is a lack of physical

explanation of the mechanisms governing both the resistance of the conductive path and the oxide barrier lowering [14].

**5. Transient-Carrier-Flux (TCF) model:** This model was proposed by Butt and Alam [14] to explain the charge loss due to a SEU in FG memory cells. In this model it is assumed that the dominant physical mechanism that causes the FG charge loss due to a particle strike is the net flux of hot carriers flowing within a short time (~ ps) over the oxide barrier at the FG/oxide interfaces. After a particle strike, a dense cluster of hot electron-hole pairs are generated with carriers having broad energy distributions which return to thermal equilibrium in a time ~ 1 ps [14]. The tail of the high energy distribution induces a transient carrier flow in and out of the floating gate over the tunnel and inter-poly oxides. In case of a zero electric field in the oxide, the incoming and outgoing carrier flow balances each other at both oxide/FG interfaces and therefore the net flux is zero. On the contrary, in the programmed state, the electron negative charge stored in the floating gate induces a relatively high electric field in the oxide. Due to this electric field the electrons flux leaving the floating gate is greater than the electron flux entering the floating gate. In addition, the incoming holes flux is greater than the holes flux exiting the floating gate. The net flux therefore causes a reduction of the number of electrons stored in the floating gate. A small imbalance between the incoming and outgoing fluxes may be sufficient to disturb the state of the memory cell for which the tolerance of charge loss can be 100 electrons or less [14]. Butt and Alam validated their model by numerical simulations using a high-energy particle physics based toolkit - Geant4 for the generation and initial energy distributions in the high energy range (~10eV - ~ keVs). The hydrodynamic model coupled with Monte Carlo simulations was used for carrier relaxation in low energy (< 10eV) range, in order to accurately take into account the energy relaxation due to phonon scattering and impact ionization [14]. The transient fluxes of hot carriers flowing in and out the floating gate over the barrier oxides are calculated by solving self-consistently a system of equations including the transmission probability through the oxides and the Poisson equation, until carriers relax and reach the thermal equilibrium. These fluxes are then used to obtain the charge loss in flash memory cells due to alpha particles and cosmic neutron strikes. Butt and Alam finally demonstrated that the TCF model is in very good agreement with

Computational Modeling and Monte Carlo Simulation of Soft Errors in Flash Memories

http://dx.doi.org/10.5772/57220

375

experimental data from Ref. [16], as will be shown later in Section 4.2.

compute the SER related to the floating-gate array of a flash memory circuit.

**4.1. Description of TIARA-G4 NVM platform**

**platform**

**4. Modeling and simulation of non-volatile memories using TIARA-G4**

In this section, we describe in details our modeling and numerical simulation approaches to

The Tool Suite for Radiation Reliability Assessment (TIARA) platform has been devel‐ oped these last years conjointly at Aix-Marseille University (IM2NP laboratory) and at STMicroelectronics (Central R&D, Crolles). The last version of the code has been called TIARA-G4 in reference to the fact that it is totally rewritten in C++ using Geant4 classes

5. **Transient-Carrier-Flux (TCF) model:** This model was proposed by Butt and Alam [14] to explain the charge loss due to a SEU in FG memory cells. In this model it is assumed that the dominant physical mechanism that causes the FG charge loss due to a particle strike is the net flux of hot carriers flowing within a short time (~ ps) over the oxide barrier at the FG/oxide interfaces. After a particle strike, a dense cluster of hot electron-hole pairs are generated with carriers having broad energy distributions which return to thermal equilibrium in a time ~ 1 ps [14]. The tail of the high energy distribution induces a transient carrier flow in and out of the floating gate over the tunnel and inter-poly oxides. In case of a zero electric field in the oxide, the incoming and outgoing carrier flow balances each other at both oxide/FG interfaces and therefore the net flux is zero. On the contrary, in the programmed state, the electron negative charge stored in the floating gate induces a relatively high electric field in the oxide. Due to this electric field the electrons flux leaving the floating gate is greater than the electron flux entering the floating gate. In addition, the incoming holes flux is greater than the holes flux exiting the floating gate. The net flux therefore causes a reduction of the number of electrons stored in the floating gate. A small imbalance between the incoming and outgoing fluxes may be sufficient to disturb the state of the memory cell for which the tolerance of charge loss can be 100 electrons or less [14]. Butt and Alam validated their model by numerical simulations using a high-energy particle physics based toolkit - Geant4 for the generation and initial energy distributions in the high energy range (~10eV - ~ keVs). The hydrodynamic model coupled with Monte Carlo simulations was used

Figure 5. Schematic illustration of different models of charge loss due to a radiation particle strike. Adapted from Butt et Alam [14]. **Figure 5.** Schematic illustration of different models of charge loss due to a radiation particle strike. Adapted from Butt et Alam [14].

3. **Trap Assisted Tunneling (TAT):** This mechanism is one of the most important causes of oxide wear out due to electrical stress of program/erased cycles of a FG cell. When an ionizing particle strikes the cell, defects are created in the tunnel oxide. These defects may provide a percolation path for the electrons which can thus pass by tunneling effect through the tunnel oxide; therefore, this mechanism is called trap assisted tunneling (TAT). It has been shown that TAT is responsible for retention problems in at least a certain percentage of irradiated devices [14]. However, a very long time is required to discharge a FG cell by TAT mechanism (a few hours to a few weeks) [16]. Therefore, the TAT mechanism cannot be responsible for SEU in FG cell taking into account that SEU data are taken immediately after the cell irradiation and then do not change with time [14]. TAT may nevertheless 4. **Conductive Pipe Model:** This model has been proposed by Cellere et al. to explain the charge loss due to heavy ions strikes [15], [18]. This model assumes that the dense plasma of e-h pairs generated by the ion strike creates a temporary very thin (~ 10 nm) conductive path in the tunnel oxide during a short time (sub picosecond) after the strike. This is accompanied by the local lowering of the oxide energy barrier, which allows the electrons stored in the floating gate to pass through this conducting pipe. This phenomenological model reproduces well the experimental data of charge loss. However, there is a lack of physical explanation of the mechanisms governing both the resistance of the conductive path and the oxide barrier lowering [14]. **5. Transient-Carrier-Flux (TCF) model:** This model was proposed by Butt and Alam [14] to explain the charge loss due to a SEU in FG memory cells. In this model it is assumed that the dominant physical mechanism that causes the FG charge loss due to a particle strike is the net flux of hot carriers flowing within a short time (~ ps) over the oxide barrier at the FG/oxide interfaces. After a particle strike, a dense cluster of hot electron-hole pairs are generated with carriers having broad energy distributions which return to thermal equilibrium in a time ~ 1 ps [14]. The tail of the high energy distribution induces a transient carrier flow in and out of the floating gate over the tunnel and inter-poly oxides. In case of a zero electric field in the oxide, the incoming and outgoing carrier flow balances each other at both oxide/FG interfaces and therefore the net flux is zero. On the contrary, in the programmed state, the electron negative charge stored in the floating gate induces a relatively high electric field in the oxide. Due to this electric field the electrons flux leaving the floating gate is greater than the electron flux entering the floating gate. In addition, the incoming holes flux is greater than the holes flux exiting the floating gate. The net flux therefore causes a reduction of the number of electrons stored in the floating gate. A small imbalance between the incoming and outgoing fluxes may be sufficient to disturb the state of the memory cell for which the tolerance of charge loss can be 100 electrons or less [14]. Butt and Alam validated their model by numerical simulations using a high-energy particle physics based toolkit - Geant4 for the generation and initial energy distributions in the high energy range (~10eV - ~ keVs). The hydrodynamic model coupled with Monte Carlo simulations was used for carrier relaxation in low energy (< 10eV) range, in order to accurately take into account the energy relaxation due to phonon scattering and impact ionization [14]. The transient fluxes of hot carriers flowing in and out the floating gate over the barrier oxides are calculated by solving self-consistently a system of equations including the transmission probability through the oxides and the Poisson equation, until carriers relax and reach the thermal equilibrium. These fluxes are then used to obtain the charge loss in flash memory cells due to alpha particles and cosmic neutron strikes. Butt and Alam finally demonstrated that the TCF model is in very good agreement with experimental data from Ref. [16], as will be shown later in Section 4.2.
