**4. Modeling and simulation of non-volatile memories using TIARA-G4 platform**

In this section, we describe in details our modeling and numerical simulation approaches to compute the SER related to the floating-gate array of a flash memory circuit.

### **4.1. Description of TIARA-G4 NVM platform**

mechanism cannot be responsible for SEU in FG cell taking into account that SEU data are taken immediately after the cell irradiation and then do not change with time [14]. TAT

Figure 5. Schematic illustration of different models of charge loss due to a radiation particle strike. Adapted from Butt et Alam [14].

5. **Transient-Carrier-Flux (TCF) model:** This model was proposed by Butt and Alam [14] to explain the charge loss due to a SEU in FG memory cells. In this model it is assumed that the dominant physical mechanism that causes the FG charge loss due to a particle strike is the net flux of hot carriers flowing within a short time (~ ps) over the oxide barrier at the FG/oxide interfaces. After a particle strike, a dense cluster of hot electron-hole pairs are generated with carriers having broad energy distributions which return to thermal equilibrium in a time ~ 1 ps [14]. The tail of the high energy distribution induces a transient carrier flow in and out of the floating gate over the tunnel and inter-poly oxides. In case of a zero electric field in the oxide, the incoming and outgoing carrier flow balances each other at both oxide/FG interfaces and therefore the net flux is zero. On the contrary, in the programmed state, the electron negative charge stored in the floating gate induces a relatively high electric field in the oxide. Due to this electric field the electrons flux leaving the floating gate is greater than the electron flux entering the floating gate. In addition, the incoming holes flux is greater than the holes flux exiting the floating gate. The net flux therefore causes a reduction of the number of electrons stored in the floating gate. A small imbalance between the incoming and outgoing fluxes may be sufficient to disturb the state of the memory cell for which the tolerance of charge loss can be 100 electrons or less [14]. Butt and Alam validated their model by numerical simulations using a high-energy particle physics based toolkit - Geant4 for the generation and initial energy distributions in the high energy range (~10eV - ~ keVs). The hydrodynamic model coupled with Monte Carlo simulations was used

may nevertheless result in hard errors that cause retention problems of FG cell.

result in hard errors that cause retention problems of FG cell.

CG ONO FG TO

CG ONO FG TO

**(3) TrapAssisted Tunneling (TAT) (4) Conductive Pipe Model**

strike e‐ h+

**(5) Transient Carrier Flux (TCF)**

**Figure 5.** Schematic illustration of different models of charge loss due to a radiation particle strike. Adapted from Butt

*P‐type Substrate*

*SourceN+ Drain N+*

QFG<0

pipe

QFG<0

**(2) Electron Emission**

*SourceN+ Drain N+*

CG ONO FG TO

*P‐type Substrate*

*P‐type Substrate*

Conductive Particle strike

Particle strike

*SourceN+ Drain N+*

CG ONO FG TO

> CG ONO FG TO

path and the oxide barrier lowering [14].

QFG<0

374 Computational and Numerical Simulations

QFG<0

et Alam [14].

**(1)Generation/Recombination/ Transport inOxide**

Particle strike

*SourceN+ Drain N+*

QFG<0

Particle

*P‐type Substrate*

*P‐type Substrate*

*SourceN+ Drain N+*

Particle strike

**4. Conductive Pipe Model:** This model has been proposed by Cellere et al. to explain the charge loss due to heavy ions strikes [15], [18]. This model assumes that the dense plasma of e-h pairs generated by the ion strike creates a temporary very thin (~ 10 nm) conductive path in the tunnel oxide during a short time (sub picosecond) after the strike. This is accompanied by the local lowering of the oxide energy barrier, which allows the electrons stored in the floating gate to pass through this conducting pipe. This phenomenological model reproduces well the experimental data of charge loss. However, there is a lack of physical explanation of the mechanisms governing both the resistance of the conductive

> The Tool Suite for Radiation Reliability Assessment (TIARA) platform has been devel‐ oped these last years conjointly at Aix-Marseille University (IM2NP laboratory) and at STMicroelectronics (Central R&D, Crolles). The last version of the code has been called TIARA-G4 in reference to the fact that it is totally rewritten in C++ using Geant4 classes

and libraries and compiled as a full Geant4 application [19]. This major evolution of TIARA allows us to consider now all the complexity of a given integrated circuit in terms of materials, doping and 3D geometry, using the Virtual Geometry Model (VGM [20]) factory and interface with both Geant4 for calculation and Root [21] for visualization. Up to now, TIARA-G4 has been used to simulate the interaction of Geant4 particles (including high energy and thermal neutrons, protons, muons, alpha-particles and heavy ions) with various SRAM and Flip-Flop architectures [9].

[22]. Figure 7(a) shows a TEM cross-section of the floating-gate devices along the transistor channel and Figure 7(b) shows a portion of the cell array layout at metal1/metal2 level. The

domains have been modeled as simple axis-aligned box volumes (Geant4 elements) of different materials (silicon, silicon dioxide, ONO and back-end-of-line stack), as illustrated in Figure 7(c) for a portion of the memory array. Figure 7(d) also shows a larger view of the array with

In complementto geometrical aspects, we also implemented in TIARA-G4 NVM a new module describing the charge loss from floating gates after single radiation particles strikes. From the review of the different available models in literature presented in Section 3, our initial choice was to adopt the full physical model of the Transient Carrier Flux (TCF) proposed by Butt and Alam [14]. The original approach of these authors is therefore based on complex simulations, in particular for the computation of carrier relaxation in the low energy (< 10eV) range, using coupled hydrodynamic and Monte Carlo simulations in order to correctly account for energy relaxation due to phonon scattering and impact ionization. This requires outsourcing from the main code the calculation of the charge loss from FG as a function of the incident particle

calculation of the charge loss from FG as a function of the incident particle properties.

Figure 6. Schematics of the TIARA-G4 NVM simulation flow showing the different code inputs and outputs and the links with Geant4 classes,

Computational Modeling and Monte Carlo Simulation of Soft Errors in Flash Memories

In complement to geometrical aspects, we also implemented in TIARA-G4 NVM a new module describing the charge loss from floating gates after single radiation particles strikes. From the review of the different available models in literature presented in Section 3, our initial choice was to adopt the full physical model of the Transient Carrier Flux (TCF) proposed by Butt and Alam [14]. The original approach of these authors is therefore based on complex simulations, in particular for the computation of carrier relaxation in the low energy (< 10eV) range, using coupled hydrodynamic and Monte Carlo simulations in order to correctly account for energy relaxation due to phonon scattering and impact ionization. This requires outsourcing from the main code the

Figure 7. 90 nm NOR floating-gate flash memory architecture considered in this work. (a) TEM cross-section of the floating-gate transistor geometry along the transistor channel and (b) layout of the cell array at metal1/metal2 level. (c) and (d): ROOT screenshots of a TIARA-G4 simulation showing detailed (c) and global (d) views of the memory array and different particle tracks resulting from atmospheric neutrons interaction with circuit materials. For a better view at FG cell level, all BEOL materials (6 metal levels), silicon substrate and intra-cell silicon and

An example of Butt and Alam's simulations is illustrated in Figure 8. Simulated curves very well reproduce experimental data without any fitting parameter (data extracted from Fig. 12 of Ref. [14]). From a practical point-of-view and in absence of a relatively simple computational solution to implement the Butt and Alam's model, we adopted a pragmatic approach assuming that an

Figure 8 shows that Eq. (1) is able to very well reproduce data. Of course, fitting coefficients A and B must be carefully evaluated for each device considered for the simulation from experimental measurements (heavy ion irradiation) or complementary numerical simulation using the Butt and Alam's complete computational procedure. The next release of TIARA-G4 NVM will integrate such an external dedicated module to confer to the code the capability to simulate a wide variety of NVM devices.

In the particular case of the present study and by chance, Figure 8 is based on data from Cellere et al. who precisely worked on STMicoelectronics FG arrays. It has been found that device T3 in Ref. [16] is technologically very close to our circuit, with the same thicknesses for the different layers composing both the FEOL and BEOL stacks. In order to consider values given by Eq. (1) to our memory devices, we introduced a scaling factor coefficient to take into account the difference in the dimensions of the floating gate polysilicon electrodes between devices considered in Fig. 8 and the present memory cell architecture (simple ratio of the volumes). Without any other calibration, we use in the following Eq. (1) to directly derive the threshold voltage shift resulting from a single

ionizing particle of LET striking the FG produces a Number of Electron Loss given by the following analytical function:

**Figure 7.** nm NOR floating-gate flash memory architecture considered in this work. (a) TEM cross-section of the float‐ ing-gate transistor geometry along the transistor channel and (b) layout of the cell array at metal1/metal2 level. (c) and (d): ROOT screenshots of a TIARA-G4 simulation showing detailed (c) and global (d) views of the memory array and different particle tracks resulting from atmospheric neutrons interaction with circuit materials. For a better view at FG cell level, all BEOL materials (6 metal levels), silicon substrate and intra-cell silicon and dielectrics are not shown.

. In TIARA-G4 NVM, the different transistor

http://dx.doi.org/10.5772/57220

377

elementary memory cell has an area of 0.18 µm2

**4.2. Physical model considered**

properties.

different particle tracks interacting with certain floating-gate stacks.

libraries, models or external modules and visualization tools.

**4.2. Physical model considered** 

**<sup>a</sup> <sup>c</sup>**

dielectrics are not shown.

**b d**

<sup>2</sup> *NEL A LET B LET* (1)

particle strike in the FG domain using:

Figure 6 shows a schematic of the new TIARA-G4 NVM simulation flow structured into several independent modules and integrating new dedicated modules/subroutines to floating-gate NVM devices. In particular, we wrote a new cell/circuit construction model to reproduce the flash chip geometry (floating-gate array) with high fidelity. A second dedicated module implementing a physical model for radiation-induced charge loss from the floating-gate has been also developed, as detailed in paragraph 4.2.

**Figure 6.** Schematics of the TIARA-G4 NVM simulation flow showing the different code inputs and outputs and the links with Geant4 classes, libraries, models or external modules and visualization tools.

To test the capability of the code to consider a real geometry, we based our developments on a NOR floating-gate flash memory architecture designed and fabricated by STMicroelectronics using a 90 nm CMOS process. This process is based on a Boro-Phospho-Silicate Glass (BPSG) free Back-End Of Line (BEOL) which eliminates the major source of 10B in the circuits and drastically reduces the possible interaction between 10B and low – thermal energy neutrons [22]. Figure 7(a) shows a TEM cross-section of the floating-gate devices along the transistor channel and Figure 7(b) shows a portion of the cell array layout at metal1/metal2 level. The elementary memory cell has an area of 0.18 µm2 . In TIARA-G4 NVM, the different transistor domains have been modeled as simple axis-aligned box volumes (Geant4 elements) of different materials (silicon, silicon dioxide, ONO and back-end-of-line stack), as illustrated in Figure 7(c) for a portion of the memory array. Figure 7(d) also shows a larger view of the array with different particle tracks interacting with certain floating-gate stacks.

### **4.2. Physical model considered**

and libraries and compiled as a full Geant4 application [19]. This major evolution of TIARA allows us to consider now all the complexity of a given integrated circuit in terms of materials, doping and 3D geometry, using the Virtual Geometry Model (VGM [20]) factory and interface with both Geant4 for calculation and Root [21] for visualization. Up to now, TIARA-G4 has been used to simulate the interaction of Geant4 particles (including high energy and thermal neutrons, protons, muons, alpha-particles and heavy ions) with various

Figure 6 shows a schematic of the new TIARA-G4 NVM simulation flow structured into several independent modules and integrating new dedicated modules/subroutines to floating-gate NVM devices. In particular, we wrote a new cell/circuit construction model to reproduce the flash chip geometry (floating-gate array) with high fidelity. A second dedicated module implementing a physical model for radiation-induced charge loss from the floating-gate has

**Figure 6.** Schematics of the TIARA-G4 NVM simulation flow showing the different code inputs and outputs and the

To test the capability of the code to consider a real geometry, we based our developments on a NOR floating-gate flash memory architecture designed and fabricated by STMicroelectronics using a 90 nm CMOS process. This process is based on a Boro-Phospho-Silicate Glass (BPSG) free Back-End Of Line (BEOL) which eliminates the major source of 10B in the circuits and drastically reduces the possible interaction between 10B and low – thermal energy neutrons

links with Geant4 classes, libraries, models or external modules and visualization tools.

SRAM and Flip-Flop architectures [9].

376 Computational and Numerical Simulations

been also developed, as detailed in paragraph 4.2.

In complementto geometrical aspects, we also implemented in TIARA-G4 NVM a new module describing the charge loss from floating gates after single radiation particles strikes. From the review of the different available models in literature presented in Section 3, our initial choice was to adopt the full physical model of the Transient Carrier Flux (TCF) proposed by Butt and Alam [14]. The original approach of these authors is therefore based on complex simulations, in particular for the computation of carrier relaxation in the low energy (< 10eV) range, using coupled hydrodynamic and Monte Carlo simulations in order to correctly account for energy relaxation due to phonon scattering and impact ionization. This requires outsourcing from the main code the calculation of the charge loss from FG as a function of the incident particle properties. Figure 6. Schematics of the TIARA-G4 NVM simulation flow showing the different code inputs and outputs and the links with Geant4 classes, libraries, models or external modules and visualization tools. **4.2. Physical model considered**  In complement to geometrical aspects, we also implemented in TIARA-G4 NVM a new module describing the charge loss from floating gates after single radiation particles strikes. From the review of the different available models in literature presented in Section 3, our initial choice was to adopt the full physical model of the Transient Carrier Flux (TCF) proposed by Butt and Alam [14]. The original approach of these authors is therefore based on complex simulations, in particular for the computation of carrier relaxation in the low energy (< 10eV) range, using coupled hydrodynamic and Monte Carlo simulations in order to correctly account for energy relaxation due to phonon scattering and impact ionization. This requires outsourcing from the main code the

calculation of the charge loss from FG as a function of the incident particle properties.

Figure 7. 90 nm NOR floating-gate flash memory architecture considered in this work. (a) TEM cross-section of the floating-gate transistor geometry along the transistor channel and (b) layout of the cell array at metal1/metal2 level. (c) and (d): ROOT screenshots of a TIARA-G4 simulation showing detailed (c) and global (d) views of the memory array and different particle tracks resulting from atmospheric neutrons interaction with circuit materials. For a better view at FG cell level, all BEOL materials (6 metal levels), silicon substrate and intra-cell silicon and dielectrics are not shown. **Figure 7.** nm NOR floating-gate flash memory architecture considered in this work. (a) TEM cross-section of the float‐ ing-gate transistor geometry along the transistor channel and (b) layout of the cell array at metal1/metal2 level. (c) and (d): ROOT screenshots of a TIARA-G4 simulation showing detailed (c) and global (d) views of the memory array and different particle tracks resulting from atmospheric neutrons interaction with circuit materials. For a better view at FG cell level, all BEOL materials (6 metal levels), silicon substrate and intra-cell silicon and dielectrics are not shown.

<sup>2</sup> *NEL A LET B LET* (1)

particle strike in the FG domain using:

An example of Butt and Alam's simulations is illustrated in Figure 8. Simulated curves very well reproduce experimental data without any fitting parameter (data extracted from Fig. 12 of Ref. [14]). From a practical point-of-view and in absence of a relatively simple computational solution to implement the Butt and Alam's model, we adopted a pragmatic approach assuming that an

Figure 8 shows that Eq. (1) is able to very well reproduce data. Of course, fitting coefficients A and B must be carefully evaluated for each device considered for the simulation from experimental measurements (heavy ion irradiation) or complementary numerical simulation using the Butt and Alam's complete computational procedure. The next release of TIARA-G4 NVM will integrate such an external dedicated module to confer to the code the capability to simulate a wide variety of NVM devices.

In the particular case of the present study and by chance, Figure 8 is based on data from Cellere et al. who precisely worked on STMicoelectronics FG arrays. It has been found that device T3 in Ref. [16] is technologically very close to our circuit, with the same thicknesses for the different layers composing both the FEOL and BEOL stacks. In order to consider values given by Eq. (1) to our memory devices, we introduced a scaling factor coefficient to take into account the difference in the dimensions of the floating gate polysilicon electrodes between devices considered in Fig. 8 and the present memory cell architecture (simple ratio of the volumes). Without any other calibration, we use in the following Eq. (1) to directly derive the threshold voltage shift resulting from a single

ionizing particle of LET striking the FG produces a Number of Electron Loss given by the following analytical function:

An example of Butt and Alam's simulations is illustrated in Figure 8. Simulated curves very well reproduce experimental data without any fitting parameter (data extracted from Fig. 12 of Ref. [14]). From a practical point-of-view and in absence of a relatively simple computational solution to implement the Butt and Alam's model, we adopted a pragmatic approach assuming that an ionizing particle of LET striking the FG produces a Number of Electron Loss given by the following analytical function:

$$NEL = A \times LET^2 + B \times LET \tag{1}$$

´ D = *<sup>T</sup>*

0 20 40 60

Linear Energy Transfer, LET [MeV-cm2 / mg]

NEL = A×LET2 + B×LET

Eox = -3.5 MV/cm

**5. Results and discussion**

0

1000

2000

Number of Electron Loss, NEL

3000

4000

**5. Results and discussion** 

imposed by the semiconductor manufacturer.

**neutron**

**proton**

*T*

*pp q NEL <sup>V</sup> C* (2)

semiconductor manufacturer.

represented in yellow.

**5.1. Numerical simulations**

of the 238U decay chain) [24].

memory cells (up to 105

**5.1. Numerical simulations** 

dielectrics are not shown, silicon substrate is represented in yellow.

*pp q NEL <sup>V</sup>*

where Cpp is the coupling capacitance between the FG and CG electrodes (see Fig. 2 left).

This last section presents the numerical simulations performed with TIARA-G4 NVM for the 90 nm NOR floating-gate flash memory architecture previously described. In a second part, we report experimental measurements obtained from the direct exposition of a large number of circuits to natural radiation. These two sets of data are finally compared and discussed in the last part of this section. It is important to notice that, in the following, all numerical results concerning the characterization and the simulation of the 90 nm flash circuit have been normalized by a common arbitrary scaling factor for confidentiality reasons imposed by the

> **Reac on vertex**

**Figure 9.** ROOT screenshots of a TIARA-G4 simulation showing several hundred of memory cells and different particle tracks resulting from atmospheric neutrons interaction with circuit materials. All BEOL materials, intra-cell silicon and

Using TIARA-G4 NVM, we performed extensive Monte Carlo simulations on large arrays of

energy incident neutrons above 1 MeV [23]. Other simulations have been also performed using a random generation of alpha particles inside the silicon material for mimicking the presence of 238U contamination at ppb-level (we considered in this case the eight alpha-particle emitters

**Si**

where Cpp is the coupling capacitance between the FG and CG electrodes (see Fig. 2 left).

Experiment (Cellere et al. [16]) Simulation (Butt & Alam [14]) Fit on experiment [Eq. (1)]

*<sup>C</sup>* (2)

http://dx.doi.org/10.5772/57220

379

Figure 8. Number of electron loss (NEL) as a function of the particle LET for device T3 of Ref. [16] under an oxide electric field of 3.5 MV/cm. Simulation results from Butt & Alam (Ref. [14]) are also reported. The full line corresponds to the fitting function (1) on experi-mental data.

Computational Modeling and Monte Carlo Simulation of Soft Errors in Flash Memories

This last section presents the numerical simulations performed with TIARA-G4 NVM for the 90 nm NOR floating-gate flash memory architecture previously described. In a second part, we report experimental measurements obtained from the direct exposition of a large number of circuits to natural radiation. These two sets of data are finally compared and discussed in the last part of this section. It is important to notice that, in the following, all numerical results concerning the characterization and the simulation of the 90 nm flash circuit have been normalized by a common arbitrary scaling factor for confidentiality reasons

Figure 9. ROOT screenshots of a TIARA-G4 simulation showing several hundred of memory cells and different particle tracks resulting from atmospheric neutrons interaction with circuit materials. All BEOL materials, intra-cell silicon and dielectrics are not shown, silicon substrate is

Using TIARA-G4 NVM, we performed extensive Monte Carlo simulations on large arrays of memory cells (up to 105 cells) considering the JEDEC atmospheric neutron source for high-energy incident neutrons above 1 MeV [23]. Other simulations have been also performed using a random generation of alpha particles inside the silicon material for mimicking the presence of 238U

contamination at ppb-level (we considered in this case the eight alpha-particle emitters of the 238U decay chain) [24].

cells) considering the JEDEC atmospheric neutron source for high-

where Cpp is the coupling capacitance between the FG and CG electrodes (see Fig. 2 left).

Figure 8 shows that Eq. (1) is able to very well reproduce data. Of course, fitting coefficients A and B must be carefully evaluated for each device considered for the simulation from experimental measurements (heavy ion irradiation) or complementary numerical simulation using the Butt and Alam's complete computational procedure. The next release of TIARA-G4 NVM will integrate such an external dedicated module to confer to the code the capability to simulate a wide variety of NVM devices. *T pp q NEL <sup>V</sup> C* (2)

Figure 8. Number of electron loss (NEL) as a function of the particle LET for device T3 of Ref. [16] under an oxide electric field of 3.5 MV/cm. Simulation results from Butt & Alam (Ref. [14]) are also reported. The full line corresponds to the fitting function (1) on experi-mental data. **Figure 8.** Number of electron loss (NEL) as a function of the particle LET for device T3 of Ref. [16] under an oxide elec‐ tric field of 3.5 MV/cm. Simulation results from Butt & Alam (Ref. [14]) are also reported. The full line corresponds to the fitting function (1) on experi-mental data.

**5. Results and discussion**  This last section presents the numerical simulations performed with TIARA-G4 NVM for the 90 nm NOR floating-gate flash memory architecture previously described. In a second part, we report experimental measurements obtained from the direct exposition of a large number of circuits to natural radiation. These two sets of data are finally compared and discussed in the last part of this section. It is important to notice that, in the following, all numerical results concerning the characterization and the simulation of the 90 nm flash circuit have been normalized by a common arbitrary scaling factor for confidentiality reasons imposed by the semiconductor manufacturer. **neutron** In the particular case of the present study and by chance, Figure 8 is based on data from Cellere et al. who precisely worked on STMicoelectronics FG arrays. It has been found that device T3 in Ref. [16] is technologically very close to our circuit, with the same thicknesses for the different layers composing both the FEOL and BEOL stacks. In order to consider values given by Eq. (1) to our memory devices, we introduced a scaling factor coefficient to take into account the difference in the dimensions of the floating gate polysilicon electrodes between devices considered in Fig. 8 and the present memory cell architecture (simple ratio of the volumes). Without any other calibration, we use in the following Eq. (1) to directly derive the threshold voltage shift resulting from a single particle strike in the FG domain using:

**proton**

**Reac on vertex**

**Si**

represented in yellow.

**5.1. Numerical simulations** 

Figure 9. ROOT screenshots of a TIARA-G4 simulation showing several hundred of memory cells and different particle tracks resulting from atmospheric neutrons interaction with circuit materials. All BEOL materials, intra-cell silicon and dielectrics are not shown, silicon substrate is

Using TIARA-G4 NVM, we performed extensive Monte Carlo simulations on large arrays of memory cells (up to 105 cells) considering the JEDEC atmospheric neutron source for high-energy incident neutrons above 1 MeV [23]. Other simulations have been also performed using a random generation of alpha particles inside the silicon material for mimicking the presence of 238U

contamination at ppb-level (we considered in this case the eight alpha-particle emitters of the 238U decay chain) [24].

Eox = -3.5 MV/cm Computational Modeling and Monte Carlo Simulation of Soft Errors in Flash Memories http://dx.doi.org/10.5772/57220 379

$$
\Delta V\_T = \frac{q \times NEL}{C\_{pp}} \tag{2}
$$

where Cpp is the coupling capacitance between the FG and CG electrodes (see Fig. 2 left). 1000 Number of Electron Loss, NEL Experiment (Cellere et al. [16]) Simulation (Butt & Alam [14])

Fit on experiment [Eq. (1)]

where Cpp is the coupling capacitance between the FG and CG electrodes (see Fig. 2 left).

#### **5. Results and discussion** 0 0 20 40 60

2000

3000

4000

imposed by the semiconductor manufacturer.

NEL = A×LET2 + B×LET

Linear Energy Transfer, LET [MeV-cm2 / mg]

*T*

*pp q NEL <sup>V</sup> C* (2)

An example of Butt and Alam's simulations is illustrated in Figure 8. Simulated curves very well reproduce experimental data without any fitting parameter (data extracted from Fig. 12 of Ref. [14]). From a practical point-of-view and in absence of a relatively simple computational solution to implement the Butt and Alam's model, we adopted a pragmatic approach assuming that an ionizing particle of LET striking the FG produces a Number of Electron Loss given by

Figure 8 shows that Eq. (1) is able to very well reproduce data. Of course, fitting coefficients A and B must be carefully evaluated for each device considered for the simulation from experimental measurements (heavy ion irradiation) or complementary numerical simulation using the Butt and Alam's complete computational procedure. The next release of TIARA-G4 NVM will integrate such an external dedicated module to confer to the code the capability to

NEL = A×LET2 + B×LET

Eox = -3.5 MV/cm

0 20 40 60

Linear Energy Transfer, LET [MeV-cm2 / mg]

**Figure 8.** Number of electron loss (NEL) as a function of the particle LET for device T3 of Ref. [16] under an oxide elec‐ tric field of 3.5 MV/cm. Simulation results from Butt & Alam (Ref. [14]) are also reported. The full line corresponds to

In the particular case of the present study and by chance, Figure 8 is based on data from Cellere et al. who precisely worked on STMicoelectronics FG arrays. It has been found that device T3 in Ref. [16] is technologically very close to our circuit, with the same thicknesses for the different layers composing both the FEOL and BEOL stacks. In order to consider values given by Eq. (1) to our memory devices, we introduced a scaling factor coefficient to take into account the difference in the dimensions of the floating gate polysilicon electrodes between devices considered in Fig. 8 and the present memory cell architecture (simple ratio of the volumes). Without any other calibration, we use in the following Eq. (1) to directly derive the threshold

<sup>2</sup> *NEL A LET B LET* =´ +´ (1)

where Cpp is the coupling capacitance between the FG and CG electrodes (see Fig. 2 left).

Experiment (Cellere et al. [16]) Simulation (Butt & Alam [14]) Fit on experiment [Eq. (1)]

> **Reac on vertex**

**Si**

Simulation results from Butt & Alam (Ref. [14]) are also reported. The full line corresponds to the fitting function (1) on experi-mental data.

Figure 9. ROOT screenshots of a TIARA-G4 simulation showing several hundred of memory cells and different particle tracks resulting from atmospheric neutrons interaction with circuit materials. All BEOL materials, intra-cell silicon and dielectrics are not shown, silicon substrate is

Using TIARA-G4 NVM, we performed extensive Monte Carlo simulations on large arrays of memory cells (up to 105 cells) considering the JEDEC atmospheric neutron source for high-energy incident neutrons above 1 MeV [23]. Other simulations have been also performed using a random generation of alpha particles inside the silicon material for mimicking the presence of 238U

contamination at ppb-level (we considered in this case the eight alpha-particle emitters of the 238U decay chain) [24].

the following analytical function:

378 Computational and Numerical Simulations

simulate a wide variety of NVM devices.

*T*

*pp q NEL <sup>V</sup> C* (2)

0

1000

2000

Number of Electron Loss, NEL

the fitting function (1) on experi-mental data.

3000

4000

**5. Results and discussion** 

represented in yellow.

**5.1. Numerical simulations** 

imposed by the semiconductor manufacturer.

**neutron**

voltage shift resulting from a single particle strike in the FG domain using:

**proton**

This last section presents the numerical simulations performed with TIARA-G4 NVM for the 90 nm NOR floating-gate flash memory architecture previously described. In a second part, we report experimental measurements obtained from the direct exposition of a large number of circuits to natural radiation. These two sets of data are finally compared and discussed in the last part of this section. It is important to notice that, in the following, all numerical results concerning the characterization and the simulation of the 90 nm flash circuit have been normalized by a common arbitrary scaling factor for confidentiality reasons imposed by the semiconductor manufacturer. Figure 8. Number of electron loss (NEL) as a function of the particle LET for device T3 of Ref. [16] under an oxide electric field of 3.5 MV/cm. Simulation results from Butt & Alam (Ref. [14]) are also reported. The full line corresponds to the fitting function (1) on experi-mental data. **5. Results and discussion**  This last section presents the numerical simulations performed with TIARA-G4 NVM for the 90 nm NOR floating-gate flash memory architecture previously described. In a second part, we report experimental measurements obtained from the direct exposition of a large number of circuits to natural radiation. These two sets of data are finally compared and discussed in the last part of this section. It is important to notice that, in the following, all numerical results concerning the characterization and the simulation of the 90 nm flash circuit have been normalized by a common arbitrary scaling factor for confidentiality reasons

Figure 9. ROOT screenshots of a TIARA-G4 simulation showing several hundred of memory cells and different particle tracks resulting from atmospheric neutrons interaction with circuit materials. All BEOL materials, intra-cell silicon and dielectrics are not shown, silicon substrate is represented in yellow. **Figure 9.** ROOT screenshots of a TIARA-G4 simulation showing several hundred of memory cells and different particle tracks resulting from atmospheric neutrons interaction with circuit materials. All BEOL materials, intra-cell silicon and dielectrics are not shown, silicon substrate is represented in yellow.

#### This last section presents the numerical simulations performed with TIARA-G4 NVM for the 90 nm NOR floating-gate flash memory architecture previously described. In a second part, we report experimental measurements obtained from the direct **5.1. Numerical simulations**

**5.1. Numerical simulations** 

exposition of a large number of circuits to natural radiation. These two sets of data are finally compared and discussed in the last part of this section. It is important to notice that, in the following, all numerical results concerning the characterization and the simulation of the 90 nm flash circuit have been normalized by a common arbitrary scaling factor for confidentiality reasons considering the JEDEC atmospheric neutron source for high-energy incident neutrons above 1 MeV [23]. Other simulations have been also performed using a random generation of alpha particles inside the silicon material for mimicking the presence of 238U contamination at ppb-level (we considered in this case the eight alpha-particle emitters of the 238U decay chain) [24]. Using TIARA-G4 NVM, we performed extensive Monte Carlo simulations on large arrays of memory cells (up to 105 cells) considering the JEDEC atmospheric neutron source for highenergy incident neutrons above 1 MeV [23]. Other simulations have been also performed using a random generation of alpha particles inside the silicon material for mimicking the presence of 238U contamination at ppb-level (we considered in this case the eight alpha-particle emitters of the 238U decay chain) [24].

Using TIARA-G4 NVM, we performed extensive Monte Carlo simulations on large arrays of memory cells (up to 105 cells)

Two simulation screenshots are shown in Figure 7(c) and (d) in the case of a reduced matrix of 30×30 cells (considered for a better view). A larger simulation view is shown in Figure 9 for several hundred cells. They illustrate the interaction of atmospheric neutrons with the circuit materials and the way in which the neutron-induced secondary particles can impact the memory cells (direct strikes on the FG electrodes). A large part of the events are induced by secondary particles generated in the proximity of the FEOL/BEOL interface and predominantly by protons and silicon recoil nuclei. The BEOL stack is found to contribute marginally (< 2%) to the total SER in spite of the presence of several layers and vias of high density materials (W, Cu, Ta).

In complement to Figure 10, Figure 11 shows the threshold voltage shift distribution for all the cells of the simulated array. The peak at ΔV<sup>T</sup> = 0 V indicates that the great majority of the cells have not been impacted during the simulation run. For ΔVT > 0 V, the distribution is decreasing when ΔVT increases. This directly reflects (cf. Eqs. (1) and (2)) the LET distribution of the secondary particles (i.e. neutron byproducts) striking the floating gates: the lightest particles

Computational Modeling and Monte Carlo Simulation of Soft Errors in Flash Memories

number of events characterized by a small or moderate ΔVT shift (<1 V); on the contrary, particles with the highest LET values, much less numerous, induce the largest ΔV<sup>T</sup> (> 3V). From the number of cells verifying VT < 5.7 V after irradiation, the neutron-SER at sea-level has been numerically evaluated to 7.7 (in arbitrary unit taking into account the common arbitrary scaling factor for confidentiality reasons). This value is expressed for the reference location (NYC).

For the alpha-SER, a value of 0.12 (a.u.) has been obtained considering a concentration of 0.2 ppb of 238U uniformly distributed in the volume of circuit materials at both FEOL and BEOL levels. This concentration was directly deduced from experimental emissivity measurements

In parallel to this work of modeling and numerical simulation, previously described, we launched an experimental verification procedure to estimate the circuit SER from direct measurements. For this, we considered a large collection of NOR floating-gate flash memory circuits fabricated by STMicroelectronics using a 90 nm CMOS process. Circuits have been

/mg) induce a large

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381

(protons, alphas) with low LET values (typically below 1.5 MeV.cm<sup>2</sup>

**Figure 11.** Distributions of ΔVT values extracted from data of Fig. 10.

(see below).

**5.2. Experimental characterization and results**

directly operated and characterized at wafer-level.

**Figure 10.** Distributions of VT values computed by TIARA-G4 NVM for a population of 100,000 memory cells before and after irradiation with atmospheric neutrons.

Figure 10 shows the simulated VT distributions for 105 cells before and after irradiation. The initial distribution corresponds to a Gaussian distribution with the mean and standard deviation values calibrated on experimental data (see 5.2, Fig. 13). The final distribution is the result of 109 incident JEDEC neutrons on the cell matrix, which corresponds to 50×106 h (i.e. more than 5700 years!) under natural atmospheric radiation at New-York City (NYC), the reference location defined by a high energy neutron flux of 20 n/cm2 /h (neutron energies above 1 MeV). One can observe the emergence of a typical neutron-induced tail on a large domain of VT values below 7 V. This tail indicates that the VT value has sufficiently decreased for a certain number of cells to appear outside the Gaussian distribution. Among them, some cells have shifted below the sense value fixed at 5.7 V: their state has thus changed from a logical point-of-view (0 → 1 transition) and their number must be taken into account for the evaluation of the neutron-SER. For the other cells of the distribution tail, ΔVT values are not sufficient to decrease their VT below 5.7 V but large enough to shift the cells outside the initial curve.

**Figure 11.** Distributions of ΔVT values extracted from data of Fig. 10.

Two simulation screenshots are shown in Figure 7(c) and (d) in the case of a reduced matrix of 30×30 cells (considered for a better view). A larger simulation view is shown in Figure 9 for several hundred cells. They illustrate the interaction of atmospheric neutrons with the circuit materials and the way in which the neutron-induced secondary particles can impact the memory cells (direct strikes on the FG electrodes). A large part of the events are induced by secondary particles generated in the proximity of the FEOL/BEOL interface and predominantly by protons and silicon recoil nuclei. The BEOL stack is found to contribute marginally (< 2%) to the total SER in spite of the presence of several layers and vias of high density materials (W,

**Figure 10.** Distributions of VT values computed by TIARA-G4 NVM for a population of 100,000 memory cells before

initial distribution corresponds to a Gaussian distribution with the mean and standard deviation values calibrated on experimental data (see 5.2, Fig. 13). The final distribution is the

more than 5700 years!) under natural atmospheric radiation at New-York City (NYC), the

1 MeV). One can observe the emergence of a typical neutron-induced tail on a large domain of VT values below 7 V. This tail indicates that the VT value has sufficiently decreased for a certain number of cells to appear outside the Gaussian distribution. Among them, some cells have shifted below the sense value fixed at 5.7 V: their state has thus changed from a logical point-of-view (0 → 1 transition) and their number must be taken into account for the evaluation of the neutron-SER. For the other cells of the distribution tail, ΔVT values are not sufficient to decrease their VT below 5.7 V but large enough to shift the cells outside the initial curve.

incident JEDEC neutrons on the cell matrix, which corresponds to 50×106

cells before and after irradiation. The

/h (neutron energies above

h (i.e.

Cu, Ta).

380 Computational and Numerical Simulations

and after irradiation with atmospheric neutrons.

result of 109

Figure 10 shows the simulated VT distributions for 105

reference location defined by a high energy neutron flux of 20 n/cm2

In complement to Figure 10, Figure 11 shows the threshold voltage shift distribution for all the cells of the simulated array. The peak at ΔV<sup>T</sup> = 0 V indicates that the great majority of the cells have not been impacted during the simulation run. For ΔVT > 0 V, the distribution is decreasing when ΔVT increases. This directly reflects (cf. Eqs. (1) and (2)) the LET distribution of the secondary particles (i.e. neutron byproducts) striking the floating gates: the lightest particles (protons, alphas) with low LET values (typically below 1.5 MeV.cm<sup>2</sup> /mg) induce a large number of events characterized by a small or moderate ΔVT shift (<1 V); on the contrary, particles with the highest LET values, much less numerous, induce the largest ΔV<sup>T</sup> (> 3V). From the number of cells verifying VT < 5.7 V after irradiation, the neutron-SER at sea-level has been numerically evaluated to 7.7 (in arbitrary unit taking into account the common arbitrary scaling factor for confidentiality reasons). This value is expressed for the reference location (NYC).

For the alpha-SER, a value of 0.12 (a.u.) has been obtained considering a concentration of 0.2 ppb of 238U uniformly distributed in the volume of circuit materials at both FEOL and BEOL levels. This concentration was directly deduced from experimental emissivity measurements (see below).

### **5.2. Experimental characterization and results**

In parallel to this work of modeling and numerical simulation, previously described, we launched an experimental verification procedure to estimate the circuit SER from direct measurements. For this, we considered a large collection of NOR floating-gate flash memory circuits fabricated by STMicroelectronics using a 90 nm CMOS process. Circuits have been directly operated and characterized at wafer-level.

**Figure 12.** Layout (left) and die (right) of the ANNA test chip (area 9.230×7.044mm²) fabricated by STMicroelectronics in CMOS 90 nm technology. The memory array is segmented into 32 blocks of 4 Mbits or 128 sectors of 1 Mbits (total capacity of 128 Mbits per chip).

The test chip, named "macrocell ANNA" and shown in Figure 12, is a 128 Mbit array of memory cells organized in 1 Mbit sectors, 4 Mbit blocks and 16 Mbit quarters without ECC. Several tens of macrocells are available per test wafer (200 mm wafers); more than 50 Gbits (~20 wafers) were used and fully characterized for the present experiment.

The test began by an initial wafer-level characterization at ST-Rousset (near Marseille) of all the circuits using a high performance tester (Verigy® V93000 platform). The test platform uses high precision voltage sources and parameter analyzers calibrated before each measurement campaign: the accuracy on VT extraction is guaranteed to be less than 10 mV. Memory arrays have been written (all "0" pattern) and then read several times, allowing the compilation of a reference threshold voltage (VT) mapping for all the test chips, cell per cell and wafer per wafer. The corresponding numerical data have been stored on a hard disk bay. During this initial characterization, all the wafers were also submitted to a 24h bake at 250°C followed by a new VT characterization in order to identify (and thus to eliminate) all the test chips exhibiting electrical instabilities and/or abnormal FG charge loss. Figure 13 shows a typical VT distribu‐ tion, sharply centered around 7.8 V for a population of memory cells corresponding to all functional test chips for a series of five wafers (same technological lot). The reproducibility (i.e. repeatability) of such an electrical characterization has been attested by the fact that repeated measurements on the same wafer show exactly the same VT distribution within measurement margins (< 10 mV), cell per cell.

**0 0.0002 0.0004 0.0006 0.0008 0.001 0.0012 0.0014 0.0016 0.0018 0.002**

"0" pattern) related to a series of 5 wafers.

**Emissivity (**a**/cm²/h)**

**0 2 4 6 8 10 12 14 16 18 20 22 24**

**Time (h)**

**Emissivity Sigma**

**0**

**0 1 2 3 4 5 6 7 8 9 10**

**Energy (MeV)**

**1**

**2**

**C ounts**

**Figure 13.** Initial distribution of the measured threshold voltage VT values for all the programmed FG memory cells (all

**Figure 14.** Alpha-particle emissivity characterization of 90 nm flash memory wafers using a XIA UltraLo-1800 alphaparticle counter. Left: emissivity and measurement error sigma as a function of measurement duration. Right: energy

After the initial characterization, approximately one half of the total number of wafers was stored in Rousset and the second half was delivered to an altitude test site by express mail and exposed to natural radiation. Figure 15 shows the flowchart of this test method that illustrates the sequencing of the different characterization and wafer transportation steps. Two different radiation environments have thus been considered: the first one at sea-level in Rousset for reference and the second one in altitude on the ASTEP platform [26]. The two sites are characterized by a relative atmospheric neutron flux of 1.04 and 6.02 with respect to New-York City, respectively [27-28]. After a period of exposition of several months, the wafers stored on ASTEP (see Figure 16) have been delivered to ST-Rousset for complete electrical characteri‐ zation. Those remained in Rousset were also measured in the same time. The complete characterization loop Rousset → ASTEP → Rousset was repeated 3 times for the present work.

distribution of the detected alpha particles emitted from the surface of the wafers (fully-processed wafers).

**3**

**4**

Computational Modeling and Monte Carlo Simulation of Soft Errors in Flash Memories

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383

In addition to this initial electrical characterization, we also performed alpha-emissivity measurements at wafer-level using a XIA UltraLo-1800 alpha-particle counter. Figure 14 shows the results of this characterization, in terms of emissivity and measurement error (Fig. 14 left) and of energy distribution (Fig. 14 right) of the emitted alpha particles from the fully processed wafers. An emissivity level of 0.0013 α/cm<sup>2</sup> /h was measured, which corresponds to a concen‐ tration of 0.2 ppb of 238U uniformly distributed in the volume of circuit materials at both FEOL and BEOL levels. Such a correspondence has been estimated using a reverse α-particle emissivity analytical modeling recently developed [25].

Computational Modeling and Monte Carlo Simulation of Soft Errors in Flash Memories http://dx.doi.org/10.5772/57220 383

**QUARTER 16 Mbit**

**Figure 12.** Layout (left) and die (right) of the ANNA test chip (area 9.230×7.044mm²) fabricated by STMicroelectronics in CMOS 90 nm technology. The memory array is segmented into 32 blocks of 4 Mbits or 128 sectors of 1 Mbits (total

The test chip, named "macrocell ANNA" and shown in Figure 12, is a 128 Mbit array of memory cells organized in 1 Mbit sectors, 4 Mbit blocks and 16 Mbit quarters without ECC. Several tens of macrocells are available per test wafer (200 mm wafers); more than 50 Gbits

The test began by an initial wafer-level characterization at ST-Rousset (near Marseille) of all the circuits using a high performance tester (Verigy® V93000 platform). The test platform uses high precision voltage sources and parameter analyzers calibrated before each measurement campaign: the accuracy on VT extraction is guaranteed to be less than 10 mV. Memory arrays have been written (all "0" pattern) and then read several times, allowing the compilation of a reference threshold voltage (VT) mapping for all the test chips, cell per cell and wafer per wafer. The corresponding numerical data have been stored on a hard disk bay. During this initial characterization, all the wafers were also submitted to a 24h bake at 250°C followed by a new VT characterization in order to identify (and thus to eliminate) all the test chips exhibiting electrical instabilities and/or abnormal FG charge loss. Figure 13 shows a typical VT distribu‐ tion, sharply centered around 7.8 V for a population of memory cells corresponding to all functional test chips for a series of five wafers (same technological lot). The reproducibility (i.e. repeatability) of such an electrical characterization has been attested by the fact that repeated measurements on the same wafer show exactly the same VT distribution within measurement

In addition to this initial electrical characterization, we also performed alpha-emissivity measurements at wafer-level using a XIA UltraLo-1800 alpha-particle counter. Figure 14 shows the results of this characterization, in terms of emissivity and measurement error (Fig. 14 left) and of energy distribution (Fig. 14 right) of the emitted alpha particles from the fully processed

tration of 0.2 ppb of 238U uniformly distributed in the volume of circuit materials at both FEOL and BEOL levels. Such a correspondence has been estimated using a reverse α-particle

/h was measured, which corresponds to a concen‐

(~20 wafers) were used and fully characterized for the present experiment.

capacity of 128 Mbits per chip).

382 Computational and Numerical Simulations

margins (< 10 mV), cell per cell.

wafers. An emissivity level of 0.0013 α/cm<sup>2</sup>

emissivity analytical modeling recently developed [25].

**BLOCK 4 Mbit**

> **SECTOR 1Mbit**

**Figure 13.** Initial distribution of the measured threshold voltage VT values for all the programmed FG memory cells (all "0" pattern) related to a series of 5 wafers.

**Figure 14.** Alpha-particle emissivity characterization of 90 nm flash memory wafers using a XIA UltraLo-1800 alphaparticle counter. Left: emissivity and measurement error sigma as a function of measurement duration. Right: energy distribution of the detected alpha particles emitted from the surface of the wafers (fully-processed wafers).

After the initial characterization, approximately one half of the total number of wafers was stored in Rousset and the second half was delivered to an altitude test site by express mail and exposed to natural radiation. Figure 15 shows the flowchart of this test method that illustrates the sequencing of the different characterization and wafer transportation steps. Two different radiation environments have thus been considered: the first one at sea-level in Rousset for reference and the second one in altitude on the ASTEP platform [26]. The two sites are characterized by a relative atmospheric neutron flux of 1.04 and 6.02 with respect to New-York City, respectively [27-28]. After a period of exposition of several months, the wafers stored on ASTEP (see Figure 16) have been delivered to ST-Rousset for complete electrical characteri‐ zation. Those remained in Rousset were also measured in the same time. The complete characterization loop Rousset → ASTEP → Rousset was repeated 3 times for the present work. **Emissivity (/cm²/h)**

**0 0.0002 0.0004 0.0006 0.0008 0.001 0.0012 0.0014 0.0016 0.0018 0.002**

emissivity analytical modeling recently developed [25].

from the surface of the wafers (fully-processed wafers).

**0 2 4 6 8 10 12 14 16 18 20 22 24**

**Time (h)**

**Emissivity Sigma**

the volume of circuit materials at both FEOL and BEOL levels. Such a correspondence has been estimated using a reverse α-particle

emissivity and measurement error sigma as a function of measurement duration. Right: energy distribution of the detected alpha particles emitted

**0 1 2 3 4 5 6 7 8 9 10**

**Energy (MeV)**

Figure 17 shows the results for the two series of wafers exposed in Rousset and on the ASTEP Platform. Three reading operations have been performed on the wafers stored in Rousset, respectively after 5, 12 and 18 months of exposition. Similarly, two reading operations have been performed on the ASTEP wafers, after 5 and 12 months of natural irradiation in altitude.

For wafers exposed at sea-level, one memory cell compared to more than several tens of Gbits has been detected with a VT value changing at t0 + 12 months and becoming inferior to the

the threshold voltage shifted from 8.0 to 4.5 V. Likewise, 2 and 3 shifted-VT cells have been detected on the ASTEP wafers, respectively after 5 months and one year of exposition.

Measured VT values for these flipped cells are also reported in Figure 17.

 First reading

**ASTEP (alt. 2552 m)**

VT (V) 4.4 5.4

No detected

cell

first and the second wafer readings.

states and detected during the first and the second wafer readings.

exposed to natural radiation on the ASTEP platform.

of programmed memory cells exposed to natural radiation on the ASTEP platform.

**Figure 18.** Comparison between the two distributions of VT values measured at t0 and at t0 +12 months for population

in Figure 17.

2

4

0

2

Number of cell upsets

4

**Rousset (sea-level)**

REF = 5.7 V) delimiting the "0" and "1" logical states. For this memory cell,

Computational Modeling and Monte Carlo Simulation of Soft Errors in Flash Memories

Second reading

0 2 4 6 8 10 12 14 16 18 20

Experiment duration (months)

**Figure 17.** Number of memory cells with shifted VT below the reference value (5.7 V) delimiting the "0" and "1" logical

VT (V) 3.5 4.8 5.0

VT (V) 4.5

Figure 16.Global view of one of the ASTEP experimental room showing, in the foreground, six wafers of flash memories stored on the ground during their exposition to natural radiation on the ASTEP platform and, in the background, a real-time test setup based on 40nm SRAM circuits [9].

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385

Figure 17 shows the results for the two series of wafers exposed in Rousset and on the ASTEP Platform. Three reading operations have been performed on the wafers stored in Rousset, respectively after 5, 12 and 18 months of exposition. Similarly, two reading

For wafers exposed at sea-level, one memory cell compared to more than several tens of Gbits has been detected with a VT value changing at t0 + 12 months and becoming inferior to the reference value (VTREF = 5.7 V) delimiting the "0" and "1" logical states. For this memory cell, the threshold voltage shifted from 8.0 to 4.5 V. Likewise, 2 and 3 shifted-VT cells have been detected on the ASTEP wafers, respectively after 5 months and one year of exposition. Measured VT values for these flipped cells are also reported

Figure 17.Number of memory cells with shifted VT below the reference value (5.7 V) delimiting the "0" and "1" logical states and detected during the

Figure 18.Comparison between the two distributions of VT values measured at t0 and at t0 +12 months for population of programmed memory cells

operations have been performed on the ASTEP wafers, after 5 and 12 months of natural irradiation in altitude.

 Third reading

No detected

**N.A.**

cell

*Altitude SEE Test European Platform*

reference value (VT

**0**

**1**

**2**

**Counts**

**3**

**4**

After the initial characterization, approximately one half of the total number of wafers was stored in Rousset and the second half

Figure 15.Flowchart of the multi-site characterization technique developed to evaluate the soft error rate of flash memories written and read at wafer-level using a Verigy® V93000 platform. **Figure 15.** Flowchart of the multi-site characterization technique developed to evaluate the soft error rate of flash memories written and read at wafer-level using a Verigy® V93000 platform.

**Figure 16.** Global view of one of the ASTEP experimental room showing, in the foreground, six wafers of flash memo‐ ries stored on the ground during their exposition to natural radiation on the ASTEP platform and, in the background, a real-time test setup based on 40nm SRAM circuits [9].

*Altitude SEE Test European Platform*

Figure 17 shows the results for the two series of wafers exposed in Rousset and on the ASTEP Platform. Three reading operations have been performed on the wafers stored in Rousset, respectively after 5, 12 and 18 months of exposition. Similarly, two reading operations have been performed on the ASTEP wafers, after 5 and 12 months of natural irradiation in altitude. Figure 16.Global view of one of the ASTEP experimental room showing, in the foreground, six wafers of flash memories stored on the ground during their exposition to natural radiation on the ASTEP platform and, in the background, a real-time test setup based on 40nm SRAM circuits [9]. Figure 17 shows the results for the two series of wafers exposed in Rousset and on the ASTEP Platform. Three reading operations

For wafers exposed at sea-level, one memory cell compared to more than several tens of Gbits has been detected with a VT value changing at t0 + 12 months and becoming inferior to the reference value (VT REF = 5.7 V) delimiting the "0" and "1" logical states. For this memory cell, the threshold voltage shifted from 8.0 to 4.5 V. Likewise, 2 and 3 shifted-VT cells have been detected on the ASTEP wafers, respectively after 5 months and one year of exposition. Measured VT values for these flipped cells are also reported in Figure 17. have been performed on the wafers stored in Rousset, respectively after 5, 12 and 18 months of exposition. Similarly, two reading operations have been performed on the ASTEP wafers, after 5 and 12 months of natural irradiation in altitude. For wafers exposed at sea-level, one memory cell compared to more than several tens of Gbits has been detected with a VT value changing at t0 + 12 months and becoming inferior to the reference value (VTREF = 5.7 V) delimiting the "0" and "1" logical states. For this memory cell, the threshold voltage shifted from 8.0 to 4.5 V. Likewise, 2 and 3 shifted-VT cells have been detected on the ASTEP wafers, respectively after 5 months and one year of exposition. Measured VT values for these flipped cells are also reported

in Figure 17.

*Altitude SEE Test European Platform*

the volume of circuit materials at both FEOL and BEOL levels. Such a correspondence has been estimated using a reverse α-particle

Figure 14.Alpha-particle emissivity characterization of 90 nm flash memory wafers using a XIA UltraLo-1800 alpha-particle counter. Left: emissivity and measurement error sigma as a function of measurement duration. Right: energy distribution of the detected alpha particles emitted

> Reference VT mapping for all memory cells

*Verigy (Agilent) 93000 SOC Tester* 

**0 1 2 3 4 5 6 7 8 9 10**

**Energy (MeV)**

VT mapping for all memory cells

Figure 15.Flowchart of the multi-site characterization technique developed to evaluate the soft error rate of flash memories written and read at

After the initial characterization, approximately one half of the total number of wafers was stored in Rousset and the second half was delivered to an altitude test site by express mail and exposed to natural radiation. Figure 15 shows the flowchart of this test method that illustrates the sequencing of the different characterization and wafer transportation steps. Two different radiation environments have thus been considered: the first one at sea-level in Rousset for reference and the second one in altitude on the ASTEP platform [26]. The two sites are characterized by a relative atmospheric neutron flux of 1.04 and 6.02 with respect to New-York City, respectively [27-28]. After a period of exposition of several months, the wafers stored on ASTEP (see Figure 16) have been delivered to ST-Rousset for complete electrical characterization. Those remained in Rousset were also measured in the same

time. The complete characterization loop Rousset → ASTEP → Rousset was repeated 3 times for the present work.

emissivity analytical modeling recently developed [25].

from the surface of the wafers (fully-processed wafers).

**0 2 4 6 8 10 12 14 16 18 20 22 24**

**Time (h)**

**Emissivity Sigma**

Initial wafer-level characterization (Rousset site) **WRITING/READING** of the memory arrays

> **Exposition** to the natural radiation environments (several months) **ASTEP and sea-level**

*express delivery (1 day)* 

*express delivery (1 day)* 

**Figure 15.** Flowchart of the multi-site characterization technique developed to evaluate the soft error rate of flash

*comparison*

**0**

**1**

**2**

**Counts**

**3**

**4**

**READING** of the memory arrays (Rousset site)

**Detection** of VT-shift

wafer-level using a Verigy® V93000 platform.

memories written and read at wafer-level using a Verigy® V93000 platform.

**New measurement Step+1** 

*express delivery (1 dy)* 

**0 0.0002 0.0004 0.0006 0.0008 0.001 0.0012 0.0014 0.0016 0.0018 0.002**

384 Computational and Numerical Simulations

**Emissivity (/cm²/h)**

**Figure 16.** Global view of one of the ASTEP experimental room showing, in the foreground, six wafers of flash memo‐ ries stored on the ground during their exposition to natural radiation on the ASTEP platform and, in the background, a

real-time test setup based on 40nm SRAM circuits [9].

Figure 17.Number of memory cells with shifted VT below the reference value (5.7 V) delimiting the "0" and "1" logical states and detected during the first and the second wafer readings. **Figure 17.** Number of memory cells with shifted VT below the reference value (5.7 V) delimiting the "0" and "1" logical states and detected during the first and the second wafer readings.

exposed to natural radiation on the ASTEP platform. **Figure 18.** Comparison between the two distributions of VT values measured at t0 and at t0 +12 months for population of programmed memory cells exposed to natural radiation on the ASTEP platform.

Figure 18.Comparison between the two distributions of VT values measured at t0 and at t0 +12 months for population of programmed memory cells

A detailed analysis of the analogic VT bitmaps (not shown) for all these impacted cells shown that these latters correspond to isolated cells (i.e. adjacent cells not impacted) randomly distributed in the FG array and on the exposed wafers. A more detailed investigation on the complete VT distributions shows that several other cells have been potentially impacted during their exposition to natural radiation. Figure 18 shows such a distribution for the whole cell population exposed on ASTEP. At t0 + 12 months, two groups of impacted cells can be distinguished: a first group of 3 cells, labeled A, which corresponds to the 0→1 flipped cells reported in Figure 17 (bottom graph, at t0 + 12), and a second group of 6 cells, labeled B, for which the VT have shifted but not enough to cross the limit of 5.7 V delimiting the two binary states "0" and "1".

A detailed analysis of the analogic VT bitmaps (not shown) for all these impacted cells shown that these latters correspond to isolated cells (i.e. adjacent cells not impacted) randomly distributed in the FG array and on the exposed wafers. A more detailed investigation on the complete VT distributions shows that several other cells have been potentially impacted during their exposition to natural radiation. Figure 18 shows such a distribution for the whole cell population exposed on ASTEP. At t0 + 12 months, two groups of impacted cells can be distinguished: a first group of 3 cells, labeled A, which corresponds to the 0→1 flipped cells reported in Figure 17 (bottom graph, at t0 + 12), and a second group of 6 cells, labeled B, for which the VT have shifted but not

From data of Figure 17 obtained at two different locations, the global soft error rate (SER) and its two components can be determined, as suggested in [29]. The two components are, on one hand, the n-SER taking into account the atmospheric neutrons contribution to the SER and, on the other hand, the so-called α-i-SER accounting for all the internal failure mechanisms in the chips, including the possible alpha-particle emitter contribution. Indeed, several physical intrinsic mechanisms can be invoked to explain the long-term charge loss generally observed in FG devices, in particular different leakage mechanisms through the tunnel oxide or through the ONO interpoly dielectric based on various possible trap/defect assisted tunneling [30]. These latter are not inevitably related to radiation effects but can be also linked to material properties or induced by the technological process or by an electrical stress. This is the reason why the second contribution to the SER is called here α-i-SER and not only α-SER. We thus have a system

Figure 8 shows the results of this SER extraction, considering results of Figure 17, durations and memory capacities related to the different experiments. Global SER values of 9.7 and 28.8 a.u. are obtained for Rousset (sea-level) and ASTEP (altitude) experiments,

These results demonstrate a very limited impact of the atmospheric radiation on the total SER without ECC, typically in the range [10-100] FIT/GBit. With respect to all other internal failure mechanisms, the external natural radiation constraint is found to represent less than one third (27%) of the total SER. Note that all these SER values are found strictly equal to 0 if ECC is activated

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387

Figure 19.Summary of the SER deduced from data of Fig. 4 for sea-level and ASTEP conditions. The two components of the SER are given for normalized New-York City conditions. SER values are in a.u. for confidentiality reasons but the order of magnitude of these values is a few

In this last paragraph, we conclude by comparing these experimental results with predictive values obtained using the TIARA-G4

A good agreement is found for the neutron-SER taking into account all experimental and simulation uncertainties, in the first instance, the relatively weak statistics of the experiment in terms of number of events detected. Indeed, despite the duration of the experiment (18 months) and the huge quantity of data to manipulate (the individual VT evolution of more than 50 Gbits of memory cells has been stored and processed), the statistics of this first experiment remains relatively weak because of the extremely low rate

NVM simulation platform. Figure 20 summarizes this comparison for the different defined SER components.

**Normalized to NYC**

3.2 8.7

where AFRousset = 1.04 and AFASTEP = 6.02 are the neutron flux acceleration factor, as previously reported in II.B.

on the chips, due to the fact that only rare events always corresponding to single cell upsets have been detected.

ASTEP acceleration factor **AF = 6.02**

Computational Modeling and Monte Carlo Simulation of Soft Errors in Flash Memories

enough to cross the limit of 5.7 V delimiting the two binary states "0" and "1".

with two equations and two unknown quantities:

which leads to an estimation of α-i-SER = 3.2 and n-SER = 8.7 a.u.

**ASTEP**

**Figure 19.** Summary of the SER deduced from data of Fig. 4 for sea-level and ASTEP conditions. The two components of the SER are given for normalized New-York City conditions. SER values are in a.u. for confidentiality reasons but the

In this last paragraph, we conclude by comparing these experimental results with predictive values obtained using the TIARA-G4 NVM simulation platform. Figure 20 summarizes this

A good agreement is found for the neutron-SER taking into account all experimental and simulation uncertainties, in the first instance, the relatively weak statistics of the experiment in terms of number of events detected. Indeed, despite the duration of the experiment (18 months) and the huge quantity of data to manipulate (the individual VT evolution of more than 50 Gbits of memory cells has been stored and processed), the statistics of this first experiment remains relatively weak because of the extremely low rate of cell flips in this kind of memory.

For alpha-SER, the discrepancy is flagrant between the two values. This confirms our initial precaution to name the second extracted component of the SER (Fig. 19) α-i-SER instead of classically α-SER because, in the present case of FG devices, this component may be the result of other intrinsic failure mechanisms occurring in parallel inside the chips. From literature [31-33], we can invoke different intrinsic or extrinsic leakage current mechanisms though the dielectric layers present in the floating gate stack (tunnel oxide, ONO, spacers). Intrinsic mechanisms that contribute to charge loss are field-assisted electron emission, thermionic emission and electron detrapping. Extrinsic mechanisms are essentially oxide defects that can form conductive paths through a given dielectric. Whatever the mechanism or eventually the activation of several leakage paths, our results suggest that these electrical processes appear to be dominant in the observed failure rate with respect to the contribution of alpha-particle

internal emission. This point will have to be carefully reevaluated in future works.

**90 nm NOR Flash memory without ECC**

i SER+ n SER= *AFRousset Rousset*

i SER+ n SER= *AFASTEP ASTEP*

*SER* (4)

*SER* (3)

hundreds FIT per GBit.

order of magnitude of these values is a few hundreds FIT per GBit.

0

5

10

15

Soft Error Rate [a.u.]

**5.3. Discussion**

 Rousset **AF = 1.04**

**Sea-level**


20

25

30

**5.3. Discussion** 

comparison for the different defined SER components.

of cell flips in this kind of memory.

From data of Figure 17 obtained at two different locations, the global soft error rate (SER) and its two components can be determined, as suggested in [29]. The two components are, on one hand, the n-SER taking into account the atmospheric neutrons contribution to the SER and, on the other hand, the so-called α-i-SER accounting for all the internal failure mechanisms in the chips, including the possible alpha-particle emitter contribution. Indeed, several physical intrinsic mechanisms can be invoked to explain the long-term charge loss generally observed in FG devices, in particular different leakage mechanisms through the tunnel oxide or through the ONO interpoly dielectric based on various possible trap/defect assisted tunneling [30]. These latter are not inevitably related to radiation effects but can be also linked to material properties or induced by the technological process or by an electrical stress. This is the reason why the second contribution to the SER is called here α-i-SER and not only α-SER. We thus have a system with two equations and two unknown quantities:

$$\mathbf{a} - \mathbf{i} - \mathbf{SER} + AF\_{Rounset}\mathbf{n} - \mathbf{SER} \equiv \mathbf{SER}\_{Rouzset} \tag{3}$$

$$\mathbf{a} - \mathbf{i} - \mathbf{SER} + AF\_{ASTEP}\mathbf{n} - \mathbf{SER} \equiv \mathbf{SER}\_{ASTEP} \tag{4}$$

where AFRousset = 1.04 and AFASTEP = 6.02 are the neutron flux acceleration factor, as previously reported in II.B.

Figure 8 shows the results of this SER extraction, considering results of Figure 17, durations and memory capacities related to the different experiments. Global SER values of 9.7 and 28.8 a.u. are obtained for Rousset (sea-level) and ASTEP (altitude) experiments, which leads to an estimation of α-i-SER = 3.2 and n-SER = 8.7 a.u.

These results demonstrate a very limited impact of the atmospheric radiation on the total SER without ECC, typically in the range [10-100] FIT/GBit. With respect to all other internal failure mechanisms, the external natural radiation constraint is found to represent less than one third (27%) of the total SER. Note that all these SER values are found strictly equal to 0 if ECC is activated on the chips, due to the fact that only rare events always corresponding to single cell upsets have been detected.

where AFRousset = 1.04 and AFASTEP = 6.02 are the neutron flux acceleration factor, as previously reported in II.B.

on the chips, due to the fact that only rare events always corresponding to single cell upsets have been detected.

enough to cross the limit of 5.7 V delimiting the two binary states "0" and "1".

with two equations and two unknown quantities:

i SER+ n SER= *AFRousset Rousset*

i SER+ n SER= *AFASTEP ASTEP*

*SER* (4)

*SER* (3)

A detailed analysis of the analogic VT bitmaps (not shown) for all these impacted cells shown that these latters correspond to isolated cells (i.e. adjacent cells not impacted) randomly distributed in the FG array and on the exposed wafers. A more detailed investigation on the complete VT distributions shows that several other cells have been potentially impacted during their exposition to natural radiation. Figure 18 shows such a distribution for the whole cell population exposed on ASTEP. At t0 + 12 months, two groups of impacted cells can be distinguished: a first group of 3 cells, labeled A, which corresponds to the 0→1 flipped cells reported in Figure 17 (bottom graph, at t0 + 12), and a second group of 6 cells, labeled B, for which the VT have shifted but not

From data of Figure 17 obtained at two different locations, the global soft error rate (SER) and its two components can be determined, as suggested in [29]. The two components are, on one hand, the n-SER taking into account the atmospheric neutrons contribution to the SER and, on the other hand, the so-called α-i-SER accounting for all the internal failure mechanisms in the chips, including the possible alpha-particle emitter contribution. Indeed, several physical intrinsic mechanisms can be invoked to explain the long-term charge loss generally observed in FG devices, in particular different leakage mechanisms through the tunnel oxide or through the ONO interpoly dielectric based on various possible trap/defect assisted tunneling [30]. These latter are not inevitably related to radiation effects but can be also linked to material properties or induced by the technological process or by an electrical stress. This is the reason why the second contribution to the SER is called here α-i-SER and not only α-SER. We thus have a system

Figure 8 shows the results of this SER extraction, considering results of Figure 17, durations and memory capacities related to the different experiments. Global SER values of 9.7 and 28.8 a.u. are obtained for Rousset (sea-level) and ASTEP (altitude) experiments,

These results demonstrate a very limited impact of the atmospheric radiation on the total SER without ECC, typically in the range

which leads to an estimation of α-i-SER = 3.2 and n-SER = 8.7 a.u.

Figure 19.Summary of the SER deduced from data of Fig. 4 for sea-level and ASTEP conditions. The two components of the SER are given for normalized New-York City conditions. SER values are in a.u. for confidentiality reasons but the order of magnitude of these values is a few hundreds FIT per GBit. **Figure 19.** Summary of the SER deduced from data of Fig. 4 for sea-level and ASTEP conditions. The two components of the SER are given for normalized New-York City conditions. SER values are in a.u. for confidentiality reasons but the order of magnitude of these values is a few hundreds FIT per GBit.

### **5.3. Discussion**

**5.3. Discussion** 

A detailed analysis of the analogic VT bitmaps (not shown) for all these impacted cells shown that these latters correspond to isolated cells (i.e. adjacent cells not impacted) randomly distributed in the FG array and on the exposed wafers. A more detailed investigation on the complete VT distributions shows that several other cells have been potentially impacted during their exposition to natural radiation. Figure 18 shows such a distribution for the whole cell population exposed on ASTEP. At t0 + 12 months, two groups of impacted cells can be distinguished: a first group of 3 cells, labeled A, which corresponds to the 0→1 flipped cells reported in Figure 17 (bottom graph, at t0 + 12), and a second group of 6 cells, labeled B, for which the VT have shifted but not enough to cross the limit of 5.7 V delimiting the two binary

From data of Figure 17 obtained at two different locations, the global soft error rate (SER) and its two components can be determined, as suggested in [29]. The two components are, on one hand, the n-SER taking into account the atmospheric neutrons contribution to the SER and, on the other hand, the so-called α-i-SER accounting for all the internal failure mechanisms in the chips, including the possible alpha-particle emitter contribution. Indeed, several physical intrinsic mechanisms can be invoked to explain the long-term charge loss generally observed in FG devices, in particular different leakage mechanisms through the tunnel oxide or through the ONO interpoly dielectric based on various possible trap/defect assisted tunneling [30]. These latter are not inevitably related to radiation effects but can be also linked to material properties or induced by the technological process or by an electrical stress. This is the reason why the second contribution to the SER is called here α-i-SER and not only α-SER. We thus

where AFRousset = 1.04 and AFASTEP = 6.02 are the neutron flux acceleration factor, as previously

Figure 8 shows the results of this SER extraction, considering results of Figure 17, durations and memory capacities related to the different experiments. Global SER values of 9.7 and 28.8 a.u. are obtained for Rousset (sea-level) and ASTEP (altitude) experiments, which leads to an

These results demonstrate a very limited impact of the atmospheric radiation on the total SER without ECC, typically in the range [10-100] FIT/GBit. With respect to all other internal failure mechanisms, the external natural radiation constraint is found to represent less than one third (27%) of the total SER. Note that all these SER values are found strictly equal to 0 if ECC is activated on the chips, due to the fact that only rare events always corresponding to single cell



have a system with two equations and two unknown quantities:

a

a

estimation of α-i-SER = 3.2 and n-SER = 8.7 a.u.

states "0" and "1".

386 Computational and Numerical Simulations

reported in II.B.

upsets have been detected.

In this last paragraph, we conclude by comparing these experimental results with predictive values obtained using the TIARA-G4 NVM simulation platform. Figure 20 summarizes this comparison for the different defined SER components. In this last paragraph, we conclude by comparing these experimental results with predictive values obtained using the TIARA-G4 NVM simulation platform. Figure 20 summarizes this comparison for the different defined SER components.

A good agreement is found for the neutron-SER taking into account all experimental and simulation uncertainties, in the first instance, the relatively weak statistics of the experiment in terms of number of events detected. Indeed, despite the duration of the experiment (18 months) and the huge quantity of data to manipulate (the individual VT evolution of more than 50 Gbits of memory cells has been stored and processed), the statistics of this first experiment remains relatively weak because of the extremely low rate of cell flips in this kind of memory. A good agreement is found for the neutron-SER taking into account all experimental and simulation uncertainties, in the first instance, the relatively weak statistics of the experiment in terms of number of events detected. Indeed, despite the duration of the experiment (18 months) and the huge quantity of data to manipulate (the individual VT evolution of more than 50 Gbits of memory cells has been stored and processed), the statistics of this first experiment remains relatively weak because of the extremely low rate of cell flips in this kind of memory.

For alpha-SER, the discrepancy is flagrant between the two values. This confirms our initial precaution to name the second extracted component of the SER (Fig. 19) α-i-SER instead of classically α-SER because, in the present case of FG devices, this component may be the result of other intrinsic failure mechanisms occurring in parallel inside the chips. From literature [31-33], we can invoke different intrinsic or extrinsic leakage current mechanisms though the dielectric layers present in the floating gate stack (tunnel oxide, ONO, spacers). Intrinsic mechanisms that contribute to charge loss are field-assisted electron emission, thermionic emission and electron detrapping. Extrinsic mechanisms are essentially oxide defects that can form conductive paths through a given dielectric. Whatever the mechanism or eventually the activation of several leakage paths, our results suggest that these electrical processes appear to be dominant in the observed failure rate with respect to the contribution of alpha-particle internal emission. This point will have to be carefully reevaluated in future works.

determined through experimental emissivity measurements. The experimental verification of these simulated results has been conducted, for the first time, following a totally new approach: the direct exposition to natural radiation of a large amount of test circuits programmed and periodically read at wafer-level with a dedicated industrial test equipment. In spite of a relatively weak statistics achieved during this experimental phase, the remarkable conver‐ gence of the experimental results and our numerical simulations (considering no fitting parameter in the complete simulation chain) for the neutron- SER indicates that this later value is more than two decades below the soft error rate usually measured in modern SRAMs. In the same way, the comparison of experimental data measured at sea-level and alpha-SER simulations clearly suggests that another mechanism than internal alpha-particle production in bulk materials may be responsible of charge loss from floating gates. This point will have

Computational Modeling and Monte Carlo Simulation of Soft Errors in Flash Memories

http://dx.doi.org/10.5772/57220

389

The authors would like to acknowledge G. Just, A. Regnier and J.L. Ogier from STMicroelec‐ tronics (Reliability and Electrical Characterization Laboratory, Rousset Plant, France) for their contribution to the electrical characterization of the flash memory wafers and Sébastien Sauze (ASTEP platform) for his technical and support. They also sincerely acknowledge their past post-doc students Sébastien Martinie (now at CEA-LETI, Grenoble) and Sébastien Serre (now at TRAD, Toulouse) for their different contributions to this work. The logistical support of the Institute for Radio astronomy at Millimeter Wavelengths (IRAM) is finally gratefully acknowl‐

, Gilles Gasiot2

[1] Massengill L.W., Bhuva B.L., Holman W.T., Alles M.L., Loveless T.D. Technology Scaling and Soft Error Reliability. In: Proceedings of the IEEE International Reliabili‐

[2] International Technology Roadmap for Semiconductors (ITRS), available online at

and Philippe Roche1

to be carefully investigated in future works.

, Daniela Munteanu1

1 Aix-Marseille University & CNRS, Marseille, France

ty Physics Symposium 2012, 3C.1

2 STMicroelectronics, Crolles, France

www.itrs.net

**Acknowledgements**

edged.

**Author details**

Jean-Luc Autran1

**References**

**Figure 20.** Comparison of the SER component values obtained by TIARA-G4 NVM simulation and from exposition to natural radiation in Rousset and on ASTEP.

Another interesting point of comparison comes from the ratio of the numbers of upset cells to the numbers of cells for which VT have shifted but not enough to cross the limit of 5.7 V delimiting the two logical states. Although statistics are low for data of Fig. 18, the ratio (number of cells B/number of cells A) can be roughly evaluated to 50%. From simulation results with a much larger statistics, this ratio is 40.7%, which is clearly in the same order of magnitude. Beyond the fact that this point consolidates the comparison between experiment and simula‐ tion, this result shows that the number of impacted cells with a final VT ranging between the sense voltage value and the edge of the initial Gaussian distribution is approximately two times larger than the number of cells verifying the upset criterion.

### **6. Conclusion**

In conclusion, we developed in this work a numerical simulation code (TIARA-G4 NVM) capable of computing the soft-error rate of floating-gate flash memories induced by the two main natural radiation components at ground-level: the atmospheric high-energy neutrons and the alpha-particles emitted from ultra-traces of radioactive contaminants in circuit materials. Based on Geant4 geometry classes, elements and materials, the code is able to reproduce the circuit geometry from silicon substrate to back-end-of-line levels with fidelity. In complement to geometrical aspects, TIARA-G4 NVM also integrates a new module describing the charge loss from floating gates as a function of the properties (LET) of the incident ionizing particles. Using this code, we performed extensive Monte Carlo simulations on large arrays of memory cells (up to 105 cells) related to a 90 nm NOR floating-gate flash memory architecture designed by STMicroelectronics. Values of the SER for atmospheric neutrons and alpha-particle emitters have been computed and expressed, respectively, at sealevel (New-York City) and for a concentration of 238U in the circuit materials separately determined through experimental emissivity measurements. The experimental verification of these simulated results has been conducted, for the first time, following a totally new approach: the direct exposition to natural radiation of a large amount of test circuits programmed and periodically read at wafer-level with a dedicated industrial test equipment. In spite of a relatively weak statistics achieved during this experimental phase, the remarkable conver‐ gence of the experimental results and our numerical simulations (considering no fitting parameter in the complete simulation chain) for the neutron- SER indicates that this later value is more than two decades below the soft error rate usually measured in modern SRAMs. In the same way, the comparison of experimental data measured at sea-level and alpha-SER simulations clearly suggests that another mechanism than internal alpha-particle production in bulk materials may be responsible of charge loss from floating gates. This point will have to be carefully investigated in future works.
