**1. Introduction**

Microelectronics industry has experienced tremendous progress in the last forty years, especially with regard to the evolution of the products (i.e. integrated circuits) performances, and at the same time, concerning the drastic reduction of manufacturing costs by elementary function integrated. So far, this considerable growth of the semiconductor industry has been due to its technological capability to constantly miniaturize the elementary components of circuits, namely the MOSFET (metal-oxide-semiconductor field effect transistor), the basic building block of VLSI (very large scale integration) integrated circuits. The continuous decrease of the silicon surface used by these elementary components has kept the race integration at the rhythm dictated by the famous "Moore's Law", which states that the number transistors per integrated circuit doubles every 18 to 24 months [1]. However, the conventional bulk MOSFET scaling down encountered this last decade serious physical and technological limitations, mainly related to the gate oxide (SiO2) leakage currents [2-3], the large increase of parasitic short channel effects and the dramatic mobility reduction [4] due to highly doped silicon substrates precisely used to reduce these short channel effects. Technological solutions have been proposed in order to continue to use the "bulk solution" until the 32-28 nm ITRS nodes [5]. Most of these solutions have then introduced high-permittivity gate dielectric stacks (to reduce the gate leakage [1], [6], midgap metal gate (to suppress the Silicon gate polyde‐ pletion-induced parasitic capacitances) and strained silicon channel (to increase carrier mobility) [7]. However, in parallel to these efforts, alternative solutions to replace the conven‐ tional bulk MOSFET architecture have been proposed and studied in the recent literature. These options are numerous and can be classified in general according to three main directions: (i) the use of new materials in the continuity of the "bulk solution", allowing increasing

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MOSFET performances due to their dielectric properties (permittivity), electrostatic immunity (SOI materials), mechanical (strain), or transport (mobility) properties; (ii) the complete change of the device architecture (e.g. Multiple-Gate devices, Silicon nanowires MOSFET) allowing better electrostatic control, and, as a result, intrinsic channels with higher mobilities and currents; (iii) the exploitation of certain new physical phenomena that appear at the nanometer scale, such as quantum ballistic transport, substrate orientation or modifications of the material band structure in devices/wires with nanometer dimensions [8-9].

these devices is no longer degraded by the leakage current of the reversely-biased sourcechannel and channel-drain diodes, but is uniquely controlled by the gate. This could be very attractive for ultra-short devices, typically for deca-nanometer channel lengths, for which the

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Although standard DGFETs with junctions, also called inversion-mode (IM) DGFETs, and JL-DGFETs are very similar, the operating principle of the junctionless devices is quite different from that of IM-DGFETs. The conventional IM-DGFET is normally in the off state at VG=0 V; the source-channel and channel-drain junctions are reversely biased and the current in the transistor is off. A voltage must be applied on the gate to turn on the transistor. The vertical electric field created across the gate insulator attracts minority carriers at the silicon/insulator interface to create an inversion (conduction) channel and then these carriers flow from source to drain through this channel. Thus, in IM-DGFET transistor, the electric field is the highest when the transistor is in the on-state and the lowest in the off-state. In contrast to IM-DGFET, the electric field is high in the off-state for JL-DGFET and very low in the on-state [31]. The junctionless transistor is normally on-state and the current flows into the channel which extends throughout the entire silicon film [32]. In this transistor, the work function difference between the gate and the doped silicon film leads to a positive flat-band voltage. Therefore, in the on-state, the junctionless transistor is under flat-band conditions and the transverse electric field is zero [32]. The conduction takes place in the film volume unlike conventional devices where the conduction takes place at the silicon/insulator interface. Thus, even at high gate voltages, the majority carriers flow mainly through the film volume and not at the interface. This can be beneficial for the carrier mobility because the impact of the surface roughness is reduced. In order to switch-off the transistor, a low gate voltage has to be applied on the gates; the vertical electric field increases and depletes the film, which cuts-off the transistor (in contrast to IM-DGFET where the high electric field is used to create an inversion layer at the

From a radiation-hardness point-of-view, the high doping level in the silicon film of JL-DGFET could have a negative impact on its immunity to single-events, because the floating-body effects are expected to be strong. Then, in spite of its double-gate configuration, JL-DGFET should be more sensitive to radiation than IM-DGFET where the channel is intrinsic. The transient response of the IM-DGFET devices under heavy-ion irradiation has been studied by 3-D numerical simulation in [35]-[38]. These previous studies show that IM-DGFET shows a better resistance to radiation than Fully Depleted SOI transistors (FDSOI) with single-gate, due to the enhanced control of the film potential by the two connected gates which reduces the floating-body effects. The bipolar amplification of JL-DGFET was studied in [39] and compared to that of IM-DGFET with similar geometrical parameters. In that work, we have shown that JL-DGFET is characterized by a higher bipolar gain than IM-DGFET, due to worse radiation hardness. However, in that preliminary work we have not analyzed in depth the radiation sensitivity of JL-DGFET, especially the dependence on the position of the ion strike in the channel. Similarly, the impact of time parameters of the ion track on the transient response of

off-state current could be reduced.

interface).

these devices has not been addressed.

As the MOSFET is scaling down, the sensitivity of the integrated circuits to radiation coming from the natural space or present in the terrestrial environment has been found to seriously increase [10-13]. In nowadays ultra-scaled devices, natural radiation is inducing one of the highest failure rates of all reliability concerns for devices and circuits entering in the area of nanoelectronics [5],[14]. In particular, ultra-scaled memory integrated circuits have been found to be more sensitive to single-event-upset (SEU) and digital devices more subjected to digital single-event transient (DSETs). This sensitivity is a direct consequence of the reduction of device dimensions and spacing within memory cells combined with the reduction of supply voltage and node capacitance, resulting in a decrease of both the critical charge (i.e. the minimum amount of charge required to induce the flipping of the logic state) and the sensitive area (i.e. the minimum collection area inside which a given particle can deposit enough charge to induce the flipping of the cell) [13]-[15].

As explained before, among the technological solutions to replace the bulk MOSFET, it was envisaged to completely change the device architecture, making then possible a better electrostatic control of the channel by the gate. MOSFETs designed with Double-Gate (DGFET) configuration are now widely recognized as one of the most promising solutions to meet the requirements of the roadmap at the nanometer scale [16]-[20]. These structures present a very good control of parasitic short channel effects (SCE) and drain-induced barrier lowering (DIBL) resulting from an improved electrostatic coupling between the conduction channel and the gate electrodes [20]-[22]. The constraints on the channel doping can then be greatly reduced in these devices, which can be designed with an intrinsic film. Parasitic doping level fluctuation effects are then eliminated and, in the same time, the carrier mobility and drain current are increased [23]. The intrinsic films are also characterized by a high probability of ballistic transport in the channel [24]-[28], which could additionally reinforce the electrical perform‐ ances of DGFET.

Recently, a new concept of field-effect MOS transistor without junctions (called junctionless MOSFET) has been proposed [29]-[34] and experimentally validated. A junctionless MOSFET is a transistor having the same type of semiconductor throughout the entire silicon film, including the source, channel and drain regions. A Double-Gate junctionless MOSFET (JL-DGFET) contains a heavily doped silicon film sandwiched between two gate electrodes connected together. The two gates are used to deplete the silicon film (resp. to accumulate majority carriers from the doped silicon layer) and then to turn off (resp. to turn on) the device. This is a very interesting transistor, particularly from a technological point-of-view, because its fabrication is simplified compared to the conventional process (there are no doping gradients in the device [31] and no semiconductor-type inversion). The off-state current of these devices is no longer degraded by the leakage current of the reversely-biased sourcechannel and channel-drain diodes, but is uniquely controlled by the gate. This could be very attractive for ultra-short devices, typically for deca-nanometer channel lengths, for which the off-state current could be reduced.

MOSFET performances due to their dielectric properties (permittivity), electrostatic immunity (SOI materials), mechanical (strain), or transport (mobility) properties; (ii) the complete change of the device architecture (e.g. Multiple-Gate devices, Silicon nanowires MOSFET) allowing better electrostatic control, and, as a result, intrinsic channels with higher mobilities and currents; (iii) the exploitation of certain new physical phenomena that appear at the nanometer scale, such as quantum ballistic transport, substrate orientation or modifications of the material

As the MOSFET is scaling down, the sensitivity of the integrated circuits to radiation coming from the natural space or present in the terrestrial environment has been found to seriously increase [10-13]. In nowadays ultra-scaled devices, natural radiation is inducing one of the highest failure rates of all reliability concerns for devices and circuits entering in the area of nanoelectronics [5],[14]. In particular, ultra-scaled memory integrated circuits have been found to be more sensitive to single-event-upset (SEU) and digital devices more subjected to digital single-event transient (DSETs). This sensitivity is a direct consequence of the reduction of device dimensions and spacing within memory cells combined with the reduction of supply voltage and node capacitance, resulting in a decrease of both the critical charge (i.e. the minimum amount of charge required to induce the flipping of the logic state) and the sensitive area (i.e. the minimum collection area inside which a given particle can deposit enough charge

As explained before, among the technological solutions to replace the bulk MOSFET, it was envisaged to completely change the device architecture, making then possible a better electrostatic control of the channel by the gate. MOSFETs designed with Double-Gate (DGFET) configuration are now widely recognized as one of the most promising solutions to meet the requirements of the roadmap at the nanometer scale [16]-[20]. These structures present a very good control of parasitic short channel effects (SCE) and drain-induced barrier lowering (DIBL) resulting from an improved electrostatic coupling between the conduction channel and the gate electrodes [20]-[22]. The constraints on the channel doping can then be greatly reduced in these devices, which can be designed with an intrinsic film. Parasitic doping level fluctuation effects are then eliminated and, in the same time, the carrier mobility and drain current are increased [23]. The intrinsic films are also characterized by a high probability of ballistic transport in the channel [24]-[28], which could additionally reinforce the electrical perform‐

Recently, a new concept of field-effect MOS transistor without junctions (called junctionless MOSFET) has been proposed [29]-[34] and experimentally validated. A junctionless MOSFET is a transistor having the same type of semiconductor throughout the entire silicon film, including the source, channel and drain regions. A Double-Gate junctionless MOSFET (JL-DGFET) contains a heavily doped silicon film sandwiched between two gate electrodes connected together. The two gates are used to deplete the silicon film (resp. to accumulate majority carriers from the doped silicon layer) and then to turn off (resp. to turn on) the device. This is a very interesting transistor, particularly from a technological point-of-view, because its fabrication is simplified compared to the conventional process (there are no doping gradients in the device [31] and no semiconductor-type inversion). The off-state current of

band structure in devices/wires with nanometer dimensions [8-9].

to induce the flipping of the cell) [13]-[15].

228 Computational and Numerical Simulations

ances of DGFET.

Although standard DGFETs with junctions, also called inversion-mode (IM) DGFETs, and JL-DGFETs are very similar, the operating principle of the junctionless devices is quite different from that of IM-DGFETs. The conventional IM-DGFET is normally in the off state at VG=0 V; the source-channel and channel-drain junctions are reversely biased and the current in the transistor is off. A voltage must be applied on the gate to turn on the transistor. The vertical electric field created across the gate insulator attracts minority carriers at the silicon/insulator interface to create an inversion (conduction) channel and then these carriers flow from source to drain through this channel. Thus, in IM-DGFET transistor, the electric field is the highest when the transistor is in the on-state and the lowest in the off-state. In contrast to IM-DGFET, the electric field is high in the off-state for JL-DGFET and very low in the on-state [31]. The junctionless transistor is normally on-state and the current flows into the channel which extends throughout the entire silicon film [32]. In this transistor, the work function difference between the gate and the doped silicon film leads to a positive flat-band voltage. Therefore, in the on-state, the junctionless transistor is under flat-band conditions and the transverse electric field is zero [32]. The conduction takes place in the film volume unlike conventional devices where the conduction takes place at the silicon/insulator interface. Thus, even at high gate voltages, the majority carriers flow mainly through the film volume and not at the interface. This can be beneficial for the carrier mobility because the impact of the surface roughness is reduced. In order to switch-off the transistor, a low gate voltage has to be applied on the gates; the vertical electric field increases and depletes the film, which cuts-off the transistor (in contrast to IM-DGFET where the high electric field is used to create an inversion layer at the interface).

From a radiation-hardness point-of-view, the high doping level in the silicon film of JL-DGFET could have a negative impact on its immunity to single-events, because the floating-body effects are expected to be strong. Then, in spite of its double-gate configuration, JL-DGFET should be more sensitive to radiation than IM-DGFET where the channel is intrinsic. The transient response of the IM-DGFET devices under heavy-ion irradiation has been studied by 3-D numerical simulation in [35]-[38]. These previous studies show that IM-DGFET shows a better resistance to radiation than Fully Depleted SOI transistors (FDSOI) with single-gate, due to the enhanced control of the film potential by the two connected gates which reduces the floating-body effects. The bipolar amplification of JL-DGFET was studied in [39] and compared to that of IM-DGFET with similar geometrical parameters. In that work, we have shown that JL-DGFET is characterized by a higher bipolar gain than IM-DGFET, due to worse radiation hardness. However, in that preliminary work we have not analyzed in depth the radiation sensitivity of JL-DGFET, especially the dependence on the position of the ion strike in the channel. Similarly, the impact of time parameters of the ion track on the transient response of these devices has not been addressed.

In the present work, we investigated by 3-D numerical simulation the sensitivity to singleevent of JL-DGFET and we compared the JL-DGFET behavior with that of more conventional inversion-mode devices, IM-DGFET and FDSOI. The effect of an ion strike on the main internal electrical parameters inside the structure (potential and carrier density) and on the drain current transient is investigated. JL-DGFET is compared with IM-DGFET and FDSOI in terms of collected charge and bipolar amplification. The impact on the transient response of several parameters of the ion track (such as the characteristic time and the track radius), as well as of the position of the ion strike along the channel and of the film doping level is addressed. Our simulations show that JL-DGFET may be more resistant to heavy-ion radiation (i.e. may have a lower bipolar gain) than IM-DGFET and FDSOI for some particular configurations (specific ion LET values and ion-impact locations along the channel between the source and drain contacts).

and a thick silicon substrate lowly-doped at 1016 cm-3 have been also considered in FDSOI. The very thin buried oxide is necessary to minimize the short channel effects in these devices. All devices were calibrated to meet the requirements of the ITRS Low Power technology node corresponding to the year 2015 [5]. To facilitate comparison, the gates work function has been

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Numerical simulations in 3 dimensions (3-D) were carried out with the DESSIS module of the commercial simulator Synopsis [41]. We considered in the simulation physical models such as Shockley-Read-Hall (SRH) and Auger recombination models, as well as the Fermi-Dirac carrier statistics. In the SRH recombination model, carrier lifetimes depend on the doping level [41-43]. The model of the effective intrinsic density includes a doping-dependent band-gap narrowing (Slotboom's model [41]) and a lattice temperature-dependent band gap. The carrier transport model used in the simulation is the hydrodynamic model which includes the energy balance equations for electrons, holes and lattice. We also used models for impact ionization and carrier mobility depending on the carrier energy calculated by the hydrodynamic model. The mobility model also takes into account the dependence of mobility with normal electric field (through the Lombardi's model [41]), temperature and channel doping. The physical parameters of the models used in the simulation (in particular the carrier mobility) are not calibrated on experimental data, but realistic values are considered in the simulation. The parameters and models chosen in this way were then used for the simulation of drain current transients induced by the energetic particle striking the sensitive area of the device. The transistors were simulated in the off-state (most sensitive case) under VG=0 V and VD=0.75 V. Transient simulations have been performed considering an ion track with a Gaussian shape and a very narrow radius of 20 nm, in order to facilitate comparison with experimental and simulation results reported in references [35] and [44]. In addition, we performed in section 5.2 simulations with different track radii in order to discuss the influence of the track radius on the radiation sensitivity of the three devices simulated here. The ion track has a Gaussian time dependence centered on t=10 ps, with a characteristic time of 2 ps. We chose this charac‐ teristic time value because a good agreement was obtained in a previous study [35] between the simulation and experimental data. However, it is clear that, if we change the characteristic time of the Gaussian distribution, the transient current will be modified. Nevertheless, it is not sure that the radiation resistance of the device and its bipolar amplification will change. To clarify this point, additional simulations with different characteristic time will be presented in section 5.1. The linear energy transfer (LET) value is kept constant along the ion track; this is

justified by the very short ion-track length (equal to the silicon film thickness, 6 nm).

The ion strikes the device in a vertical incidence perpendicular to the gate, as shown in Fig. 1. In a first step, we considered that the ion strikes in the middle of the channel (at equal distance from the source and drain contacts). In a second step, we will consider several locations for the ion impact between the source and the drain, in order to investigate the sensitivity of the device to the ion strike position (section 5.3). In most cases the ion track is not entirely contained in the active area of the device, which requires accurately calculating the charge deposited by

refined to achieve the same off-state current (IOFF) for all devices.

**2.2. Simulation models**

The chapter is organized as follows. In section 2 we describe in detail the simulated devices and the simulation models used in this work. The static operation of JL-DGFET, IM-DGFET and FDSOI is presented in section 3. The transient response of JL-DGFET for ions striking in the middle of the channel (at equal distance from the source and drain contacts) is detailed in section 4. In particular, we compare JL-DGFET, IM-DGFET and FDSOI in terms of electron density, electrostatic potential, drain current transient and bipolar amplification. Section 5 addresses the impact of heavy-ion track parameters (ion track characteristic time, track radius and ion strike location between source and drain contact) on the JL-DGFET transient response. The JL-DGFET behavior is systematically compared with that of IM-DGFET and FDSOI structures. Finally, section 6 presents the influence of the silicon film doping level on the bipolar amplification in JL-DGFET.
