**1. Introduction**

Electric Power Systems, High Voltage, Electric Machines (POWER '08), Venice, Italy,

[6] Surianu F.D., Measurements on the Ground and Mathematical Modeling of Voltages Induced by High Voltage Overhead Power Lines Working on Parallel and Narrow Routes, Proceedings of WSEAS International Conference on Electric Power Systems, High Voltages, Electric Machines, Genova, Italy, 17-19 Oct., 2009, ISSN 1790-5117,

[7] Surianu F.D., Olariu A., Technical solution to alert the working staff to the dangerous values of the currents induced in the conductors of the disconnected circuit of a dou‐ ble circuit overhead power line, Proceedings of 45th International Universities' Pow‐

[8] Vatau D., Surianu F.D., Bianu A.E., Olariu A., Bota V., Considerations on the Electro‐ magnetic Pollution Produced by High Voltage Power Plants, WSEAS Proceedings of the European Computing Conference, 28-30 April, 2011, Paris, France, ISBN:

[9] Hemmady S., Antonsen T.M., Ott E. Jr.,Anlage S.M., Statistical Prediction and Meas‐ urement of Induced Voltages on Components Within Complicated Enclosures: A Wave-Chaotic Approach, IEEE Transactions on Electromagnetic Comparibility, Au‐

gust 2012, Volume 54, Number 4, IEMCAE, ISSN 0018-9375, pp. 758-771.

er Engineering Conference (UPEC), 2010, Cardiff, United Kingdom, pp.1-4;

21-23 November, 2008, ISSN 1790-5117, ISBN 978-960-474-026-0, pp. 61-66;

ISBN 978-960-474-130-4, pp. 51-58;

366 Computational and Numerical Simulations

978-960-474-297-4, pp. 182-186.

As CMOS technologies are scaling down, the susceptibility of integrated circuits (IC's) to radiation coming from space or present in the terrestrial environment has been found to seriously increase [1]. Until now, radiation effects in IC's have mainly been an issue for space or avionics applications. At ground level and in nowadays ultra-scaled devices, natural atmospheric radiation principally induces Single event effects (SEE), which has been identified to induce one of the highest failure rates of all reliability concerns for devices and circuits entering in the area of nano-electronics [2]. SEE's are the result of the interaction of highly energetic particles, such as protons, neutrons, alpha particles, or heavy ions, with the sensitive region(s) of a microelectronic device or circuit. A single event may perturb the device/circuit operation (e.g., reverse or flip the data state of a memory cell, latch, flip-flop, etc.) or definitively damage the circuit (e.g. gate oxide rupture, destructive latch-up events) [3].

Among all integrated circuits used in many application areas for which a high reliability level is required (medical, space, automotive, networking, nuclear), non-volatile memories are known for their relative robustness to single events, even if the different components of a flash memory circuit (on one hand the memory cell array, on the other hand the peripheral control circuitry) exhibit distinct levels of radiation sensitivity. In addition, the specific question of their sensitivity to the terrestrial radiation environment has been little studied until now. Cellere et al. [4-5] and Gerardin et al. [6-7] have been the first to clearly state, using accelerated tests, that atmospheric neutron induced soft error occurrence is possible in flash memories, although with extremely low probabilities at ground level. A vey recent study by Just et al. [8], based for the first time on real-time tests performed in a mountain altitude natural environ‐ ment, has concluded in a similar way: natural atmospheric radiation at ground level can induce

© 2014 Autran et al.; licensee InTech. This is a paper distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

soft-errors in flash memories, typically several decades below the soft-error rate (SER) of static RAM (SRAM) of comparable technological nodes.

In this context, we recently developed a numerical simulation code capable of computing the SER of floating-gate flash memories. Our simulation platform named TIARA-G4 and described in Ref. [9], has been adapted to flash memory architectures (TIARA-G4 NVM release for "Non-Volatile Memories") by modifying the device/circuit 3D geometries and by implementing a model for charge loss from the floating gates induced by ionizing particles. This chapter presents in detail our modeling and simulation approach as well as the code validation by comparison of numerical results with experimental data reported in [8].

The chapter is organized as follows: in Section II, we briefly introduce some basic knowledge about the architecture and electrical operation of floating gate flash memories. Section III also briefly reviews the current comprehension of radiation effects in floating-gate memories. The objective of these two first sections is to introduce for a non-specialist reader the technical background necessary for a good understanding of the second part of this chapter more specifically dedicated to computational modeling and Monte Carlo simulation issues. In Section IV, we detail our modeling and simulation approach based on the adaptation of our TIARA-G4 simulation platform [9] to flash memory architectures. Finally, in Section V, we expose the simulation results and compare them to experimental results obtained on a large collection of memories exposed to natural radiation.

on-chip using special DC-to-DC converters (charge pumps) that uses capacitors as energy storage elements to create higher voltages from the circuit external supply voltage. Two

**Figure 1.** Schematic cross-sections of a floating-gate transistor, acting as the elementary memory element in a flash

information in the cell. The difference between the two levels, ΔVT, is directly linked to the variation of the charge amount in the FG and to the coupling capacitance between CG and FG

a demarcation level between the two logical states "0" and "1" (Fig. 2 right).

VFG

different values of the floating-gate charge corresponding to erased and programmed states.

VFG

REF, intermediate between VT

QFG > 0 Erased

I DS

VT

**Figure 2.** Left: Equivalent capacitance network of the floating-gate transistor with four terminals and definition of the main voltage and capacitance values. Right: Electrical characteristics IDS(VCG) of the floating-gate transistor with two

To form dense circuits with storage capacities up to several millions or billions of bits, elementary memory cells are arranged in matrix, i.e. in rows and columns. In addition, cells are generally grouped to form a hierarchical organization of increasing size: groups, blocks, pages, etc. Lines, called "wordlines" are connected to the control gates and columns, called "bitlines", are connected to the drain terminals. Around the matrix memory is the peripheral control circuitry composed of additional circuits for decoding cell addresses, generating high voltage signals (charge pumps), reading cells (sense amplifiers) and managing circuit infor‐ mation. There are two main types of circuit architectures at the memory plan level, called NOR and NAND gate flash memories, each corresponds to a certain manner to associate several cells. The construction and the operation of NOR and NAND flash memories are briefly

I DS

, see Fig. 2 right) are considered to store one bit of

Figure 2. Left: Equivalent capacitance network of the floating-gate transistor with four terminals and definition of the main voltage and capacitance values. Right: Electrical characteristics IDS(VCG) of the floating-gate transistor with two different values of the floating-gate charge

<sup>0</sup> VT <sup>1</sup> VT REF

**Logic "1" Logic "0"**

**Logic "1" Logic "0"**

QFG > 0 Erased

VT

To form dense circuits with storage capacities up to several millions or billions of bits, elementary memory cells are arranged in matrix, i.e. in rows and columns. In addition, cells are generally grouped to form a hierarchical organization of increasing size: groups, blocks, pages, etc. Lines, called "wordlines" are connected to the control gates and columns, called "bit-lines", are connected to the drain terminals. Around the matrix memory is the peripheral control circuitry composed of additional circuits for decoding cell addresses, generating high voltage signals (charge pumps), reading cells (sense amplifiers) and managing circuit information. There are two main types of circuit architectures at the memory plan level, called NOR and NAND gate flash memories, each corresponds to a certain manner to associate several cells. The construction and the operation of NOR and NAND flash memories

Figure 2. Left: Equivalent capacitance network of the floating-gate transistor with four terminals and definition of the main voltage and capacitance values. Right: Electrical characteristics IDS(VCG) of the floating-gate transistor with two different values of the floating-gate charge

<sup>0</sup> VT <sup>1</sup> VT REF

To form dense circuits with storage capacities up to several millions or billions of bits, elementary memory cells are arranged in matrix, i.e. in rows and columns. In addition, cells are generally grouped to form a hierarchical organization of increasing size: groups, blocks, pages, etc. Lines, called "wordlines" are connected to the control gates and columns, called "bit-lines", are connected to the drain terminals. Around the matrix memory is the peripheral control circuitry composed of additional circuits for decoding cell addresses, generating high voltage signals (charge pumps), reading cells (sense amplifiers) and managing circuit information. There are two main types of circuit architectures at the memory plan level, called NOR and NAND gate flash memories, each corresponds to a certain manner to associate several cells. The construction and the operation of NOR and NAND flash memories

 **NOR architecture:** The organization of the NOR gate flash, shown in Fig. 3(a) is the following: several cells are connected to a bit line; each cell has the source terminal connected directly to ground, and the drain terminal is connected directly to a bit line. The drain contacts of individual transistors connected to the bitline are shared between two adjacent cells. This setting of elementary devices is called "NOR flash" because it operates as a NOR gate. The default state of a single-level NOR flash cell is logically equivalent to a binary "1" value: when a suitable voltage is applied on the control gate the current flows through the channel and the bitline voltage is pulled down. The programming operation of a NOR flash cell (i.e. setting to a binary "0" value) is done by injection of hot carriers from the channel. The high current, required by this mechanism, limits the parallelism of the operation (only some cells can be programmed in same time) [10]. The programming procedure is the following: a voltage increase (typically > 5 V) is applied to the control gate which turns on the channel and the electrons can flow from source to drain (for an nchannel MOS transistor). The source-drain current is sufficiently high so that a certain number of electrons of high energy are able to pass through the insulating layer on the floating gate by hot electrons injection mechanism. The erasing operation of a NOR flash cell (resetting it to the "1" state) is done by Fowler-Nordheim (FN) mechanism. For this purpose, a large voltage of the opposite polarity is applied between the control gate and the source terminal, pulling out the electrons from the floating gate by FN tunneling. This organization of the NOR flash allows a fast random access (approximately 100 ns). The programming operation is carried out at block level, and is much slower (approximately 5 μs). The erasing operation is carried out on the level of block and is

 **NOR architecture:** The organization of the NOR gate flash, shown in Fig. 3(a) is the following: several cells are connected to a bit line; each cell has the source terminal connected directly to ground, and the drain terminal is connected directly to a bit line. The drain contacts of individual transistors connected to the bitline are shared between two adjacent cells. This setting of elementary devices is called "NOR flash" because it operates as a NOR gate. The default state of a single-level NOR flash cell is logically equivalent to a binary "1" value: when a suitable voltage is applied on the control gate the current flows through the channel and the bitline voltage is pulled down. The programming operation of a NOR flash cell (i.e. setting to a binary "0" value) is done by injection of hot carriers from the channel. The high current, required by this mechanism, limits the parallelism of the operation (only some cells can be programmed in same time) [10]. The programming procedure is the following: a voltage increase (typically > 5 V) is applied to the control gate which turns on the channel and the electrons can flow from source to drain (for an nchannel MOS transistor). The source-drain current is sufficiently high so that a certain number of electrons of high energy are able to pass through the insulating layer on the floating gate by hot electrons injection mechanism. The erasing operation of a NOR flash cell (resetting it to the "1" state) is done by Fowler-Nordheim (FN) mechanism. For this purpose, a large voltage of the opposite polarity is applied between the control gate and the source terminal, pulling out the electrons from the floating gate by FN tunneling. This organization of the NOR flash allows a fast random access (approximately 100 ns). The programming operation is carried out at block level, and is much slower (approximately 5 μs). The erasing operation is carried out on the level of block and is

Figure 1. Schematic cross-sections of a floating-gate transistor, acting as the elementary memory element in a flash memory circuit, along its length

Computational Modeling and Monte Carlo Simulation of Soft Errors in Flash Memories

As illustrated in Fig. 1, the memory cell consists of a single n-channel transistor with a control-gate (CG) and an electrically isolated polysilicon floating gate (FG). The two gates are separated by an oxide-nitride-oxide dielectric stack (ONO), often called "inter-poly oxide". Data can be stored in the cell by adding or removing electrons in the FG, which induces changes of the threshold voltage of the cell transistor. Charge injection into the floating-gate through the tunnel oxide (TO) is governed by the electrical signals applied on the control-gate owing to the electrostatic coupling existing between the two gates. Indeed, the electrostatic potential of the FG (VFG, see Fig. 2 left) is directly determined by the potential of the CG and the amount of electrical charge stored in the FG. These operations require high voltage signals produced on-chip using special DC-to-DC converters (charge pumps) that uses capacitors as energy storage elements to create higher voltages from the circuit external supply voltage. Two threshold voltage levels (VT0 and VT1, see Fig. 2 right) are considered to store one bit of information in the cell. The difference between the two levels, ΔVT, is directly linked to the variation of the charge amount in the FG and to the coupling capacitance between CG and FG electrodes. A reference voltage value VTREF, intermediate between VT0 and VT1 is considered as a demarcation level between the two logical states "0" and

0 and VT

Figure 1. Schematic cross-sections of a floating-gate transistor, acting as the elementary memory element in a flash memory circuit, along its length

As illustrated in Fig. 1, the memory cell consists of a single n-channel transistor with a control-gate (CG) and an electrically isolated polysilicon floating gate (FG). The two gates are separated by an oxide-nitride-oxide dielectric stack (ONO), often called "inter-poly oxide". Data can be stored in the cell by adding or removing electrons in the FG, which induces changes of the threshold voltage of the cell transistor. Charge injection into the floating-gate through the tunnel oxide (TO) is governed by the electrical signals applied on the control-gate owing to the electrostatic coupling existing between the two gates. Indeed, the electrostatic potential of the FG (VFG, see Fig. 2 left) is directly determined by the potential of the CG and the amount of electrical charge stored in the FG. These operations require high voltage signals produced on-chip using special DC-to-DC converters (charge pumps) that uses capacitors as energy storage elements to create higher voltages from the circuit external supply voltage. Two threshold voltage levels (VT0 and VT1, see Fig. 2 right) are considered to store one bit of information in the cell. The difference between the two levels, ΔVT, is directly linked to the variation of the charge amount in the FG and to the coupling capacitance between CG and FG electrodes. A reference voltage value VTREF, intermediate between VT0 and VT1 is considered as a demarcation level between the two logical states "0" and

VT = QFG / CPP

<sup>1</sup> is considered as

http://dx.doi.org/10.5772/57220

369

VCG

QFG < 0 Programmed

VCG

QFG < 0 Programmed

VT = QFG / CPP

threshold voltage levels (VT

"1" (Fig. 2 right).

CPP

"1" (Fig. 2 right).

(left) and its width (right).

(left) and its width (right).

memory circuit, along its length (left) and its width (right).

electrodes. A reference voltage value VT

VCG

CS CD VS VD VSUB Cox

CPP

VCG

0 and VT 1

corresponding to erased and programmed states.

CS CD VS VD VSUB Cox

corresponding to erased and programmed states.

are briefly described in the following.

are briefly described in the following.

described in the following.
