**2. Simulation details**

### **2.1. Description of the simulated devices**

Figure 1 shows the schematic 3-D description of the simulated devices. Planar IM-DGFET structures are based on real devices reported in [40]. These devices are designed with 20 nm channel length, 100 nm gate width, 6 nm-thick silicon film and 1 nm-thick gate oxide. The channel is intrinsic; the source/drain regions are highly n-type doped and the doping profile in these regions is uniform. The transition between the channel and the highly–doped source/ drain regions is characterized by an abrupt doping profile. JL-DGFET have the same geomet‐ rical dimensions, but the silicon film is uniformly n-type doped at 1019 cm-3. In this device there are no highly-doped source/drain regions, as shown in Fig. 1(a). In addition, the channel thickness has to be sufficiently small in order to make possible the complete depletion of the silicon film and to be able to cut-off the device [29]. This condition is satisfied for the doping level and the film thickness considered here. The two gates are connected together in IM-DGFET and JL-DGFET. The silicon film in FDSOI devices has the same geometrical parameters and doping profiles as the silicon film of IM-DGFET. However, only a single gate controls the electrostatic potential and the current flow in the film of FDSOI. A 10 nm-thick buried oxide and a thick silicon substrate lowly-doped at 1016 cm-3 have been also considered in FDSOI. The very thin buried oxide is necessary to minimize the short channel effects in these devices. All devices were calibrated to meet the requirements of the ITRS Low Power technology node corresponding to the year 2015 [5]. To facilitate comparison, the gates work function has been refined to achieve the same off-state current (IOFF) for all devices.

## **2.2. Simulation models**

In the present work, we investigated by 3-D numerical simulation the sensitivity to singleevent of JL-DGFET and we compared the JL-DGFET behavior with that of more conventional inversion-mode devices, IM-DGFET and FDSOI. The effect of an ion strike on the main internal electrical parameters inside the structure (potential and carrier density) and on the drain current transient is investigated. JL-DGFET is compared with IM-DGFET and FDSOI in terms of collected charge and bipolar amplification. The impact on the transient response of several parameters of the ion track (such as the characteristic time and the track radius), as well as of the position of the ion strike along the channel and of the film doping level is addressed. Our simulations show that JL-DGFET may be more resistant to heavy-ion radiation (i.e. may have a lower bipolar gain) than IM-DGFET and FDSOI for some particular configurations (specific ion LET values and ion-impact locations along the channel between the source and drain

The chapter is organized as follows. In section 2 we describe in detail the simulated devices and the simulation models used in this work. The static operation of JL-DGFET, IM-DGFET and FDSOI is presented in section 3. The transient response of JL-DGFET for ions striking in the middle of the channel (at equal distance from the source and drain contacts) is detailed in section 4. In particular, we compare JL-DGFET, IM-DGFET and FDSOI in terms of electron density, electrostatic potential, drain current transient and bipolar amplification. Section 5 addresses the impact of heavy-ion track parameters (ion track characteristic time, track radius and ion strike location between source and drain contact) on the JL-DGFET transient response. The JL-DGFET behavior is systematically compared with that of IM-DGFET and FDSOI structures. Finally, section 6 presents the influence of the silicon film doping level on the bipolar

Figure 1 shows the schematic 3-D description of the simulated devices. Planar IM-DGFET structures are based on real devices reported in [40]. These devices are designed with 20 nm channel length, 100 nm gate width, 6 nm-thick silicon film and 1 nm-thick gate oxide. The channel is intrinsic; the source/drain regions are highly n-type doped and the doping profile in these regions is uniform. The transition between the channel and the highly–doped source/ drain regions is characterized by an abrupt doping profile. JL-DGFET have the same geomet‐ rical dimensions, but the silicon film is uniformly n-type doped at 1019 cm-3. In this device there are no highly-doped source/drain regions, as shown in Fig. 1(a). In addition, the channel thickness has to be sufficiently small in order to make possible the complete depletion of the silicon film and to be able to cut-off the device [29]. This condition is satisfied for the doping level and the film thickness considered here. The two gates are connected together in IM-DGFET and JL-DGFET. The silicon film in FDSOI devices has the same geometrical parameters and doping profiles as the silicon film of IM-DGFET. However, only a single gate controls the electrostatic potential and the current flow in the film of FDSOI. A 10 nm-thick buried oxide

contacts).

amplification in JL-DGFET.

230 Computational and Numerical Simulations

**2. Simulation details**

**2.1. Description of the simulated devices**

Numerical simulations in 3 dimensions (3-D) were carried out with the DESSIS module of the commercial simulator Synopsis [41]. We considered in the simulation physical models such as Shockley-Read-Hall (SRH) and Auger recombination models, as well as the Fermi-Dirac carrier statistics. In the SRH recombination model, carrier lifetimes depend on the doping level [41-43]. The model of the effective intrinsic density includes a doping-dependent band-gap narrowing (Slotboom's model [41]) and a lattice temperature-dependent band gap. The carrier transport model used in the simulation is the hydrodynamic model which includes the energy balance equations for electrons, holes and lattice. We also used models for impact ionization and carrier mobility depending on the carrier energy calculated by the hydrodynamic model. The mobility model also takes into account the dependence of mobility with normal electric field (through the Lombardi's model [41]), temperature and channel doping. The physical parameters of the models used in the simulation (in particular the carrier mobility) are not calibrated on experimental data, but realistic values are considered in the simulation. The parameters and models chosen in this way were then used for the simulation of drain current transients induced by the energetic particle striking the sensitive area of the device. The transistors were simulated in the off-state (most sensitive case) under VG=0 V and VD=0.75 V.

Transient simulations have been performed considering an ion track with a Gaussian shape and a very narrow radius of 20 nm, in order to facilitate comparison with experimental and simulation results reported in references [35] and [44]. In addition, we performed in section 5.2 simulations with different track radii in order to discuss the influence of the track radius on the radiation sensitivity of the three devices simulated here. The ion track has a Gaussian time dependence centered on t=10 ps, with a characteristic time of 2 ps. We chose this charac‐ teristic time value because a good agreement was obtained in a previous study [35] between the simulation and experimental data. However, it is clear that, if we change the characteristic time of the Gaussian distribution, the transient current will be modified. Nevertheless, it is not sure that the radiation resistance of the device and its bipolar amplification will change. To clarify this point, additional simulations with different characteristic time will be presented in section 5.1. The linear energy transfer (LET) value is kept constant along the ion track; this is justified by the very short ion-track length (equal to the silicon film thickness, 6 nm).

The ion strikes the device in a vertical incidence perpendicular to the gate, as shown in Fig. 1. In a first step, we considered that the ion strikes in the middle of the channel (at equal distance from the source and drain contacts). In a second step, we will consider several locations for the ion impact between the source and the drain, in order to investigate the sensitivity of the device to the ion strike position (section 5.3). In most cases the ion track is not entirely contained in the active area of the device, which requires accurately calculating the charge deposited by

obtained by calculating the ratio between the collected and the deposited charges. The bipolar amplification is a key-parameter that characterizes the device sensitivity to ionizing particles,

Investigation of Sensitivity to Heavy-Ion Irradiation of Junctionless Double-Gate MOSFETs by 3-D Numerical Simulation

The simulated steady-state drain current characteristics of JL-DGFET, IM-DGFET and FDSOI are plotted in Fig. 2. The three devices have the same off-state current, but different subthres‐ hold swings and on-state currents. While Double-Gate devices (both JL-DGFET and IM-DGFET) have near ideal subthreshold swings (65 mV/dec), FDSOI has a much higher subthreshold swing (90 mV/dec) because the single-gate configuration reduces the control by the gate of the channel potential and increases the parasitic short-channel effects compared to a double-gate configuration. The highest on-state current is obtained in IM-DGFET, due to the combination of a double-gate structure and an intrinsic channel; this structure has the advantage to maximize the carrier mobility. In JL-DGFET the highly-doped silicon film degrades the mobility and then, the on-state current is the lowest in spite of a double-gate configuration. The on-state current in FDSOI is situated between those of IM-DGFET and JL-DGFET: it is lower than in IM-DGFET because only a single gate controls the channel, but it is

and gives insights on the radiation-hardness of circuits based on this type of device.

higher than in JL-DGFET since the channel is intrinsic and the mobility is enhanced.

JL-DGFET IM-DGFET FDSOI

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7

**Figure 2.** Drain current as a function of gate voltage for JL-DGFET, IM-DGFET and FDSOI. The gate workfunction for each device has been finely tuned to obtain the same off-state current for all devices. Characteristics simulated for

Gate voltage VG (V)

0

50

100

Drain current (µA)

150

200

http://dx.doi.org/10.5772/57048

233

**3. Static operation**

Drain current (A)

VD=0.75 V.

10-10

10-9

10-8

10-7

10-6

10-5

10-4

10-3

**Figure 1.** Schematic description of the simulated JL-DGFET (a), IM-DGFET (b), and FDSOI (c) structures considered in this work. The doping level distribution in each device is shown and the main geometrical parameters are defined. For a better view, the spacers and isolation oxide are not shown. The position of the ion strike is indicated by the arrow; the ion strikes vertically in the middle of the channel and in a direction parallel to the z axis.

the ion in the device. The deposited charge is then obtained in each case taking into account the Gaussian distribution of the ion track, the 3-D geometry of the silicon film and the exact location of the ion strike. The deposited carriers are rapidly transported (mainly by drift and diffusion mechanisms [37]) and collected by the drain contact. A part of these carriers can be recombined by carrier recombination mechanisms; the deposited charge can also be amplified by bipolar amplification mechanism. This phenomenon is specific to partially-depleted SOI (PDSOI) devices, but also exists in FDSOI [45]-[46] and double-gate transistors [37]. The charge collected at the drain contact, following the ion strike, results in a drain current transient, which is further used to accurately calculate the collected charge (by integrating the drain current on the duration of the transient). The bipolar amplification of the charge deposited by the ion is obtained by calculating the ratio between the collected and the deposited charges. The bipolar amplification is a key-parameter that characterizes the device sensitivity to ionizing particles, and gives insights on the radiation-hardness of circuits based on this type of device.
