**5. Conclusion**

190 Recent Advances in Nanofabrication Techniques and Applications

nm. A thin layer of silicon oxide is used as the etching resist at high temperatures. If the etching time is long, the PSS pattern transforms intocylindrical rods with amaximum height of 700 nm (Figure 14). With the ICP etching process using anNi thin film as the resist layer, an even higher cylindrical rod can be obtained due to the higher etching selective ratio

Hsieh et al. [62] created NPSS via a thermal nanoimprint technique, usingNi as the resist layer. A anti-adhesive layer (1H, 1H, 2H, and 2H-perfluorooctyltrichlorosilane) was coated on the mold, followed by a thin Ni layer. A layer of PMMA was sprayed onto the substrate. The Ni layer on the protrudent mold was peel-off before being transferred to the PMMA, using thermal pressing. NPSS (~0.4 μm depth) was then created via ICP etching. The diameters were 0.4, 0.6, 0.8, 1.0, 2.0, and 3.0 μm, with the corresponding EL intensity of 128.4, 120.2, 109.2, 102.5, 91.6, 90.3, and 69.5 mcd, respectively. In comparison to the unpatterned substrate, the efficiency of the NPSS (0.4 μm) LED was increased by 84.7%.

between the sapphire and the Ni, as shown in Figure 15. [61].

Fig. 13. AFM images of concave NPSS formed using wet etching

Fig. 14. SEM images of convex NPSS formed using wet etching

Fig. 15. SEM images of dry etched cylinder NPSS

Nanotechnology is typically defined as the fabrication of structures under 100 nm. The fabrication of structures between 100 nm~999 nm is referred to as sub-micron technology. However, much literature related to LEDs referring to the sub-micron process as nanotechnology exists. Therefore, this study referred to the nanoimprint as the fabrication of several hundred nanometer structures via the imprint technique, nonetheless indicating that the few hundred-nanometer fabrication process is applicable to the industry. This scale is suitable for the development of the nanoimprint technique because the limitation of optical lithography does not affect it, and the technique is low cost compared to the expensive advanced projection lithography and the electron beam lithography. The LED chip has a 0~10 μm bow and the epitaxy is usually processed under a temperature near 1000C. Because the coefficients of thermal expansion of the substrate and the GaN epitaxial layer are different, the epitaxy process is likely to cause the deformation of the chip. Moreover, due to (a) the cleanness issues, (b) surface defects of the epitaxial layer, and (c) the emphasis on the height of the electrode after the chip process, the imprint process of the entire wafer is rendered difficult. Therefore, the use of a flexible soft mold is crucial.

This article presents the nanoimprinting technique integrated with the conventional LED fabrication process. Due to its low cost, simplicity, easy integration, and the enhancement of the optical efficiency, nanoimprinting has a widespread application in various industries. The future business aspect of nanoimprint technology is dependent on the development of manufacturing equipment suitable for LEDs fabrication.
