**1. Introduction**

432 Recent Advances in Nanofabrication Techniques and Applications

Beug, M.F.; Knöfler, R.; Ludwig, C.; Hagenbeck, R.; Müller, T.; Riedel, S.; Höhr, T.; Sachse, J.-

Ghaida, R.S.; Torres, G.; Gupta, P. (2011). Single-Mask Double-Patterning Lithography for

Dusa, M.; Arnold, B.; Finders, J.; Meiling, H.; van Ingen Schenau, K.; Chen, A. C. (2008). The

Bencher, C.; Chen, Y.; Dai, H.; Montgomery, W.; Huli, L. (2008). 22nm half-pitch patterning

Wie,Y.; Brainard, R. L.. (2009). Advanced Processes for 193-nm Immersion Lithography

Chiou, T.-B.; Socha, R.; Kang, H.-Y.; Chen, A. C; Hsu, S.; Chen, H.; Chen, L.. (2008). Full-chip

*Proceedings of the SPIE*, Volume 7140, pp. 71401Z, DOI: 10.1117/12.804763 Noelscher, C.; Jauzion-Graverolle, F.; Heller, M.; Markert, M.; Hong, B.-K.; Egger, U.;

Ludwig, C ; Beug, M.F. ; Küsters, K.-H. (2010). Advances in Flash Memories, *Materials* 

Volume 7028, pp. 702810-702810-11, DOI: 10.1117/12.796016

6924, pp. 69244E-69244E-7, DOI: 10.1117/12.772953

USA, December 15-17, 2008, ISSN 8164-2284

52, pp. 571-576

Volume: 24 , Issue:1

Book, ISBN: 0819475572

12, DOI: 10.1117/12.772750

*Science-Poland*, Vol. 28, No. 1. 105-116

*International Electron Devices Meeting Technical Digest*, p.353, San Francisco, CA,

U.; Nagel, N.; Mikolajick, T.; Küsters, K.-H. (2008). Charge cross talk in sublithographically shrinked 32nm Twin Flash memory cells, *Solid-State Electronics Vol.* 

Reduced Cost and Improved Overlay Control, *Semiconductor Manufacturing,*

lithography technology for the 32nm HP and beyond, *Proceedings of the SPIE*,

by CVD spacer self alignment double patterning, *Proceedings of the SPIE*, Volume

pitch/pattern splitting for lithography and spacer double patterning technologies,

Temmler, D. (2008). Double patterning down to k1=0.15 with bilayer resist, *Proceedings of the SPIE*, Proceedings of the SPIE, Volume 6924, pp. 69240Q-69240Q-

193nm optical immersion lithography is approaching its minimum practical single-exposure limit of 80nm pitch [1]. The semiconductor industry has adopted double patterning technology (DPT) as an attractive solution for the low k1 regime until extreme ultraviolet (EUV) lithography becomes commercialized. DPT also brings additional demands of increased critical dimension uniformity (CDU) and decreased overlay errors. The International Technology Roadmap for Semiconductors (ITRS) [2] target for overlay control at the 32nm DRAM node in single patterned lithography steps is 6nm. The process budget is reduced to 1.1nm for DPT. If 20% of the process error budget is allowed to occur in the metrology tool, as the ITRS states, then the measurement error budget at the 32nm node is 1.2nm for single patterning, and 0.22nm for DPT.

The ITRS defines total measurement uncertainty (TMU) for overlay only in terms of precision, tool-induced shift (TIS) variation and site-to-site tool matching differences. Determining whether a measurement technology is capable of controlling these advanced processes is no longer a case of simple data self-consistency checks on precision, TIS and matching. For example, the error arising from assumptions of a linear change of overlay error with position is significant. This error can be reduced by using very small targets [3] and performing in-device overlay measurements, but the demanding sub-nanometer measurement budget in overlay measurements still remains a considerable challenge.

Recent advances in lithography metrology for advanced patterning have led to the proposal of three different pitch splitting technologies [Fig. 1]. The Litho-Etch-Litho-Etch method (LELE, Fig. 1a) involving two process steps requires very tight overlay control and is both very expensive and slow, making alternative methods attractive. The first alternative process flow is Litho-Freeze-Litho-Etch (LFLE), which reduces the processing cost by replacing the intermediate etch step with a process step in the litho track (Fig. 1b). After exposing the first pattern, the resist is baked in a post-exposure bake (PEB) step and developed. Exposed pattern is coated with material to freeze the resist. The second resist layer is added and the second exposure is done. The freezing material prevents the first resist layer from washing away during the second layer PEB and develop steps. This

Diffraction Based Overlay Metrology for Double Patterning Technologies 435

wave analysis (RCWA) regression approach to calculate the overlay error [9]. W. Yang *et al.* [10] and D. Kandel *et al.* [11] used arrays of specially constructed pads with programmed offsets to determine overlay without the need for model fitting. These DBO methods have the potential to meet the demanding overlay metrology budget for sub-32nm technology nodes. In this chapter, the advantages of DBO for precise and accurate overlay measurement

Spectroscopic scatterometry is used to measure overlay errors between stacked periodic structures (*e.g.,* gratings). In this technique, broadband linearly polarized light is incident perpendicular to the wafer surface and the zero-order diffracted signal (spectrum) is measured as a function of wavelength. Fig. 2 shows a typical experimental configuration. At normal incidence, different reflectance spectra are obtained for various angles of polarization with respect to that of the periodic structure. Typical data collection involved both TE and TM spectra. A specific advantage of using polarized light is that it provides enhanced sensitivity as both the amplitude and phase differences between the TE and TM

(a) (c) Fig. 2. The figure shows a typical hardware set up for a normal incidence scatterometer (a) spectroscopic reflectometry, (b) normal incidence reflection, and (c) TE TM data acquisition

Spectra are obtained from pads, each of which has gratings patterned in both layers between which the overlay error is being measured (Fig. 3). The gratings in each pad are overlaid but by design shifted with respect to each other. Spectra from pads with shifts of equal

magnitude but opposite direction are identical due to symmetry:

(b)

in LELE, LFLE and SADP processes will be shown.

**2. Spectroscopic scatterometry** 

**2.1 Experimental setup** 

spectra can be measured.

modes.

**2.2 Theory** 

technique allowed printing 2D logic cells and dense poly lines with two lithography steps, illustrating good resolution and process margin [4].

The next alternative process is Self-Aligned Double Patterning (SADP, Fig. 1c), in which a spacer film is formed on the sidewalls of pre-patterned features. Etching removes all the material of the original pattern, leaving only the spacer material. Since there are two spacers for every line, the line density has now doubled. The spacer approach is unique in that with one lithographic exposure the pitch can be halved indefinitely with a succession of spacer formation and pattern transfer processes. The spacer film deposition process is very uniform and results in extremely good SADP CDU of less than 1nm. The spacer lithography technique has most frequently been applied in patterning fins for FinFETs and metal layers [5].

Fig. 1. Various double patterning schemes: (a) Litho-etch-litho-etch (LELE), (b) Litho-freezelitho-etch (LFLE), and (c) Self-aligned double patterning (SADP)

These pitch splitting double patterning techniques not only involve more demanding process steps, they also require tighter overlay control than conventional single patterning [2]. Therefore measurement of overlay with much higher certainty is a necessity. As technology transitions toward the 22nm and 16nm nodes using these methods there is serious concern about the capability of the available metrology solutions, both in process development and production control.

High TIS and tool-to-tool matching errors make it difficult to meet the measurement uncertainty requirements using the traditional Image-Based Overlay method (IBO), even though most advanced IBO tools are operating at TMU levels under 1nm. Diffraction-based (scatterometry) overlay (DBO) measurement is an alternative optical measurement technique that has been reported to offer better precision than IBO and near zero TIS [6, 12, 14-15], and is therefore a possible solution to the measurement uncertainty budget. Bischoff *et al.* proposed measuring overlay using the diffraction efficiencies of the first diffracted orders [7]. Chun-Hung Ko used angular scatterometry combined with an experimental library to determine the overlay error on ADI stacks with intermediate poly-silicon lines [8]. H.-T. Huang *et al.* used spectra from reflection symmetry gratings and a rigorous coupledwave analysis (RCWA) regression approach to calculate the overlay error [9]. W. Yang *et al.* [10] and D. Kandel *et al.* [11] used arrays of specially constructed pads with programmed offsets to determine overlay without the need for model fitting. These DBO methods have the potential to meet the demanding overlay metrology budget for sub-32nm technology nodes. In this chapter, the advantages of DBO for precise and accurate overlay measurement in LELE, LFLE and SADP processes will be shown.
