**4.4 Conclusion**

90 Recent Advances in Nanofabrication Techniques and Applications

(a) Area versus timing constraint

5.8 6.2 6.6 7.0 7.4 7.8 8.2 8.6 9.0 Timing constraint [ns]

α=1,β=0 α=0,β=1

=1,=0 =0,=1

120,000 130,000 140,000 150,000 160,000 170,000 180,000 190,000 200,000

30,000 40,000 50,000 60,000 70,000 80,000 90,000 100,000

The number of EB shots

Area [a.u.]

Fig. 16. Area and the number of EB shots with the LP cell library under timing constraints

(b) The number of EB shots versus timing constraint

5.8 6.2 6.6 7.0 7.4 7.8 8.2 8.6 9.0 Timing constraint [ns]

Our technology mapping technique for the CP lithography achieved a 54.6% less number of EB shots with 8.4% area increase under no timing constraints than the conventional one. Our technology mapping for the CP lithography also achieved a 26.6% less number of EB shots with 41.1% area increase and without any performance degradation than the conventional one. Varying the ratio /, we found that there exists a tradeoff between area and the number of EB shots.

In the other experiments, tightening timing constraint increased area and the number of EB shots. It was found that there exists a tradeoff between delay time and the number of EB shots. We think that a timing constraint for shorter delay time has caused a logic synthesis tool to choose the off-characters cell functions that have higher current drivability.

Our technology mapping technique reduced the number of EB shots to project patterns for the FEOL with some area increase. It is probable that some increase of cell instances causes the number of wires to increase and does the number of EB shots for projecting the BEOL patterns to increase. A technology mapping technique should be studied for reducing the number of EB shots required for both the FEOL and the BEOL patterns as future work.

The number of cell functions which are placed on a CP aperture mask will increase as the technology node proceeds. It is probable that all cell functions of a commercial cell library, which includes more than 500 cell functions, will be placed on a single CP aperture mask at the 32 nm technology node. This indicates that the VSB lithography will be required less and less for projecting such cell functions. We suppose that our technology mapping technique is effective before the 32 nm technology node. We think that another technology mapping technique will be needed to increase throughput of MCC systems after the 32 nm technology node.

It is easy for both IC designers and equipment developers to adopt our technology mapping technique because a software approach such as our technique imposes no modification on CP equipment. This means that no additional cost is necessary to adopt our technique in their IC design.
