**3.2 Fan-out**

428 Recent Advances in Nanofabrication Techniques and Applications

margin require some kind of so called landing pad, i.e. a local enlargement (landing pad) of the bit line around the bit line contact. This is only feasibly by LBF, since only in the LBF, the layouter can intentionally modify the width of the bit line. The LBS would ascribe the bit

> WC BLh70 WC Double Pat 36-36-36 BC Double Pat BC BLh50 WC BLh70 WC Double Pat 36-36-36 BC Double Pat

Fig. 13. Bit line capacitance in a 36nm flash M0 layer for the extreme 3 sigma cases of double patterning variations, marked by the red boxes, and in addition bit line height variations of

(10-10 F/m) LBF (%)

Metal Dummy Contact Pad

Line

LBF

WC incl. BL height (3 ) 2,61 17 2,61 17 WC (double patt. only) (3 ) 2,54 14 2,55 14 Target dimension 2,23 0 2,23 0 BC (double patt. only) (3 ) 1,97 -12 2,01 -10 BC incl. BL height (3 ) 1,90 -15 1,93 -14 Table 3. Bit line capacitance (numbers absolute and relative to the geometrical target dimensions) for LBF and LBS. All variations represent 3 sigma values. The range between the largest, i.e. worst case (WC) capacitance and the lowest, i.e. best case (BC) capacitance is roughly identical for both double patterning schemes. Besides the pure double patterning effects, the table also considers a calculation of the bit line height variations. Altogether, the

two double patterning schemes do not exhibit a significant difference.

Core Line Fill Line

Fig. 14. LBF allows local enlargements of the bit line width.

**Contributions to bitline capacitance (F/m)**

BC BLh50 next neighbor (left) next neighbor (right)

2nd neighbor (left) 2nd neighbor (right) 3rd neighbor (left) 3rd neighbor (right) Bottom Capacitance Top Capacitance

0,0E+00 5,0E-11 1,0E-10 1,5E-10 2,0E-10 2,5E-10 3,0E-10

1,18E-10 1,06E-10 9,23E-11 8,11E-11 7,21E-11

1,38E-10 1,24E-10 9,23E-11 8,13E-11 7,22E-11

LBS

(10-10 F/m) LBS (%)

1,18E-10 1,06E-10 9,23E-11 8,11E-11 7,21E-11 1,03E-10 9,29E-11 9,23E-11 8,13E-11 7,22E-11

lines a well-defined, fixed width.

**WC-BLh70 WC-pitchfrag 36-36-36 BC-pitchfrag BC-BLh50 WC-BLh70 WC-pitchfrag 36-36-36 BC-pitchfrag BC-BLh50**

**Line** 

**Line by**

+/- 10nm.

**by Fill**

**Spacer**

**46.10 46.10 36.00 25.90 25.90 0.00**

> **36.00 41.10 41.10**

**35.90 35.90**

**Line-space configuration (nm)**

**30.90 30.90 36.00 41.10 41.10 41.10 41.10 36.00 30.90 30.90**

**0.00 36.00 72.00 108.00 144.00**

**bad CD spacer CD good CD spacer CD**

secondary line spacer primary line spacer

**36.10 36.10 36.00 35.90 35.90 25.90 25.90 36.00 41.10 41.10**

**30.90 30.90 36.00 41.10 41.10 41.10 41.10 36.00 30.90 30.90** So far, we have focussed our discussion mainly on the regular array. The edge of the array deserves special attention.

Self-aligned double patterning naturally creates lines or spaces which are connected pairwise. In general, this is not desired. Therefore after the array formation by double patterning, the edge of the array is cut by applying a second uncritical litho & etch step, as illustrated in figure 15. Preferably, this step is applied to the hard mask before etching the full stack.

Fig. 15. An uncritical litho & etch step is used to remove the unintended pair-wise connections of the double patterning lines.

The array lines have to be connected electrically to other functional elements on the chip. This requires a so-called fan-out, a topological connection between the double patterning elements and the structures printed by direct lithography.

A possible process sequence of a "Christmas tree" fan-out for the gate layer of a NAND flash is shown in figure 16. The ends of the lines formed by primary lithography are drawn in a shape as depicted in figure 16 (a). The first lithography step prints the primary lines, having twice the array pitch, and forms the fan-out core. The spacer covering the sidewalls of the primary lines follows the core edges and routes each array line into the Christmas tree fan out (figure 16 (b)). The spacer has the intended pitch within the array and is transformed into array lines. They are connected in pairs. Therefore an additional (uncritical) litho & etch cut step must be performed (figure 16 (c)). Finally, landing pads are added for better overall process robustness (figure 16 (d)). The additive structuring requires one more litho & etch, which is usually combined with the periphery patterning. For the additive structuring, the combination of the already formed double patterning hard mask and the add-on photo resist act as an etch mask for the final etch.

A SEM photography of such a "Christmas tree" word line fan-out is given in figure 17.

Double Patterning for Memory ICs 431

Fig. 17. SEM view of a word line (gate) fan-out for a 36nm half pitch array.

lithography is still on its way towards production maturity.

36nm NAND flash as an example, process flows have been presented.

the Federal Republic of Germany (project nos. 01M3167 A and 01M3171 A).

Double Patterning has become an important technique for advanced microelectronics devices. Cost-competitive memory chips have structure dimensions which are well below the diffraction limit of any available productive lithography tool. The generation EUV

We have shown a classification of double patterning and have discussed possible implementations. Their specific challenges and advantages have been considered. For a

This work was financially supported in part by the European Commission in the projects GOSSAMER and PULLNANO, and by the Federal Ministry of Education and Research of

The authors would like to express their gratitude to the whole flash development team of

Beug, M.F.; Hoehr, T.; Müller, T.; Reichelt, R.; Müller-Meskamp, L.; Geiser, P.; Geppert, T.;

Bach, L.; Bewersdorff-Sarlette, U.; Kenny, O.; Olligs, D.; Brandl, S.; Marschner, T. ; Parascandola, S.; Meyer, S.; Riedel, S .; Specht, M.; Manger, D.; Knöfler, R.; Knobloch, K.; Kratzert, P.; Ludwig, C. & Küsters, K.-H. (2008). Pitch Fragmentation Induced Odd/Even Effects in a 36nm Floating Gate NAND Technology,

the former company Qimonda, especially Tim Höhr for the capacitance simulations.

**4. Conclusion** 

**5. Acknowledgment** 

**6. References** 

Fig. 16. "Christmas tree" fan-out for the gate layer of a NAND flash.

(a)

(b)

(c)

(d)

After Core Etch and Spacer Formation

After Periphery and Landing Pad Additive Structuring

After Periphery and Landing Pad Additive Structuring

Fig. 16. "Christmas tree" fan-out for the gate layer of a NAND flash.

Mask Layout

Fig. 17. SEM view of a word line (gate) fan-out for a 36nm half pitch array.
