**3.1.3 Active area / STI**

For the active area, the following elements are relevant:


The balance of the mentioned three arguments led the authors to the decision of LBF (line by fill) for the active area layer.

### **3.1.4 Bit line contact**

NAND-Flash memory arrays require single rows of so called dense bit line contacts. They connect the metal bit lines to the active area, and they are following the critical pitch. The special challenge consists in the lack of any room for overlay tolerances and in the extreme asymmetry of the pattern: the contact row can be considered an isolated structure in one dimension, and in the orthogonal dimension a periodic structure with minimum pitch.

Double Patterning for Memory ICs 427

Fig. 11. Electric field simulations for bit line capacitance calculations, depicted for the LBF

It is not upfront clear by intuition, which combination of double patterning variations will result in the largest and lowest bit line capacitance, respectively. For example, in the LBS scheme, the smallest bit line capacitance does not occur for the largest primary space. The reason is the linear (inter-)dependence of the four parameters: The sum of two spaces and two lines is fixed to twice the pitch, 144 nm in our example. An illustration of the line / space variations towards lower capacitances is given in figure 12. The lowest possible value for LBS (3 sigma geometrical variations assumed) is 2,01 x 10-10 F/m, which is 10% below the

x100nm 3 2 1 0 -1 -2

x100nm 3 2 1 0 -1 -2


value of the target geometry (2,23 x 10-10 F/m).

**Wafer BC: Line-space configuration (nm)**

0.00 36.00 72.00 108.00 144.00

good space line 1 bad space line 2

primary space line 1 secondary space line 2

considerations is a tiny preference for the LBS scheme.

36.00 46.10 44.10 41.10 39.70 36.00 34.00 25.90 46.10 46.10 46.10

36.00 30.90 30.90 30.90 30.90 32.75 33.75 37.80 34.20 32.45 30.95

found to be the best case, resulting in a total capacitance of 2,01 x 10-10 F/m.

36.00 30.90 30.90 30.90 30.90 32.75 33.75 37.80 34.20 32.45 30.95

36.00 36.10 38.10 41.10 42.50 42.50 42.50 42.50 29.50 33.00 36.00

36-36 36.1-46.1 38.1-44.1 41.1-41.1 42.5-39.7 42.5-36 42.5-34 42.5-25.9 29.5-46.1 33-46.1 36-46.1

x100nm 3 2 1 0 -1 -2

process.


**Contributions to bitline capacitance (F/m)**

0.0E+00 5.0E-11 1.0E-10 1.5E-10 2.0E-10 2.5E-10

9.23E-11 7.30E-11 7.61E-11 8.13E-11 8.39E-11 9.19E-11 9.69E-11 1.23E-10 7.33E-11 7.31E-11 7.30E-11

next neighbor (left) next neighbor (right) 2nd neighbor (left) 2nd neighbor (right) 3rd neighbor (left) 3rd neighbor (right) Bottom Capacitance Top Capacitance

9.23E-11 9.15E-11 8.71E-11 8.13E-11 7.88E-11 7.90E-11 7.91E-11 7.94E-11 1.10E-10 9.93E-11 9.17E-11

36-36 36.1-46.1 38.1-44.1 41.1-41.1 42.5-39.7 42.5-36 42.5-34 42.5-25.9 29.5-46.1 33-46.1 36-46.1

Fig. 12. Bit line capacitance for various extreme geometry parameters in the LBS scheme, for lowest capacitances from process variations ("best case"). A totally symmetric configuration of 41.1 nm for both the primary and the secondary space and a line width of 30.9 nm is

A summary of the results is depicted in figure 13 and listed in table 3. The outcome of the

The feasibility of process architecture finally requires a clear decision between the two double patterning schemes. A reliable connection to the bit line contact and a robust process

Fig. 10. A two-mask process for the formation of a single row of on-pitch contacts.

Figure 10 shows one example how to realize elongated dense bit line contacts. In a first step a dense array-like hard mask is created by double patterning. The lines and spaces of this array-like hard mask define the bit line contact widths and the contact to contact distances, respectively. The array is much larger than the intended contacts in order to reach a good imaging in the lithography tool. A second lithography layer is used to cut out only a small region of the array-like hard mask. This second litho step prints a long opening in a resist mask across the array-like hard mask. The width of this long opening defines the length of the contacts. The following etch process is to open only the regions which are neither covered by the spacer nor by the photo resist.

### **3.1.5 Tight pitch metal layer**

The predominant issues for the selection of the proper double patterning scheme for metallization are


Typically, bit lines are supposed to run fast electrical signal pulses with lowest possible loss and lowest possible cross-talk. This requirement suggests that a lower limit of the metal space might be important in order to minimize RC losses. Simulations have been performed for the bit line capacitance in a flash memory for both the LBF (line by fill) and the LBS (line by space) process scheme. The results led to the conclusion that both LBS and LBF show nearly identical variations with respect to the capacitive coupling between adjacent bit lines. The resistivity variations, however, are clearly in favour of the LBS scheme, which has a well controlled metal line width, i.e. the resistance tolerances are much better than for LBF. But in the end, deeper study of process architecture and complexity and cost led to the decision of LBF.

Two-dimensional electric field and capacitance simulations have been performed for LBF (figure 11) and LBS. The calculations include fringing fields for up the third neighbour bit line as well as the capacitance to the top and bottom layers of the chip. Worst and best cases, i.e. largest and lowest capacities have been calculated. For the variations, not only the double patterning induced line and space variations have been considered, but also variations in bit line thickness. The target thickness of the considered example is 60nm for the full metal stack, the tolerance is +/- 10nm.

Fig. 10. A two-mask process for the formation of a single row of on-pitch contacts.

Figure 10 shows one example how to realize elongated dense bit line contacts. In a first step a dense array-like hard mask is created by double patterning. The lines and spaces of this array-like hard mask define the bit line contact widths and the contact to contact distances, respectively. The array is much larger than the intended contacts in order to reach a good imaging in the lithography tool. A second lithography layer is used to cut out only a small region of the array-like hard mask. This second litho step prints a long opening in a resist mask across the array-like hard mask. The width of this long opening defines the length of the contacts. The following etch process is to open only the regions which are neither

The predominant issues for the selection of the proper double patterning scheme for


Typically, bit lines are supposed to run fast electrical signal pulses with lowest possible loss and lowest possible cross-talk. This requirement suggests that a lower limit of the metal space might be important in order to minimize RC losses. Simulations have been performed for the bit line capacitance in a flash memory for both the LBF (line by fill) and the LBS (line by space) process scheme. The results led to the conclusion that both LBS and LBF show nearly identical variations with respect to the capacitive coupling between adjacent bit lines. The resistivity variations, however, are clearly in favour of the LBS scheme, which has a well controlled metal line width, i.e. the resistance tolerances are much better than for LBF. But in the end, deeper

Two-dimensional electric field and capacitance simulations have been performed for LBF (figure 11) and LBS. The calculations include fringing fields for up the third neighbour bit line as well as the capacitance to the top and bottom layers of the chip. Worst and best cases, i.e. largest and lowest capacities have been calculated. For the variations, not only the double patterning induced line and space variations have been considered, but also variations in bit line thickness. The target thickness of the considered example is 60nm for

study of process architecture and complexity and cost led to the decision of LBF.

2) Second Litho (contact length) 3) final Bit-Line Contact

1) Double patterning hard mask after Spacer, Fill & Recess

covered by the spacer nor by the photo resist.

the full metal stack, the tolerance is +/- 10nm.

**3.1.5 Tight pitch metal layer** 



beyond or beneath.


metallization are

Fig. 11. Electric field simulations for bit line capacitance calculations, depicted for the LBF process.

It is not upfront clear by intuition, which combination of double patterning variations will result in the largest and lowest bit line capacitance, respectively. For example, in the LBS scheme, the smallest bit line capacitance does not occur for the largest primary space. The reason is the linear (inter-)dependence of the four parameters: The sum of two spaces and two lines is fixed to twice the pitch, 144 nm in our example. An illustration of the line / space variations towards lower capacitances is given in figure 12. The lowest possible value for LBS (3 sigma geometrical variations assumed) is 2,01 x 10-10 F/m, which is 10% below the value of the target geometry (2,23 x 10-10 F/m).

Fig. 12. Bit line capacitance for various extreme geometry parameters in the LBS scheme, for lowest capacitances from process variations ("best case"). A totally symmetric configuration of 41.1 nm for both the primary and the secondary space and a line width of 30.9 nm is found to be the best case, resulting in a total capacitance of 2,01 x 10-10 F/m.

A summary of the results is depicted in figure 13 and listed in table 3. The outcome of the considerations is a tiny preference for the LBS scheme.

The feasibility of process architecture finally requires a clear decision between the two double patterning schemes. A reliable connection to the bit line contact and a robust process

Double Patterning for Memory ICs 429

In an NAND flash, the regular bit line pattern exhibits periodic interruptions which are needed for the source line contacts. This enables the introduction of some dummy extra bit lines. They are used to allow tiny landing pads on top of the bit line contacts. Figure 14

So far, we have focussed our discussion mainly on the regular array. The edge of the array

Self-aligned double patterning naturally creates lines or spaces which are connected pairwise. In general, this is not desired. Therefore after the array formation by double patterning, the edge of the array is cut by applying a second uncritical litho & etch step, as illustrated in figure 15. Preferably, this step is applied to the hard mask before etching the

b) uncritical array edge

c) final array pattern

litho

Fig. 15. An uncritical litho & etch step is used to remove the unintended pair-wise

The array lines have to be connected electrically to other functional elements on the chip. This requires a so-called fan-out, a topological connection between the double patterning

A possible process sequence of a "Christmas tree" fan-out for the gate layer of a NAND flash is shown in figure 16. The ends of the lines formed by primary lithography are drawn in a shape as depicted in figure 16 (a). The first lithography step prints the primary lines, having twice the array pitch, and forms the fan-out core. The spacer covering the sidewalls of the primary lines follows the core edges and routes each array line into the Christmas tree fan out (figure 16 (b)). The spacer has the intended pitch within the array and is transformed into array lines. They are connected in pairs. Therefore an additional (uncritical) litho & etch cut step must be performed (figure 16 (c)). Finally, landing pads are added for better overall process robustness (figure 16 (d)). The additive structuring requires one more litho & etch, which is usually combined with the periphery patterning. For the additive structuring, the combination of the already formed double patterning hard mask and the add-on photo

A SEM photography of such a "Christmas tree" word line fan-out is given in figure 17.

shows an example for bit line landing pads.

a) double patterning formation

connections of the double patterning lines.

resist act as an etch mask for the final etch.

elements and the structures printed by direct lithography.

**3.2 Fan-out** 

full stack.

deserves special attention.

margin require some kind of so called landing pad, i.e. a local enlargement (landing pad) of the bit line around the bit line contact. This is only feasibly by LBF, since only in the LBF, the layouter can intentionally modify the width of the bit line. The LBS would ascribe the bit lines a well-defined, fixed width.

Fig. 13. Bit line capacitance in a 36nm flash M0 layer for the extreme 3 sigma cases of double patterning variations, marked by the red boxes, and in addition bit line height variations of +/- 10nm.


Table 3. Bit line capacitance (numbers absolute and relative to the geometrical target dimensions) for LBF and LBS. All variations represent 3 sigma values. The range between the largest, i.e. worst case (WC) capacitance and the lowest, i.e. best case (BC) capacitance is roughly identical for both double patterning schemes. Besides the pure double patterning effects, the table also considers a calculation of the bit line height variations. Altogether, the two double patterning schemes do not exhibit a significant difference.

Fig. 14. LBF allows local enlargements of the bit line width.

In an NAND flash, the regular bit line pattern exhibits periodic interruptions which are needed for the source line contacts. This enables the introduction of some dummy extra bit lines. They are used to allow tiny landing pads on top of the bit line contacts. Figure 14 shows an example for bit line landing pads.
