**3.1 DPT structures for testing DBO**

The first DPT test structure is on a silicon substrate (fig 7a). The structure consists of ~120 nm photoresist lines and ~40 nm nitride lines with silicon over etch. The second DPT stack (Fig. 7b) comes from a gate (bitline)-level patterning step in a NOR flash process.

Fig. 7. (a) DPT test structure with ~120 nm photoresist lines and ~40 nm nitride lines with silicon over etch on a silicon substrate. (b) Gate level (bitline) patterning step in a NOR flash process.
