**3. Self aligned double patterning**

The second main stream is often called self aligned double patterning. Some people call this technique pitch fragmentation and you might often hear spacer based double patterning, because for most of this techniques spacer-like approaches are used to double the number of features.

Self aligned double pattering comes with strong layout limitations. However, it is well suited for regular patterns e.g. of memory chips. The design process is more complex than LELE and the pattern on the photo masks look different compared to the final pattern. This creates a first challenge, because layout versus schematic checks require additional CAD tooling to transform the self aligned double patterning mask data into the final layout data. The transformation in the other direction – from final layout to double patterning layout – is even more challenging. Automated tools are rare and manual interaction of the designers is required. This is limiting the application to a manageable number of layout features and is the main reason why self aligned double patterning is mostly only used by memory manufactures.

The big advantage of self aligned double patterning is that only one main feature lithography step has to be done. However, one or two additional assist lithography steps with considerably reduced resolution requirements are used to form the edges of the regular pattern within the memory array as well as the transition from the regular array towards the remaining area of the chip, containing the control function elements of the memory.

The lithography tool overlay requirement is only driven by the inter-layer technology demands and not by the intra-layer alignment as for LELE.

Double Patterning for Memory ICs 421

with an aspect ratio of typical 1:3 to 1:5 is formed. This can be done directly in the photo resist system, or - more common – can be transferred by reactive ion etch into a relative thick underlying hard mask. Afterwards a thin conformal liner will be deposited onto the core shape. Now a spacer etch is performed and the core pattern gets stripped out. Finally the spacer structures will be transferred into another under laying thin hard mask and the spacer will be taken off as well. Figure 4 and 5 show such a process sequence. A detailed process description including key process parameters is listed in table 1. For this sequence the final line structure width is defined by the deposited thickness of the sacrificial spacer. Therefore this scheme is called "line by space" (LBS). All created lines will have the width of the sacrificial spacer. There is no degree of freedom for the chip layouter to modify the line

width. Only the space between the lines can be varied by layout.

Litho 193nm immersion 72nm line / 72 nm space

Clean Wet minimum attack of SiON

Etch Recess Poly complete carrier a-Si removal Etch Plasma SiON spacer transfer etch, stop on a-Si

Subtractive Patterning etch SiON selective to a-Si

Etch Wet TEOS high selectivity, minimum attack of SiON

Deposition of CVD carbon hard mask 150nm (should to be adjusted to layer

requirement)

CD uniformity < 3nm

CD uniformity < 2nm

taper within the array: 90 deg

thickness uniformity < 0,5nm

minimum attack of SiON

Additive Patterning etch aSi with SiON and resist mask with stop on SiON Table 1. Process Sequence for Spacer Transfer Scheme (LBS) with process targets for the gate

Some applications however require lines with well-defined different line widths, but can accept equal spaces. This can be realized by a slight modification of the described processing sequence: filling the pattern after the spacer etch followed by a controlled recess etch and spacer material strip. Figure 6 demonstrates an example for a process flow which is called

25nm SiON + 25nm a-Si + 35nm SiON + 150nm a-

Si + 20nm TEOS (from bottom to top)

Process Step Target

Deposition of CVD multi-layer stack (double patterning hard mask)

Strip Resist

Etch Spacer Oxide

"line by fill" (LBF).

layer in a 36nm NAND flash chip.

Anneal carbon 630°C, 60min

Trim etch of poly mask ~ 42nm line

Deposition CVD HARP liner 36nm thickness

Etch Wet Oxide remove space;

Fig. 4. Sketch of a process sequence for "line by space" double patterning.

Fig. 5. Example of a process sequence "line by spacer": The SEM cross section at the top reveals the primary line pattern as defined by lithography, after print and dry etch. The cross section in the middle shows the primary lines now covered by (sacrificial) spacers, after spacer deposition and spacer etch. The bottom picture is taken after removal of the primary lines. The sacrificial spacers have become now a regular pattern of twice the spatial frequency compared to the primary pattern, and can be further used as a hard mask for the subsequent patterning of the desired stacks.

With the main lithography step, a so called "primary" or "core" pattern is printed on the wafer. This pattern has a pitch twice as large as the final structures and gets usually biased for process window reasons. Out of this pattern, a tall rectangular-shaped core structure

1) Litho 2) Trim-Etch 3) Core-Etch 4) Spacer Deposition

5) Spacer Etch 6) Core-Strip 7) Transfer Etch 8) Spacer Strip

Fig. 5. Example of a process sequence "line by spacer": The SEM cross section at the top reveals the primary line pattern as defined by lithography, after print and dry etch. The cross section in the middle shows the primary lines now covered by (sacrificial) spacers, after spacer deposition and spacer etch. The bottom picture is taken after removal of the primary lines. The sacrificial spacers have become now a regular pattern of twice the spatial frequency compared to the primary pattern, and can be further used as a hard mask for the

With the main lithography step, a so called "primary" or "core" pattern is printed on the wafer. This pattern has a pitch twice as large as the final structures and gets usually biased for process window reasons. Out of this pattern, a tall rectangular-shaped core structure

subsequent patterning of the desired stacks.

Fig. 4. Sketch of a process sequence for "line by space" double patterning.

with an aspect ratio of typical 1:3 to 1:5 is formed. This can be done directly in the photo resist system, or - more common – can be transferred by reactive ion etch into a relative thick underlying hard mask. Afterwards a thin conformal liner will be deposited onto the core shape. Now a spacer etch is performed and the core pattern gets stripped out. Finally the spacer structures will be transferred into another under laying thin hard mask and the spacer will be taken off as well. Figure 4 and 5 show such a process sequence. A detailed process description including key process parameters is listed in table 1. For this sequence the final line structure width is defined by the deposited thickness of the sacrificial spacer. Therefore this scheme is called "line by space" (LBS). All created lines will have the width of the sacrificial spacer. There is no degree of freedom for the chip layouter to modify the line width. Only the space between the lines can be varied by layout.


Table 1. Process Sequence for Spacer Transfer Scheme (LBS) with process targets for the gate layer in a 36nm NAND flash chip.

Some applications however require lines with well-defined different line widths, but can accept equal spaces. This can be realized by a slight modification of the described processing sequence: filling the pattern after the spacer etch followed by a controlled recess etch and spacer material strip. Figure 6 demonstrates an example for a process flow which is called "line by fill" (LBF).

Double Patterning for Memory ICs 423

One of the biggest challenges for self aligned double patterning is the control of the critical dimensions. Compared to the traditional litho, when CD control was more or less managed by lithography, self aligned double patterning relies also on tight process control for etch and deposition processes. For the example sequence sketched in figure 4, the line width is defined by the thickness of the deposited (spacer) liner and the subsequent spacer etch. Extremely low process variations, exact reproducibility, uniformity are mandatory. Therefore, special care has to be dedicated to the search of well controlled deposition

The first process choice for a well-controlled deposition process could be LPCVD. However, most of the LPCVD furnace processes require process temperatures above 500°C. Front-end application might allow such temperatures, but in the back-end of line such high temperature would destroy the already manufactured metal lines or contact junctions.

PECVD processes can run at lower temperatures and come with acceptable cost. However, still most of the PECVD deposition processes are not suitable for spacer based double patterning, because the deposition mechanism is transport limited. In other words: the new material deposition reaction is very fast and is limited by how fast and how much new material can be transported out of the plasma to the wafer. The "stream" of new material is limited in time and will be distributed over the wafer surface. As a consequence the thickness of the deposited liner will vary with the surface area. Therefore dense structure areas with larger surface will see thinner liner ticknesses compared to isolated structures. Unfortunately this so-called micro-loading has quite some range and will create dozens of array edge line with different line width. As a result, PECVD processes cannot deliver tight

A highly promising process candidate is atomic layer deposition (ALD). They come with extreme good thickness uniformity and can be done at very low temperatures. The first ALD processes hat the drawback of a relatively slow process speed, resulting in high process cost. However, the original ALD with its slow atom-by-atom like deposition has experienced considerable improvements. Nowadays modified ALD processes are available like e.g. catalytic (fast) ALD, spatial ALD, molecular layer depositions or pulsed plasma depositions. Some of these advanced deposition processes can be done at temperature around or even below 100°C. This enables spacer liner depositions directly on photo resist type core

The liner thickness variations are not the only critical parameter. Also for other process steps, the control of critical dimensions is challenging. The CD variation of the "primary" or "core" space results from both litho and core-etch non-uniformity. The line width variation depends on spacer deposition and etch uniformity. The "secondary" or remaining space in principle will suffer from the sum of both variations. In order to keep the "secondary" or remaining space within the allowed technology variation specifications, one has either to run each process with very tight specifications or to implement an advanced feedforward / feedback APC system. Such a system is capable e.g. of tuning the etch-bias as a function of

The uniformity of the line width is affected by the topography of the environment. There are both short-range effects and long-range effects. Transport processes and reaction kinetics of chemical and plasma reactions are sensitive to the effective surface in the vicinity of a considered line as well as to the macroscopic location on the wafer. In addition to the structure dimension of interest, monitoring structures need to be developed for a fast and

**3.1.1 Process tolerances** 

in-chip CD control.

materials.

processes with reasonable process cost.

Therefore, LPCVD cannot be applied to critical metal layers.

the photo resist CD after the lithography patterning.

reliable monitoring of the mass production.

Fig. 6. Sketch of a process scheme for "line by fill" double patterning.

#### **3.1 Line by space (LBS) – Line by fill (LBF)**

The decision for either of the two basic self-aligned double patterning schemes LBS or LBF has to be taken for each lithography layer individually. In general, LBS is advantageous if the tolerances in line width are most critical for the electrical functionality of the product, and LBF is the preferred option if the distance between the lines are most critical for the product functionality. Figure 7 illustrates this difference. Therefore, sound knowledge of the fabrication process tolerances and thorough simulation are mandatory.

Fig. 7. Critical dimension of the gate hard mask, measured across the full wafer. The left hand graph shows the hard mask spaces, the "space-1", being defined by the primary line, whereas the right hand graph reprents the hard mask "lines", being formed by the sacrificial spacers. The hardmask lines show a much smaller spread in width than the hard mask spaces. Note that the hardmask lines are narrower than the intended gates: this is to compensate for the gate etch bias.

### **3.1.1 Process tolerances**

422 Recent Advances in Nanofabrication Techniques and Applications

Deposition


Feature defined by spacer (nm) 26 25 24 23 22

1) Litho 2) Trim-Etch 3) Core-Etch 4) Spacer

5) Spacer Etch 6) Overfill 7) Recess Etch 8) Spacer Strip

The decision for either of the two basic self-aligned double patterning schemes LBS or LBF has to be taken for each lithography layer individually. In general, LBS is advantageous if the tolerances in line width are most critical for the electrical functionality of the product, and LBF is the preferred option if the distance between the lines are most critical for the product functionality. Figure 7 illustrates this difference. Therefore, sound knowledge of the

mm

100

50

0

 wafer center (y)

Fig. 7. Critical dimension of the gate hard mask, measured across the full wafer. The left hand graph shows the hard mask spaces, the "space-1", being defined by the primary line, whereas the right hand graph reprents the hard mask "lines", being formed by the sacrificial spacers. The hardmask lines show a much smaller spread in width than the hard mask spaces. Note that the hardmask lines are narrower than the intended gates: this is to



Fig. 6. Sketch of a process scheme for "line by fill" double patterning.

fabrication process tolerances and thorough simulation are mandatory.

Feature defined by carrier structure (nm) 50 48 46 44

**3.1 Line by space (LBS) – Line by fill (LBF)** 


compensate for the gate etch bias.

mm 100

50

0

 wafer center (y)



One of the biggest challenges for self aligned double patterning is the control of the critical dimensions. Compared to the traditional litho, when CD control was more or less managed by lithography, self aligned double patterning relies also on tight process control for etch and deposition processes. For the example sequence sketched in figure 4, the line width is defined by the thickness of the deposited (spacer) liner and the subsequent spacer etch. Extremely low process variations, exact reproducibility, uniformity are mandatory. Therefore, special care has to be dedicated to the search of well controlled deposition processes with reasonable process cost.

The first process choice for a well-controlled deposition process could be LPCVD. However, most of the LPCVD furnace processes require process temperatures above 500°C. Front-end application might allow such temperatures, but in the back-end of line such high temperature would destroy the already manufactured metal lines or contact junctions. Therefore, LPCVD cannot be applied to critical metal layers.

PECVD processes can run at lower temperatures and come with acceptable cost. However, still most of the PECVD deposition processes are not suitable for spacer based double patterning, because the deposition mechanism is transport limited. In other words: the new material deposition reaction is very fast and is limited by how fast and how much new material can be transported out of the plasma to the wafer. The "stream" of new material is limited in time and will be distributed over the wafer surface. As a consequence the thickness of the deposited liner will vary with the surface area. Therefore dense structure areas with larger surface will see thinner liner ticknesses compared to isolated structures. Unfortunately this so-called micro-loading has quite some range and will create dozens of array edge line with different line width. As a result, PECVD processes cannot deliver tight in-chip CD control.

A highly promising process candidate is atomic layer deposition (ALD). They come with extreme good thickness uniformity and can be done at very low temperatures. The first ALD processes hat the drawback of a relatively slow process speed, resulting in high process cost. However, the original ALD with its slow atom-by-atom like deposition has experienced considerable improvements. Nowadays modified ALD processes are available like e.g. catalytic (fast) ALD, spatial ALD, molecular layer depositions or pulsed plasma depositions. Some of these advanced deposition processes can be done at temperature around or even below 100°C. This enables spacer liner depositions directly on photo resist type core materials.

The liner thickness variations are not the only critical parameter. Also for other process steps, the control of critical dimensions is challenging. The CD variation of the "primary" or "core" space results from both litho and core-etch non-uniformity. The line width variation depends on spacer deposition and etch uniformity. The "secondary" or remaining space in principle will suffer from the sum of both variations. In order to keep the "secondary" or remaining space within the allowed technology variation specifications, one has either to run each process with very tight specifications or to implement an advanced feedforward / feedback APC system. Such a system is capable e.g. of tuning the etch-bias as a function of the photo resist CD after the lithography patterning.

The uniformity of the line width is affected by the topography of the environment. There are both short-range effects and long-range effects. Transport processes and reaction kinetics of chemical and plasma reactions are sensitive to the effective surface in the vicinity of a considered line as well as to the macroscopic location on the wafer. In addition to the structure dimension of interest, monitoring structures need to be developed for a fast and reliable monitoring of the mass production.

Double Patterning for Memory ICs 425

After removing the primary lines and transforming the sacrificial spacers into the hard

Wafer Uniformity Center to Edge 3nm Micro Loading Array to Select Gate Edge 2..3nm Micro Loading Gate Array Edge 6..10nm Micro Loading Array to Litho Monitor (nested) 10nm Micro Loading Array to Litho Monitor (isolated) 17nm Table 2. Experimental data for uniformity and micro loading and uniformity of the the gate

In general, the gate length is critical, requiring LBS (line by spacer) for the gate level. Typical

In the case of a flash memory, another electrical parameter comes into play: the coupling ratio, which determines mainly the programming and erase characteristics of the flash transistors. The coupling ratio is affected by the capacitance between the floating gate and the active area, i.e. the CD variations of both the (floating) gate and the active area cause a

As a result, a carefully controlled balance of the gate length in all kinds of chips is more




The balance of the mentioned three arguments led the authors to the decision of LBF (line by

NAND-Flash memory arrays require single rows of so called dense bit line contacts. They connect the metal bit lines to the active area, and they are following the critical pitch. The special challenge consists in the lack of any room for overlay tolerances and in the extreme asymmetry of the pattern: the contact row can be considered an isolated structure in one dimension, and in the orthogonal dimension a periodic structure with minimum pitch.


mask, one obtains values as given in Table 2.

layer of a 36nm NAND flash patterned by LBS.


spread in programming and erase performance.

For the active area, the following elements are relevant:

the source/drain junction into the substrate.

important than the control of the gate spaces.

**3.1.3 Active area / STI** 

current variations.

fill) for the active area layer.

**3.1.4 Bit line contact** 

program and erase speed.

electrical parameters of relevance are:

**3.1.2 Gate** 

 Fig. 8. Micro loading in the double patterning hard mask for the gate level of a 36nm NAND

Flash. The hard mask is made for the line by space (LBS) scheme.

We have selected the gate layer of a 36nm flash memory as an example of micro loading. Figure 8 shows measurements taken from cross-sections after the formation of the sacrificial spacer at the sides of the primary lines. The hard mask is not yet structured. An in-line measurement at this process step will reveal the sum of the width of the primary line plus two adjacent spacer thicknesses, equalling roughly the desired line with plus two spaces. An intuitive way of plotting this in-line measurement number is shown in Figure 9.

Fig. 9. Plot of the in-line measured line width consisting of the primarily formed line plus two adjacent spacers. The coloured area represents a quarter of the regular gate array. The center of the array is located at the bottom right of the plot, the corner of the array corresponds to the top left corner of the plot. Obviously, the line width increases from the center of the array towards the corners. The right hand graph was taken from an improved spacer deposition process, showing a narrower width distribution.

After removing the primary lines and transforming the sacrificial spacers into the hard mask, one obtains values as given in Table 2.


Table 2. Experimental data for uniformity and micro loading and uniformity of the the gate layer of a 36nm NAND flash patterned by LBS.
