EB shots with CP and VSB

Data conversion (library compiler)

Cell library for character projection (.db format)

instance specifies the optimal projection method for every cell functions.

typical logic synthesis flow.

Conventional cell library for logic synthesis (.lib format)

Fig. 11. Design flow in our design framework

on a CP aperture mask.

(ILOG, 2003).

Synopsys ".lib" format), the numbers of EB shots which are needed to project an instance of every cell function with the CP and VSB lithographies, and the optimal projection method of every cell function. In the cell library file format specification for the Design Compiler, the attributes designating area, delay, and power can be specified for each cell function but the number of EB shots cannot be specified. The attribute "area" has been used to represent both area and the number of EB shots by setting the linear combination of them as the attribute "area" for making the Design Compiler capable of optimizing them. And then the ".lib" file of the cell library has been converted into the Synopsys ".db" format file with the Synopsys Library Compiler.

We have utilized two cell libraries, high-performance and low-power ones, which were provided by the VLSI Design and Education Center (VDEC) at the University of Tokyo, as conventional cell libraries. The technology node of the two cell libraries was 0.35 m. We have demagnified all patterns of the two cell libraries by a factor of 90/350 in order to simulate the number of EB shots at the 90 nm technology node. With the two conventional cell libraries, we have generated cell libraries specialized in the CP system whose specification is shown in Table 12. The numbers of cell functions, on-characters cell functions, and off-characters cell functions are described in Table 13. Note that the cell libraries were supplied from academia and the number of cell functions is smaller than commercial ones. This means that the usage of an industrial cell library increases the number of off-characters cell functions and possibly deteriorates the throughput of the projection system in exchange for more design flexibility.


Table 12. Specification of projection equipment


Table 13. Two cell library description

#### **4.3.2 Experimental results**

We examined the numbers of EB shots to project several benchmark circuits with the two cell libraries.

First, we examined the relation between area and the number of EB shots to project each of ITC'99 benchmark circuits (Davidson, 1999). In the examination, all circuits were logicsynthesized for two objectives: area-minimization (=1, =0 in Equation (8)) and EB-shotsminimization (=0, =1 in the equation). The purpose of this examination was to obtain the minimal values of both area and EB shots of all benchmark circuits. We logic-optimized each of circuits ten times and have taken the best value of area and EB shots among the results. Fig. 12 and Fig. 13 show area and shots ratios for both area-minimized logic synthesis (=1, =0) and shots-minimized one ( = 0, = 1) with the two cell libraries, respectively.

Character Projection Lithography for Application-Specific Integrated Circuits 87

Fig. 13. Area and the number of EB shots of ITC'99 benchmark circuits with LP cell library Changing ratio /, we examined the relation between area and the number of EB shots for a benchmark circuit, b18\_1, as shown in Fig. 14. We show the range of both area and the number of EB shots observed in the process of ten logic optimizations in the figure in order to observe the tendency of area and the number of EB shots to change. This is because the logic synthesis tool returns quasi-optimal circuits with some variation of both area and EB shots and makes it hard to observe a consistent tendency of them. The figure shows that area tends to increase as the ratio / increases while the number of EB shots tends to decrease. These results show that there exists a tradeoff between area and the number of EB shots. We think that area-saving and off-characters cell functions are mapped as area is important. Such cell functions are substituted on-characters ones as the number of EB shots becomes important. ASIC designers should choose the ratio / according as they want to

(b) The number of EB shots under area- and EB shots-minimizations

(a) Area under area- and EB shots-minimizations

reduce area or the number of EB shots.

0 0.2 0.4 0.6 0.8 1 1.2 1.4

0 0.2 0.4 0.6 0.8 1 1.2

Normalized shots ratio

b01

b02

b03

b04

b05

b06

b07

b08

b09

b10

b11

b12

b13

b14

b14\_1

Benchmark circuit name

b15

b15\_1

b17

b17\_1

b18

b18\_1

b19

b19\_1

b20

b20\_1

b21

b21\_1

b22

b22\_1

Normalized area ratio

b01

b02

b03

b04

b05

b06

b07

b08

b09

b10

b11

b12

b13

b14

b14\_1

Benchmark circuit name

b15

b15\_1

b17

b17\_1

b18

b18\_1

b19

b19\_1

b20

b20\_1

b21

b21\_1

b22

b22\_1

α=1,β=0 α=0,β=1

α=1,β=0 α=0,β=1

Depending on and , the cell library was optimized for Circuit b19. The cell library is equivalent to the original one under =1 and=0. The area and EB shot count are normalized with those of area-minimized circuits. Note that the numbers of EB shots shown in the figures are the ones for projecting the FEOL patterns. They do not include any EB shots to project the BEOL patterns. Shots-minimizing logic synthesis reduced 54.6% of EB shot count at the best case in exchange for 8.4% area increase. Shots-minimization logic synthesis has increased 0.0% to 24.0% of area on logic-synthesizing all circuits.

(a) Area under area- and EB shots-minimizations

(b) The number of EB shots under area- and EB shots-minimizations

Depending on and , the cell library was optimized for Circuit b19. The cell library is equivalent to the original one under =1 and=0. The area and EB shot count are normalized with those of area-minimized circuits. Note that the numbers of EB shots shown in the figures are the ones for projecting the FEOL patterns. They do not include any EB shots to project the BEOL patterns. Shots-minimizing logic synthesis reduced 54.6% of EB shot count at the best case in exchange for 8.4% area increase. Shots-minimization logic

Fig. 12. Area and the number of EB shots of ITC'99 benchmark circuits with HP cell library

(b) The number of EB shots under area- and EB shots-minimizations

synthesis has increased 0.0% to 24.0% of area on logic-synthesizing all circuits.

0 0.2 0.4 0.6 0.8 1 1.2 1.4

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6

Normalized shots ratio

b01

b02

b03

b04

b05

b06

b07

b08

b09

b10

b11

b12

b13

b14

b14\_1

Benchmark circuit name

b15

b15\_1

b17

b17\_1

b18

b18\_1

b19

b19\_1

b20

b20\_1

b21

b21\_1

b22

b22\_1

α=1,β=0 α=0,β=1

Normalized area ratio

b01

b02

b03

b04

b05

b06

b07

b08

b09

b10

b11

b12

(a) Area under area- and EB shots-minimizations

b13

b14

b14\_1

Benchmark circuit name

b15

b15\_1

b17

b17\_1

b18

b18\_1

b19

b19\_1

b20

b20\_1

b21

b21\_1

b22

b22\_1

α=1,β=0 α=0,β=1

(a) Area under area- and EB shots-minimizations

(b) The number of EB shots under area- and EB shots-minimizations

Fig. 13. Area and the number of EB shots of ITC'99 benchmark circuits with LP cell library

Changing ratio /, we examined the relation between area and the number of EB shots for a benchmark circuit, b18\_1, as shown in Fig. 14. We show the range of both area and the number of EB shots observed in the process of ten logic optimizations in the figure in order to observe the tendency of area and the number of EB shots to change. This is because the logic synthesis tool returns quasi-optimal circuits with some variation of both area and EB shots and makes it hard to observe a consistent tendency of them. The figure shows that area tends to increase as the ratio / increases while the number of EB shots tends to decrease. These results show that there exists a tradeoff between area and the number of EB shots. We think that area-saving and off-characters cell functions are mapped as area is important. Such cell functions are substituted on-characters ones as the number of EB shots becomes important. ASIC designers should choose the ratio / according as they want to reduce area or the number of EB shots.

Character Projection Lithography for Application-Specific Integrated Circuits 89

(a) Area versus timing constraint

4.8 5.2 5.6 6.0 6.4 6.8 7.2 7.6 8.0 Timing constraint [ns]

=1,=0 =0,=1

=1,=0 =0,=1

170,000 175,000 180,000 185,000 190,000 195,000 200,000 205,000 210,000 215,000 220,000

50,000 60,000 70,000 80,000 90,000 100,000 110,000 120,000 130,000

The number of EB shots

Area [a.u.]

Fig. 15. Area and the number of EB shots with the HP cell library under timing constraints

(b) The number of EB shots versus timing constraint

4.8 5.2 5.6 6.0 6.4 6.8 7.2 7.6 8.0 Timing constraint [ns]

(b) The number of EB shots versus /

#### Fig. 14. Tradeoff between area and the number of EB shots

We have examined area and the number of EB shots under several timing constraints with a Z80-compatible processor. Fig. 15 and Fig. 16 show area and the number of EB shots under various timing constraints. When timing constraints were given, the effectiveness of the shots-minimization and area-minimization became less but the number of EB shots was reduced up to 26.6% nevertheless. The area increase accompanied with EB shots minimization was from 10.6% to 46.2%. These results show that area and the number of EB shots decreased as the timing constraint was loosened. We think that there exists a tradeoff between delay time and the number of EB shots (or area). A timing constraint for shorter delay time causes logic synthesis tools to choose off-characters cell functions that have higher current drivability. Such cell functions have larger transistors and require many EB shots to be projected with the VSB lithography.

(a) Area versus /

0 1 10 100 1,000 10,000 β/α

Fig. 14. Tradeoff between area and the number of EB shots

200,000 300,000 400,000 500,000 600,000 700,000 800,000

The number of EB shots

1,600,000 1,650,000 1,700,000 1,750,000 1,800,000 1,850,000 1,900,000 1,950,000

Area [a.u.]

shots to be projected with the VSB lithography.

We have examined area and the number of EB shots under several timing constraints with a Z80-compatible processor. Fig. 15 and Fig. 16 show area and the number of EB shots under various timing constraints. When timing constraints were given, the effectiveness of the shots-minimization and area-minimization became less but the number of EB shots was reduced up to 26.6% nevertheless. The area increase accompanied with EB shots minimization was from 10.6% to 46.2%. These results show that area and the number of EB shots decreased as the timing constraint was loosened. We think that there exists a tradeoff between delay time and the number of EB shots (or area). A timing constraint for shorter delay time causes logic synthesis tools to choose off-characters cell functions that have higher current drivability. Such cell functions have larger transistors and require many EB

(b) The number of EB shots versus /

0 1 10 100 1,000 10,000 β/α

(a) Area versus timing constraint

(b) The number of EB shots versus timing constraint

Fig. 15. Area and the number of EB shots with the HP cell library under timing constraints

Character Projection Lithography for Application-Specific Integrated Circuits 91

Our technology mapping technique for the CP lithography achieved a 54.6% less number of EB shots with 8.4% area increase under no timing constraints than the conventional one. Our technology mapping for the CP lithography also achieved a 26.6% less number of EB shots with 41.1% area increase and without any performance degradation than the conventional one. Varying the ratio /, we found that there exists a tradeoff between area and the

In the other experiments, tightening timing constraint increased area and the number of EB shots. It was found that there exists a tradeoff between delay time and the number of EB shots. We think that a timing constraint for shorter delay time has caused a logic synthesis

Our technology mapping technique reduced the number of EB shots to project patterns for the FEOL with some area increase. It is probable that some increase of cell instances causes the number of wires to increase and does the number of EB shots for projecting the BEOL patterns to increase. A technology mapping technique should be studied for reducing the number of EB shots required for both the FEOL and the BEOL patterns as future work. The number of cell functions which are placed on a CP aperture mask will increase as the technology node proceeds. It is probable that all cell functions of a commercial cell library, which includes more than 500 cell functions, will be placed on a single CP aperture mask at the 32 nm technology node. This indicates that the VSB lithography will be required less and less for projecting such cell functions. We suppose that our technology mapping technique is effective before the 32 nm technology node. We think that another technology mapping technique will be needed to increase throughput of MCC systems after the 32 nm

It is easy for both IC designers and equipment developers to adopt our technology mapping technique because a software approach such as our technique imposes no modification on CP equipment. This means that no additional cost is necessary to adopt our technique in

Character projection lithography is one of promising projection methods for manufacturing application specific integrated circuits at a low cost. From the viewpoint of ASIC design, the number of EB shots, which reflects the manufacturing cost for ASICs, is reduced by (i) cell

Cell library generation consists of two parts: cell selection and character sizing. We presented a cell selection method (Sugihara et al., 2005, 2006a) and character sizing methods (Sugihara et al., 2006c, 2007b). Cell selection and character sizing achieved 72.0% reduction of EB shots with a feasible EB size in the best, comparing with the conventional and

We also presented a technology mapping technique for reducing the number of EB shots in character projection lithography. Our technology mapping technique for the CP lithography has achieved a 54.6% less number of EB shots with 8.4% area increase under no timing constraints than the conventional one. Our technology mapping for the CP lithography has also achieved a 26.6% less number of EB shots with 41.1% area increase and without any performance degradation than the conventional one. Our experiments suggested that there

tool to choose the off-characters cell functions that have higher current drivability.

**4.4 Conclusion** 

number of EB shots.

technology node.

their IC design.

**5. Conclusion** 

intuitional character sizing.

library generation and (ii) technology mapping.

exists a tradeoff between area and the number of EB shots.

Fig. 16. Area and the number of EB shots with the LP cell library under timing constraints
