**6. References**

Beug, M.F.; Hoehr, T.; Müller, T.; Reichelt, R.; Müller-Meskamp, L.; Geiser, P.; Geppert, T.; Bach, L.; Bewersdorff-Sarlette, U.; Kenny, O.; Olligs, D.; Brandl, S.; Marschner, T. ; Parascandola, S.; Meyer, S.; Riedel, S .; Specht, M.; Manger, D.; Knöfler, R.; Knobloch, K.; Kratzert, P.; Ludwig, C. & Küsters, K.-H. (2008). Pitch Fragmentation Induced Odd/Even Effects in a 36nm Floating Gate NAND Technology,

**22** 

*1Nanometrics 2Globalfoundries*

*USA*

**Diffraction Based Overlay Metrology** 

**for Double Patterning Technologies** 

193nm optical immersion lithography is approaching its minimum practical single-exposure limit of 80nm pitch [1]. The semiconductor industry has adopted double patterning technology (DPT) as an attractive solution for the low k1 regime until extreme ultraviolet (EUV) lithography becomes commercialized. DPT also brings additional demands of increased critical dimension uniformity (CDU) and decreased overlay errors. The International Technology Roadmap for Semiconductors (ITRS) [2] target for overlay control at the 32nm DRAM node in single patterned lithography steps is 6nm. The process budget is reduced to 1.1nm for DPT. If 20% of the process error budget is allowed to occur in the metrology tool, as the ITRS states, then the measurement error budget at the 32nm node is

The ITRS defines total measurement uncertainty (TMU) for overlay only in terms of precision, tool-induced shift (TIS) variation and site-to-site tool matching differences. Determining whether a measurement technology is capable of controlling these advanced processes is no longer a case of simple data self-consistency checks on precision, TIS and matching. For example, the error arising from assumptions of a linear change of overlay error with position is significant. This error can be reduced by using very small targets [3] and performing in-device overlay measurements, but the demanding sub-nanometer measurement budget in overlay measurements still remains a

Recent advances in lithography metrology for advanced patterning have led to the proposal of three different pitch splitting technologies [Fig. 1]. The Litho-Etch-Litho-Etch method (LELE, Fig. 1a) involving two process steps requires very tight overlay control and is both very expensive and slow, making alternative methods attractive. The first alternative process flow is Litho-Freeze-Litho-Etch (LFLE), which reduces the processing cost by replacing the intermediate etch step with a process step in the litho track (Fig. 1b). After exposing the first pattern, the resist is baked in a post-exposure bake (PEB) step and developed. Exposed pattern is coated with material to freeze the resist. The second resist layer is added and the second exposure is done. The freezing material prevents the first resist layer from washing away during the second layer PEB and develop steps. This

**1. Introduction** 

considerable challenge.

1.2nm for single patterning, and 0.22nm for DPT.

Prasad Dasari1, Jie Li1, Jiangtao Hu1, Nigel Smith1 and Oleg Kritsun2

*International Electron Devices Meeting Technical Digest*, p.353, San Francisco, CA, USA, December 15-17, 2008, ISSN 8164-2284

