**1. Introduction**

416 Recent Advances in Nanofabrication Techniques and Applications

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In order to continue technology shrink roadmaps and to provide year by year smaller chips with more functionality, nearly all of the leading edge semiconductor companies have adopted double patterning process technologies in their fabrication lines to bridge the time until next generation EUV lithography reaches production maturity. Double patterning technology can be classified into two major main streams, however its implementation and especially the details of the process integration vary strongly among the semiconductor company and every manufacturer found his own optimum.

Therefore the given schemata will focus on the key principles. We will not stress material combinations, but point out particular challenges, show some detailed analyses, and sketch solutions.

#### **2. Double patterning by litho-etch-litho-etch**

The most straightforward approach of doing double patterning is splitting a given pattern into two parts by separating neighbouring patterns (see figure 1a). By doing this the minimum pitch of each split will be enlarged and becomes again printable with standard ARF immersion exposure tools. At the first lithography step, a photo mask containing only the blue part of the pattern will be used. As one can easily see from figure 1b, the pitch of blue only pattern is about two times larger than in the original layout. However, in order to achieve a good optical contrast during imaging as well as to get sufficient (photo resist) process window for the patterning, the pattern will usually be biased on the mask as shown in figure 1c.

Fig. 1. Example of decomposing an irregular structure for double patterning processing.

Double Patterning for Memory ICs 419

needed for the plasma etch process of the intended layer stack anyway. The limits of the plasma etch selectivities and the aspect ratios require the usage of sophisticated hard mask stacks. Etching a complex stack twice is also more costly than doing the double patterning etch sequences only on the thin hard mask and perform the complex and expensive full stack etch only once. Last for the sake of completeness we want to mention here, that for cost and complexity reasons techniques of freezing the first split pattern directly in photo

Splitting the given pattern into two parts allows complex designs. Therefore this type of double patterning is the preferred choice for logic manufactures. But since two lithography steps must be done to achieve the patterning for one layer, the intra-layer overlay must be controlled with a very high degree of precision. This was challenging in the past, because first and second generation ARF immersion tools could hardly achieve overlay control beyond 6-8nm, which is above the needed budget for 36nm…32nm and 28nm…24nm technologies. Around 2010, lithography tool makers removed this blocking point by introducing a third generation of ARF immersion tools with can meet double patterning overlay control requirements. This double patterning technique is usually referenced with Litho-Etch-Litho-Etch (LELE) but other names such as Brute Force or Pitch Splitting exist as

For the extremely regular arrays of memory chips like e.g. NAND flash memories, aggressive double patterning technology nodes have been introduced already in 2008, before exposure tools with improved overlay control became available. Memory chip manufacturers have therefore driven another double patterning main stream, which we will

The second main stream is often called self aligned double patterning. Some people call this technique pitch fragmentation and you might often hear spacer based double patterning, because for most of this techniques spacer-like approaches are used to double the number of

Self aligned double pattering comes with strong layout limitations. However, it is well suited for regular patterns e.g. of memory chips. The design process is more complex than LELE and the pattern on the photo masks look different compared to the final pattern. This creates a first challenge, because layout versus schematic checks require additional CAD tooling to transform the self aligned double patterning mask data into the final layout data. The transformation in the other direction – from final layout to double patterning layout – is even more challenging. Automated tools are rare and manual interaction of the designers is required. This is limiting the application to a manageable number of layout features and is the main reason why self aligned double patterning is mostly only used by memory

The big advantage of self aligned double patterning is that only one main feature lithography step has to be done. However, one or two additional assist lithography steps with considerably reduced resolution requirements are used to form the edges of the regular pattern within the memory array as well as the transition from the regular array towards the

The lithography tool overlay requirement is only driven by the inter-layer technology

remaining area of the chip, containing the control function elements of the memory.

demands and not by the intra-layer alignment as for LELE.

resist system are showing up in the industry.

well.

features.

manufactures.

describe in the next paragraph.

**3. Self aligned double patterning** 

Triangular conflicts deserve special attention. They can for instance be solved by using junctions to bridge split part features with each other as shown in figure 2. Another way is to restrict the layout to full splits and to use separate interconnects. Despite the need of such kind of additional rules, LELE can handle complex layout and modern CAD tools do support pitch splitting well.

Fig. 2. Topological conflict (a) and a possible decomposition by a junction bridge (b).

To achieve the intended structure dimensions, the applied bias must be removed again. Overexposing the photo resist is commonly used to reduce the bias, but there are limits for process stability reasons. Therefore further bias reduction might be required. Often this will be done in subsequent etch steps, which also have the function of "freezing" the pattern, so that it will not be destroyed when the second part of the pattern will be added. Figure 3 shows a sample sequence.

Fig. 3. Process sequence for litho-etch-litho-etch double patterning.

The first pattern freeze is typically done in a thin sacrificial hard mask. Although this thin sacrificial hard mask adds process complexity and thus fabrication cost, there are two good arguments for introducing it. The argument #1 is as follows: It is easier to assemble all pattern elements first within a thin sacrificial layer and later transfer them altogether to the intended layer stack, rather than structuring the full intended layer stack step by step. This is because the intended structures on wafers tend to have large aspect ratios. But once the second lithography gets carried out, the topography of the wafer must be nearly flat. Otherwise resist spin-on gets problematic and one has to struggle with reflective notching and local CD (critical dimension) variation. That means, without using the sacrificial thin hard mask, complex planarization steps would be necessary. However, the thin hard mask topography differences can easily be covered by BARC / bottom layer coatings, which have to be applied for ARF resist systems anyway. The argument #2 is: Hard masks are typically

Triangular conflicts deserve special attention. They can for instance be solved by using junctions to bridge split part features with each other as shown in figure 2. Another way is to restrict the layout to full splits and to use separate interconnects. Despite the need of such kind of additional rules, LELE can handle complex layout and modern CAD tools do

**B A**

Fig. 3. Process sequence for litho-etch-litho-etch double patterning.

Fig. 2. Topological conflict (a) and a possible decomposition by a junction bridge (b).

To achieve the intended structure dimensions, the applied bias must be removed again. Overexposing the photo resist is commonly used to reduce the bias, but there are limits for process stability reasons. Therefore further bias reduction might be required. Often this will be done in subsequent etch steps, which also have the function of "freezing" the pattern, so that it will not be destroyed when the second part of the pattern will be added. Figure 3

The first pattern freeze is typically done in a thin sacrificial hard mask. Although this thin sacrificial hard mask adds process complexity and thus fabrication cost, there are two good arguments for introducing it. The argument #1 is as follows: It is easier to assemble all pattern elements first within a thin sacrificial layer and later transfer them altogether to the intended layer stack, rather than structuring the full intended layer stack step by step. This is because the intended structures on wafers tend to have large aspect ratios. But once the second lithography gets carried out, the topography of the wafer must be nearly flat. Otherwise resist spin-on gets problematic and one has to struggle with reflective notching and local CD (critical dimension) variation. That means, without using the sacrificial thin hard mask, complex planarization steps would be necessary. However, the thin hard mask topography differences can easily be covered by BARC / bottom layer coatings, which have to be applied for ARF resist systems anyway. The argument #2 is: Hard masks are typically

(a) (b)

**A**

support pitch splitting well.

shows a sample sequence.

needed for the plasma etch process of the intended layer stack anyway. The limits of the plasma etch selectivities and the aspect ratios require the usage of sophisticated hard mask stacks. Etching a complex stack twice is also more costly than doing the double patterning etch sequences only on the thin hard mask and perform the complex and expensive full stack etch only once. Last for the sake of completeness we want to mention here, that for cost and complexity reasons techniques of freezing the first split pattern directly in photo resist system are showing up in the industry.

Splitting the given pattern into two parts allows complex designs. Therefore this type of double patterning is the preferred choice for logic manufactures. But since two lithography steps must be done to achieve the patterning for one layer, the intra-layer overlay must be controlled with a very high degree of precision. This was challenging in the past, because first and second generation ARF immersion tools could hardly achieve overlay control beyond 6-8nm, which is above the needed budget for 36nm…32nm and 28nm…24nm technologies. Around 2010, lithography tool makers removed this blocking point by introducing a third generation of ARF immersion tools with can meet double patterning overlay control requirements. This double patterning technique is usually referenced with Litho-Etch-Litho-Etch (LELE) but other names such as Brute Force or Pitch Splitting exist as well.

For the extremely regular arrays of memory chips like e.g. NAND flash memories, aggressive double patterning technology nodes have been introduced already in 2008, before exposure tools with improved overlay control became available. Memory chip manufacturers have therefore driven another double patterning main stream, which we will describe in the next paragraph.
