**4.2 Laser-assisted wafer planarization**

High-performance large-scale integrated circuits (ICs) require several levels of interconnect. Planarization processes which smooth and flatten the surface of an IC at various stages of fabrication are essential for high-resolution photolithography. Besides being smooth and flat, good film step-coverage without internal voids is also crucial for interconnection. Present IC interconnects are fabricated by the damascene process that consists of four major steps: patterning trenches in low-k dielectric materials by photolithography, sputtering metal plating base, copper electrical plating to fill the trench, and chemical mechanical polishing that planarizes the surface. The step-coverage of electrodeposited metal film, though better than other PVD (physical vapor deposition,

Ultrafast Fabrication of Metal Nanostructures Using Pulsed Laser Melting 127

SiO2 IBE mask

Fig. 10. Laser-assisted planarization of a 200 nm-period Cu grating on SiO2. (a) Before planarization. (b) After planarization by 0.22 J/cm2, shown here was a SEM image with evaporated SiO2 IBE-mask still on top. (c) AFM image showing surface smoothness better than 4 nm. (d) Cu lines embedded in SiO2 with flat surface fabricated after IBE removal of the Cu on top. (SEM cross-section was "cut" by IBE using evaporated SiO2 as mask)

Filling via holes or trenches with a deposited material is an important step in IC manufacturing. At present, the metal interconnect for ICs is typically fabricated by the dual damascene and, for the first wiring level, tungsten CVD plug process, where the via holes and trenches are etched in a dielectric material and subsequently filled up with a metal. Clearly, any voids left in the vias or trenches caused by poor step coverage will create a serious problem for the interconnect. Though superior to PVD, the step coverage of tungsten CVD is still limited by the low volatility of the precursor gas WF6 that leads to a low vapor pressure. The result is a mass transport limited deposition rate, and the hole opening receives faster deposition and would be closed before the holes are completely filled.

Atomic layer deposition (ALD) can achieve excellent step coverage in certain conditions. It is a modified form of CVD with gas precursors introduced one at a time with pump/purge in between. So the film is deposited one atomic layer per cycle, with a typical deposition rate of order 0.5 nm/min. Not only the slow deposition rate is a manufacturing issue, but also in ALD, voids will be formed if the via holes or trenches have a sidewall with negative angle. The process we developed to fill via-holes is very close to the laser-assisted wafer planarization process, except that the trenches were replaced with deep and high aspect

Another disadvantage of CVD is its relatively high thermal budget.

**4.3 Laser-assisted via-hole filling** 

(c) (d)

(a) (b)

SiO2 Cu

including evaporation and sputtering) metal films, is not as good as CVD (chemical vapor deposition) films because trench edges plate faster than trench bottoms. This problem will become even more severe for future ICs with narrower line-widths. Therefore, it is desirable to develop a technique that can both flatten the surface and enhance the step-coverage at the same time. Laser-assisted planarization might be one answer.

The setup for planarization is the same as LADI except that now a flat un-patterned quartz "mold" is used. The process is shown in Fig. 9. First, an insulator layer, typically thermal oxide which is also a good heat insulator, was patterned by NIL and RIE. Metal was then evaporated or sputtered onto the pattern. Finally, the metal was melted by a pulsed excimer laser and thus conformed to the flat and smooth surface of the quartz mold. IC interconnect typically consists of metal lines embedded in an insulator, which can be readily achieved here by etching away the metal on top using argon ion beam etching (IBE).

Fig. 9. Laser-assisted planarization. (a) Pattern insulator; (b) Deposit metal, here by evaporation; (c) Laser-melt and planarize. Metal on top of insulator was etched away by ion beam etching in (d).

Fig. 10 shows laser-assisted planarization of 180 nm-thick Cu evaporated onto a 200 nmperiod SiO2 grating on a silicon wafer. The laser fluence was 0.22 J/cm2, which was close to the fluence used for LADI of Cu. As seen in Fig. 10(a), the step-coverage of evaporated Cu film was very poor. But after planarization the underlying voids were all filled with Cu (Fig. 10(b)), and the surface became very smooth with fluctuation less than 4 nm (Fig. 10(c)). Fig. 10(d) shows a 200 nm-period Cu grating embedded in an insulator (here silicon dioxide) fabricated by laser-assisted planarization and IBE removal of the Cu on top of the insulator. The laser fluence used for this sample was 70% higher than previous one, and the number of applied pulses was 150! Yet no apparent damage of Cu was found, suggesting that the number of pulses has only minor impact on laser-assisted planarization.

including evaporation and sputtering) metal films, is not as good as CVD (chemical vapor deposition) films because trench edges plate faster than trench bottoms. This problem will become even more severe for future ICs with narrower line-widths. Therefore, it is desirable to develop a technique that can both flatten the surface and enhance the step-coverage at the same time. Laser-assisted planarization might be one

The setup for planarization is the same as LADI except that now a flat un-patterned quartz "mold" is used. The process is shown in Fig. 9. First, an insulator layer, typically thermal oxide which is also a good heat insulator, was patterned by NIL and RIE. Metal was then evaporated or sputtered onto the pattern. Finally, the metal was melted by a pulsed excimer laser and thus conformed to the flat and smooth surface of the quartz mold. IC interconnect typically consists of metal lines embedded in an insulator, which can be readily achieved here by etching away the metal on top using argon ion beam

Fig. 9. Laser-assisted planarization. (a) Pattern insulator; (b) Deposit metal, here by

Dielectric Metal Sub-layer

evaporation; (c) Laser-melt and planarize. Metal on top of insulator was etched away by ion

d

c

Fig. 10 shows laser-assisted planarization of 180 nm-thick Cu evaporated onto a 200 nmperiod SiO2 grating on a silicon wafer. The laser fluence was 0.22 J/cm2, which was close to the fluence used for LADI of Cu. As seen in Fig. 10(a), the step-coverage of evaporated Cu film was very poor. But after planarization the underlying voids were all filled with Cu (Fig. 10(b)), and the surface became very smooth with fluctuation less than 4 nm (Fig. 10(c)). Fig. 10(d) shows a 200 nm-period Cu grating embedded in an insulator (here silicon dioxide) fabricated by laser-assisted planarization and IBE removal of the Cu on top of the insulator. The laser fluence used for this sample was 70% higher than previous one, and the number of applied pulses was 150! Yet no apparent damage of Cu was found, suggesting that the number of pulses has only minor impact on laser-assisted

answer.

etching (IBE).

a

beam etching in (d).

b

planarization.

Fig. 10. Laser-assisted planarization of a 200 nm-period Cu grating on SiO2. (a) Before planarization. (b) After planarization by 0.22 J/cm2, shown here was a SEM image with evaporated SiO2 IBE-mask still on top. (c) AFM image showing surface smoothness better than 4 nm. (d) Cu lines embedded in SiO2 with flat surface fabricated after IBE removal of the Cu on top. (SEM cross-section was "cut" by IBE using evaporated SiO2 as mask)

#### **4.3 Laser-assisted via-hole filling**

Filling via holes or trenches with a deposited material is an important step in IC manufacturing. At present, the metal interconnect for ICs is typically fabricated by the dual damascene and, for the first wiring level, tungsten CVD plug process, where the via holes and trenches are etched in a dielectric material and subsequently filled up with a metal. Clearly, any voids left in the vias or trenches caused by poor step coverage will create a serious problem for the interconnect. Though superior to PVD, the step coverage of tungsten CVD is still limited by the low volatility of the precursor gas WF6 that leads to a low vapor pressure. The result is a mass transport limited deposition rate, and the hole opening receives faster deposition and would be closed before the holes are completely filled. Another disadvantage of CVD is its relatively high thermal budget.

Atomic layer deposition (ALD) can achieve excellent step coverage in certain conditions. It is a modified form of CVD with gas precursors introduced one at a time with pump/purge in between. So the film is deposited one atomic layer per cycle, with a typical deposition rate of order 0.5 nm/min. Not only the slow deposition rate is a manufacturing issue, but also in ALD, voids will be formed if the via holes or trenches have a sidewall with negative angle.

The process we developed to fill via-holes is very close to the laser-assisted wafer planarization process, except that the trenches were replaced with deep and high aspect

Ultrafast Fabrication of Metal Nanostructures Using Pulsed Laser Melting 129

LA-nTP process, we use a pre-patterned transparent support in intimate contact with a substrate, therefore the resolution is no longer limited by the processing parameters but is

The LA-nTP process is shown in Fig. 12. For proof of concept, we fabricated the donor support (DS) consisting a square chromium nanodot array with 200 nm period and 35 nm height (Fig. 12A). In parallel, we fabricated the acceptor substrate (AS) by photolithography and reactive ion etching, which contained an array of microwells with a diameter of 100 µm and depth 40 nm. The two patterned surfaces were then brought into contact by sandwiching them between two press plates. After shining with a laser pulse of fluence ~0.35 J/cm2, the Cr nanodots were transferred only onto the protruded parts of the acceptor substrate that were in intimate contact with the donor support (Fig. 12C). We also found that using higher fluences (>0.6 J/cm2), the results obtained were similar to those observed in other LIFT studies, namely Cr dot was transferred to the protruded areas as well as the recessed areas of the acceptor substrate with an increasing amount of spatter. At even higher fluencies (>1 J/cm2), significant chromium vaporization was observed. On the other hand, experiments using laser fluencies lower than 0.2 J/cm2 (below the melting threshold of a 30

Nanotips have many applications such as scanning probe microscopy (SPM) and vacuum microelectronic devices like field emission display (FED), where their performance is often limited by the tip. Carbon nanotubes (Nguyen 2005, Jeong 2006) or nanocones (Chen 2006) have been studied extensively for applications as tips or emitters owning to its fine diameter and high aspect ratio. Silicon tips with high aspect ratio can be readily fabricated by highly anisotropic dry etching (Rangelow 2001). Metal is highly conductive and mechanically strong and robust, which are favorable properties for field emitter or scanning probe. Unfortunately, it is more challenging to fabricate metal tips on a wafer due to the difficulty in etching metals. Single metal tip can be routinely fabricated by focused ion beam milling or electrochemical etching (Kim 2006). But for FED or high throughput nanolithography using SPM, tip arrays are essential, which are very difficult to fabricate by the previous two methods. Metal tip arrays with low aspect ratio were traditionally fabricated by the Spindt process where the metal is evaporated through apertures that become gradually closed by the evaporated material (Spindt 1968). Similarly yet via a different mechanism, Au tips were formed by evaporation into porous alumina (Losic 2005). Alternatively, metal tips can be

We found that sharp metal tips could also be self-formed by simply melting momentarily (~100 ns) a metal film deposited on a wafer with a second wafer placed a gap (submicrometers) below, as shown in Fig. 13 (Cui 2008). In the experiment, a silicon wafer with 500 nm thermal oxide was placed below the Cr film with a gap formed by a spacer. Next, a single excimer laser pulse (fluence 0.4 J/cm2) shone through the quartz to melt the metal film momentarily that caused it to transfer toward the lower wafer. The two wafers were separated after Cr solidification and examined by SEM that showed nano-tip formation on both surfaces. The size, shape and location of the tips were random, but more regular tips are expected if the Cr is pre-patterned into identical isolated mesas. In addition, The ends of most tips resemble a sharp cone (not flat), hence they should be broken by the tensile force due to surface tension and/or volume shrinkage upon solidification; whereas those with a flat end were broken by mechanical force when the two wafers were separated.

replicated by physical vapor deposition or electroplating into etch holes.

determined only by the initial feature size on the transparent support.

nm Cr thin film) failed to transfer the Cr nanopatterns.

**4.5 Laser-assisted nanotip formation** 

ratio holes (Cui 2006). We fabricated in Si a hole array having 100 nm diameter, 500 nm depth (aspect ratio 5) and 200 nm inter-hole spacing (pitch). The hole array was patterned by nanoimprint lithography and etched by Cl2/Ar RIE. As silicon is a good heat sink, a 15 nm thermal oxide layer was grown to reduce heat loss to the surrounding bulk Si, and to shrink the hole size at the same time. Finally, 200 nm Si or Cu was deposited on top of the hole array by e-beam evaporation. As expected and shown in Fig. 11a, evaporation has very poor step coverage, so the holes were only partially filled, with the sidewall of the holes receiving little deposition before the hole opening was closed. Fig. 11b shows via filling by Si, indicating a complete filling without voids. For via filling by Cu (Fig. 11c), the Cu plugs were found broken after wafer cut, and it is possible that the built-in stress caused by fast cooling of the liquid Cu has contributed to the Cu plug fracture. Nonetheless, we believe that most holes were completely filled to the bottom, as indicated by the Cu plug sections found on the bottom of the holes.

Fig. 11. (a) Holy array with 200 nm period and aspect ratio 5:1 after evaporation of filling material, here 200 nm Si. (15 nm thermal oxide has been grown to reduce heat loss to bulk Si). (b) Laser-assisted via-hole filling by -Si, showing all holes were completely filled without void. (c) Laser-assisted via-hole filling by Cu.

#### **4.4 Laser-assisted nanotransfer printing**

Laser-assisted nanotransfer printing (LA-nTP) is a dry-contact printing process which combines into one single step several steps needed for metal nanopatterning (Le Drogoff 2006). This process shares some attributes with laser-induced forward transfer (LIFT) process (Bohandy 1986). In LIFT, a thin laser-light absorbing film is irradiated with a focused laser pulse through a transparent support, and transferred, in the form of micron-sized dots, onto a suitable substrate facing it. The pattern is created through selective deposition on the substrate by scanning the laser beam. The resolution is hence determined and limited by the laser beam size and by the gap between the two samples (which determines the lateral spreading). In the LA-nTP process, we use a pre-patterned transparent support in intimate contact with a substrate, therefore the resolution is no longer limited by the processing parameters but is determined only by the initial feature size on the transparent support.

The LA-nTP process is shown in Fig. 12. For proof of concept, we fabricated the donor support (DS) consisting a square chromium nanodot array with 200 nm period and 35 nm height (Fig. 12A). In parallel, we fabricated the acceptor substrate (AS) by photolithography and reactive ion etching, which contained an array of microwells with a diameter of 100 µm and depth 40 nm. The two patterned surfaces were then brought into contact by sandwiching them between two press plates. After shining with a laser pulse of fluence ~0.35 J/cm2, the Cr nanodots were transferred only onto the protruded parts of the acceptor substrate that were in intimate contact with the donor support (Fig. 12C). We also found that using higher fluences (>0.6 J/cm2), the results obtained were similar to those observed in other LIFT studies, namely Cr dot was transferred to the protruded areas as well as the recessed areas of the acceptor substrate with an increasing amount of spatter. At even higher fluencies (>1 J/cm2), significant chromium vaporization was observed. On the other hand, experiments using laser fluencies lower than 0.2 J/cm2 (below the melting threshold of a 30 nm Cr thin film) failed to transfer the Cr nanopatterns.

#### **4.5 Laser-assisted nanotip formation**

128 Recent Advances in Nanofabrication Techniques and Applications

ratio holes (Cui 2006). We fabricated in Si a hole array having 100 nm diameter, 500 nm depth (aspect ratio 5) and 200 nm inter-hole spacing (pitch). The hole array was patterned by nanoimprint lithography and etched by Cl2/Ar RIE. As silicon is a good heat sink, a 15 nm thermal oxide layer was grown to reduce heat loss to the surrounding bulk Si, and to shrink the hole size at the same time. Finally, 200 nm Si or Cu was deposited on top of the hole array by e-beam evaporation. As expected and shown in Fig. 11a, evaporation has very poor step coverage, so the holes were only partially filled, with the sidewall of the holes receiving little deposition before the hole opening was closed. Fig. 11b shows via filling by Si, indicating a complete filling without voids. For via filling by Cu (Fig. 11c), the Cu plugs were found broken after wafer cut, and it is possible that the built-in stress caused by fast cooling of the liquid Cu has contributed to the Cu plug fracture. Nonetheless, we believe that most holes were completely filled to the bottom, as indicated by the Cu plug sections

Fig. 11. (a) Holy array with 200 nm period and aspect ratio 5:1 after evaporation of filling material, here 200 nm Si. (15 nm thermal oxide has been grown to reduce heat loss to bulk Si). (b) Laser-assisted via-hole filling by -Si, showing all holes were completely filled

1µm a

c

b

Laser-assisted nanotransfer printing (LA-nTP) is a dry-contact printing process which combines into one single step several steps needed for metal nanopatterning (Le Drogoff 2006). This process shares some attributes with laser-induced forward transfer (LIFT) process (Bohandy 1986). In LIFT, a thin laser-light absorbing film is irradiated with a focused laser pulse through a transparent support, and transferred, in the form of micron-sized dots, onto a suitable substrate facing it. The pattern is created through selective deposition on the substrate by scanning the laser beam. The resolution is hence determined and limited by the laser beam size and by the gap between the two samples (which determines the lateral spreading). In the

without void. (c) Laser-assisted via-hole filling by Cu.

**4.4 Laser-assisted nanotransfer printing** 

found on the bottom of the holes.

Nanotips have many applications such as scanning probe microscopy (SPM) and vacuum microelectronic devices like field emission display (FED), where their performance is often limited by the tip. Carbon nanotubes (Nguyen 2005, Jeong 2006) or nanocones (Chen 2006) have been studied extensively for applications as tips or emitters owning to its fine diameter and high aspect ratio. Silicon tips with high aspect ratio can be readily fabricated by highly anisotropic dry etching (Rangelow 2001). Metal is highly conductive and mechanically strong and robust, which are favorable properties for field emitter or scanning probe. Unfortunately, it is more challenging to fabricate metal tips on a wafer due to the difficulty in etching metals. Single metal tip can be routinely fabricated by focused ion beam milling or electrochemical etching (Kim 2006). But for FED or high throughput nanolithography using SPM, tip arrays are essential, which are very difficult to fabricate by the previous two methods. Metal tip arrays with low aspect ratio were traditionally fabricated by the Spindt process where the metal is evaporated through apertures that become gradually closed by the evaporated material (Spindt 1968). Similarly yet via a different mechanism, Au tips were formed by evaporation into porous alumina (Losic 2005). Alternatively, metal tips can be replicated by physical vapor deposition or electroplating into etch holes.

We found that sharp metal tips could also be self-formed by simply melting momentarily (~100 ns) a metal film deposited on a wafer with a second wafer placed a gap (submicrometers) below, as shown in Fig. 13 (Cui 2008). In the experiment, a silicon wafer with 500 nm thermal oxide was placed below the Cr film with a gap formed by a spacer. Next, a single excimer laser pulse (fluence 0.4 J/cm2) shone through the quartz to melt the metal film momentarily that caused it to transfer toward the lower wafer. The two wafers were separated after Cr solidification and examined by SEM that showed nano-tip formation on both surfaces. The size, shape and location of the tips were random, but more regular tips are expected if the Cr is pre-patterned into identical isolated mesas. In addition, The ends of most tips resemble a sharp cone (not flat), hence they should be broken by the tensile force due to surface tension and/or volume shrinkage upon solidification; whereas those with a flat end were broken by mechanical force when the two wafers were separated.

Ultrafast Fabrication of Metal Nanostructures Using Pulsed Laser Melting 131

(a)

Fig. 13. (a) Schematic laser-induced metal nanotip formation process, with the metal here as 25 nm Cr. (b) Cr tips formed on the Si/SiO2 substrate. (c) Cr tips formed on the quartz wafer. The inset is the zoom-in image of the tip at the center that has an apex of 10 nm and

(b) (c)

The experimentally observed metal nano-tip formation phenomenon can be explained in term of an electro-hydrodynamic instability process as shown in Fig. 14. Briefly, the nano-tip formation can be roughly divided into four stages: free charge buildup, mass transfer to the lower wafer upon laser illumination, liquid pillar formation due to electrostatic attraction,

When the two wafers are brought close together, free charges are built up on both wafers due to the work function difference between Cr and SiO2, which results in a strong electric field of order 105 V/cm for a 500 nm gap. Interaction between electric field and induced dipole or free charges accumulated at the interface results in an electrostatic pressure. **T**he attractive electrostatic force sets the two molten metal films into tension subject to infinitesimal disturbances, and interfacial ripples start to develop. The periodicity of the ripple that determines the areal number density of the tips would depend on the liquid metal density, film thickness, surface tension and work function difference. The electrostatic force between two approaching peaks is further enhanced due to the locally strengthened electric field. As a result, the electrostatic force keeps on overcoming the stabilizing surface tension and viscous force and pulling the peaks further together until the peaks are bridged together to form a liquid bridge or the liquid metal solidifies. Once the peaks bridged together, the charges are neutralized and thus the electrostatic force disappears, and the bridges may break by the large surface tension of liquid metal that is about 20 times that of water. Meanwhile, solidification propagates from the two metal-wafer interfaces toward the gap center, because the wafers are heat sinks and the temperature distribution before

height of 180 nm. (This tip appears tilted due to SEM stage drift during imaging.)

and solidification and break of the pillars.

The quartz and SiO2 surface was found to be rather flat after the process. Since the melting temperature of quartz is much lower than the boiling temperature of Cr, a top SiO2 layer of order 100 nm on both wafers should have been melted by heat transfer. However, due to the six orders higher viscosity of molten SiO2 compared to that of chromium (3.0 × 106 cP for SiO2 versus 3.7 cP for Cr at 2673 K (Yaws 1998)), the flow of the molten SiO2 is negligible, leading to no apparent distortion of the two wafer surfaces.

Fig. 12. (left) Schematic sequence of the fabrication process of LA-nTP (DS: donor support, AS: acceptor substrate). (right) A). Cr dot array on DS; B). Cr dot array on DS facing the recessed area of the AS; C). AS after LA-nTP showing Cr dot array was transferred from DS only to the protruded area of AS.

The quartz and SiO2 surface was found to be rather flat after the process. Since the melting temperature of quartz is much lower than the boiling temperature of Cr, a top SiO2 layer of order 100 nm on both wafers should have been melted by heat transfer. However, due to the six orders higher viscosity of molten SiO2 compared to that of chromium (3.0 × 106 cP for SiO2 versus 3.7 cP for Cr at 2673 K (Yaws 1998)), the flow of the molten SiO2 is negligible,

Fig. 12. (left) Schematic sequence of the fabrication process of LA-nTP (DS: donor support, AS: acceptor substrate). (right) A). Cr dot array on DS; B). Cr dot array on DS facing the recessed area of the AS; C). AS after LA-nTP showing Cr dot array was transferred from DS

**C** 

only to the protruded area of AS.

leading to no apparent distortion of the two wafer surfaces.

Fig. 13. (a) Schematic laser-induced metal nanotip formation process, with the metal here as 25 nm Cr. (b) Cr tips formed on the Si/SiO2 substrate. (c) Cr tips formed on the quartz wafer. The inset is the zoom-in image of the tip at the center that has an apex of 10 nm and height of 180 nm. (This tip appears tilted due to SEM stage drift during imaging.)

The experimentally observed metal nano-tip formation phenomenon can be explained in term of an electro-hydrodynamic instability process as shown in Fig. 14. Briefly, the nano-tip formation can be roughly divided into four stages: free charge buildup, mass transfer to the lower wafer upon laser illumination, liquid pillar formation due to electrostatic attraction, and solidification and break of the pillars.

When the two wafers are brought close together, free charges are built up on both wafers due to the work function difference between Cr and SiO2, which results in a strong electric field of order 105 V/cm for a 500 nm gap. Interaction between electric field and induced dipole or free charges accumulated at the interface results in an electrostatic pressure. **T**he attractive electrostatic force sets the two molten metal films into tension subject to infinitesimal disturbances, and interfacial ripples start to develop. The periodicity of the ripple that determines the areal number density of the tips would depend on the liquid metal density, film thickness, surface tension and work function difference. The electrostatic force between two approaching peaks is further enhanced due to the locally strengthened electric field. As a result, the electrostatic force keeps on overcoming the stabilizing surface tension and viscous force and pulling the peaks further together until the peaks are bridged together to form a liquid bridge or the liquid metal solidifies. Once the peaks bridged together, the charges are neutralized and thus the electrostatic force disappears, and the bridges may break by the large surface tension of liquid metal that is about 20 times that of water. Meanwhile, solidification propagates from the two metal-wafer interfaces toward the gap center, because the wafers are heat sinks and the temperature distribution before

Ultrafast Fabrication of Metal Nanostructures Using Pulsed Laser Melting 133

than that used for regular thermal nanoimprint lithography (order of 10 bar). However, considerably lower applied pressure would be sufficient for patterning metals and silicon if: (1) the molten metal partly wets the SiO2 substrate; and/or (2) the mold consists of sparse protruded patterns to create sparse recessed metal features (such as a periodic hole array having diameter ~100 nm and pitch 500–600 nm in Au for extraordinary optical transmission devices (Lesuffleur 2008)), because the effective local pressure at the protruded mold features is significantly higher than the applied pressure (applied force divided by

Fig. 15. Schematic drawing showing the calculation of minimum pressure to squeeze a liquid into (a) a trench, (b) a trench with liquid partly squeezed against the bottom, and (c) a via hole. The pressures are calculated assuming 90o contact angle and no wetting/adhesion.

The maximum feature size that can be patterned depends on how far the molten metal can flow before re-solidification. For a rough estimation, the dynamic flowing process is modeled as in Fig. 16. It is assumed that the grating structure has a period 2L and a trench depth h0; and the entire layer is melted at t=0 and re-solidification takes place simultaneously throughout the film thickness at time t=. The mold will travel a distance of h0/2 and the residual molten layer thickness will decrease to h0/2 when the trench is fully filled. Since L is large, the effect of surface tension can be ignored and thus the internal pressure at x=L/2 is zero. There are three forces acting on the liquid: the pressing force from

We first consider only the effect of viscous force by assuming that a steady flow develops momentarily at t=0 (i.e. ignore inertial force). Then the maximum grating half pitch L1 that can be patterned (trench fully filled) before the liquid metal solidifies is given by

(11)

where *h* is the metal film thickness (200 nm), P is the applied pressure (order 100 bar), is the viscosity, and is the melting duration (~ 200 ns) that depends on laser fluence. The

1 *<sup>P</sup> L h*

wafer surface area).

**5.2 Upper limit of achievable feature size** 

the mold, the viscous force, and the inertial force.

(Heyderman 2000, Cui 2006):

solidification across the gap should be uniform (since the melting time is order 100 ns that is much longer than pulse duration). Nano-tips are formed at the broken bridge necks before or during solidification due to surface tension and volume shrinkage, or after the two wafers were separated.

Fig. 14. Schematic of the physical mechanism behind the nano-tip formation. (a) Build-up of free charges on the two wafers. (b) Metal transfer to lower wafer by evaporationcondensation. (c) Nano-bridge formation due to attractive electrostatic force. (d) Bridging of approaching peaks and charge neutralization. (e) Break of bridges upon solidification or after separation.
