**3.1.2 Gate**

424 Recent Advances in Nanofabrication Techniques and Applications

Fig. 8. Micro loading in the double patterning hard mask for the gate level of a 36nm NAND

We have selected the gate layer of a 36nm flash memory as an example of micro loading. Figure 8 shows measurements taken from cross-sections after the formation of the sacrificial spacer at the sides of the primary lines. The hard mask is not yet structured. An in-line measurement at this process step will reveal the sum of the width of the primary line plus two adjacent spacer thicknesses, equalling roughly the desired line with plus two spaces. An

Fig. 9. Plot of the in-line measured line width consisting of the primarily formed line plus two adjacent spacers. The coloured area represents a quarter of the regular gate array. The

corresponds to the top left corner of the plot. Obviously, the line width increases from the center of the array towards the corners. The right hand graph was taken from an improved

center of the array is located at the bottom right of the plot, the corner of the array

spacer deposition process, showing a narrower width distribution.

intuitive way of plotting this in-line measurement number is shown in Figure 9.

Flash. The hard mask is made for the line by space (LBS) scheme.

Width of liner + primary line + liner (nm) 129 128 127 126 125 124

**Wafer Center**  Array ~ 38..43 nm Edge ~ 44..48 nm

**Wafer Edge**  Array ~ 42..48 nm Edge ~ 43..51 nm

Width of liner + primary line + liner (nm) 132 131 130 129 128

In general, the gate length is critical, requiring LBS (line by spacer) for the gate level. Typical electrical parameters of relevance are:


In the case of a flash memory, another electrical parameter comes into play: the coupling ratio, which determines mainly the programming and erase characteristics of the flash transistors. The coupling ratio is affected by the capacitance between the floating gate and the active area, i.e. the CD variations of both the (floating) gate and the active area cause a spread in programming and erase performance.

As a result, a carefully controlled balance of the gate length in all kinds of chips is more important than the control of the gate spaces.
