**5. Conclusion**

Character projection lithography is one of promising projection methods for manufacturing application specific integrated circuits at a low cost. From the viewpoint of ASIC design, the number of EB shots, which reflects the manufacturing cost for ASICs, is reduced by (i) cell library generation and (ii) technology mapping.

Cell library generation consists of two parts: cell selection and character sizing. We presented a cell selection method (Sugihara et al., 2005, 2006a) and character sizing methods (Sugihara et al., 2006c, 2007b). Cell selection and character sizing achieved 72.0% reduction of EB shots with a feasible EB size in the best, comparing with the conventional and intuitional character sizing.

We also presented a technology mapping technique for reducing the number of EB shots in character projection lithography. Our technology mapping technique for the CP lithography has achieved a 54.6% less number of EB shots with 8.4% area increase under no timing constraints than the conventional one. Our technology mapping for the CP lithography has also achieved a 26.6% less number of EB shots with 41.1% area increase and without any performance degradation than the conventional one. Our experiments suggested that there exists a tradeoff between area and the number of EB shots.

Character Projection Lithography for Application-Specific Integrated Circuits 93

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