**4. Technology mapping technique for character projection equipment**

Technology mapping techniques were discussed for character projection lithography of a single-column-cell system (Sugihara et al., 2006b, 2007c). A technology mapping technique was also proposed for a multi-column-cell system (Sugihara et al., 2007a). This section mainly discusses a technology mapping technique which reduces projection time of a singlecolumn-cell system (Sugihara et al., 2006b, 2007c).

#### **4.1 Review on technology mapping**

In the most popular paradigm for logic synthesis, after a technology independent optimization of a set of logic equations, the result is mapped into a feasible circuit which is optimal with respect to area and satisfies a maximum critical-path delay. In this paradigm, the role of *technology mapping* is to finish the synthesis of the circuit by performing the final gate selection from a particular cell library. The role of technology mapping is the actual cell choice to implement the equations — for example, choosing the fastest cells along the critical path, and using the most area-efficient combination of cells off the critical path (Hachtel, 1996).

A set of base functions is chosen such as a two-input NAND-gate and an inverter. The logic equations are optimized in a technology-independent manner and are then converted into a graph where each node is restricted to one of the base functions. This graph is called the *subject graph*. The logic function for each library gate is also represented by a graph where

$$F\_{\quad} = \overline{(\overline{d+e})\cdot(\overline{a\cdot(b+h)+c})+f\cdot g\cdot h}. \tag{7}$$

$$\text{Area}\_{\text{all}} = \sum\_{l} \text{Ref}\_{l} \cdot \text{Area}\_{l\prime} \tag{8}$$

$$\text{Stbits}\_{\text{all}} = \sum\_{l} \text{Ref}\_{l} \cdot \text{Stbits}\_{l'} \tag{9}$$

$$
\alpha \cdot \text{Area}\_{\text{all}} + \mathcal{J} \cdot \text{Shots}\_{\text{all}\nu} \tag{10}
$$

Character Projection Lithography for Application-Specific Integrated Circuits 85

Synopsys ".lib" format), the numbers of EB shots which are needed to project an instance of every cell function with the CP and VSB lithographies, and the optimal projection method of every cell function. In the cell library file format specification for the Design Compiler, the attributes designating area, delay, and power can be specified for each cell function but the number of EB shots cannot be specified. The attribute "area" has been used to represent both area and the number of EB shots by setting the linear combination of them as the attribute "area" for making the Design Compiler capable of optimizing them. And then the ".lib" file of the cell library has been converted into the Synopsys ".db" format file with the

We have utilized two cell libraries, high-performance and low-power ones, which were provided by the VLSI Design and Education Center (VDEC) at the University of Tokyo, as conventional cell libraries. The technology node of the two cell libraries was 0.35 m. We have demagnified all patterns of the two cell libraries by a factor of 90/350 in order to simulate the number of EB shots at the 90 nm technology node. With the two conventional cell libraries, we have generated cell libraries specialized in the CP system whose specification is shown in Table 12. The numbers of cell functions, on-characters cell functions, and off-characters cell functions are described in Table 13. Note that the cell libraries were supplied from academia and the number of cell functions is smaller than commercial ones. This means that the usage of an industrial cell library increases the number of off-characters cell functions and possibly deteriorates the throughput of the

> The maximum width and height of rectangles for VSB 3.5 m The width and height of characters for CP 5.0 m

> > # cells # cells on

library 310 53 257

We examined the numbers of EB shots to project several benchmark circuits with the two

First, we examined the relation between area and the number of EB shots to project each of ITC'99 benchmark circuits (Davidson, 1999). In the examination, all circuits were logicsynthesized for two objectives: area-minimization (=1, =0 in Equation (8)) and EB-shotsminimization (=0, =1 in the equation). The purpose of this examination was to obtain the minimal values of both area and EB shots of all benchmark circuits. We logic-optimized each of circuits ten times and have taken the best value of area and EB shots among the results. Fig. 12 and Fig. 13 show area and shots ratios for both area-minimized logic synthesis (=1, =0) and shots-minimized one ( = 0, = 1) with the two cell libraries, respectively.

Low power cell library 310 101 209

characters
