**2.3 Case study**

74 Recent Advances in Nanofabrication Techniques and Applications

account, the number is 1, otherwise 0. Likewise, the second, third and fourth bits denote the

Conf. 2 (1,0,1,0)

799.5 × 792 N/A N/A N/A N/A 810 × 808.5 7.09 6.97 N/A N/A 819 × 808.5 7.37 7.43 N/A N/A 829.5 × 825 7.52 - N/A N/A 840 × 825 7.16 - N/A N/A 849 × 841.5 7.24 - N/A N/A 859.5 × 858 7.11 - N/A N/A 870 × 858 - - 7.15 N/A 879 × 874.5 - - 7.23 7.15

A number in each column denotes the delay time with the least area "N/A" means that the given areas were infeasible to place and route the circuit with the place-and-route tool. For example, the least area and the delay time for the area were obtained as 810 × 808.5 and 7.09 ns respectively in Conf. 1. The least areas in Confs. 1, 2, 3, and 4 were 810 × 808.5, 810 × 808.5, 870 × 858, and 879 × 874.5 respectively. About 14% area increased when the mirror-Y and the mirror-XY were forbidden. Theoretically speaking, delay time decreases under a case in which one can use a larger place-and-route area. Delay time in a column of the table is expected to decrease downward but it did not. This is because the CAD tool is based on approximate algorithm. Comparing the two values of Conf. 2, 6.6% delay time

Conf. 1 is the configuration in which all the four cell directions are available and is supposed to be best with regard to area and delay time among the configurations because its design space includes design space of the other configurations. In other words, any layout based on Confs. 2, 3 or 4 can be realized by Conf. 1. The results which the CAD tool reported does not straightforwardly reflect this supposition because the layouts obtained by the CAD tool are approximate solutions, e.g. the delay time of Conf. 2 (6.97 ns) was shorter than that of Conf.

Conf. 2 is the configuration in which the horizontal flippings are removed from Conf. 1. In other words, the mirror-X and mirror-XY directions are not taken into account in Conf. 2. There was no great difference of delay times among Confs. 1 and 2. Horizontal flipping

Conf. 3 is the configuration in which the vertical flippings (mirror-Y and mirror-XY) are removed from Conf. 1. Experimental results show that the vertical flipping of cells had little influence on delay time of the chip and it had some influence on the area. Comparing Conf. 3 with Conf. 1, about 14% area increased. This is because the gaps between cell areas were added by eliminating vertical flipping of cells and each cell area got to own its own power

Conf. 4 is the configuration in which any flipping cells are forbidden and only a basic direction of cells is available. Comparing Conf. 4 with Conf. 1, the differences of the delay

Delay times for four cell directional variations [ns], (basic, mirror-X, mirror-Y, mirror-XY)

> Conf. 3 (1,1,0,0)

Conf. 4 (1,0,0,0)

existences of the mirror-X, mirror-Y and mirror-XY directions respectively.

Conf. 1 (1,1,1,1)

Table 1. Delay times for four cell directional variations

increased while place-and-route area increased.

1 (7.09 ns) as the place-and-route area was 810 × 808.5!

seems not to be so effective to reduce delay time and area.

and ground lines.

Chip area

In this section, a case study is shown for five cases to examine the relation between the number of EB shots and how to select cell objects to place on characters. The five cases are described in Table 2. We developed the cell selection software described in Section 2.1.1 with a commercial mathematical optimization engine, ILOG CPLEX 9.0 (ILOG, 2003). Every optimization process finished within a second.


Table 2. Cell directional variations for experiments

The specification of the CP equipment for which we assumed is shown in Table 3. Two benchmark circuits were used to examine their numbers of EB shots under the five cases. The description for the benchmark circuits is shown in Table 4. Note that the cell library is from academia and comprises fewer kinds of cells than that from industry.


Table 3. Specification of CP/VSB equipment

Character Projection Lithography for Application-Specific Integrated Circuits 77

approximately under Cases 2 and 4 by assigning the equal number of characters to each

Comparing the number of EB shots of Circuit 1 under Case 2 with that under Case 4, 44% reduction of EB shots was achieved. Likewise, comparing the number of EB shots of Circuit 2 under Case 2 with that under Case 4, about 26% reduction of EB shots was achieved. It was experimentally found that the elimination of cell directions is quite effective to reduce EB shots. It was experimentally found that the elimination of horizontal flipping reduced the much number of EB shots effectively while it has small impact on area and delay time of

In this section, we proposed an ILP-based cell library development methodology to reduce the number of EB shots. All optimization processes finished within a second. More than 3.85% reduction of EB shots was achieved only by distinguishing between the differently

We examined the influence of cell directions on both area and delay time of the circuit. It was experimentally confirmed that both of the horizontal and vertical flipping of cells had little influence on delay time of chips. The horizontal flipping had little influence on area while the vertical flipping had some influence on area. This examination helps which cell

The forbiddance of horizontal flipping caused little deterioration of area while 25.6% reduction of EB shots. It was found that the forbiddance of horizontal flipping was effective to reduce the number of EB shots while it deteriorated little area and delay time of chips. The forbiddance of vertical flipping caused 13.9% increase of area while it caused less than 1% increase of delay time. The forbiddance of vertical flipping should be determined with taking a tradeoff between area and EB shots into account. For many chips of the state of the art, cells are placed so "loosely" that the deterioration of area caused by forbiddance of multi directions of cells might have less impact on area. The relation between cell directions

Character size optimization techniques were studied for character projection (Sugihara, 2006c, 2007b, 2010). We first presented an idea to optimize a character size for higher projection throughput (Sugihara et al., 2006c). We presented a character size optimization by enumerating all possible character sizes and generating a cell library for every given character size (Sugihara et al., 2006c). Next we presented a cell library development methodology in which a character size and a set of cells were optimized at the same time (Sugihara et al., 2007b). We also presented a character size optimization technique for multicolumn-cell projection equipment. In this section, we focus on the first work (Sugihara et al.,

In Section 2, the size of characters on CP masks was given and treated as a constant because of the restriction which attributes to character projection equipment. Cells used in a design were, consequently, partitioned to fit the constant size of characters by intuition. In this

and EB shots in design of such chips should be further examined as future work.

**3. Character size optimization for higher projection throughput** 

directions of cells.

**2.4 Conclusion** 

mirrored cells whose functions are identical.

2006c) for a simple explanation.

**3.1 Character size optimization problem** 

direction should be implemented on CP aperture masks.

chips.


Table 4. Benchmark circuits

The EB shots under the five cases were sought out by solving mathematical problem instances and are shown in Table 5. In the table, the parenthesized values show the numbers of cell objects. The areas and delay times of Circuit 2 are shown in Table 6. In our experiment, areas and delay times of Circuit 1 were not examined because the benchmark circuit was not logic-synthesizable.


Table 5. EB shots and cell objects


Table 6. Area and delay time of Circuit 2

According to Table 5, as the number of cell objects increases, in other words, the number of cell directions increases, the number of EB shots increases. This is because the reduction of cell directions enables more cell functions to be on a CP aperture mask and to be projected with the CP. The area of Circuit 2 under Case 1 was largest among the five cases as shown in Table 6 because only a single direction, that is a basic direction, was adopted for place-androute. This was because the gaps between cell areas came to arise and each cell area got to own its own power and ground lines. Theoretically speaking, the design with the four cell directions should be best among the five cases with regard to area and delay time. Similarly, the design with the two cell directions should be intermediate. The experimentally obtained values of areas do not reflect this supposition. The delay time of Circuit 2 under Cases 2 and 3 was found best. This is because the CAD tool returned approximate solutions of layout and happened to result against the supposition. Note that the values shown in Table 1 and Table 6 are nothing more than the ones the CAD tool reported. If a design obtained with the two cell directions is better than a design obtained with the four cell directions, the design of two-cell direction may be adopted as a design of four-cell direction.

Comparing the number of EB shots of Circuit 1 under Case 4 with that under Case 5, 3.85% reduction of the number of EB shots was achieved. The difference in the numbers of EB shots was caused by solving the problem instances exactly or approximately. The optimal sets of cells was selected exactly under Cases 3 and 5 while sets of cells was selected approximately under Cases 2 and 4 by assigning the equal number of characters to each directions of cells.

Comparing the number of EB shots of Circuit 1 under Case 2 with that under Case 4, 44% reduction of EB shots was achieved. Likewise, comparing the number of EB shots of Circuit 2 under Case 2 with that under Case 4, about 26% reduction of EB shots was achieved. It was experimentally found that the elimination of cell directions is quite effective to reduce EB shots. It was experimentally found that the elimination of horizontal flipping reduced the much number of EB shots effectively while it has small impact on area and delay time of chips.
