**5. Single-metal-layer flexible MEAs**

### **5.1. Fabrication**

Single-metal-layer parylene C-based electrode arrays are fabricated as shown in Figure 5. A photoresist sacrificial layer is optionally spun on a standard silicon wafer. Approximately 8 µm of parylene C is then vapor deposited in a PDS2010 system (Specialty Coating Systems, Indianapolis, IN, USA) on the entire wafer. An LOR3B photoresist layer (Microchem Corp., Newton, MA, USA) and an AZ1518 layer (AZ Electronic Materials, Branchburg, NJ, USA) are spun on top of the parylene, exposed in a 10X reduction GCA Mann 4800 DSW wafer stepper (General Signal Corporation, Stamford, CT, USA) or a Kasper 2001 contact aligner (Kasper Instruments, Inc., Sunnyvale, CA, USA) depending on the required resolution of the electrode array, and developed to achieve a liftoff pattern comprising contacts, conductive traces, and electrodes. After hard bake, approximately 2000 Å to 5000 Å of platinum, with or without a 200 Å titanium layer, is then e-beam evaporated (SE600 RAP, CHA Industries, Fremont, CA, USA) on the wafer. The subsequent photoresist strip generates the desired single-layer metallization pattern. An approximately 7 µm thick coating of parylene C is then deposited, followed by a spin coating of photoresist. This photoresist etch mask is exposed over the areas of the electrodes and contact pads and to pattern the overall array geometry, and the entire wafer is then subjected to an RIE in oxygen plasma, removing the parylene insulation over the electrodes and the parylene surrounding the array. The photoresist mask is then removed with solvent. Finally, if a sacrificial photoresist layer was used, the array is released from the substrate in an acetone bath. If no sacrificial layer was used, it is peeled from the silicon in a water bath. Ultimately, for most cases, the sacrificial photoresist layer is unnecessary, and can often complicate array fabrication due to cracking while under process. The arrays can be easily released from a natively oxidized silicon surface by placing them in a deionized water bath and peeling them from their edge. The water will then release the rest of the structure due to the hydrophobicity of the underlying parylene surface.

A single-layer square-grid electrode array, consisting of 256 Ti/Pt thin-film electrodes 125 µm in diameter in a 16 × 16 grid with connecting lines of 12 µm pitch fabricated in the manner of Figure 5 is shown in Figure 6. An SEM highlighting the typical electrode morphology in such structures is shown in Figure 7. As can be seen, the parylene covering the electrode has been completely removed, whereas the incoming trace remains conformally coated with the material.

Flexible Circuit Technologies for Biomedical Applications http://dx.doi.org/10.5772/55308 11


**Figure 5.** Fabrication process for parylene-based single-metal-layer flexible MEAs.

for an intraocular retinal prosthesis and other ocular implants, and paved the way for the design and fabrication of a flexible electrode arrays and a packaging system using parylene C as the primary substrate. Given these biocompatibility results, we have also been investigating parylene in several other ocular implants, with excellent results to date [42-44]. Similar experiments were performed with parylene C implanted on the spinal cord of mice. The arrays

Single-metal-layer parylene C-based electrode arrays are fabricated as shown in Figure 5. A photoresist sacrificial layer is optionally spun on a standard silicon wafer. Approximately 8 µm of parylene C is then vapor deposited in a PDS2010 system (Specialty Coating Systems, Indianapolis, IN, USA) on the entire wafer. An LOR3B photoresist layer (Microchem Corp., Newton, MA, USA) and an AZ1518 layer (AZ Electronic Materials, Branchburg, NJ, USA) are spun on top of the parylene, exposed in a 10X reduction GCA Mann 4800 DSW wafer stepper (General Signal Corporation, Stamford, CT, USA) or a Kasper 2001 contact aligner (Kasper Instruments, Inc., Sunnyvale, CA, USA) depending on the required resolution of the electrode array, and developed to achieve a liftoff pattern comprising contacts, conductive traces, and electrodes. After hard bake, approximately 2000 Å to 5000 Å of platinum, with or without a 200 Å titanium layer, is then e-beam evaporated (SE600 RAP, CHA Industries, Fremont, CA, USA) on the wafer. The subsequent photoresist strip generates the desired single-layer metallization pattern. An approximately 7 µm thick coating of parylene C is then deposited, followed by a spin coating of photoresist. This photoresist etch mask is exposed over the areas of the electrodes and contact pads and to pattern the overall array geometry, and the entire wafer is then subjected to an RIE in oxygen plasma, removing the parylene insulation over the electrodes and the parylene surrounding the array. The photoresist mask is then removed with solvent. Finally, if a sacrificial photoresist layer was used, the array is released from the substrate in an acetone bath. If no sacrificial layer was used, it is peeled from the silicon in a water bath. Ultimately, for most cases, the sacrificial photoresist layer is unnecessary, and can often complicate array fabrication due to cracking while under process. The arrays can be easily released from a natively oxidized silicon surface by placing them in a deionized water bath and peeling them from their edge. The water will then release the rest of the structure due to

A single-layer square-grid electrode array, consisting of 256 Ti/Pt thin-film electrodes 125 µm in diameter in a 16 × 16 grid with connecting lines of 12 µm pitch fabricated in the manner of Figure 5 is shown in Figure 6. An SEM highlighting the typical electrode morphology in such structures is shown in Figure 7. As can be seen, the parylene covering the electrode has been completely removed, whereas the incoming trace remains conformally coated with the

were well tolerated, with no obvious immune reaction or gliosis.

10 Advances in Micro/Nano Electromechanical Systems and Fabrication Technologies

**5. Single-metal-layer flexible MEAs**

the hydrophobicity of the underlying parylene surface.

**5.1. Fabrication**

material.

**Figure 6.** Photograph of Ti/Pt electrode array of 256 electrodes and lines of 12 µm pitch.

**Figure 7.** SEM of electrode morphology showing parylene C insulation surrounding exposed metal electrode.
