**2.4. Nanowire conductivity**

deposited alloy, and in this study, was varied from pH = 1.8 to 5.0 by carefully titrating the solution with 3M NaOH (aq) solution. With respect to deposition potential, a potentiodynamic program was used to drive deposition. Previous studies by our group have shown that changing the potential range impacts the compositional ratio of Pt:Ir [25]. Specifically the potential range was cycled over a 150mV potential range, e.g. between U = 0.0 V to -0.15 V vs.

Nanowires were isolated from the AAO templates, Figure 4, for further analysis of the nanowire properties. The electrodeposited AAO templates with embedded nanowires were immersed in an aqueous solution of 3M NaOH(aq) to dissolve the oxide membrane. The nanowire suspension was allowed to stand, to settle the nanowires out of the basic solution. Excess solution (supernatant) was carefully pipetted off and DI water was added to the vial to neutralize the remaining supernatant's pH. This process was repeated three times until a neutral solution was achieved. Nanowires in suspension were then pipetted onto either fresh, un-sputtered AAO filters to capture for SEM or onto TEM mesh grids for TEM analysis.

**Figure 4.** Schematic of the isolation process used to separate electrodeposited nanowires from AAO templates. Draw‐

All scanning electron microscopy imaging was performed using a field emission scanning

Tranmission electron microscopy was used to further characterize nanowire morphology and microstructure. Isolated nanowires were captured on carbon coated copper grids with 300 mesh size (Ted Pella Inc.) and imaged using a JEOL 2100 (Japan) TEM. Brightfield and darkfield images as well as diffraction patterns were captured. Images were taken on the edges of the nanowires, at the thinner branches (*ɸ* = 20 nm) to ensure transmission of the electron beam through the samples. Diffraction patterns were taken using beam widths smaller than the width of the nanowires, to minimize probability of outside contributions to measured patterns.

**2.3. Electron microscopy (SEM & TEM) characterization**

electron microscope (ZEISS 1550VP) with an accelerating voltage of 4 kV.

Ag/AgCl. The ranges used are listed in Table 1.

212 Advances in Micro/Nano Electromechanical Systems and Fabrication Technologies

**2.2. Nanowire isolation**

ing not to scale.

Electrical conductivity measures were taken on individual nanowires trapped across litho‐ graphically patterned electrical contacts [26]. In this process, a silicon wafer is masked with photoresist that has been patterned into an array of source-sink contact strip pairs. A sourcesink pair consist of two, macro-scale, square contacts, each with a single lead approximately 4 mm in thickness and 10 mm in length extending towards the complimentary pad. The two parallel whiskers are separated by a 2 mm gap of patterned photoresist.

To prepare a single sample for testing, a suspension of nanowires in methanol is pipetted onto the substrate surface and the solvent is allowed to evaporate. Nanowires stick preferentially to the photoresist mask and not to the silicon wafer surface. Once dried, each source-sink pair is reviewed via SEM imaging to identify if any source-sink pair has a single nanowire trapped on the photoresist and also is bridged between the source lead whiskers and the sink lead whisker, Figure 5. Successful preparations are labeled, and the whole wafer is then sputter coated with Ti (*h* = 5 nm) adhesion and Au (*h* = 50 nm). After metalization, photoresist is lifted off, leaving behind the source-sink leads/contacts in gold, with bridging nanowires pinned between the Ti/Au layer and the silicon wafer.

Once prepared a voltage bias was applied across the contacts and current was measured through the leads. Electron transport measurements were performed using an Agilent 4156B semiconductor parameter analyzer. Current-voltage curves were generated to characterize nanowire resistivity.

**Figure 5.** Schematics showing three steps used to MEMS fabricate nanowire resisitivity test system. A photoresist mask (blue) is spin coated and patterned onto a silicon substrate (gray) and nanowires are dispersed from suspension until a source/sink pair trap a wire. Metallization (center) with a gold layer followed by liftoff (right) leaves patterned leads holding the nanowires in place for testing.

**Figure 5**. Schematics showing three steps used to MEMS fabricate nanowire resisitivity test system. A photoresist mask (blue) is spin coated and patterned onto a silicon substrate (gray) and nanowires are dispersed from suspension until a source/sink pair trap a wire. Metallization (center) with a gold layer followed by liftoff (right) leaves patterned leads holding the nanowires in place for testing.
