**3.1. Resonant MEMS magnetic field sensor**

Beam width (w)

gap (g)

(a) The square structure illustrating the large opening undercut rule 

Square width (w)

132 Advances in Micro/Nano Electromechanical Systems and Fabrication Technologies

Beam width (w)

(b) The cantilever structure illustrating the gap undercut rule 

gap (g)

Hole separation

(c) The plate structure illustrating the hole undercut rule

Hole size

Fig. 16: Layout of three test structures used for extracting MEMS design rules for post-CMOS micromachining.

**Figure 16.** Layout of three test structures used for extracting MEMS design rules for post-CMOS micromachining.

The post-CMOS process steps of the resonant magnetic field sensor using DRIE were designed to successfully release the sensor structure. The first step in the post-CMOS process was at wafer level with the selective application of photoresist at the back-side of the 8" inch silicon wafer to etch from the back-side to produce a substrate thickness of approximately 50 µm as shown in Fig.17. DRIE was performed using SS110A Tegal plasma etcher to anisotropically etch the silicon substrate to the desired thickness.

Fig. 17: (a) Optical image of back side Si etching at wafer level, (b) Backside optical image of a chip and (c) FESEM of backside of a sensor. **Figure 17.** a) Optical image of back side Si etching at wafer level, (b) Backside optical image of a chip and (c) FESEM of backside of a sensor.

Optical microscope was used to estimate the thickness of the Si substrate during the etching process. Fig.17 (c) shows the back-side view of one of the sensors that has been successfully etched to approximately 284 µm depth leaving a about 50 µm thickness under the CMOS layers. From the back-side etching of the bulk silicon, the silicon etching rate was found to be ~3.66 µm/min. The second step was dicing the wafer as shown in Fig. 18 (a). Dicing of the wafer has to be done before the front side RIE of SiO2 and DRIE of silicon is implemented. This sequence was followed in order to prevent the breakage of the released structures. Optical microscope was used to estimate the thickness of the Si substrate during the etching process. Fig.17 (c) shows the back-side view of one of the sensors that has been successfully etched to approximately 284 µm depth leaving a about 50 µm thickness under the CMOS layers. From the back-side etching of the bulk silicon, the silicon etching rate was found to be ~3.66 µm/min. The second step was dicing the wafer as shown in Fig. 18 (a). Dicing of the wafer has to be done before the front side RIE of SiO2 and DRIE of silicon is implemented. This sequence was followed in order to prevent the breakage of the released structures.

Pads Test structure The third process was SiO2 RIE on the diced chip shown in Fig. 18 (b), which was performed from the front-side of the chip using Tegal plasma etcher. Front side RIE process opened the pattern of the resonant magnetic sensor by removing the SiO2 layer and thus exposing the silicon underneath while the MEMS sensor pattern was maintained by metal 3 acting as a mask

Fig. 18: (a) Optical image of the diced wafer and (b) optical image of front side of a 5 mm × 5 mm chip.

(a) (b)

to prevent the breakage of the released structures.

(a) (b) (c)

Fig. 17: (a) Optical image of back side Si etching at wafer level, (b) Backside optical image of a chip and (c) FESEM of backside of a sensor.

Optical microscope was used to estimate the thickness of the Si substrate during the etching process. Fig.17 (c) shows the back-side view of one of the sensors that has been successfully etched to approximately 284 µm depth leaving a about 50 µm thickness under the CMOS layers. From the back-side etching of the bulk silicon, the silicon etching rate was found to be ~3.66 µm/min. The second step was dicing the wafer as shown in Fig. 18 (a). Dicing of the wafer has to be done before

Fig. 18: (a) Optical image of the diced wafer and (b) optical image of front side of a 5 mm × 5 mm **Figure 18.** a) Optical image of the diced wafer and (b) optical image of front side of a 5 mm × 5 mm chip.

for the pattern. The process at chip level started by flipping over the chips such that the thin film was now on the front side. The chips were then attached to the 8" platinum coated carrier wafer using kapton tape as illustrated in Fig.19. After 13 minutes of etching, a gray colour (silicon colour) appeared in the trenches that indicated the completion of SiO2 etching. The test structures to the right of the sensor beam were used to estimate SiO2 etching rate and to avoid over-etch of the SiO2 material as shown in Fig.18 (b). The total SiO2 etching depth was approximately 5 µm. The third process was SiO2 RIE on the diced chip shown in Fig. 18 (b), which was performed from the front-side of the chip using Tegal plasma etcher. Front side RIE process opened the pattern of the resonant magnetic sensor by removing the SiO2 layer and thus exposing the silicon underneath while the MEMS sensor pattern was maintained by metal 3 acting as a mask for the pattern. The process at chip level started by flipping over the chips such that the thin film was now on the front side. The chips were then attached to the 8" platinum coated carrier wafer using kapton tape as illustrated in Fig.19. After 13 minutes of etching, a gray colour (silicon colour) appeared in the trenches that indicated the completion of SiO2 etching. The test structures to the right of the sensor beam were used to estimate SiO2 etching rate and to avoid over-etch of the SiO2 material as shown in Fig.18 (b) . The

chip.

Fig. 19: Sample preparation for front side etching

obtained from previous backside DRIE etching of silicon. The thickness of the central shuttle and long beams was approximately 50 µm, which was observed under optical microscope during backside etching. Therefore the test structures on the chip were used as reference. Fig.20 shows FESEM micrograph of the fabricated sensor with inset showing a close-up of the comb fingers and part of dummy structure close to the beams that has fallen out while others still remain intact on the substrate [10]. Additional 3 more minutes were required to fully etch-through. This happened when all the

dummy structures dropped and indicated that the etched-through process was completed.

Next, front-side bulk silicon DRIE process step was performed using the etching rate of 3.66 µm/min **Figure 19.** Sample preparation for front side etching

total SiO2 etching depth was approximately 5 µm.

Next, front-side bulk silicon DRIE process step was performed using the etching rate of 3.66 µm/min obtained from previous backside DRIE etching of silicon. The thickness of the central shuttle and long beams was approximately 50 µm, which was observed under optical micro‐ scope during back-side etching. Therefore the test structures on the chip were used as reference. Fig.20 shows FESEM micrograph of the fabricated sensor with inset showing a closeup of the comb fingers and part of dummy structure close to the beams that has fallen out while others still remain intact on the substrate [10]. Additional 3 more minutes were required to fully etch-through. This happened when all the dummy structures dropped and indicated that the etched-through process was completed.

Fig. 20: FESEM image of the fabricated CMOS-MEMS resonant magnetic field sensor with inset showing shuttle and stator fingers. **Figure 20.** FESEM image of the fabricated CMOS-MEMS resonant magnetic field sensor with inset showing shuttle and stator fingers.

#### **3.2 Resonant MEMS Chemical sensor 3.2. Resonant MEMS chemical sensor**

for the pattern. The process at chip level started by flipping over the chips such that the thin film was now on the front side. The chips were then attached to the 8" platinum coated carrier wafer using kapton tape as illustrated in Fig.19. After 13 minutes of etching, a gray colour (silicon colour) appeared in the trenches that indicated the completion of SiO2 etching. The test structures to the right of the sensor beam were used to estimate SiO2 etching rate and to avoid over-etch of the SiO2 material as shown in Fig.18 (b). The total SiO2 etching depth was

Fig. 18: (a) Optical image of the diced wafer and (b) optical image of front side of a 5 mm × 5 mm chip.

(a) (b)

**Figure 18.** a) Optical image of the diced wafer and (b) optical image of front side of a 5 mm × 5 mm chip.

(a) (b) (c)

Fig. 17: (a) Optical image of back side Si etching at wafer level, (b) Backside optical image of a chip and (c) FESEM of backside of a sensor.

Optical microscope was used to estimate the thickness of the Si substrate during the etching process. Fig.17 (c) shows the back-side view of one of the sensors that has been successfully etched to approximately 284 µm depth leaving a about 50 µm thickness under the CMOS layers. From the back-side etching of the bulk silicon, the silicon etching rate was found to be ~3.66 µm/min. The second step was dicing the wafer as shown in Fig. 18 (a). Dicing of the wafer has to be done before the front side RIE of SiO2 and DRIE of silicon is implemented. This sequence was followed in order

The third process was SiO2 RIE on the diced chip shown in Fig. 18 (b), which was performed from the front-side of the chip using Tegal plasma etcher. Front side RIE process opened the pattern of the resonant magnetic sensor by removing the SiO2 layer and thus exposing the silicon underneath while the MEMS sensor pattern was maintained by metal 3 acting as a mask for the pattern. The process at chip level started by flipping over the chips such that the thin film was now on the front side. The chips were then attached to the 8" platinum coated carrier wafer using kapton tape as illustrated in Fig.19. After 13 minutes of etching, a gray colour (silicon colour) appeared in the trenches that indicated the completion of SiO2 etching. The test structures to the right of the sensor beam were used to estimate SiO2 etching rate and to avoid over-etch of the SiO2 material as shown in Fig.18 (b) . The

Test structure

Fig. 19: Sample preparation for front side etching

Kapton tape

Pads

Chips

Next, front-side bulk silicon DRIE process step was performed using the etching rate of 3.66 µm/min obtained from previous backside DRIE etching of silicon. The thickness of the central shuttle and long beams was approximately 50 µm, which was observed under optical microscope during backside etching. Therefore the test structures on the chip were used as reference. Fig.20 shows FESEM micrograph of the fabricated sensor with inset showing a close-up of the comb fingers and part of dummy structure close to the beams that has fallen out while others still remain intact on the substrate [10]. Additional 3 more minutes were required to fully etch-through. This happened when all the

dummy structures dropped and indicated that the etched-through process was completed.

approximately 5 µm.

8" platinum coated carrier wafer

total SiO2 etching depth was approximately 5 µm.

to prevent the breakage of the released structures.

134 Advances in Micro/Nano Electromechanical Systems and Fabrication Technologies

**Figure 19.** Sample preparation for front side etching

In resonant MEMS chemical sensors, known as gravimetric sensors, the principle of detection of the gaseous species is based on the change in resonant frequency of the microresonator membrane or plate. This frequency change results from a change in the mass of the microresonator due to absorption/adsorption of an analyte molecule onto the surface of the active material deposited on it. Fig. 21 shows 2-D schematic diagram of the chemical microsensor device. In resonant MEMS chemical sensors, known as gravimetric sensors, the principle of detection of the gaseous species is based on the change in resonant frequency of the microresonator membraneorplate.This frequencychange results froma change inthemassofthemicroresona‐ tor due to absorption/adsorption of an analyte molecule onto the surface of the active material deposited on it. Fig. 21 shows 2-D schematic diagram of the chemical microsensor device.

The post-CMOS micromachining process steps of the resonant MEMS chemical sensor were similar to the process steps of the resonant MEMS magnetic field sensor. The process started with the selective application of photoresist at the back-side of the die around the sensor followed by sample placement on the platinum coated carrier wafer. The second step of the process was to perform back-side silicon DRIE to achieve proof mass thickness of approxi‐ mately 40 µm. The same plasma silicon etcher was used to anisotropically etch the silicon substrate to the desired thickness. Fig. 22 shows the FESEM image of the successfully released MEMS chemical sensor with the inset showing a close-up view of the perfectly flat sensing comb fingers with the SCS underneath [15].

Fig. 21: 2-D Schematic of the resonant MEMS chemical sensor

The post-CMOS micromachining process steps of the resonant MEMS chemical sensor were similar to the process steps of the resonant MEMS magnetic field sensor. The process started with the selective application of photoresist at the back-side of the die around the sensor followed by sample Fig. 21 shows 2-D schematic diagram of the chemical microsensor device.

**3.2 Resonant MEMS Chemical sensor**

Dummy Structures

Fig. 20: FESEM image of the fabricated CMOS-MEMS resonant magnetic field sensor with inset showing shuttle and stator fingers.

In resonant MEMS chemical sensors, known as gravimetric sensors, the principle of detection of the gaseous species is based on the change in resonant frequency of the microresonator membrane or

FESEM image of the successfully released MEMS chemical sensor with the inset showing a close-up view of the perfectly flat sensing comb fingers with the SCS underneath [15]. Fig. 21: 2-D Schematic of the resonant MEMS chemical sensor **Figure 21.** D Schematic of the resonant MEMS chemical sensor

of micromechanical devices using 0.35 µm CMOS technology.

Fig. 22: FESEM image of fabricated device with inset showing a close-up view of the fingers with the SCS underneath **Figure 22.** FESEM image of fabricated device with inset showing a close-up view of the fingers with the SCS underneath

### **Conclusion 4. Conclusion**

**Acknowledgment**

No.04-02-02-SF0095.

*System*s, Vol. 16, 5, pp. 1152-1161.

**References**

CMOS MEMS bulk micromachining. The chapter was divided into three sections. In the first section an introduction to bulk micromachining of silicon and isotropic and anisotropic wet and dry etching was given. The second section discussed briefly DRIE post-CMOS micromachining process with particular emphasis on DRIE post-CMOS bulk micromachining process and the third and last section provides a few examples of devices fabricated by our research group using the DRIE CMOS-MEMS process. These devices were resonant MEMS magnetic field sensor and resonant MEMS chemical sensor. The aim of the chapter was to discuss and analyze practical processes involved in the design This chapter discussed bulk micromachining technology with particular emphases on DRIE post CMOS MEMS bulk micromachining. The chapter was divided into three sections. In the first section an introduction to bulk micromachining of silicon and isotropic and anisotropic wet and dry etching was given. The second section discussed briefly DRIE post-CMOS micromachining process with particular emphasis on DRIE post-CMOS bulk micromachining process and the third and last section provides a few examples of devices fabricated by our

The authors would like to thank MIMOS Bhd Malaysia for facilitating the microfabrication of the sensors and MOSTI Malaysia for financially supporting this research under E-Science project

[1]. Hongwei Qu and Huikai Xie, "Process Development for CMOS-MEMS Sensors with Robust Isolated Bulk Silicon Microstructures", *IEEE/ASME Journal of Micro-Electro-Mechanical* 

This chapter discussed bulk micromachining technology with particular emphases on DRIE post

research group using the DRIE CMOS-MEMS process. These devices were resonant MEMS magnetic field sensor and resonant MEMS chemical sensor. The aim of the chapter was to discuss and analyze practical processes involved in the design of micromechanical devices using 0.35 µm CMOS technology.
