**9. Chip-level integrated interconnect technology**

### **9.1. Introduction**

Despite our ability to fabricate such a large number of electrodes in such a small area, a significant impediment to future progress is the problem of how to package and interconnect these multielectrode arrays with foundry-fabricated ASICs, discrete components (e.g., chip capacitors, oscillators, diodes) and RF coils in a way that provides for high lead-count interconnects. A wafer-level process is cost prohibitive, as it is necessary to maximize the area of a wafer devoted to IC processing to keep costs low. Furthermore, current technologies for packaging would be far too tedious and low yield to apply to a 1000-electrode device. In order to achieve our goal of a 1000-electrode retinal prosthesis and a high-density spinal cord stimulation system, then, a new way of forming such a package so as to enable high-lead-count integration is necessary.

We have invented a way to place prefabricated chips, manufactured, for example, at a foundry, into the fabrication process of a parylene-based multielectrode array and/or RF coil, such that all interconnections to the chip are made using standard photolithography and standard microfabrication techniques in a fully scalable manner [40]. This packaging scheme is known as the chip-level integrated interconnect (CL-I2 ) package. Figure 26 shows an overview of the fabrication process and how multiple chips could be joined together in this manner. A detailed discussion of the fabrication process, as adapted from [40], follows.

**Figure 26.** Overview of the CL-I2 process. Multiple chip connections are possible.

### **9.2. Fabrication**

**Figure 25.** Magnitude of the electrochemical impedances at 1 kHz of an unplated and plated electrode over time. The unplated electrode showed a dramatic increase in impedance around day 30, at which time the test was stopped, whereas the plated electrode showed steady impedance through day 50. The arrow denotes a temporary dip in impe‐

Despite our ability to fabricate such a large number of electrodes in such a small area, a significant impediment to future progress is the problem of how to package and interconnect these multielectrode arrays with foundry-fabricated ASICs, discrete components (e.g., chip capacitors, oscillators, diodes) and RF coils in a way that provides for high lead-count interconnects. A wafer-level process is cost prohibitive, as it is necessary to maximize the area of a wafer devoted to IC processing to keep costs low. Furthermore, current technologies for packaging would be far too tedious and low yield to apply to a 1000-electrode device. In order to achieve our goal of a 1000-electrode retinal prosthesis and a high-density spinal cord stimulation system, then, a new way of forming such a package so as to enable high-lead-count

We have invented a way to place prefabricated chips, manufactured, for example, at a foundry, into the fabrication process of a parylene-based multielectrode array and/or RF coil, such that

**9. Chip-level integrated interconnect technology**

26 Advances in Micro/Nano Electromechanical Systems and Fabrication Technologies

dance due to CV scanning.

**9.1. Introduction**

integration is necessary.

Three MOSIS-fabricated ASICs, as well as seven chips fabricated to simulate them (with circuitry that facilitated testing), were used to demonstrate the CL-I2 packaging technology. In order to fabricate the replicas of the MOSIS chips, these chips were imaged using a WYKO interferometer (Veeco Instruments Inc., Woodbury, NY, USA), and were found to have mean dimensions of 2.500 mm in length, 2.617 mm in width, and 254.2 µm in total thickness.

One hundred angstroms of chrome and 2000 Å of gold were e-beam evaporated on a 260 µm thick silicon wafer. Using a photoresist mask, the metal was wet etched to pattern pads of the same size and in the same locations as on the MOSIS-fabricated chips (approximately 70–100 × 100 µm2 with a center-to-center pad spacing of approximately 200 µm), as well as a pattern of short circuits connecting these pads to nearby pads. After stripping the photoresist, a second photoresist layer was spun on the wafer and patterned as a mask for a Bosch through-wafer etch in a PlasmaTherm SLR-770B deep reactive ion etching (DRIE) system (Unaxis Corpora‐ tion, St. Petersburg, FL, USA). This etch defined the length, width, and thickness of the simulated chips as 2.49 mm, 2.61 mm, and 260 µm, respectively. Finally, the photoresist mask was removed from the individual chips. In this manner, chips comprising simple electrical shorts and intrinsic resistors were fabricated as our primary CL-I2 package test structures (Figure 27.)

**Figure 27.** MOSIS ASIC (left) next to test chip (right).

The only properties of these prefabricated chips that had to be known before incorpora‐ tion in the CL-I2 process were their overall length, width, and thickness, and the dimen‐ sions and locations of the contact pads. Figure 28 gives a detailed CL-I2 process flow. To begin, shallow alignment marks are etched into a standard 550 µm thick silicon wafer using a thin photoresist mask and an SF6 plasma. 2.51 × 2.63 mm2 holes are then patterned after alignment in a 10X reduction stepper in thick photoresist and an optional silicon dioxide mask. Through holes are then etched using the Bosch DRIE process. After photoresist and oxide removal, Nitto tape is placed on the frontside of the wafer. The chips are then selfaligned in the holes by inserting them from the backside (the Nitto tape enables front‐ side planarization whereas the lateral dimensions of the etched cavity determine lateral displacement), and they are sealed in place using several drops of sacrificial photoresist to cover the backside of the chip and to fill the gaps around it. A subsequent approximate‐ ly 12 µm thick parylene C deposition in a PDS2010 mechanically anchors the chips in place from the backside. After removal of the frontside parylene by peeling off the Nitto tape, vertical displacements of the chips are measured using a stylus profilometer (Alphastep 200 and P-15, KLA-Tencor, San Jose, CA, USA).

The parylene-based flexible electrodes, or, in this implementation, contact pads for electrical testing, are then fabricated on this wafer as if it were a whole wafer with prefabricated integrated circuitry. First, a photoresist sacrificial layer is spun on the wafer and patterned to

**Figure 28.** Detailed process flow for CL-I2 package fabrication.

photoresist layer was spun on the wafer and patterned as a mask for a Bosch through-wafer etch in a PlasmaTherm SLR-770B deep reactive ion etching (DRIE) system (Unaxis Corpora‐ tion, St. Petersburg, FL, USA). This etch defined the length, width, and thickness of the simulated chips as 2.49 mm, 2.61 mm, and 260 µm, respectively. Finally, the photoresist mask was removed from the individual chips. In this manner, chips comprising simple electrical shorts and intrinsic resistors were fabricated as our primary CL-I2 package test structures

28 Advances in Micro/Nano Electromechanical Systems and Fabrication Technologies

The only properties of these prefabricated chips that had to be known before incorpora‐ tion in the CL-I2 process were their overall length, width, and thickness, and the dimen‐ sions and locations of the contact pads. Figure 28 gives a detailed CL-I2 process flow. To begin, shallow alignment marks are etched into a standard 550 µm thick silicon wafer using a thin photoresist mask and an SF6 plasma. 2.51 × 2.63 mm2 holes are then patterned after alignment in a 10X reduction stepper in thick photoresist and an optional silicon dioxide mask. Through holes are then etched using the Bosch DRIE process. After photoresist and oxide removal, Nitto tape is placed on the frontside of the wafer. The chips are then selfaligned in the holes by inserting them from the backside (the Nitto tape enables front‐ side planarization whereas the lateral dimensions of the etched cavity determine lateral displacement), and they are sealed in place using several drops of sacrificial photoresist to cover the backside of the chip and to fill the gaps around it. A subsequent approximate‐ ly 12 µm thick parylene C deposition in a PDS2010 mechanically anchors the chips in place from the backside. After removal of the frontside parylene by peeling off the Nitto tape, vertical displacements of the chips are measured using a stylus profilometer (Alphastep

The parylene-based flexible electrodes, or, in this implementation, contact pads for electrical testing, are then fabricated on this wafer as if it were a whole wafer with prefabricated integrated circuitry. First, a photoresist sacrificial layer is spun on the wafer and patterned to

(Figure 27.)

**Figure 27.** MOSIS ASIC (left) next to test chip (right).

200 and P-15, KLA-Tencor, San Jose, CA, USA).

expose the chip's surface. After baking to remove excess solvent, approximately 3 µm of parylene C is deposited on the entire wafer. Photoresist is spun on the wafer, exposed in the 10X reduction stepper, and developed to pattern etch holes above the on-chip pads, similar to the vias in the dual metal-layer process. This pattern is transferred into the parylene using an O2 plasma in an RIE system, exposing the metal of these on-chip pads. Two hundred angstroms of titanium and 2000 Å of gold are deposited in the e-beam evaporation system using optimized step coverage, and patterned (using a photoresist mask and wet etching) to define the remote contact pads and remote pad to on-chip pad interconnects. The top photoresist is stripped, and a second layer of approximately 10 µm of parylene C is deposited and patterned as before, but this time to open the remote pads/electrodes to enable electrical testing. Finally, all photoresist, including the sacrificial layer, is removed by soaking the wafer in acetone, releasing a flexible parylene skin with embedded interconnects to the packaged ASIC. The host wafer can be substituted in the process with a precisely machined substrate, and can be reused after this release step. It is also important to note that the ASIC or discrete component can be of any thickness, but generally the thickness should be less than that of the host wafer or machined substrate, and it can have parylene or any hermetic coating deposited on it *a priori*, provided that the chip contacts can be opened using microfabrication techniques before the interconnect metal is laid down and patterned (Figure 28 steps 8 and 9). Thus, this technology combines the best aspects of chip-level packaging, in which every surface of the prefabricated chip can be manipulated or coated beforehand, and wafer-level packaging, in that photolithography and microfabrication can be performed on the surface after such chip-level techniques.

### **9.3. Integration testing results**

We successfully performed photolithography on ten prefabricated stand-alone chips using this paradigm: seven test chips (three conformally coated in parylene *a priori*) and three MOSISfabricated chips (one coated in parylene *a priori*). A MOSIS chip anchored in place in the host substrate is shown centrally in Figure 29 with the host wafer shown on the perimeter. As is expected, minimizing vertical displacement of the ASIC from the wafer surface is crucial for further photolithography steps. Figure 30 gives typical surface profiles of all ten chips with respect to the surrounding host wafer, and indicates that for most chips, this vertical displace‐ ment was less than 5 µm after removal of the frontside Nitto tape. Photolithography on the somewhat anomalous test chips 2 and 7, however, was also successful.

The accurate horizontal alignment of the perimeter interconnects to the embedded chips is shown in Figure 31, with Figure 32 giving a detailed micrograph of a single interconnect for both the test chip (a) and the MOSIS chip (b). By design, the chips should be self-aligned to within 10 µm of lateral displacement; some chips were aligned far better than this, however others were misaligned worse than this. With tighter tolerances on the cavity sidewalls, or with chip-alignment lithographic equipment, this alignment error could be improved. The embed‐ ded chip with remote contact pads is shown in Figure 33, and Figure 34 depicts the flexibility of this package. Functional contacts to the chips were verified as described in [40].

**Figure 29.** MOSIS chip (center) shown anchored in host silicon substrate (perimeter).

be manipulated or coated beforehand, and wafer-level packaging, in that photolithography and microfabrication can be performed on the surface after such chip-level techniques.

We successfully performed photolithography on ten prefabricated stand-alone chips using this paradigm: seven test chips (three conformally coated in parylene *a priori*) and three MOSISfabricated chips (one coated in parylene *a priori*). A MOSIS chip anchored in place in the host substrate is shown centrally in Figure 29 with the host wafer shown on the perimeter. As is expected, minimizing vertical displacement of the ASIC from the wafer surface is crucial for further photolithography steps. Figure 30 gives typical surface profiles of all ten chips with respect to the surrounding host wafer, and indicates that for most chips, this vertical displace‐ ment was less than 5 µm after removal of the frontside Nitto tape. Photolithography on the

The accurate horizontal alignment of the perimeter interconnects to the embedded chips is shown in Figure 31, with Figure 32 giving a detailed micrograph of a single interconnect for both the test chip (a) and the MOSIS chip (b). By design, the chips should be self-aligned to within 10 µm of lateral displacement; some chips were aligned far better than this, however others were misaligned worse than this. With tighter tolerances on the cavity sidewalls, or with chip-alignment lithographic equipment, this alignment error could be improved. The embed‐ ded chip with remote contact pads is shown in Figure 33, and Figure 34 depicts the flexibility

of this package. Functional contacts to the chips were verified as described in [40].

somewhat anomalous test chips 2 and 7, however, was also successful.

30 Advances in Micro/Nano Electromechanical Systems and Fabrication Technologies

**Figure 29.** MOSIS chip (center) shown anchored in host silicon substrate (perimeter).

**9.3. Integration testing results**

**Figure 30.** Typical single-axis vertical displacements of all 10 chips after mechanical anchoring in the host wafer (Fig‐ ure 28, step 4), where the top surface of the wafer corresponds to 0 µm.

**Figure 31.** Embedded chip with fabricated perimeter interconnects (numbered traces connect to numbered remote pads shown in Figure 33).

**Figure 32.** (a) Example of <10 µm lateral misalignment of a test chip; (b) Example of >10 µm lateral misalignment of a MOSIS chip.

**Figure 33.** A CL-I2 packaged chip shown resting on a penny.

**Figure 34.** Demonstrates flexibility of CL-I2 package. Chip can be seen underlying overlying parylene "skin."

### **9.4. Discussion**

**Figure 32.** (a) Example of <10 µm lateral misalignment of a test chip; (b) Example of >10 µm lateral misalignment of a

32 Advances in Micro/Nano Electromechanical Systems and Fabrication Technologies

MOSIS chip.

**Figure 33.** A CL-I2 packaged chip shown resting on a penny.

It should be stressed that the lead-count and interconnect density limitations for this technology stem only from the limitations of the microfabrication and photolithography equipment used to fabricate the CL-I2 package, and, in particular, to pattern the first parylene etch (Figure 28, step 7). All interconnects to the chip are fabricated simultaneous‐ ly during the metal deposition step, and depend on optimal step coverage of the pary‐ lene sidewall (aided in part by the slightly isotropic nature of the O2 plasma etch of parylene [47]). The CL-I2 process thus avoids the use of tedious and comparatively lowdensity ball-wedge [38] or wire bonding.

Our method of incorporating discrete modules into a MEMS process is far more cost-effective when compared with full-wafer IC processing and MEMS integration [51], because valuable space on the wafer is not wasted during the IC fabrication step. Furthermore, in comparison to other ASIC integration attempts [51-53], this packaging scheme is superior for biodevices because it takes advantage of parylene's low water-absorption [54] and highly conformal pinhole-free deposition, and because the package is both flexible and biocompatible. Among the feasible uses for this technology is the interconnection of chips, devices such as other CMOS-compatible MEMS, as well as discrete components such as chip capacitors, fabricated using different materials and processes, to make large conglomerate circuits for neural prostheses and for other applications. This technology is capable of increasing the previously projected number of I/O interconnects available in 2010 significantly, while using lead-free, biocompatible materials. Fabrication is not limited to the use of parylene as either the backside anchoring material or as the frontside electrode insulation material, although, because of its superior electrical, mechanical, and water permeability properties when compared with other polymers, we believe parylene will ultimately prove to be the best choice for monolithic highdensity neural prosthetics. It is interesting to note that another research group has, after our original publications [40, 56, 57], explored an integration technique in polyimide very similar to ours, with interconnect density motivations much akin to our own [58]. We have recently demonstrated a fully integrated parylene-based single-channel neural stimulator [59]. *In vitro* measurements demonstrated the ability to generate 7 V pulses of 500 µs pulse width from a wireless transmitter 4 mm away. Preliminary evidence from animal implantation studies has shown these are mechanically reliable under surgical conditions.
