**1. Introduction**

The use of implantable microelectronic devices for treatment of medical conditions, e.g. movement disorders, deafness and urinary incontinence has increased steadily over the years [1]. These devices use microelectronic components to sense biological activities in the im‐ planted patient. The microelectronic components must be protected from the surrounding tissue using insulating (hermetic) packaging material. This packaging prevents the aqueous saline environment of the body from corroding, short-circuiting and contaminating the internal electronics. Microelectronic packages must incorporate some electrically conducting elements that bridge through the protective packaging to allow the internal microelectronics to sense (or stimulate) the surrounding external environment. These conductive elements are called interconnects or feed-throughs.

First generation implantable electronic devices, such as the first cardiac pacemakers, had few, relatively large interconnects. To this day, many of these interconnects are constructed using labor intensive, manual assembly techniques. Electrode contacts are tack-welded to conductive leads, and then the entire assembly is laid inside a mold and encased in silicone insulation. The insulated wires are then released from the mold, flashing is removed and the final assembly is quality tested.

Next generation devices could have as many as 1000 interconnects condensed in a similar crosssectional surface area of the device packages. At this scale, hand laid and molded wires in silicone will not suffice. Simple but accurately repeatable processes must be developed to create functional feed-throughs. Existing feed-through designs and fabrication processes will not be appropriate and will warrant new strategies to prevent the penetration of mobile ions such as K+ , Na+ and Cl from surrounding body fluid [2, 3].

© 2013 Petrossians et al.; licensee InTech. This is an open access article distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. © 2013 Petrossians et al.; licensee InTech. This is a paper distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

The hermeticity of a package is its ability to prevent ion migration across (or through) its structure. Research and development in this area has accelerated significantly [4]. Simply put the hermeticity of different materials classes can be ordered as follows: polymers (least hermetic) < glass < polycrystalline metals/oxides (most hermetic). Interfaces between two different materials can serve as an avenue for contaminant ions to migrate as can grain boundaries between crystals of the same, polycrystalline material. Helium leak testing is currently the gold standard for evaluating hermeticity.

A number of research groups are trying to overcome existing issues with fabrication of hermetic packages for implantable microelectronics [5-8]. Since these implanted devices must remain hermetic for the lifetime of the patients, many important factors should be considered in their design, including the location of implantation, dimensional constraints, materials constraints (e.g. biocompatibility, conductivity, etc.), and selection of an appropriate fabrica‐ tion process technology

Our group has investigated using electrochemical plating to fill cylindrical channels in channeled substrates. Our theoretical approach is to take a two-dimensional substrate with penetrating channels orthogonal to the planar surfaces, and fill these channels with electro‐ chemically deposited metal. The resulting "assembly" of conducting elements embedded in the insulating substrate, can then be bump-bonded to a microchip, and the chip can then be encased in a gas-filled, brazed hard casket or embedded in a conformal coating.

This approach has been successful using larger channeled (*ɸ* = 200 µm) substrates, like the U.S. Naval Research Labs channel glass, with electroplated copper and chromium intercon‐ nects [9]. However, electrochemically depositing non-porous, continuous interconnects made from implantable electrical stimulator metals (e.g. platinum, iridium or their alloys) cannot be achieved due to solubility and deposition rate challenges. As a result, our group proposed and developed a strategy of electroplating several adjacent high-aspect ratio nano-channels, in nano-channeled substrates, with precious metal solutions. Once deposited, adjacent embed‐ ded nanowires can be electrically connected in parallel to create larger conducting elements.

Figure 1 depicts two schematics illustrating how this type of assembly would work. Here, metallic nanowires are deposited into a nano-channeled substrate, forming hermetic feedthroughs. Instead of using a single conducting element bump-bonded to each single contact on the chip, an array of co-deposited nanowires forms a single conductor unit through the substrate.

Fabricating these assemblies is achieved using a commonly used approach by nanowire researchers, called the "template synthesis" approach [10]. In this method, metallic ions in solution (plating solution) are electrochemically reduced at a working electrode surface that has been applied to the base of the channels of a nano-channeled substrate.

Using this template synthesis approach to deposit nanoscale elements provides distinct performance advantages. By confining the metal deposition to nanometer dimensions inside the channel, mass transport gradients that cause dendritic deposition and growth no longer occur. Further, by completely filling the channels, we are able to develop a dense interconnect from platinum and iridium that spans the substrate material.

The hermeticity of a package is its ability to prevent ion migration across (or through) its structure. Research and development in this area has accelerated significantly [4]. Simply put the hermeticity of different materials classes can be ordered as follows: polymers (least hermetic) < glass < polycrystalline metals/oxides (most hermetic). Interfaces between two different materials can serve as an avenue for contaminant ions to migrate as can grain boundaries between crystals of the same, polycrystalline material. Helium leak testing is

A number of research groups are trying to overcome existing issues with fabrication of hermetic packages for implantable microelectronics [5-8]. Since these implanted devices must remain hermetic for the lifetime of the patients, many important factors should be considered in their design, including the location of implantation, dimensional constraints, materials constraints (e.g. biocompatibility, conductivity, etc.), and selection of an appropriate fabrica‐

Our group has investigated using electrochemical plating to fill cylindrical channels in channeled substrates. Our theoretical approach is to take a two-dimensional substrate with penetrating channels orthogonal to the planar surfaces, and fill these channels with electro‐ chemically deposited metal. The resulting "assembly" of conducting elements embedded in the insulating substrate, can then be bump-bonded to a microchip, and the chip can then be

This approach has been successful using larger channeled (*ɸ* = 200 µm) substrates, like the U.S. Naval Research Labs channel glass, with electroplated copper and chromium intercon‐ nects [9]. However, electrochemically depositing non-porous, continuous interconnects made from implantable electrical stimulator metals (e.g. platinum, iridium or their alloys) cannot be achieved due to solubility and deposition rate challenges. As a result, our group proposed and developed a strategy of electroplating several adjacent high-aspect ratio nano-channels, in nano-channeled substrates, with precious metal solutions. Once deposited, adjacent embed‐ ded nanowires can be electrically connected in parallel to create larger conducting elements. Figure 1 depicts two schematics illustrating how this type of assembly would work. Here, metallic nanowires are deposited into a nano-channeled substrate, forming hermetic feedthroughs. Instead of using a single conducting element bump-bonded to each single contact on the chip, an array of co-deposited nanowires forms a single conductor unit through the

Fabricating these assemblies is achieved using a commonly used approach by nanowire researchers, called the "template synthesis" approach [10]. In this method, metallic ions in solution (plating solution) are electrochemically reduced at a working electrode surface that

Using this template synthesis approach to deposit nanoscale elements provides distinct performance advantages. By confining the metal deposition to nanometer dimensions inside the channel, mass transport gradients that cause dendritic deposition and growth no longer occur. Further, by completely filling the channels, we are able to develop a dense interconnect

has been applied to the base of the channels of a nano-channeled substrate.

from platinum and iridium that spans the substrate material.

encased in a gas-filled, brazed hard casket or embedded in a conformal coating.

currently the gold standard for evaluating hermeticity.

208 Advances in Micro/Nano Electromechanical Systems and Fabrication Technologies

tion process technology

substrate.

**Figure 1.** The top diagram shows an interconnect substrate with a case bonded over the top of the chip. Bumps on both the chip and the interconnect substrate facilitate electrical connections. This interconnect substrate could also be used with conformal coating technology (bottom). Drawing not to scale.

This approach also provides several key commercialization advantages. First, electroplating is a cost-effective processing technique. Second, unlike many nano-fabrication processes, template synthesis can be performed at ambient temperature and pressure. Lastly nonequilibrium phases can be produced by electrodeposition, a result that cannot be achieved using thermal processing techniques [11].

To date, no study has reported fabrication of ultra-high-density platinum-iridium nanowire arrays using a template synthesis approach. Only a handful of reports have been published on platinum nanowires synthesis. Approaches reported include focused ion beam [12], photoreduction in mesoporous silicides [13-17], colloidal synthesis [18, 19], self-assembly [20, 21], and nano-channel filling by electrochemistry [22-24],

This study focuses on the fabrication and evaluation of nonporous, platinum-iridium dense nanowires with improved electrical and mechanical properties to be used, embedded in their original template substrate, as a novel feed-through technology in hermetically packaged implantable microelectronics. Here we report on the fabrication process, the material proper‐ ties of the isolated nanowires, and lastly an assessment of the performance characteristics of the nanowire-in-template assembly as a hermetic feed-through platform.
