*3.1.1. Patterning graphene device using photolithography*

As mechanically exfoliated graphene sheets are in a mesoscopic scale, a lithographic technique is required to make metallic contacts on the sheet. Highly oriented pyrolytic graphite (HOPG) was used as the source material for graphene fabrication. Graphene flakes were mechanically transferred onto a highly doped silicon wafer. The graphene flakes for device fabrication were chosen by color and contrast method. p-type silicon wafers (100) with a boron doping con‐ centration of *N*A = 1015 cm−3 can be used in which SiO2 was thermally oxidized with the thickness of *t*ox = 300 nm. The substrate, p +Si (resistivity 1-30 Ω cm), serves as a back-gate for the FET. To keep the disorder level comparable, standard RCA cleaning process followed by acetone and isopropyl alcohol to clean the Si/SiO2 wafers.

Photo-lithography method can be used in this work to make electrode pattern. Details about the lithography process is discussed below. Figure 2 shows the mask aligner system.

**Figure 2.** Mask aligner system (MDA-400 M) for lithography pattern fabrication

The various stages of this lithography process or the procedures to be followed for lithographic pattern which are given below:

Stage -1: Wafer or substrate cleaning:


*3.1.1. Patterning graphene device using photolithography*

190 Advances in Micro/Nano Electromechanical Systems and Fabrication Technologies

and isopropyl alcohol to clean the Si/SiO2 wafers.

As mechanically exfoliated graphene sheets are in a mesoscopic scale, a lithographic technique is required to make metallic contacts on the sheet. Highly oriented pyrolytic graphite (HOPG) was used as the source material for graphene fabrication. Graphene flakes were mechanically transferred onto a highly doped silicon wafer. The graphene flakes for device fabrication were chosen by color and contrast method. p-type silicon wafers (100) with a boron doping con‐ centration of *N*A = 1015 cm−3 can be used in which SiO2 was thermally oxidized with the thickness of *t*ox = 300 nm. The substrate, p +Si (resistivity 1-30 Ω cm), serves as a back-gate for the FET. To keep the disorder level comparable, standard RCA cleaning process followed by acetone

**Figure 1.** Schematic of photolithographic process. A pattern has been made on the substrate. (Scale bar is not mentioned)

Photo-lithography method can be used in this work to make electrode pattern. Details about

the lithography process is discussed below. Figure 2 shows the mask aligner system.

**Figure 2.** Mask aligner system (MDA-400 M) for lithography pattern fabrication

**•** Use tissue paper and Air - drying to remove the water particles from the surface of wafer (both side).

Stage – 2: Spin coating of Photo-resist:


### Stage – 3: Baking the wafer

Put the spin coated wafer in the hot plate which is in 60º C for 150 sec and then remove wafer from the hot plate and do air cooling (only for back side of wafer )

Stage – 4: UV Exposure

Check and ensure the initial machine set up parameters is done carefully.


### Stage – 5: Removal of wafer

**•** Now put off Vacuum contact button


## Stage – 6: Developing process

The UV-exposed wafer to be put in developer solvent [standard developer solution AZ 300 MIF used]. Slow soaking has to be performed with respect to user need and process. In this process, the UV-unexposed parts (in case of positive PR) the photo-resist will be dissolved in the developer solution and show clear electrode pattern fabricated via mask. Then put the wafer in DI water bath for 1 min and do air- drying to clean the wafer thoroughly.

Stage – 7: Pattern Analysis

After developing,



**Table 1.** Optimized condition for Lithographic Process in MDA-400M Mask Aligner (using AZ 5214 positive photo-resist)

The schematic of the detailed lithographic process is presented in Figure.3 (a-e).

After completing the experiment: Mask cleaning to be done

Mask cleaning after exposure is important in the lithographic pattern process. Hence, the defects deposited in mask can be avoided during next experiment time. To clean the mask, the following things to be followed:


The Lithographic process was followed which was described in the above section 2.4. The positive photo-resist (AZ 5214) was spin-coated over the graphene flakes on the substrate. By using photolithography (Mask Aligner MDA- 400M; MIDAS), the graphene flakes were patterned through *Cr* mask for electrode formation. Then the gold (99.99 %) electrodes of 100 nm- thick were formed through thermal evaporation technique and structured by lift-off using acetone. A metal contact was made to the substrate as the back-gate contact. After lift-off

**•** Then bring down the stage by using Micrometer handle

192 Advances in Micro/Nano Electromechanical Systems and Fabrication Technologies

**•** Then press substrate vac. button off and remove wafer from the wafer stage.

wafer in DI water bath for 1 min and do air- drying to clean the wafer thoroughly.

**•** Put the developed wafer again in wafer stage and press substrate Vac. Button

**Sample Spin coating Prebake Expose UV with**

2200 rpm 40 sec (timer 2)

After completing the experiment: Mask cleaning to be done

**•** Use CCD camera -module's adjusting knobs in order to check the developed pattern.

**Table 1.** Optimized condition for Lithographic Process in MDA-400M Mask Aligner (using AZ 5214 positive photo-resist)

Mask cleaning after exposure is important in the lithographic pattern process. Hence, the defects deposited in mask can be avoided during next experiment time. To clean the mask, the

The Lithographic process was followed which was described in the above section 2.4. The positive photo-resist (AZ 5214) was spin-coated over the graphene flakes on the substrate. By using photolithography (Mask Aligner MDA- 400M; MIDAS), the graphene flakes were patterned through *Cr* mask for electrode formation. Then the gold (99.99 %) electrodes of 100 nm- thick were formed through thermal evaporation technique and structured by lift-off using acetone. A metal contact was made to the substrate as the back-gate contact. After lift-off

The schematic of the detailed lithographic process is presented in Figure.3 (a-e).

60°C 150 sec 55 sec 2 sec

**Mask Developing time Remarks**

Excellent 4 probe Pattern obtained

The UV-exposed wafer to be put in developer solvent [standard developer solution AZ 300 MIF used]. Slow soaking has to be performed with respect to user need and process. In this process, the UV-unexposed parts (in case of positive PR) the photo-resist will be dissolved in the developer solution and show clear electrode pattern fabricated via mask. Then put the

**•** Remove mask holder carefully

Stage – 6: Developing process

Stage – 7: Pattern Analysis

300 rpm 6sec (timer 1)

following things to be followed:

**•** rinse the mask with acetone

**•** Dry the Mask using the N2 gun

**•** rinse the Mask with IPA

After developing,

**1**

**Figure 3.** Photolithographic process of electrode patterning on graphene. (a) Graphene flake on Si/SiO2 substrate (b) Photoresist is spin-coated over the graphene flake and UV light illuminated through Cr mask. (c) the pattern after de‐ veloping process (d) gold (Au) evaporation through thermal evaporation technique (e) after lift-off process, the device with source and drain electrode structure with back-gate configuration. (Venugopal, 2011).

**Figure 4.** (a) An optical image of single layer graphene is shown. Single and few layer graphene flakes are clearly seen. (b) Schematic of graphene device with electrode pattern.

process, the device was annealed at 200° C in Ar/H2 atmosphere for 45 min to improve the adhesion with graphene flake as well as to avoid contaminants. After the lithography, metallic Au/Al electrodes are deposited by using thermal evaporation system. Then lift-off process is carried out (using acetone) to get the final pattern for device characterization. If necessary, graphene can be etched to a desired shape by the oxygen plasma ashing with negative or positive electron-beam resist stencils, which were not followed here.
