**A Successive Approximation ADC using PWM Technique for Bio-Medical Applications**

Tales Cleber Pimenta, Gustavo Della Colletta, Odilon Dutra, Paulo C. Crepaldi, Leonardo B. Zocal and Luis Henrique de C. Ferreira

Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/51715

## **1. Introduction**

Analog to digital (A/D) converters provide the interface between the real world (analog) and the digital processingdomain. The analog signals to be converted may originate from many transducers that convert physical phenomena like temperature, pressure or position to elec‐ trical signals. Since these electrical signals are analog voltage or current proportionals to the measured physical phenomena, its necessary to convert them to digital domain to conduct any computational. Nowadays, the development of the IC technology resulted in a growth of digital systems. A/D converters are present in the automotive industry, embedded sys‐ tems and medicine for example. Thus, A/D converters have become important and the large variety of applications implies different types of A/D conversions.

For the A/D type considerations, the analog input should be characterized as one of the fol‐ lowing three basic signal types [3].


For sampling the first type of signals, typical A/D conversion architectures are slope, volt‐ age to frequency, counter ramp and sigma-delta. The second signal type is better sampled using the successive approximation, multistep and full parallel A/D conversion architec‐ tures. The last signal type uses successive approximation, multistep, pipeline and full par‐ allel architectures.

© 2013 Pimenta et al.; licensee InTech. This is an open access article distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. © 2013 Pimenta et al.; licensee InTech. This is a paper distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

After choosing the A/D converter architecture, it is important to keep in mind that any of them have nonlinearities that degrade the converter performance. These nonlinearities are accuracy parameters that can be defined in terms of Differential Nonlinearity (DNL) and In‐ tegral Nonlinearity (INL). Both have negative influence in the converter Effective Number of Bits (ENOB) [2].


Therefore it is important to design implementations capable of improving the ADCs per‐ formance by improving DNL and INL.

Physiological signals have amplitudes ranging from tens of *μV* to tens of *mV* and the fre‐ quencies spanning from DC to a few *KHz*. By considering those features and the application requirements, in order to make a reliable conversion, A/D converter may not have missing codes and must be monotonic. This can be accomplished assuring that the DNL error is less then *0.5* of last significant bits (LSBs).

## **2. Biomedical Application**

Advances in low power circuit designs and CMOS technologies have supported the research and development of biomedical devices that can be implanted in the patient. These devices have a sensor interface specially designed to acquire physiological signals, usually com‐ posed of an operational amplifier with programmable gain and reconfigurable band-width features, low pass filter and an A/D converter [8, 10]. The signals are acquired and digital‐ ized in the sensor, thus protecting data from external noise interference.

Specific research on A/D converters for biomedical application is focused on design low power circuits regardless of the monotonic feature, once DNL error is above *0.5 LSBs*, affect‐ ing the converter accuracy [5, 6]. The proposed Successive Approximation architecture of‐ fers both low power consumption and high accuracy features for use in biomedical applications.

## **3. Conventional SAR architectures**

Figure 1 illustrates the block diagram of the conventional SAR architecture. It is composed of a Successive Approximation Register that controls the operation and stores the output converted digital data, of a digital-to-analog converter stage (DAC), a comparator usually built with a operational amplifier and of a sample and hold circuit. The output can be taken serially from the comparator output or parallel from the SAR outputs.

The operation consists on evaluating and determining the bits of the converted digital word, one by one, initiating from the most significant bit. Thus the SAR architecture uses *n* clock cycles to convert a digital word of *n* bits. The successive approximation architecture pro‐ vides intermediate sample rates at moderate power consumption that makes it suitable for low power applications.

After choosing the A/D converter architecture, it is important to keep in mind that any of them have nonlinearities that degrade the converter performance. These nonlinearities are accuracy parameters that can be defined in terms of Differential Nonlinearity (DNL) and In‐ tegral Nonlinearity (INL). Both have negative influence in the converter Effective Number of

**•** Differential Nonlinearity (DNL) is a measure of how uniform the transfer function step sizes are. Each one is compared to the ideal step size and the difference in magnitude is

Therefore it is important to design implementations capable of improving the ADCs per‐

Physiological signals have amplitudes ranging from tens of *μV* to tens of *mV* and the fre‐ quencies spanning from DC to a few *KHz*. By considering those features and the application requirements, in order to make a reliable conversion, A/D converter may not have missing codes and must be monotonic. This can be accomplished assuring that the DNL error is less

Advances in low power circuit designs and CMOS technologies have supported the research and development of biomedical devices that can be implanted in the patient. These devices have a sensor interface specially designed to acquire physiological signals, usually com‐ posed of an operational amplifier with programmable gain and reconfigurable band-width features, low pass filter and an A/D converter [8, 10]. The signals are acquired and digital‐

Specific research on A/D converters for biomedical application is focused on design low power circuits regardless of the monotonic feature, once DNL error is above *0.5 LSBs*, affect‐ ing the converter accuracy [5, 6]. The proposed Successive Approximation architecture of‐ fers both low power consumption and high accuracy features for use in biomedical applications.

Figure 1 illustrates the block diagram of the conventional SAR architecture. It is composed of a Successive Approximation Register that controls the operation and stores the output converted digital data, of a digital-to-analog converter stage (DAC), a comparator usually built with a operational amplifier and of a sample and hold circuit. The output can be taken

The operation consists on evaluating and determining the bits of the converted digital word, one by one, initiating from the most significant bit. Thus the SAR architecture uses *n* clock

ized in the sensor, thus protecting data from external noise interference.

serially from the comparator output or parallel from the SAR outputs.

**•** Integral Nonlinearity (INL) is the code midpoints deviation from their ideal locations.

Bits (ENOB) [2].

4 Analog Circuits

the DNL.

formance by improving DNL and INL.

then *0.5* of last significant bits (LSBs).

**3. Conventional SAR architectures**

**2. Biomedical Application**

The internal DAC stage, illustrated in Figure 1 is usually designed using capacitor networks that are susceptible to mismatches caused by the fabrication process variation, since the de‐ sign is based on absolute capacitance values. These mismatches affect the converter accura‐ cy, thus increasing the DNL and INL errors.

#### **4. Proposed Architecture**

The presented architecture aims to eliminate the mismatches introduced during fabrication process by replacing the conventional internal DAC based on capacitor networks by a digi‐ tal PWM modulator circuit and a first order low pass filter.

Figure 1 shows the block diagram of the proposed architecture (dotted line) as a modifica‐ tion on a conventional one (full line).

A PWM signal can be stated in terms of an even function, as illustrated in Figure 2 [1]. By using Fourier series, it can be represented in terms of equations (1) to (4).

**Figure 2.** PWM signal stated as an even function.

$$f\left(t\right) = A\_0 + \sum\_{n=1}^{\alpha} \left[A\_n \cos\left(\frac{2n\pi t}{T}\right) + B\_n \sin\left(\frac{2n\pi t}{T}\right)\right] \tag{1}$$

$$A\_0 = \frac{1}{2T} \mathbf{f}\_{-T}^T f(t)dt \tag{2}$$

$$A\_n = \frac{1}{2T} \int\_{-T}^{T} f\left(t\right) \cos\left(\frac{2n\pi t}{T}\right) dt\tag{3}$$

$$B\_n = \frac{1}{2T} \int\_{-T}^{T} f\left(t\right) \sin\left(\frac{2n\pi t}{T}\right) dt\tag{4}$$

where *A0* represents the fundamental frequency, *An* states the even harmonics and *Bn* states the odd harmonics.

By performing the integral on a PWM signal with amplitude *(f(t)=k)*, the results are given by equations (5) to (7).

$$A\_0 = kp\tag{5}$$

A Successive Approximation ADC using PWM Technique for Bio-Medical Applications http://dx.doi.org/10.5772/51715 7

$$A\_n = k \frac{1}{n\pi} \mathbb{E} \sin(n\pi p) - \sin(2n\pi \mathbf{(1} - \frac{p}{2})) \mathbf{I} \tag{6}$$

$$B\_n = 0\tag{7}$$

where *p* denotes the duty cycle.

**4. Proposed Architecture**

6 Analog Circuits

tion on a conventional one (full line).

**Figure 2.** PWM signal stated as an even function.

the odd harmonics.

equations (5) to (7).

*f* (*t*)= *A*<sup>0</sup> + ∑

*n*=1 ∞

*An* <sup>=</sup> <sup>1</sup> <sup>2</sup>*<sup>T</sup> ∫* −*T <sup>T</sup> f* (*t*)*cos*(

*Bn* <sup>=</sup> <sup>1</sup> <sup>2</sup>*<sup>T</sup> ∫* −*T <sup>T</sup> f* (*t*)*sin*(

*Ancos*(

*<sup>A</sup>*<sup>0</sup> <sup>=</sup> <sup>1</sup> <sup>2</sup>*<sup>T</sup> ∫* −*T*

2*nπt*

*<sup>T</sup>* ) + *Bnsin*(

2*nπt*

2*nπt*

where *A0* represents the fundamental frequency, *An* states the even harmonics and *Bn* states

By performing the integral on a PWM signal with amplitude *(f(t)=k)*, the results are given by

2*nπt*

*<sup>T</sup>* ) (1)

*<sup>T</sup> f* (*t*)*dt* (2)

*A*<sup>0</sup> =*kp* (5)

*<sup>T</sup>* )*dt* (3)

*<sup>T</sup>* )*dt* (4)

tal PWM modulator circuit and a first order low pass filter.

using Fourier series, it can be represented in terms of equations (1) to (4).

The presented architecture aims to eliminate the mismatches introduced during fabrication process by replacing the conventional internal DAC based on capacitor networks by a digi‐

Figure 1 shows the block diagram of the proposed architecture (dotted line) as a modifica‐

A PWM signal can be stated in terms of an even function, as illustrated in Figure 2 [1]. By

That result shows that the PWM signal consists of a DC level and a square wave of zero average, as illustrated in Figure 3. Only the DC level is necessary in order to implement an internal DAC stage, since any DC level varying from zero to *k* can be obtained by selecting the proper duty cycle.

**Figure 3.** PWM signal split in a D.C level plus a square wave.

A way of recovering the DC level is to low pass filter the PWM signal. Since there is no ideal filter, the recovered DC level will have a certain ripple, as illustrated in Figure 4.

**Figure 4.** Low pass filtering the PWM signal.

#### **4.1 Modeling**

This section provides the modeling of a *4 bit* A/D Converter. Functional models for the SAR, PWM generator, Low pass filter and comparator blocks are discussed. Also the equating necessary to determine the filter features and clock frequencies is developed. SAR and PWM generator digital circuits are modeled using VHDL hardware description language. Compa‐ rator and the first order low pass filter are modeled using compartmental blocks.

A macro level simulation is performed using MatLab in order to validate the architecture. Electrical and post layout simulations are performed using Spectre simulator. The A/D con‐ verter Layout is developed in *0.5 μm* standard CMOS process using Cadence Virtuoso and NCSU Design Kit (Free design kit available from North Caroline State University).

#### *4.1.1 Successive Approximation Digital Logic*

The Successive Approximation logic evaluates every digital word output bit according to the clock (CLK) signal. Thus, initiating by the most significant bit, one by one, the bits are evaluated and determined, until the last significant bit. Figure 4 illustrates the SAR digital circuit. The control logic is based on a simple shift register. There is also a flip-flop array that stores the input selection (SEL) that is attached to the comparator output.

On a reset (RST) signal, the shift register is loaded with 10000 and the flip-flop array is load‐ ed with 0000. The combinational logic based on OR gates assures the value 1000 at the out‐ put (*Q3-Q0*). When the first clock pulse arrives, the shift register value is changed to 01000 while the flip-flop array remains with the same value, except for the most significant bit, since it has been already determined. Thus, the SAR output will show something like *X000*, where *X* represents the previously determined value.

One special feature is to use an extra flip-flop in the shift register to indicate the end of con‐ version (END), enabling the converted digital word to be read in the rising edge of the fifth clock pulse.

**Figure 5.** Successive Approximation Register.

#### *4.1.2 Low Pass Filter*

Circuits powered by *2.5V* using a *0.5 μm* standard CMOS process, as in this case, can operate at *2MHz* maximum frequency, limiting the operation to about *200 Hz* of sampling rate, re‐ garding the proposed architecture design. These feature lead to a high value of capacitance in the RC first order low pass filter, which is impracticable to be integrated. An alternative used to validate the proposed architecture is the implementation of an external first order RC low pass filter, as show in Figure 6.

#### *4.1.3 Digital PWM Modulator*

generator digital circuits are modeled using VHDL hardware description language. Compa‐

A macro level simulation is performed using MatLab in order to validate the architecture. Electrical and post layout simulations are performed using Spectre simulator. The A/D con‐ verter Layout is developed in *0.5 μm* standard CMOS process using Cadence Virtuoso and

The Successive Approximation logic evaluates every digital word output bit according to the clock (CLK) signal. Thus, initiating by the most significant bit, one by one, the bits are evaluated and determined, until the last significant bit. Figure 4 illustrates the SAR digital circuit. The control logic is based on a simple shift register. There is also a flip-flop array that

On a reset (RST) signal, the shift register is loaded with 10000 and the flip-flop array is load‐ ed with 0000. The combinational logic based on OR gates assures the value 1000 at the out‐ put (*Q3-Q0*). When the first clock pulse arrives, the shift register value is changed to 01000 while the flip-flop array remains with the same value, except for the most significant bit, since it has been already determined. Thus, the SAR output will show something like *X000*,

One special feature is to use an extra flip-flop in the shift register to indicate the end of con‐ version (END), enabling the converted digital word to be read in the rising edge of the fifth

Circuits powered by *2.5V* using a *0.5 μm* standard CMOS process, as in this case, can operate at *2MHz* maximum frequency, limiting the operation to about *200 Hz* of sampling rate, re‐

rator and the first order low pass filter are modeled using compartmental blocks.

NCSU Design Kit (Free design kit available from North Caroline State University).

stores the input selection (SEL) that is attached to the comparator output.

*4.1.1 Successive Approximation Digital Logic*

where *X* represents the previously determined value.

**Figure 5.** Successive Approximation Register.

*4.1.2 Low Pass Filter*

clock pulse.

8 Analog Circuits

The digital PWM modulator circuit is capable of varying the duty cycle of the output (PWM) according to the digital input word (*D3™ D0*). The circuit is illustrated in Figure 7 and con‐ sists of registers, a synchronous *4-bit* counter, a combinational reset and a combinational comparison logic.

**Figure 6.** External RC first order low pass filter.

On a reset (RST) pulse, the counter resets to *0000* and the registers store the input word. The counter is incremented at every clock (CLK) cycle and the comparison logic assures that the output remains set while the counter does not reach the value stored into the registers. When it occurs, the output resets and the count continues until the counter reaches the end of counting. The reset logic makes the output flip-flop to set every time the counter resets, thus assuring that the output is set at the beginning of the counting. At this time, the regis‐ ters are updated with the value present in the input (*D3- D0*) from the SAR output. The reset logic also has a flip-flop responsible for synchronizing the output of the AND gate to the clock signal, since the AND inputs arrive at different timings.

#### *4.1.4 Inverter Based Comparator*

The inverter based comparator circuit is used in order to decrease power consumption, since there is no quiescent power consumption. Figure 8 illustrates the comparator stage that uses a low power consumption architecture [7].

The circuit uses lagged clock signals to avoid overlapping, therefore assuring that the switches *S1, S2* and *S3* do not close at the same time. At time *ϕ 1*, the switch *S2* is open and the switches *S1* and *S3* are closed, thus charging the capacitor *C* with *Vin-Vth*, where *Vth* is the in‐ verter threshold voltage. Consequently any voltage variation during time *ϕ 2* will be sensed by the inverter.

At time *ϕ 2*, the switches *S1* and *S3* are open and *S2* is closed, thus applying to the capacitor *C* the voltage produced by the PWM generator. This produces a voltage variation in the inver‐ ter input and the comparator makes the decision.

The switches *S1*, *S2* and *S3* were replaced by solid state switches based on a nMOS transistor. After passing through a booster circuit, the clock signal is applied to the transistors gates.

#### *4.1.5 Equating*

The previous subsections illustrated the functional models for each stage of the proposed *4 bit* A/D converter. Nevertheless is still necessary to determine the low pass filter features and the clock frequency for the digital stages, SAR, comparator and PWM generator.

The comparator must evaluate every time the SAR tests a new bit, so they have to be synchronized by the same clock signal. Assuming that all *N* bits must have to be determined before a new sampling begins, equation (8) states the clock frequency for the comparator and the SAR stage.

**Figure 7.** Digital Pulse Width Modulation generator.

$$f\_{SAR} \ge f\_s \times N \tag{8}$$

where *N* represents the shift register number of bits, including the EOC bit and *fs* represents the sampling rate.

Now, the low pass filter time constant ought to be determined. Equation (9) shows the cut off frequency for the first order filter.

$$f\_c = \frac{1}{2\pi\pi} \tag{9}$$

where *fc* represents the cut of frequency and *τ* states the filter time constant.

*τ* ≤

Assuming *5 τ* to accommodate a signal, equation (9) can be rewritten as equation (10)

$$f\_c = \frac{1}{2\pi 5\pi} \tag{10}$$

(11)

From Figure 1, it can be observed that the filter must respond faster or at least at the same rate the SAR tests each bit. Thus, equation (11) states the maximum time constant for the low pass filter.

> 1 2*π*5 *f SAR*

**Figure 8.** Inverter comparator circuit.

verter threshold voltage. Consequently any voltage variation during time *ϕ 2* will be sensed

At time *ϕ 2*, the switches *S1* and *S3* are open and *S2* is closed, thus applying to the capacitor *C* the voltage produced by the PWM generator. This produces a voltage variation in the inver‐

The switches *S1*, *S2* and *S3* were replaced by solid state switches based on a nMOS transistor. After passing through a booster circuit, the clock signal is applied to the transistors gates.

The previous subsections illustrated the functional models for each stage of the proposed *4 bit* A/D converter. Nevertheless is still necessary to determine the low pass filter features

The comparator must evaluate every time the SAR tests a new bit, so they have to be synchronized by the same clock signal. Assuming that all *N* bits must have to be determined before a new sampling begins, equation (8) states the clock frequency for the comparator

*f SAR* ≥ *f <sup>s</sup>* × *N* (8)

and the clock frequency for the digital stages, SAR, comparator and PWM generator.

by the inverter.

10 Analog Circuits

*4.1.5 Equating*

and the SAR stage.

**Figure 7.** Digital Pulse Width Modulation generator.

ter input and the comparator makes the decision.

The frequency of the PWM signal must have to be characterized in order to be properly fil‐ tered. Since there is no ideal filter, the filtered signal will present a ripple. The PWM signal can be stated in terms of DC level and a sum of even harmonics, as in 12.

$$F\_{PWM} \left( t \right) = A\_0 + \sum\_{n=1}^{\infty} A\_n \cos \left( \frac{2nnt}{T} \right) \tag{12}$$

Taking into account only the even harmonics, as stated in 13, the energy carried by them can be determined.

$$\mathbf{g}\_n(t) = A\_n \cos(\frac{2n\pi t}{T}), \ n = \{0, 1, 2, \dots\} \tag{13}$$

It is known that the energy is proportional to (*gn* 2(*t*)). The maximum energy occurs at ∂ <sup>∂</sup>*<sup>p</sup> gn* 2 (*t*)=0. Thus:

$$\begin{aligned} \frac{\partial}{\partial p} g\_n^2(t) &= \frac{\partial}{\partial p} (A\_n^2 \cos^2(\frac{2n\pi t}{T})) \\ &= \cos^2(\frac{2n\pi t}{T}) \frac{\partial}{\partial p} (A\_n^2) \\ &= \cos^2(\frac{2n\pi t}{T}) 2A\_n \frac{\partial}{\partial p} (A\_n) = 0 \end{aligned} \tag{14}$$

Equation 14 shows that the cosine term is independent of the duty cycle *p* and that the maxi‐ mum energy occurs when <sup>∂</sup> <sup>∂</sup>*<sup>p</sup> An* =0, as shown in 15.

$$\begin{aligned} \frac{\partial}{\partial p} A\_n &= \frac{\partial}{\partial p} (\frac{1}{n\pi} \mathbb{E} \sin(n\pi p) - \sin(2n\pi (1 - \frac{p}{2}) \mathbb{I})) \\ &= \cos(n\pi p) + \cos(2n\pi (1 - \frac{p}{2})) \\ &= \cos(n\pi p) + \cos(2n\pi - n\pi p) \\ &= \cos(n\pi p) + \cos(2n\pi) \cdot \cos(n\pi p) + \sin(2n\pi) \cdot \sin(n\pi p) = 0 \end{aligned} \tag{15}$$

It can be observed that *cos(2 n π)* is unity for any value of *n*, the term *sin(2 n π)* is zero for any value of *n*. Thus, equation 15 can be rewritten in terms as 16.

$$\frac{\partial}{\partial p}A\_n = 2\cos\{n\pi p\} = 0\tag{16}$$

Equation 16 shows that the maximum energy in each harmonic is obtained at different duty cycles.

Since there is no ideal filter, after the low pass filtering, the harmonics will not be completely eliminated, but attenuated. It is necessary to evaluate the minimum attenuation required by system, once it is directly linked to ripple amplitude present in the filtered DC level.

Since the first harmonic caries the most energy, it is reasonable to take just it into account to characterize the low pass filter.

Thus, considering the first harmonic (*n=1*) and the maximum energy scenario (*<sup>p</sup>* <sup>=</sup> <sup>1</sup> <sup>2</sup> ), isolat‐ ing the first harmonic term *Ancos*( 2*nπt <sup>T</sup>* ), the maximum ripple expression can be expressed by 17. Figure 9 illustrates the PWM signal, where *h1* represents the ripple amplitude variation given by the first harmonic.

$$\mathcal{H}\_1 = \frac{2k}{\pi} \cos\left(\frac{2v\pi t}{T}\right) \tag{17}$$

It is important to notice that the cosine term introduces a variation interval of <sup>−</sup> <sup>2</sup>*<sup>k</sup> π* ≤ 2*k <sup>π</sup>* in the ripple amplitude. Equation 18 shows the maximum peak to peak variation.

$$\left. \begin{array}{c} \frac{1}{n} \\ \end{array} \right|\_{\mathcal{V}} = \frac{2k}{\pi} - \left( -\frac{2k}{\pi} \right) = \frac{4k}{\pi} \end{array} \tag{18}$$

Figure 9 illustrates two sequential quantization levels defined by the filtered PWM signal. If the ripple present in two sequential quantization levels overlaps, the converter will lead to a wrong conversion.

**Figure 9.** Maximum ripple amplitude.

It is known that the energy is proportional to (*gn*

∂ <sup>∂</sup> *<sup>p</sup> gn* 2 (*t*)= <sup>∂</sup> <sup>∂</sup> *<sup>p</sup>* (*An* 2 *cos* <sup>2</sup> ( 2*nπt <sup>T</sup>* ))

> = *cos* <sup>2</sup> ( 2*nπt <sup>T</sup>* ) <sup>∂</sup> <sup>∂</sup> *<sup>p</sup>* (*An* 2 )

= *cos* <sup>2</sup> ( 2*nπt <sup>T</sup>* )2*An*

<sup>∂</sup>*<sup>p</sup> An* =0, as shown in 15.

*<sup>n</sup><sup>π</sup> sin*(*nπp*)−*sin*(2*nπ*(1<sup>−</sup> *<sup>p</sup>*

<sup>=</sup> *cos*(*nπp*) <sup>+</sup> *cos*(2*nπ*(1<sup>−</sup> *<sup>p</sup>*

= *cos*(*nπp*) + *cos*(2*nπ* −*nπp*)

any value of *n*. Thus, equation 15 can be rewritten in terms as 16.

∂

∂ <sup>∂</sup> *<sup>p</sup>* (*An*)=0

<sup>2</sup> ) )

<sup>∂</sup> *<sup>p</sup> An* =2*cos*(*nπp*)=0 (16)

*<sup>T</sup>* ), the maximum ripple expression can be expressed by

*<sup>T</sup>* ) (17)

Equation 14 shows that the cosine term is independent of the duty cycle *p* and that the maxi‐

<sup>2</sup> ))

= *cos*(*nπp*) + *cos*(2*nπ*) ⋅ *cos*(*nπp*) + *sin*(2*nπ*) ⋅ *sin*(*nπp*)=0

It can be observed that *cos(2 n π)* is unity for any value of *n*, the term *sin(2 n π)* is zero for

Equation 16 shows that the maximum energy in each harmonic is obtained at different

Since there is no ideal filter, after the low pass filtering, the harmonics will not be completely eliminated, but attenuated. It is necessary to evaluate the minimum attenuation required by

Since the first harmonic caries the most energy, it is reasonable to take just it into account to

17. Figure 9 illustrates the PWM signal, where *h1* represents the ripple amplitude variation

2*nπt*

system, once it is directly linked to ripple amplitude present in the filtered DC level.

Thus, considering the first harmonic (*n=1*) and the maximum energy scenario (*<sup>p</sup>* <sup>=</sup> <sup>1</sup>

2*nπt*

*<sup>h</sup>*<sup>1</sup> <sup>=</sup> <sup>2</sup>*<sup>k</sup> <sup>π</sup> cos*(

∂ <sup>∂</sup>*<sup>p</sup> gn* 2

12 Analog Circuits

(*t*)=0. Thus:

mum energy occurs when <sup>∂</sup>

∂ <sup>∂</sup> *<sup>p</sup> An* <sup>=</sup> <sup>∂</sup>

duty cycles.

characterize the low pass filter.

ing the first harmonic term *Ancos*(

given by the first harmonic.

<sup>∂</sup> *<sup>p</sup>* ( <sup>1</sup>

2(*t*)). The maximum energy occurs at

(14)

(15)

<sup>2</sup> ), isolat‐

Thus, equation (19) states the minimum attenuation necessary to keep ripple under an ac‐ ceptable value.

$$\begin{aligned} & -h\_{1\_{rr}} A \le \frac{k}{2^{N-1}}\\ & -\frac{4k}{\pi} A \le \frac{k}{2^{N-1}}\\ & & A \ge \frac{\pi}{2^{N+1}}\\ & & A\_{dB} \ge 20 \log\left(\frac{\pi}{2^{N+1}}\right) \end{aligned} \tag{19}$$

Since equation (19) expresses the attenuation in *dB*, the easier way to determine the PWM frequency is to plot the Bode diagram of the previously designed low pass filter and look directly into the frequency that provides the minimum necessary attenuation, as shown in Figure 10. Higher attenuation will decrease the ripple amplitude assuring the correct behav‐ ior of the A/D converter and a maximum attenuation is limited by the maximum frequency achieved by the PWM signal.

Finally, the PWM generator design requires a clock frequency 2*<sup>N</sup>* <sup>−</sup><sup>1</sup> times greater then out‐ put PWM signal, as stated by equation (20).

$$f\_{\text{pwur}} = \mathbf{2}^{N-1} f\_{\text{pwur}} \tag{20}$$

where *<sup>f</sup> pwm clk* states the clock frequency and *<sup>f</sup> pwm* states the PWM signal frequency.

**Figure 10.** Determining the PWM signal frequency.

## **5. Simulations**

The *4 ™ bit* SAR ADC using PWM technique was designed for the ON *0.5 μ m* CMOS proc‐ ess using Cadence Virtuoso. simulations were conducted on Spectre simulator.

Figure 11 shows the circuit layout that occupies *0.749 mm2* . The main simulation results are given in table I.

It can be observed that the proposed architecture improved the A/D Converter accuracy, since the DNL and INL values are less then 0.1 LSB and also that it consumes low power.

A Successive Approximation ADC using PWM Technique for Bio-Medical Applications http://dx.doi.org/10.5772/51715 15

**Figure 11.** Circuit layout.

Since equation (19) expresses the attenuation in *dB*, the easier way to determine the PWM frequency is to plot the Bode diagram of the previously designed low pass filter and look directly into the frequency that provides the minimum necessary attenuation, as shown in Figure 10. Higher attenuation will decrease the ripple amplitude assuring the correct behav‐ ior of the A/D converter and a maximum attenuation is limited by the maximum frequency

times greater then out‐

. The main simulation results are

*<sup>f</sup> pwm clk* =2*<sup>N</sup>* <sup>−</sup><sup>1</sup> *<sup>f</sup> pwm* (20)

Finally, the PWM generator design requires a clock frequency 2*<sup>N</sup>* <sup>−</sup><sup>1</sup>

where *<sup>f</sup> pwm clk* states the clock frequency and *<sup>f</sup> pwm* states the PWM signal frequency.

The *4 ™ bit* SAR ADC using PWM technique was designed for the ON *0.5 μ m* CMOS proc‐

It can be observed that the proposed architecture improved the A/D Converter accuracy, since the DNL and INL values are less then 0.1 LSB and also that it consumes low power.

ess using Cadence Virtuoso. simulations were conducted on Spectre simulator.

Figure 11 shows the circuit layout that occupies *0.749 mm2*

achieved by the PWM signal.

14 Analog Circuits

put PWM signal, as stated by equation (20).

**Figure 10.** Determining the PWM signal frequency.

**5. Simulations**

given in table I.


**Table 1.** SAR ADC simulated performance.

Figure 12 shows the post layout simulation of DNL and INL for a slow ramp input. The val‐ ues are good, lower than *0.086 LSB* and *0.1 LSB*, respectively, showing that the characteristic of proposed architecture does not differ too much form the ideal one.

**Figure 12.** DNL and INL post simulation results.

Figure 13 illustrates the output frequency spectrum for a *32* point DFT. When ADC is tested with sinusoidal input at 166.67 Hz for a 15.63 Hz signal, it gives a good SNDR value of 24.36 dB, which results in 3.7549 effective number of bits (ENOB), thus proving the high accuracy achieved by the proposed architecture.

**Figure 13.** ADC simulated output frequency spectrum.

#### **6. Future Research**

The 4-bit layout was fabricated trough MOSIS education program. The prototypes will be tested and the results will be compared to the simulations.

After chip characterization, a proper integrated low pass filter will be implemented in a new prototyping. A new ADC with a larger number of bits will be developed in order to better investigate the non-linearities, ENOB and FoM results.

## **7. Conclusion**

Figure 12 shows the post layout simulation of DNL and INL for a slow ramp input. The val‐ ues are good, lower than *0.086 LSB* and *0.1 LSB*, respectively, showing that the characteristic

Figure 13 illustrates the output frequency spectrum for a *32* point DFT. When ADC is tested with sinusoidal input at 166.67 Hz for a 15.63 Hz signal, it gives a good SNDR value of 24.36 dB, which results in 3.7549 effective number of bits (ENOB), thus proving the high accuracy

The 4-bit layout was fabricated trough MOSIS education program. The prototypes will be

of proposed architecture does not differ too much form the ideal one.

**Figure 12.** DNL and INL post simulation results.

16 Analog Circuits

achieved by the proposed architecture.

**Figure 13.** ADC simulated output frequency spectrum.

tested and the results will be compared to the simulations.

**6. Future Research**

In order to validate the proposed architecture, a *4 ™ bit* SAR A/D converter was designed in *0.5μ m* CMOS standard process. The layout was developed using CADENCE Virtuoso and occupies *0.749 mm2* . Post-layout simulations conducted in Spectre simulator using the BSIM3v3 model show that the modifications introduced in the internal DAC stage contribut‐ ed to minimize DNL (*0.086 LSB*) and INL (*0.099*) errors, as expected.

They also contributed to improve A/D converter accuracy, since the SNDR was improved to *24.36 dB* of *25.84 dB* maximum theoretical value, leading to *3.75* effective bits.

The feature of being almost fully digital contributes to reduce the circuit complexity, the sili‐ con area and power consumption.

The features of high accuracy and low power consumption make the proposed architecture suitable for biomedical applications.

This architecture can be extended to build higher resolution converters by only adding more hardware to the digital stages or building pipeline structures.

## **Author details**

Tales Cleber Pimenta\* , Gustavo Della Colletta, Odilon Dutra, Paulo C. Crepaldi, Leonardo B. Zocal and Luis Henrique de C. Ferreira

\*Address all correspondence to: tales@unifei.edu.br

Universidade Federal de Itajuba-UNIFEI, Brazil

## **References**


**Provisional chapter**

## **Radio Frequency IC Design with Nanoscale DG-MOSFETs DG-MOSFETs**

**Radio Frequency IC Design with Nanoscale**

Soumyasanta Laha and Savas Kaya Additional information is available at the end of the chapter

Soumyasanta Laha and Savas Kaya

Additional information is available at the end of the chapter 10.5772/55006

http://dx.doi.org/10.5772/55006

## **1. Introduction**

[3] Hoeschele, D. F. J. (1994). Analog-to-Digital and Digital-to-Analog Conversion Tech‐

[4] Lin, Y. Z., Liu, C.C., Huang, G. Y., Shyu, Y. T., & Chang, S. J. (2010). A 9-bit 150-ms/s 1.53- mw subranged sar adc in 90-nm cmos. *VLSI Circuits (VLSIC), 2010 IEEE Sympo‐*

[5] Lu, T. C., Van, L. D., Lin, C. S., & Huang, C.-M. (2011). A 0.5v 1ks/s 2.5nw 8.52-enob 6.8fj/conversion-step sar adc for biomedical applications. *Custom Integrated Circuits*

[6] Mesgarani, A., & Ay, S. (2011). A low voltage, energy efficient supply boosted sar adc for biomedical applications. *Biomedical Circuits and Systems Conference (BioCAS),*

[7] Mikkola, E., Vermeire, B., Barnaby, H., Parks, H., & Borhani, K. (2004). Set tolerant

[8] Ng, K., & Chan, P. (2005). A cmos analog front-end ic for portable eeg/ecg monitor‐ ing applications. *Circuits and Systems I: Regular Papers, IEEE Transactions on*, 52(11),

[9] Talekar, S., Ramasamy, S., Lakshminarayanan, G., & Venkataramani, B. (2009). A low power 700msps 4bit time interleaved sar adc in 0.18um cmos. *TENCON 2009-2009*

[10] Zou, X., Xu, X., Yao, L., & Lian, Y. (2009). A 1-v 450-nw fully integrated programma‐ ble biomedical sensor interface chip. *Solid-State Circuits, IEEE Journal of*, 44(4),

cmos comparator. *Nuclear Science, IEEE Transactions on*, 51(6), 3609-3614.

niques. John Wiley e Sons, 2nd edition.

*Conference (CICC), 2011 IEEE*, 1-4.

*IEEE Region 10 Conference*, 1-5.

*sium on*, 243-244.

18 Analog Circuits

*2011 IEEE*, 401-404.

2335-2347.

1067-1077.

Today's nanochips contain billions of transistors on a single die that integrates whole electronic systems as opposed to sub-system parts. Together with ever higher frequency performances resulting from transistor scaling and material improvements, it thus become possible to include on the same silicon chip analog functionalities and communication circuitry that was once reserved to only an elite class of compound III-V semiconductors. It appears that the last stretch of Moore's scaling down to 5 nm range, only limited by fabrication at atomic dimensions and fundamental physics of conduction and insulation, these systems will only become more capable and faster, due to novel types of transistor geometries and functionalities as well as better integration of passive elements, antennas and novel isolation approaches. Accordingly, this chapter is an example to how RF-CMOS integration may benefit from use of a novel multi-gate transistors called FinFETs or double-gate MOSFETs (DG-MOSFETs). More specifically, we hope to illustrate how radio frequency wireless communication circuits can be improved by the use of these novel transistor architectures.

## **1.1. CMOS downscaling to DG-MOSFETs**

As device scaling aggressively continues down to sub-32nm scale, MOSFETs built on Silicon on Insulator (SOI) substrates with ultra-thin channels and precisely engineered source/drain contacts are required to replace conventional bulk devices [1]. Such SOI MOSFETs are built on top of an insulation (SiO2) layer, reducing the coupling capacitance between the channel and the substrate as compared to the bulk CMOS. The other advantages of an SOI MOSFET include higher current drive and higher speed, since doping-free channels lead to higher carrier mobility. Additionally, the thin body minimizes the current leakage from the source

Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. © 2013 Laha and Kaya; licensee InTech. This is an open access article distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. © 2013 LLaha and Kaya; licensee InTech. This is a paper distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

©2012 Laha and Kaya, licensee InTech. This is an open access chapter distributed under the terms of the

to drain as well as to the substrate, which makes the SOI MOSFET a highly desirable device applicable for high-speed and low-power applications. However, even these redeeming features are not expected to provide extended lifetime for the conventional MOSFET scaling below 22nm and more dramatic changes to device geometry, gate electrostatics and channel material are required. Such extensive changes are best introduced gradually, however, especially when it comes to new materials. It is the focus on 3D transistor geometry and electrostatic design, rather than novel materials, that make the multi-gate (i.e double, triple, surround) MOSFETs as one of the most suitable candidates for the next phase of evolution in Si MOSFET technology [2]- [5].

Being the simpler and relatively easier to fabricate among the multigate MOSFET structures (MIGFET, Π-MOSFET and so on) the double gate MOSFET (DG-MOSFET) (Fig. 1) is chosen here to explore these new circuit possibilities. The DG-MOSFET architectures can efficiently control the channel from two sides of instead of one as in planar bulk MOSFETs. The advantages of DG-MOSFETs are as follows [6]:


Due to the reasons stated above, the last decade has witnessed a frenzy of design activity to evaluate, compare and optimize various multi-gate geometries, mostly from the digital CMOS viewpoint [7], [8]. While this effort is still ongoing, the purpose of the present chapter is to underline and exemplify the massive increase in the headroom for CMOS nano-circuit engineering of RF communication systems, when the conventional MOSFET architecture is augmented with one extra gate.

The great potential of DG-MOSFETs for new directions in tunable analog and reconfigurable digital circuit engineering has been explored before in [9]. The innate capability of this device has also been explored by others, such as the Purdue group led by K. Roy [6], [7] has demonstrated the impact of DG-MOSFETs (specifically in FinFET device architecture) for power reduction in digital systems and for new SRAM designs. Kursun (Wisconsin & Hong Kong) has illustrated similar power/area gains in sequential and domino-logic circuits [10]. A couple of French groups have recently provided a very comprehensive review of their DG-MOSFET device and circuit works in a single book [8]. Their works contain both simulation and practical implementation examples, similar to the work carried out by the AIST XMOS and XDXMOS initiative in Japan [11]-[13] as well as a unique DG-MOSFET implementation named FlexFET by the ASI Inc [14], [15]. Recently, Intel has announced the most dramatic change to the architecture of the transistor since the device was invented. They will henceforth build transistors in three dimensions, which they called the 3D-MOSFET [4], a device that corresponds to FinFET/DG-MOSFET.

#### **1.2. RF/Analog IC design**

In addition to features essential for digital CMOS scaling such as the higher *ION*/*IOFF* ratio and better short channel performance, DG-MOSFETs possess architectural features also

**Figure 1.** Generic DG MOSFET structure.

2 Analog Circuits

body.

in Si MOSFET technology [2]- [5].

augmented with one extra gate.

**1.2. RF/Analog IC design**

advantages of DG-MOSFETs are as follows [6]:

devices compared to bulk-CMOS structures.

a device that corresponds to FinFET/DG-MOSFET.

• Reduced subthreshold leakage current due to reduced SCE.

to drain as well as to the substrate, which makes the SOI MOSFET a highly desirable device applicable for high-speed and low-power applications. However, even these redeeming features are not expected to provide extended lifetime for the conventional MOSFET scaling below 22nm and more dramatic changes to device geometry, gate electrostatics and channel material are required. Such extensive changes are best introduced gradually, however, especially when it comes to new materials. It is the focus on 3D transistor geometry and electrostatic design, rather than novel materials, that make the multi-gate (i.e double, triple, surround) MOSFETs as one of the most suitable candidates for the next phase of evolution

Being the simpler and relatively easier to fabricate among the multigate MOSFET structures (MIGFET, Π-MOSFET and so on) the double gate MOSFET (DG-MOSFET) (Fig. 1) is chosen here to explore these new circuit possibilities. The DG-MOSFET architectures can efficiently control the channel from two sides of instead of one as in planar bulk MOSFETs. The

• Reduced Short Channel Effects (SCE) due to the presence of two gates and ultra-thin

• Reduced gate leakage current due to the use of thicker oxide. Lower SCE in DG devices and the higher driver current (due to two gates) allows the use of thicker oxide in DG

Due to the reasons stated above, the last decade has witnessed a frenzy of design activity to evaluate, compare and optimize various multi-gate geometries, mostly from the digital CMOS viewpoint [7], [8]. While this effort is still ongoing, the purpose of the present chapter is to underline and exemplify the massive increase in the headroom for CMOS nano-circuit engineering of RF communication systems, when the conventional MOSFET architecture is

The great potential of DG-MOSFETs for new directions in tunable analog and reconfigurable digital circuit engineering has been explored before in [9]. The innate capability of this device has also been explored by others, such as the Purdue group led by K. Roy [6], [7] has demonstrated the impact of DG-MOSFETs (specifically in FinFET device architecture) for power reduction in digital systems and for new SRAM designs. Kursun (Wisconsin & Hong Kong) has illustrated similar power/area gains in sequential and domino-logic circuits [10]. A couple of French groups have recently provided a very comprehensive review of their DG-MOSFET device and circuit works in a single book [8]. Their works contain both simulation and practical implementation examples, similar to the work carried out by the AIST XMOS and XDXMOS initiative in Japan [11]-[13] as well as a unique DG-MOSFET implementation named FlexFET by the ASI Inc [14], [15]. Recently, Intel has announced the most dramatic change to the architecture of the transistor since the device was invented. They will henceforth build transistors in three dimensions, which they called the 3D-MOSFET [4],

In addition to features essential for digital CMOS scaling such as the higher *ION*/*IOFF* ratio and better short channel performance, DG-MOSFETs possess architectural features also helpful for the design of massively integrated radio frequency analog and adaptive systems with minimal overhead to the fabrication sequence. Given the fact that they are designed for sub-22nm technology nodes, the DG MOSFETs can effectively handle GHz modulation, making them relevant for the RF/Analog/Mixed-Signal system-on-chip applications and giga-scale integration [16], [17].

The two most important metrics for RF CMOS/DG-CMOS circuits are the transit frequency *fT* and the maximum oscillation frequency *fmax*. The former is defined as the frequency at which the current gain of the active device is unity, while the latter is the frequency for which the power gain is unity. Both these quantities relate the achievable transconductance to "parasitics" as gate-source and gate-drain capacitances (*Cgs* and *Cgd*). In case of *fmax* the gate resistance *RG* is also considered as it deals with power dissipation. The *fT* increases with decreasing gate lengths and for a DG-MOSFET at 45 nm it is obtained around 400 GHz [18].

Also, they have reduced cross-talk and better isolation provided naturally by the SOI substrate, multi-finger gates, low parasitics and scalability. However, the DG-MOSFET's potential for facilitating mixed-signal and adaptive system design is highest when the two gates are driven with independent signals [19]. It is the independently-driven mode of operation that furnishes DG MOSFET with a unique capability to alter the front gate threshold via the back gate bias. This in turn leads to:


## **2. DG MOSFET modeling and simulation**

#### **2.1. ASU PTM for FinFETs**

The widely available compact models for SOI-based single-gate MOSFETs can not be used for the DG-MOSFETs, for which new surface-potential based models are developed [20]-[23].

**Figure 2.** The *ID* - *Vf g* characteristics of an n-type DG-MOSFETs at different back-gate bias conditions as observed in a) ASU PTM 32 nm DG FinFET b) ASU PTM 45 nm DG-FinFET technology with Synopsys HSPICE RF simulation.

Instead either physically-rigorous demanding TCAD simulations or approximate SPICE models utilizing two back-to-back MOSFETs mathematically coupled for improved accuracy may be used. In this chapter, most of the circuits investigated use this latter approach. We have used the ASU Predictive Technology Model for 45 nm & 32 nm DG FinFETs [24] for our simulations for most of the circuits. The circuit simulator used for the design and analysis is the industry standard Synopsys HSPICE RF. The reliability of these two ASU technology models are evident from the typical transfer characteristics of an n-type DG-MOSFET with independent back-gate biasing as shown in Figs. 2a & b. It is obvious that the front gate threshold can be tuned via the applied back-gate voltage, which is sufficient for us to confirm the tunable functionality and carry out a comparative study. This 'dynamic' threshold control is crucial to appreciate the tunable properties of the oscillator and amplifier circuits.

#### **2.2. UFDG SPICE**

The UFDG model is a process/physics and charge based compact model for generic DG MOSFETs [25]. The key parameters are related directly to the device physics . This model is a compact Poisson-Schrodinger solver for DG MOSFETs that physically accounts for the charge coupling between the front and the back gates. The UFDG allows operation in the independent gate mode and is applicable to FD SOI MOSFETs. The quantum mechanical modeling of the carrier confinement, dependent on the Ultra Thin body (UTB) thickness (t*Si*) as well as transverse electric field is incorporated via Newton Raphson iterations that link it to the classical formalism.

The dependence of carrier mobility on Si-film thickness, subject to the QM confinement and on transverse electric field is also accounted for in the model. The carrier velocity overshoot and dependence on carrier temperature is characterized in the UFDG transport modeling to account for the ballistic and quasiballistic transport in scaled DG MOSFETS [26]. The channel current is limited by the thermal injection velocity at the source, which is modeled based on the QM simulation. The UFDG model also accounts for the parasitic (coupled) BJT (current and charge) which can be driven by transient body charging current (due to capacitive coupling) and/or thermal generation, GIDL [27] and impact ionization currents, the latter of which is characterized by a non-local carrier temperature-dependent model for the ionization rate integrated across the channel and the drain.

The charge modeling which is patterned after that is physically linked to the channel-current modeling. All terminal charges and their derivatives are continuous for all bias conditions, as are all currents and their derivatives. Temperature dependence for the intrinsic device characteristics and associated model parameters are also implemented without the need for any additional parameters. This temperature dependence modeling is the basis for the self-heating option, which iteratively solves for local device temperature in DC and transient simulations in accord with a user defined thermal impedance.

The Relaxation Oscillator and the RF-Mixer analysis are carried with this simulator.

## **3. Transmitter design**

4 Analog Circuits

**0.1 0.2 0.3 0.4 0.5 0.6 0.7**

**− 0.30V − 0.15V 0.0V 0.15V**

**Vbg**

**2.2. UFDG SPICE**

to the classical formalism.

**Current (mA)**

**<sup>0</sup> 0.1 0.2 0.3 0.4 0.5 0.6 <sup>0</sup>**

**<sup>0</sup> 0.1 0.2 0.3 0.4 0.5 0.6 <sup>0</sup>**

**Voltage, Vfg (V)**

(b)

**0.1 0.2 0.3 0.4 0.5**

**Figure 2.** The *ID* - *Vf g* characteristics of an n-type DG-MOSFETs at different back-gate bias conditions as observed in a) ASU

Instead either physically-rigorous demanding TCAD simulations or approximate SPICE models utilizing two back-to-back MOSFETs mathematically coupled for improved accuracy may be used. In this chapter, most of the circuits investigated use this latter approach. We have used the ASU Predictive Technology Model for 45 nm & 32 nm DG FinFETs [24] for our simulations for most of the circuits. The circuit simulator used for the design and analysis is the industry standard Synopsys HSPICE RF. The reliability of these two ASU technology models are evident from the typical transfer characteristics of an n-type DG-MOSFET with independent back-gate biasing as shown in Figs. 2a & b. It is obvious that the front gate threshold can be tuned via the applied back-gate voltage, which is sufficient for us to confirm the tunable functionality and carry out a comparative study. This 'dynamic' threshold control

is crucial to appreciate the tunable properties of the oscillator and amplifier circuits.

The UFDG model is a process/physics and charge based compact model for generic DG MOSFETs [25]. The key parameters are related directly to the device physics . This model is a compact Poisson-Schrodinger solver for DG MOSFETs that physically accounts for the charge coupling between the front and the back gates. The UFDG allows operation in the independent gate mode and is applicable to FD SOI MOSFETs. The quantum mechanical modeling of the carrier confinement, dependent on the Ultra Thin body (UTB) thickness (t*Si*) as well as transverse electric field is incorporated via Newton Raphson iterations that link it

The dependence of carrier mobility on Si-film thickness, subject to the QM confinement and on transverse electric field is also accounted for in the model. The carrier velocity overshoot and dependence on carrier temperature is characterized in the UFDG transport modeling to account for the ballistic and quasiballistic transport in scaled DG MOSFETS [26]. The channel current is limited by the thermal injection velocity at the source, which is modeled based on the QM simulation. The UFDG model also accounts for the parasitic (coupled) BJT (current and charge) which can be driven by transient body charging current (due to capacitive coupling) and/or thermal generation, GIDL [27] and impact ionization currents, the latter of which is characterized by a non-local carrier temperature-dependent model for

the ionization rate integrated across the channel and the drain.

PTM 32 nm DG FinFET b) ASU PTM 45 nm DG-FinFET technology with Synopsys HSPICE RF simulation.

**− 0.75V − 0.5V − 0.25V 0.0V**

**Vbg**

**Current (mA)**

**Voltage, Vfg (V)**

(a)

The transmitter (Fig. 3) consists of an oscillator, modulator, power amplifier and finally an antenna. A matching network (*Z*<sup>0</sup> in Fig. 3) which maximizes the power transfer and minimizes the reflection losses generally precedes the 50 Ω antenna. In this article, the components that have been investigated with DG-MOSFET technology include a Relaxation Oscillator, LC Oscillator, an OOK Modulator and two different topologies of Power Amplifier. It is to be noted that the oscillators are also part of the receiver design and has its use in RF Mixer and Phase Locked Loops (PLLs).

**Figure 3.** The transmitter block consisting of the oscillator, modulator and power amplifier and other passive devices/circuits.

#### **3.1. Relaxation oscillator**

Relaxation oscillator is an inductorless non-resonant oscillator that is either current controlled or voltage controlled. The second circuit in [28] implements a dual input S/R latch. As illustrated in Fig. 4a the NOR gates used to construct the latch consist of only four DG-MOSFET as opposed to eight required in conventional CMOS architecture. This serves to save circuit area and a decent amount of power dissipation. The two inverters are biased with equal copies of the input current, *IIN*, from the current mirrors implemented with three pMOS. The back gate of the two inverters are tuned in voltage to vary the frequency.

The DG-MOSFET implementation also has two advantages, firstly it can be used also as a VCO by virtue of the back gate bias and secondly it operates more efficiently with a higher upper limit as a result of very high transconductance of DG-MOSFETs [29]. Although the accessible frequency range in the VCO mode is dwarfed in contrast to massive ICO response given in logarithmic scale, the operation as a VCO provides the circuit with an extra degree of freedom in tuning. Specifically, the voltage operated fine 'vernier' frequency tuning sets a frequency with precision after it has been 'coarsely' selected by the current operated crude logarithmic tuning.

**Figure 4.** a)The current/voltage controlled relaxation oscillator in DG-MOSFET technology. b) The 'crude tuning' of the relaxation oscillator with varying current. c) The fine tuning in frequency with back gate bias when *V<sup>p</sup> bg* <sup>=</sup> *<sup>V</sup><sup>n</sup> bg* of the relaxation oscillator.

In Fig. 4b, we can verify the frequency has a log-log relationship with the current. The frequency ranges from 30 MHz to a few GHz for a change in current supply from 0.4 *µ*A to 50 *µ*A. This coarse tuning in frequency is supported via back gate fine tuning of the DG MOSFET inverters. For a constant current and voltage supply, the frequency can be tuned to vary in the order of MHz, as the inverter back gate voltage varies from 0.1 V to 1 V. It is observed, a higher *VDD* results in a slower oscillation at a fixed input current, because the SR Latch takes longer time to reach a higher switching threshold (∼ 1/2*VDD*) as *VDD* is increased. The Fig. 4c demonstrates these facts with three different current sources and supply voltage. The phase noise of the oscillator is -104 dBc/Hz at 1 MHz offset. All these analysis are carried with 45 nm DG-MOSFET using UFDG SPICE.

#### **3.2. LC oscillator and OOK modulator**

6 Analog Circuits

**0.1**

oscillator.

**Frequency (GHz)**

**1**

**10**

VDD

**0 0.2 0.4 0.6 0.8 1**

**n = Vbg p**

*bg* <sup>=</sup> *<sup>V</sup><sup>n</sup>*

**0.8 V; 2** µ**A 0.6 V; 2** µ**A 1.0 V; 10** µ**A 0.8 V; 10** µ**A 1.2 V; 50** µ**A 1.0 V; 50** µ**A**

*bg* of the relaxation

**VDD;Iin**

**Back Gate Bias [V], Vbg**

(c)

Q

(a)

C

S

Vbg p

VDD VDD VDD

Vbg n

**0.6 V; 0.4 V (Single) 0.8 V; 0.4 V (Single) 1 V; 0.6 V (Dual) 1.2 V; 0.6 V (Dual) VDD; Vbg p**

relaxation oscillator with varying current. c) The fine tuning in frequency with back gate bias when *V<sup>p</sup>*

analysis are carried with 45 nm DG-MOSFET using UFDG SPICE.

Q

**0.1 <sup>1</sup> <sup>10</sup> <sup>100</sup> 0.01**

(b)

**Current (**µ**A)**

I IN

> Vbg p

> > R

C

Vbg n

**0.01**

**Figure 4.** a)The current/voltage controlled relaxation oscillator in DG-MOSFET technology. b) The 'crude tuning' of the

In Fig. 4b, we can verify the frequency has a log-log relationship with the current. The frequency ranges from 30 MHz to a few GHz for a change in current supply from 0.4 *µ*A to 50 *µ*A. This coarse tuning in frequency is supported via back gate fine tuning of the DG MOSFET inverters. For a constant current and voltage supply, the frequency can be tuned to vary in the order of MHz, as the inverter back gate voltage varies from 0.1 V to 1 V. It is observed, a higher *VDD* results in a slower oscillation at a fixed input current, because the SR Latch takes longer time to reach a higher switching threshold (∼ 1/2*VDD*) as *VDD* is increased. The Fig. 4c demonstrates these facts with three different current sources and supply voltage. The phase noise of the oscillator is -104 dBc/Hz at 1 MHz offset. All these

**0.1**

**Frequency [GHz]**

**1**

**10**

VDD

Q

Q

LC oscillators consists of inductors and capacitors connected in parallel. Although inductors consume a lot of area when compared to the inductorless oscillator described above oscillators, it is a must in RF Design to use inductors because of two primary reasons [30]. They are as follows:


We have chosen the differential negative resistance voltage controlled oscillator (VCO) variant of the LC oscillator (Fig. 5a) for the investigation. The latch circuit in the differential mode serves as negative resistance to nullify the effects of a positive resistance arising out of the imperfect inductor. The Q factor determines the undesired resistance value (R) of the inductor (L) at the resonance frequency, *ω*. Modeling the resistive loss in the inductor, L by the parallel resistance (R) we can write [30]:

$$Q = \frac{R}{\omega L} \tag{1}$$

The LC tank achieves a frequency that is much higher and has a phase noise that is much lower than that of the relaxation oscillator. This is primarily because of the resonance of the circuit.

The OOK Modulation is a non-coherent modulation scheme that modulates the carrier only when the circuit is in the 'ON' state. It is the special case of Amplitude Shift Key (ASK) modulation where no carrier is present during the transmission of a 'zero'. The bit error rate for OOK modulation without the implementation of any error correcting scheme is given by [31]

$$BER = \frac{1}{2} \exp(\frac{-E\_b}{2N\_0}) + \frac{1}{2}Q\sqrt{\frac{E\_b}{N\_0}}\tag{2}$$

Although, the associated bit error rate of OOK modulation is inferior to that of other coherent modulation schemes, simple OOK modulation scheme is implemented to avoid the complicated carrier recovery circuit and for their ability to modulate very high frequency signals in extremely long-life battery operated applications. The non-coherent OOK demodulation generally employs an envelope detector in the receiver which saves the power, area, cost and complexity since no local oscillator (LO) or carrier synchronization scheme is involved.

#### *3.2.1. Design and simulation*

The DG-MOSFET based VCO can be tuned from the back gate for controlling the rms voltage (*Vrms*). Fig. 5b illustrates this interesting tunable feature of the DG MOSFET VCO. Without any change in the supply, the *Vrms* can be controlled via back gate bias (*Vbg*), which can have

**Figure 5.** a) The OOK Modulator circuit with the VCO. The proposed OOK Modulator uses only two DG-MOSFET for modulation and switching. b) The variation of VCO output amplitude at different *Vbg*. Inset: Amplitude and frequency variation for different *Vbg*. c) The phase noise of the VCO at 60 GHz. The phase noise at 1 MHz offset is observed at -133 dBc/Hz in time variant Hajimiri-Lee model [32].

application in many adaptive low power wireless systems. The bias at the back gate can also be tuned to change the oscillation frequency after a certain threshold (0.5 V) (Fig. 5b inset). Although DG-MOSFET is not reputed for its noise performance, the phase noise of the 60 GHz VCO is found to be -133 dBc/Hz at 1 MHz offset (Fig. 5c) which is comparable to that of bulk CMOS [33]. As expected, the phase noise is dominated by the process dependent flicker noise of slope ∼ -30 dB/decade. The corner frequency *fcor* is obtained around 10 MHz.

The proposed novel DG-MOSFET based OOK Modulator [34] consists of only two DG-MOSFETs making it ideal for use in ultra low power systems (Fig. 5a). The modulator can

**Figure 6.** The OOK Modulated output for a carrier frequency of 60 GHz and data rate of 1 Gbps. The input data sequence resembles 50% duty cycle.

work up to a data rate of 5 Gbps without any discernible distortion for 60 GHz carrier. The DG-MOSFET MN4 acts as the key OOK modulating device. The 60 GHz sinusoidal carrier from the VCO is fed into one of the gates of the transistor whereas the pulsed digital data is input to the other gate. The charge capacitive coupling of the two gates provided by the thin Si body determines the modulation, and therefore depends on the bias conditions of the two gates as well as device dimensions. The modulation occurs when the device operates in the saturation or in cut-off region, that is when there is either a '1' or '0' respectively emanating from the pulsed digital data. In other words, the modulation takes place at all instants of time. The symmetric DG-MOSFET MN3 acts as the switch and is kept at a high threshold voltage (filled) for better electrostatics and keying and to maximize the I*ON*/I*OFF* ratio. The MN3 is turned on at the 'HIGH' state of the pulsed data and remains off at the 'LOW' state, maintaining the principle of OOK Modulation scheme. The modulated output is obtained at the drain of MN3. This is illustrated in Fig. 6. All these analysis are carried in 32 nm ASU PTM FinFET technology.

#### **3.3. Power Amplifier**

8 Analog Circuits

**−0.4 0 0.4 0.8 1.2 1.6**

**0.2 0.4 0.6 0.8 Amplitude (V)**

Hajimiri-Lee model [32].

**Voltage (V)**

 **Vbg1 Vbg2**

**C**

**MN2 MN1**

**0.2 0.24 0.28 0.32 0.36 0.4**

**0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 <sup>0</sup>**

**Vbg (V)**

**Time (GHz)**

(b)

**VCO** 

**Frequency (GHz)**

**0.9V 0.6V 0.3V Vbg**

**VDD**

**Vout1** 

**Vout2 : To PA L1 L2** 

**From VCO, (60 GHz Carrier)** 

> **−160 −130 −100 −70 −40 −10**

**Phase Noise (dBc/Hz)**

**Figure 5.** a) The OOK Modulator circuit with the VCO. The proposed OOK Modulator uses only two DG-MOSFET for modulation and switching. b) The variation of VCO output amplitude at different *Vbg*. Inset: Amplitude and frequency variation for different *Vbg*. c) The phase noise of the VCO at 60 GHz. The phase noise at 1 MHz offset is observed at -133 dBc/Hz in time variant

application in many adaptive low power wireless systems. The bias at the back gate can also be tuned to change the oscillation frequency after a certain threshold (0.5 V) (Fig. 5b inset). Although DG-MOSFET is not reputed for its noise performance, the phase noise of the 60 GHz VCO is found to be -133 dBc/Hz at 1 MHz offset (Fig. 5c) which is comparable to that of bulk CMOS [33]. As expected, the phase noise is dominated by the process dependent flicker noise of slope ∼ -30 dB/decade. The corner frequency *fcor* is obtained around 10 MHz.

The proposed novel DG-MOSFET based OOK Modulator [34] consists of only two DG-MOSFETs making it ideal for use in ultra low power systems (Fig. 5a). The modulator can

(a)

**L3** 

**VDD**

**OOK Modulator** 

**MN4**

**Data, 1 Gbps**

**<sup>102</sup> <sup>103</sup> <sup>104</sup> <sup>105</sup> <sup>106</sup> <sup>107</sup> <sup>108</sup> −190**

(c)

**Frequency Offset (Hz)**

**1 MHz Offset @ 60 GHz Carrier**

**MN3** 

The Power Amplifier (PA) is the final stage of transmitter design before signal transmission through antenna. They are responsible for amplifying the power level of the transmitted signal several times so that the received signal is above the sensitivity of the receiver which is calculated from the link budget analysis. The PAs are divided into various classes such as A, B, AB, C D, E, F etc. Among these classes A, B, AB and C incorporate similar design methodologies differing only in the biasing point. Among these Class A amplifier is the most linear and is widely used in RF transmitter design although they have the least Power Added Efficiency (PAE). Several acclaimed literatures [35], [30] are available for interested readers on these concepts. This book chapter focusses on the design of tunable DG-MOSFET Class A PA.

The design of the wide band and high gain PA is a challenging task, especially in ultra-compact MOSFETs with low output impedance. Consequently, in [36], we simply adapted two recent single-gate implementations with competitive features in the GHz range, which allows a more fair performance comparison to be made between different devices. In the first PA topology [37], we modify the architecture slightly for the DG-MOSFET to explore its gain and bandwidth characteristics as well as its tunability. The second topology reported here is a three stage single-ended, common-source (CS) PA similar to the one reported by Yao et al. [38] for conventional CMOS. The basic difference over the published topologies in both cases is the length of the DG-MOSFET devices (45 nm) that is substantially smaller. There are a number of reasons for this gate length choice. Firstly, the proposed PAs are essentially designed for low-power highly compact Si mixed-signal radio applications where the range and area will be typically quite limited. Secondly, the DG-MOSFET architecture is inherently a narrow width device technology in which very large number of fingers needed to obtain large W/L ratios. Finally, we wish to implement a PA for ultra-compact wide-band RF CMOS applications such as vehicular anti-collision radar. Given that DG-MOSFET technology is aimed for sub-22 nm digital technologies, 45 nm is a good compromise for analog circuit implementation.

The next two sections will discuss in detail about these design modifications and provide their simulated response including gain tuning, peak gain, bandwidth and linearity. Interested readers can compare the performances of these power amplifiers with a few other conventional designs in [36].

#### *3.3.1. Topology A - Design and simulation*

The circuit topology of the first wide band (3-33 GHz) DG-MOSFET PA is shown in Fig. 7a, which consists of three DG-MOSFETs in a Darlington cascode arrangement. The common source transistor *MN*<sup>1</sup> operates in the symmetric mode while the two transistors *MN*<sup>2</sup> and *MN*<sup>3</sup> are configured for independent mode operation. The width of *MN*<sup>1</sup> is taken to be 1 *µ*m while the width for transistors *MN*<sup>2</sup> and *MN*<sup>3</sup> are kept higher at 2.4 *µ*m for better input return loss and optimized gain performance. *MN*<sup>3</sup> is biased at 2.6 V (*Vb*1). The back gate of the transistors *MN*<sup>2</sup> and *MN*<sup>3</sup> are biased for gain tuning. The resistors *R*<sup>1</sup> and *R*<sup>2</sup> complete a self biasing network for Class A operation. This modified DG-MOSFET darlington configuration is divided into two stages. The first stage is the series peaking stage and inter-stage matching, and the second stage is the output power stage.

The series peaking circuit consisting of *R*<sup>3</sup> and *L*<sup>1</sup> increases the output load pull impedance, and also provides the peaking impedance for feeding forward signals. The inductor *L*<sup>3</sup> along with the source degeneration circuit consisting of *R*<sup>4</sup> and *L*<sup>2</sup> yields in real part wide band inter-stage impedance matching for maximizing the power transfer between the stages. The common source transistor *MN*<sup>2</sup> and *MN*<sup>3</sup> are connected in cascode. The transistor *MN*<sup>3</sup> acts in common gate configuration and one of its gate is grounded with the aid of the peaking inductor *L*<sup>4</sup> and a bypass capacitor *C*<sup>1</sup> [30]. Along with achieving a near constant gain by maintaining the flatness, the bandwidth of the amplifier is also increased with the aid of this peaking inductor. A high pass L-network (*L*<sup>5</sup> & *C*3) is used as the matching circuit.

Our simulation verifies the forward gain (*S*21) to vary from 3 to 33 GHz, while maintaining a desired flatness (Fig. 7b). The gain changes by less than 20% in this frequency range, attesting to the extreme flatness. The peak gain is observed at 24.5 dB. The input and output return

10 Analog Circuits

implementation.

conventional designs in [36].

*3.3.1. Topology A - Design and simulation*

The design of the wide band and high gain PA is a challenging task, especially in ultra-compact MOSFETs with low output impedance. Consequently, in [36], we simply adapted two recent single-gate implementations with competitive features in the GHz range, which allows a more fair performance comparison to be made between different devices. In the first PA topology [37], we modify the architecture slightly for the DG-MOSFET to explore its gain and bandwidth characteristics as well as its tunability. The second topology reported here is a three stage single-ended, common-source (CS) PA similar to the one reported by Yao et al. [38] for conventional CMOS. The basic difference over the published topologies in both cases is the length of the DG-MOSFET devices (45 nm) that is substantially smaller. There are a number of reasons for this gate length choice. Firstly, the proposed PAs are essentially designed for low-power highly compact Si mixed-signal radio applications where the range and area will be typically quite limited. Secondly, the DG-MOSFET architecture is inherently a narrow width device technology in which very large number of fingers needed to obtain large W/L ratios. Finally, we wish to implement a PA for ultra-compact wide-band RF CMOS applications such as vehicular anti-collision radar. Given that DG-MOSFET technology is aimed for sub-22 nm digital technologies, 45 nm is a good compromise for analog circuit

The next two sections will discuss in detail about these design modifications and provide their simulated response including gain tuning, peak gain, bandwidth and linearity. Interested readers can compare the performances of these power amplifiers with a few other

The circuit topology of the first wide band (3-33 GHz) DG-MOSFET PA is shown in Fig. 7a, which consists of three DG-MOSFETs in a Darlington cascode arrangement. The common source transistor *MN*<sup>1</sup> operates in the symmetric mode while the two transistors *MN*<sup>2</sup> and *MN*<sup>3</sup> are configured for independent mode operation. The width of *MN*<sup>1</sup> is taken to be 1 *µ*m while the width for transistors *MN*<sup>2</sup> and *MN*<sup>3</sup> are kept higher at 2.4 *µ*m for better input return loss and optimized gain performance. *MN*<sup>3</sup> is biased at 2.6 V (*Vb*1). The back gate of the transistors *MN*<sup>2</sup> and *MN*<sup>3</sup> are biased for gain tuning. The resistors *R*<sup>1</sup> and *R*<sup>2</sup> complete a self biasing network for Class A operation. This modified DG-MOSFET darlington configuration is divided into two stages. The first stage is the series peaking stage

The series peaking circuit consisting of *R*<sup>3</sup> and *L*<sup>1</sup> increases the output load pull impedance, and also provides the peaking impedance for feeding forward signals. The inductor *L*<sup>3</sup> along with the source degeneration circuit consisting of *R*<sup>4</sup> and *L*<sup>2</sup> yields in real part wide band inter-stage impedance matching for maximizing the power transfer between the stages. The common source transistor *MN*<sup>2</sup> and *MN*<sup>3</sup> are connected in cascode. The transistor *MN*<sup>3</sup> acts in common gate configuration and one of its gate is grounded with the aid of the peaking inductor *L*<sup>4</sup> and a bypass capacitor *C*<sup>1</sup> [30]. Along with achieving a near constant gain by maintaining the flatness, the bandwidth of the amplifier is also increased with the aid of this

Our simulation verifies the forward gain (*S*21) to vary from 3 to 33 GHz, while maintaining a desired flatness (Fig. 7b). The gain changes by less than 20% in this frequency range, attesting to the extreme flatness. The peak gain is observed at 24.5 dB. The input and output return

peaking inductor. A high pass L-network (*L*<sup>5</sup> & *C*3) is used as the matching circuit.

and inter-stage matching, and the second stage is the output power stage.

**Figure 7.** a) The DG MOSFET based power amplifier circuit in modified darlington cascode configuration. Transistors *MN*<sup>1</sup> operates in the symmetric mode while *MN*<sup>2</sup> and *MN*<sup>3</sup> operate in independent mode with the back gates used for dynamic tuning. b) The S parameters which provide the gain (*S*21) and reflection losses (*S*<sup>11</sup> & *S*22) of the power amplifier. This is measured for *Vbg* = 0.2 V. c) The back gate dependence of the gain is clearly evident. The gain changes by ∼ 10 dB in the tuning range of *Vbg*. Inset: Gain variation with *Vbg* at different frequencies. d) The rollet stability factor (K) is above unity in the operating range of 2 - 32 GHz verifying the amplifier to remain unconditionally stable in this range. K drops below unity beyond ∼ 38 GHz.

losses (*S*<sup>11</sup> & *S*22) are also obtained from the simulation. Fig. 7c shows these S parameters at a *Vbg* of 0.2 V which is applied at the back gate of the transistors *MN*<sup>2</sup> and *MN*3. The back gate voltage (*Vbg*) is varied from 0.1 V to 0.25 V for the operating frequency range during which the gain of the amplifier increases considerably. The range of gain tuning is observed to be limited to almost 10 dB. The inset of the figure shows the gain variation with *Vbg* at different frequencies. The unconditional stability of the amplifier is verified measuring the rollet stability factor, K which is given as

$$K = \frac{1 - |\mathbf{S}\_{11}|^2 - |\mathbf{S}\_{22}|^2 + |\triangle|^2}{2|\mathbf{S}\_{12}\mathbf{S}\_{21}|}\tag{3}$$

$$
\triangle = \mathbf{S}\_{11}\mathbf{S}\_{22} - \mathbf{S}\_{12}\mathbf{S}\_{21} \tag{4}
$$

**Figure 8.** a) The three stage DG MOSFET based power amplifier circuit. All the three transistors operate in the independent mode. b) The S parameters which provide the gain (*S*21) and reflection losses (*S*<sup>11</sup> & *S*22) of the power amplifier. This is also measured for *Vbg* = 0.2 V. c) The back gate dependence of the gain is clearly evident. The gain changes by ∼ 6 dB in the tuning range of *Vbg*. Inset: Gain variation with *Vbg* at different frequencies. d) The rollet stability factor (K) is well over unity in the operating range of 60 - 90 GHz verifying the amplifier to remain unconditionally stable in the range.

The value of K is observed to be above unity in the operating frequency range indicating the unconditional stability of the amplifier (Fig. 7d). The back gate tuning of the PA is verified from Fig. 5. The 1 dB compression point (P1*dB*) and the 3rd order Input Intercept Point (IIP3) are found to be 11.9 dBm and 27.5 dBm, respectively, indicating the suitability of the circuit. The 15.6 dB difference between P1*dB* and IIP3 can be attributed to the scaling down of DG MOSFET to 45 nm [35]. The power added efficiency (PAE) and the fractional bandwidth (FB) of the amplifier is ∼12% and 176% respectively.

#### *3.3.2. Topology B - Design and simulation*

In the second topology, the DG-MOSFET Class A amplifier is implemented in three stages (Fig. 8a). Although the earlier cascode topology has higher & flatter gain, and larger output impedance, the CS configuration is advantageous in terms of the lower supply voltage required, leading to higher efficiency. All the transistors in this topology operate in the

**Figure 9.** The receiver block consisting of the RF Front End (LNA & RF Mixer) and the Demodulator (Envelope Detector, for non-coherent detection or PLL, for coherent detection).

independent mode. The source degeneration inductors *L*3, *L*<sup>6</sup> and *L*<sup>9</sup> along with the inter stage inductors *L*<sup>4</sup> and *L*<sup>7</sup> maximizes the power transfer and improves linearity [35]. The width of the three transistors are kept fixed at 1.2 *µ*m. The source and the bias voltage (*Vb*) are both kept at 1 V.

Although the 3-dB bandwidth is ≥ 50 GHz, as evident from Fig. 8b, for all cases of back gate voltages (Fig. 8c) a more realistic operating range of this amplifier can be considered to be in the range of 60 - 90 GHz. Once again, the inset of the Fig. 8 shows the gain variation with *Vbg* at different frequencies. The peak gain achieved is ≥ 8 dB. The rollet stability factor remains more than unity for this operating range as shown by simulated data in Fig. 8d. The P1*dB* and the IIP3 are found to be 7.2 dBm and 19.8 dBm respectively. The PAE and the FB of this amplifier is ∼14% and 40% respectively.

## **4. Receiver design**

12 Analog Circuits

**L2** 

**L3** 

**RFin**

**L1**

**−6**

**−2**

**S21 (dB)**

**2**

**6**

**10**

**VDD VDD VDD** 

**L5**

**Vb Vb** 

(a)

**<sup>40</sup> <sup>50</sup> <sup>60</sup> <sup>70</sup> <sup>80</sup> <sup>90</sup> <sup>100</sup> −10**

(c)

of the amplifier is ∼12% and 176% respectively.

*3.3.2. Topology B - Design and simulation*

**S21 (dB)**

**Frequency (GHz)**

**0.2 0.3 0.4 0.5 <sup>0</sup>**

**55GHz 75GHz 95GHz**

**Back gate Bias (V)**

**R1 R2 MN1 MN2 MN3** 

**L6**

**L4** 

**Vbg Vbg Vbg** 

**C1 C2 C3**

**L7**

**L8**

**RFout**

**−20**

**3**

**5**

**Rollet Stability Factor**

**Figure 8.** a) The three stage DG MOSFET based power amplifier circuit. All the three transistors operate in the independent mode. b) The S parameters which provide the gain (*S*21) and reflection losses (*S*<sup>11</sup> & *S*22) of the power amplifier. This is also measured for *Vbg* = 0.2 V. c) The back gate dependence of the gain is clearly evident. The gain changes by ∼ 6 dB in the tuning range of *Vbg*. Inset: Gain variation with *Vbg* at different frequencies. d) The rollet stability factor (K) is well over unity in the

The value of K is observed to be above unity in the operating frequency range indicating the unconditional stability of the amplifier (Fig. 7d). The back gate tuning of the PA is verified from Fig. 5. The 1 dB compression point (P1*dB*) and the 3rd order Input Intercept Point (IIP3) are found to be 11.9 dBm and 27.5 dBm, respectively, indicating the suitability of the circuit. The 15.6 dB difference between P1*dB* and IIP3 can be attributed to the scaling down of DG MOSFET to 45 nm [35]. The power added efficiency (PAE) and the fractional bandwidth (FB)

In the second topology, the DG-MOSFET Class A amplifier is implemented in three stages (Fig. 8a). Although the earlier cascode topology has higher & flatter gain, and larger output impedance, the CS configuration is advantageous in terms of the lower supply voltage required, leading to higher efficiency. All the transistors in this topology operate in the

**7**

**−10**

**S parameters (dB)**

**0**

**10**

**<sup>20</sup> <sup>30</sup> <sup>40</sup> <sup>50</sup> <sup>60</sup> <sup>70</sup> <sup>80</sup> <sup>90</sup> <sup>100</sup> −30**

(b)

**<sup>50</sup> <sup>60</sup> <sup>70</sup> <sup>80</sup> <sup>90</sup> <sup>100</sup> <sup>1</sup>**

(d)

**Frequency (GHz)**

**Frequency (GHz)**

**S21 S11 S22**

**L9**

**0.2V 0.3V 0.35V 0.4V 0.45V 0.5V**

**Vbg**

operating range of 60 - 90 GHz verifying the amplifier to remain unconditionally stable in the range.

The front end of the receiver consists of a Low Noise Amplifier (LNA) and RF Mixer. To demodulate a non-coherent signal an Envelope Detector is used while to demodulate a coherent signal a Phase Locked Loop is generally used (Fig. 9). In this chapter, we have designed an LNA, Envelope Detector and a Charge Pump Phase Frequency Detector (which is an essential component in PLL design) and analyzed an existing RF Mixer.

#### **4.1. Low Noise Amplifier**

The Low Noise Amplifier (LNA) is an essential component in the front-end of any communication/navigation receiver. The received signal at antenna is very weak and therefore it is necessary to amplify the signal for demodulation and processing. At the same time the noise figure of the amplifier has to be very low because the received signal will eventually be passed to non-linear devices such as RF Mixers which add noise. Therefore LNA design optimizes to minimize the noise level at the first stage of the receiver i.e. at the LNA itself. Other characteristics that require from an LNA include high gain, impedance matching linearity and stability.

The circuit topology of the tunable 45 nm DG-MOSFET LNA implemented here is shown in Fig. 10, which consists of three DG-MOSFETs in a 2 stage common source cascode topology. The common source transistor *MN*<sup>1</sup> operates in the symmetric mode while the two transistors *MN*<sup>2</sup> and *MN*<sup>3</sup> are configured for independent mode operation. The common

**Figure 10.** The DG MOSFET based LNA in common source cascode configuration. Transistors *MN*<sup>1</sup> operates in the symmetric mode while *MN*<sup>2</sup> and *MN*<sup>3</sup> operate in the independent mode with the back gates used for dynamic tuning.

**Figure 11.** a) The gain (*S*21) of the LNA varies with *Vbg*. This is measured for *Vbg* = 0.3 V to 0.7 V. b) The noise figure dependence on *Vbg* of the LNA is evident. The NF changes by 4.4 dB in the tuning range of *Vbg* at 65 GHz.

source transistor *MN*<sup>2</sup> and *MN*<sup>3</sup> are connected in cascode. The transistor *MN*<sup>3</sup> acts in common gate configuration. The width of *MN*<sup>1</sup> is taken to be 1 *µ*m while the width for transistors *MN*<sup>2</sup> and *MN*<sup>3</sup> are kept higher at 2.4 *µ*m for better input return loss and optimized gain performance. The supply, *VDD* is kept constant at 1.2 V. *MN*<sup>3</sup> is biased at 2 V (*Vb*). The back gate of the transistors *MN*<sup>2</sup> and *MN*<sup>3</sup> are biased for gain tuning.

The series peaking circuit consists of an inductive load, *L*2, that allows for low voltage operation and resonates with the inter stage capacitance, *C*1, enabling a higher operating frequency [30]. The inductor *L*<sup>1</sup> is set to resonate with the gate source capacitance of *MN*1. The source degeneration circuit consisting of *L*<sup>3</sup> yields (in real part) wide band impedance matching to maximize the inter-stage power transfer. The inductor *L*<sup>4</sup> tunes out the middle pole of the cascode, thus compensating for the lower *fT* [39] of DG-MOSFET which is nearly 150 GHz at 45 nm.

The simulation shows the 3-dB bandwidth to be 15 GHz, ranging from 60 to 75 GHz. The forward gain (*S*21) achieves a peak value of 15 dB at 65 GHz for *Vbg* = 0.7 V (Fig. 11a). Beyond this maximum operating voltage the gain gets saturated and is independent of *Vbg*. The peak gain reduces gradually as *Vbg* is reduced and drops to ∼5 dB for *Vbg* = 0.3 V. The power dissipated (*Pdc*) by the LNA also varies with *Vbg*, reaching 18 mW at *Vbg* = 0.7 V. Similarly, the LNA noise figure (NF) also depends upon the back gate bias, dropping to a minimum at peak gain as expected. It ranges from 7 dB at *Vbg* = 0.7 V to 11.4 dB at *Vbg* = 0.3 V (Fig. 11b). Clearly, the back gate tuning provides a convenient tool to optimize specific device performance parameters, setting up unique trade-offs such as that between power and gain.

The proposed LNA is unconditionally stable in the operating frequency range, verified from the simulated rollet stability factor, i.e. K > 1. The circuit is also simulated for linearity performance using a two tone frequency analysis near 60 GHz and the observed 3*rd* order Input Intercept Point (IIP3) is −5.2 dBm.

Overall, the DG-MOSFET implementations have impressive characteristics that either match or exceed the bulk MOSFET and even SiGe counterparts [40]-[42]. It is fair to point out that much of this response can be attributed to small gate length in our designs. However, a short gate length has also consequences for linearity and lower output impedance, with which this architecture appears to cope well.

#### **4.2. RF mixers**

14 Analog Circuits

**−40**

**−50**

150 GHz at 45 nm.

**−20**

**−30**

**−10**

**S21 (dB)**

**0**

**20 10** **RFin**

**40 50 60 70 80**

(a)

**Frequency (GHz)**

**L2** 

**C1** 

**MN1** 

mode while *MN*<sup>2</sup> and *MN*<sup>3</sup> operate in the independent mode with the back gates used for dynamic tuning.

**0.3 0.4 0.5 0.6 0.7**

dependence on *Vbg* of the LNA is evident. The NF changes by 4.4 dB in the tuning range of *Vbg* at 65 GHz.

back gate of the transistors *MN*<sup>2</sup> and *MN*<sup>3</sup> are biased for gain tuning.

**Vbg (V)**

**R1** 

**Vb** 

**Figure 10.** The DG MOSFET based LNA in common source cascode configuration. Transistors *MN*<sup>1</sup> operates in the symmetric

**VDD** 

**L3** 

**L1** 

**Vbg**

**<sup>20</sup> <sup>30</sup> <sup>40</sup> <sup>50</sup> <sup>60</sup> <sup>70</sup> <sup>80</sup> <sup>90</sup> <sup>0</sup>**

**0.7 0.6 0.5 0.4 0.3**

**Vbg (V)**

**Frequency (GHz)**

(b)

**RFout** 

**L4** 

**MN3** 

**MN2** 

**4**

**8**

**Noise Figure (dB)**

**Figure 11.** a) The gain (*S*21) of the LNA varies with *Vbg*. This is measured for *Vbg* = 0.3 V to 0.7 V. b) The noise figure

source transistor *MN*<sup>2</sup> and *MN*<sup>3</sup> are connected in cascode. The transistor *MN*<sup>3</sup> acts in common gate configuration. The width of *MN*<sup>1</sup> is taken to be 1 *µ*m while the width for transistors *MN*<sup>2</sup> and *MN*<sup>3</sup> are kept higher at 2.4 *µ*m for better input return loss and optimized gain performance. The supply, *VDD* is kept constant at 1.2 V. *MN*<sup>3</sup> is biased at 2 V (*Vb*). The

The series peaking circuit consists of an inductive load, *L*2, that allows for low voltage operation and resonates with the inter stage capacitance, *C*1, enabling a higher operating frequency [30]. The inductor *L*<sup>1</sup> is set to resonate with the gate source capacitance of *MN*1. The source degeneration circuit consisting of *L*<sup>3</sup> yields (in real part) wide band impedance matching to maximize the inter-stage power transfer. The inductor *L*<sup>4</sup> tunes out the middle pole of the cascode, thus compensating for the lower *fT* [39] of DG-MOSFET which is nearly

**12**

**16**

**L5** 

**C2** 

The RF mixer is a non-linear electrical circuit that creates two new frequencies from the two signals applied to it. The new frequencies (sum & difference) are called the intermediate frequencies (IF). The sum frequency has its application on the up conversion whereas the difference frequency is used in the down conversion of an input signal. The conversion gain (CG) determines the mixing performance of the circuit [35].

#### *4.2.1. DG-MOSFET mixers and methodology*

DG-MOSFET mixer occupies a special status among analog applications given the compact and high performance nature of an active mixer using only one transistor which saves both power and area compared to conventional CMOS. Accordingly, there are already several literatures available focusing solely on this simple but promising circuit. For instance, a recent work by S. Huang et. al. [43] analyzes the RF Mixer based on the derivative superposition method. An earlier work [44] considers the evaluation of power consumption and area overhead of the DG-MOSFET for RF-mixer applications. W. Zhang et. al. [45] explored the use of multiple independent-gate FinFETs (MIGFETs) application and compares the spectral response of the single-and multiple-transistor (balanced) versions. Although this research provides valuable physical insights regarding the operational principles and behavior of the DG-MOSFET mixer, unfortunately the temporal resolution or the length of the transient data used in their Fast Fourier Transform (FFT) analysis, and the range of device parameters explored, are insufficient for a thorough study of the mixing performance in a methodical manner.

In contrast, in [46] we focus on the structural and operational parameters of DG-MOSFET in a methodical and accurate manner to optimize the biasing for maximum conversion

**Figure 12.** a) DG MOSFET RF Mixer circuit. b) The variation of V*<sup>T</sup>* for the different device parameters L*gate*, N*<sup>d</sup>* and t*Si*.

gain and power efficient design of the mixer circuit. Additionally, we also look into the correlation between conversion gain and the device parameters. In our methodology, we carefully considered the input RF and local oscillator (LO) signals' bias conditions while fairly comparing conversion gain recorded with different structural parameters, ensuring that gate over-drive (LO DC offset) has been kept the same.

The DG-MOSFET RF Mixer circuit (Fig. 12a) explored in [46] consists of a single double gate transistor. For a fair comparison of mixing performance obtained from varying important structural parameters, we first explore the dependence of threshold voltage (*VT*) (Fig. 12b) on each of the device parameters, gate length (*Lg*), doping concentration (*NA*) and body thickness (*tSi*). The source voltage (V*DD*) is kept at the typical value of 1 V and the circuit load, R*L*, is kept at 6 kΩ for the analysis. The sinusoidal RF signal is considered at the frequency *fRF* of 50 MHz while the sinusoidal local oscillator signal is chosen at a frequency *fLO* of 10 MHz so to down convert the incoming frequency to 40 MHz. In this DG MOSFET based architecture, the RF input signal ((*vRF* = (*vr f* + V*RF*) sin(2*π fRF*t)) is applied at one gate while the local oscillator (LO) signal (v*LO* = (*vlo* + *VLO*) sin(2*π fLO*t) is applied at the another gate of the transistor. Here, *vr f* and *vlo* are the AC components of RF and LO signal respectively, while *VRF* and *VLO* are the respective DC bias components. The output signal (*Vout* = A*v*[cos2*π*t(*fRF* - *fLO*) - cos2*π*t(*fRF* + *fLO*)]) consisting of the two intermediate frequencies is observed at the drain of the DG MOSFET and A*<sup>v</sup>* is (*vr f* + *VRF*)(*vlo* + *VLO*)/2. The conversion gain (CG) by definition, then becomes (*vlo* + *VLO*)/2. However, this theoretical linear proportionality of CG on LO amplitude is not valid everywhere and there is a strong dependence on the device geometries and threshold as evident from this analysis, and this necessitates the requirement for bias optimization with quantum corrected simulations.

#### *4.2.2. Non-linearity analysis*

The DG-MOSFET Mixer's multiplicative/non-linear property has been analyzed here from Fig. 12a. The RF signal which is applied at the front gate is represented by small signal model. This is justified because the power level of RF signal is very small on reception at the antenna and remains small even amplified by the LNA. Therefore, the output voltage, *Vout* is given as:

16 Analog Circuits

**VDD** 

**vRF**

**vLO**

that gate over-drive (LO DC offset) has been kept the same.

**Figure 12.** a) DG MOSFET RF Mixer circuit. b) The variation of V*<sup>T</sup>* for the different device parameters L*gate*, N*<sup>d</sup>* and t*Si*.

gain and power efficient design of the mixer circuit. Additionally, we also look into the correlation between conversion gain and the device parameters. In our methodology, we carefully considered the input RF and local oscillator (LO) signals' bias conditions while fairly comparing conversion gain recorded with different structural parameters, ensuring

The DG-MOSFET RF Mixer circuit (Fig. 12a) explored in [46] consists of a single double gate transistor. For a fair comparison of mixing performance obtained from varying important structural parameters, we first explore the dependence of threshold voltage (*VT*) (Fig. 12b) on each of the device parameters, gate length (*Lg*), doping concentration (*NA*) and body thickness (*tSi*). The source voltage (V*DD*) is kept at the typical value of 1 V and the circuit load, R*L*, is kept at 6 kΩ for the analysis. The sinusoidal RF signal is considered at the frequency *fRF* of 50 MHz while the sinusoidal local oscillator signal is chosen at a frequency *fLO* of 10 MHz so to down convert the incoming frequency to 40 MHz. In this DG MOSFET based architecture, the RF input signal ((*vRF* = (*vr f* + V*RF*) sin(2*π fRF*t)) is applied at one gate while the local oscillator (LO) signal (v*LO* = (*vlo* + *VLO*) sin(2*π fLO*t) is applied at the another gate of the transistor. Here, *vr f* and *vlo* are the AC components of RF and LO signal respectively, while *VRF* and *VLO* are the respective DC bias components. The output signal (*Vout* = A*v*[cos2*π*t(*fRF* - *fLO*) - cos2*π*t(*fRF* + *fLO*)]) consisting of the two intermediate frequencies is observed at the drain of the DG MOSFET and A*<sup>v</sup>* is (*vr f* + *VRF*)(*vlo* + *VLO*)/2. The conversion gain (CG) by definition, then becomes (*vlo* + *VLO*)/2. However, this theoretical linear proportionality of CG on LO amplitude is not valid everywhere and there is a strong dependence on the device geometries and threshold as evident from this analysis, and this necessitates the requirement for bias optimization with quantum corrected simulations.

The DG-MOSFET Mixer's multiplicative/non-linear property has been analyzed here from Fig. 12a. The RF signal which is applied at the front gate is represented by small signal model. This is justified because the power level of RF signal is very small on reception at the antenna and remains small even amplified by the LNA. Therefore, the output voltage, *Vout* is

**ID** 

**RL** 

**ID/2 ID/2**

*4.2.2. Non-linearity analysis*

$$V\_{out} = \mathcal{g}\_m \mathcal{v}\_{RF} \mathcal{R}\_L \tag{5}$$

where *gm* is the transconductance of the device at the front gate. The I-V characteristics of DG-MOSFET at saturation is modeled as [47]

$$I\_D = K[(V\_{\mathcal{S}^s} - V\_T)^2 - K'e^{\frac{V\_{\mathcal{S}^s} - V\_0 - V\_{\mathcal{S}^s}}{kT}}] \tag{6}$$

where K & K' are process and device constants and *V*<sup>0</sup> is a second order term of *VT* [47]. Here the drain current at the front gate is modeled by ignoring the exponential term assuming a large *Vds* at saturation, where the numerator at the exponent goes negative.

$$\frac{I\_D}{2} \simeq K(V\_{\mathcal{S}^\text{s}} - V\_T)^2\tag{7}$$

The transconductance at the front gate is,

$$g\_{\mathcal{W}} = \frac{1}{2} \frac{\partial I\_D}{\partial V\_{\mathcal{S}^s}} \tag{8}$$

From eqns. (7) and (8) we can write,

$$\mathbf{g}\_{\mathfrak{m}} = \mathbf{2}K(V\_{\mathfrak{g}^\mathbf{s}} - V\_T) \tag{9}$$

Now from eqns. (7) and (9),

$$\mathbf{g}\_m = \sqrt{\mathbf{(2KI\_D)}}\tag{10}$$

A large signal model is assumed for the back gate as the LO signal is locally generated and usually has high amplitude levels,

$$I\_D/2 = K(v\_{LO} - V\_T)^2\tag{11}$$

implies,

$$I\_D = 2K(v\_{LO} - V\_T)^2 \tag{12}$$

Therefore from eqns. (5), (10) & (12),

$$V\_{\rm out} = K^{\prime\prime} (v\_{LO} - V\_T) v\_{\rm RF} \tag{13}$$

Here *<sup>K</sup>*′′ is a constant which include the process and device parameters and the resistor *RL*. The eqn. (13) analyzes the DG-MOSFET device analysis for non-linear RF Mixer operation. The output voltage is the product of two input voltages. The process dependent parameter *VT* can be eliminated if we consider a balanced/differential mixer mode. However, typically the balanced mode is avoided because in a receiver design the mixer follows the LNA which is generally single ended as it follows a single ended antenna. A balun which consumes a large area is thus required to construct before the mixer for the differential mode use.

#### *4.2.3. Operating point analysis*

After the FFT analysis (Fig. 13a inset) of the output at a very high temporal resolution, we observe significant spectral lines at the two intermediate frequencies of 40 MHz (*fRF fLO*) and 60 MHz (*fRF* + *fLO*) indicating the appropriate double gate mixing performance and non-linearity. The presence of higher harmonics (such as at 100 MHz frequency) in the spectra indicates higher-order non-linearities and must be filtered out to work with the desired frequency. For the analysis purposes and simplification of the observed spectra, the LO signal used in our study is a pure sine-wave with a DC offset providing the operating point for the device, while the RF AC input at the another gate is held constant without a DC offset.

Our study indicates that the CG of the mixer rapidly changes with the amplitude of the LO rising to 200 mV (Fig. 13b), beyond which the increase is limited. Hence, for all *Lgate* values, the operating point of the mixer is chosen to be set around 120 mV for optimum power efficiency and CG. Similar results were also obtained for different *NAs* and *tSis* from corresponding analyses.

The CG is particularly sensitive to the LO DC bias (Fig. 13c) with an 'm-shape' dependence, where the middle dip could be as much as -80 dB. Hence, seemingly there are two bias conditions that provide similar performance in CG of the mixer (Fig. 13b). For instance, these two bias points are observed at 0.3 V and 1 V for *Lgate* = 30 nm and *vlo* = 40 mV. Moreover, this m-shape is a very weak function of LO AC bias and *Lgate*. Data recorded with AC inputs of 40 mV with 120 mV shift mainly vertically with a large lateral similarity in terms of DC bias dependence. Likewise, the peak position shifts roughly 0.1 V only, as the gate length is varied from 90 nm to 30 nm. It is interesting to note that these optimum DC-bias ranges correspond to the least 'linear' sections of the device operation, as can be seen from the transfer characteristics and transconductance (*gm* vs. *Id*) curves in Fig. 13d. The current changes in a very non linear pattern around the optimum bias ranges and the *gm* peak corresponds to the central dip in Fig. 13c. Clearly, the lower bias point (∼ 0.3 V in Fig. 13c) should be preferred because of power efficiency and better stability indicated by the broader plateau. Similar analyses conducted for different *NA* and *tSi* of the DG-MOSFET mixer yield in similar results to our study of *Lgate*. A double-peaked LO-DC behavior persists in all cases. Summarizing results from these simulations, Tables 1, 2 and 3 list the optimum (lower) bias points for different structural parameters studied.

18 Analog Circuits

Therefore from eqns. (5), (10) & (12),

*4.2.3. Operating point analysis*

DC offset.

corresponding analyses.

*Vout* <sup>=</sup> *<sup>K</sup>*′′(*vLO* <sup>−</sup> *VT*)*vRF* (13)

Here *<sup>K</sup>*′′ is a constant which include the process and device parameters and the resistor *RL*. The eqn. (13) analyzes the DG-MOSFET device analysis for non-linear RF Mixer operation. The output voltage is the product of two input voltages. The process dependent parameter *VT* can be eliminated if we consider a balanced/differential mixer mode. However, typically the balanced mode is avoided because in a receiver design the mixer follows the LNA which is generally single ended as it follows a single ended antenna. A balun which consumes a large area is thus required to construct before the mixer for the differential mode use.

After the FFT analysis (Fig. 13a inset) of the output at a very high temporal resolution, we observe significant spectral lines at the two intermediate frequencies of 40 MHz (*fRF fLO*) and 60 MHz (*fRF* + *fLO*) indicating the appropriate double gate mixing performance and non-linearity. The presence of higher harmonics (such as at 100 MHz frequency) in the spectra indicates higher-order non-linearities and must be filtered out to work with the desired frequency. For the analysis purposes and simplification of the observed spectra, the LO signal used in our study is a pure sine-wave with a DC offset providing the operating point for the device, while the RF AC input at the another gate is held constant without a

Our study indicates that the CG of the mixer rapidly changes with the amplitude of the LO rising to 200 mV (Fig. 13b), beyond which the increase is limited. Hence, for all *Lgate* values, the operating point of the mixer is chosen to be set around 120 mV for optimum power efficiency and CG. Similar results were also obtained for different *NAs* and *tSis* from

The CG is particularly sensitive to the LO DC bias (Fig. 13c) with an 'm-shape' dependence, where the middle dip could be as much as -80 dB. Hence, seemingly there are two bias conditions that provide similar performance in CG of the mixer (Fig. 13b). For instance, these two bias points are observed at 0.3 V and 1 V for *Lgate* = 30 nm and *vlo* = 40 mV. Moreover, this m-shape is a very weak function of LO AC bias and *Lgate*. Data recorded with AC inputs of 40 mV with 120 mV shift mainly vertically with a large lateral similarity in terms of DC bias dependence. Likewise, the peak position shifts roughly 0.1 V only, as the gate length is varied from 90 nm to 30 nm. It is interesting to note that these optimum DC-bias ranges correspond to the least 'linear' sections of the device operation, as can be seen from the transfer characteristics and transconductance (*gm* vs. *Id*) curves in Fig. 13d. The current changes in a very non linear pattern around the optimum bias ranges and the *gm* peak corresponds to the central dip in Fig. 13c. Clearly, the lower bias point (∼ 0.3 V in Fig. 13c) should be preferred because of power efficiency and better stability indicated by the broader plateau. Similar analyses conducted for different *NA* and *tSi* of the DG-MOSFET mixer yield in similar results to our study of *Lgate*. A double-peaked LO-DC behavior persists in all cases. Summarizing results from these simulations, Tables 1, 2 and 3 list the optimum

(lower) bias points for different structural parameters studied.

**Figure 13.** a) The FFT (inset) of the voltage at the mixer output (main panel) shows both the sum & difference terms as well as additional higher order harmonics. b) Variation of conversion gain with AC Input for different L*gates*. The CG increases rapidly before 120mV, after which the performance of the conversion gain is limited. c) Variation of CG with DC bias at different L*gate*s. Observation of two AC inputs (120 mV & 40 mV) shows their CG variation with DC bias is similar. d) Transconductance (g*m*) & drain current (I*d*) over DC bias for different L*gate*s. Out of two optimum bias points, the lower one at 0.3 V (30 nm) is chosen for better stability and power efficiency.


**Table 1.** Optimum LO DC bias for different gate lengths at N*<sup>A</sup>* = 10<sup>15</sup> *cm*−<sup>3</sup> & *tSi* = 5 *nm*


**Table 2.** Optimum LO DC bias for different doping concentrations at L*gate* = 45 *nm* & *tSi* = 5 *nm*


**Table 3.** Optimum LO DC bias for different body thicknesses at N*<sup>A</sup>* = 10<sup>15</sup> *cm*−<sup>3</sup> & L*gate* = 90 *nm*

**Figure 14.** a) Dependence of CG on the gate length (*Lgate*) & doping concentration (*NA*) for different AC Inputs. The weak correlation of these two parameters on the CG is clearly evident. b) Dependence of CG on the body thickness (*tSi*) for different AC Inputs. CG varies with L*gate* because of short channel effects.

#### *4.2.4. Structural parameters*

Next, we study the dependence of CGs recorded at the various LO AC amplitudes and at optimum DC (lower peak) bias conditions as a function of most significant structural parameters of the DG-MOSFET used for mixing. The results are summarized in Figs. 14a & 14b, which show the dependence of conversion gain with *Lgate*, *NA* & *tSi*. Clearly, the *Lgate* has almost no impact on the conversion gain at higher values while at lower value the impact becomes more pronounced. For *NA*, the conversion gain almost remains constant at low doping levels whereas it slightly increases at very high (impractical) doping levels. However, from Fig. 14b we find that *tSi* is a more significant parameter for conversion gain optimization. In a given gate length there appears to be an optimum body thickness that maximizes the CG. For example, at *Lgate* of 45 nm and 90 nm, the optimum body thickness is 10 nm and 30 nm, respectively. At either extreme of these values, the conversion gate is compromised due to the short channel effects in the higher end and quantum size effects at the lower end. Thus it is important to include both 2D/3D simulations and quantum corrections to optimize mixing performance in such nano-scale transistors, as with the case in this study.

We like to draw attention that the weak dependence of performance on the structural parameters here is a result of careful bias optimization. It also indicates that the choice of bias conditions, particularly the LO DC bias, is the most dominant handle in using DG-MOSFET active mixer. Admittedly, this observation may be counter intuitive, because the short channel effect are well known to adversely impact analog performance of the conventional MOSFETs in sub-100 nm regime. However, these adverse impacts are mostly related to the increase of the non-linearity in *gm* which is certainly helpful for a mixer. In any case the well-scaled

**Figure 15.** Computation of IP<sup>3</sup> using two tone frequency analysis (0.99 GHz and 1.01 GHz) around 1 GHz. The Intermodulation Ratio (IMR) gives level difference between the fundamental and the IP<sup>3</sup> terms and is used to obtain the IIP<sup>3</sup> = P*in*(f1,f2) + IMR/2.

nature of the DG-MOSFET minimizes the emergence of strong short channel effects for the mixer performance.

Moreover, the apparent stability of mixer performance with device geometrical scaling could affect the phase noise in both positive and negative fashion. In terms of inter-device performance variations, the DG-MOSFETs will not suffer as much as the logic applications as the process variations in geometry does not appear to be a worry. However, since the LO-DC bias is the most important figure of merit, variations in threshold among devices and biasing errors/variations in circuits can be the main source of phase noise and limit the performance.

#### *4.2.5. Linearity analysis*

20 Analog Circuits

**<sup>30</sup> <sup>40</sup> <sup>50</sup> <sup>60</sup> <sup>70</sup> −25**

*4.2.4. Structural parameters*

**40mV 80mV 200mV**

**Gate Length (nm)**

**VAC VAC**

**−20 −15 −10 −5 0 5**

in this study.

**Conversion Gain (dB)**

t*Si* (nm) 5 10 20 30 DC Bias (V) 0.6 0.5 0.4 0.3

**−12**

**−8**

**−4**

**Conversion Gain (dB)**

**Figure 14.** a) Dependence of CG on the gate length (*Lgate*) & doping concentration (*NA*) for different AC Inputs. The weak correlation of these two parameters on the CG is clearly evident. b) Dependence of CG on the body thickness (*tSi*) for different

Next, we study the dependence of CGs recorded at the various LO AC amplitudes and at optimum DC (lower peak) bias conditions as a function of most significant structural parameters of the DG-MOSFET used for mixing. The results are summarized in Figs. 14a & 14b, which show the dependence of conversion gain with *Lgate*, *NA* & *tSi*. Clearly, the *Lgate* has almost no impact on the conversion gain at higher values while at lower value the impact becomes more pronounced. For *NA*, the conversion gain almost remains constant at low doping levels whereas it slightly increases at very high (impractical) doping levels. However, from Fig. 14b we find that *tSi* is a more significant parameter for conversion gain optimization. In a given gate length there appears to be an optimum body thickness that maximizes the CG. For example, at *Lgate* of 45 nm and 90 nm, the optimum body thickness is 10 nm and 30 nm, respectively. At either extreme of these values, the conversion gate is compromised due to the short channel effects in the higher end and quantum size effects at the lower end. Thus it is important to include both 2D/3D simulations and quantum corrections to optimize mixing performance in such nano-scale transistors, as with the case

We like to draw attention that the weak dependence of performance on the structural parameters here is a result of careful bias optimization. It also indicates that the choice of bias conditions, particularly the LO DC bias, is the most dominant handle in using DG-MOSFET active mixer. Admittedly, this observation may be counter intuitive, because the short channel effect are well known to adversely impact analog performance of the conventional MOSFETs in sub-100 nm regime. However, these adverse impacts are mostly related to the increase of the non-linearity in *gm* which is certainly helpful for a mixer. In any case the well-scaled

**0**

**4**

**<sup>0</sup> <sup>10</sup> <sup>20</sup> <sup>30</sup> <sup>40</sup> <sup>50</sup> <sup>60</sup> −16**

(b)

**Body Thickness (nm)**

**80mV(Lgate=45nm) 80mV(Lgate=90nm) 200mV(Lgate=45nm) 200mV(Lgate=90nm)**

**VAC**

**Table 3.** Optimum LO DC bias for different body thicknesses at N*<sup>A</sup>* = 10<sup>15</sup> *cm*−<sup>3</sup> & L*gate* = 90 *nm*

**<sup>1015</sup> <sup>1016</sup> <sup>1017</sup> <sup>1018</sup> −25**

**40mV 80mV 200mV**

**Doping Concentration (cm−3)**

**−20 −15 −10 −5 0 5**

(a)

AC Inputs. CG varies with L*gate* because of short channel effects.

Finally, we examine the circuit for linearity implementing the two tone frequency analysis (Fig. 15). The 3rd order Input Intercept point (IIP3) is found to be 15.9 dBm for 2 dBm LO power, indicating the suitability of the circuit [35].

## **4.3. Envelope detector**

The demodulation of a non-coherent modulated wave requires an envelope detector. The envelope detector is basically a rectifier circuit that generates an envelope of the incoming high frequency carrier signal and strips off the carrier to recover the data.

In Fig. 16a, we have illustrated a 45 nm DG-MOSFET envelope detector circuit in which the output is inverted to that of binary input (Refer Fig. 6). The output signal needs further to be passed through an inverter for the recovery of the original signal. Although requires additional hardware, this circuit has an advantage over the straightforward recovery as the former has a better output swing over the latter [48]. The simulation (Fig. 16b) illustrates the recovered binary input information as same as that is shown in Fig. 6. The high frequency noise present with logic 1 data at the output can be easily filtered out.

#### **4.4. Charge pump Phase Frequency Detector**

The Phase Frequency Detector (PFD) is one of the two major components of a PLL, that is used for the demodulation of coherent modulated signal. The other being the local oscillator/VCO. It consists of two D Flip Flops and a reset circuit. The two D Flip Flops are implemented with eight NOR gates (four each) [49]. The reset path consists of another

**Figure 16.** a) Envelope Detector Circuit with only two DG MOSFETs. b) The modulated input consisting of the both the carrier and data; the recovered demodulated output consisting only of data sans the carrier.

NOR gate. Here, each of the NOR gates are constructed with DG-MOSFETs. The circuit also consists of two DG-MOSFET NMOS switches implemented in regular *VT* configuration (Fig. 17a).

#### *4.4.1. DG-MOSFET NOR gate*

The DG MOSFET NOR gate consists of only two DG transistors instead of four as in conventional CMOS architecture (Fig. 17b). This was first proposed by Chiang et. al [50]. The design employs the threshold-voltage (*VT*) difference between double-gated and single-gated modes in a high *VT* DG device to reduce the number of transistors by half.

The NOR logic with DG-MOSFETS is shown in Fig. 17c. One of the major advantages of using NOR gates using DG-MOSFETs is speed. The area and capacitance of the DG-MOSFET NOR gate is almost 2x less than the conventional CMOS due to reduced transistor count (half that of conventional CMOS) and associated isolation and wirings which lowers the capacitance and speeds up the circuit. In Fig. 17d we demonstrate this fact for different supply voltages. The advantage in higher speed is crucial for tiny phase error detection in PLL and is the subject of the following section.

#### *4.4.2. Design and analysis*

This analysis is carried with a supply of 1 V for (*W*/*L*)*<sup>p</sup>* = 4 *µ*m / 45 nm and (*W*/*L*)*<sup>n</sup>* = 1 *µ*m / 45 nm. The power consumed by the DG-MOSFET based Charge Pump PFD is 3.4 mW which is 21% less than that of the conventional CMOS under identical device dimensions and parameters. Although the drive current (*ION*) for DG-MOSFET is higher for both regular and high *VT* configurations than that of a single gate MOSFET, the reduction in the number of transistor counts, reduces the power consumption decently. The area is also reduced almost by half resulting from this reduction.

The phase error between two pulses A and B can be correctly detected for both conventional CMOS and DG-MOSFET when the phase error between the two pulses (*Tpe*) is above a certain threshold. Now from our analysis at the previous section on speed enhancement of DG-MOSFET based NOR architecture we can deduce the rise time of the DG-MOSFET (*TthDG*) is faster than that for rise time of conventional CMOS (*TthSG*) to reach the desired threshold of logic 'HIGH' and thus we can write *TthDG* < *TthSG*. However, for low phase

22 Analog Circuits

(Fig. 17a).

*4.4.1. DG-MOSFET NOR gate*

subject of the following section.

by half resulting from this reduction.

*4.4.2. Design and analysis*

ഥ**Demod**

and data; the recovered demodulated output consisting only of data sans the carrier.

(a) (b)

**Figure 16.** a) Envelope Detector Circuit with only two DG MOSFETs. b) The modulated input consisting of the both the carrier

NOR gate. Here, each of the NOR gates are constructed with DG-MOSFETs. The circuit also consists of two DG-MOSFET NMOS switches implemented in regular *VT* configuration

The DG MOSFET NOR gate consists of only two DG transistors instead of four as in conventional CMOS architecture (Fig. 17b). This was first proposed by Chiang et. al [50]. The design employs the threshold-voltage (*VT*) difference between double-gated and single-gated

The NOR logic with DG-MOSFETS is shown in Fig. 17c. One of the major advantages of using NOR gates using DG-MOSFETs is speed. The area and capacitance of the DG-MOSFET NOR gate is almost 2x less than the conventional CMOS due to reduced transistor count (half that of conventional CMOS) and associated isolation and wirings which lowers the capacitance and speeds up the circuit. In Fig. 17d we demonstrate this fact for different supply voltages. The advantage in higher speed is crucial for tiny phase error detection in PLL and is the

This analysis is carried with a supply of 1 V for (*W*/*L*)*<sup>p</sup>* = 4 *µ*m / 45 nm and (*W*/*L*)*<sup>n</sup>* = 1 *µ*m / 45 nm. The power consumed by the DG-MOSFET based Charge Pump PFD is 3.4 mW which is 21% less than that of the conventional CMOS under identical device dimensions and parameters. Although the drive current (*ION*) for DG-MOSFET is higher for both regular and high *VT* configurations than that of a single gate MOSFET, the reduction in the number of transistor counts, reduces the power consumption decently. The area is also reduced almost

The phase error between two pulses A and B can be correctly detected for both conventional CMOS and DG-MOSFET when the phase error between the two pulses (*Tpe*) is above a certain threshold. Now from our analysis at the previous section on speed enhancement of DG-MOSFET based NOR architecture we can deduce the rise time of the DG-MOSFET (*TthDG*) is faster than that for rise time of conventional CMOS (*TthSG*) to reach the desired threshold of logic 'HIGH' and thus we can write *TthDG* < *TthSG*. However, for low phase

modes in a high *VT* DG device to reduce the number of transistors by half.

**Vin**

**VDD**

**Figure 17.** a) The Charge Pump PFD circuit implemented with DG-MOSFETs. b) 2-Input NOR Logic Gate in Conventional CMOS and its equivalent in DG-MOSFET. Two transistors are required in the DG-MOSFET. The PMOS in DG-MOSFET is kept at a high-*VT* symbolized by a filled transistor. c) 2-Input DG-MOSFET NOR Logic simulated waveform for *VDD* = 1 V. d) Delay comparison of 2-input NOR gate between conventional CMOS and DG-MOSFET for different supply voltages.

error applications, when *TthDG* ≤ *Tpe* ≤ *TthSG*, the PFD ceases to work correctly for the conventional CMOS. As observed from Fig. 18, for *Tpe* = 80 ps, the voltage at the output *QA* of the flip flop fails to reach the threshold to switch on the transistor *MN*<sup>1</sup> in the period when A is 'HIGH' and B is 'LOW'. The voltage *only* reaches the threshold when both A and B are HIGH. When B is high the voltage at *QB* also reaches 'HIGH' which turns the transistor *MN*<sup>2</sup> 'ON'. Therefore, when both *QA* and *QB* are 'HIGH' (reaches the *VT*) simultaneously, the current *I*<sup>1</sup> instead of charging the capacitor *CP* passes through the switch *MN*2. Thus the output voltage (*Vout*) remains nearly constant and changes only by a fraction of what should be in order to send the accurate message of phase error to the VCO, which follows the PFD in a PLL architecture. As a matter of fact, the *Vout* changes only by a meagre 0.005 mV for 100 ns. This is negligible and an incorrect feedback to the VCO. The *Vout* characteristics is verified from Fig. 19. This is the familiar dead zone condition where there is no or negligible charge pump current that contributes to no change in *Vout*.

**Figure 18.** Phase error characteristics of two pulses A & B for conventional CMOS and DG-MOSFET for a phase error of 80 ps.

**Figure 19.** Charge Pump output voltage characteristics of Conventional CMOS and DG-MOSFET when *TthDG* ≤ *Tpe* ≤ *TthSG*

On the other hand, the advantage of DG-MOSFET is clearly evident from Fig. 18 where it can be confirmed that for the same period the threshold for the DG-MOSFET reaches the logic 'HIGH' when A is 'HIGH' and B is 'LOW'. Thus the current *I*<sup>1</sup> cannot escape through *MN*<sup>2</sup> and charges *CP* instead. This is clearly because even when *Tpe* ≤ *TthSG*, the inequality *Tpe* ≥ *TthDG*, is still valid due to the fact that *TthDG* < *TthSG* owing to the lower capacitance as discussed in the previous section. Thus the dead zone is avoided with the correct and significant change of 0.6 mV in *Vout* for the same duration as that of conventional CMOS (Fig. 19).

#### **5. Summary and future prospects**

The chapter has provided examples for unique and significant performance improvements available via a novel transistor architecture (FinFET or DG-MOSFET) in a wide collection of analog and mixed-signal circuits that can be used in today's integrated wireless communication, satellite navigation systems and sensor networks, verified through industry standard SPICE simulations. In particular, the chapter documents the tunable frequency response in relaxation and LC oscillators along with the gain tuning in wide-band PA and the LNA circuits. In all these cases, the performance improvements and tunable characteristics can be achieved via the availability of independently biased second gates in these new device architectures. In addition to gain tuning, the PA and the LNA performance parameters such as gain, bandwidth, linearity, NF are either comparable or better than some of the recent designs in conventional CMOS or III-V technologies. The fact that DG-MOSFET circuits utilize reduced transistor count compared to single gate CMOS is exemplified by relaxation oscillator, RF Mixer, OOK Modulator, Envelope Detector and Charge Pump PFD circuits. As obvious, the reduced transistor count aids in reducing area and may lower power dissipation. The biasing optimization technique of the RF Mixer described here maximizes the conversion gain of the RF Mixer with power efficiency. The DG-MOSFET Charge Pump PFD circuit avoids dead zone in PLL for low phase difference applications which is not possible in conventional CMOS as demonstrated here. The primary reason for this is reduced delay because of reduced area which in turn is achieved as a result of reduced transistor count.

With fabrication processes of DG-MOSFETs soon coming up with initiation from TSMC and rapidly expanding system-level efforts led by several national and international programs in US, Japan and Europe, along with several companies (such as Intel [4]) and academic centers focussing on these DG-MOSFET/FinFET/3DMOSFET technologies, we should expect a wide range of tunable analog RF circuits, reconfigurable logic blocks, on-chip power management blocks and mixed-signal system-on-chip applications to come into existence in the next few years.

Ultimately, with the ongoing nanotechnology revolution further performance improvements and architectural changes in devices are to be expected in the next decade and beyond. Our work here shows that such changes can be utilized by circuit engineering to result in very compact and capable systems, even when the actual change is to include merely an additional gate in the MOSFET architecture. This indicates that circuit engineering has a lot more to say not only in the final stretch of Moore's scaling, extending perhaps until 2020, but also in post-Moore area where fundamental fabric of building circuits may be altered significantly, and novel devices architectures and materials such as graphene, carbon nanotube, nanowire or molecular transistors are likely to play a significant role.

## **Acknowledgement**

24 Analog Circuits

(Fig. 19).

**0 1 A (V)**

**0 1 B (V)**

**0 1 QA (V)** 

**CMOS**

**DG MOSFET**

**DG MOSFET**

**CMOS**

**0 1 QB (V)**

**0 1 QA (V)** 

> **0 1**

**42.22 42.222 42.224 42.226 42.228 42.23**

> **65.6 65.8 66 66.2**

**Vout (mV) [CMOS]**

**Vout (mV) [DG MOS]**

**5. Summary and future prospects**

**QB (V)** 

**19.4 19.6 19.8 20 20.2 20.4 20.6 20.8**

**TthDG**

**TthSG**

**Tpe**

**Time (ns)**

**Figure 18.** Phase error characteristics of two pulses A & B for conventional CMOS and DG-MOSFET for a phase error of 80 ps.

**<sup>0</sup> <sup>20</sup> <sup>40</sup> <sup>60</sup> <sup>80</sup> <sup>100</sup> 65.4**

**Figure 19.** Charge Pump output voltage characteristics of Conventional CMOS and DG-MOSFET when *TthDG* ≤ *Tpe* ≤ *TthSG*

On the other hand, the advantage of DG-MOSFET is clearly evident from Fig. 18 where it can be confirmed that for the same period the threshold for the DG-MOSFET reaches the logic 'HIGH' when A is 'HIGH' and B is 'LOW'. Thus the current *I*<sup>1</sup> cannot escape through *MN*<sup>2</sup> and charges *CP* instead. This is clearly because even when *Tpe* ≤ *TthSG*, the inequality *Tpe* ≥ *TthDG*, is still valid due to the fact that *TthDG* < *TthSG* owing to the lower capacitance as discussed in the previous section. Thus the dead zone is avoided with the correct and significant change of 0.6 mV in *Vout* for the same duration as that of conventional CMOS

The chapter has provided examples for unique and significant performance improvements available via a novel transistor architecture (FinFET or DG-MOSFET) in a wide collection of analog and mixed-signal circuits that can be used in today's integrated wireless communication, satellite navigation systems and sensor networks, verified through industry

**Time (ns)**

This research was partially supported by the NSF Award ECCS-1129010. We are thankful to the Co-PIs of this award, Prof. Avinash Kodi of Ohio University and Prof. David Matolak of University of South Carolina (formerly of Ohio University) for their support.

## **Author details**

Soumyasanta Laha<sup>⋆</sup> and Savas Kaya

<sup>⋆</sup> Address all correspondence to: sl922608@ohio.edu

School of Electrical Engineering & Computer Science, Ohio University, Athens, OH, USA

#### **References**


[16] J.P Raskin, T.M. Chung, V. Kilchytska, D. Lederer, and D. Flandre. Analog/rf performance of multiple gate SOI devices: wideband simulation and characterization. *IEEE Trans. Electron Devices*, 53:1088–1095, May 2006.

26 Analog Circuits

**References**

2007.

*Physics*, 93:4956–4978, 2003.

479:310–316, Nov 2011.

*Electronics*, 5:1–12, 2009.

*(CICC)*, pages 247–250, 2005.

[1] G. K. Celler and Sorin Cristoloveanu. Frontiers of silicon-on-insulator. *J. of Applied*

[2] Thomas Skotnicki, James A. Hutchby, Tsu-Jae King, H.-S.Philip Wong, and Frederic Boeuf. The end of CMOS scaling. *IEEE Circuits Devices Mag.*, pages 16–26, 2005.

[3] J. Colinge. Multi-gate SOI MOSFETs. *Microelectronic Engineering (Elsevier)*, 84:2071–2076,

[5] Isabelle Ferain, Cynthia A. Colinge, and Jean-Pierre Colinge. Multigate transistors as the future of classical metal-oxide-semiconductor field-effect transistors. *Nature*,

[6] K. Roy, H. Mahmoodi, S. Mukhopadhyay, H. Ananthan, A. Bansal, and T. Cakici. Double-gate SOI Devices for Low-Power and High-Performance Applications. In

[7] Jae-Joon Kim and K. Roy. Double Gate-MOSFET Subthreshold Circuit for Ultralow

[9] S. Kaya, H.F.A Hamed, and S. Laha. *Tunable Analog and Reconfigurable Digital Circuits with Nanoscale DG-MOSFETs*, chapter 9. INTECH, Rijeka, Croatia, Feb 2011.

[10] S. A. Tawfik and V. Kursun. Robust finFET memory circuits with P-Type data access Transistors for higher Integration Density and Reduced Leakage Power. *J. of Low Power*

[11] Meishoku Masahara et. al. Optimum Gate workfunction for Vth-Controllable Four-Terminal-driven double-gate MOSFETs (4t-XMOSFETs)-band-edge Workfunction

[12] Hanpei Koike and Toshihiro Sekigawa. XDXMOS: A novel technique for the Double-Gate MOSFETs Logic Circuits. In *IEEE Custom Integrated Circuits Conference*

[13] Kazuhiko Endo et. al. Four-Terminal FinFETs fabricated using an etch-back gate

[14] D. Wilson, R. Hayhurst, A. Oblea, S. Parke, and D. Hackler. Flexfet: Independently-double-gated SOI Transistor with Variable vt and 0.5v operation achieving near ideal subthreshold slope. In *IEEE Intl. SOI Conf.*, pages 147–148, 2007.

[15] K. Modzelewski, R. Chintala, H. Moolamalla, S. Parke, and D.Hackler. Design of a 32nm Independently-Double-Gated flexFET SOI Transistor. In *IEEE University/Government/Industry Micro/Nano Symposium (UGIM)*, pages 64 – 67, 2008.

versus Midgap Workfunction. *IEEE Trans. Nanotechnol.*, 5:716–722, Nov 2006.

[4] K. Ahmed and K. Schuegraf. Transistor Wars. *IEEE Spectr.*, page 50, Nov 2011.

*IEEE/ACM Int. Conf. on CAD*, pages 217 – 224, Nov 2005.

separation. *IEEE Trans. Nanotechnol.*, 6:201–205, Mar 2007.

Power Applications. *IEEE Trans. Electron Devices*, 51:1468–1474, 2004.

[8] A. Amara and O. Rozeau (Eds.). *Planar Double-Gate Transistor*. Springer, 2009.


[45] W. Zhang, J.G. Fossum, L. Mathew, and Y. Du. Physical Insights Regarding Design and Performance of Independent-Gate FinFETs. *IEEE Trans. Electron Devices*, 52:2198–2206, 2005.

28 Analog Circuits

[31] F. Xiong. *Digital Modulation Techniques*. Artech House, Boston, 2006.

*J. Solid-State Circuits*, 33:179–194, Feb 1998.

*and Systems (ICWITS) (Accepted to appear)*, 2012.

Press, Cambridge, UK, 2004.

*(WAMICON)*, pages 1–4, 2012.

*Symposium*, pages 4–7, 2006.

pages 1040 – 1043, 2000.

*(ASQED)*, page 361, 2010.

– 492, 2010.

*Wireless Compon. Lett.*, 20:43–45, Jan 2010.

[32] A. Hajimiri and T.H. Lee. A general theory of phase noise in electrical oscillators. *IEEE*

[33] Guansheng Li and Ehsan Afshari. A Low-Phase-Noise Multi-Phase Oscillator Based on

[34] S. Laha, S. Kaya, A. Kodi, and D. Matolak. 60 GHz OOK Transmitter in 32 nm DG FinFET Technology. In *IEEE International Conference on Wireless Information Technology*

[35] T.H. Lee. *The Design of CMOS Radio-Frequency Integrated Circuits*. Cambridge University

[36] S. Laha, S. Kaya, A. Kodi, and D. Matolak. Double Gate MOSFET based Efficient Wideband Tunable Power Amplifiers. In *IEEE Wireless and Microwave Conference*

[37] Pin-Cheng Huang, Kun-You Lin, and Huei Wang. A 4-17 GHz Darlington Cascode Broadband Medium Power Amplifier in 0.18 micron CMOS Technology. *IEEE Microw.*

[38] Terry Yao, Michael Gordon, Kenneth Yau, M.T. Yang, and Sorin P. Voinigescu. 60-GHz PA and LNA in 90-nm RF-CMOS. In *IEEE Radio Frequency Integrated Circuits (RFIC)*

[39] Wong-Sun Kim, Xiaopeng Li, and M. Ismail. A 2.4 GHz CMOS low noise amplifier using an inter-stage matching inductor. In *IEEE Midwest Symposium on Circuits and Systems*,

[40] Michael Gordon, Terry Yao, and Sorin P. Voinigescu. 65-GHz Receiver in SiGe BiCMOS using Monolithic Inductors and Transformers. In *IEEE Topical Meeting on Silicon*

[41] Chi-Chen Chen, Yo-Sheng Lin, Pen-Li Huang, Jin-Fa Chang, and Shey-Shi Lu. A 4.9-dB NF 53.5-62 GHz micro-machined CMOS Wideband LNA with Small Group-Delay-Variation. In *IEEE International Microwave Symposium Digest*, pages 489

[42] S. Pellarano, Y. Palaskas, and K. Soumyanath. A 64 GHz LNA with 15.5 dB Gain and 6.5 dB NF in 90 nm CMOS. *IEEE J. Solid-State Circuits*, 43:1542–1552, Jul 2008.

[43] Shuai Huang, Xinnan Lin, Yiqun Wei, and Jin He. Derivative Superposition method for DG MOSFET application to RF mixer. In *Asia Symposium on Quality Electronic Design*

[44] M. V. R Reddy, D. K. Sharma, M. B. Patil, and V. R. Rao. Power-Area Evaluation of Various Double-Gate RF Mixer Topologies. *IEEE Electron Device Lett.*, 26:664–666, 2005.

*Monolithic Integrated Circuits on RF Systems Digest*, pages 1–4, 2006.

Left-Handed LC-Ring. *IEEE J. Solid-State Circuits*, 45:1822–1833, Sep 2010.


**Section 2**
