**4. An example of a CMOS low power potentiostat amplifier**

process [18]. This appears to be simple, but there are several problems in the implementation. First of all, it is very difficult to generate a fast step function and a very fast potentiostat capable of driving this step on the electrodes and extracting the resulting current signal. If the poten‐ tiostat rising time is too slow, the resulting frequency components will be distorted. Since the important information is contained in a short period of time after the step is applied, in addition to a very fast potentiostat, very fast ADC with a high precision bit resolution is also required

A simpler solution is based on the FRA approach. In this case a sine and cosine signals are adopted and by means of two multipliers and a filter stage the real and imaginary components of the response are obtained. This measurement must be done for each frequency. Working with just one sensor and in terms of the size of the final product, the FFT option could be adopted, although high speed hardware and heavy algorithm implementation is required, because the response for several frequencies is obtained. The FRA solution is more oriented to multi-sensor approaches but is also a good option in the case of single sensors, in terms of the trade-off between complexity and speed, if not too low frequencies are to be measured.

This lock-in approach is more feasible. The digital lock-in FRA approach [19] is based on the principle that there is no correlation between noise and measured signal. In contrast to the analogue approach, an orthogonal arithmetic multiplying between the incoming potentiostat signal and reference signal are used to get the real and imaginary components, coming close to the theoretical behavior of a lock-in amplifier depicted in section 3.2. A digital lock-in has no low frequency limitations, being capable of working properly at the sub-hertz region. The upper frequency limitation is mainly limited by the ADC conversion time, being able to develop a wide frequency range EIS system. On the other hand, the digital lock-in is limited by area and power consumption. The area and power consumption levels depend on the electronics involved. If a microprocessor is needed, we get typical power consumption, for commercial solutions, of several hundreds of mW, which is far from the desired power waste. But in the recent years a step forward in microprocessors field has been presented in [54] and [55]. [54] Present a microprocessor, in a 180 nm technology, with a power consumption of 226

is explored. In the same way there has been an evolution in microprocessor development, in terms of area and power consumption. [19] Present an evolution of the digital lock-in algorithm

. It evolved from [55], where the sub-threshold operating region

**Figure 18.** Digital lock-in block diagram.

262 State of the Art in Biosensors - General Aspects

nW, and area of 915x915 mm2

In this section the design of a CMOS low power potentiostat amplifier using a 0.13µm technology is described. Potentiostat architecture [2,6,56,57], using the described electrochem‐ ical model, is depicted in Figure 19.

This structure is based on four amplifiers (Opamp) and two resistors. OP4 is the transimpe‐ dance amplifier, which defines the virtual ground voltage of the WE electrode, and provides current-to-voltage conversion such that,

$$\cdot V\_{out,POT} = -\; I\_{CELL} \cdot R\_{TIA} \tag{35}$$

where ICELL is the current through the cell and RTIA the gain defined on the transimpedance amplifier.

OP3 is used to ensure minimal current flow through the RE electrode. It senses the voltage difference between the RE and WE electrodes (virtual ground). This difference is compared by OP2 with the desired VIN voltage, changing the voltage at the AUX electrode and defining a current through the cell in such a way that the voltage difference between the RE and WE electrodes follows the defined VIN DC+AC signal that polarizes the sensitive cell.

**Figure 19.** Full schematic view of the potentiostat amplifier with the adopted electrochemical electrical model [58].

If WE electrode is attached at a virtual ground by the transimpedance amplifier, it can be demonstrated that the Zcell impedance, and variations, could be detected continuously by:

$$\mathbf{V}\_{\rm out, POT} = \frac{\mathbf{R}\_{\rm TA}}{\mathbf{Z}\_{\rm CLL}} \left( \mathbf{V}\_{\rm ref} \, ^\circ \mathbf{V}\_{\rm work} \right) = \frac{\mathbf{R}\_{\rm TA}}{\mathbf{Z}\_{\rm CLL}} \mathbf{V}\_{\rm IN} \tag{36}$$

$$\mathbf{Z\_{CELL}} \text{(j\omega)} = \frac{\mathbf{V\_{IN}}}{\nabla\_{\text{out,POT}}} \text{ R}\_{\text{TIA}} \tag{37}$$

The amplifier adopted to design the potentiostat amplifier is based on a wide-swing, cascode output stage with feedforward class-AB control, Figure 20 and Figure 21, [58-60] for OP1, OP2 and OP3 amplifiers and a full-custom, multi-stage, high input impedance, cascode output stage for transimpedance amplifier OP4. The AB amplifiers (OP1, OP2 and OP3) output transistors have been sized in such a way they can supply the right current for the worst load conditions, defined by the electrochemical model, which has a total value of several MΩ. The input stage of the transimpedance amplifier (OP4) has been designed to increase by three orders of magnitude, the input impedance, minimizing offset and current losses at WE electrode. The power supply is 1.2 V for all the electronics.

**Figure 20.** Full schematic view of the AB amplifier [58].

Individual amplifier AB (OP1, OP2 and OP3) is 440µm in height and 500µm in width, with 84 µW of power consumption in nominal conditions (10MΩ@10pF), 108 dB open-loop gain at low frequencies, 300 kHz bandwidth with a PM = 59º and 12 µV of input systematic offset. In Table

**Figure 21.** Full layout view of the AB amplifier [58].

If WE electrode is attached at a virtual ground by the transimpedance amplifier, it can be demonstrated that the Zcell impedance, and variations, could be detected continuously by:

ZCELL (Vref-Vwork) <sup>=</sup> RTIA

The amplifier adopted to design the potentiostat amplifier is based on a wide-swing, cascode output stage with feedforward class-AB control, Figure 20 and Figure 21, [58-60] for OP1, OP2 and OP3 amplifiers and a full-custom, multi-stage, high input impedance, cascode output stage for transimpedance amplifier OP4. The AB amplifiers (OP1, OP2 and OP3) output transistors have been sized in such a way they can supply the right current for the worst load conditions, defined by the electrochemical model, which has a total value of several MΩ. The input stage of the transimpedance amplifier (OP4) has been designed to increase by three orders of magnitude, the input impedance, minimizing offset and current losses at WE electrode. The

Individual amplifier AB (OP1, OP2 and OP3) is 440µm in height and 500µm in width, with 84 µW of power consumption in nominal conditions (10MΩ@10pF), 108 dB open-loop gain at low frequencies, 300 kHz bandwidth with a PM = 59º and 12 µV of input systematic offset. In Table

ZCELL(jω)= VIN

ZCELL VIN (36)

Vout,POT RTIA (37)

Vout,POT <sup>=</sup> RTIA

power supply is 1.2 V for all the electronics.

264 State of the Art in Biosensors - General Aspects

**Figure 20.** Full schematic view of the AB amplifier [58].

1 different results are summarized, based on the typical (TYP), fast (FFA) and slow (SSA) mobility values of the electrical carriers, and for different simulation conditions, are reported.


**Table 1.** Folded Cascode AB amplifier characterization @ ± 0.6Vsupply

.

Transimpedance amplifier (OP4) is 500µm in height and 1000µm in width, with 61 µW power consumption in nominal conditions(10MΩ@10pF), 85 dB open-loop gain at low frequencies, 400 kHz bandwidth with a PM = 67º and 26 µV input systematic offset.

Taking account of an extremely low offset requirement for bio-implantable devices, this low offset performance is due to an accurate channel length modulation of transistors size at the differential pairs, applying careful techniques for the analogue layout [61]. The linear range of the potentiostat amplifier has been analysed by simulations and it is expected to be 80% of the supply range. As an example; considering a ±100mV full scale voltage, in the ±75mV range the linearity response is quite good, with a deviation error of less than 0.01% [6], as is depicted in Figure 22. The potentiostat amplifier is 1400µm in height and 1000µm in width, with a power consumption of 400µW@|VDD-VSS|=1.2V.

The full system has been analyzed based on the extracted views of the design. The ranges of the electrochemical parameters are good enough for the targets of the electrochemical cells. Initial simulations of this approach are presented, with positive results in terms of the potentiostat amplifier and lock-in amplifier response. The potentiostat assures a good linearity, and also ensures that the electrochemical cell follows the input voltage VIN as expected. Current losses on the TIA amplifier stage are totally negligible and enclosed.

**Figure 22.** These signals are the derived functions, where A is the input signal (VIN) and C the polarization signal (VCELL).

#### **5. Summary and conclusions**

In this chapter, we have introduced the basic principles of biosensors and bioelectronics interfaces specially focused on the design of instrumentation related to amperometrics biosensors, potentiostat amplifiers and lock-in amplifiers. These elements have been intro‐ duced with regard to the state-of-the-art and the trends involved in such systems, and the development of custom built electronic solutions for bio-electronics applications, from discrete devices to ASICS solutions.

Discrete systems are useful for implementation in portable point-of-care applications. As we get less area and power restrictions than an ASIC solution, there are several architectures for data acquisition, processing and transmission. Potentiostat amplifiers can be designed with discrete devices or a monolithic ASIC solution while the lock-in amplifier can be designed with discrete devices or monolithic ASIC for an analogue approach, or an external commercial microcontroller or DSP for a digital approach. We must choose our fit depending on portability, accuracy and reliability requirements.

However, for body sensor networks body or implantable devices development, the increased functionality, reduced systems, with smaller multiplexed electrodes, for ultra-low current detection and versatility will require potentiostat amplifiers to be designed on a system-onchip (SoC), which will force us to implement the system in CMOS technology.

As stated by [62] a trade-off between versatility and power consumption, aggressive digital processing and analogue data processing or general purpose and custom design, must be considered when developing such systems that integrates medical and electronic technologies. These trade-offs have been presented on this chapter split in two different sections, related to the potentiostat amplifier and to the lock-in amplifier. Finally, an example of CMOS low power potentiostat amplifier has been reported.


**Table 2.** Summary table section 3.1.

.

(VCELL).

**5. Summary and conclusions**

Transimpedance amplifier (OP4) is 500µm in height and 1000µm in width, with 61 µW power consumption in nominal conditions(10MΩ@10pF), 85 dB open-loop gain at low frequencies,

Taking account of an extremely low offset requirement for bio-implantable devices, this low offset performance is due to an accurate channel length modulation of transistors size at the differential pairs, applying careful techniques for the analogue layout [61]. The linear range of the potentiostat amplifier has been analysed by simulations and it is expected to be 80% of the supply range. As an example; considering a ±100mV full scale voltage, in the ±75mV range the linearity response is quite good, with a deviation error of less than 0.01% [6], as is depicted in Figure 22. The potentiostat amplifier is 1400µm in height and 1000µm in width, with a power

The full system has been analyzed based on the extracted views of the design. The ranges of the electrochemical parameters are good enough for the targets of the electrochemical cells. Initial simulations of this approach are presented, with positive results in terms of the potentiostat amplifier and lock-in amplifier response. The potentiostat assures a good linearity, and also ensures that the electrochemical cell follows the input voltage VIN as expected. Current

**Figure 22.** These signals are the derived functions, where A is the input signal (VIN) and C the polarization signal

In this chapter, we have introduced the basic principles of biosensors and bioelectronics interfaces specially focused on the design of instrumentation related to amperometrics

400 kHz bandwidth with a PM = 67º and 26 µV input systematic offset.

losses on the TIA amplifier stage are totally negligible and enclosed.

consumption of 400µW@|VDD-VSS|=1.2V.

266 State of the Art in Biosensors - General Aspects

In section 3.1, different potentiostat amplifier topologies have been reported. Different approaches to develop a potentiostat amplifier were introduced, taking account of on every particular situation the pros and contras. Table 2. Choosing the best fit analogue instrumen‐ tation has repercussions on several benefits in terms of area and power consumption, and is the first step to a solid efficient design. Exploiting the analogue processing before digitization is the optimal way to develop these systems, regarding all the benefits described.

In section 3.2 the lock-in amplifier is shown with two different approaches, the analogue approach and the digital approach. Table 3.

The analogue lock-in amplifier provides several advantages in terms of post-processing requirement as the digitization of the output data, being a DC signal, is easier than in other kinds of devices, decreasing considerably the complexity of the post-processing and data transmission electronics. On the other hand, this analogue approach has some limitations in terms of versatility and bandwidth, which is limited by the whole lock-in electronics. Assum‐ ing the implementation of a CMOS monolithic solution for a whole implantable device, versatility and bandwidth limitations can be acceptable in terms of an efficient custom system.

The digital approach of a lock-in amplifier allows us to develop a very versatile and powerful device. The bandwidth of this system is only limited by the analogue to digital converter and data transmission electronics if needed. The digital lock-in approach being a whole mathe‐ matical embedded system can be implemented in different processing topologies, such as real time processing by means of a FPGA (Field Programmable Gate Array), or standard processing by means of a DSP or microprocessor. A digital lock-in has no low frequency limitations, being able to work effectively at the sub-hertz region. The upper frequency limitation is mainly limited by the ADC conversion time, being capable of developing a wide frequency range EIS system.


**Table 3.** Summary table section 3.2.

We must keep in mind the large area and power increase represented by a microprocessor, DSP or FPGA, which can make this lock-in approach not suitable for low power consumption electronics or implantable devices. However, as it has been reported in section 3.2.2, advances in DSP area and power requirements and advances in digital lock-in algorithms have made the possibility of a digital lock-in implementation on a low-power system-on-a-chip CMOS implantable device feasible.
