**Acknowledgements**

This study is based on work conducted with Mr. Hiroo Anan, Dr. Yusmeeraz Binti Yusof, and Dr. Shigeyasu Uno of Nagoya in collaboration with Dr. Masao Kamahori and Mr. Yu Ishige at the Central Research Laboratory, Hitachi, Japan. This research was financially sup‐ ported by a Grant-in-Aid for Scientific Research (No. 20226009) from the Ministry of Educa‐ tion, Culture, Sports, Science and Technology of Japan. The fabrication of CMOS chips is supported by ON Semiconductor Technology Japan Ltd. (1.2 µm process) and TSMC (0.6 µm process), and the VLSI Design and Education Center (VDEC), University of Tokyo in collaboration with Synopsys, Inc. and Cadence Design Systems, Inc.
