**Author details**

In section 3.1, different potentiostat amplifier topologies have been reported. Different approaches to develop a potentiostat amplifier were introduced, taking account of on every particular situation the pros and contras. Table 2. Choosing the best fit analogue instrumen‐ tation has repercussions on several benefits in terms of area and power consumption, and is the first step to a solid efficient design. Exploiting the analogue processing before digitization

In section 3.2 the lock-in amplifier is shown with two different approaches, the analogue

The analogue lock-in amplifier provides several advantages in terms of post-processing requirement as the digitization of the output data, being a DC signal, is easier than in other kinds of devices, decreasing considerably the complexity of the post-processing and data transmission electronics. On the other hand, this analogue approach has some limitations in terms of versatility and bandwidth, which is limited by the whole lock-in electronics. Assum‐ ing the implementation of a CMOS monolithic solution for a whole implantable device, versatility and bandwidth limitations can be acceptable in terms of an efficient custom system.

The digital approach of a lock-in amplifier allows us to develop a very versatile and powerful device. The bandwidth of this system is only limited by the analogue to digital converter and data transmission electronics if needed. The digital lock-in approach being a whole mathe‐ matical embedded system can be implemented in different processing topologies, such as real time processing by means of a FPGA (Field Programmable Gate Array), or standard processing by means of a DSP or microprocessor. A digital lock-in has no low frequency limitations, being able to work effectively at the sub-hertz region. The upper frequency limitation is mainly limited by the ADC conversion time, being capable of developing a wide frequency range EIS




**Structure Topology Advantages Disadvantages**



We must keep in mind the large area and power increase represented by a microprocessor, DSP or FPGA, which can make this lock-in approach not suitable for low power consumption electronics or implantable devices. However, as it has been reported in section 3.2.2, advances in DSP area and power requirements and advances in digital lock-in algorithms have made the possibility of a digital lock-in implementation on a low-power system-on-a-chip CMOS

Analog lock-in. Section 3.2.1. - Simplest analog output signal A/D conversion.


operation.

is the optimal way to develop these systems, regarding all the benefits described.

approach and the digital approach. Table 3.

268 State of the Art in Biosensors - General Aspects

system.

Digital lock-in. Section 3.2.2.

**Table 3.** Summary table section 3.2.

implantable device feasible.

Jaime Punter Villagrasa\* , Jordi Colomer-Farrarons and Pere Ll. Miribel

\*Address all correspondence to: jpunter@el.ub.edu

Department of Electronics, Bioelectronics and Nanobioengineering Research Group (SIC-BIO), University of Barcelona, Spain
