**2. Proposed Buffering System**

#### **2.1. Architecture of the Buffering System**

The proposed buffering system consists of *N* parallel buffering modules and a combiner as shown in Fig.1. Each module can manage the buffering in autonomous fashion by ex‐ changing the information signals that include utilization of output port as indicated by dashed lines. Packets forwarded by the buffering modules are transmitted to output port through an *N*×1 combiner.

**Figure 1.** Schematic diagram of proposed buffering system.

The structure of a buffering module is also shown in inset of Fig. 1. It consists of a bit ex‐ tractor, a controller, and an FDL buffer. The bit extractor creates trigger signal by detect‐ ing the first bit and the last bit of incoming packets. The first and last bits can be composed of specific coded bit patterns. Optical code-correlation processing can find the start and the end of the packet as the first and the last bits, respectively. The controller generates control signal autonomously by using the trigger signal. The FDL buffer stores and forwards packets by using the control signal.

### **2.2. Configuration of the Controller**

We have proposed an autonomous first-in-first-out (FIFO) buffer management system us‐ ing all-optical sensing of packets [13]. Each of FDLs in the reported system stores a single packet. In this chapter, we describe architecture and operation of the buffering system. The buffering performances such as packet loss rate (PLR) and delay time are evaluated

The proposed buffering system consists of *N* parallel buffering modules and a combiner as shown in Fig.1. Each module can manage the buffering in autonomous fashion by ex‐ changing the information signals that include utilization of output port as indicated by dashed lines. Packets forwarded by the buffering modules are transmitted to output port

Buffering module

*From others To others*

*Buffering information*

Buffering module

*N* x 1 combiner Output

Buffering module

Controller

The structure of a buffering module is also shown in inset of Fig. 1. It consists of a bit ex‐ tractor, a controller, and an FDL buffer. The bit extractor creates trigger signal by detect‐ ing the first bit and the last bit of incoming packets. The first and last bits can be composed of specific coded bit patterns. Optical code-correlation processing can find the start and the end of the packet as the first and the last bits, respectively. The controller generates control signal autonomously by using the trigger signal. The FDL buffer stores

*From others To others*

Trigger signal (First bit / Last bit)

Bit extractor

FDL buffer

Control signal

by numerical simulation.

through an *N*×1 combiner.

**2. Proposed Buffering System**

376 Optoelectronics - Advanced Materials and Devices

Input 1

*Packet*

**Figure 1.** Schematic diagram of proposed buffering system.

and forwards packets by using the control signal.

2

*N*

**2.1. Architecture of the Buffering System**

Figure 2 shows the schematic diagram of the controller composed of four components. Con‐ troller A creates timing clock C1 to be used to open the buffer for storing packets. Controller B creates 'store' signal which indicates the actually storing FDL in the buffer. Controller C creates another timing clock C2 to be used to forward the already stored packets. Controller D creates 'forward' signal and the buffering information to other modules which indicates whether the buffer is now forwarding packets or not.

Figure 3 shows the configuration of controller A. Timing clock C1 corresponds to the extract‐ ed first bit of incoming packets. The extracted last bit is not used in this case. However, it is reserved for future enhancement of the buffering system.

**Figure 2.** Schematic diagram of the controller.

**Figure 3.** Configuration of controller A.

Figure 4 shows the configuration of controller B. It autonomously generates 'store' signals by processing C1 and C2. The number of 'store' signals is *M*+1 where *M* corresponds to the number of FDLs in the buffer. In order to indicate actual storing position, none or only one of the 'store' signals becomes on-state. When C1 comes, position of on-state moves up from #1 to #(*M*+1), namely, initially all off-state turns to #1-on, then moves to #2-on, #3-on, and so on. On the contrary, when C2 comes, position of on-state moves down from #(*M*+1) to #1. There are some delay lines with delay time of *T* FIFO-*T* 1 and *T* 1, where *T* FIFO and *T* 1 are delay of single FDL in the buffer and 1-bit, respectively. Note that these components are expressed by some sort of logic circuits. Although it depends on the function and the performance such as operating speed, power consumption, and footprint, both electrical and optical logic circuits might be candidates to be employed.

Figure 5 shows the configuration of controller C. It autonomously generates C2 by process‐ ing C1, 'store' signal, buffering information signals from other modules, and 'forward' signal mentioned below. The operation of controller C is similar to the FDL buffer for packets. Therefore, we describe the detailed operation in the latter section about FDL buffer.

Figure 6 shows the configuration of controller D. It autonomously generates 'forward' signal by processing C2. The 'forward' signal keeps on-state for a period of *T* FIFO by using the flipflop triggered by C2.

Input

**Figure 5.** Configuration of controller C.

**Figure 6.** Configuration of Controller D.

**2.3. Configuration of the FDL Buffer**

than or equal to the maximum packet length.

C1

*T*FIFO

'Store' signal

'Forward' signal

*Buffering Information From others* 1x2 switch #*M*

FDL #1

FDL #2

On

Off

Off

On

On

#1 #2 #*M* #*M*+1 Off

1x2 switch #2

1 x (*M*+1) switch

1x2 switch #1 Coupler #1

Flip-flop

Q

Q

*Buffering Information To others*

S

C2 'Forward' signal

R

The FIFO buffer consists of *M* parallel FDLs that have delay time of *T* FIFO, a 1×(*M*+1) input switch, *M*1×2 output switches and couplers as shown in Fig. 7. The buffer stores and for‐ wards packets by using 'store' and 'forward' signals, respectively. The stored position is de‐ termined by the state of 'store' signal. Namely, when *k-*th signal is on-state (*k*=1,..,*M*), incoming packets are switched to *k*-th FDL by the input switch. In case that (*M*+1)-th signal is on-state, then incoming packets will be discarded because all of the FDLs have already been occupied with other packets. The stored packets are forwarded to output by control‐ ling the output switches. When the 'forward' signal is incident, all of the output switches move the stored packets to next neighbor FDLs. Note that *T* FIFO is designed to be greater

FDL #*M*

*T*FIFO

*T*FIFO

All-Optical Autonomous First-in–First-out Buffer Managed with Carrier Sensing of Output Packets

Discard

Coupler #2

C2

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379

Coupler #*M*

*T*FIFO

**Figure 4.** Configuration of controller B.

**Figure 5.** Configuration of controller C.

on. On the contrary, when C2 comes, position of on-state moves down from #(*M*+1) to #1. There are some delay lines with delay time of *T* FIFO-*T* 1 and *T* 1, where *T* FIFO and *T* 1 are delay of single FDL in the buffer and 1-bit, respectively. Note that these components are expressed by some sort of logic circuits. Although it depends on the function and the performance such as operating speed, power consumption, and footprint, both electrical and optical logic

Figure 5 shows the configuration of controller C. It autonomously generates C2 by process‐ ing C1, 'store' signal, buffering information signals from other modules, and 'forward' signal mentioned below. The operation of controller C is similar to the FDL buffer for packets.

Figure 6 shows the configuration of controller D. It autonomously generates 'forward' signal by processing C2. The 'forward' signal keeps on-state for a period of *T* FIFO by using the flip-

*T*FIFO-*T*<sup>1</sup>

'Q' from flip-flop #(*M*-1) 'Q' from flip-flop #2

Flip-flop #(*M*+1)

Flip-flop #*M*

Flip-flop #1

Flip-flop #0

Q

Q

*T*1

*T*1

<sup>Q</sup> *<sup>T</sup>*<sup>1</sup>

<sup>Q</sup> *<sup>T</sup>*<sup>1</sup>

Q

'Store' signal #(*M*+1)

#*M*

#1

Q

*T*1

Q

<sup>Q</sup> *<sup>T</sup>*<sup>1</sup>

S

R

S

R

S

R

S

R

Therefore, we describe the detailed operation in the latter section about FDL buffer.

circuits might be candidates to be employed.

378 Optoelectronics - Advanced Materials and Devices

flop triggered by C2.

C1

C2

**Figure 4.** Configuration of controller B.

**Figure 6.** Configuration of Controller D.

#### **2.3. Configuration of the FDL Buffer**

The FIFO buffer consists of *M* parallel FDLs that have delay time of *T* FIFO, a 1×(*M*+1) input switch, *M*1×2 output switches and couplers as shown in Fig. 7. The buffer stores and for‐ wards packets by using 'store' and 'forward' signals, respectively. The stored position is de‐ termined by the state of 'store' signal. Namely, when *k-*th signal is on-state (*k*=1,..,*M*), incoming packets are switched to *k*-th FDL by the input switch. In case that (*M*+1)-th signal is on-state, then incoming packets will be discarded because all of the FDLs have already been occupied with other packets. The stored packets are forwarded to output by control‐ ling the output switches. When the 'forward' signal is incident, all of the output switches move the stored packets to next neighbor FDLs. Note that *T* FIFO is designed to be greater than or equal to the maximum packet length.

We assume that there are initially no packets stored in the FDLs, and then five packets are arriving sequentially with random timing and variable lengths. The number of FDLs *M* is

All-Optical Autonomous First-in–First-out Buffer Managed with Carrier Sensing of Output Packets

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When packet no.1 is incident, 'store' signal #1 turns on triggered by the first bit and C1. The state of the 'store' signal is kept for a period of *T* FIFO. When *T* FIFO is expired, 'forward' signal turns on triggered by the C2. Then, stored packets no.1 is forwarded to output. If another module has already been open for forwarding, the 'forward' signal of this module does not turn on in order to avoid collision between this module and the forwarding module. When packet no.3 is incident before the expiration period *T* FIFO of packet no.2, it is stored into an‐

Although similar operation can be seen for following packets, packet no.5 is slightly differ‐ ent. The front part of it is discarded because all FDLs have already been occupied by other packets. When packet no.3 is forwarded, FDL #2 is open for storing. At the moment, the rear part of packet no.5 is stored into there. Note that the packet no.5 is therefore treated as a

Two kinds of characteristics such as packet loss rate (PLR) and average delay time are inves‐ tigated by computer simulation. We assume in the simulation that packets arrive randomly and have variable lengths from *L* min=10 to *L* max=150 bytes. We define load at input port by the ratio of the packet existence length to a unit length. For simplicity, operation speed of the composed devices, such as switching speed of some spatial switches and flip-flops, rise time of logic gates, are assumed to be much faster than bit-rate of arriving packets. There‐

The PLR is verified with changing the number of FDLs *M*, length of each FDL *L*, number of input *N*, and the load. Because of a finite number of FDLs in the buffer system, overflow may occur when the load exceeds the capacity of the buffer, resulting in rejection of the overflowed packets. Even if the load is less than the capacity, collision of packets may occur when packets forwarded by some modules are simultaneously coming into the following combiner as shown in Fig.1. Therefore in the simulation, the overflow and the collision are

Figure 9 shows the PLR as a function of the load at module #1 with the number of FDLs *M* as a parameter. The number of modules is *N*=2. The load of the module #2 is set to 0.5. The length of each FDL is *L*=*L* max. It is found that the PLR increases with load at module #1.

Figure 10 shows the PLR as a function of the load at module #1 with the length of FDLs *L* as a parameter. The number of modules is *N*=2. The load of the module #2 is set to 0.5. The

other FDL because each FDL is designed for storing only a single packet.

broken packet when it gets out from the buffer.

fore, bit-rate is not specified in our simulation.

Moreover, the PLR decreases when *M* increases.

**3. Computer Simulation**

**3.1. Packet Loss Rate**

both treated as loss of packet.

assumed to be *M*=2.

**Figure 7.** Configuration of the FDL buffer.

#### **2.4. Operation Overview of Buffering**

An example of timing chart for buffering process of a module is shown in Fig. 8.

We assume that there are initially no packets stored in the FDLs, and then five packets are arriving sequentially with random timing and variable lengths. The number of FDLs *M* is assumed to be *M*=2.

When packet no.1 is incident, 'store' signal #1 turns on triggered by the first bit and C1. The state of the 'store' signal is kept for a period of *T* FIFO. When *T* FIFO is expired, 'forward' signal turns on triggered by the C2. Then, stored packets no.1 is forwarded to output. If another module has already been open for forwarding, the 'forward' signal of this module does not turn on in order to avoid collision between this module and the forwarding module. When packet no.3 is incident before the expiration period *T* FIFO of packet no.2, it is stored into an‐ other FDL because each FDL is designed for storing only a single packet.

Although similar operation can be seen for following packets, packet no.5 is slightly differ‐ ent. The front part of it is discarded because all FDLs have already been occupied by other packets. When packet no.3 is forwarded, FDL #2 is open for storing. At the moment, the rear part of packet no.5 is stored into there. Note that the packet no.5 is therefore treated as a broken packet when it gets out from the buffer.
