**2. Design and simulation of two variants of the OPR MFLD base cell**

#### **2.1. Picture continuous logic elements (PCLE)**

Figure 1 shows the structural diagram of picture neural element (PNE) for computation of all basic matrix-continuous-logic (MCL) operations in matrix quasiBoolean algebra **C=((А,В),^, ˇ,-)** [11] for which in any set of MCL arguments matrix continuous logic function (MCLF) **F** takes the value of a subregion of one of the arguments or its supplement. The PE of matrix two-valued logic (MTVL), performing MTVL operations over matrix temporal functions Oi <sup>t</sup> (t) (in point of fact two-valued 2D-operands) realize MCLF over continuous logic variables (CLV) Oi t . The time-pulse coding of a grayscale picture is shown in Figure 1. As it is seen in Figure 2 at each point of picture output of PNE, MCL can be performed over continuous logic variables (CLV) O1 ijT,…On=2 ijT, presented by t1 ij,...tn ij durations of time pulse signals, during each interval T one of the following operations of CL: min(a,b), max(a,b), mod(a-b), mod ¯ (*a* −*b*), complementary*a*¯ =1−*a*, equivalence, etc [10, 11, 23]. The du‐ ration of MTVL formed at the output and as a result of PNE, signal *f ij NE*(*t*)= *<sup>f</sup> ij NE*(*Oij* 1(*t*), *Oij* 2(*t*)), is CL function of input binary temporal variables durations. Thus, as it is seen from Figure 3, almost all basic operations of continuous logic, neural-fuz‐ zy logic, that are shown in work [21], can be realized with the help of the time-pulse coding of variables*X*1,…,*X<sup>n</sup>* and universal (or multifunctional)picture element (UPE) of two-valued logic (TVL). But for that pulse width modulator (PWM) of PT is needed. It is not needed to Design and Modeling of Optoelectronic Photocurrent Reconfigurable (OPR) Multifunctional Logic Devices (MFLD) as the Universal Circuitry Basis for Advanced Parallel High-Performance Processing http://dx.doi.org/10.5772/54540 353

form contrast-conversion (complementary operand) image for analog picture optic inputs if PWMs PT have complementary outputs.

**Figure 1.** The PNE of matrix-continuous-logic (MCL) with programmable tuning

solutions that is why they require further development and perfection. Mathematical and other theoretical fundamentals of design of matrix multi-functional logical devices with fast acting programmable tuning were considered in paper[19], where expediency of functional basis unification, that is promising for optoelectronic parallel-pipeline systems (OEPS) with command-flow 2D-page (picture) organization [20], necessity in arrays of optic or optoelec‐ tronic triggers (memory elements) of picture type for storage of information and controlling adjusting operands as well as perspective principles of presentation and coding of multi-val‐ ued matrix data (spatial, time-pulse and spectral) were shown. Besides, the analysis of vari‐ ous algebra logics [11, 19, 21-24] for functional systems of switching functions, in spite of their diversity allows us to suggest a very useful idea, in our opinion, that lies in following.

It is possible to create more sophisticated problem-oriented processors, in which the specific time-pulse operands encoding and only elements of two-valued logic are used, which will realize functions of different logics, continuous etc. Taking into account the universality, parallel information processing of the universal elements and the use of only two-valued logic elements for implementation of all other operations the approach is a very promising.

That is why the aim of the given work is to consider the results of design and investigation of optoelectronic smart time-pulse coded photocurrent reconfigurable MFLD as basic com‐ ponents for 2D-array logic devices for advanced neural networks and optical computers.

**2. Design and simulation of two variants of the OPR MFLD base cell**

Figure 1 shows the structural diagram of picture neural element (PNE) for computation of all basic matrix-continuous-logic (MCL) operations in matrix quasiBoolean algebra **C=((А,В),^, ˇ,-)** [11] for which in any set of MCL arguments matrix continuous logic function (MCLF) **F** takes the value of a subregion of one of the arguments or its supplement. The PE of matrix two-valued logic (MTVL), performing MTVL operations over matrix temporal

As it is seen in Figure 2 at each point of picture output of PNE, MCL can be performed over continuous logic variables (CLV) O1 ijT,…On=2 ijT, presented by t1 ij,...tn ij durations of time pulse signals, during each interval T one of the following operations of CL: min(a,b),

ration of MTVL formed at the output and as a result of PNE, signal

Thus, as it is seen from Figure 3, almost all basic operations of continuous logic, neural-fuz‐ zy logic, that are shown in work [21], can be realized with the help of the time-pulse coding of variables*X*1,…,*X<sup>n</sup>* and universal (or multifunctional)picture element (UPE) of two-valued logic (TVL). But for that pulse width modulator (PWM) of PT is needed. It is not needed to

(t) (in point of fact two-valued 2D-operands) realize MCLF over continuous

. The time-pulse coding of a grayscale picture is shown in Figure 1.

(*a* −*b*), complementary*a*¯ =1−*a*, equivalence, etc [10, 11, 23]. The du‐

2(*t*)), is CL function of input binary temporal variables durations.

**2.1. Picture continuous logic elements (PCLE)**

352 Optoelectronics - Advanced Materials and Devices

t

¯

functions Oi <sup>t</sup>

*NE*(*t*)= *<sup>f</sup> ij*

*f ij*

logic variables (CLV) Oi

max(a,b), mod(a-b), mod

*NE*(*Oij*

1(*t*), *Oij*

Thus, becomes obvious that for time – pulse coding realization of PNE of matrix-continuous -logic (MCL) with programmable tuning is necessary UPE of TVL or picture MFLD, by means of which continuously – logic operations over time – pulse signals can be realized. In Figure 1 selection of picture logic functions is carried out by electric adjusting signals and all array cells will realize the same function at the same time. For many appendices it is expedi‐ ent to choose a logic function at each point of the matrix processor, and therefore there is a desire to make management and tuning also in the form of optical matrix operands. It essen‐ tially expands functionality of such processors and MFLD on which basis they are realized.

In work [25] MFLD of two-valued logic (TVL) on current mirrors, photodiodes and LEDs with schemes of their drivers are described and simulated. They are relatively difficult as contain four current mirrors (CM), four schemes ХОR, four elements АND and one logic ele‐ ment OR. In the same work different optoelectronic circuitry were offered on base of 2-4 CM and one photo diode, realizing the Boolean operations AND, NOT, OR, NOR, et al with po‐ tential and current outputs. They are based on threshold elements, comparators of currents (photocurrents) on current mirrors and circuitry of limited subtraction (CLS). Such base ele‐ ments also were used for realization of other elements of continuous logic, including opera‐ tions equivalence (nonequivalence) and etc. [21, 26, 27]. Therefore developing further this approach we use for design of the OPR MFLD.

**Figure 2.** Time diagrams of CL operation fulfillment by means of time-pulse CL variables

#### **2.2. Designing of the base cell for the first version of OPR MFLD-1**

The function circuit of the OPR MFLD-1 (the first version) is shown in figure. 3, and the cir‐ cuit diagram of the OPR MFLD-1 on 1.5μm CMOS transistors is shown in figure. 4. It con‐ tains 4 optical inputs (the aperture of photodiodes PD) four cells (PD-CM)1 ÷ (PD-CM)4 executing a role of threshold elements (a threshold -i0) and realizing operation of the limited subtraction(LS):*i CMi* =*ipd* − . *i* <sup>0</sup>; current mirror СМ5 (or instead of its CM'5 with the optical ad‐ justed threshold) for the reproduction of thresholds*i* <sup>0</sup> =2*I*0 ; current mirrors СМ6-M and СМ7-M (M denotes the multiplication currents) for formation together with drivers signals

The cell for the first version of OPR MFLD-1 has a different sub-options, which correspond to different patterns of formation of the thresholds*i* <sup>0</sup>, namely: 1) sub-option with the forma‐ tion of all four thresholds using individual current sources, 2) sub-option - with the help of a current mirror - multiplier CM5 and a single current source2*I*0, 3) sub-option - using the cur‐ rent mirror-multiplier CM'5 with a photodiode for input of the threshold current*i* <sup>0</sup> =2*I*0.

**Figure 3.** The function circuit of the OPR MFLD-1

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(currents) for four LEDs (2 direct outputs) and LED ' (2 additional inverse outputs).

In Figures 5a, 5b it is shown constructive (a matrix fragment – one OPR MFLD-1) the scheme of base nodes and the most simple optical imaging system for connections. The scheme contains 4 photo diodes, 5+8+5=18 transistors (without transistors of drivers) and the scheme is enough simple. By changing optical (or electrical) signals of tuning vector у1÷у4 at in‐ put 4 photodiodes signals from light emitter diodes LED and *LED* ¯ of the OPR MFLD-1 scheme are moved.

Design and Modeling of Optoelectronic Photocurrent Reconfigurable (OPR) Multifunctional Logic Devices (MFLD) as the Universal Circuitry Basis for Advanced Parallel High-Performance Processing http://dx.doi.org/10.5772/54540 355

**Figure 3.** The function circuit of the OPR MFLD-1

**Figure 2.** Time diagrams of CL operation fulfillment by means of time-pulse CL variables

**2.2. Designing of the base cell for the first version of OPR MFLD-1**

subtraction(LS):*i*

scheme are moved.

*CMi* =*ipd* − . *i*

354 Optoelectronics - Advanced Materials and Devices

justed threshold) for the reproduction of thresholds*i*

to different patterns of formation of the thresholds*i*

The function circuit of the OPR MFLD-1 (the first version) is shown in figure. 3, and the cir‐ cuit diagram of the OPR MFLD-1 on 1.5μm CMOS transistors is shown in figure. 4. It con‐ tains 4 optical inputs (the aperture of photodiodes PD) four cells (PD-CM)1 ÷ (PD-CM)4 executing a role of threshold elements (a threshold -i0) and realizing operation of the limited

СМ7-M (M denotes the multiplication currents) for formation together with drivers signals

The cell for the first version of OPR MFLD-1 has a different sub-options, which correspond

tion of all four thresholds using individual current sources, 2) sub-option - with the help of a current mirror - multiplier CM5 and a single current source2*I*0, 3) sub-option - using the cur‐

In Figures 5a, 5b it is shown constructive (a matrix fragment – one OPR MFLD-1) the scheme of base nodes and the most simple optical imaging system for connections. The scheme contains 4 photo diodes, 5+8+5=18 transistors (without transistors of drivers) and the scheme is enough simple. By changing optical (or electrical) signals of tuning vector у1÷у4 at in‐ put 4 photodiodes signals from light emitter diodes LED and *LED* ¯ of the OPR MFLD-1

(currents) for four LEDs (2 direct outputs) and LED ' (2 additional inverse outputs).

rent mirror-multiplier CM'5 with a photodiode for input of the threshold current*i*

<sup>0</sup>; current mirror СМ5 (or instead of its CM'5 with the optical ad‐

<sup>0</sup> =2*I*0 ; current mirrors СМ6-M and

<sup>0</sup>, namely: 1) sub-option with the forma‐

<sup>0</sup> =2*I*0.

**Figure 4.** The circuit diagram of the OPR MFLD-1 on 1.5µm CMOS transistors for modeling with OrCAD 16.3 PSpice

**Figure 5.** а) Optical plane-to-plane imaging system (b) The constructive scheme of a base cell (fragment) for the OPR

Design and Modeling of Optoelectronic Photocurrent Reconfigurable (OPR) Multifunctional Logic Devices (MFLD) as

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Results of modeling by means of package OrCAD 16.3 of the offered OPR MFLD-1 are shown in Figure 6 for different tuning signals у1у4 which set necessary functions, for differ‐ ent supply voltage and different amplitudes of currents *I*0 (3μА, 10μА and 30μА) according‐ ly. In Figure 6a, the first diagram above shows the pulses of currents I30, I29, which correspond to the inputs of BN, AN, and current ID (Q40) at the output node (PD-CM)1. On the same Figure, the second, third and fourth diagrams show, respectively, the input and output pulse currents of nodes (PD-CM)2÷ (PD-CM)4. Current pulse I35 duration (see the third diagram in Figure 6a), which is at the input A, equals 2μs. Current pulse I39 duration (see the fourth diagram in Figure 6a) equals 7μs at the input B. The output pulse current ID (Q44) of the circuit is shown in the bottom diagram in Figure 6a and its duration equals 8μS

**2.3. Simulation of the base cell for the first version of OPR MFLD-1**

(8=10-2). This confirms the correctness work of the circuit.

MFLD-1

Signals from the first input A and from the second input B (a variant of output II) together with tuning vector у1÷у4 will be transformed to a total photocurrent. Base elements of limit‐ ed subtraction (LS) based on (PD-CM)i separate out corresponding logic minterms by sub‐ traction of threshold currents *i* 0from currents of PDs. We researched various updating of such base circuits. For the task of thresholds it is possible to use the various optical and elec‐ tric approaches, besides operating generators of currents and various schemes of drivers are possible. A basic accent we nevertheless do on input part of conversion and processing, be‐ cause forming of matrix of emitters is simpler task, if not to take into account the technologi‐ cal aspects of their integration on a chip.

Design and Modeling of Optoelectronic Photocurrent Reconfigurable (OPR) Multifunctional Logic Devices (MFLD) as the Universal Circuitry Basis for Advanced Parallel High-Performance Processing http://dx.doi.org/10.5772/54540 357

**Figure 5.** а) Optical plane-to-plane imaging system (b) The constructive scheme of a base cell (fragment) for the OPR MFLD-1

#### **2.3. Simulation of the base cell for the first version of OPR MFLD-1**

**Figure 4.** The circuit diagram of the OPR MFLD-1 on 1.5µm CMOS transistors for modeling with OrCAD 16.3 PSpice

ed subtraction (LS) based on (PD-CM)i

cal aspects of their integration on a chip.

traction of threshold currents *i*

356 Optoelectronics - Advanced Materials and Devices

Signals from the first input A and from the second input B (a variant of output II) together with tuning vector у1÷у4 will be transformed to a total photocurrent. Base elements of limit‐

such base circuits. For the task of thresholds it is possible to use the various optical and elec‐ tric approaches, besides operating generators of currents and various schemes of drivers are possible. A basic accent we nevertheless do on input part of conversion and processing, be‐ cause forming of matrix of emitters is simpler task, if not to take into account the technologi‐

separate out corresponding logic minterms by sub‐

0from currents of PDs. We researched various updating of

Results of modeling by means of package OrCAD 16.3 of the offered OPR MFLD-1 are shown in Figure 6 for different tuning signals у1у4 which set necessary functions, for differ‐ ent supply voltage and different amplitudes of currents *I*0 (3μА, 10μА and 30μА) according‐ ly. In Figure 6a, the first diagram above shows the pulses of currents I30, I29, which correspond to the inputs of BN, AN, and current ID (Q40) at the output node (PD-CM)1. On the same Figure, the second, third and fourth diagrams show, respectively, the input and output pulse currents of nodes (PD-CM)2÷ (PD-CM)4. Current pulse I35 duration (see the third diagram in Figure 6a), which is at the input A, equals 2μs. Current pulse I39 duration (see the fourth diagram in Figure 6a) equals 7μs at the input B. The output pulse current ID (Q44) of the circuit is shown in the bottom diagram in Figure 6a and its duration equals 8μS (8=10-2). This confirms the correctness work of the circuit.

vanced, that is possibility to receive processing time T at level 1÷10ns, i.e. to raise

Design and Modeling of Optoelectronic Photocurrent Reconfigurable (OPR) Multifunctional Logic Devices (MFLD) as

We tested experimentally the circuit for all functions that it can implement. The experiments confirm the implementation of all theoretically possible functions in a wide range of voltag‐ es, currents and operating periods of treatment. But given the size limitations of article, here

**Figure 7.** а) Dependence of the power consumption from supply voltage and input current range; (b) dependence of

If cells of the MFLD-1 with *Pdrain*= 1÷5mW are integrated into array of 32x32 elements or more, the general productivity of such array OPR MFLD-1 will reach 1012 CL-logic opera‐ tions/sec. A modified variant of OPR MFLD-1 in which signals у1¸у4 are realized on current generators with possibility of their programming is also offered. Besides, if the array of cells MFLD-1 realizes the same function it is possible to choose signals with sample correspond‐

case. Because it is necessary to give signals not from three optical apertures, but only from

Modeling results of the OPR MFLD-1 with MathCAD which confirm normal functioning of OPR MFLD-1 for all 16 possible functions of binary logic and corresponding functions of continuous logic are shown in figure 8-11. Two inputs 2D operands XA and XB (Figure 8) with dimensional of 32x32 pixels are transformed to XAR and XBR by multiplication of one

. The problem of simplification of the optical system is decided in this


CL-logic operations/sec.

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the Universal Circuitry Basis for Advanced Parallel High-Performance Processing

productivity of one channel OPR MFLD-1 to 108

time delay and fronts from supply voltage and input current values

ing nodes (PD-CM)i

two apertures on the OPR MFLD-1 chip.

**2.4. Modeling of array of the OPR MFLD-1 with MathCAD**

pixel to 2x2 pixels. Matrixes XAR, XBR have dimensional of 64x64 pixels.

we do not present all results and charts.

**Figure 6.** а) Simulation results of cell of OPR MFLD-1 for functions of NAND two-valued logic(TVL) and NMIN continu‐ ous logic (CL) at a supply voltage5 V; (b) Simulation results of cell of OPR MFLD-1 for functions of OR TVL and MAX CL logic (3 V, t(A)=t(I35)=200nS, t(B)=t(I39)=700nS, t=100nS, T=1,1µs); (с) Simulation results of cell of OPR MFLD-1 for functions XOR TVL and NEQ CL (3V, 0.1mW, 3µA, t(A)=t(I35)=200nS, t(B)=t(I39)=700nS,T=1.1µs); (d) Simulation results of cell of OPR MFLD-1 for functions NXOR TVL and EQ CL (3V, 10µA, photo-configurable, t(A)=t(I35)=2µS, t(B)=t(I39)=7µS, tout = t(ID(Q44))=2+3=5 µS)

The diagrams in Figures 6b, 6c, 6d, similar to Figure 6a shows the corresponding input and output currents of the circuit. The difference lies in the different modes for different input pulse durations and the presence of additional power consumption graphics. In Figure 7а dependence of power consumption of OPR MFLD-1 from *I*0and supply voltage is shown, and in Figure 7b dependence of *t*preset and *t*frontsfrom *I*<sup>0</sup> = *I*max is shown. From them it is visi‐ ble, that the power consumption of OPR MFLD-1 *Pdrain* (without drivers and output part) is about 0.1-2.5mW. If to take into account that the currents of LEDs must (taking into account the coefficient of transformation and sensitiveness of photo-detectors PD) to be at least in 5÷10 times more, the *Pdrain* will increase in 2÷4 times. But, for example, at*I*<sup>0</sup> =10*μА*, the power consumption will be *Pdrain* ≤4÷5mW. At currents 1÷3μA it decreases to 1mW. Delay time is no more than 50÷100 ns, and the period T of time pulse processed signals go into in a micro‐ second range 1÷16 μs. If to use not 1.5μm technologies CMOS transistors, but more ad‐ vanced, that is possibility to receive processing time T at level 1÷10ns, i.e. to raise productivity of one channel OPR MFLD-1 to 108 -109 CL-logic operations/sec.

We tested experimentally the circuit for all functions that it can implement. The experiments confirm the implementation of all theoretically possible functions in a wide range of voltag‐ es, currents and operating periods of treatment. But given the size limitations of article, here we do not present all results and charts.

**Figure 7.** а) Dependence of the power consumption from supply voltage and input current range; (b) dependence of time delay and fronts from supply voltage and input current values

If cells of the MFLD-1 with *Pdrain*= 1÷5mW are integrated into array of 32x32 elements or more, the general productivity of such array OPR MFLD-1 will reach 1012 CL-logic opera‐ tions/sec. A modified variant of OPR MFLD-1 in which signals у1¸у4 are realized on current generators with possibility of their programming is also offered. Besides, if the array of cells MFLD-1 realizes the same function it is possible to choose signals with sample correspond‐ ing nodes (PD-CM)i . The problem of simplification of the optical system is decided in this case. Because it is necessary to give signals not from three optical apertures, but only from two apertures on the OPR MFLD-1 chip.

#### **2.4. Modeling of array of the OPR MFLD-1 with MathCAD**

**Figure 6.** а) Simulation results of cell of OPR MFLD-1 for functions of NAND two-valued logic(TVL) and NMIN continu‐ ous logic (CL) at a supply voltage5 V; (b) Simulation results of cell of OPR MFLD-1 for functions of OR TVL and MAX CL logic (3 V, t(A)=t(I35)=200nS, t(B)=t(I39)=700nS, t=100nS, T=1,1µs); (с) Simulation results of cell of OPR MFLD-1 for functions XOR TVL and NEQ CL (3V, 0.1mW, 3µA, t(A)=t(I35)=200nS, t(B)=t(I39)=700nS,T=1.1µs); (d) Simulation results of cell of OPR MFLD-1 for functions NXOR TVL and EQ CL (3V, 10µA, photo-configurable, t(A)=t(I35)=2µS,

The diagrams in Figures 6b, 6c, 6d, similar to Figure 6a shows the corresponding input and output currents of the circuit. The difference lies in the different modes for different input pulse durations and the presence of additional power consumption graphics. In Figure 7а dependence of power consumption of OPR MFLD-1 from *I*0and supply voltage is shown, and in Figure 7b dependence of *t*preset and *t*frontsfrom *I*<sup>0</sup> = *I*max is shown. From them it is visi‐ ble, that the power consumption of OPR MFLD-1 *Pdrain* (without drivers and output part) is about 0.1-2.5mW. If to take into account that the currents of LEDs must (taking into account the coefficient of transformation and sensitiveness of photo-detectors PD) to be at least in 5÷10 times more, the *Pdrain* will increase in 2÷4 times. But, for example, at*I*<sup>0</sup> =10*μА*, the power consumption will be *Pdrain* ≤4÷5mW. At currents 1÷3μA it decreases to 1mW. Delay time is no more than 50÷100 ns, and the period T of time pulse processed signals go into in a micro‐ second range 1÷16 μs. If to use not 1.5μm technologies CMOS transistors, but more ad‐

t(B)=t(I39)=7µS, tout = t(ID(Q44))=2+3=5 µS)

358 Optoelectronics - Advanced Materials and Devices

Modeling results of the OPR MFLD-1 with MathCAD which confirm normal functioning of OPR MFLD-1 for all 16 possible functions of binary logic and corresponding functions of continuous logic are shown in figure 8-11. Two inputs 2D operands XA and XB (Figure 8) with dimensional of 32x32 pixels are transformed to XAR and XBR by multiplication of one pixel to 2x2 pixels. Matrixes XAR, XBR have dimensional of 64x64 pixels.

ESAB 1 1 UQSAB 1 UQSAB 1 UQSAB 1 UQSAB k,l ( k,l)( k,l) ( k,l)( k,l) =F -F - <sup>é</sup> - ù é - F - <sup>ù</sup> <sup>ë</sup> û ë <sup>û</sup> (3)

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For more detailed consideration fragments AP, BP, OPP, OSP, OQP, QSP with dimensional of 2x2 subpixels or 4x4 pixels from matrixes AXR, BXR, OP, SAB, UQSAB, ESAB are shown in Figure 10. The fragments are shown as matrixes and images. For conventional presenta‐ tion of the images in MathCAD the matrixes are multiplied by 80. Output of equivalence op‐ eration is QSP with dimensional of 2x2, but for OPR MFLD correct operation matrixes QSAP

Design and Modeling of Optoelectronic Photocurrent Reconfigurable (OPR) Multifunctional Logic Devices (MFLD) as

**Figure 10.** Simulation results of four base cells (2х2 subpixel) of matrix OPR MFLD-1 (function NXOR - EQ)

**Figure 11.** Simulation results for other functions realizations with the OPR MFLD-1

*2.5.1. Simulation of OPR MFLD-2 with OrCAD 16.3*

**2.5. Investigation of the base cell for the second version of OPR MFLD-2**

The second circuit variant is shown in Figure 12. It differs from the previously discussed first variant that the input optical signals from each of the i,j-th base cell of two picture oper‐ ands are fed to a photo-detector. One of the picture input using the appropriate shadow mask weakens the signals of one of the operands is a factor of 2. Therefore, the first unit of

Examples of other functions realizations with the OPR MFLD-1 as fragments of images are

and output matrix ESAB is formed.

shown in Figures 11

and QABP with dimensional of 4x4 are used.

**Figure 8.** Simulation results of forming and processing processes using OPR MFLD-1

Four matrixes M1÷M4 are formed with formulas shown in Figure 9. These matrixes are used for selection of one subpixel of four pixels of XAR and XBR. Matrixes AXR and BXR are formed after XAR and XBR by elementwise non-equivalence (⊕) operation on matrixes MA and MB. Tuning 2D operand OP is formed by matrixes M1÷M4 and scalar tuning signals oy1÷oy4 or by signals y1÷y4.

$$\begin{array}{llll} \text{M1}\_{\mathbf{i}\_{\star},\mathbf{j}} \simeq \mathsf{mod}[\{\mathbf{i} + 1\}, \mathbf{2}] \cdot \mathsf{mod}[\{\mathbf{j} + 1\}, \mathbf{2}] & \text{MA} \coloneqq \mathsf{M1} + \mathsf{M2} \quad \mathsf{OP} \coloneqq \sum\_{i=1}^{d} \mathrm{op}\_{i} \cdot \mathrm{M}\_{\mathbf{i}},\\ \text{M2}\_{\mathbf{i}\_{\star},\mathbf{j}} \simeq \mathsf{mod}[\{\mathbf{i} + 1\}, \mathbf{2}] \cdot \mathsf{mod}[\{\mathbf{j} + 0\}, \mathbf{2}] & \text{MB} \coloneqq \mathsf{M1} + \mathsf{M2} \quad \mathsf{where } \mathrm{M\_1} \in \mathsf{M1} \,\,\, \mathsf{of} \,\, \mathsf{M1} \\ \text{MB}\_{\mathbf{i}\_{\star},\mathbf{j}} \simeq \mathsf{mod}[\{\mathbf{i} + 0\}, \mathbf{2}] \cdot \mathsf{mod}[\{\mathbf{j} + 1\}, \mathbf{2}] & \text{AZR} \coloneqq \mathsf{$$

**Figure 9.** Transformations formulas for matrixes, tuning operand OP formation and additions

Matrix SAB is formed as sum of AXR, BXR and OP. Threshold processing is done over ele‐ ments of SAB matrix and matrix QSAB is formed:

$$\mathbf{QSAB}\_{\mathbf{l}\_{\parallel}|} = \Phi \left[ 1 - \Phi \left( 3 - \mathbf{SAB}\_{\mathbf{l}\_{\parallel}} \right) \left( 3 - \mathbf{SAB}\_{\mathbf{l}\_{\parallel}} \right) \right] \left[ 1 - \Phi \left( 3 - \mathbf{SAB}\_{\mathbf{l}\_{\parallel}} \right) \left( 3 - \mathbf{SAB}\_{\mathbf{l}\_{\parallel}} \right) \right] \tag{1}$$

The threshold value tr =3. Four subpixels are united to one pixel with formula

$$\text{UQSAB}\_{\text{k,l}} \text{=QSAB}\_{\text{2k,2l}} \text{+QSAB}\_{\text{2k,2l+1}} \text{+QSAB}\_{\text{2k+1,2l}} \text{+QSAB}\_{\text{2k+1,2l+1}} \tag{2}$$

and output matrix UQSAB dimension is 32x32. Another final threshold processing (t0=1) is done with formula

Design and Modeling of Optoelectronic Photocurrent Reconfigurable (OPR) Multifunctional Logic Devices (MFLD) as the Universal Circuitry Basis for Advanced Parallel High-Performance Processing http://dx.doi.org/10.5772/54540 361

$$\mathbf{ESAB}\_{\mathbf{k},\mathbf{l}} = \Phi \left[ \mathbf{1} - \Phi \left( \mathbf{1} - \mathbf{UQSAB}\_{\mathbf{k},\mathbf{l}} \right) \left( \mathbf{1} - \mathbf{UQSAB}\_{\mathbf{k},\mathbf{l}} \right) \right] \left[ \mathbf{1} - \Phi \left( \mathbf{UQSAB}\_{\mathbf{k},\mathbf{l}} \right) \left( \mathbf{1} - \mathbf{UQSAB}\_{\mathbf{k},\mathbf{l}} \right) \right] \tag{3}$$

and output matrix ESAB is formed.

**Figure 8.** Simulation results of forming and processing processes using OPR MFLD-1

**Figure 9.** Transformations formulas for matrixes, tuning operand OP formation and additions

The threshold value tr =3. Four subpixels are united to one pixel with formula

ments of SAB matrix and matrix QSAB is formed:

oy1÷oy4 or by signals y1÷y4.

360 Optoelectronics - Advanced Materials and Devices

done with formula

Four matrixes M1÷M4 are formed with formulas shown in Figure 9. These matrixes are used for selection of one subpixel of four pixels of XAR and XBR. Matrixes AXR and BXR are formed after XAR and XBR by elementwise non-equivalence (⊕) operation on matrixes MA and MB. Tuning 2D operand OP is formed by matrixes M1÷M4 and scalar tuning signals

Matrix SAB is formed as sum of AXR, BXR and OP. Threshold processing is done over ele‐

and output matrix UQSAB dimension is 32x32. Another final threshold processing (t0=1) is

QSAB 1 3 SAB 3 SAB 1 3 SAB 3 SAB i,j ( )( ) ( )( ) i,j i,j i,j i,j =F -F - - -F - - é ùé ù ë ûë û (1)

UQSAB =QSAB +QSAB +QSAB +QSAB k,l 2k,2l 2k,2l+1 2k+1,2l 2k+1,2l+1 (2)

For more detailed consideration fragments AP, BP, OPP, OSP, OQP, QSP with dimensional of 2x2 subpixels or 4x4 pixels from matrixes AXR, BXR, OP, SAB, UQSAB, ESAB are shown in Figure 10. The fragments are shown as matrixes and images. For conventional presenta‐ tion of the images in MathCAD the matrixes are multiplied by 80. Output of equivalence op‐ eration is QSP with dimensional of 2x2, but for OPR MFLD correct operation matrixes QSAP and QABP with dimensional of 4x4 are used.

**Figure 10.** Simulation results of four base cells (2х2 subpixel) of matrix OPR MFLD-1 (function NXOR - EQ)

Examples of other functions realizations with the OPR MFLD-1 as fragments of images are shown in Figures 11

**Figure 11.** Simulation results for other functions realizations with the OPR MFLD-1

#### **2.5. Investigation of the base cell for the second version of OPR MFLD-2**

#### *2.5.1. Simulation of OPR MFLD-2 with OrCAD 16.3*

The second circuit variant is shown in Figure 12. It differs from the previously discussed first variant that the input optical signals from each of the i,j-th base cell of two picture oper‐ ands are fed to a photo-detector. One of the picture input using the appropriate shadow mask weakens the signals of one of the operands is a factor of 2. Therefore, the first unit of the circuit consists of current comparators, which convert the output voltages into a digital form that is uniquely appropriate input situation.

rent which is required for light emitters, or for driver circuit, you can use the multiplier cur‐

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The simulation results of this scheme on 65nm CMOS transistors with OrCAD 16.3 PSpice,

**Figure 13.** The results of modeling of the base cell for second version of OPR MFLD-2 for implementation of function

Experiments have shown that the power consumption of a cell does not exceed 200÷300μW, delay times and pulse fronts are less than 1 nanosecond, and the basic cell is realized on 44 (or 36) transistors and 11 current sources on 11÷15 transistors. The duration time of pulsecoded signal is in the range of processing cycles, and the pulse period is 100 nanoseconds. This shows that it is possible to increase the frame processing rate to 10 MHz but at the ex‐ pense of accuracy and complexity of matching photodetectors with current mirrors. Simula‐ tion results with OrCAD16.3 of the same basic cell circuit of the OPR MFLD-2 in the mode of implementation of the functions of the nonequivalence CL or XOR TVL are shown in Fig. 13. Diagrams that explain the work of OPR MFLD-2 in the implementation of functions of the

nonequivalence CL or XOR TVL: Id = 5μA, 3V supply voltage, signal durations ta

pulse = 80ns. In the first diagram above - the output current signal, the second - two input signals and their weighted sum, the down three: the third, fourth and fifth - currents at the output of the threshold units (green solid) and their complements (blue dashed). It uses vec‐ tor tuning signals **Y**= {Y0, Y1, Y2, Y3} = {0, 1, 1, 0}, and the current level is 5 μA. At the out‐ put the correct signal is formed ≈ 30 ns duration. The change of the vector set to {0, 1, 0, 0} allows for the output function I22 \* NI23 (where NI23 – the complement of the signal I23), as shown in Figure 14. For credibility, that the function is implemented correctly, we did a change in the duration of signals, such that the first signal tpulse(I22) = 80ns and tpulse (I23) = 50ns (the signals changed their duration). The results showed that there was a signal at the

pulse = 50ns,

at different voltages and power levels of input signals are shown in fig. 13 -20.

rent at the current mirror.

non-equivalence of continuous logic (CL) based on XOR TVL

output, which has a duration ≈30 ns.

t b

**Figure 12.** Circuit diagram of the base cell for the OPR MFLD-2 (the second version)

With the help of nodes in the current voltage conversion and control signals Y0-Y3 at the output node is formed by the resulting signal as a current, which corresponds to the selected desired logic function. The set of possible logical set of vector signals Y0-Y3 has 16 possible combinations. Selecting one of them allows you to implement any 16 of possible two-valued logic of binary operations. If the input signals are continuous in the time-pulse coded form, selecting the desired operation as a two-valued logic, such as AND, the operation MIN is implemented from time-pulse encoded signals. For the first model experiments in the scheme of an input photo-sensor used two of the current source to set the time of the input time-pulse signals (TPS).Instead of photo detectors are used to control the function of the sources of Y0 ÷ Y3 current. The reference currents are shown as current sources for simplici‐ ty. The current sources can be implemented on the same transistors or may be given by means of optical signals with fixed intensity. For the formation of the amplified output cur‐ rent which is required for light emitters, or for driver circuit, you can use the multiplier cur‐ rent at the current mirror.

the circuit consists of current comparators, which convert the output voltages into a digital

form that is uniquely appropriate input situation.

362 Optoelectronics - Advanced Materials and Devices

**Figure 12.** Circuit diagram of the base cell for the OPR MFLD-2 (the second version)

With the help of nodes in the current voltage conversion and control signals Y0-Y3 at the output node is formed by the resulting signal as a current, which corresponds to the selected desired logic function. The set of possible logical set of vector signals Y0-Y3 has 16 possible combinations. Selecting one of them allows you to implement any 16 of possible two-valued logic of binary operations. If the input signals are continuous in the time-pulse coded form, selecting the desired operation as a two-valued logic, such as AND, the operation MIN is implemented from time-pulse encoded signals. For the first model experiments in the scheme of an input photo-sensor used two of the current source to set the time of the input time-pulse signals (TPS).Instead of photo detectors are used to control the function of the sources of Y0 ÷ Y3 current. The reference currents are shown as current sources for simplici‐ ty. The current sources can be implemented on the same transistors or may be given by means of optical signals with fixed intensity. For the formation of the amplified output cur‐

The simulation results of this scheme on 65nm CMOS transistors with OrCAD 16.3 PSpice, at different voltages and power levels of input signals are shown in fig. 13 -20.

**Figure 13.** The results of modeling of the base cell for second version of OPR MFLD-2 for implementation of function non-equivalence of continuous logic (CL) based on XOR TVL

Experiments have shown that the power consumption of a cell does not exceed 200÷300μW, delay times and pulse fronts are less than 1 nanosecond, and the basic cell is realized on 44 (or 36) transistors and 11 current sources on 11÷15 transistors. The duration time of pulsecoded signal is in the range of processing cycles, and the pulse period is 100 nanoseconds. This shows that it is possible to increase the frame processing rate to 10 MHz but at the ex‐ pense of accuracy and complexity of matching photodetectors with current mirrors. Simula‐ tion results with OrCAD16.3 of the same basic cell circuit of the OPR MFLD-2 in the mode of implementation of the functions of the nonequivalence CL or XOR TVL are shown in Fig. 13. Diagrams that explain the work of OPR MFLD-2 in the implementation of functions of the nonequivalence CL or XOR TVL: Id = 5μA, 3V supply voltage, signal durations ta pulse = 50ns, t b pulse = 80ns. In the first diagram above - the output current signal, the second - two input signals and their weighted sum, the down three: the third, fourth and fifth - currents at the output of the threshold units (green solid) and their complements (blue dashed). It uses vec‐ tor tuning signals **Y**= {Y0, Y1, Y2, Y3} = {0, 1, 1, 0}, and the current level is 5 μA. At the out‐ put the correct signal is formed ≈ 30 ns duration. The change of the vector set to {0, 1, 0, 0} allows for the output function I22 \* NI23 (where NI23 – the complement of the signal I23), as shown in Figure 14. For credibility, that the function is implemented correctly, we did a change in the duration of signals, such that the first signal tpulse(I22) = 80ns and tpulse (I23) = 50ns (the signals changed their duration). The results showed that there was a signal at the output, which has a duration ≈30 ns.

to 3.3V and in accordance with the results: power consumption *Pdrain* ≤150*μW* by 1.5V, cur‐ rent pulses amplitudes are 5μA and 10μA; power consumption *Pdrain* ≤350*μW* by 3.3V, cur‐

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**Figure 16.** Simulation results of the base cell for second version of OPR MFLD-2 for implementation of function: left -

Circuit diagram (Figure 18) of the OPR MFLD-2 with photodiodes is used for simulations with OrCAD16.3 PSpice. The model of the photodiode is the same as in Figure 4. The simu‐ lation results are shown in Figure 19. Displaying 4 periods, at each different tuning vector set is applied and different functions is performed: the first period - vector {1,0,0,1} (equiva‐ lence), the second period - vector {1,0, 1,0} (inversion of the first variable), the third period -

The signals of these vectors are displayed on the lower four graphs yellow lines. The blue lines show the output currents generated configuration signals and the corresponding no‐ des. The sum of output currents of these nodes represents the output signal. It was featured on the second chart above the green line and the input photocurrent from the two argu‐

vector {0,1,1,0} (non-equivalence), the fourth period - vector {0,1,0,0} (AND (*a*¯, *b*).

equivalence operation CL (NXOR TVL), right - operation max ¯(*a*, *<sup>b</sup>*) CL (NOR TVL)

**Figure 17.** Signal diagrams for mode of AND (min CL) operation implementation

rent pulse amplitudes 5μA and 10μA.

**Figure 14.** The diagrams of signals in the circuit with a vector set {0, 1, 0, 0} for the implementation of the function AND(*a*, *b*¯), where a=I22, b=I23

If change of the vector set to {0, 0, 1, 0} than there is a signal at the output which differs only in the short false pulses. Change of durations of the input signals at the same vector set pro‐ vides the desired signal at the output (see Figure 15). This confirms the correct operation of the scheme.

**Figure 15.** The diagrams of signals in the implementation of the function AND (*a*, ¯ *b*)defined by the vector set {0, 0, 1, 0}, where a=I22, b=I23, *t*p (I22) = 50ns, *t* p(I23) = 80ns.

In Figure 16 (left) the implementation of the equivalence CL (based on NXOR TVL) is shown. The output signal (the first graph above) has the total duration of 70ns. The opera‐ tion NOR TVL and on its basis the operation max ¯(*<sup>a</sup>*, *<sup>b</sup>*) CL, or the same operation min(*a*¯, *<sup>b</sup>* ¯) CL is shown in Figure 16 (right). Duration of the output signal is 20ns. Signal diagrams for mode of formation of min CL-function (based on AND) are shown in Figure 17. Left on the diagrams shows the control signals of the vector **Y**= {Y0, Y1, Y2, Y3} = {0, 0, 0, 1}, and the right - signals: output, input and intermediate. As can be seen from the simulations, device successfully implements the desired function when changing the supply voltage from 1,5V Design and Modeling of Optoelectronic Photocurrent Reconfigurable (OPR) Multifunctional Logic Devices (MFLD) as the Universal Circuitry Basis for Advanced Parallel High-Performance Processing http://dx.doi.org/10.5772/54540 365

to 3.3V and in accordance with the results: power consumption *Pdrain* ≤150*μW* by 1.5V, cur‐ rent pulses amplitudes are 5μA and 10μA; power consumption *Pdrain* ≤350*μW* by 3.3V, cur‐ rent pulse amplitudes 5μA and 10μA.

**Figure 16.** Simulation results of the base cell for second version of OPR MFLD-2 for implementation of function: left equivalence operation CL (NXOR TVL), right - operation max ¯(*a*, *<sup>b</sup>*) CL (NOR TVL)

**Figure 17.** Signal diagrams for mode of AND (min CL) operation implementation

**Figure 14.** The diagrams of signals in the circuit with a vector set {0, 1, 0, 0} for the implementation of the function

If change of the vector set to {0, 0, 1, 0} than there is a signal at the output which differs only in the short false pulses. Change of durations of the input signals at the same vector set pro‐ vides the desired signal at the output (see Figure 15). This confirms the correct operation of

In Figure 16 (left) the implementation of the equivalence CL (based on NXOR TVL) is shown. The output signal (the first graph above) has the total duration of 70ns. The opera‐ tion NOR TVL and on its basis the operation max ¯(*<sup>a</sup>*, *<sup>b</sup>*) CL, or the same operation min(*a*¯, *<sup>b</sup>*

CL is shown in Figure 16 (right). Duration of the output signal is 20ns. Signal diagrams for mode of formation of min CL-function (based on AND) are shown in Figure 17. Left on the diagrams shows the control signals of the vector **Y**= {Y0, Y1, Y2, Y3} = {0, 0, 0, 1}, and the right - signals: output, input and intermediate. As can be seen from the simulations, device successfully implements the desired function when changing the supply voltage from 1,5V

¯

*b*)defined by the vector set {0, 0, 1,

¯)

**Figure 15.** The diagrams of signals in the implementation of the function AND (*a*,

0}, where a=I22, b=I23, *t*p (I22) = 50ns, *t* p(I23) = 80ns.

AND(*a*, *b*¯), where a=I22, b=I23

364 Optoelectronics - Advanced Materials and Devices

the scheme.

Circuit diagram (Figure 18) of the OPR MFLD-2 with photodiodes is used for simulations with OrCAD16.3 PSpice. The model of the photodiode is the same as in Figure 4. The simu‐ lation results are shown in Figure 19. Displaying 4 periods, at each different tuning vector set is applied and different functions is performed: the first period - vector {1,0,0,1} (equiva‐ lence), the second period - vector {1,0, 1,0} (inversion of the first variable), the third period vector {0,1,1,0} (non-equivalence), the fourth period - vector {0,1,0,0} (AND (*a*¯, *b*).

The signals of these vectors are displayed on the lower four graphs yellow lines. The blue lines show the output currents generated configuration signals and the corresponding no‐ des. The sum of output currents of these nodes represents the output signal. It was featured on the second chart above the green line and the input photocurrent from the two argu‐ ments shows a blue line. At the top graph shows the power consumption of the base cell. The main problem in these cells is a significant deterioration in fronts (an increase of up to 200 ns). Moreover, no change in the operating voltage from 3V to 5V, no change in ampli‐ tude of photocurrents (in the experiments, Io = 5μA, 10μA, 15μA, but at 20μA did not work!), including at different levels of reference current generators, practice does not signifi‐ cantly affect the duration of the fronts. It is therefore necessary to look for other circuit solu‐ tions, for example, use the cascode circuit of current mirrors, more complex, but high-speed, current or voltage comparators. But at the same time significantly increase the hardware cost of a basic cell, and it does not allow for a high level of integration on a chip. So here we are showing the circuit with extended processing period up to 10μS, which with Io = 5μA circuit will provide the required characteristics. Power consumption does not exceed 300÷350μW at a supply voltage of 2.4V and the 3.0V on photodiodes. Results of experiments are shown in Figure 20. By dynamic reconfiguration of optical signals (vector Y) the desired function of the basic cell is provided and duration of the reconfiguration process is equal to the period T = 10÷100μs. In addition, if use other technologies, the vectors set can be repre‐ sented using electrical signals.

**Figure 19.** Diagrams of signals at modeling cell with an optical configuration for the desired function and the input

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**Figure 20.** Diagrams showing the ability to dynamically reconfigurable the cells on the implementation of all 16 possi‐ ble functions of TVL with period of 100µs (total duration 16 periods). The first graph shows the output signal and the second - the input signals. At the bottom four graphs in yellow show signals at photodiodes, and green - generated

Simulation results of the offered OPR MFLD-2 with MathCAD and it usage for image proc‐

photodiode

current logical components

*2.5.2. Simulation of the OPR MFLD-2 with MathCAD*

essing and fuzzy logic operations are shown in fig. 21-24.

**Figure 18.** The base cell for OPR MFLD-2 with one input and four control photodiodes

Design and Modeling of Optoelectronic Photocurrent Reconfigurable (OPR) Multifunctional Logic Devices (MFLD) as the Universal Circuitry Basis for Advanced Parallel High-Performance Processing http://dx.doi.org/10.5772/54540 367

**Figure 19.** Diagrams of signals at modeling cell with an optical configuration for the desired function and the input photodiode

**Figure 20.** Diagrams showing the ability to dynamically reconfigurable the cells on the implementation of all 16 possi‐ ble functions of TVL with period of 100µs (total duration 16 periods). The first graph shows the output signal and the second - the input signals. At the bottom four graphs in yellow show signals at photodiodes, and green - generated current logical components

#### *2.5.2. Simulation of the OPR MFLD-2 with MathCAD*

ments shows a blue line. At the top graph shows the power consumption of the base cell. The main problem in these cells is a significant deterioration in fronts (an increase of up to 200 ns). Moreover, no change in the operating voltage from 3V to 5V, no change in ampli‐ tude of photocurrents (in the experiments, Io = 5μA, 10μA, 15μA, but at 20μA did not work!), including at different levels of reference current generators, practice does not signifi‐ cantly affect the duration of the fronts. It is therefore necessary to look for other circuit solu‐ tions, for example, use the cascode circuit of current mirrors, more complex, but high-speed, current or voltage comparators. But at the same time significantly increase the hardware cost of a basic cell, and it does not allow for a high level of integration on a chip. So here we are showing the circuit with extended processing period up to 10μS, which with Io = 5μA circuit will provide the required characteristics. Power consumption does not exceed 300÷350μW at a supply voltage of 2.4V and the 3.0V on photodiodes. Results of experiments are shown in Figure 20. By dynamic reconfiguration of optical signals (vector Y) the desired function of the basic cell is provided and duration of the reconfiguration process is equal to the period T = 10÷100μs. In addition, if use other technologies, the vectors set can be repre‐

sented using electrical signals.

366 Optoelectronics - Advanced Materials and Devices

**Figure 18.** The base cell for OPR MFLD-2 with one input and four control photodiodes

Simulation results of the offered OPR MFLD-2 with MathCAD and it usage for image proc‐ essing and fuzzy logic operations are shown in fig. 21-24.

Formulas for simulation processing with MathCAD are shown in Figure 21. At first, input two 2D operands **A1** and **B1** and its weighted sum **SIAB** are formed. The coefficient and threshold t0= 10 because the current in the OPR MFLD-2 circuit is 10μA. Contrast comple‐ mentary images are matrixes **AN1** and **BN1**. After threshold processing by current compara‐ tors the direct matrixes **T1SIAB**, **T2SIAB**, **T3SIAB** and matrixes **TN1SIAB**, **TN2SIAB**, **TN3SIAB** of complementary images are formed. Four picture tuning operand **NY0 ÷NY3** are formed with tuning vector signals ny0÷ny3. Four logical members **SY0÷SY3** are formed using simultaneous threshold and state decoding operations. The sum of those members is the output matrix function **NF**. All operands dimension is 64x64 elements. All images of above mentioned matrixes and some output functions are shown in Figure 22.

**Figure 22.** The simulation results of the OPR MFLD-2 with MathCAD for single-cycle high-speed computation of con‐ tinuous logic operations and / or fuzzy logic for membership functions. In the bottom row the functions realization MAX/OR, MIN/AND, EQ/NXOR, (*A*¯ ⋅ *B*) over the two graphs presented in the form of membership functions of oper‐

Design and Modeling of Optoelectronic Photocurrent Reconfigurable (OPR) Multifunctional Logic Devices (MFLD) as

the Universal Circuitry Basis for Advanced Parallel High-Performance Processing

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369

Simulation results for different functions (AND, EQ, NEQ, OR) implementation in four dif‐ ferent sub-regions is shown in Figure 23. **XD** and **YD** are the input matrixes. Tuning matrix‐ es **VY0÷VY3** have different values in sub-regions. Output matrix **VF** is concatenation of sub-

ands **A1** and **B1**

region functions.

**Figure 21.** Formulas for simulation of OPR MFLD-2 with MathCAD

Design and Modeling of Optoelectronic Photocurrent Reconfigurable (OPR) Multifunctional Logic Devices (MFLD) as the Universal Circuitry Basis for Advanced Parallel High-Performance Processing http://dx.doi.org/10.5772/54540 369

Formulas for simulation processing with MathCAD are shown in Figure 21. At first, input two 2D operands **A1** and **B1** and its weighted sum **SIAB** are formed. The coefficient and threshold t0= 10 because the current in the OPR MFLD-2 circuit is 10μA. Contrast comple‐ mentary images are matrixes **AN1** and **BN1**. After threshold processing by current compara‐ tors the direct matrixes **T1SIAB**, **T2SIAB**, **T3SIAB** and matrixes **TN1SIAB**, **TN2SIAB**, **TN3SIAB** of complementary images are formed. Four picture tuning operand **NY0 ÷NY3** are formed with tuning vector signals ny0÷ny3. Four logical members **SY0÷SY3** are formed using simultaneous threshold and state decoding operations. The sum of those members is the output matrix function **NF**. All operands dimension is 64x64 elements. All images of

above mentioned matrixes and some output functions are shown in Figure 22.

368 Optoelectronics - Advanced Materials and Devices

**Figure 21.** Formulas for simulation of OPR MFLD-2 with MathCAD


**Figure 22.** The simulation results of the OPR MFLD-2 with MathCAD for single-cycle high-speed computation of con‐ tinuous logic operations and / or fuzzy logic for membership functions. In the bottom row the functions realization MAX/OR, MIN/AND, EQ/NXOR, (*A*¯ ⋅ *B*) over the two graphs presented in the form of membership functions of oper‐ ands **A1** and **B1**

Simulation results for different functions (AND, EQ, NEQ, OR) implementation in four dif‐ ferent sub-regions is shown in Figure 23. **XD** and **YD** are the input matrixes. Tuning matrix‐ es **VY0÷VY3** have different values in sub-regions. Output matrix **VF** is concatenation of subregion functions.

**3. Conclusions**

logic operations/sec.

**Author details**

ment "Ukraine", Ukraine

112(7), 274-282.

**References**

We have developed two version of OPR MFLD which realizes the universal binary logic on optical signals. They have subpixel configuration of 2x2 elements, consist of a small amount of photodiodes (4) and transistors (18), have low power consumption <1-5mW, high produc‐ tivity and realize the basic set of operations of continuous logic with time pulse representa‐ tion of processed signals. Modeling of such cells with OrCad is made. It is confirmed that all set of possible functions will be realized with such MFLD by a simple photo tuning. Such cells for OPR MFLD are integrated into array of 32х32 allow reaching productivity 1012 CL-

Design and Modeling of Optoelectronic Photocurrent Reconfigurable (OPR) Multifunctional Logic Devices (MFLD) as

the Universal Circuitry Basis for Advanced Parallel High-Performance Processing

http://dx.doi.org/10.5772/54540

371

Vladimir G. Krasilenko1\*, Aleksandr I. Nikolskyy2\* and Alexander A. Lazarev2

1 Vinnitsa Social Economy Institute of Open International University of Human Develop‐

[1] Semiconductor Industry Association. (2001). The international Technology Roadmap

[2] Fey, D. (2001). Architecture and technologies for an optoelectronic VLSI. *Optik*,

[3] Li, G, Huang, D, Yucetukk, E, Marchand, P, Esener, J, Ozguz, S, & Liu, Y. (2002). There- Dimensional Optoelectronic Stacked Processor by use of Free-Spase Optical

[5] Masahiko, M, & Toyohiko, Y. (1997). Optical learning neural networks with two di‐

[6] Berger, C, Collings, N, & Gehriger, D. (1997). Recurrent Optical Neural Network for

Interconnection and Three-Dimensional VLSI Chip Stacks. *Applied optics.*, 41.

[4] Honeywell Technology Center. http://htchoneywell.com/photonics.

the Study of Pattern Dynamics. *Proc. SPIE.*, 3402, 233-244.

mensional structures. *Proc. SPIE.*, 3402, 226-232.

\*Address all correspondence to: krasilenko@mail.ru,fortuna888@i.ua

2 Vinnitsa National Technical University, Ukraine

for Semiconductors San Jose, USA.

**Figure 23.** The simulation results for sub-region function AND, EQ, NEQ, OR implementation

Let's demonstrate the possibilities for image processing with such devices. An example of contour extraction (**NF**) when processing the first input operand image A1 and its shifted copy **AES1** as the second operand is shown in figure 24. In figure 24: **NY0, NY1, NY2, NY3** – tuning matrixes for that operation; **NF** – the output image.

**Figure 24.** Simulation results of the OPR MFLD-2 with MathCAD for contour extraction

Design and Modeling of Optoelectronic Photocurrent Reconfigurable (OPR) Multifunctional Logic Devices (MFLD) as the Universal Circuitry Basis for Advanced Parallel High-Performance Processing http://dx.doi.org/10.5772/54540 371
