**3. Computer Simulation**

Input

*Packet*

**2.4. Operation Overview of Buffering**

**Figure 7.** Configuration of the FDL buffer.

First bit Input

C1 C2

'Store' signals #1

#2 #3

#2

1

**Figure 8.** Timing chart example of a module of the buffer.

1

2

Discard

'Forward' signal

FDLs in buffer #1

Output

'Store' signal

'Forward' signal

380 Optoelectronics - Advanced Materials and Devices

1x2 switch #*M*

FDL #1

FDL #2

On

Off

Off

On

On

#1 #2 #*M* #*M*+1

An example of timing chart for buffering process of a module is shown in Fig. 8.

Off

1x2 switch #2

switch

1x2 switch #1 Coupler #1

1 2 3 4 5b

*T*FIFO *T*FIFO *T*FIFO *T*FIFO

3

2 3

3

time

4

FDL #*M*

*T*FIFO

*T*FIFO

1 x (*M*+1) Discard

Output

Coupler #2

5a

5a

5b 4

*T*FIFO

Coupler #*M*

*T*FIFO

Two kinds of characteristics such as packet loss rate (PLR) and average delay time are inves‐ tigated by computer simulation. We assume in the simulation that packets arrive randomly and have variable lengths from *L* min=10 to *L* max=150 bytes. We define load at input port by the ratio of the packet existence length to a unit length. For simplicity, operation speed of the composed devices, such as switching speed of some spatial switches and flip-flops, rise time of logic gates, are assumed to be much faster than bit-rate of arriving packets. There‐ fore, bit-rate is not specified in our simulation.

#### **3.1. Packet Loss Rate**

The PLR is verified with changing the number of FDLs *M*, length of each FDL *L*, number of input *N*, and the load. Because of a finite number of FDLs in the buffer system, overflow may occur when the load exceeds the capacity of the buffer, resulting in rejection of the overflowed packets. Even if the load is less than the capacity, collision of packets may occur when packets forwarded by some modules are simultaneously coming into the following combiner as shown in Fig.1. Therefore in the simulation, the overflow and the collision are both treated as loss of packet.

Figure 9 shows the PLR as a function of the load at module #1 with the number of FDLs *M* as a parameter. The number of modules is *N*=2. The load of the module #2 is set to 0.5. The length of each FDL is *L*=*L* max. It is found that the PLR increases with load at module #1. Moreover, the PLR decreases when *M* increases.

Figure 10 shows the PLR as a function of the load at module #1 with the length of FDLs *L* as a parameter. The number of modules is *N*=2. The load of the module #2 is set to 0.5. The number of FDLs is *M*=10. It is found that the PLR increases both with load at module #1 and *L*. This is because incoming packets are separately stored in different FDLs, resulting in many FDLs are occupied with unused space remained. When *L* becomes long, the duration of occupation becomes long, and then it takes longer time to get out from the buffer. There‐ fore, it may cause the increase of packet loss because of the occupied FDLs.

Loads of modules other than #1 are all set to 0.3. It is found that the PLR increases with

All-Optical Autonomous First-in–First-out Buffer Managed with Carrier Sensing of Output Packets

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0 0.1 0.2 0.3 0.4 0.5 Load at module #1

0 0.1 0.2 0.3 0.4 0.5 Load at module #1

Figure 13 shows the breakdown of such numbers as input, output, discarded and broken packet in (a) module #1 and (b) module #2. Parameters are set to as follows; the number of modules is *N*=2, the number of FDLs is *M*=30, the length of each FDL is *L*=*L* max, the load of module #1 is changed, and that of module #2 is 0.5 fixed. It is found from Fig. 13(a) that the number of output packets saturates up to 70 when the load at module #1 exceeds 0.3. This is because it starts overflow at that point, namely the number of discarded packets increases in proportion to the input. As a result, the PLR also increases. In case of module #2 shown in Fig. 13(b) that the fixed number of input initially exceeds its overflow limit, and so the num‐

Load at module #2 = 0.5

0.3

*N*=2

*N*=3

*N*=5

0

0

0.1

0.2

0.3

Packet loss rate

0.4

0.5

0.1

0.2

0.3

Packet loss rate

**Figure 11.** PLR with parameter load at module #2.

**Figure 12.** PLR with parameter *N*.

0.4

0.5

load at module #1 and *N*.

**Figure 9.** PLR with parameter *M*.

**Figure 10.** PLR with parameter *L*.

Figure 11 shows the PLR as a function of the load at module #1 with the load at module #2 as a parameter. The number of modules is *N*=2. The number of FDLs is *M*=30. The length of each FDL is *L*=*L* max. It is found that the PLR increases with load at module #1 and #2.

Figure 12 shows the PLR as a function of the load at module #1 with the number of mod‐ ule *N* as a parameter. The number of FDLs is *M*=30. The length of each FDL is *L*=*L* max. Loads of modules other than #1 are all set to 0.3. It is found that the PLR increases with load at module #1 and *N*.

**Figure 11.** PLR with parameter load at module #2.

number of FDLs is *M*=10. It is found that the PLR increases both with load at module #1 and *L*. This is because incoming packets are separately stored in different FDLs, resulting in many FDLs are occupied with unused space remained. When *L* becomes long, the duration of occupation becomes long, and then it takes longer time to get out from the buffer. There‐

0 0.1 0.2 0.3 0.4 0.5

Load at module #1

0 0.1 0.2 0.3 0.4 0.5 Load at module #1

Figure 11 shows the PLR as a function of the load at module #1 with the load at module #2 as a parameter. The number of modules is *N*=2. The number of FDLs is *M*=30. The length of

Figure 12 shows the PLR as a function of the load at module #1 with the number of mod‐ ule *N* as a parameter. The number of FDLs is *M*=30. The length of each FDL is *L*=*L* max.

each FDL is *L*=*L* max. It is found that the PLR increases with load at module #1 and #2.

*L*=*L*max

*L*=3*L*max

*L*=5*L*max

*M*=50

*M*=30

*M*=10

fore, it may cause the increase of packet loss because of the occupied FDLs.

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Packet loss rate

Packet loss rate

382 Optoelectronics - Advanced Materials and Devices

**Figure 9.** PLR with parameter *M*.

**Figure 10.** PLR with parameter *L*.

**Figure 12.** PLR with parameter *N*.

Figure 13 shows the breakdown of such numbers as input, output, discarded and broken packet in (a) module #1 and (b) module #2. Parameters are set to as follows; the number of modules is *N*=2, the number of FDLs is *M*=30, the length of each FDL is *L*=*L* max, the load of module #1 is changed, and that of module #2 is 0.5 fixed. It is found from Fig. 13(a) that the number of output packets saturates up to 70 when the load at module #1 exceeds 0.3. This is because it starts overflow at that point, namely the number of discarded packets increases in proportion to the input. As a result, the PLR also increases. In case of module #2 shown in Fig. 13(b) that the fixed number of input initially exceeds its overflow limit, and so the num‐ ber of discarded packets increases up to a certain value. Then, the number of output de‐ creases to the same level as that of module #1. Therefore, this 2×1 buffer puts the identical output priority to the two modules.

0.5. The length of each FDL is *L*=*L* max. It is found that the average delay increases with load

All-Optical Autonomous First-in–First-out Buffer Managed with Carrier Sensing of Output Packets

Figure 15 shows the average delay as a function of the load at module #1 with the length of each FDL *L* as a parameter. The number of modules is *N*=2. The load of the module #2 is set to 0.5. The number of FDLs is *M*=10. It is found that the average delay increases

> 0 0.1 0.2 0.3 0.4 0.5 Load at module #1

> > *L*=5*L*max

*L*=3*L*max

*L*=*L*max

0 0.1 0.2 0.3 0.4 0.5 Load at module #1

Figure 16 shows distribution and moving average indicated by dots and solid curves, re‐ spectively, of delay time as a function of packet arrival time to each module with loads as parameters. The load of the module #1 is changed between 0.3, 0.5, and 0.7. The load of the

module #2 is set to 0.5. The number of modules is *N*=2. The number of FDLs is *M*=30.

*M*=10

*M*=30

*M*=50

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0 1,000 2,000 3,000 4,000 5,000 6,000 7,000 8,000 9,000 10,000 11,000 12,000

0 1,000 2,000 3,000 4,000 5,000 6,000 7,000 8,000 9,000 10,000 11,000 12,000

Average delay [byte]

Average delay [byte]

at module #1 and *M*.

with load at module #1 and *L*.

**Figure 14.** Average delay with parameter *M*.

**Figure 15.** Average delay with parameter *L*.

**Figure 13.** Breakdown of such numbers as input, output, discarded, and broken packet in each module.

#### **3.2. Average Delay**

Packets stored and forwarded through the buffer have been experienced a certain amount of delay determined mainly by the load and parameters *M* and *L*. We examine the average de‐ lay time by computer simulation.

Figure 14 shows the average delay as a function of the load at module #1 with the number of FDLs *M* as a parameter. The number of modules is *N*=2. The load of the module #2 is set to 0.5. The length of each FDL is *L*=*L* max. It is found that the average delay increases with load at module #1 and *M*.

Figure 15 shows the average delay as a function of the load at module #1 with the length of each FDL *L* as a parameter. The number of modules is *N*=2. The load of the module #2 is set to 0.5. The number of FDLs is *M*=10. It is found that the average delay increases with load at module #1 and *L*.

**Figure 14.** Average delay with parameter *M*.

ber of discarded packets increases up to a certain value. Then, the number of output de‐ creases to the same level as that of module #1. Therefore, this 2×1 buffer puts the identical

**Figure 13.** Breakdown of such numbers as input, output, discarded, and broken packet in each module.

Packets stored and forwarded through the buffer have been experienced a certain amount of delay determined mainly by the load and parameters *M* and *L*. We examine the average de‐

Figure 14 shows the average delay as a function of the load at module #1 with the number of FDLs *M* as a parameter. The number of modules is *N*=2. The load of the module #2 is set to

output priority to the two modules.

384 Optoelectronics - Advanced Materials and Devices

**3.2. Average Delay**

lay time by computer simulation.

**Figure 15.** Average delay with parameter *L*.

Figure 16 shows distribution and moving average indicated by dots and solid curves, re‐ spectively, of delay time as a function of packet arrival time to each module with loads as parameters. The load of the module #1 is changed between 0.3, 0.5, and 0.7. The load of the module #2 is set to 0.5. The number of modules is *N*=2. The number of FDLs is *M*=30.

The length of each FDL is *L*=*L* max. It is found that the delay time shows linear increase with packet arrival time because of the growth of buffer occupation. Moreover, the delay time shows saturation where the buffer occupation comes up to a maximum capacity. In addi‐ tion, the heavily-loaded module, which corresponds to module #2 at Fig. 16(a) whereas

All-Optical Autonomous First-in–First-out Buffer Managed with Carrier Sensing of Output Packets

We have proposed an autonomous first-in-first-out buffer with capability of storing a single packet in each of FDLs. Characteristics of PLR and average delay have been investigated by numerical simulation. As a result, the PLR and the average delay have a trade-off relation at such parameters as number of FDL *M* and length of each FDL *L*. Therefore they should be determined by system demand. Smaller *M* and larger *L* can be options for implementing the system from viewpoints of footprint, power consumption, and avoid complicated control. Our future works include detailed investigation of buffering performance considering re‐ sponse time in switching and other constituent devices, and experimental verification.

, Yoshitomo Shiramizu2

1 Department of Optical Science and Technology, The University of Tokushima, Japan

2 Department of Information and Computer Sciences, Toyohashi University of Technology,

[1] Burmeister, E. F., Blumenthal, D. J., & Bowers, J. E. (2008, Mar). A comparisonof opti‐

[2] Hunter, D. K., Chia, M. C., & Andonovic, I. (1998, Dec). Buffering in optical packet

[3] Tucker, R. S., Ku, P., , C., & Chang-Hasnain, C. J. (2005, Dec). Slow-light optical buf‐ fers: Capabilities and fundamental limitations. *J. LightwaveTechnol.*, 23(12), 4046-4066.

[4] Baba, T. (2008, Aug). Slow light in photonic crystals. *Nature Photonics* [8], 465-473.

cal buffering technology. *Optical Switching and Networking*, 5(1), 10-18.

, Jiro Oda2

, Nobuo Goto1\* and

http://dx.doi.org/10.5772/51083

387

module #1 at (c), shows faster increase and saturation than another module.

**4. Conclusion**

**Author details**

Hiroki Kishikawa1

Japan

**References**

Shin-ichiro Yanagiya1

, Hirotaka Umegae1

\*Address all correspondence to: goto@opt.tokushima-u.ac.jp

switches. *J. Lightwave Technol.*, 16(12), 2081-2094.

**Figure 16.** Distribution of delay time at each module.

The length of each FDL is *L*=*L* max. It is found that the delay time shows linear increase with packet arrival time because of the growth of buffer occupation. Moreover, the delay time shows saturation where the buffer occupation comes up to a maximum capacity. In addi‐ tion, the heavily-loaded module, which corresponds to module #2 at Fig. 16(a) whereas module #1 at (c), shows faster increase and saturation than another module.
