**1. Introduction**

Along with rapid progress of optical fiber links in the physical layer of networks, optical processing in the control layer such as data links and internet layers is expected to realize photonic networks. Various kinds of architectures of optical routers and switches have been exploited. Optical buffering is one of the indispensable key technologies for avoiding packet collision in these network nodes.

Various optical buffering systems have been reported [1,2]. Most of them consist of optical fiber delay lines (FDLs). Although optical slow light can be a potential candidate to adjust short delay timing [3,4,5], FDLs are regarded to be most useful elements for packet buffer‐ ing. Basically, two kinds of architectures of buffers with FDLs have been considered. One is a feedforward architecture, consisting of parallel FDLs that have different lengths corre‐ sponding to desired delay times. A combination of input and output buffered switch [6] and multistage FDL buffer [7] were reported as feedforward architectures. The other is an archi‐ tecture consisting of feedback-looped FDLs. It potentially provides infinite delay time if waveform distortion caused by loss, noise, dispersion etc., is managed to be compensated. However, the FDLs can provide only a restricted function of a finite delay time as buffers because the optical packet cannot be read out during the propagation in the FDLs.

In most of the proposed architectures, electrical processing for scheduling and management has been employed [8-12]. Although flexible control including quality of service (QoS) can be realized using such a control method, simple autonomous control is preferable for simple and low-power consumption buffering.

© 2013 Kishikawa et al.; licensee InTech. This is an open access article distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. © 2013 Kishikawa et al.; licensee InTech. This is a paper distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

We have proposed an autonomous first-in-first-out (FIFO) buffer management system us‐ ing all-optical sensing of packets [13]. Each of FDLs in the reported system stores a single packet. In this chapter, we describe architecture and operation of the buffering system. The buffering performances such as packet loss rate (PLR) and delay time are evaluated by numerical simulation.

**2.2. Configuration of the Controller**

whether the buffer is now forwarding packets or not.

reserved for future enhancement of the buffering system.

*Buffering* C2

First bit (FB)

Last bit (LB)

First bit (FB)

Last bit (LB)

*Information From others*

**Figure 2.** Schematic diagram of the controller.

**Figure 3.** Configuration of controller A.

Figure 2 shows the schematic diagram of the controller composed of four components. Con‐ troller A creates timing clock C1 to be used to open the buffer for storing packets. Controller B creates 'store' signal which indicates the actually storing FDL in the buffer. Controller C creates another timing clock C2 to be used to forward the already stored packets. Controller D creates 'forward' signal and the buffering information to other modules which indicates

All-Optical Autonomous First-in–First-out Buffer Managed with Carrier Sensing of Output Packets

Figure 3 shows the configuration of controller A. Timing clock C1 corresponds to the extract‐ ed first bit of incoming packets. The extracted last bit is not used in this case. However, it is

Controller A Controller B

C1

'Store' signal

http://dx.doi.org/10.5772/51083

377

'Forward' signal

*Buffering Information To others*

C1

Not used.

Figure 4 shows the configuration of controller B. It autonomously generates 'store' signals by processing C1 and C2. The number of 'store' signals is *M*+1 where *M* corresponds to the number of FDLs in the buffer. In order to indicate actual storing position, none or only one of the 'store' signals becomes on-state. When C1 comes, position of on-state moves up from #1 to #(*M*+1), namely, initially all off-state turns to #1-on, then moves to #2-on, #3-on, and so

Controller C Controller D
