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fields produced are compensated by a corresponding charge of the semiconductor. Since the ideal dielectric does not conduct any current, the semiconductor Fermi level remains flats. +3!2!.\_z0\$!z\* /z.!z!\* %\*#z%\*z+),(%\*!z3%0\$z0\$!z,,(%! z\* z.!0! z"%!( /^z+z+)¥ pensate this bending and to reach the flatband situation (=0), a gate bias has to be applied. This bias will shift the C-V characteristics of the MOS capacitor. The flatband (RCdz/%010%+\*

*oxt fit it S*

<sup>=</sup> + +

*C*

The effective charge density at the interface Neff is obtained from a C-V measurement and

When the interface trap density is high (>1011 cm-2), the flatband biases for the opposite

\$!z,,(%! z#0!z%/z%/z0\$!z/1)z+"z0\$!z,+0!\*0%(z .+,z+2!.z0\$!z+4% !z+40\_z0\$!z"(0\* z2+(0¥

\$!z+4% !z,%0\*!z+..!/,+\* /z0+z0\$!z1)1(0! z\$.#!z0z0\$!z#0!z %2% ! z5z0\$!z,+¥

*G*

*oxt <sup>Q</sup> <sup>C</sup>*

In the ideal case, this charge equals to the space charge of the semiconductor with negative sign QG=-QSC cSd\_z3\$!.!/z 0\$!z/,!z\$.#!z+"z 0\$!z/!)%+\* 10+.z%/zz "1\*0%+\*z+"z 0\$!z/1.¥ "!z ,+0!\*0%(^z ((z 0\$!/!z +\*/% !.0%+\*/z(! z 0+z 0\$!z "+((+3%\*#z .!(0%+\*/\$%,z !03!!\*z 0\$!z ,¥ plied gate voltage and the surface potential. Figure 15 shows the work functions of various metals used as gate dielectric together with the energy position SiC valence and conduction

> ( ) *SC S G FB S oxt*

*C* 

*<sup>Q</sup> V V*

*oxt*

*VV V G oxt FB S* =++

*Q QQ*

*oxt*

<sup>0</sup> ( ) *<sup>S</sup>*

 

(14)

( )( ) *VH V accum depl V depl accum FB FB* (15)

(16)

*<sup>V</sup>* <sup>=</sup> (17)

(18)

is reached, when the flatband bias VFB is applied:

230 Physics and Technology of Silicon Carbide Devices

has the form:

*FB ms*

sweep directions are different. This difference id called hysteresis:

*V*

*Neff* =*Veff* ×*Coxt* = (*VFB* o*ms*).*Coxt* =*Qoxt* + *Q fit* + *Qit*(p*<sup>S</sup>* =0)

age VFBz\* z0\$!z,+0!\*0%(z0z0\$!z%z/1."!zS.

tential drop over the oxide

band edge.

Sanjeev Kumar Gupta, Jitendra Singh and Jamil Akhtar

CSIR-Central Electronics Engineering Research Institute (CEERI), Pilani, India
