4. Correlation between atomic structure and electrical properties of SiO2/SiC interface

Corresponding SiC-MOS capacitors were fabricated with the top aluminum electrode evaporated through a shadow mask after post oxidation annealing at 900ºC in argon ambient. Electrical properties, such as the interface state density (D) and fixed oxide charge density (Qx) of the SiO%SiC interface, were extracted from the high-frequency C-V characteristics of SiC capacitors. The Di, value was extracted with the Terman method, and the Q& was deduced from the flatband voltage (V%) shift that depends on the oxide thickness [21]. Figure 6 summarizes the changes in Da and V .. values. Since post-treatment, such as nitrogen and hydrogen incorporation, was not conducted in this experiment, high Dki over 1022 cm2eV14 was extracted at an energy level of E. - E = 0.36 eV. The high Di, value indicates degradation of the electrical properties of the SiO2/SiC interface, especially for thick thermal oxides. In addition, the positive V " shift in the C-V curves implies the existence of a negative fixed charge within the gate oxides. Assuming that the fixed charge is located at the SiO , SiC interface, the Q , of the SiC-MOS devices estimated from the thickness-V ,, slope was 2.3 x 1011 cm² for oxides thinner than 20 nm and 1.2 x 1012 cm² for thick oxides, meaning that the fixed charges also accumulated at the interface probably due to the suppressed outdiffusion of carbon impurities as dry oxidation progressed.

Figure 6. Summary of electrical properties of SiC-MOS capacitors fabricated by dry oxidation. Horizontal axis represents oxide thickness extracted from measured maximum capacitance. The Da and Q& were estimated using Terman method and Vt shift in C-V curves, respectively.

The correlation between electrical degradation and the atomic bonding feature of the SiO2/SiC interfaces raises the intrinsic problem of SiC oxidation. This is consistent with the common understanding of SiC-MOS devices, whereas our synchrotron XPS analysis excludes the several-nm-thick transition layer having excess carbon as a physical origin of the electrical degradation. Instead, we think that the electrical defects at the interface, such as Du and Q ~ are partly ascribed to the atomic scale roughness and imperfection identified with the intermediate oxide states in the Si 2p spectra. Moreover, considering the significant mobility reduction in SiC-MOSFETs, we should take into account the various forms of carbon interstitials forming local C-C dimers located on the SiC bulk side as a possible origin of the electrical defects [22]. Therefore, it is concluded that, for improving the performance of SiC- /! z
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Fundamental Aspects of Silicon Carbide Oxidation

http://dx.doi.org/10.5772/51514

243

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(000-1) C-face 4H-SiC substrates.


ides on SiC [17], these results seem to be quite reasonable.

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Figure 7. O 1s energy loss spectra for thermal oxides on (0001) Si-face and (000-1) C-face 4H-SiC substrates. The onset G>L@==P;AL9LAGF >JGEL@=N9D=F;=LG;GF<M;LAGF:9F<K :9F<?9H;9F:=<=L=JEAF=< >JGEL@==F=J?QDGKK0@=N9s lence band maximum of SiC substrates and the oxides was determined by the valence spectra taken from SiO2/SiC structures and a reference SiC surface [24]. Figure 8 represents measured and deconvoluted valence spectra obtained after 3-nm oxidation of the Si-face and C-face substrates, in which the valence band maximum of the thermal oxides was estimated by subtracting the reference SiC spectra ( ) from the measured SiO2/SiC spectra ( ) both for the Si- and C-face substrates (see
