**7. Phosphorus**

12 Physics and Technology of Silicon Carbide Devices

comes with less demanding handling requirements.

contribution to understanding the role of nitrogen.

**6.3. N implants and radicals**

implant can never be ruled out.

interface boundary.

**6.2. N**2**O and NH**<sup>3</sup>

breakdown voltage.

region of the oxide. Since we have shown that more nitrogen would increase the mobility even further, other nitridation methods could maximize its density while confining it to the

Ammonia (NH3) POA shows benefits as well in terms of *Dit* reduction close to the conduction band edge of 4H-SiC [39, 53, 133]. However, it yields unnecessary incorporation of nitrogen throughout the oxide, totalling a density ∼ 100 times larger than NO POA. This compromises the integrity and reliability of the gate dielectric, as evidenced by the lowering of the

Nitrous oxide (N2O) oxidation or POA also improves the properties of the oxide/semiconductor interface, but to a lesser extent than NO [12, 37, 70, 76, 81]. This is because it decomposes at high temperature into NO, O2, and N2. While the resulting NO incorporates nitrogen at the 4H-SiC/SiO2 interface, the larger fraction of background oxygen mitigates this greatly. Indeed, since incorporated N is unstable against the slow re-oxidation occurring in parallel, N2O POA yields about an order of magnitude less nitrogen than pure NO POA at similar process temperature. It reduces D*it* by about a factor of 2 close to E*c* and leads to a peak field-effect mobility of up to ≈ 25 cm2/V.s in 4H-SiC transistors, as indicated in Fig. 10. However, nitrous oxide is sometimes preferred over NO for safety reasons as it

Following the improvements induced by NO POA, other methods were developed to introduce N at the SiO2/SiC interface. Although they may be more involved, they can yield NO-like properties for oxide-based devices formed on 4H-SiC and bring their own

One such nitridation technique is implantation. N<sup>+</sup> ions can be inserted in the top semiconductor layer that will subsequently be consumed by thermal oxidation, yielding the presence of nitrogen at the interface. The amount of N atoms can be tuned by implantation dose and energy. Studies have revealed that similarly to NO POA, the higher the nitrogen density at the thermally-formed interface, the lower the *Dit*, and the higher the field-effect mobility [42, 91, 93]. In fact, Poggi *et al.* have reported about an order of magnitude reduction of electrically active defects close to the conduction band edge of 4H-SiC and a room temperature field-effect mobility of up to 42 cm2/V.s in lateral nFETs fabricated on the (0001) surface [94, 95], Fig. 10. While the progressive increase of *µFE* with N dose is consistent with the reduction of Coulomb scattering, Hall mobility measurements reveal that in devices with the higher nitrogen content, *µHall* decreases with temperature. This implies that, unlike for the NO process, another dominant scattering mechanism appears following high implant doses. This has been attributed to induced damages in SiC and residual N interstitials left within the semiconductor [16]. Also, note that the process temperature can be kept at or below 1100 ◦C following implantation, to avoid activation that would convert N atoms into donors in SiC. But activation of a minority of dopants in the tail end of the In 2009, about a decade after the introduction of NO annealing, Okamoto *et al.*, from the Nara Institute of Science and Technology in Japan, proposed another post-oxidation annealing technique that significantly reduces *Dit* at SiO2/4H-SiC interfaces. As mentioned in the previous section, implantation of nitrogen in SiC prior to oxidation has proved to be a beneficial nitridation technique. Hence, Prof. Yano and his group cleverly extended this logic to a screening method for various potential passivating species [87]. This is how phosphorus caught their attention as oxidation of P-implanted SiC also showed a lower density of electrically active defects than as-oxidized un-implanted interfaces. Following this discovery, they implemented a more gentle way to introduce P at the interface in order to avoid ion-induced damages and undesirable doping of the substrate, by flowing gas through a POCl3 bubbler during a high temperature post-oxidation anneal.

When performed at 1000 ◦C on SiO2, grown on the Si-face of 4H-SiC, POCl3 POA leads to <sup>a</sup> *Dit* below 10<sup>11</sup> cm<sup>−</sup>2eV<sup>−</sup><sup>1</sup> close to E*c*, or several times lower than following NO POA [88]. This is reflected in the efficiency of lateral nFETs as the peak value of the field-effect mobility almost doubles compared to NO POA to about 90 cm2/V.s. This has been correlated with the presence of phosphorus at the interface. Another proposed method to reach similar mobility values is exposing a thermal oxide to P2O5 extracted from a solid phosphosilicate glass (PSG) diffusion source [115]. Device properties following POCl3 or PSG POA are reported in Figs. 8(a), 8(b) & 10.

Note that from SIMS analysis, it is found that both POCl3 and PSG POA convert the dielectric into a phosphosilicate by yielding phosphorus throughout the gate. This compromises the reliability of the devices. Recently, forming a thin P-containing interfacial oxide, using POCl3 and O2, followed by dielectric deposition, was shown to reduce trapping by narrowing the phosphorus profile [11].

The benefits of phosphorus at SiO2/SiC interfaces represent a milestone for silicon carbide research; not only because of mobility improvements, but also because it shines light on the nature of passivation at the atomic level. Indeed, both N and P are among the group V elements of the periodic table, possessing similar chemistry due to their 5 valence electrons. For example, it has fueled the discussion of the role of sub-surface SiC doping in improving device characteristics [36]. But while the physics of N and P binding at interfaces is still being debated, we are one step closer to a more comprehensive understanding of post-oxidation annealing mechanisms.

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Tailoring Oxide/Silicon Carbide Interfaces: NO Annealing and Beyond

**8.1. Alternate dielectrics**

and reliability [38].

processing schemes [14].

The versatility added in device fabrication from using deposited oxides allows to explore a variety of deposition techniques, temperatures, and most importantly the ability to use gate materials other than SiO2. It is interesting to note that the reason for considering alternate dielectrics is to move away from thick thermal oxides to reach higher mobility, which is fundamentally different from the evolution of gate fabrication in silicon technology where the motivation comes from scaling and the need for physically thicker oxides at a given capacitance to maintain gate control while minimizing leakage, often at the expense of mobility [56, 131]. This has led to the development and integration of materials which possess a higher dielectric constant, or higher k, that are used in the new generations of Si electronics. Regardless of the dichotomy, it comes at a very opportune time for SiC device research which looks to take advantage of the acquired expertise in deposited gate dielectrics. Another factor to consider when using high-k oxides on a wide band gap material like SiC however, is the reduced band offsets between the semiconductor and the dielectric. The conduction band offset relative to 4H-SiC for example goes from ≈ 3 eV with a SiO2 gate to ≈ 1 eV with a HfO2 gate [1, 102]. This has implications in terms of leakage current and reliability as such small barriers promote tunneling of carriers into the insulator, even more so that SiC devices are expected to perform at high temperature, which exacerbates the issue [105]. So if HfO2 is to be considered as a gate material, a thin SiO interlayer is necessary to achieve reasonable leakage. Indeed, Afanas'ev *et al.* have demonstrated that such structures have good interface properties, without the need for nitridation, but that it comes at the expense of a maximum surface field of about 3 MV/cm in the semiconductor to ensure gate integrity, dangerously close to transistor minimum requirements [7]. Ultimately, a balancing act between SiO and HfO2 thicknesses yields a compromise between performance

But unlike Si technology, we are not aiming for the highest possible dielectric constant, so we can somewhat move away from this compromise as long as a quality dielectric can be obtained on SiC. A promising candidate in this respect is Al2O3; it has a dielectric constant close to 9 and a band gap only a few tens of eV narrower than SiO2, yielding a conduction band offset relative to 4H-SiC that is still above 2 eV. Most importantly, it does not possess the same dominating trap level as SiO2, so that high electron mobility can be achieved in n-channel devices. Indeed, peak field-effect mobility values measured at room temperature on the Si-face can exceed 100 cm2/V.s [60, 79]. A key observation is again that a thin thermal SiO or SiON layer is still required, not so much to reduce gate leakage but to increase efficiency by providing a progressive transition between the semiconductor and the deposited oxide. Since it acts as a passivating layer, it is no surprise that while it is needed, the thinner it is, the better, so that a good interface can be formed while reducing the impact of remote thermal oxide traps on channel transport properties. In practice, the stability of a high-k material on SiO has to be considered carefully to avoid intermixing of the atomic species during subsequent device fabrication steps. To mitigate this, a SiN barrier layer can be used between the thermal oxide and Al2O3, blocking Al diffusion to the interface [83], or the learning from Si technology can be extended to the use of low-temperature gate-last

**Figure 8.** (a) *Dit* reduction compared to as-oxidized films using NO POA or a phosphorus source. Adapted from Ref.[115]. (b) Transfer characteristics and extracted field-effect mobilities showing the efficiency of P. Adapted from Ref.[115].
