**8. Deposited oxides**

Considering all the efforts necessary to improve the interface, boasting that silicon carbide should be preferred over other wide band gap semiconductors because it can grow a stable thermal oxide may no longer be a valid argument. First, the dominating trap level close to the conduction band edge of 4H-SiC has been associated with slow near-interface defects most likely residing inside SiO2, possibly oxygen vacancies. Second, evidence is mounting that the oxidation process itself, which creates C-related defects at the oxide/semiconductor interface, also yields a transition region that extends within SiC, potentially affecting transport properties inside the inversion layer of transistors [10, 17, 19, 117].

In particular, it has been proposed by the group of Prof. Kimoto, from Kyoto University in Japan, that thermal oxidation results in the emission of C atoms from the interface towards the bulk of the semiconductor [61]. Indeed, deep level transient spectroscopy (DLTS) measurements reveal a strong similarity between the effects of thermal oxidation and the ones of C implantation in irradiated samples, as both processes yield the suppression of a level labeled *<sup>Z</sup>*1/2 thought to be associated with C vacancies in silicon carbide [69, 123]. A refined oxidation model including the kinetics of emitted atoms was then put forward by Prof. Hijikata's research group at Saitama University in Japan; it successfully models their in-situ ellipsometry observations of thermal oxide growth rate on silicon carbide in both the thin and thick film regimes [59].

Because of these drawbacks of thermal oxidation, it should not come as a surprise that using deposited oxides has yielded encouraging results. For example, chemical vapor deposition of a thin SiN buffer layer on the Si-face of 4H-SiC followed by SiO2 deposition and N2O annealing, has been reported to lower the *Dit* and increase the field-effect mobility to above 30 cm2/V.s in lateral n-channel devices [85]. This is an improvement in efficiency compared to gates formed thermally in N2O, highlighting the benefits of deposited dielectrics. In that particular case, thinning the SiN layer has also proven to be key as thick oxynitride films resulting from oxygen insertion can possess a high density of positive charges which lower mobility and move the threshold voltage to negative values.

#### **8.1. Alternate dielectrics**

14 Physics and Technology of Silicon Carbide Devices

As-oxidized

NO anneal

PSG anneal

**8. Deposited oxides**

thin and thick film regimes [59].

mobility and move the threshold voltage to negative values.

0.2 0.3 0.4 0.5 0.6 EC - E (eV)

**(a) (b)**

**Thermal SiO2 N vs P annealing**

100

80

60

2

**Figure 8.** (a) *Dit* reduction compared to as-oxidized films using NO POA or a phosphorus source. Adapted from Ref.[115]. (b)

Considering all the efforts necessary to improve the interface, boasting that silicon carbide should be preferred over other wide band gap semiconductors because it can grow a stable thermal oxide may no longer be a valid argument. First, the dominating trap level close to the conduction band edge of 4H-SiC has been associated with slow near-interface defects most likely residing inside SiO2, possibly oxygen vacancies. Second, evidence is mounting that the oxidation process itself, which creates C-related defects at the oxide/semiconductor interface, also yields a transition region that extends within SiC, potentially affecting

In particular, it has been proposed by the group of Prof. Kimoto, from Kyoto University in Japan, that thermal oxidation results in the emission of C atoms from the interface towards the bulk of the semiconductor [61]. Indeed, deep level transient spectroscopy (DLTS) measurements reveal a strong similarity between the effects of thermal oxidation and the ones of C implantation in irradiated samples, as both processes yield the suppression of a level labeled *<sup>Z</sup>*1/2 thought to be associated with C vacancies in silicon carbide [69, 123]. A refined oxidation model including the kinetics of emitted atoms was then put forward by Prof. Hijikata's research group at Saitama University in Japan; it successfully models their in-situ ellipsometry observations of thermal oxide growth rate on silicon carbide in both the

Because of these drawbacks of thermal oxidation, it should not come as a surprise that using deposited oxides has yielded encouraging results. For example, chemical vapor deposition of a thin SiN buffer layer on the Si-face of 4H-SiC followed by SiO2 deposition and N2O annealing, has been reported to lower the *Dit* and increase the field-effect mobility to above 30 cm2/V.s in lateral n-channel devices [85]. This is an improvement in efficiency compared to gates formed thermally in N2O, highlighting the benefits of deposited dielectrics. In that particular case, thinning the SiN layer has also proven to be key as thick oxynitride films resulting from oxygen insertion can possess a high density of positive charges which lower

Transfer characteristics and extracted field-effect mobilities showing the efficiency of P. Adapted from Ref.[115].

transport properties inside the inversion layer of transistors [10, 17, 19, 117].

V-1 s-1 )

40 FE mobility (cm

20

0 2 4 6 8 10 12 Gate bias (V)

PSG anneal

NO anneal

As-oxidized

Drain current (10-6 A)

10<sup>10</sup>

10<sup>11</sup>

10<sup>12</sup>

Dit (cm-2.eV-1)

10<sup>13</sup>

The versatility added in device fabrication from using deposited oxides allows to explore a variety of deposition techniques, temperatures, and most importantly the ability to use gate materials other than SiO2. It is interesting to note that the reason for considering alternate dielectrics is to move away from thick thermal oxides to reach higher mobility, which is fundamentally different from the evolution of gate fabrication in silicon technology where the motivation comes from scaling and the need for physically thicker oxides at a given capacitance to maintain gate control while minimizing leakage, often at the expense of mobility [56, 131]. This has led to the development and integration of materials which possess a higher dielectric constant, or higher k, that are used in the new generations of Si electronics. Regardless of the dichotomy, it comes at a very opportune time for SiC device research which looks to take advantage of the acquired expertise in deposited gate dielectrics.

Another factor to consider when using high-k oxides on a wide band gap material like SiC however, is the reduced band offsets between the semiconductor and the dielectric. The conduction band offset relative to 4H-SiC for example goes from ≈ 3 eV with a SiO2 gate to ≈ 1 eV with a HfO2 gate [1, 102]. This has implications in terms of leakage current and reliability as such small barriers promote tunneling of carriers into the insulator, even more so that SiC devices are expected to perform at high temperature, which exacerbates the issue [105]. So if HfO2 is to be considered as a gate material, a thin SiO interlayer is necessary to achieve reasonable leakage. Indeed, Afanas'ev *et al.* have demonstrated that such structures have good interface properties, without the need for nitridation, but that it comes at the expense of a maximum surface field of about 3 MV/cm in the semiconductor to ensure gate integrity, dangerously close to transistor minimum requirements [7]. Ultimately, a balancing act between SiO and HfO2 thicknesses yields a compromise between performance and reliability [38].

But unlike Si technology, we are not aiming for the highest possible dielectric constant, so we can somewhat move away from this compromise as long as a quality dielectric can be obtained on SiC. A promising candidate in this respect is Al2O3; it has a dielectric constant close to 9 and a band gap only a few tens of eV narrower than SiO2, yielding a conduction band offset relative to 4H-SiC that is still above 2 eV. Most importantly, it does not possess the same dominating trap level as SiO2, so that high electron mobility can be achieved in n-channel devices. Indeed, peak field-effect mobility values measured at room temperature on the Si-face can exceed 100 cm2/V.s [60, 79]. A key observation is again that a thin thermal SiO or SiON layer is still required, not so much to reduce gate leakage but to increase efficiency by providing a progressive transition between the semiconductor and the deposited oxide. Since it acts as a passivating layer, it is no surprise that while it is needed, the thinner it is, the better, so that a good interface can be formed while reducing the impact of remote thermal oxide traps on channel transport properties. In practice, the stability of a high-k material on SiO has to be considered carefully to avoid intermixing of the atomic species during subsequent device fabrication steps. To mitigate this, a SiN barrier layer can be used between the thermal oxide and Al2O3, blocking Al diffusion to the interface [83], or the learning from Si technology can be extended to the use of low-temperature gate-last processing schemes [14].
