7. Summary

+z2!.%"5z0\$%/z\$5,+0\$!/%/\_zz(.#!z/0!,z1\*\$%\*#z3/z%\*0!\*0%+\*((5z"+.)! z5z\$%#\$z0!),!.¥ 01.!z \*\*!(%\*#^z /z /\$+3\*z %\*z %#^z DEcd\_z 
z +/!.20%+\*z +"z 0\$!z Gw%cCCCDdz /1."!z \*¥ nealed at 1700ºC showed that the height of the step bunching ranged from 10 to 20 nm, 3\$%(!z0\$!z
z.+1#\$\*!//z3%0\$%\*z0\$!z0!..!z3/zC^DLz\*)^z"0!.z+4% 0%+\*\_zz/%)%(.z/0!,w0!.¥ race structure to the one observed in Fig. 12(a) is preserved on the oxide surface, except for the bumps around the step bunching (see Fig. 12(b)). However, the RMS roughness in the flat region that was originally a terrace remains unchanged (<0.19 nm). This result strongly

Figure 12. AFM images and cross-sectional profiles of (a) 4H-SiC(0001) surface after annealing at 1700ºC and (b) SiO2

Furthermore, as shown in Fig. 13, a cross-sectional TEM image of the sample shown in Fig. 12(b) also clearly indicates pronounced oxidation at the step bunching. On the other hand, SiO2/4H-SiC interface morphology is clearly more moderated than that of the SiO2 surface, implying that the step bunching at the oxide interface became smooth by oxidation. The maximum SiO2 thickness (~80 nm) was located facing the step, which is more than double 0\$0z+\*z0\$!z0!..!^z%\*!z0\$!z+4% 0%+\*z.!0%+\*z%/z+\*0.+((! z5z0\$!z)+1\*0z+"z+45#!\*z)+(!¥ cules diffused through the SiO2z(5!.\_z/0!,z! #!/z3%((z!+)!z.+1\* ! z!1/!z+"z0\$!z0\$%\*¥

suggests significantly enhanced oxidation at the step face.

246 Physics and Technology of Silicon Carbide Devices

surface formed on the sample shown in (a) by dry oxidation at 1100ºC for 12 h.

Figure 13. A cross-sectional TEM image of SiO2/SiC structure shown in Fig. 12(b).

We have investigated the fundamental aspects of SiC oxidation and SiO2u%z%\*0!."!/^z!¥ /,%0!z0\$!z(%0!.01.!z/! z+\*z
z+/!.20%+\*\_z3!z"+1\* z0\$0zz\*!.w,!."!0z%\*0!."!z +)%¥ nated by Si-O bonds is formed by dry oxidation of 4H-SiC(0001) substrates. However, atomic scale roughness and imperfection causing electrical degradation of SiC-MOS devices was found to be introduced as oxide thickness increases. We also pointed out the problems regarding oxide reliability originating from the gate leakage. It was found that, although negative fixed charges due to the interface defects enlarge the conduction band offset of SiC-MOS devices, small conduction band offset leading to increased gate leakage is an intrinsic feature, especially for the SiC(000-1) C-face substrates. We have also examined surface and %\*0!."!z)+.,\$+(+#5z+"z0\$!.)((5z#.+3\*z+4% !/z0+z(.%"5z0\$!z.!(0%+\*z!03!!\*z/0!,z1\*\$¥ %\*#z\* z+4% !z.!' +3\*^z
1(0%,(!w(5!.z/0!,/z/z3!((z/z/0!,z1\*\$%\*#z+\*z 0\$!z3"!.z/1.¥ face lead to oxide thickness fluctuation due to the difference in oxidation rate between the terrace and the step face. The bump-like structure of the SiO2 layer near the step bunching and the relatively thinner oxide on the terrace will cause a local electric field concentration, 3\$%\$z!\*\$\*!/z0\$!z#!\*!.0%+\*z+"z!(!0.%(z !"!0/z%\*z0\$!z+4% !\_z%\* %0%\*#z0\$0z\*z0+)%(¥ ly-flat surface needs to be formed before gate oxide formation.
