**9. Summary and conclusions**

16 Physics and Technology of Silicon Carbide Devices

In the previous Sections, we have shown that while moving away from a thermally-formed gate oxide improves transport properties in 4H-SiC devices, a thin SiO transition layer still brings a much-needed passivated interface. While this is also true for deposited dielectrics on Si, the remarkable difference is that the thinner the thermal oxide is, the better. The next logical step is therefore to avoid thermally-formed SiO entirely, circumventing the negative impact of oxidation-induced defects and near-interface traps. But how can this be done so

It all comes down to surface preparation of the semiconductor, which cannot simply end with a wet clean since atomic ordering and bonding are paramount. A common surface preparation technique that has been used prior to epitaxial deposition or graphene formation on SiC might provide part of the answer. Hydrogen exposure of the (0001) face of hexagonal SiC to high temperatures (e.g. 1350 ◦C) etches the surface, smoothing it and yielding atomic reconstruction [18, 101, 120, 126]. However, if a gate dielectric is deposited directly on it, there appears to be no reduction of the D*it* when compared to an HF-last surface, which, as expected, is even worse than a thermally formed interface, at least when looking at SiO2 deposition on 4H-SiC. But Shirasawa *et al.* observed on 6H-SiC that when high temperature H2 exposure is directly followed by N2 exposure at the same temperature, it results in an ordered surface terminated by a monolayer of SiN topped by a monolayer of SiO [118, 119]. These thin films have well defined band gaps, a sign of their electrical integrity, and are

that there is a clean transition between the SiC surface and the deposited oxide?

estimated to be stable without the existence of dangling bonds at the SiC surface.

silicon oxide, while still offering a clean transition to a deposited layer.

new approach

Our group at the Central Research Institute of Electronic Industry, located in Yokosuka, Japan, then speculated that such a technique could be applied to 4H-SiC in order to form an ideal seed layer for subsequent deposition [110, 111]. Indeed, this "nitrogen conditioning" process is expected to yield an interface saturated by N atoms which are highly localized within a monolayer, a very promising scenario since we know that maximizing nitrogen content at the interface while limiting its presence in the oxide is key. Moreover, the single oxide layer formed by Si-O-Si bridges bonded to the nitrogen provides the bare minimum

**Figure 9.** Schematic of the nitrogen conditioning technique for deposited oxides vs. conventional nitridation methods. On the right is the corresponding *Dit* from deposited SiO<sup>2</sup> on surfaces which were subjected to various treatments. Adapted from

**8.2. Surface conditioning**

conventional method

Refs. [110, 111].

In order to realize the full potential of SiC-based devices across the voltage range depicted in Fig. 1, the quality of the oxide/semiconductor interface must be improved. Figure 10 summarizes both mobility and *Dit* from thermal oxide gates following the various annealing processes described in this Chapter. Despite increasingly efficient POA processes from N2O, to NO, to phosphorus exposure, the wide band gap and complex oxidation process yield a large density of states that still limits the mobility in even the best oxide-based SiC transistors. While rigourous experiments have led to that conclusion, the trend depicted in Fig. 10 shows a clear dependence between carrier transport and interface states. It suggests that the significant increase in mobility compared to NO POA induced by PSG or POCl3 annealing is

**Figure 10.** Peak field-effect mobilities extracted from lateral MOSFETs fabricated on (0001) 4H-SiC using thermal oxides with various POAs and the corresponding *Dit* @ 0.2 eV from the conduction band. The plot suggests that Coulomb scattering is the dominant mechanism affecting carrier transport. Further reduction of the interface trap density will keep improving device efficiency. Data gathered from Refs. [12, 88, 94, 106, 108, 115, 130].

still hampered by trap-induced Coulomb scattering. Moreover, it is another indication that if *Dit* can be decreased further, the mobility could potentially reach values well above 100 cm2/V.s.

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One can then speculate whether the best properties will be obtained from passivating a defective thermally-formed SiO2/SiC interface or using alternate dielectrics like promising Al2O3 gate stacks that have demonstrated such high mobilities. Both of these top-down and bottom-up approaches come with their respective challenges going from process integration to device stability and reliability. Thermal oxide POA must optimize the density of passivating species while limiting their presence inside the oxide, indeed *Dit* is inversely proportional to the amount of nitrogen but the quantity of hole traps increases with it. As for alternate dielectrics, benefits could arise by moving away from pre- or post-deposition oxidation, using instead efficient surface preparation techniques.

If the steady progress made during the past couple decades is any indication, silicon carbide research, development, and technology, have a bright future ahead.
