6. Surface and interface morphology of thermally grown SiO2 dielectrics on 4H-SiC(0001)

Finally, surface and interface morphology of thermal oxides grown on 4H-SiC(0001) substrates was investigated using AFM and TEM [30]. Thermal oxidation of 4-off-angled 4H-SiC(0001) Si-face substrate with an n-type epilayer was carried out in dry O2 ambient at T100℃ for 12 hours. The root mean square (RMS) roughness of the as-grown surface was estimated to be 0.23 - 0.26 nm (see Fig. 10(a)), suggesting that it is an almost step-bunchingfree substrate. However, in some locations, step bunching was observed, and the RMS roughness of the area, including step bunching, was about 2.3 nm. For some samples, hightemperature annealing was performed in an inert ambient at 1700℃ to intentionally emphasize the step bunching prior to the dry oxidation.

As shown in Fig. 10(b), the RMS roughness value of the oxide surface was about 0.36 nm, which is slightly higher than that of the as-grown epilayer surface. In addition, it seems that steps on the oxide surface are more rounded than the initial surface. Figure 11 shows crosssectional TEM images of as-grown and oxidized samples. Single steps are observed at the SiO2/4H-SiC interface in contrast to multiple-layer steps for the initial epilayer surface. These findings indicate that the step-terrace structure of an epilayer is enormously transterred to the SiO2 surface, while the interface roughness decreases by smoothening step bunching. Since the oxidation rate for C-face 4H-SiC is much higher than that for Si-face, it is considered that the step edges will be rounded by enhanced oxidation and that the resulting oxide near the steps will be thicker due to a volume expansion from SiC to SiO2.

Figure 10. AFM images of (a) as-grown 4H-SiC(0001) epilayer surface and (b) SiO2 surface formed on sample shown in (a) by dry O₂ oxidation at 1100°C for 12 h.

Figure 11. Cross-sectional TEM images of (a) as-grown 4H-SiC(0001) epilayer surface and (b) SiQ₂/4H-SiC interface formed on sample shown in (a). The oxide thickness was about 35 nm.

+z2!.%"5z0\$%/z\$5,+0\$!/%/\_zz(.#!z/0!,z1\*\$%\*#z3/z%\*0!\*0%+\*((5z"+.)! z5z\$%#\$z0!),!.¥ 01.!z \*\*!(%\*#^z /z /\$+3\*z %\*z %#^z DEcd\_z 
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ner oxide on the terrace. The large oxide thickness fluctuation surely leads to the local !(!0.%z"%!( z+\*!\*0.0%+\*z.+1\* z0\$!z/0!,z1\*\$%\*#z 1.%\*#z0\$!z!(!0.%(z/0.!//%\*#\_z0\$1/z.!¥ /1(0%\*#z%\*zz,.!"!.!\*0%(z.!' +3\*^z\$!.!"+.!\_z3!z\*z+\*(1 !z0\$0z0\$!z/1."!z)+.,\$+(+¥ gy of the channel region before gate oxide formation is important for improving reliability

Fundamental Aspects of Silicon Carbide Oxidation

http://dx.doi.org/10.5772/51514

247

We have investigated the fundamental aspects of SiC oxidation and SiO2u%z%\*0!."!/^z!¥ /,%0!z0\$!z(%0!.01.!z/! z+\*z
z+/!.20%+\*\_z3!z"+1\* z0\$0zz\*!.w,!."!0z%\*0!."!z +)%¥ nated by Si-O bonds is formed by dry oxidation of 4H-SiC(0001) substrates. However, atomic scale roughness and imperfection causing electrical degradation of SiC-MOS devices was found to be introduced as oxide thickness increases. We also pointed out the problems regarding oxide reliability originating from the gate leakage. It was found that, although negative fixed charges due to the interface defects enlarge the conduction band offset of SiC-MOS devices, small conduction band offset leading to increased gate leakage is an intrinsic feature, especially for the SiC(000-1) C-face substrates. We have also examined surface and %\*0!."!z)+.,\$+(+#5z+"z0\$!.)((5z#.+3\*z+4% !/z0+z(.%"5z0\$!z.!(0%+\*z!03!!\*z/0!,z1\*\$¥ %\*#z\* z+4% !z.!' +3\*^z
1(0%,(!w(5!.z/0!,/z/z3!((z/z/0!,z1\*\$%\*#z+\*z 0\$!z3"!.z/1.¥ face lead to oxide thickness fluctuation due to the difference in oxidation rate between the terrace and the step face. The bump-like structure of the SiO2 layer near the step bunching and the relatively thinner oxide on the terrace will cause a local electric field concentration, 3\$%\$z!\*\$\*!/z0\$!z#!\*!.0%+\*z+"z!(!0.%(z !"!0/z%\*z0\$!z+4% !\_z%\* %0%\*#z0\$0z\*z0+)%(¥

We are grateful to Dr. Takashi Nakamura, Mr. Yuki Nakano, and Mr. Shuhei Mitani for their valuable comments and discussion. Synchrotron XPS experiments were performed at BL23SU in the SPring-8 with the approval of JAEA as Nanotechnology Support Project of the Ministry of Education, Culture, Sports, Science and Technology (MEXT). We also thank .^z1 !\*z!.+'z\* z.^z'%.z+/\$%#+!z "+.z 0\$!%.z//%/0\*!z "+.z/5\*\$.+0.+\*zz)!/¥

ly-flat surface needs to be formed before gate oxide formation.

and Takuji Hosoi

\*Address all correspondence to: watanabe@mls.eng.osaka-u.ac.jp

of SiC-MOS devices.

Acknowledgements

urements.

Author details

Heiji Watanabe\*

7. Summary

Figure 12. AFM images and cross-sectional profiles of (a) 4H-SiC(0001) surface after annealing at 1700ºC and (b) SiO2 surface formed on the sample shown in (a) by dry oxidation at 1100ºC for 12 h.

Figure 13. A cross-sectional TEM image of SiO2/SiC structure shown in Fig. 12(b).

Furthermore, as shown in Fig. 13, a cross-sectional TEM image of the sample shown in Fig. 12(b) also clearly indicates pronounced oxidation at the step bunching. On the other hand, SiO2/4H-SiC interface morphology is clearly more moderated than that of the SiO2 surface, implying that the step bunching at the oxide interface became smooth by oxidation. The maximum SiO2 thickness (~80 nm) was located facing the step, which is more than double 0\$0z+\*z0\$!z0!..!^z%\*!z0\$!z+4% 0%+\*z.!0%+\*z%/z+\*0.+((! z5z0\$!z)+1\*0z+"z+45#!\*z)+(!¥ cules diffused through the SiO2z(5!.\_z/0!,z! #!/z3%((z!+)!z.+1\* ! z!1/!z+"z0\$!z0\$%\*¥ ner oxide on the terrace. The large oxide thickness fluctuation surely leads to the local !(!0.%z"%!( z+\*!\*0.0%+\*z.+1\* z0\$!z/0!,z1\*\$%\*#z 1.%\*#z0\$!z!(!0.%(z/0.!//%\*#\_z0\$1/z.!¥ /1(0%\*#z%\*zz,.!"!.!\*0%(z.!' +3\*^z\$!.!"+.!\_z3!z\*z+\*(1 !z0\$0z0\$!z/1."!z)+.,\$+(+¥ gy of the channel region before gate oxide formation is important for improving reliability of SiC-MOS devices.
