1. Introduction

Silicon carbide (SiC) is an important material for fabricating high-power, high-temperature and high frequency devices [1]. The semi-insulating (SI) form of 4H-SiC is useful for making microwave devices [2fz!1/!z%0z\$!(,/z%\*z(+3!.%\*#z0\$!z/0.5z !2%!z,%0\*!/\_z0\$!.!5z%\*¥ creasing the maximum operating frequency of the device. Selective area ion implantation is regarded as an attractive doping method for fabricating MESFETs in bulk SI 4H-SiC [3–5] due to the ease of inter-device isolation without the loss of planarity.

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z!+)!/z2!.5z,.+)%/%\*#z\* % 0!z"+.z\$%#\$z,+3!.z)%.+¥ wave applications in commercial and military communications.

However, SiC MESFETs are not without trapping problems associated with both the surface and with the layers underlying the active channel, which inuence power performance 0\$.+1#\$z 0\$!z "+.)0%+\*z +"z -1/%/00%z \$.#!z %/0.%10%+\*/^z \$%/z ,./%0%z \$.#!z 0/z 0+z .!¥ strict the drain current and voltage excursions, thereby limiting the high-frequency power output [6, 7].

Over the past few years, the vanadium-doped semi-insulating SiC substrate has attracted much attention in explaining the deterioration of the SiC MESFET microwave performance. Recently, the concern has shifted more towards surface traps due to the introduction of \$%#\$w,1.%05z /!)%w%\*/1(0%\*#z /1/0.0!/\_z3\$%\$z \$2!z !(%)%\*0! z 0\$!z(.#!.z ,.0z +"z 0\$!z ,.+¥ lems associated with the substrate [8,9f^z\$!z,.!/!\*!z+"z/1."!z/00!/z%\*z0\$!z1\*#0! z\$\*¥ nel regions between drain and source terminals has modulated the depletion of the channel 1\* !.z 0\$!z !2%!z/1."!\_z\* z\$/z.!/1(0! z%\*z 0\$!z ".!-1!\*5z %/,!./%+\*z+"z 0\$!z 0.\*/+\* 1¥ tance (gm) and gate lag transient [10, 12]. These anomalies make the device characteristics much more complicated, and make some troubles in circuit design.

© 2013 Gassoumi and Maaref; licensee InTech. This is an open access article distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. © 2013 Gassoumi and Maaref; licensee InTech. This is a paper distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

perform the measurements on a device with a small gate area and in operating conditions. However, to the best of our knowledge, no work has been conducted using this technique "+.zGw%z
/^z1/!-1!\*0(5\_z%\*z0\$%/z/01 5z3!z\$2!z%\*2!/0%#0! z0\$!z+.%#%\*z+"z,./%0¥ ic effect in DC characteristics of 4H-SiC MESFETs with a gate length of 1µm by CDLTS.

Conductance Deep-Level Transient Spectroscopic Study of 4H-SiC MESFET and Traps

http://dx.doi.org/10.5772/51212

283

In this study, we have used an old but not yet reported technique to investigate the origin of non stationnarity in 4H-SiC MESFETs. This technique is called Current (or Conductance) Deep Level Transient Spectroscopy (CDLTS). Indeed this technique is more suitable for the

\$!zGw%z
/z/01 %! z%\*z0\$%/z3+.'z3!.!z.!(%6! z0zz!/!.\$z\* z!\$\*+(¥ ogy (TRT) in Orsay (France) using the same fabrication process for all the transistors. The epitaxial layer structures were prepared by CVD on semi-insulating substrates supplied by CREE. The layer stack consists of three layers: a P-type buffer layer with a thickness of 0.3 µm and a doping level of 1.1016 cm-3, an N-type active layer with 0.3-0.4 µm thickness and

µm and Nd = 1019 cm-3. The lift-off process for the fabrication of the device has already been described elsewhere [5]. The first step consists in reactive ion etching for the channel recess. An evaporation of Ti/Pt/Au stack is realized for the gate contact. The surface is passivated by a deposited oxide layer. The measurements presented in this work have been realized on short test transistors with a gate of 1µm and a gate width of 100 µm. For all the transistors

the source gate distance is 0.5 µm and the gate drain distance is 2 µm.

contact layer with a thickness and doping of 0.2

study of transistors than the classical capacitance DLTS for two main reasons.

Figure 3. Arrhenius plot for the deep levels observed in the 4H-SiC MESFET.

2. Experimental procedure

doping level Nd = 1-2.1017 cm-3, and an N+

Figure 1. a: Static output characteristics (IDS-VDS-VGS) at T=85K. The gate voltage is first increased from 0 to -10 V GH=FKQE:GDK9F<F=PL<=;J=9K=<>JGE2LG2;JGKKKQE:GDK :/9E=9K>A?MJ=9>GJ0'0@=<J9AF;MJs rent decrease is no present for the second set of curves

Figure 2. Conductance DLTS spectra for a 4H-SiC MESFET.

Then trapping effects due to the substrate deep levels can occur. On the other hand, it is well known that SiC / insulator interface presents high density of surface states. As an example, when using a SiO2 passivation, a high interface state density (in the 1011 to 1012 cm-2 range) between SiO2 and SiC is still present. Consequently, the second hypothesis is consistent with the well known remaining passivation problem for SiC devices. Understanding the nature of the surface states in MESFETs could be a key to solve the problems. However, only a few works were reported on this topic. Conductance Deep Level Transient Spectroscopy cd\_z/z,%0\*!z\_z%/z\*z!""%%!\*0z0++(z0+z+0%\*z%\*"+.)0%+\*z+10z0.,/z%\*z/!)%¥ conductors, such as the activation energy, the capture cross section and the density of traps (in the case of Capacitance DLTS). The advantage of CDLTS over DLTS is the possibility to perform the measurements on a device with a small gate area and in operating conditions. However, to the best of our knowledge, no work has been conducted using this technique "+.zGw%z
/^z1/!-1!\*0(5\_z%\*z0\$%/z/01 5z3!z\$2!z%\*2!/0%#0! z0\$!z+.%#%\*z+"z,./%0¥ ic effect in DC characteristics of 4H-SiC MESFETs with a gate length of 1µm by CDLTS.

In this study, we have used an old but not yet reported technique to investigate the origin of non stationnarity in 4H-SiC MESFETs. This technique is called Current (or Conductance) Deep Level Transient Spectroscopy (CDLTS). Indeed this technique is more suitable for the study of transistors than the classical capacitance DLTS for two main reasons.

Figure 3. Arrhenius plot for the deep levels observed in the 4H-SiC MESFET.
