1. Introduction

[36] Afanasev, V. V., Bassler, M., Pensl, G., & Shulz, M. (1997). Intrinsic SiC/SiO2 Interface

[37] Knaup, J. M., Deák, P., Frauenheim, Th., Gari, A., Hajnal, Z., & Choyke, W. J. (2005). Theoretical study of the mechanism of dry oxidation of 4H-SiC. *Phys. Rev. B*, 71, pp. 235321-1-9, Defects in SiO2 as the possible origin of near interface traps in the SiC-

[38] Devynck, F., Alkauskas, A., Broqvist, P., & Pasquarello, A. (2011). Defect levels of carbon-related defects at the SiC/SiO2 interface from hybrid functionals. *Phys. Rev. B*, KF\_z,,^zDLHFDLwDwDD\_z\$.#!z0.\*/%0%+\*z(!2!(/z+"z.+\*w\_z+45#!\*w\_z\* z\$5 .+#!\*w.!(0¥ ed defects at the SiC/SiO2 interface through hybrid functionals, ibid, 84, 235320-1-18.

ic resonance study of performance limiting defects in SiC metal oxide semiconductor

[40] Shen, X., & Pantelides, S. T. (2011). Identification of a major cause of endemically poor mobilities SiC/SiO2 structures. *Appl. Phys. Lett.*, 98, 0535071-1-0535071-3.

[41] %&%'0\_z^\_z#1\$%\_z^\_z\z+/\$% \_z^zcECDDd^z\$!+.!0%(z/01 %!/z"+.z%z\* zz!)%/¥

[42] Hijikata, Y., Yaguchi, H., Yoshikawa, M., & Yoshida, S. (2001). Composition analysis of SiO2/SiC interfaces by electron spectroscopic measurements using slope-shaped

[43] %5+/\$%\_z^\_z\z%)+0+\_z^zcECCLd^z! 10%+\*z+"z!!,z!2!(/z\* z ),.+2!)!\*0z+"z.¥ rier Lifetime in n-Type 4H-SiC by Thermal Oxidation. *Appl. Phys. Express*, 2, pp.

[44] Storasta, L., Tsuchida, H., & Miyazawa, T. (2008). Enhanced annealing of the Z1/2 !¥

[45] Hiyoshi, T., & Kimoto, T. (2009). Elimination of the Major Deep Levels in n- and p-Type 4H-SiC by Two-Step Thermal Treatment. *Appl. Phys. Express*, 2,

[46] Kawahara, K., Suda, J., & Kimoto, T. (2012). Analytical model for reduction of deep

[47] Yamagata, H., Yagi, S., Hijikata, Y., & Yaguchi, H. (2012). Micro-Photoluminescence study on the influence of oxidation on stacking faults in 4H-SiC epilayers. *Appl. Phys.*

levels in SiC by thermal oxidation. *J. Appl. Phys.*, 111, 053710-1-053710-9.

sion into SiC layer during oxidation. *Mater. Sci. Forum*, 679-680, 429-432.

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SiO2 system: A systematic theoretical study, ibid, 72, 115323-1-9.

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field effect transistors. *J. Appl. Phys.*, 109, 014506-1-014506-12.

fect in 4H-SiC epilayers. *J. Appl. Phys.*, 103, 013705-1-013705-7.

States. *Phys. stat. sol. (a)*, 162, 321-337.

206 Physics and Technology of Silicon Carbide Devices

oxide films. *Appl. Surf. Sci.*, 184, 161-166.

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Dielectrics are the materials that do not conduct current in the presence of an electric field. \$!z,,(%0%+\*/z+"z 0\$%/z)0!.%(z%\*z/!)%+\* 10+.z%\* 1/0.%!/z.!z2!.5z.+ z%\*z2.%+1/z¥ pacities. Nowadays, extensive research and development (R&D) are in progress to grow \$%#\$z-1(%05z\$%#\$w'z#0!z %!(!0.%/z+\*z/!)%+\* 10+./z/1."!^z,,(%0%+\*/z%\*(1 !z!40!\* ¥ ing the limit of transistor gate capacitance beyond that of ultra thin silicon dioxide (SiO2) and to improve the gate dielectric reliability in wide band gap semiconductor devices. SiO2 is one of the best gate dielectric, which is continuously investigated rigorously since long (%)!z'z "+.z/%(%+\*z/! z)!0(w+4% !w/!)%+\* 10+.z c
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+.!¥ over, SiC is the only material that can be thermally oxidized to grow high quality SiO2, which enables to fabricate the MOS structures. A large drawback of SiO2 is its low dielectric constant, which is about 2.5 times lower than that of SiC and also poorer interface properties at SiO2/SiC. This causes a proportionally large electric field enhancement in the dielectric +),.! z0+z0\$0z%\*z0\$!z/!)%+\* 10+.\_z3\$%\$z%/zz.!/+\*z3\$5z\*!3z %!(!0.%/z3%0\$z %!(!¥ tric constant at least similar to that of SiC and lower interface states densities are desired for !2%!z ,,(%0%+\*/^z\$!.!z\$2!z!!\*z "!3z/1!//"1(z\$%#\$w'z %!(!0.%/z%\*(1 %\*#z/%(%+\*z\*%¥ tride (Si3N4), Oxynitride, aluminum nitride (AlN), hafnium dioxide (HfO2), tin oxide (SnO2),

© 2013 Gupta et al.; licensee InTech. This is an open access article distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. © 2013 Gupta et al.; licensee InTech. This is a paper distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

cesium oxide (CeO2), titanium oxide (TiO2), tungsten oxide (WO3), aluminum oxide (Al2O3), lanthanum oxide (La2O3), gadolinium oxide and others have been attempted in SiC technology. This chapter covers the selection of gate dielectrics, their processing, interface properties, their electronic structure, flat band voltage shifts and electronic defects.

#### 2. Selection of gate dielectrics

Most of the gate dielectrics material fallows the trend of decrement in their bandgap energy, when the value of their dielectric constant goes towards higher end (high-k). Therefore, the band offset alignment at the interface of gate dielectric and SiC interfaces is an important issue while integrating a high-k gate dielectric in SiC-based devices because SiC belongs to the family of wide gap semiconductor (>3 eV). Figure 1 shows the tendency of bandgap energy as a function of dielectric constant. The bandgap energy of dielectric material has a direct correlation to the leakage current through the band edge offset. Wider bandgap energy means a better chance for a larger conduction or valence band offsets at the interface of semiconductor and the gate dielectric. Furthermore, the band gap energy of high-k oxides (5-6 eV) is modest as an insulator, which may result in large leakage current because of insufficient barrier height at interface. The value of low band offsets at the high-k/SiC interface may be overcome by introducing an ultrathin SiO2 interfacial layer in between dielectric and SiC layer (Mahapatra R., 2008). Figure 2 shows the energy band diagram of metal-gate dielectric-SiC structures as well as stack layers of HfOj/SiO/4H-SiC. In figure 2, HfO2 was considered as gate dielectric while 4H-SiC was the base substrate. In a situation when the theoretical calculations of energy band diagrams are not available, nor there are measured differences between insulator and SiC energy bands, the size of the bandgap allows for a rough evaluation of the probable usability of the gate dielectric. In ideal case, symmetrical offsets for electrons and holes of the order of 2 eV, the bandgap energy of the gate dielectric should be at least 7 eV. The mechanical and structural properties of ideal gate dielectrics are as important as its electrical performance. The most recommended form of the materials is mono-crystalline structures but those are often grown at very high temperatures and precise pressures. In case of passivation, when the dielectric material is considered to be deposited as the last processing step at low temperatures, the material should have an amorphous composition. This would prevent a possible current conduction through the grain boundaries of the polycrystalline material. Moreover, a lot of research is oriented towards nanocrystalline structures and application of those could provide materials with e.g. larger bandgap, modified by small grains dimension. Other mechanical teature like surface roughness, purity, or right stoichiometry of insulators implies that a good control over the deposition process and correct film uniformity is achieved. To eliminate the mechanical stress caused by device operation at high temperature, the thermal expansion coefficient and thermal conductivity of the dielectric and SiC should be similar. The insulator should also be hard, resistant to cracks and should not be influenced by the surrounding atmosphere.

Figure 1. Variation of bandgap energy of different dielectric materials as function of its dielectric constant

Figure 2. Energy band diagram of HfO2/4H-SiC and HfO2/SiO2/4H-SiC system

However, a significant higher interface state density and inferior electrical properties were found at the SiC/oxide interface because of the interface imperfections. It has been demonstrated by many researchers that a proper annealing of gate dielectrics can reduce the density of traps and passivate the defects level. The process parameters of annealing (temperature, ambient, time etc) can also be a key factor on interface properties. The incorporation of atomic nitrogen shows favorable effects on the structural stability of gate dielectric layers (Chen Q., 2008). At high temperature operation the quality of gate dielectric degrade as the result interface properties show the poor performance. Therefore, the understanding of proper band alignment and the thermal stability at the interface is critical for the application of high-k/SiC-base stacks for high temperature applications (Weng M-H, 2006). Another issue of interest is surface preparation techniques prior to dielectric deposition. There are standard process in Si technology is wet chemical etching in hydrofluridic acid (HF) to remove the native oxide and initial impurities. Unfortunately, this procedure does not provide much satisfactory outcome in the case of SiC as a base material. Many methods are incorporated to clean the SiC surface. The most common method is UV light cleaning, which has a sufficient energy to break carbon clusters that are present on the SiC surface.

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