8. The Metal Oxide Silicon Carbide (MOSiC) band diagram

#### 8.1. An ideal band diagram of MOSiC capacitor

In accord to the ideal case, the value of interface traps (Qit) should be zero. The relationship +"z/1."!z,+0!\*0%(z0+z0\$!z#0!z2+(0#!z\$2%\*#z%\*0!."!z0.,/z6!.+z%/z'\*+3\*z/z\*z% !(z
¥ SiC capacitor as shown in figure 14.

Figure 14. Flatband energy band diagram of an ideal MOSiC structure

An ideal MOS diode is defined as follows:

charge. Sodium ion is the dominant contaminant. The other ionic impurities like potassium may !z%\*0.+ 1! z 1.%\*#z\$!)%(w)!\$\*%(z,+(%/\$%\*#^z+.z)+%(!z\$.#!z(1(0%+\*z0\$!z)!/¥ urement temperature must be sufficient high so the charge to be mobile. Typically, the devices

"+.zz/1""%%!\*0(5z(+\*#z0%)!z%\*z+. !.z0+z .%"0z\$.#!z".+)z%\*0!."!^z\$!z)+%(!z\$.#!z\*z!z !¥

These are positive or negative charges, due to structural defects, oxidation-induced defects, metal impurities, or other defects caused by radiation or similar bond breaking processes (*e.g.*, hot electrons). The interface trapped charge is located at the SiC–SiO2 interface. Unlike the fixed \$.#!z+.z0.,,! z\$.#!\_z%\*0!."!z0.,,! z\$.#!z%/z%\*z!(!0.%(z+))1\*%0%+\*z3%0\$z0\$!z1\*¥ !.(5%\*#z%^z \*0!."!z0.,/z\*z!z\$.#! z+.z %/\$.#! \_z !,!\* %\*#z+\*z0\$!z/1."!z,+0!\*¥ tial.This charge type has been also called surface states, fast statesand interface states and so on.

5z 0\$!z +),.%/+\*z +"z)!/1.! z \$%#\$z ".!-1!\*5z ,%0\*!z3%0\$z z 0\$!+.!0%(z ,%¥

5z 0\$!z +),.%/+\*z +"z )!/1.! z (+3z ".!-1!\*5z ,%0\*!z 3%0\$z z 0\$!+.!0%(z ,%¥

5z 0\$!z +),.%/+\*z +"z )!/1.! z \$%#\$z ".!-1!\*5z ,%0\*!z 3%0\$z )!/1.! z (+3z ".!¥

1 1

 \*0!."!z0.,z\$\*#!z0\$!%.z\$.#!/z/0!z !,!\* %\*#z+\*z3\$!0\$!.z0\$!5z.!z"%((! z+.z!),05^z¥ !,0+.z%\*0!."!z0.,/z.!z\*!#0%2!z3\$!\*z"%((! \_z\* z\*!10.(z3\$!\*z!),05\_z3\$!.!/z +\*+.z%\*¥ terface traps are neutral when filled and positive when empty. Both types of interface traps

11 1 1 1

*qC C C C* ' \* \* " "" " ( + + " "" " ! ,! , )

8. The Metal Oxide Silicon Carbide (MOSiC) band diagram

*LF oxt HF oxt*

In accord to the ideal case, the value of interface traps (Qit) should be zero. The relationship +"z/1."!z,+0!\*0%(z0+z0\$!z#0!z2+(0#!z\$2%\*#z%\*0!."!z0.,/z6!.+z%/z'\*+3\*z/z\*z% !(z
¥

There are three main approaches to investigate the problem of interface state.

C. A gate bias, to produce an oxide field of around 106

. *Q VC mob FB oxt* (12)

V/cm is applied

(13)

are heated to 2000

1. -

2. -

3. -

C to 3000

228 Physics and Technology of Silicon Carbide Devices

7.5. Interface trap level density (Dit)

tance with no interface traps.

tance with no interface traps.

may exist, perhaps simultaneously in the same device.

*it*

*D*

8.1. An ideal band diagram of MOSiC capacitor

SiC capacitor as shown in figure 14.

quency capacitance.

termined from the flatband voltage shift, according to the equation:


#### 8.2. The real MOSiC capacitor

 \*z.!(\_z0\$!z+4% !/z+"z\*5z
z,%0+.z"!01.!/zz\*1)!.z+"z\$.#!/z"+.z!4),(!z"%4! z+4¥ ide charge, mobile charge, oxide trap charge and interface trap level density. There is also a non-zero difference between the gate metal and semiconductor work function. The electric fields produced are compensated by a corresponding charge of the semiconductor. Since the ideal dielectric does not conduct any current, the semiconductor Fermi level remains flats. +3!2!.\_z0\$!z\* /z.!z!\* %\*#z%\*z+),(%\*!z3%0\$z0\$!z,,(%! z\* z.!0! z"%!( /^z+z+)¥ pensate this bending and to reach the flatband situation (=0), a gate bias has to be applied. This bias will shift the C-V characteristics of the MOS capacitor. The flatband (RCdz/%010%+\* is reached, when the flatband bias VFB is applied:

$$\mathcal{V}\_{\text{FB}} = \boldsymbol{\wp}\_{\text{ms}} - \frac{\left. \mathcal{Q}\_{\text{out}} + \mathcal{Q}\_{\text{f}\text{f}} + \mathcal{Q}\_{\text{il}} (\boldsymbol{\wp}\_{\text{S}}) \right|\_{\boldsymbol{\wp}\_{\text{S}} = 0}}{\mathcal{C}\_{\text{out}}} \tag{14}$$

**SiO2** 

**EC (4H) 2.7**

**EV (for all polytypes) 6.0**

**EC (6H) 2.95**

**SiC**

**0.9** 

Materials and Processing for Gate Dielectrics on Silicon Carbide (SiC) Surface

**EC (15R) 3.0**

**EC (3C) 3.7**

http://dx.doi.org/10.5772/52553

231

**EV (9.0)**

CSIR-Central Electronics Engineering Research Institute (CEERI), Pilani, India

Figure 15. 3GJC>MF;LAGFKG>N9JAGMKE=L9DKMK=<9K?9L=LG?=L@=JOAL@L@==F=J?QHGKALAGF/AN9D=F;=9F<;GF<M;s

[1] Amy, F., Soukiassian, P., Hwu, Y., Brylinski, K., & , C. (1999). SiO2/6H-SiC (0001) 3x3 initial interface formation by Si overlayer oxidation,Applied Physics Letters, , 75(21),

[2] Afanasev, V. V., Bassler, M., Pensl, G., Schulz, M., & (1997, . (1997). Intrinsic SiC/SiO2

[3] Afanas'ev, V. V. ., Ciobanu, F., Dimitrijev, S., Pensl, G., & and, Stesmans. A. (2005). SiC/SiO2 Interface States: Properties and Models, Materials Science Forum, 483-485,

**EC** 

**Vacuum energy** 

Pt 5.30 Ag 4.20 Au 4.20 Ti 4.20 Cu 4.20 Cu 3.65 Al 3.20 Mg 2.45

Sanjeev Kumar Gupta, Jitendra Singh and Jamil Akhtar

Interface States. Physica Status Solidia), , 162, 321.

**Energy (eV)** 

**EFM** 

**0**

**3**

**6**

**9**

tion band edge

Author details

References

3360.

563.

The effective charge density at the interface Neff is obtained from a C-V measurement and has the form:

$$N\_{eff} = V\_{eff} \times C\_{\alpha \text{xt}} = -\left(V\_{FB} - \rho\_{ms}\right). \\ C\_{\alpha \text{xt}} = Q\_{\alpha \text{xt}} + Q\_{fit} + Q\_{it} (\psi\_S = 0).$$

When the interface trap density is high (>1011 cm-2), the flatband biases for the opposite sweep directions are different. This difference id called hysteresis:

$$
\Delta VH = V\_{FB}(\text{acuum} \to \text{depl}) - V\_{FB}(\text{depl} \to \text{accum}) \tag{15}
$$

\$!z,,(%! z#0!z%/z%/z0\$!z/1)z+"z0\$!z,+0!\*0%(z .+,z+2!.z0\$!z+4% !z+40\_z0\$!z"(0\* z2+(0¥ age VFBz\* z0\$!z,+0!\*0%(z0z0\$!z%z/1."!zS.

$$V\_G = V\_{out} + V\_{FB} + \psi\_S \tag{16}$$

\$!z+4% !z,%0\*!z+..!/,+\* /z0+z0\$!z1)1(0! z\$.#!z0z0\$!z#0!z %2% ! z5z0\$!z,+¥ tential drop over the oxide

$$\mathcal{C}\_{out} = \frac{\mathcal{Q}\_{\mathcal{G}}}{V\_{out}} \tag{17}$$

In the ideal case, this charge equals to the space charge of the semiconductor with negative sign QG=-QSC cSd\_z3\$!.!/z 0\$!z/,!z\$.#!z+"z 0\$!z/!)%+\* 10+.z%/zz "1\*0%+\*z+"z 0\$!z/1.¥ "!z ,+0!\*0%(^z ((z 0\$!/!z +\*/% !.0%+\*/z(! z 0+z 0\$!z "+((+3%\*#z .!(0%+\*/\$%,z !03!!\*z 0\$!z ,¥ plied gate voltage and the surface potential. Figure 15 shows the work functions of various metals used as gate dielectric together with the energy position SiC valence and conduction band edge.

$$\left(V\_G - V\_{FB} = -\frac{Q\_{S\mathcal{C}}\left(\nu\_S\right)}{\mathcal{C}\_{out}} + \nu\_S\right) \tag{18}$$

Figure 15. 3GJC>MF;LAGFKG>N9JAGMKE=L9DKMK=<9K?9L=LG?=L@=JOAL@L@==F=J?QHGKALAGF/AN9D=F;=9F<;GF<M;s tion band edge
