**2. Breakdown field and device efficiency**

2 Physics and Technology of Silicon Carbide Devices

to achieve optimum properties [109].

and high power applications.

to adopt the new technology.

annealing, and deposited dielectrics.

**Figure 1.** DC efficiency of SiC-based FETs relative to Si devices at given designed blocking voltages. While commercially available switches using NO-annealed thermal gate oxides have improved efficiency, one suggested route is the use of deposited oxides

yield. Demand and production costs have thus progressively driven down the price of the material, which has translated into cheaper and higher quality components for optoelectronic

*Efficiency* - While investment costs have diminished, SiC-based devices are still more expensive than their Si counterparts. Their efficiency is what can make them attractive in the long run. As illustrated in Fig. 1, the energy consumption of metal-oxide field-effect transistors (MOSFETs) can be orders of magnitude lower when using silicon carbide as a substrate to control high blocking voltages. Industries that would benefit from the widespread of such components include transportation, electricity distribution, grid coupling, high-performance computing, etc. Indeed, automakers have invested heavily in SiC research, targeting the implementation of SiC-based inverters in hybrid vehicles. To get an idea of how single device consumption will translate into system efficiency, let's take the example of photovoltaic (PV) power converters. PV inverters are used to convert the DC current from solar sources to feed it to the AC grid. They are made of power diodes and switches. A typical residential system has a nominal power of 5 kW at 400 V AC. Such Si-based converters can operate at over 95% efficiency but replacing Si components by commercially available SiC Schottky diodes and power MOSFETs can cut the loss by about 50%, yielding a saving of the order of \$100 a year per household [22, 23]. Moreover, they can operate at higher temperature, so that limited cooling and volume requirements go in favor of system prices which can indeed prove beneficial over the years for the consumer choosing

Further improvements in SiC device efficiency will make the case even stronger. Among the key building blocks at the device level is the oxide/semiconductor interface. Figure 1 highlights how it affects consumption, especially at low biases. In this Chapter, we will derive important parameters defining SiC devices from physical properties, and discuss the role and formation of the oxide/semiconductor interface, covering thermal oxides, post-oxidation Let us compare vertical double-implanted MOSFETs (DMOSFETs) designed to control the same bias, one Si-based, the other SiC-based, as shown in Fig. 2(b), using the constants of Fig. 2(a). The key differences between the two materials can be traced back to the Si-Si bond and the Si-C bond, respectively. The stronger interaction between silicon and carbon atoms is evidenced by the shorter bond length of 1.89 Å when compared to 2.35 Å for Si-Si. The proximity of atoms in SiC yield a more pronounced splitting of bonding and antibonding levels, which translates into a wider band gap in the periodic crystalline structures. The diatomic base of silicon carbide also explains the better thermal conductivity of the material because its vibration modes, i.e. phonons, are more energetic on average, as reflected in the Debye temperature. Ultimately, it is the phonon distribution that explains the higher critical field of silicon carbide, *ξc*, that can be used to derive a key parameter impacting device efficiency in high power electronics, the drift component of the specific ON resistance.

The breakdown field of a material is indeed not directly related to its band gap *Eg*. While, to first order, the free carriers need to reach a kinetic energy of at least 3/2 *Eg* to induce the cascading impact ionization phenomenon, called avalanche, that multiplies the number of carriers and therefore the conductivity, the limiting factor in the bulk is phonon coupling [84, 86]. If the net velocity of carriers *v*¯, proportional to the current, is smaller than or equal to the thermal velocity *vth* <sup>=</sup> <sup>3</sup>*kbT*/*m*∗, the electron-phonon system is in equilibrium because of the ability of phonons to thermalize the carriers. In that regime, phonon scattering damps the energy gain of free carriers whose distribution in the bands can be visualized as a Fermi sphere slightly shifted in the direction of the electric field. However, if the field increases and reaches *ξc*, the rate at which carriers gain energy becomes too high to allow equilibrium with the lattice vibrations. Hot carriers then achieve phonon runaway. Their motion is no longer damped and they can accelerate freely from *vth* to the critical speed *vc* <sup>≈</sup> <sup>3</sup>*Eg*/*m*<sup>∗</sup> allowing the avalanche process to start. It is worth noting here that in thin films, an additional constraint comes from the time the carriers take to accelerate to *vc*, so that *ξ<sup>c</sup>* can become larger than the bulk value, as illustrated in Fig. 3(a).


**(a) (b)**

**Figure 2.** (a) Properties of 4H-SiC and Si with 1015-10<sup>16</sup> cm−<sup>2</sup> doping at 300 K [30, 65, 66, 84, 121]. (b) Vertical power DMOSFET.

**Figure 3.** (a) Hot carrier velocity saturation and dielectric breakdown [105]. (b) Field distribution in a one-sided reverse-biased PN junction.

The critical field *ξ<sup>c</sup>* of a semiconductor, can be used to design the most efficient device for a given blocking voltage *Vd*. When a DMOSFET is in the OFF state, the positive bias applied to the drain is entirely dropped in the N<sup>−</sup> drift region [84, 124]. Indeed, together with the P base, it forms a reverse-biased one-sided PN junction, represented in Fig. 3(b). For a large blocking voltage, *Vd Eg*/*q*, the extent of the depletion region on the lowly-doped side in the step-junction approximation is

$$\propto\_d = \sqrt{\frac{2\varepsilon\_s V\_d}{qN\_d}}\tag{1}$$

10.5772/54396

http://dx.doi.org/10.5772/54396

(5)

255

(6)

(7)

(8)

**SiO2/SiC**

*D***it**

*R*∗ *dr R*∗ *dr*

for a given ON current [15].

is then

(4)


<sup>=</sup> *<sup>N</sup>*<sup>∗</sup> *<sup>d</sup> µdr x*∗ *d*

 *Si*

in this Chapter. It can be calculated using the long channel approximation as

*Rch* <sup>=</sup> *Vd Isat*

*Rtot* = *R*<sup>∗</sup>

Si-Si

**Figure 4.** Schematic of the density of interface traps at the SiO2/SiC interface.

*x*∗ *d N*<sup>∗</sup> *<sup>d</sup> µdr*

where *µdr* is the drift mobility in the bulk of the semiconductor. Plugging the respective constants of the bulk semiconductors into Eq. (5) implies that in ideal devices the energy dissipated using 4H-SiC would be several hundred times lower compared to the Si equivalent

In a real device, however, there are other components to the resistance such as the contact resistance and the channel resistance. Here we will discuss only the channel specific resistance which contains the contribution from the oxide/semiconductor interface of interest

where *L* is the channel length, *P* is the channel width, or the square cell pitch, *µch* is the inversion mobility, and *n* is the minority carrier density [9]. The total specific ON resistance

*dr* <sup>+</sup> *Rch* <sup>=</sup> *<sup>x</sup>*<sup>∗</sup>

which has the following dependence on designed blocking voltage according to Eqs. (3) &

*d µdr<sup>s</sup>ξ*<sup>3</sup> *c* + *LP nqµch*

Si C Ox y

*Rtot* <sup>=</sup> <sup>4</sup>*V*<sup>2</sup>

**Electron energy (eV)** 2.8

 *SiC*

*<sup>P</sup>*<sup>2</sup> <sup>=</sup> *LP nqµch*

> *d N*<sup>∗</sup> *<sup>d</sup> qµdr*

+ *LP nqµch*

Si-SI

<sup>=</sup> *<sup>µ</sup>dr <sup>s</sup> <sup>ξ</sup>*<sup>3</sup>

*c µdr <sup>s</sup> ξ*<sup>3</sup> *c* |*Si* |*SiC*

Tailoring Oxide/Silicon Carbide Interfaces: NO Annealing and Beyond

where *Nd* is the density of donor atoms in the drift region, *<sup>s</sup>* is the permittivity of the semiconductor, and *q* is the elementary charge. The peak electric field, at the boundary, being

$$
\zeta\_{\text{max}} = 2 \frac{V\_d}{\varkappa\_d} = \sqrt{\frac{2qN\_d V\_d}{\varepsilon\_s}} \tag{2}
$$

The highest doping concentration that can sustain *Vd* is therefore

$$N\_d^\* = \zeta\_c^2 \frac{\mathfrak{e}\_s}{2qV\_d} \tag{3}$$

obtained by substituting for the critical field in Eq. (2). Then, from Eqs. (1) & (3), the minimum thickness of the drift region is given by

$$x\_d^\* = 2\frac{V\_d}{\tilde{\xi}\_c} \tag{4}$$

Accordingly, the drift region of a 4H-SiC DMOSFET can be substantially thinner and more highly doped than a Si-based device designed to control the same bias. Neglecting the current spread [9], the ratio of the optimal ON resistance components from the drift region can thus be estimated by

$$\frac{R\_{dr}^{\*}}{R\_{dr}^{\*}} \Big|\_{Si} = \left. \frac{N\_d^{\*} \mu\_{dr}}{\mathbf{x}\_d^{\*}} \right|\_{Si} \frac{\mathbf{x}\_d^{\*}}{N\_d^{\*} \mu\_{dr}} \Big|\_{Si\mathbb{C}} = \frac{\mu\_{dr} \epsilon\_\mathrm{s} \mathsf{f}\_\mathrm{c}^{3}}{\mu\_{dr} \epsilon\_\mathrm{s} \mathsf{f}\_\mathrm{c}^{3}} \Big|\_{Si\mathbb{C}} \tag{5}$$

where *µdr* is the drift mobility in the bulk of the semiconductor. Plugging the respective constants of the bulk semiconductors into Eq. (5) implies that in ideal devices the energy dissipated using 4H-SiC would be several hundred times lower compared to the Si equivalent for a given ON current [15].

4 Physics and Technology of Silicon Carbide Devices

the step-junction approximation is

PN junction.

being

**(a) (b)**

**Figure 3.** (a) Hot carrier velocity saturation and dielectric breakdown [105]. (b) Field distribution in a one-sided reverse-biased

The critical field *ξ<sup>c</sup>* of a semiconductor, can be used to design the most efficient device for a given blocking voltage *Vd*. When a DMOSFET is in the OFF state, the positive bias applied to the drain is entirely dropped in the N<sup>−</sup> drift region [84, 124]. Indeed, together with the P base, it forms a reverse-biased one-sided PN junction, represented in Fig. 3(b). For a large blocking voltage, *Vd Eg*/*q*, the extent of the depletion region on the lowly-doped side in

> 2*sVd qNd*

where *Nd* is the density of donor atoms in the drift region, *<sup>s</sup>* is the permittivity of the semiconductor, and *q* is the elementary charge. The peak electric field, at the boundary,

obtained by substituting for the critical field in Eq. (2). Then, from Eqs. (1) & (3), the

Accordingly, the drift region of a 4H-SiC DMOSFET can be substantially thinner and more highly doped than a Si-based device designed to control the same bias. Neglecting the current spread [9], the ratio of the optimal ON resistance components from the drift region

2*qNdVd s*

*Vd xd* =  (1)

(2)

(3)

(4)

*xd* =

*ξmax* = 2

*N*∗ *<sup>d</sup>* <sup>=</sup> *<sup>ξ</sup>*<sup>2</sup> *c s* 2*qVd*

> *x*∗ *<sup>d</sup>* <sup>=</sup> <sup>2</sup> *Vd ξc*

The highest doping concentration that can sustain *Vd* is therefore

minimum thickness of the drift region is given by

can thus be estimated by

In a real device, however, there are other components to the resistance such as the contact resistance and the channel resistance. Here we will discuss only the channel specific resistance which contains the contribution from the oxide/semiconductor interface of interest in this Chapter. It can be calculated using the long channel approximation as

$$R\_{\rm ch} = \frac{V\_d}{I\_{\rm sat}} P^2 = \frac{LP}{nq\mu\_{\rm ch}} \tag{6}$$

where *L* is the channel length, *P* is the channel width, or the square cell pitch, *µch* is the inversion mobility, and *n* is the minority carrier density [9]. The total specific ON resistance is then

$$R\_{tot} = R\_{dr}^{\*} + R\_{cl} = \frac{\mathbf{x}\_{d}^{\*}}{N\_{d}^{\*} \, q\mu\_{dr}} + \frac{LP}{n\eta\mu\_{ch}} \tag{7}$$

which has the following dependence on designed blocking voltage according to Eqs. (3) & (4)

$$R\_{\rm tot} = \frac{4V\_d^2}{\mu\_{dr}\epsilon\_s\xi\_c^3} + \frac{LP}{n\eta\mu\_{\rm ch}}\tag{8}$$

**Figure 4.** Schematic of the density of interface traps at the SiO2/SiC interface.

From Eqs. (7) & (8), it can be seen that the smaller the designed blocking voltage, the smaller the width of the necessary drift region, and the larger the contribution from the channel resistance. In Si, that does not have a major impact in power devices because *µch* can be as high as 50% of the bulk value *µdr*. However, SiC channels suffer from a mobility that can be less than 1% of *µdr* at the native SiO2/4H-SiC interface. Therefore, interface quality can affect performance even in the kV range and the full potential of the SiC material cannot be reached. This is highlighted in Fig. 1, where the ratio of ON resistances was calculated using Fig. 2(a) constants, *<sup>L</sup>* <sup>=</sup> <sup>1</sup>*µm*, *<sup>P</sup>* <sup>=</sup> <sup>10</sup>*µm*, *<sup>n</sup>* <sup>=</sup> 1015 cm<sup>−</sup>2, and the following SiC *<sup>µ</sup>ch*: 5, 50, and 500 cm2/V.s. The significance of those mobility values are discussed in the next Sections.
