3. New 4H-SiC Power MESFETs

al new SiC power MESFETs had been designed to optimize the characteristic of the breakdown

For the *n*w\$\*\*!(z
/\_z3\$%\$z%\*(1 %\*#z\*+.)((5w+\*zc !,(!0%+\*z)+ !dz\* z\*+.)(¥ ly-off (enhancement mode) devices, as are shown in Fig.1, an *n*-type channel connects the drain and source regions with the *n* + type doping. The depletion layer under the metalsemiconductor contact determines the current flow across the channel between the source and drain electrodes. The thickness of the channel conductivity is modulated by the gate

The channel of normally-off MESFETs is totally depleted by the gate build-in potential even at zero gate bias, and its threshold voltage is positive. In contrast, the normally-on /z\$2!zz"%\*%0!z.+//w/!0%+\*z+"z+\* 10%\*#z\$\*\*!(z0z6!.+z#0!z%/z\* z0\$!z\*!#¥

The basic operation principle will be discussed in this section for the 4H-SiC power MESFETs. For the normally-on MESFETs, usually, the source is grounded, and the gate and drain are biased negatively and positively, respectively. A schematic diagram of the depletion region under the gate of MESFETs for a finite drain-to-source voltage is shown in Fig. 2. On this condition, the electrons will flow from the source to the drain and a current flow (*I* ds) occurs in the channel. When the negative gate bias is changed, or an altering-current (AC) voltage /%#\*(z%/z/1,!.,+/! z+\*z0\$!z %.!0wz1..!\*0zcdz#0!z%/\_z0\$!z0\$%'\*!//z+"z0\$!z !,(!0%+\*z(5¥ er or the width of the conducting channel, which determining the resistance of the channel, will be modulated, and thus the current flow in the channel is regulated. So, the MESFETs is actually a voltage-controlled electric device by the means that the gate bias modulates the

conducting channel resistance, and thus controls the current flow in the channel.

For the *p*-channel normally-on MESFETs, the gate is biased positively, so as to ensure that the gate is reverse biased. Note that it is the electrons for the *n*-channel MESFETs, but the

voltage, specific on resistance, frequency and transconductance.

Figure 1. Normally-on (a) and normally-off (b) MESFETs at zero gate bias.

bias-dependent depletion region.

292 Physics and Technology of Silicon Carbide Devices

tive threshold voltage.

2. Operation principle for the 4H-SiC Power MESFETs

In this section several new structures for the 4H-SiC power MESFETs are provided in which the surface electric field and breakdown characteristics are optimized.

Figure 2. Depletion region in MESFETs with positive drain bias.

#### 3.1. Field-Plated 4H-SiC MESFETs structure

Fig. 3 is the schematic diagram of the 4H-SiC MESFETs with the field-plate [25], which is the same as the channel-recessed device except the Si3N4 layer on top of the surface. The gate length (*L* g) is 0.5 µm, and the space of gate-source (*L* gs) and gate-drain (*L* gd) are 0.5 µm and 1.0 µm, respectively. The thickness of Si3N4 is 100 nm.

Figure 3. Field-plate SiC MESFETS structure.

Fig.4 shows that the breakdown voltage is dependent on the extension length of the fieldplate toward the drain side *L* ext and show a peak at *L* ext=0.35 µm. The breakdown voltage of 240-250V is obtained at *L* ext=0.35 µm, which is 100 V higher than that of the conventional structure without the field-plate. This is because that the gate leakage current is decreased due to the surface field peak significantly lowered at the gate corner while raised at the drain corner, as is shown in Fig.5.

3.2. Double-recessed 4H-SiC MESFETs structure with recessed source/drain drift region

for the improved DR structure.

cessed (DR) structure.

Fig. 6 shows the schematic cross-section of the 4H-SiC MESFETs [26]. Fig. 6a and 6b show the improved DR and conventional DR structures, respectively. Compared with the conventional DR structure, additional source/drain drift region recess will be formed

Silicon Carbide Power MESFET http://dx.doi.org/10.5772/51085 295

Figure 6. /;@=E9LA; ;JGKKK=;LAGF G> L@= \$/A )!/"!0K KLJM;LMJ=K 9 %EHJGN=< . KLJM;LMJ= : <GM:D=J=s

It can be seen from Fig.7 that the breakdown voltage (*V* b) of the improved DR structure is increased compared to that of the conventional DR structure. A further investigation shows that the breakdown happened at gate corner near drain electrode due to the electric field

Figure 4. Breakdown voltage versus the extension length of the field-plate toward the drain side *L*ext.

Figure 5. Behavior of the gate leakage current versus the drain voltage as a function of *L*ext.

#### 3.2. Double-recessed 4H-SiC MESFETs structure with recessed source/drain drift region

Fig.4 shows that the breakdown voltage is dependent on the extension length of the fieldplate toward the drain side *L* ext and show a peak at *L* ext=0.35 µm. The breakdown voltage of 240-250V is obtained at *L* ext=0.35 µm, which is 100 V higher than that of the conventional structure without the field-plate. This is because that the gate leakage current is decreased due to the surface field peak significantly lowered at the gate corner while raised at the

Figure 4. Breakdown voltage versus the extension length of the field-plate toward the drain side *L*ext.

Figure 5. Behavior of the gate leakage current versus the drain voltage as a function of *L*ext.

drain corner, as is shown in Fig.5.

294 Physics and Technology of Silicon Carbide Devices

Fig. 6 shows the schematic cross-section of the 4H-SiC MESFETs [26]. Fig. 6a and 6b show the improved DR and conventional DR structures, respectively. Compared with the conventional DR structure, additional source/drain drift region recess will be formed for the improved DR structure.

Figure 6. /;@=E9LA; ;JGKKK=;LAGF G> L@= \$/A )!/"!0K KLJM;LMJ=K 9 %EHJGN=< . KLJM;LMJ= : <GM:D=J=s cessed (DR) structure.

It can be seen from Fig.7 that the breakdown voltage (*V* b) of the improved DR structure is increased compared to that of the conventional DR structure. A further investigation shows that the breakdown happened at gate corner near drain electrode due to the electric field crowding at that corner for these two structures. Actually, the maximum electrical field at gate corner near drain of the improved DR structure is reduced, compared with that of the +\*2!\*0%+\*(zz/0.101.!^z\$!.!"+.!\_z%0z(!.(5z/\$+3/z0\$0z0\$!z%\*.!/!z+"z.!' +3\*z2+(0¥ age is attributed to reduced electric field crowding at gate corner near the drain due to thin channel thickness between the gate and drain electrodes with recessed drain drift region.

In Buffer-Gate 4H-SiC MESFETs, the gate length and width are 0.7 µm and 332 µ)^z
!\*¥ while, the thickness and doping concentration are 0.26 µm and 1.7×1017 cm-3 for the channel layer, and 0.2 µm and 1×1014 cm-3 for the gate-buffer layer between the gate and channel.

Silicon Carbide Power MESFET http://dx.doi.org/10.5772/51085 297

Fig. 9 shows the dependence of the current in the channel on the gate-buffer layer. It reveals that the thicker the gate-buffer layer is, the larger the drain current is. This is because the channel width is increased owing to the decrease of the thickness of the depletion layer in the channel when the gate-buffer layer doping concentration and thickness are increased. It is also shown in Fig. 9 0\$0z3\$!\*z0\$!z#0!w1""!.z(5!.z%/z%\*.!/! z/1""%%!\*0(5\_z0\$!z .%\*z1.¥ .!\*0z%\*.!/!/z /(+3(5z !1/!z 0\$!z 0\$%'\*!//z +"z 0\$!z !,(!0! z(5!.z%\*z 0\$!z \$\*\*!(z(5!.z !¥ creases, and thus the width of the conduction channel increases more and more slowly with

Figure 9. The dependence of the drain current on the gate-buffer layer for *N*0=1×1015cm-3(solid line), *N*

Fig.10(a). is the breakdown characteristics for the two structures. It can be seen that the breakdown voltage (*V*b) is significantly increased, compared with that of the conventional structure. In fact, the breakdown happens at the gate corner near to the drain side due to the !(!0.%z"%!( z.+3 %\*#z\$!.!z"+.z+0\$z03+z/0.101.!/^z+3!2!.\_z0\$!z!(!0.%z"%!( z,!'z%/z/%#¥ nificantly lowered at the gate corner, i.e., the surface electric field is more uniform, owing to the inserted lower doped gate-buffer layer when compared with that of the conventional 4H-SiC MESFETs. Fig.10 (b) plots the corresponding electric field distribution. The reason for the suppression of the electric field at the gate corner is similar to that for the weakened

surface electric field caused by lightly doped drain (LDD) in the MOSFETs [28].

increasing the thickness of the gate-buffer layer.

0=5×1015cm-3(dash line) and *N* 0=1×1016cm-3(dot line). *V gs*=0 V, *V ds*=5 V.

Figure 7. Simulated three-terminal breakdown characteristics.

#### 3.3. Buffer-Gate 4H-SiC MESFETs structure

Fig. 8 is the schematic diagram of the structure of the Buffer-Gate SiC MESFETs structure [27f^z+),.! z3%0\$z0\$!z+\*2!\*0%+\*(zGw%z
/\_zz(+3z +,! z#0!w1""!.z(5!.z%/z%\*¥ troduced between the gate and channel layer.

Figure 8. The schematic diagram of the buffer-gate structure.

In Buffer-Gate 4H-SiC MESFETs, the gate length and width are 0.7 µm and 332 µ)^z
!\*¥ while, the thickness and doping concentration are 0.26 µm and 1.7×1017 cm-3 for the channel layer, and 0.2 µm and 1×1014 cm-3 for the gate-buffer layer between the gate and channel.

crowding at that corner for these two structures. Actually, the maximum electrical field at gate corner near drain of the improved DR structure is reduced, compared with that of the +\*2!\*0%+\*(zz/0.101.!^z\$!.!"+.!\_z%0z(!.(5z/\$+3/z0\$0z0\$!z%\*.!/!z+"z.!' +3\*z2+(0¥ age is attributed to reduced electric field crowding at gate corner near the drain due to thin channel thickness between the gate and drain electrodes with recessed drain drift region.

Fig. 8 is the schematic diagram of the structure of the Buffer-Gate SiC MESFETs structure [27f^z+),.! z3%0\$z0\$!z+\*2!\*0%+\*(zGw%z
/\_zz(+3z +,! z#0!w1""!.z(5!.z%/z%\*¥

Figure 7. Simulated three-terminal breakdown characteristics.

3.3. Buffer-Gate 4H-SiC MESFETs structure

296 Physics and Technology of Silicon Carbide Devices

troduced between the gate and channel layer.

Figure 8. The schematic diagram of the buffer-gate structure.

Fig. 9 shows the dependence of the current in the channel on the gate-buffer layer. It reveals that the thicker the gate-buffer layer is, the larger the drain current is. This is because the channel width is increased owing to the decrease of the thickness of the depletion layer in the channel when the gate-buffer layer doping concentration and thickness are increased. It is also shown in Fig. 9 0\$0z3\$!\*z0\$!z#0!w1""!.z(5!.z%/z%\*.!/! z/1""%%!\*0(5\_z0\$!z .%\*z1.¥ .!\*0z%\*.!/!/z /(+3(5z !1/!z 0\$!z 0\$%'\*!//z +"z 0\$!z !,(!0! z(5!.z%\*z 0\$!z \$\*\*!(z(5!.z !¥ creases, and thus the width of the conduction channel increases more and more slowly with increasing the thickness of the gate-buffer layer.

Figure 9. The dependence of the drain current on the gate-buffer layer for *N*0=1×1015cm-3(solid line), *N* 0=5×1015cm-3(dash line) and *N* 0=1×1016cm-3(dot line). *V gs*=0 V, *V ds*=5 V.

Fig.10(a). is the breakdown characteristics for the two structures. It can be seen that the breakdown voltage (*V*b) is significantly increased, compared with that of the conventional structure. In fact, the breakdown happens at the gate corner near to the drain side due to the !(!0.%z"%!( z.+3 %\*#z\$!.!z"+.z+0\$z03+z/0.101.!/^z+3!2!.\_z0\$!z!(!0.%z"%!( z,!'z%/z/%#¥ nificantly lowered at the gate corner, i.e., the surface electric field is more uniform, owing to the inserted lower doped gate-buffer layer when compared with that of the conventional 4H-SiC MESFETs. Fig.10 (b) plots the corresponding electric field distribution. The reason for the suppression of the electric field at the gate corner is similar to that for the weakened surface electric field caused by lightly doped drain (LDD) in the MOSFETs [28].

Figure 11. The schematic diagram of the MESFETs with gate-drain surface epi-layer.

Figure 12. GEH9JAKGFG>L@=KMJ>9;==D=;LJA;>A=D<99F<L@=:J=9C<GOFNGDL9?=:>GJL@=;GFN=FLAGF9D

ed, and the GDSE structure.

"A=D<HD9Ls

Silicon Carbide Power MESFET http://dx.doi.org/10.5772/51085 299

Figure 10. (a) The simulated breakdown characteristics for *a*0eEGH=F9F<*a* <sup>0</sup>eE>ADD=< :0@=<AKLJA:Ms tion of the surface electric field for *a* <sup>0</sup>eE<9K@9F<*a* <sup>0</sup>eEKGDA<

#### 3.4. Gate-drain surface epitaxial layer MESFETs structure (GDSE)

The schematic diagram of the GDSE structure is shown in Fig.11 [29]. Compared with the +\*2!\*0%+\*(zGw%z
/\_zz(+3z +,! z,w05,!z/1."!z!,%04%(z(5!.z%/z%\*0.+ 1! z!¥ tween the gate and drain when its doping concentration is lower than that of the channel layer by two orders. Firstly, there appears a build-in potential in the p-n junction between the p-type epitaxial layer and n-type channel layer or n+ cap layer, which reduces the electric field peak at the gate corner. Thus it improves the electric field distribution. Secondly, the most part of the depletion layer in the p-n junction lies in the p-type epitaxial layer due to its doping concentration much lower than that of the n-type channel layer. Therefore, the gatedrain p-type epitaxial layer has little bad effect on the current density.

Figure 11. The schematic diagram of the MESFETs with gate-drain surface epi-layer.

Figure 10. (a) The simulated breakdown characteristics for *a*0eEGH=F9F<*a* <sup>0</sup>eE>ADD=<

The schematic diagram of the GDSE structure is shown in Fig.11 [29]. Compared with the +\*2!\*0%+\*(zGw%z
/\_zz(+3z +,! z,w05,!z/1."!z!,%04%(z(5!.z%/z%\*0.+ 1! z!¥ tween the gate and drain when its doping concentration is lower than that of the channel layer by two orders. Firstly, there appears a build-in potential in the p-n junction between the p-type epitaxial layer and n-type channel layer or n+ cap layer, which reduces the electric field peak at the gate corner. Thus it improves the electric field distribution. Secondly, the most part of the depletion layer in the p-n junction lies in the p-type epitaxial layer due to its doping concentration much lower than that of the n-type channel layer. Therefore, the gate-

tion of the surface electric field for *a* <sup>0</sup>eE<9K@9F<*a* <sup>0</sup>eEKGDA<

298 Physics and Technology of Silicon Carbide Devices

3.4. Gate-drain surface epitaxial layer MESFETs structure (GDSE)

drain p-type epitaxial layer has little bad effect on the current density.

:0@=<AKLJA:Ms

Figure 12. GEH9JAKGFG>L@=KMJ>9;==D=;LJA;>A=D<99F<L@=:J=9C<GOFNGDL9?=:>GJL@=;GFN=FLAGF9D "A=D<HD9Ls ed, and the GDSE structure.

The breakdown characteristics and surface electric field distribution are shown in Fig.11. Fig.12 (a) shows that the breakdown voltage of the GDSE structure is the largest one for the 0\$.!!z/0.101.!/^z\$!z.!/+\*z"+.z0\$!z.!' +3\*z%\*.!/! z%/z0\$0z0\$!z!(!0.%z"%!( z,!'z%/z/%#¥ nificantly lowered at the gate corner, i.e., the surface electric field is more uniform, owing to the inserted lower doped p-type epitaxial layer when compared with that of the other two SiC MESFETs, as is shown in Fig.12 (b).

### 4. New 4H-SiC Power MESFETs Modeling

In most cases, the constant mobility is adopted for simplicity to develop the analytical models +"z0\$!z
/z3\$%\$z !/.%!/z !2%!z+,!.0%+\*^z+3!2!.\_z0\$!z+\*/0\*0z)+%(%05z,,.+4%¥ mation is not adequate to describe the electron transport in the low field region and leads to an inaccurate estimation of the drain current and device characteristics of the 4H-SiC MESFETs. \*z0\$%/z/!0%+\*\_z0\$!z%),.+2! z\*(50%(z)+ !(z"+.z0\$!z+\*2!\*0%+\*(zGw%z
/z%/z,.+2% ¥ ed which adopts the field-dependent mobility of the electrons, and takes into account the ungated high field region between the gate and drain which is usually omitted [30].

For the 4H-SiC material, the dependence of the mobility of the electron on the electric field can be described by Caughey–Thomas model [31].

$$\mu\left(E\right) = \frac{\mu\_0}{\left[1 + \left(\frac{\mu\_0 E}{\nu\_s}\right)^\beta\right]^{1/\beta}}\tag{1}$$

*IC*(*VG*, *VD*)= *IP*

*µ*0*W* <sup>6</sup>c*<sup>L</sup>* , *Vp* <sup>=</sup>

*Ip* = *q* 2 *ND*2*<sup>a</sup>* <sup>3</sup>

Figure 13. The schematic diagram of the 4H-SiC MESFETs.

respectively. The saturation channel current is

*h*1 *<sup>a</sup>* <sup>=</sup> <sup>1</sup> *a*

c *qND*

the saturation velocity, a=0.99.

*u*1(*VG*, *VD*)=

3(*ud* <sup>2</sup> *u*<sup>0</sup>

2)2(*ud*

<sup>2</sup> *u*<sup>0</sup>

1 + *Z*(*ud*

where *u* 0 (*u* d) is the depletion layer width *h* 0 (*h* <sup>d</sup>dz0z0\$!z/+1.!zc .%\*dz!\* z+"z0\$!z\$\*\*!(z\*+.¥ malized to the epi-layer channel layer thickness *a*. *I* P, *Z* and *V* P are constants expressed by

> *qNDa* <sup>2</sup> <sup>2</sup><sup>c</sup> , *<sup>Z</sup>* <sup>=</sup>

With the drain bias increasing gradually, the lateral electric field increases and the electron 2!(+%05z.%/!/z0+3. z%0/z/01.0%+\*z2(1!^z0z!\*+1#\$z\$%#\$z .%\*z%/\_z0\$!z\$\*\*!(z%/z%\*z/01¥ ration regime, and can be divided into three regions which are shown in Fig. 13. In region with its length of *L* <sup>1</sup> and nearer to the source under the gate, the electric field is low and the electron velocity is less than the saturation velocity (n s). The saturation region below the gate and the saturation region between the gate and the drain are labeled as regions and ,

where *u* <sup>1</sup> is the normalized depletion layer thickness at the point where the electron reaches

<sup>3</sup> *u*<sup>0</sup> 3)

> *qNDa* <sup>2</sup> *µ*0 2c*L* n*<sup>s</sup>*

*Icsat* =*qNDWa*an*s*(1*u*1) (5)

*VP*

*<sup>V</sup>* (*<sup>L</sup>* <sup>1</sup>) <sup>+</sup> *VG* <sup>+</sup> *Vbi* <sup>=</sup> *<sup>V</sup>* (*<sup>L</sup>* 1) <sup>+</sup> *VG* <sup>+</sup> *Vbi*

2) (3)

Silicon Carbide Power MESFET http://dx.doi.org/10.5772/51085

(4)

301

(6)

where *µ* 0 is the low field mobility, n s the saturation velocity, *E* the electric field strength and ` z1.201.!z,.)!0!.z+"z0\$!z+. !.z+"zDz !/.%%\*#z0\$!z/01.0%+\*z0!\* !\*5^z+.z%z)0!.%¥ al, the measured value of ` is 1.2 in the experiment [32]. For simplicity, `D1 is a reasonably good approximation [33].

Fig. 13 is the schematic diagram of the 4H-SiC MESFETs. The depletion layer thickness *h*(*x*) under the gate, *x* away from the source is obtained by solving the one dimensional (1-D) Poisson's equation.

$$h(\mathbf{x}) = \left(\frac{2\varepsilon \left[V(\mathbf{x}) + V\_G + V\_{bi}\right]}{qN\_D}\right)^{\frac{1}{2}}\tag{2}$$

where *N* D is the uniformly doping concentration of the channel layer, and c the dielectric constant. *V(x)* is the potential difference between the source and the point *x* away from the source, *V* G the gate bias, and *V* bi the build-in voltage.

When the drain voltage is low, the electric field in the channel is less than the saturation field *E* s, and only region exists. Based on integrating over the channel length *L*\_z0\$!z\$\*¥ nel current is obtained

$$I\_C(V\_{G'}, V\_D) = I\_p \frac{[\Im(\mu\_d^{-2} - \mu\_0^{-2}) - 2(\mu\_d^{-3} - \mu\_0^{-3})]}{1 + Z\{\mu\_d^{-2} - \mu\_0^{-2}\}} \tag{3}$$

where *u* 0 (*u* d) is the depletion layer width *h* 0 (*h* <sup>d</sup>dz0z0\$!z/+1.!zc .%\*dz!\* z+"z0\$!z\$\*\*!(z\*+.¥ malized to the epi-layer channel layer thickness *a*. *I* P, *Z* and *V* P are constants expressed by

$$I\_p = \frac{q^2 N\_D 2a^3 \mu\_0 W}{6\varepsilon L}, \; V\_p = \frac{qN\_D a^2}{2\varepsilon}, \; Z = \frac{qN\_D a^2 \mu\_0}{2\varepsilon L \cdot \nu\_s} \tag{4}$$

Figure 13. The schematic diagram of the 4H-SiC MESFETs.

The breakdown characteristics and surface electric field distribution are shown in Fig.11. Fig.12 (a) shows that the breakdown voltage of the GDSE structure is the largest one for the 0\$.!!z/0.101.!/^z\$!z.!/+\*z"+.z0\$!z.!' +3\*z%\*.!/! z%/z0\$0z0\$!z!(!0.%z"%!( z,!'z%/z/%#¥ nificantly lowered at the gate corner, i.e., the surface electric field is more uniform, owing to the inserted lower doped p-type epitaxial layer when compared with that of the other two

In most cases, the constant mobility is adopted for simplicity to develop the analytical models +"z0\$!z
/z3\$%\$z !/.%!/z !2%!z+,!.0%+\*^z+3!2!.\_z0\$!z+\*/0\*0z)+%(%05z,,.+4%¥ mation is not adequate to describe the electron transport in the low field region and leads to an inaccurate estimation of the drain current and device characteristics of the 4H-SiC MESFETs. \*z0\$%/z/!0%+\*\_z0\$!z%),.+2! z\*(50%(z)+ !(z"+.z0\$!z+\*2!\*0%+\*(zGw%z
/z%/z,.+2% ¥ ed which adopts the field-dependent mobility of the electrons, and takes into account the un-

For the 4H-SiC material, the dependence of the mobility of the electron on the electric field

` 1/` (1)

<sup>2</sup> (2)

gated high field region between the gate and drain which is usually omitted [30].

*<sup>µ</sup>*(*E*)= *<sup>µ</sup>*<sup>0</sup>

<sup>1</sup> <sup>+</sup> ( *<sup>µ</sup>*0*<sup>E</sup>* n*s* )

where *µ* 0 is the low field mobility, n s the saturation velocity, *E* the electric field strength and ` z1.201.!z,.)!0!.z+"z0\$!z+. !.z+"zDz !/.%%\*#z0\$!z/01.0%+\*z0!\* !\*5^z+.z%z)0!.%¥ al, the measured value of ` is 1.2 in the experiment [32]. For simplicity, `D1 is a reasonably

Fig. 13 is the schematic diagram of the 4H-SiC MESFETs. The depletion layer thickness *h*(*x*) under the gate, *x* away from the source is obtained by solving the one dimensional (1-D)

*qND*

where *N* D is the uniformly doping concentration of the channel layer, and c the dielectric constant. *V(x)* is the potential difference between the source and the point *x* away from the

When the drain voltage is low, the electric field in the channel is less than the saturation field *E* s, and only region exists. Based on integrating over the channel length *L*\_z0\$!z\$\*¥

) 1

*<sup>h</sup>* (*x*)=( <sup>2</sup><sup>c</sup> *<sup>V</sup>* (*x*) <sup>+</sup> *VG* <sup>+</sup> *Vbi*

SiC MESFETs, as is shown in Fig.12 (b).

300 Physics and Technology of Silicon Carbide Devices

4. New 4H-SiC Power MESFETs Modeling

can be described by Caughey–Thomas model [31].

source, *V* G the gate bias, and *V* bi the build-in voltage.

good approximation [33].

Poisson's equation.

nel current is obtained

With the drain bias increasing gradually, the lateral electric field increases and the electron 2!(+%05z.%/!/z0+3. z%0/z/01.0%+\*z2(1!^z0z!\*+1#\$z\$%#\$z .%\*z%/\_z0\$!z\$\*\*!(z%/z%\*z/01¥ ration regime, and can be divided into three regions which are shown in Fig. 13. In region with its length of *L* <sup>1</sup> and nearer to the source under the gate, the electric field is low and the electron velocity is less than the saturation velocity (n s). The saturation region below the gate and the saturation region between the gate and the drain are labeled as regions and , respectively. The saturation channel current is

$$I\_{\rm csat} = qN\_D \mathsf{W} a \gamma \upsilon\_s (1 - u\_1) \tag{5}$$

where *u* <sup>1</sup> is the normalized depletion layer thickness at the point where the electron reaches the saturation velocity, a=0.99.

$$\mu\_1(V\_{G'}, V\_D) = \frac{h\_1}{a} = \frac{1}{a} \sqrt{\frac{\varepsilon}{qN\_D} \left[ V(L\_{-1}) + V\_G + V\_{bi} \right]} = 4 \frac{\left[ \overline{V(L\_{-1}) + V\_G + V\_{bi}} \right]}{V\_P} \tag{6}$$

where *h* <sup>1</sup>z%/z0\$!z !,(!0%+\*z(5!.z0\$%'\*!//z0z0\$!z,+%\*0z3\$!.!z0\$!z!(!0.+\*z.!\$!/z0\$!z/01.¥ tion velocity, *V(L* <sup>1</sup> *)* is the potential difference between the source and the point at *x=L* 1, where the saturation velocity n(*L* 1)=an s.

To obtain the saturation current in the channel, there requires other equations involving *u* <sup>1</sup> or *L* 1, which can be obtained by solving 2-D Poisson's equation.

The potential drop across regions and achieved by solving the 2-D Poisson's equation is

$$V(L\_s + L\_{\frac{3}{3}}) - V(L\_{\frac{1}{3}}) = (\frac{2au\_1}{\pi} + \frac{L\_{\frac{3}{3}}}{3})E\_s \sinh(\frac{\pi L\_{\frac{2}{2}}}{2au\_1}) \exp(\frac{-\pi L\_{\frac{3}{3}}}{2au\_1})$$

$$+ \frac{E\_s L\_{\frac{3}{3}}}{3} (2 \exp(\frac{\pi L\_{\frac{2}{2}}}{2au\_1}) + 1)$$

From the analysis above, the drain current can be achieved when the structure parameters

Using the obtained model, the *I-V* characteristics are calculated, as is shown in Fig.14. It can be seen that the *I*–*V* characteristics calculated using the obtained model are in agreement

Adopting the same approach, Yang et al developed analytical models for the new Buffer-Gate MESFETs [27f^z\$!z\*(50%(z)+ !(/z !/.%%\*#z 0\$!z %.!0w1..!\*0z cdz\* z(0!.\*0¥

(*L*, *W*, *a*, *a* 0, *N* D, *N* 0) and bias voltage (*V* D, *V* G) are given.

ing current (AC) characteristics are as follows: Under low drain voltage, the channel current is

> 3(*ud* <sup>2</sup> *u*<sup>0</sup>

*IC*(*VG*, *VD*)= *IP*

*u*1(*VG*, *VD*)=

where the saturation velocity n(*L* 1)=an *<sup>s</sup>*.

small signal parameters analytically.

given in equation (12)

*d P*

*a* .

*dl*

where *md* <sup>=</sup>*ud* <sup>+</sup> *<sup>a</sup>*<sup>0</sup> *h*1

*<sup>a</sup>* <sup>=</sup> (1 *<sup>N</sup>*<sup>0</sup>

*ND* ) *a*0 2 *<sup>a</sup>* <sup>2</sup> <sup>+</sup>

with the experimental data, which verifies the validity of the model.

2)2(*ud*

1 + *Z*(*ud*

<sup>3</sup> *u*<sup>0</sup>

<sup>2</sup> *u*<sup>0</sup>

At high drain bias, the channel is in saturation mode, the saturation channel current is *I csat*.

where *u* <sup>1</sup> is the depletion layer thickness normalized to the epilayer channel layer thickness *a* at the point where the electron reaches the saturation velocity and given by equation (11)

where *h* <sup>1</sup>z%/z0\$!z !,(!0%+\*z(5!.z0\$%'\*!//z0z0\$!z,+%\*0z3\$!.!z0\$!z!(!0.+\*z.!\$!/z0\$!z/01.¥ tion velocity, *V(L* <sup>1</sup> *)* is the potential difference between the source and the point at *x=L* 1,

To evaluate the high frequency performance conveniently, it is important to describe the

From Eq.(9), the device's drain conductance for the linear region can be derived which is

<sup>2</sup> (1 ) ( )( ) ( ) 2 ( ) 3( ) <sup>3</sup>

*dd d <sup>d</sup> d d P d*

*a a <sup>a</sup> u Zu u u Zu u Z u u u I u a a <sup>a</sup> <sup>g</sup> m V <sup>a</sup> Zu u Z u u <sup>a</sup>* ' ( )

2 2 3 3 0 0 <sup>0</sup> 00 0

2 2 <sup>0</sup> 0 0

1 ( )2 ( )

' ( )

*d d*

3) 3*a*<sup>0</sup>

2) <sup>+</sup> *<sup>Z</sup>* ·2*a*<sup>0</sup>

*<sup>a</sup>* · (*ud*

(*V* (*L* 1) + *VG* + *Vbi*

*Vp*

<sup>2</sup> *u*<sup>0</sup>

*<sup>a</sup>* · (*ud u*0)

*Icsat* =*qNDWa*an*s*(1*u*1) (10)

)

 *a*0 *a*

2

2)2(*ud u*0)

(9)

303

Silicon Carbide Power MESFET http://dx.doi.org/10.5772/51085

(11)

(12)

The equation involving *L* 3 is

$$\begin{aligned} &L\_s^{-2}\left[\frac{qN\_DM\_1}{\varepsilon} - E\_s \exp(\frac{\pi L\_2}{2au\_1}) + E\_s \sinh(\frac{\pi L\_2}{2au\_1})\right] \\ &= (au\,\mathrm{l})^2 E\_s \left[\exp(\frac{\pi L\_2}{2au\_1}) - 1 - \sinh(\frac{\pi L\_2}{2au\_1}) \exp(\frac{-\pi L\_3}{2au\_1})\right] \end{aligned} \tag{8}$$

where *V* (*L* + *L* <sup>3</sup>)=*VD ICRD*.

Figure 14. Calculated and experimental *I-V* characteristics, at *V* gs=0,-2,-4,-6,-8 V.

From the analysis above, the drain current can be achieved when the structure parameters (*L*, *W*, *a*, *a* 0, *N* D, *N* 0) and bias voltage (*V* D, *V* G) are given.

Using the obtained model, the *I-V* characteristics are calculated, as is shown in Fig.14. It can be seen that the *I*–*V* characteristics calculated using the obtained model are in agreement with the experimental data, which verifies the validity of the model.

Adopting the same approach, Yang et al developed analytical models for the new Buffer-Gate MESFETs [27f^z\$!z\*(50%(z)+ !(/z !/.%%\*#z 0\$!z %.!0w1..!\*0z cdz\* z(0!.\*0¥ ing current (AC) characteristics are as follows:

Under low drain voltage, the channel current is

$$I\_C(V\_{G'}, V\_D) = I\_P \frac{[\Im(\mu\_d^{-2} - \mu\_0^{-2}) - 2(\mu\_d^{-3} - \mu\_0^{-3})] - \frac{3a\_0}{a} \cdot \left[\Im(\mu\_d^{-2} - \mu\_0^{-2}) - 2(\mu\_d - \mu\_0)\right]}{1 + Z\{\mu\_d^{-2} - \mu\_0^{-2}\} + Z \cdot \frac{2a\_0}{a} \cdot \{\mu\_d - \mu\_0\}}\tag{9}$$

At high drain bias, the channel is in saturation mode, the saturation channel current is *I csat*.

$$I\_{c\text{sat}} = qN\_D W a \gamma \upsilon\_s (1 - u\_1) \tag{10}$$

where *u* <sup>1</sup> is the depletion layer thickness normalized to the epilayer channel layer thickness *a* at the point where the electron reaches the saturation velocity and given by equation (11)

$$\mu\_1(V\_{G\prime}, V\_D) = \frac{h\_1}{a} = 4\sqrt{(1 - \frac{N\_0}{N\_D})\frac{a\_0^2}{a^2} + \frac{(V(L\_1) + V\_G + V\_{bi})}{V\_p}} - \frac{a\_0}{a} \tag{11}$$

where *h* <sup>1</sup>z%/z0\$!z !,(!0%+\*z(5!.z0\$%'\*!//z0z0\$!z,+%\*0z3\$!.!z0\$!z!(!0.+\*z.!\$!/z0\$!z/01.¥ tion velocity, *V(L* <sup>1</sup> *)* is the potential difference between the source and the point at *x=L* 1, where the saturation velocity n(*L* 1)=an *<sup>s</sup>*.

To evaluate the high frequency performance conveniently, it is important to describe the small signal parameters analytically.

From Eq.(9), the device's drain conductance for the linear region can be derived which is given in equation (12)

$$\log\_{d} = \frac{3I\_{P} \cdot (u\_{d} + \frac{a\_{0}}{\sqrt{d}})}{m\_{d}V\_{P}} \cdot \frac{\left[ (1 - u\_{d}) - Z(u\_{d} - \frac{a\_{0}}{\sqrt{d}})(u\_{d}^{-2} - u\_{0}^{-2}) + \frac{2}{3} \int\_{\mathfrak{T}} \cdot Z(u\_{d}^{-3} - u\_{0}^{3}) - 2Z \cdot \frac{a\_{0}}{\sqrt{a}} \cdot u\_{d} \cdot (u\_{d} - u\_{0}) \right]}{\left[ 1 + Z(u\_{d}^{-2} - u\_{0}^{-2}) + 2Z \cdot \frac{a\_{0}}{\sqrt{a}} \Big| \cdot (u\_{d} - u\_{0}) \right]^{2}} \tag{12}$$

where

where *h* <sup>1</sup>z%/z0\$!z !,(!0%+\*z(5!.z0\$%'\*!//z0z0\$!z,+%\*0z3\$!.!z0\$!z!(!0.+\*z.!\$!/z0\$!z/01.¥ tion velocity, *V(L* <sup>1</sup> *)* is the potential difference between the source and the point at *x=L* 1,

To obtain the saturation current in the channel, there requires other equations involving *u* <sup>1</sup>

The potential drop across regions and achieved by solving the 2-D Poisson's equation is

<sup>3</sup> )*Es*sinh(

) + 1)

1 1

 

*au au*

exp( ) sinh( ) 2 2

1 11

*au au au*

)

 

j*L* <sup>2</sup> 2*au*<sup>1</sup> j*L* <sup>2</sup> 2*au*<sup>1</sup>

)exp(

j*L* <sup>3</sup> 2*au*<sup>1</sup> )

(7)

(8)

where the saturation velocity n(*L* 1)=an s.

302 Physics and Technology of Silicon Carbide Devices

*V* (*L* + *L* <sup>3</sup>)*V* (*L* <sup>1</sup>)=(

The equation involving *L* 3 is

where

*V* (*L* + *L* <sup>3</sup>)=*VD ICRD*.

3

*D*

 

*s*

Figure 14. Calculated and experimental *I-V* characteristics, at *V* gs=0,-2,-4,-6,-8 V.

or *L* 1, which can be obtained by solving 2-D Poisson's equation.

+ *EsL* <sup>3</sup>

2*au*<sup>1</sup> j + *L* <sup>3</sup>

<sup>3</sup> (2exp(

2 12 2

*qN au <sup>L</sup> <sup>L</sup> LE E*

*s s*

 ' ( )

2 2 2 3

( 1) exp( ) 1 sinh( ) exp( ) 2 22

*L L <sup>L</sup> au E*

' (

*md* <sup>=</sup>*ud* <sup>+</sup> *<sup>a</sup>*<sup>0</sup> *a* . Similarly, the transconductance for the linear region is equation (13)

2 2 3 3 0 0 <sup>0</sup> 00 0 2 2 2 <sup>0</sup> 0 0 2 2 3 3 0 0 <sup>0</sup> <sup>0</sup> 0 0 0 00 <sup>0</sup> 0 <sup>2</sup> (1 ) ( )( ) ( ) 2 ( ) 3( ) <sup>3</sup> 1 ( )2 ( ) <sup>2</sup> (1 ) ( )( ) ( ) 2 ( ) 3( ) <sup>3</sup> 1 *dd d <sup>d</sup> d d P d ml d P d d dd d <sup>P</sup> P a a <sup>a</sup> u Zu u u Zu u Z u u u I u a a <sup>a</sup> <sup>g</sup> m V <sup>a</sup> Zu u Z u u <sup>a</sup> a a <sup>a</sup> u Zu u u Zu u Z u u u I u a a <sup>a</sup> m V* ' ( ) ' ( ) ' ( ) <sup>2</sup> 2 2 <sup>0</sup> 0 0 ( )2 ( ) *d d <sup>a</sup> Zu u Z u u <sup>a</sup>* ' ( ) (13)

where

$$m\_0 = \mu\_0 + \lambda\_0 \Big|\_{a^-} $$

From Eq.(10), the drain conductance for the saturation region is obtained expressed by Eq.(14)

$$\mathbf{g}\_{ds} = -\frac{\mathbf{\mathcal{B}} \boldsymbol{\chi} \boldsymbol{I}\_{\mathrm{P}}}{2 \mathbf{Z} \boldsymbol{m}\_{\mathrm{L}\_{\mathrm{u}}} \boldsymbol{V}\_{\mathrm{P}}} \boldsymbol{f} \tag{14}$$

*<sup>h</sup>* <sup>=</sup> <sup>1</sup> 2*mL* <sup>1</sup> *VP*

{ <sup>2</sup>*u*1(1a) <sup>f</sup> <sup>+</sup>

where

*Cgs*<sup>1</sup> =

*Cgs*<sup>2</sup> =

*g* =1

4c*WL VP IP*

2c*WLZu*<sup>1</sup>

*Cgs*<sup>3</sup> = c*ESWa*

*L* <sup>1</sup>

*aID* { *gm ID*

*<sup>a</sup>* { *<sup>g</sup>*

{ *k* + 1 2*mL* <sup>1</sup> *VP* {

+

*<sup>L</sup> Zu*1{ <sup>2</sup>*u*1(1a)

shown in Fig.15 to Fig.18.

*a*0 a*a* a

(*u*1 <sup>2</sup> *u*<sup>0</sup>

+

2*ZmL* <sup>1</sup> *u*1

2*ES a* <sup>j</sup> sinh

(*u*1 <sup>2</sup> *u*<sup>0</sup> 2)<sup>2</sup> 3(*<sup>u</sup>*<sup>1</sup> <sup>3</sup> *u*<sup>0</sup> 3)

j(*L L* 1) 2(*au*<sup>1</sup> <sup>+</sup> *<sup>a</sup>*0)

<sup>a</sup>(1*u*1)2 *<sup>a</sup>*<sup>0</sup>

*u*0*ES LZ m*0*VP*

er which is obtained by solving the 2-D Poisson's equation.

(1 *a*0 *<sup>a</sup>* )(*u*<sup>1</sup>

(*k* + 1) +

1cosh

j(*L L* 1) 2(*au*<sup>1</sup> + *a*0)

3*u*<sup>1</sup> 2*mL* <sup>1</sup> *VP* (*u*<sup>1</sup> + *a*0

j*u*0*LZ*(1*u*1) <sup>2</sup>*m*0*VP*(*au*<sup>1</sup> <sup>+</sup> *<sup>a</sup>*0) sinh

> + (*u*1 <sup>2</sup> *u*<sup>0</sup> 2)<sup>2</sup> 3(*<sup>u</sup>*<sup>1</sup> <sup>3</sup> *u*<sup>0</sup> 3)

2)(*u*<sup>1</sup> *u*0) (1*u*1)<sup>2</sup> 2(1a)

The expression of the gate-source capacitance is equation (16)

a*a*

cosh

<sup>3</sup> *u*<sup>0</sup>

*u*0 *m*0

j(*L L* 1)

3) <sup>3</sup> <sup>4</sup> (*u*<sup>1</sup> <sup>4</sup> *u*<sup>0</sup> 4) + 3*a*<sup>0</sup> *<sup>a</sup>* (*u*<sup>1</sup>

*u*<sup>1</sup> *u*<sup>0</sup> <sup>a</sup>(1*u*1) <sup>+</sup>

2(*au*<sup>1</sup> <sup>+</sup> *<sup>a</sup>*0) <sup>j</sup>(1*u*1)

*a*(*L L* 1) *au*<sup>1</sup> + *a*<sup>0</sup>

j(*L L* 1) 2(*au*<sup>1</sup> <sup>+</sup> *<sup>a</sup>*0) ( <sup>1</sup>*u*<sup>0</sup>

<sup>a</sup>(1*u*1)2

Using their model, Yang et al calculate the *I-V* \$.0!.%/0%/z\* zz/)((z/%#\*(z\$.0!.¥ istics of the proposed 4H-SiC MESFETs with a gate-buffer layer of 0.2 µm. The results are

*ZID* 3*IP*

*<sup>a</sup>* )(1*u*<sup>1</sup>

(*u*1 <sup>2</sup> *u*<sup>0</sup>

j(*L L* 1) 2(*au*<sup>1</sup> + *a*0)

+z"%\* z0\$!z#0!w/+1.!z,%0\*!\_z0\$!z)#\*%01 !z+"z0\$!z\$.#!z%\*z0\$!z !,(!0%+\*z(5!.z1\*¥ !.z0\$!z#0!z%/z\*!! ! ^z 0z\*z!z !.%2! z".+)z0\$!z,+0!\*0%(z %/0.%10%+\*z%\*z0\$!z !,(!0%+\*z(5¥

*ES a*(*L L* 1) (*au*<sup>1</sup> <sup>+</sup> *<sup>a</sup>*0) cosh

> *ES LZ* 2*mL* <sup>1</sup> *VP* cosh

> > 2)(*u*<sup>1</sup> *u*0)

1*u*<sup>0</sup> <sup>a</sup>(1*u*1) <sup>1</sup> (1 <sup>+</sup>

(1*u*1)2 2(1a) }

*Cgs* =*Cgs*<sup>1</sup> + *Cgs*<sup>2</sup> + *Cgs*<sup>3</sup> (16)

<sup>2</sup> *u*<sup>0</sup> 2)

}

*a*0 *au*<sup>0</sup> )

}

(*u*<sup>0</sup> + *a*0

*<sup>a</sup>* )(1*u*<sup>0</sup>

*ZID* 3*IP* ) }

2*m*0*VP*

*a*0 *au*<sup>0</sup> )}

)(*<sup>k</sup>* <sup>+</sup> 1) <sup>3</sup>*u*<sup>0</sup>

*L* · *g L* + *L* <sup>1</sup> *u*1

<sup>a</sup>(1*u*1) 1)(1 <sup>+</sup>

}.

1a <sup>a</sup> (1 <sup>+</sup>

2(*au*<sup>1</sup> <sup>+</sup> *<sup>a</sup>*0) sinh

j(*L L* 1) 2(*au*<sup>1</sup> <sup>+</sup> *<sup>a</sup>*0) <sup>+</sup>

j(*L L* 1) 2(*au*<sup>1</sup> <sup>+</sup> *<sup>a</sup>*0) <sup>×</sup>

> *a*0 *au*<sup>0</sup> )

.

Silicon Carbide Power MESFET http://dx.doi.org/10.5772/51085 305

where

$$\begin{split} f^{-1} = 1 + \frac{1}{2m\_{L\_{-1}}V\_{P}} \Big[ \frac{2E\_{S}a}{\pi} \sinh \frac{\pi(L - L\_{-1})}{2(au\_{1} + a\_{0})} - \frac{E\_{S}a(L - L\_{-1})}{(au\_{1} + a\_{0})} \cosh \frac{\pi(L - L\_{-1})}{2(au\_{1} + a\_{0})} \Big] - \\ \frac{E\_{S}LZ}{2m\_{L\_{-1}}V\_{P}} \cosh \frac{\pi(L - L\_{-1})}{2(au\_{1} + a\_{0})} \times m\_{L\_{-1}} = u\_{1} + a\_{0} \Big[ a - \frac{2}{\gamma} \Big] \\ \left[ \frac{2u\_{1}(1 - \gamma)}{\gamma} + \frac{\langle u\_{1}^{2} - u\_{0}^{2} \rangle - \frac{2}{\gamma} \Big| \pi(1 - u\_{1})^{2} \Big|}{\gamma (1 - u\_{1})^{2}} \right] - \frac{a\_{0}}{\gamma u} \Big[ \frac{\langle u\_{1}^{2} - u\_{0}^{2} \rangle - \langle u\_{1} - u\_{0} \rangle}{(1 - u\_{1})^{2}} - 2(1 - \gamma) \Big] \end{split}$$

The expression of transconductance for the saturation region is equation (15)

$$g\_{ms} = -\frac{3\gamma I\_P}{2Zm\_{L\_\\_1}V\_P}(k+1)\tag{15}$$

where

$$\begin{split} h &= -\frac{1}{2m\_{L\_{-1}}V\_{P}} \Bigg[ \frac{2E\_{S}a}{\pi} \sinh \frac{\pi(L-L\_{-1})}{2(au\_{1}+a\_{0})} - \frac{E\_{S}a(L-L\_{-1})}{(au\_{1}+a\_{0})} \cosh \frac{\pi(L-L\_{-1})}{2(au\_{1}+a\_{0})} \Bigg] + \\ & & \frac{E\_{S}LZ}{2m\_{L\_{-1}}V\_{P}} \cosh \frac{\pi(L-L\_{-1})}{2(au\_{1}+a\_{0})} \times \\ \Bigg[ \left[ \frac{2u\_{1}(1-\gamma)}{\lambda} + \frac{(u\_{1}^{2}-u\_{0}^{2})^{2} - \frac{2}{3}(u\_{1}^{4})^{3}-u\_{0}^{3})}{\gamma(1-u\_{1})^{2}} \Bigg] - \frac{a\_{0}}{\gamma a} \Bigg[ \frac{(u\_{1}^{2}-u\_{0}^{2})^{2}-(u\_{1}-u\_{0})}{(1-u\_{1})^{2}} - 2(1-\gamma) \Bigg] \\ & & - \frac{u\_{0}E\_{S}LZ}{m\_{0}V\_{P}} \cosh \frac{\pi(L-L\_{-1})}{2(au\_{1}+a\_{0})} \Bigg[ \frac{1-u\_{0}}{\gamma(1-u\_{1})} - 1 \Bigg[ \left(1+\frac{a\_{0}}{a\_{0}}\right)^{2} \Bigg] \end{split}$$

+z"%\* z0\$!z#0!w/+1.!z,%0\*!\_z0\$!z)#\*%01 !z+"z0\$!z\$.#!z%\*z0\$!z !,(!0%+\*z(5!.z1\*¥ !.z0\$!z#0!z%/z\*!! ! ^z 0z\*z!z !.%2! z".+)z0\$!z,+0!\*0%(z %/0.%10%+\*z%\*z0\$!z !,(!0%+\*z(5¥ er which is obtained by solving the 2-D Poisson's equation.

The expression of the gate-source capacitance is equation (16)

$$\mathbf{C}\_{\mathcal{g}^{\rm s}} = \mathbf{C}\_{\mathcal{g}^{\rm s}1} + \mathbf{C}\_{\mathcal{g}^{\rm s}2} + \mathbf{C}\_{\mathcal{g}^{\rm s}3} \tag{16}$$

where

Similarly, the transconductance for the linear region is equation (13)

0

*a* .

*m V*

*P*

*d P*

304 Physics and Technology of Silicon Carbide Devices

*ml*

where

where

*f* <sup>1</sup> =1 +

{ <sup>2</sup>*u*1(1a) a

where

1 2*mL* <sup>1</sup> *VP*

> + (*u*1 <sup>2</sup> *u*<sup>0</sup> 2)<sup>2</sup> 3 (*u*1 <sup>3</sup> *u*<sup>0</sup> 3)

2*ES a* <sup>j</sup> sinh

*<sup>m</sup>*<sup>0</sup> <sup>=</sup>*u*<sup>0</sup> <sup>+</sup> *<sup>a</sup>*<sup>0</sup>

2 2 3 3 0 0 <sup>0</sup> 00 0

<sup>2</sup> (1 ) ( )( ) ( ) 2 ( ) 3( ) <sup>3</sup>

' ( )

*dd d <sup>d</sup> d d P d*

*a a <sup>a</sup> u Zu u u Zu u Z u u u I u a a <sup>a</sup> <sup>g</sup> m V <sup>a</sup> Zu u Z u u <sup>a</sup>*

2 2 3 3 0 0 <sup>0</sup> <sup>0</sup> 0 0 0 00 <sup>0</sup>

<sup>2</sup> (1 ) ( )( ) ( ) 2 ( ) 3( ) <sup>3</sup>

From Eq.(10), the drain conductance for the saturation region is obtained expressed by Eq.(14)

*VP*

*ES a*(*L L* 1) (*au*<sup>1</sup> <sup>+</sup> *<sup>a</sup>*0) cosh

> *ES LZ* 2*mL* <sup>1</sup> *VP* cosh

> > 2)(*u*<sup>1</sup> *u*0)

(1*u*1)<sup>2</sup> 2(1a) }

*gds* <sup>=</sup> <sup>3</sup>a*IP* 2*ZmL* <sup>1</sup>

a*a*

The expression of transconductance for the saturation region is equation (15)

*gms* <sup>=</sup> <sup>3</sup>a*IP* 2*ZmL* <sup>1</sup>

(*u*1 <sup>2</sup> *u*<sup>0</sup>

*VP*

j(*L L* 1) 2(*au*<sup>1</sup> <sup>+</sup> *<sup>a</sup>*0)

<sup>a</sup>(1*u*1)2 *<sup>a</sup>*<sup>0</sup>

*a a <sup>a</sup> u Zu u u Zu u Z u u u I u a a <sup>a</sup>*

' ( ) <sup>2</sup>

*dd d <sup>P</sup>*

1

2 2 <sup>0</sup> 0 0

2 2 <sup>0</sup> 0 0 ( )2 ( ) *d d <sup>a</sup> Zu u Z u u <sup>a</sup>* ' ( )

1 ( )2 ( )

' ( )

*d d*

2

*f* (14)

*mL* <sup>1</sup>

(*k* + 1) (15)

<sup>=</sup>*u*<sup>1</sup> <sup>+</sup> *<sup>a</sup>*<sup>0</sup>

*a* .

j(*L L* 1) 2(*au*<sup>1</sup> <sup>+</sup> *<sup>a</sup>*0)

j(*L L* 1) 2(*au*<sup>1</sup> <sup>+</sup> *<sup>a</sup>*0) <sup>×</sup> (13)

$$\begin{split} \mathbf{C}\_{\mathcal{S}^{2}} &= \frac{4\varepsilon W \mathbf{L} \cdot V\_{P} I\_{P}}{a \varPi} \Bigg[ + \frac{\frac{-g\_{m}}{I\_{D}} \Big[ (1 - \frac{a\_{0}}{a})(u\_{1} - u\_{0})^{2} - \frac{3}{4}(u\_{1} \cdot u\_{0}) + \frac{3a\_{0}}{a} \left( u\_{1} 2 - u\_{0} \right)^{2} \Bigg] \\ &+ \frac{3u\_{1}}{2m\_{\perp} \cdot V\_{P}} (u\_{1} + \frac{a\_{0}}{a})(1 - u\_{1} - \frac{Z I\_{D}}{2m\_{\parallel}V\_{P}})(k + 1) - \frac{3a\_{0}}{2m\_{0}V\_{P}} (u\_{0} + \frac{a\_{0}}{a})(1 - u\_{0} - \frac{Z I\_{D}}{3I\_{P}}) \Bigg] \\ \mathbf{C}\_{\mathcal{S}^{2}} &= \frac{2\varepsilon W \mathbf{L} \cdot Z \boldsymbol{u}\_{1}}{a} \Bigg[ \frac{g}{2\pi m\_{\perp}} \frac{1}{u\_{1}} \mathbf{u}\_{1} + (k + 1) \frac{\pi u\_{1}}{m\_{0}} \frac{\Gamma(-u\_{0})}{\gamma(1 - u\_{1})} + \frac{1 - \gamma}{\gamma} \bigg] \Bigg( 1 + \frac{a\_{0}}{a u\_{0}} \Bigg) \\ &\left. \frac{k + 1}{2m\_{1} \cdot V \cdot \nu} \Bigg[ \frac{1 - \cos \pi \frac{\pi(L - L\_{1})}{2(au\_{1} + a\_{0})} \frac{\pi(1 - u\_{1})}{2(au\_{1} + a\_{0})^{2}} \sinh^{-1} \Bigg] \Bigg] \\ \mathbf{C}\_{\mathcal{S}^{3}} &= -\varepsilon \operatorname$$

Using their model, Yang et al calculate the *I-V* \$.0!.%/0%/z\* zz/)((z/%#\*(z\$.0!.¥ istics of the proposed 4H-SiC MESFETs with a gate-buffer layer of 0.2 µm. The results are shown in Fig.15 to Fig.18.

Fig.15 shows the I-V characteristics of the proposed 4H-SiC MESFETs. For a specified gate bias, the drain currents achieved in their proposed device are larger than that in the conventional one. For instance, the maximum saturation drain current is 0.18 A, which is larger than U.1 A in the conventional structure. Since the total depletion layer is composed of the completely depleted gate-buffer layer and the depletion layer in the channel layer, the part in the channel layer shrinks when there exists a gate-buffer layer, compared to the conventional structure, as shown in Fig. 8. As a result, the effective channel width is increased and a larger current occurs in the Buffer-Gate MESFETs than in the conventional structure.

Figure 15. Calculated and experimental I-V characteristics, for the conventional and buffer-gate structures, V gs=0,-2,-4,-6,-8 V.

Fig. 16, 17 and 18 show the effect of the gate-buffer layer thickness on the small signal parameters. The transconductance, gate-source capacitance and channel resistance are decreased, while the drain conductance is increased with the inserted lower doped gate-buffer layer thickness (completely depleted) because the total depletion layer thickness under the gate is increased but the part in the channel is decreased, as are depicted in Fig.16 and Fig. 17. The cutoff frequency (f 7) is increased with the gate-butter layer thickness slowly because the decrease of the transconductance is overcome by the decrease of the gate-source capacitance. Since the decrease of the channel resistance is more dominant than the increase of the drain conductance with the gate buffer layer thickness, the maximum oscillation frequency (f max) is increased more rapidly than the cutoff frequency. The results show that f r and f max are significantly improved, compared with those of the conventional structure. Therefore, the buffer-gate structure has better frequency performance than that of the similar device based on the conventional structure.

Figure 16. Dependence of transconductance g, and gate-source capacitance C , on the gate buffer layer thickness, V gs=0 V, V as=30 V.

Figure 17. Dependence of drain conductance g, and channel resistance R ¿ on the gate buffer layer thickness, V gs=0 V, V ds=30 V.

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Figure 18. Dependence of cutoff frequency *f*T and maximum oscillation frequency *f* maxGFL@=?9L=:M>>=JD9Q=JL@A;Cs ness, *V* gs=0 V, *V* ds=30 V.
