**4. Summary and Future Direction for Thin Silicon Wafer Processing**

#### **4.1. Summary**

then starts improving due to the dominating effect of Al BSF over the passivation with SiNx. As the metal coverage area on the rear surface reaches as high as 85%, an improvement in infrared response with net improvement in Isc by ~ 0.16 A has been observed. This indicates that there is dominance of Al-BSF passivation in comparison to the dielectric passivation on the cells fabricated with screen printed local back contact, especially when the rear metal coverage reaches 45% or more but when the metal coverage comes below 45%, the effect of

All the results suggest that the passivation with dielectric film on the rear surface is a must for local back contact formation by screen printing of Al paste whereas the role of such die‐ lectric passivation becomes significant for Al printed local back contact only if the metal cov‐ ered area on the rear surface goes below 45%. These results indicate a suitable rear metal covered area for high efficiency thin c-Si solar cells with local back contact in conjunction with dielectric passivation with dielectric film of SiNx and were found to be in accordance

**Figure 8.** Comparison of the illuminated current-voltage (LIV) characteristics of the cells fabricated with local back contact through the opening in SiNx film on rear surface by varying the peak temperature of the co-firing profile, as

> **Tp (oC) Rs (mΩ) FF (%) η (%) Voc(mV) Isc (Amp)** 12 67 11.5 576.2 4.40 11 71 12.4 575.6 4.45 8 75 13.0 576.8 4.38 24 60 10.1 574.0 4.35 16 67 8.4 564.5 3.77

**Table 6.** Comparison of the performance parameters of the cells fabricated with local back contact through the opening window on SiNx film on rear surface by varying the peak temperature of the co-firing profile, where Tp is

the dielectric passivation becomes dominant.

124 Photodiodes - From Fundamentals to Applications

with the results obtained by simulation in ref [28].

indicated with the traces.

peak firing temperature.

**Figure 9.** Process sequence of wafer cleaning, saw damage removal and surface texturing of c-Si wafer.

Wafer cleaning for saw damage removal is a fundamental step for c-Si solar cell fabrication. Texturing the top surface of the wafer reduces reflection loss of incident light, as well as in‐ creased effective surface area of the wafer for light trapping, light absorption, carrier collec‐ tion inside the wafer. Surface passivation with silicon nitride layer increases carrier lifetime and further reduces reflectivity of the top surface as it also works as an anti-reflection coat‐ ing. It also gives protection of the sensitive and thin top n+ layer from environmental degra‐ dation. Co-firing at two different temperatures for the top and the bottom surface of the wafer may be necessary as top surface needs lowed co-firing temperature than the bottom one. Because of the thin n+ layer at the top of the cell and thin silicon nitride layer, the Ag top contact may make electrical shorting through the n+/p interface, if co-firing is done at higher temperature. The Al/Ag paste that is used for back contact works for electrical con‐ tact as well as p+ doping of Si at the back surface. Al is a group III element in the periodic table so it works as a p-type dopant for Si. After the high temperature co-firing, the Si-Al alloy that is formed at the back of the cell acts as a p+ layer and creates strong back surface field so the photo generated holes are efficiently collected during light illumination.

in the co-firing stage, results in higher ramp-up rate for temperature, that greatly enhances Voc. By studying the results of our five sets of experiments, we determined certain ap‐

Fabrication of Crystalline Silicon Solar Cell with Emitter Diffusion, SiNx Surface Passivation and Screen Printing of

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127

http://dx.doi.org/10.5772/51065

**1.** As the temperature ramp-up rate went higher, we could obtain better uniformity of the

**3.** As the emitter sheet resistance increases, the open circuit voltage decreases with the de‐ crease in dopant concentration in the emitter, although the short circuit current is in‐ creased, that is attributed to the improvement of the short wavelength response, more light entering the cell active region and to a reduction of recombination in the front sur‐

**4.** The peak temperature of the wafer was optimized for the shorter the firing time. It re‐ sults in increased minority carrier density, which in turn increases the open circuit volt‐ age. We investigated the optimal firing conditions for different sheet resistance, temperature, and belt speed, and within the profile window of the firing process, we obtained a high Voc (>620 mV) and fill factor (>77%) for a range of different sheet resist‐

**5.** By narrowing the spacing between gridlines, the series resistance and the fill factor of

However, the short circuit current falls because of shadow effect of the metal electrodes. In the case of low series resistance, we can expect to improve the fill factor, while the short cir‐

**Figure 12.** Process steps for metallization of the solar cell by screen printing (SP). In our system, the peak temperature

**2.** A higher belt speed tends to reduce the overall leakage current of a wafer.

proaches for improving the open circuit voltage and fill factor:

BSF layer.

face.

was 759.5°C.

ance emitters.

the cell got enhanced.

cuit current decreased because of the shading loss.

**Figure 10.** Process flow for doping or emitter diffusion of cleaned and textured wafer. The PSG removal can be carried out after the pre-deposition (as shown above), or it it can be done after the drive in operation. In the latter case the drive-in can be the third step (the PSG removal will be the fourth step), and all other steps remain in order. The emitter diffusion for this latter case has been depicted in Table 1.

**Figure 11.** SiNx, ARC deposition on the wafer by RF PECVD.

Out of several approaches to improve the Voc and FF, increasing the ramp-up rate of temper‐ ature and setting the belt speed along the heating furnace properly, makes it possible to get a higher Voc. This increase in Voc may be because of reduction in the deterioration due to the effect of thermal stress on the wafer. In presence of excess thermal stress small cracks in the wafer may develop, resulting in a high sheet resistance and low open circuit voltage. Thus optimizing the drive-in condition for low sheet resistance is necessary. The faster belt speed in the co-firing stage, results in higher ramp-up rate for temperature, that greatly enhances Voc. By studying the results of our five sets of experiments, we determined certain ap‐ proaches for improving the open circuit voltage and fill factor:


ing. It also gives protection of the sensitive and thin top n+ layer from environmental degra‐ dation. Co-firing at two different temperatures for the top and the bottom surface of the wafer may be necessary as top surface needs lowed co-firing temperature than the bottom one. Because of the thin n+ layer at the top of the cell and thin silicon nitride layer, the Ag top contact may make electrical shorting through the n+/p interface, if co-firing is done at higher temperature. The Al/Ag paste that is used for back contact works for electrical con‐ tact as well as p+ doping of Si at the back surface. Al is a group III element in the periodic table so it works as a p-type dopant for Si. After the high temperature co-firing, the Si-Al alloy that is formed at the back of the cell acts as a p+ layer and creates strong back surface

field so the photo generated holes are efficiently collected during light illumination.

**Figure 10.** Process flow for doping or emitter diffusion of cleaned and textured wafer. The PSG removal can be carried out after the pre-deposition (as shown above), or it it can be done after the drive in operation. In the latter case the drive-in can be the third step (the PSG removal will be the fourth step), and all other steps remain in order. The emitter

Out of several approaches to improve the Voc and FF, increasing the ramp-up rate of temper‐ ature and setting the belt speed along the heating furnace properly, makes it possible to get a higher Voc. This increase in Voc may be because of reduction in the deterioration due to the effect of thermal stress on the wafer. In presence of excess thermal stress small cracks in the wafer may develop, resulting in a high sheet resistance and low open circuit voltage. Thus optimizing the drive-in condition for low sheet resistance is necessary. The faster belt speed

diffusion for this latter case has been depicted in Table 1.

126 Photodiodes - From Fundamentals to Applications

**Figure 11.** SiNx, ARC deposition on the wafer by RF PECVD.


However, the short circuit current falls because of shadow effect of the metal electrodes. In the case of low series resistance, we can expect to improve the fill factor, while the short cir‐ cuit current decreased because of the shading loss.

**Figure 12.** Process steps for metallization of the solar cell by screen printing (SP). In our system, the peak temperature was 759.5°C.

#### **4.2. Future Direction for Thin Silicon Wafer Processing**

Thin silicon wafer is more economical because it consumes less Si material, and results in more efficient solar cell because of higher built in field. Cost of silicon is one of the major expenses in c-Si solar cell production and thus with less consumption of semiconductor mass in the form of thinner wafer, the cost of production can be significantly reduced.

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One problem that thin wafer may face is bowing during the co-firing process, and hence cre‐ ation of additional structural defects. Due to unequal thermal expansion of Si and Al back electrode these defects may be created in the wafer. The LBC approach may be more suita‐ ble for such cells.

Resistance of screen printed front electrode provides additional element to the series resist‐ ance. Each electrode creates a shadow to the cell that reduces total number of electronhole pair generation under constant illumination. Thus, although decreasing the spacing among the electrodes help reducing series resistance, yet shadow effect leads to reduced total number of electron-hole pair generation. For this, a finger with good conducting ma‐ terial and a high aspect ratio is preferable. Usually glass frit Ag/Al paste is used in the elec‐ trode design. If Ag/Al particles in the frit is bigger in size and less dense, and firing temperature profile is not best suited then an insulating layer between Si and Ag/Al elec‐ trode may form. This may be avoided by using Ag/Al nano-particles in the paste, with a higher number density of the particles.

Another method that has partly been adopted in commercial production is selective emitter design. In this method a local doping pattern is designed before phosphorus doping through diffusion chamber treatment. Ag electrodes at the front surface are fabricated over this so that a highly doped local semiconductor region is formed around the Ag-electrode after high temperature co-firing. In this way a barrier potential at metal semiconductor junc‐ tion can be reduced. This electrode structure may bring the screen printed solar cell technol‐ ogy close to buried contact solar cell with one additional process step.

### **Author details**

S. M. Iftiquar1 , Youngwoo Lee1 , Minkyu Ju1 , Nagarajan Balaji2 , Suresh Kumar Dhungel1 and Junsin Yi1,2\*

\*Address all correspondence to: yi@yurim.skku.ac.kr

1 College of Information and Communication Engineering, Sungkyunkwan University, Re‐ public of Korea

2 Department of Energy Science, Sungkyunkwan University, Republic of Korea
