**2. Fabrication Process for Industrially Applicable Crystalline Silicon Solar Cells**

The fabrication of our c-Si solar cell starts with a 300μm thick, (100) oriented Czochralski Si (or Cz-Si) wafer. The wafers generally have micrometer sized surface damages, that needs to be removed. After the damage removal, the wafer surface shows high optical reflectivity, for which an anti-reflection coating (ARC) is necessary. Furthermore, the top surface was tex‐ tured by chemical etching before an ARC was deposited.

For a p-type c-Si substrate, an n-type top layer while for an n-type c-Si substrate a p-type top layer acts as emitter. A thermal diffusion is commonly used for emitter diffusion [4]. After the emitter diffusion, the edge isolation was carried out, as otherwise the top and the bottom surfaces of the wafers remain electrically shorted.

A suitable thin dielectric coating at the front and back of the wafers were given to passivate surface defects. As the wafer becomes covered with a dielectric layer, an electrical connec‐ tion to the cell becomes necessary. Ag and Al metal electrodes were formed by using screen printing of Al pastes and co-firing at a suitable temperature.

#### **2.1. Wafer Cleaning and Saw Damage Removal**

In order to remove the organic contaminants from the c-Si wafer surfaces, we used 12% NaOCl solution and cleaned the wafers ultrasonically at room temperature (RT) for five minutes. This cleans the wafer surface with an approximate Si etching rate of 500nm/min [5]. The sur‐ face damages to the wafers were removed through isotropic etching with a concentrated sol‐ ution of NaOH in de-ionized water (DI-W). DI-W helps the NaOH to break in Na+ and OHions in the solution. An 8% NaOH solution, at 80°C temperature for about 7 minutes of etching removes the surface damages. This saw damage removal step, etches out about 5 micro me‐ ter Si from wafer surface. After that the wafers were rinsed in HCl(10%) for 1 min, DI-W for 1 min, HF(10%) for 1 min, DI-W for 1 min.

#### **2.2. Surface Texturing**

Anisotropic chemical etching of Si (100) oriented wafers give rise to textured surface. The characteristics of the etching depends upon, time of etching, etching rate, temperature, com‐ ponents of the solution and its concentration. With a dilute NaOH solution containing isopropyl alcohol (IPA) and DI-W, the Si(100) oriented smooth wafers can grow pyramidal surface texture at 80°C temperature [6]. The surface texturing was performed by asymmetric etching of front surface of the wafers, in a dilute alkaline solution, as against the concentrat‐ ed solution used for saw damage removal. The loss in mass of each wafer were estimated from the mass of the wafer measured with a microbalance before and after texturing, which subsequently led to the estimation of the etched thickness of the wafer and hence etch rate. Optical microscopic observations, SEM images, and laser scanning were the tools that were used for the characterization of the textured surface morphology. Ultraviolet visible (UV-Vis) spectrophotometry was used to estimate the retro-reflectivity of the textured surface.

The c-Si solar cells fabricated on the high quality silicon wafers, having selective emitter on the front and local contact on the rear surface [3] shows higher η, but the required additional measures to be taken for the production of such solar cells may substantially increase the

Presently the cost of the silicon wafer alone covers >20% of the total cost of solar cell produc‐ tion, so there may be a technology available in future, by which a large scale production of

**2. Fabrication Process for Industrially Applicable Crystalline Silicon**

The fabrication of our c-Si solar cell starts with a 300μm thick, (100) oriented Czochralski Si (or Cz-Si) wafer. The wafers generally have micrometer sized surface damages, that needs to be removed. After the damage removal, the wafer surface shows high optical reflectivity, for which an anti-reflection coating (ARC) is necessary. Furthermore, the top surface was tex‐

For a p-type c-Si substrate, an n-type top layer while for an n-type c-Si substrate a p-type top layer acts as emitter. A thermal diffusion is commonly used for emitter diffusion [4]. After the emitter diffusion, the edge isolation was carried out, as otherwise the top and the bottom

A suitable thin dielectric coating at the front and back of the wafers were given to passivate surface defects. As the wafer becomes covered with a dielectric layer, an electrical connec‐ tion to the cell becomes necessary. Ag and Al metal electrodes were formed by using screen

In order to remove the organic contaminants from the c-Si wafer surfaces, we used 12% NaOCl solution and cleaned the wafers ultrasonically at room temperature (RT) for five minutes. This cleans the wafer surface with an approximate Si etching rate of 500nm/min [5]. The sur‐ face damages to the wafers were removed through isotropic etching with a concentrated sol‐ ution of NaOH in de-ionized water (DI-W). DI-W helps the NaOH to break in Na+ and OHions in the solution. An 8% NaOH solution, at 80°C temperature for about 7 minutes of etching removes the surface damages. This saw damage removal step, etches out about 5 micro me‐ ter Si from wafer surface. After that the wafers were rinsed in HCl(10%) for 1 min, DI-W for

Anisotropic chemical etching of Si (100) oriented wafers give rise to textured surface. The characteristics of the etching depends upon, time of etching, etching rate, temperature, com‐

silicon solar cells from a thin wafer ( < 200μm) will be possible

tured by chemical etching before an ARC was deposited.

printing of Al pastes and co-firing at a suitable temperature.

surfaces of the wafers remain electrically shorted.

**2.1. Wafer Cleaning and Saw Damage Removal**

1 min, HF(10%) for 1 min, DI-W for 1 min.

**2.2. Surface Texturing**

production cost.

106 Photodiodes - From Fundamentals to Applications

**Solar Cells**

The etching depends mainly on two processes. One is the rate of the reaction at the surface, and the other is the rate at which reactants diffuse into the surface. These two processes con‐ trol the overall rate of the micro structural growth during the etching. The anisotropic etch‐ ants is expected to etch (110) plane at a faster rate than the (100) plane while the (111) plane etches at a slowest rate [7]. However if chemical composition of the etchant is such that some insoluble residue is formed during etching process (like oxides etc.) then diffusion of etchant into the Si will be hindered and hence etching will not happen as expected.

IPA enhances surface diffusion, so a rapid etching can take place in presence of IPA in the solution [8]. The NaOH etches silicon crystal planes differently, mostly because of different atomic concentration in different crystallographic planes. So, at a lower NaOH concentration the selective etching process helps to create textured surface of the wafer. The chemical reac‐ tion that takes place is as follows,

$$\text{Si} + 2\text{NaOH} + \text{H}\_2\text{O} \rightarrow \text{Na}\_2\text{SiO}\_3 + 2\text{H}\_2\tag{1}$$

The sodium silicate (Na2SiO3) is soluble in water and thus Si surface remains devoid of any deposition. At 80o C temperature, (100) planes etch about two orders of magnitude faster than (111) planes [9]. For a (100) silicon wafer, a solution of NaOH, IPA, DI-W creates square based four sided pyramids consisting of sections of (111) planes which form internal angles of 54.7° with the (100) surface.

The degree of isotropy is sensitive to the concentration of the solution. While a 8% NaOH solution at 80°C temperature etches silicon isotropically to achieve a polished wafer surface, a 2% NaOH, 8% IPA solution at 80°C temperature etches anisotropically to a square based pyramidal surface texture.

#### **2.3. Phosphorus Diffusion for p-n Junction Formation**

The thermal diffusion of phosphorus is necessary to create an n-type emitter to the p-type wafer. The diffusion depends on various factors, of which temperature and gaseous envi‐ ronment is most important [10]. In oxygen environment and at 850°C temperature, the diffu‐ sion coefficient (D) can be approximated as D~0.0013μm2 /hr. The phosphorus diffusion leads to formation of n+ type emitter at the top surface of the wafer. The diffusion was car‐ ried out in two stages, pre-deposition and drive-in [11-13]. At the pre-deposition stage, liq‐ uid POCl3 was evaporated by bubbling N2 gas into the liquid. The POCl3 evaporates and gets deposited at the surface of the wafers. In presence of oxygen, phosphosilicate glass (PSG) is formed at the 850°C temperature. Phosphosilicate glass or PSG is phosphorus dop‐ ed silicon dioxide, a hard material formed at the top surface of Si wafer. PSG formation rate is about 15nm in 30 minutes.

After that, in the drive-in stage, the wafers were heated at 850°C temperature for 7 mins, 0.3Torr pressure in presence of oxygen, when the P atoms from the n+-type top layer diffus‐ es deeper into the wafer, forming a deeper junction. Details of the reaction is given below

$$\text{PCCL}\_3\text{(liquid)} + \text{N}\_2\text{(bubble)} \rightarrow \text{PCl}\_3\text{(vapor)} \quad \text{(pre-deposition)}\tag{2}$$

$$\text{4POCl}\_3 + \text{ 3O}\_2 \rightarrow \text{2P}\_2\text{O}\_3 + 6\text{Cl}\_2 \tag{3}$$

**Table 1.** A typical condition for phosphorus diffusion used in this study, using POCl3 vapor as a source gas, here 'lpm'

Fabrication of Crystalline Silicon Solar Cell with Emitter Diffusion, SiNx Surface Passivation and Screen Printing of

The edge isolation was carried out after screep printing of acid barrier paste as a mask, by the reactive ion etching [14-15]. However, it can also be performed by wet etching [16-17] with HF, HNO3 and CH3COOH acidic solution in the 1:3:1 volume ratio. Then the wafers were dipped into the acid solution for 1.5 – 2 minutes, after which the stack was rinsed in DI-W. Then the wafers were thoroughly rinsed with DI-W for five minutes and later spin

Light reflection as well as electronic defects at the front surface are undesirable, that needs to be minimized. The hydrogenated SiNx layer also acts as a high quality silicon surface pas‐ sivator [18]. It has been observed that, more than 35% of the incident light gets reflected back from a bare silicon surface, and a significant amount of incident light reflects from the silicon surface even after surface texturing. For a single layer ARC, the wavelength (λ0) at which the anti-reflection is most effective at normal incidence, can be expressed as: λ0 = 4μl

μo and μ2 are the refractive indices of the medium above the ARC and that of the substrate

nm, the desired thickness of silicon nitride film with μ1 = 1.96 would be 700 Å, taking air (μ = 1) as ambient above the cells [19]. The thicknesses and refractive indices of the SiNx films prepared by PECVD under different gas flow ratios were characterized by Spectroscopic El‐

The parameters for the SiNx depositions were: chamber pressure 0.6 Torr, deposition tem‐ perature 300°C, RF power density 0.08 W cm-2 at a 13.56 MHz frequency, silane (SiH4) and ammonia (NH3) source gases, deposition time 4 minutes, with deposition rate of 3 Å/s. The Si atom of SiNx mostly comes from silane source gas in RF PECVD process, following the

are refractive index, and thickness of the ARC respectively. The reflec‐

2

–μoμ2 ) / (μ1 <sup>2</sup>

+ μ0μ2)] 2

= (μoμ2) ½. At λ = 550

, where

Electrode

109

http://dx.doi.org/10.5772/51065

stands for liter per minutes.

dl

, where μl

lipsometry.

and dl

reaction, 3 SiH4 + 4NH3 → Si3N4 + 12H2.

**2.4. Edge Isolation by Wet Chemical Etching**

dried to make it ready for silicon nitride film deposition.

**2.5. Antireflection Coating and Front Surface Passivation**

tance R of the top surface of a solar cell is given by : R = [(μl

below the ARC, respectively. For zero reflectance, i.e. R = 0, it gives: μl

$$2\text{P}\_2\text{O}\_5 + 5\text{Si} \rightarrow 4\text{P} + 5\text{SiO}\_2 \text{ (drive-in)}\tag{4}$$

$$\text{P + 3Si} \rightarrow \text{n-type doped Si} \tag{5}$$

For gaseous diffusion with POCl3, the p-type silicon wafers were loaded into a quartz boat, which was slowly moved into the middle of a fused quartz tube in a heated horizontal fur‐ nace. The boat, which can hold tens of wafers, was moved slowly into the tube so that the wafers do not suffer large temperature gradients and warping. Furnace temperature for the diffusion was held at about 800°C, with a variation across the length of the boat of not more than 2°C.

When the PSG was deposited in the pre-deposition stage, the dopant profile leads to a shal‐ low junction depth and a high surface concentration. In the drive-in stage, a deeper junction was formed as phosphorus atoms diffuse deeper, thus thicker emitter and a lower surface concentration of dopant was achieved. The junction depth is defined as the depth where the phosphorus and boron concentrations are equal (as boron already existed in p-Si wafers).

Table 1 shows details of P-diffusion process. A shorter pre-deposition of only 7 minutes at 850°C and a drive-in of about 20 min at 850°C temperature, shows good result. It is to be noted that, a relatively deeper junction and the dead layer near the top wafer surface de‐ grade blue response of solar cells. The PSG was removed by washing the wafer in a 10% HF solution for one minute.

The heated quartz tube, used for pre-deposition and drive-in, were periodically cleaned with HCl vapor in an N2 stream.


**Table 1.** A typical condition for phosphorus diffusion used in this study, using POCl3 vapor as a source gas, here 'lpm' stands for liter per minutes.

#### **2.4. Edge Isolation by Wet Chemical Etching**

leads to formation of n+ type emitter at the top surface of the wafer. The diffusion was car‐ ried out in two stages, pre-deposition and drive-in [11-13]. At the pre-deposition stage, liq‐ uid POCl3 was evaporated by bubbling N2 gas into the liquid. The POCl3 evaporates and gets deposited at the surface of the wafers. In presence of oxygen, phosphosilicate glass (PSG) is formed at the 850°C temperature. Phosphosilicate glass or PSG is phosphorus dop‐ ed silicon dioxide, a hard material formed at the top surface of Si wafer. PSG formation rate

After that, in the drive-in stage, the wafers were heated at 850°C temperature for 7 mins, 0.3Torr pressure in presence of oxygen, when the P atoms from the n+-type top layer diffus‐ es deeper into the wafer, forming a deeper junction. Details of the reaction is given below

For gaseous diffusion with POCl3, the p-type silicon wafers were loaded into a quartz boat, which was slowly moved into the middle of a fused quartz tube in a heated horizontal fur‐ nace. The boat, which can hold tens of wafers, was moved slowly into the tube so that the wafers do not suffer large temperature gradients and warping. Furnace temperature for the diffusion was held at about 800°C, with a variation across the length of the boat of not more

When the PSG was deposited in the pre-deposition stage, the dopant profile leads to a shal‐ low junction depth and a high surface concentration. In the drive-in stage, a deeper junction was formed as phosphorus atoms diffuse deeper, thus thicker emitter and a lower surface concentration of dopant was achieved. The junction depth is defined as the depth where the phosphorus and boron concentrations are equal (as boron already existed in p-Si wafers).

Table 1 shows details of P-diffusion process. A shorter pre-deposition of only 7 minutes at 850°C and a drive-in of about 20 min at 850°C temperature, shows good result. It is to be noted that, a relatively deeper junction and the dead layer near the top wafer surface de‐ grade blue response of solar cells. The PSG was removed by washing the wafer in a 10% HF

The heated quartz tube, used for pre-deposition and drive-in, were periodically cleaned

POCl3(liquid) + N2(bubble)→POCl3(vapor) (pre−deposition) (2)

3 2 25 2 4POCl 3O 2P O 6Cl +® + (3)

2P2O5 + 5Si→4P + 5SiO2 (drive-in) (4)

P + 3Si→n−type doped Si (5)

is about 15nm in 30 minutes.

108 Photodiodes - From Fundamentals to Applications

than 2°C.

solution for one minute.

with HCl vapor in an N2 stream.

The edge isolation was carried out after screep printing of acid barrier paste as a mask, by the reactive ion etching [14-15]. However, it can also be performed by wet etching [16-17] with HF, HNO3 and CH3COOH acidic solution in the 1:3:1 volume ratio. Then the wafers were dipped into the acid solution for 1.5 – 2 minutes, after which the stack was rinsed in DI-W. Then the wafers were thoroughly rinsed with DI-W for five minutes and later spin dried to make it ready for silicon nitride film deposition.

#### **2.5. Antireflection Coating and Front Surface Passivation**

Light reflection as well as electronic defects at the front surface are undesirable, that needs to be minimized. The hydrogenated SiNx layer also acts as a high quality silicon surface pas‐ sivator [18]. It has been observed that, more than 35% of the incident light gets reflected back from a bare silicon surface, and a significant amount of incident light reflects from the silicon surface even after surface texturing. For a single layer ARC, the wavelength (λ0) at which the anti-reflection is most effective at normal incidence, can be expressed as: λ0 = 4μl dl , where μl and dl are refractive index, and thickness of the ARC respectively. The reflec‐ tance R of the top surface of a solar cell is given by : R = [(μl 2 –μoμ2 ) / (μ1 <sup>2</sup> + μ0μ2)] 2 , where μo and μ2 are the refractive indices of the medium above the ARC and that of the substrate below the ARC, respectively. For zero reflectance, i.e. R = 0, it gives: μl = (μoμ2) ½. At λ = 550 nm, the desired thickness of silicon nitride film with μ1 = 1.96 would be 700 Å, taking air (μ = 1) as ambient above the cells [19]. The thicknesses and refractive indices of the SiNx films prepared by PECVD under different gas flow ratios were characterized by Spectroscopic El‐ lipsometry.

The parameters for the SiNx depositions were: chamber pressure 0.6 Torr, deposition tem‐ perature 300°C, RF power density 0.08 W cm-2 at a 13.56 MHz frequency, silane (SiH4) and ammonia (NH3) source gases, deposition time 4 minutes, with deposition rate of 3 Å/s. The Si atom of SiNx mostly comes from silane source gas in RF PECVD process, following the reaction, 3 SiH4 + 4NH3 → Si3N4 + 12H2.

SiNx can also be deposited on Si surface through forming gas annealing at a higher tempera‐ ture. Forming gas is a mixture of hydrogen (H2) and nitrogen (N2), that were obtained by dissociating ammonia (NH3) at high temperature. In this case the Si atom of SiNx come from the surface atoms of Si wafer. However, due to higher process temperature, this method was avoided, as a higher process temperature may alter distribution of phosphorus atoms and hence the junction depth.

**2.6. Metallization**

fabrication since the early 1970s.

paste and Ferro-33-462 as Ag paste.

from the paste and it was carried out between 350 ~ 510°C.

rapid cooling approach at the end of co-firing.

In order to reduce the production cost of the photovoltaic solar cell, metallization was realiz‐ ed by screen-printing of metal paste on the SiNx coating, followed by a co-firing. Another competing technology for solar cell production is buried-contact technology, that involves laser grooving and metal plating, which is a bit complex procedure, time consuming and may result in a significantly high number of faulty solar cells, because of small imperfection in metallizations, a kind of imperfection that does not make screen printed solar cells faulty.

Fabrication of Crystalline Silicon Solar Cell with Emitter Diffusion, SiNx Surface Passivation and Screen Printing of

Electrode

111

http://dx.doi.org/10.5772/51065

Screen-printing (SP) is cost effective, robust, simple, inexpensive, and fast method of metalli‐ zation of the solar cells [22-23]. It can also be easily automated with a high throughput (ex‐ ceeding about 1,000 wafers per hour). This technique has been widely used for solar cell

For selective emitter formation at the back, etchant material was screen printed before screen printing the metal paste. During the co-firing process the necessary electronic connec‐ tion of the cell layers with the electrodes were formed. We used the Ferro- 53-102 aluminum

Baking of the screen printed wafers were carried out immediately after each printing step in a separate conveyor belt furnace at 150°C. A burn-out process removes the organic binders

The thickness of the Al over the entire back surface of the cell was maintained almost uni‐ form with a variation of ± 2 μm. Wafer bowing is a problem with full Al printing at the back of the wafer, that was minimized to a level below 0.5 mm due to the use the low bow, lead free paste and a thicker wafer (300μm). Bowing happens mainly due to difference in the thermal expansion coefficients of Si and Al pastes (αSi = 7.6 K-1, αAl = 23.8 K-1) and can be avoided by the local back contact (LBC) approach. For the application of this LBC technique in industrial production, an addition step of Ag / Al printing in a pattern of two wide bus bars on the back surface was introduced in order to make back metal contact solderable dur‐ ing the module making process. Despite the simplicity and technical advantages of this process for making fully covered back metal contact and surface passivation through back surface field (BSF) in a single shot, the emerging trend of using thinner wafers to meet the

A problem of Aluminum ball formation was observed during the co-firing process, that was mostly eliminated by flowing sufficient oxygen during the co-firing and also by applying a

Metallization is a very important step for device fabrication because it strongly affects per‐ formance of the solar cell on its short circuit current density (Jsc), open circuit voltage (Voc), series resistance (Rs), shunt resistance (Rsh), and fill factor (FF). At the front surface the metal‐ lization creates electrical connection to thin n+ layer that is covered with SiNx. At the back surface it provides an electrical connection and at the same time it creates a p+ layer. A glass frit present in the Ag paste makes a superior metallization through SiNx film. However, op‐ timization of the co-firing process is critical in obtaining desired metal contact. The peak tem‐

challenges posed by depleting silicon feedstock may put this process at stake.

The recombination rate (Us) at the surface, with surface recombination velocity (S), is related to excess concentration of minority carriers (∆ns) at the surface. Us ≡ S ∆ ns. Therefore, the recombination can be minimized by a reduction of minority carrier type at the surface. Us‐ ing high-low junction n+ pp+ structure the minority carriers at the surface can be reduced [20]. This technology, known as back surface field (BSF), is widely used at the rear surface of solar cells. Another method is the field effect passivation. The fixed charges in a passivation layer repel the minority carriers or the extremely large fixed charges bend the energy band, resulting in an inverting layer at the surface.

The effective lifetime of charge carrier can reflect total effect of bulk and surface recombina‐ tion. For the p-type silicon wafer of thickness W and diffusion coefficient of electron Dn, hav‐ ing front and back surfaces equally passivated, the effective lifetime ( τeff) can be expressed as

$$\frac{1}{\tau\_{\text{eff}}} = \frac{1}{\tau\_{\text{b}}} + \frac{\text{ZS}}{\text{W}} \quad \text{for} \quad \frac{\text{SW}}{\text{D}\_{\text{a}}} < \frac{1}{4} \quad \text{(Low recombination)}\tag{6}$$

and

$$\frac{1}{\tau\_{\text{eff}}} = \frac{1}{\tau\_{\text{b}}} + \text{D}\_{\text{a}} \left(\frac{\Pi}{\text{W}}\right)^{2} \quad \text{for} \quad \frac{\text{SW}}{\text{D}\_{\text{a}}} > 100 \quad \text{\text{(High recombination)}}\tag{7}$$

where τb is minority carrier lifetime at the back surface. By combining the two cases, the ef‐ fective lifetime can be calculated by using above equations with about 5 % deviation from the exact solution [21]

$$\frac{1}{\tau\_{\text{eff}}} = \frac{1}{\tau\_{\text{b}}} + \left[\frac{2\text{S}}{\text{W}} + \text{D}\_{\text{n}} \left(\frac{\text{II}}{\text{W}}\right)^{2}\right] \tag{8}$$

If the parameters, such as bulk lifetime of silicon (Π), wafer thickness, and diffusion co-effi‐ cient of electron are considered to be constant, the measure of effective lifetime gives the di‐ rect measure of S. As the S is an indicator of surface passivation, the measured τeff can also be used as an indicator of the quality of surface passivation in silicon substrate.

#### **2.6. Metallization**

SiNx can also be deposited on Si surface through forming gas annealing at a higher tempera‐ ture. Forming gas is a mixture of hydrogen (H2) and nitrogen (N2), that were obtained by dissociating ammonia (NH3) at high temperature. In this case the Si atom of SiNx come from the surface atoms of Si wafer. However, due to higher process temperature, this method was avoided, as a higher process temperature may alter distribution of phosphorus atoms and

The recombination rate (Us) at the surface, with surface recombination velocity (S), is related to excess concentration of minority carriers (∆ns) at the surface. Us ≡ S ∆ ns. Therefore, the recombination can be minimized by a reduction of minority carrier type at the surface. Us‐

[20]. This technology, known as back surface field (BSF), is widely used at the rear surface of solar cells. Another method is the field effect passivation. The fixed charges in a passivation layer repel the minority carriers or the extremely large fixed charges bend the energy band,

The effective lifetime of charge carrier can reflect total effect of bulk and surface recombina‐ tion. For the p-type silicon wafer of thickness W and diffusion coefficient of electron Dn, hav‐ ing front and back surfaces equally passivated, the effective lifetime ( τeff) can be expressed

where τb is minority carrier lifetime at the back surface. By combining the two cases, the ef‐ fective lifetime can be calculated by using above equations with about 5 % deviation from

If the parameters, such as bulk lifetime of silicon (Π), wafer thickness, and diffusion co-effi‐ cient of electron are considered to be constant, the measure of effective lifetime gives the di‐ rect measure of S. As the S is an indicator of surface passivation, the measured τeff can also

be used as an indicator of the quality of surface passivation in silicon substrate.

structure the minority carriers at the surface can be reduced

(6)

(7)

(8)

hence the junction depth.

110 Photodiodes - From Fundamentals to Applications

ing high-low junction n+

as

and

the exact solution [21]

pp+

resulting in an inverting layer at the surface.

In order to reduce the production cost of the photovoltaic solar cell, metallization was realiz‐ ed by screen-printing of metal paste on the SiNx coating, followed by a co-firing. Another competing technology for solar cell production is buried-contact technology, that involves laser grooving and metal plating, which is a bit complex procedure, time consuming and may result in a significantly high number of faulty solar cells, because of small imperfection in metallizations, a kind of imperfection that does not make screen printed solar cells faulty.

Screen-printing (SP) is cost effective, robust, simple, inexpensive, and fast method of metalli‐ zation of the solar cells [22-23]. It can also be easily automated with a high throughput (ex‐ ceeding about 1,000 wafers per hour). This technique has been widely used for solar cell fabrication since the early 1970s.

For selective emitter formation at the back, etchant material was screen printed before screen printing the metal paste. During the co-firing process the necessary electronic connec‐ tion of the cell layers with the electrodes were formed. We used the Ferro- 53-102 aluminum paste and Ferro-33-462 as Ag paste.

Baking of the screen printed wafers were carried out immediately after each printing step in a separate conveyor belt furnace at 150°C. A burn-out process removes the organic binders from the paste and it was carried out between 350 ~ 510°C.

The thickness of the Al over the entire back surface of the cell was maintained almost uni‐ form with a variation of ± 2 μm. Wafer bowing is a problem with full Al printing at the back of the wafer, that was minimized to a level below 0.5 mm due to the use the low bow, lead free paste and a thicker wafer (300μm). Bowing happens mainly due to difference in the thermal expansion coefficients of Si and Al pastes (αSi = 7.6 K-1, αAl = 23.8 K-1) and can be avoided by the local back contact (LBC) approach. For the application of this LBC technique in industrial production, an addition step of Ag / Al printing in a pattern of two wide bus bars on the back surface was introduced in order to make back metal contact solderable dur‐ ing the module making process. Despite the simplicity and technical advantages of this process for making fully covered back metal contact and surface passivation through back surface field (BSF) in a single shot, the emerging trend of using thinner wafers to meet the challenges posed by depleting silicon feedstock may put this process at stake.

A problem of Aluminum ball formation was observed during the co-firing process, that was mostly eliminated by flowing sufficient oxygen during the co-firing and also by applying a rapid cooling approach at the end of co-firing.

Metallization is a very important step for device fabrication because it strongly affects per‐ formance of the solar cell on its short circuit current density (Jsc), open circuit voltage (Voc), series resistance (Rs), shunt resistance (Rsh), and fill factor (FF). At the front surface the metal‐ lization creates electrical connection to thin n+ layer that is covered with SiNx. At the back surface it provides an electrical connection and at the same time it creates a p+ layer. A glass frit present in the Ag paste makes a superior metallization through SiNx film. However, op‐ timization of the co-firing process is critical in obtaining desired metal contact. The peak tem‐ perature and ramp-up rate during the co-firing process are crucial along with the belt speed that determines residual time of the wafers to various temperature zones. A cylindrical proc‐ ess zone has different local temperature setting and the belt carries the Si wafers at a cer‐ tain speed. The grid pattern of the front electrode has a significant influence on Rs and FF, that demands optimization of co-firing process. With an increase in the sheet resistance (Rsheet) of the emitters, Voc decreases, however Jsc increases, which may be because of the improve‐ ment of blue-response, more light entering the solar cell active region and the reduction of recombination in the front surface. At a faster co-firing condition BSF layers and Ohmic front contacts can preferably be established, because the Rsheet of emitters may remain nearly un‐ changed. We observed a Voc of around 622mV and FF of 80.6% by Suns-Voc measurement.

*2.6.2. Co-firing of Screen Printed Pastes*

350-510o

C.

making the cell unusable.

**Interfacial**

Co-firing of printed metal paste was followed in three major steps, baking, burn- out, and sintering. Baking refers to the process of evaporating solvents of the pastes to avoid the gas bubbling and cracks formation during the high temperature treatment. The baking is carried out immediately after each metal printing step in a separate conveyor belt furnace at 150o

Fabrication of Crystalline Silicon Solar Cell with Emitter Diffusion, SiNx Surface Passivation and Screen Printing of

Burn- out process removes the organic binders from the paste and it was carried out at

The temperature profile for the co-firing cycle can be decided on the basis of the studies of Kim et. al [24]. With improper temperature and the belt speed settings of the co-firing, the metal electrodes can penetrate across the p-n junction, as schematically shown in Fig. 2, thus

The belt furnace used in this system was equipped with the facility to observe and adjust the actual front and back surface temperatures of the wafer by real time measurement, with two different thermocouples. As suggested in ref [24], we tested the co-firing with different tem‐ peratures of front and back surface. However, such a temperature difference may lead to bending of the wafer. So we prefer keeping the temperature of both the surfaces as equal. Proper Ohmic contact formation on the front and Al-Si alloying at back surface for proper

BSF generation are the two significant accomplishments of this single shot method.

**Ag Metal**

**Spiking Junction** 

**Figure 2.** P-N junction of a typical solar cell with Ag metallization on front surface showing the possible cases of

**P-silicon**

**n+ Silicon**

shunting through the p-n junction during co-firing as well as good sintering.

**( 0.1 – 0. 8 μm )**

**short**

C.

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Suns-Voc measurement is a method of estimating open circuit voltage from decay character‐ istics of photo generated charge carriers. This method is generally adopted when physical dimension of solar cell is different from its standard cell structure. Using the result, we ob‐ tain an optimized co-firing process.

Fig 1 shows important components of screen printing. The screen is made up of an interwo‐ ven mesh kept at a high tension, with an organic emulsion layer defining the printing pat‐ tern. Fig. 1(a) shows a microscopic image of the screen. Printing pattern of the front metal contact with optimized dimensions (finger width, finger spacing, busbar width, maximum defined finger length) was developed in the form of a computer- aided – design (CAD) as shown in Fig. 1(b). The screen printer is equipped with optical vision system for proper alignment. The co-firing was carried out in a conveyor belt furnace (Sierratherm).

**Figure 1.** a) Microscopic image of the screen used in SP. (b) Design of the front metal printing pattern for the single c-Si wafer of size 125mm × 125mm (pseudo square).

#### *2.6.1. Back Metallization by Screen printing*

Rear surface of solar cells were screen printed with Aluminum paste (Ferro- 53-102). The thickness of the printed metal was maintained 20μm, with a variation of ±2μm. The average gain in mass of the wafer after back printing and drying was ~ 6 mg /cm2 .

#### *2.6.2. Co-firing of Screen Printed Pastes*

perature and ramp-up rate during the co-firing process are crucial along with the belt speed that determines residual time of the wafers to various temperature zones. A cylindrical proc‐ ess zone has different local temperature setting and the belt carries the Si wafers at a cer‐ tain speed. The grid pattern of the front electrode has a significant influence on Rs and FF, that demands optimization of co-firing process. With an increase in the sheet resistance (Rsheet) of the emitters, Voc decreases, however Jsc increases, which may be because of the improve‐ ment of blue-response, more light entering the solar cell active region and the reduction of recombination in the front surface. At a faster co-firing condition BSF layers and Ohmic front contacts can preferably be established, because the Rsheet of emitters may remain nearly un‐ changed. We observed a Voc of around 622mV and FF of 80.6% by Suns-Voc measurement. Suns-Voc measurement is a method of estimating open circuit voltage from decay character‐ istics of photo generated charge carriers. This method is generally adopted when physical dimension of solar cell is different from its standard cell structure. Using the result, we ob‐

Fig 1 shows important components of screen printing. The screen is made up of an interwo‐ ven mesh kept at a high tension, with an organic emulsion layer defining the printing pat‐ tern. Fig. 1(a) shows a microscopic image of the screen. Printing pattern of the front metal contact with optimized dimensions (finger width, finger spacing, busbar width, maximum defined finger length) was developed in the form of a computer- aided – design (CAD) as shown in Fig. 1(b). The screen printer is equipped with optical vision system for proper

**Figure 1.** a) Microscopic image of the screen used in SP. (b) Design of the front metal printing pattern for the single c-

Rear surface of solar cells were screen printed with Aluminum paste (Ferro- 53-102). The thickness of the printed metal was maintained 20μm, with a variation of ±2μm. The average

.

gain in mass of the wafer after back printing and drying was ~ 6 mg /cm2

alignment. The co-firing was carried out in a conveyor belt furnace (Sierratherm).

tain an optimized co-firing process.

112 Photodiodes - From Fundamentals to Applications

Si wafer of size 125mm × 125mm (pseudo square).

*2.6.1. Back Metallization by Screen printing*

Co-firing of printed metal paste was followed in three major steps, baking, burn- out, and sintering. Baking refers to the process of evaporating solvents of the pastes to avoid the gas bubbling and cracks formation during the high temperature treatment. The baking is carried out immediately after each metal printing step in a separate conveyor belt furnace at 150o C. Burn- out process removes the organic binders from the paste and it was carried out at 350-510o C.

The temperature profile for the co-firing cycle can be decided on the basis of the studies of Kim et. al [24]. With improper temperature and the belt speed settings of the co-firing, the metal electrodes can penetrate across the p-n junction, as schematically shown in Fig. 2, thus making the cell unusable.

The belt furnace used in this system was equipped with the facility to observe and adjust the actual front and back surface temperatures of the wafer by real time measurement, with two different thermocouples. As suggested in ref [24], we tested the co-firing with different tem‐ peratures of front and back surface. However, such a temperature difference may lead to bending of the wafer. So we prefer keeping the temperature of both the surfaces as equal. Proper Ohmic contact formation on the front and Al-Si alloying at back surface for proper BSF generation are the two significant accomplishments of this single shot method.

**Figure 2.** P-N junction of a typical solar cell with Ag metallization on front surface showing the possible cases of shunting through the p-n junction during co-firing as well as good sintering.

The co-firing was carried out in the condition of sufficient dry and filtered air flow into the furnace. It is one of the most sensitive steps of the solar cell fabrication. Any non-uniformity in surface cleaning, texturing, doping, or even ARC can have detrimental effect on the per‐ formance of the fabricated cells as well, especially in industrial process. If co-firing is done at a temperature below optimum temperature profile, it results in high series resistance and hence low FF due to poor Ohmic front contact and poor BSF, whereas over – co-firing at a higher temperature profile may result in junction shunting and degradation in surface and bulk passivation. Thus, finding an optimum co-firing temperature profile should be always the first priority in the industrial process.

of SiNx layer having variation of refractive index may demonstrate a part of improvement with Si-rich SiNx thin film. This may be because of field created by positive charges fixed at its surface. It is clear that a positive fixed charge is suitable for the n-type substrate, while a

Fabrication of Crystalline Silicon Solar Cell with Emitter Diffusion, SiNx Surface Passivation and Screen Printing of

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In this respect formation of local back contact is a promising technique, where a highly dop‐ ed p-type local back contact can reduce the potential barrier that charge carriers may face

Protection of the back surface of the Si-wafer may be achieved in two possible different ways, one is a complete coverage with Al back contact, and the other is with SiNx anti reflec‐ tion coating. The problem with full metal coverage with thinner Si wafers is the cracks and lattice defects formed during high temperature co-firing when there is high possibility of wafer bending. Thus partial coverage of the back surface with metal electrode and the rest

**Figure 3.** Comparison of SEM micrograph of the (a) saw damaged wafer surface, unclean and (b) saw damage re‐

The scanning electron microscopic (SEM) surface image of one of the cleaned and surface damage removed wafers is shown in Fig. 3. It shows image of untreated as well as wet

Since the concentration limit for anisotropic etching of surface texturing is 1.6 to 4 wt.%, the concentration of NaOH (wt. %) in the etchant solution was chosen as 2 wt.%. At a different etching time the resulting surface texture and specular reflection were different. For an etch‐

chemical etched wafer surface where saw damages have been removed.

negative fixed charge is suitable for the p-type c-Si wafer substrate.

covered by SiNx ARC surface passivator is a better alternative.

**3. Measurement Results for c-Si Solar Cells**

**3.1. Wafer Cleaning and Saw Damage Removal**

before reaching the metal electrode.

moved clean surface of Cz-Si wafer.

**3.2. Surface Texturing**

An advantage of an LBSF compared to the standard full Al-BSF is the lower consumption of expensive printing pastes. In order to accomplish the local back contact in solar cells, many techniques have already been employed. It has been shown that the hybrid buried contact solar cell with photo lithographically defined rear contacts achieves an increase in Voc by 30mV [25] as compared with a standard buried contact cell with conventional aluminum al‐ loyed BSF, which may result in a high rear surface recombination velocity. Koschier et al. [26] also demonstrated a 30 to 40mV increase in open circuit voltage relative to conventional buried contact solar cells using the thyristor structure device on the rear which incorporates a grown p+ layer in localized regions of the passivating oxide. However, both these rear con‐ tact schemes require the use of photolithography to remove regions of the oxide to expose the underlying surface for contact, which may not be suitable for large-scale commercial so‐ lar cell fabrication processes. Other techniques of creating small area contacts such as laser firing have been demonstrated to be feasible [27].

#### *2.6.3. Study of rear surface passivation with SiNx film*

Recombination of charge carriers at the rear surface in a solar cell can be suppressed by dep‐ osition of a silicon dioxide (SiO2) layer at the back surface, grown in a high-temperature (≥900°C) oxidation process [28-29]. Additionally, the SiO2/Al stack at the rear should act as a reflector for the near band gap photons, that leads to improved light trapping properties and hence the Jsc of the solar cell may improve as well. Thermally grown SiO2 layers are manufactured using a time and energy intensive high temperature process, they may not be a good choice for mass production, although they possibly provide a good thermally stable passivation [30]. Hence, an alternative low temperature surface passivation became necessa‐ ry for future industrial production of high efficiency Si solar cells, which should have prop‐ erties comparable to the SiO2 passivated solar cells.

One way of achieving this is deposition of SiNx layer by PECVD technique. It has been ob‐ served that this gives comparably low surface recombination velocity (SRVs) as compared to that with a thermal SiO2 on low resistivity p-type silicon [31-32]. However, conventional studies have mentioned certain limitations of a SiNx layer on p-type substrates [33]. When it was applied to the rear of a PERC (Passivated Emitter and Rear Cell) solar cell, the short cir‐ cuit current density (Jsc) reduced as compared to a SiO2 passivated cell [34]. This effect has been attributed to the large density of the fixed positive charges in the SiNx layer, inducing an inversion layer in the c-Si near the SiNx layer. A capacitance-voltage (C-V) measurement of SiNx layer having variation of refractive index may demonstrate a part of improvement with Si-rich SiNx thin film. This may be because of field created by positive charges fixed at its surface. It is clear that a positive fixed charge is suitable for the n-type substrate, while a negative fixed charge is suitable for the p-type c-Si wafer substrate.

In this respect formation of local back contact is a promising technique, where a highly dop‐ ed p-type local back contact can reduce the potential barrier that charge carriers may face before reaching the metal electrode.

Protection of the back surface of the Si-wafer may be achieved in two possible different ways, one is a complete coverage with Al back contact, and the other is with SiNx anti reflec‐ tion coating. The problem with full metal coverage with thinner Si wafers is the cracks and lattice defects formed during high temperature co-firing when there is high possibility of wafer bending. Thus partial coverage of the back surface with metal electrode and the rest covered by SiNx ARC surface passivator is a better alternative.

**Figure 3.** Comparison of SEM micrograph of the (a) saw damaged wafer surface, unclean and (b) saw damage re‐ moved clean surface of Cz-Si wafer.
