**2. Optical Receivers Basics**

potentially higher gain and lower noise performances which in turn, as we will show here, can increase the IC-sensitivity and alleviate this requirement on the photodetector itself. Fur‐ thermore only SOI photodiodes have so far achieved bandwidth compatible with the 10Gb/ s specification and even higher data rate among the "easy to integrate" Si photodetectors [1],

In the blue and UV wavelengths, these diodes achieve a high responsivity [17] and then com‐ bine all the advantages of high speed, low dark current and finally high sensitivity [1]. This makes SOI receivers the best candidate for blue DVD applications and future optical storage generation. This also suggests that blue wavelength for multi Gb/s short reach optical commu‐ nication could be used in a near future under the condition that the recent progresses in blue

We present here a top-down design methodology, fully validated by Eldo circuit simulations [20] and experimental measurements, which allows to predict and optimize, starting from the speed requirements and the technological parameters, the architecture and performances of the receiver. Our approach generalizes the one proposed in [21] to all inversion regimes. In ad‐

diode and the transimpedance in a simultaneous way. Thanks to this modeling and the low ca‐ pacitance of thin-film integrated SOI photodiodes, we have optimized various monolithic op‐ tical front-end suitable for 1 to 10 Gb/s short distance communication or Blue DVD applications that show the potentials of 0.13*μm* Partially-Depleted (PD) SOI CMOS implemen‐

In section 2 (Optical Receivers Basics), the simple resistor system is first presented as well as its limitations. The transimpedance amplifier is then introduced and its basic theory and concepts such as transimpedance gain, bandwidth and stability are derived. Important parameters to compare transimpedance amplifiers are also discussed as well as architectures most often used in the high speed communication area. Then in section "Design of Multistage Transimpedance Amplifiers", we present our top-down methodology to design transimpedance amplifiers in the case where the voltage gain of the voltage amplifier used in the TIA is independent of the

sign procedure is then applied to the design of a 3 stages 1GHz bandwidth transimpedance amplifier in a 0.13 *μm* PD-SOI CMOS technology. Finally, in section "Single stage Transimpe‐ dance Amplifier Modeling", we present a top-down methodology to design transimpedance

stage transimpedance amplifiers. Our design procedure is then applied to the design of a sin‐ gle stage 10GHz bandwidth transimpedance amplifier in a 0.13 *μm* PD-SOI CMOS technology and to the design of a 1GHz bandwidth single stage TIA in a 0.5 *μm* FD-SOI CMOS technology.

. This is usually the case when the TIA bandwidth is not too close to the

of a given technology and leads to a multi-stage approach. Our de‐

. This is the case for very high-speed single-

tation in terms of gain, sensitivity, power consumption, area and noise.

*id* methodology [22] and allows one to optimize the

[15], [16] and [18].

332 Photodiodes - From Fundamentals to Applications

feedback resistor *Rf*

transistors frequency limit *ft*

amplifiers when the voltage gain depends on *Rf*

emitting sources make them available [17, 19].

dition our design strategy is based on the *gm*

#### **2.1 The simple Resistor Optical Receiver**

The optical receiver is a key element in the optical link. It performs the optical to elec‐ trical conversion. The receiver consists of a photodetector followed by a preamplifier and eventually one or more post-amplifiers. The performance of an optical receiver is mainly determined by the preamplifier - photodiode combination. In high-speed commu‐ nication links, the two most important specifications are speed and sensitivity. In many cases, the speed is fixed by the application, while the sensitivity has to be maxi‐ mized. The ultimate limitation is noise. The main noise sources are the photodiode and the preamplifier. In a good design, the latter contribution is minimal. Little noise is add‐ ed when no active components are used in the preamplifier. This is the case for the sim‐ plest preamplifier possible presented in fig. 1a: a simple resistor *RL* that performs both the current - voltage conversion and the preamplification. In this figure, the simple re‐ ceiver is followed by a buffering amplifier with gain A. Its major drawback is the lim‐ ited maximal achievable bandwidth when low noise is important. For an input current *iph*, the output voltage of the simple optical receiver of fig. 1 a) is given by:

**Figure 1.** a) Simple photodiode-resistor receiver, followed by a voltage amplifier. b) Transimpedance Amplifier.

$$\left(\left.w\_{out}\right|\_{\rm{}}=R\_L\right.,\left.i\_{ph}\left(\frac{1}{1+s.R\_L\cdot\left(\mathbb{C}\_{ph}+\mathbb{C}\_{inA}\right)}\right)A\tag{1}$$

in which *Cph* is the total photodiode capacitance and *CinA* is the input capacitance of the volt‐ age amplifier. The bandwidth of this simple receiver is thus given by:

$$BW\_{Rdiode} = \frac{1}{R\_L \cdot \left(\mathbf{C}\_{ph} + \mathbf{C}\_{inA}\right)}\tag{2}$$

The bandwidth is limited by *Cph* which is often much bigger than *CinA* and the transimpe‐ dance-gain *RL* of the very first stage. As a result, the required bandwidth constrains the max‐ imal transimpedance-gain *RL* and accordingly the achievable sensitivity of this receiver. Indeed, the equivalent input noise current spectral density of this front-end is given by [21]:

*dieq*,*<sup>R</sup>* ¯ <sup>2</sup> (*w*)= 4.*kT RL* + |1 + *<sup>s</sup>*.*RL* .(*Cph* <sup>+</sup> *CinA*)|<sup>2</sup> *RL* <sup>2</sup> .*SvgAmp* <sup>2</sup> (3)

and the input capacitance of the subsequent stage, *Cnext*. The closed-loop transimpedance-

Design of Multi Gb/s Monolithically Integrated Photodiodes and Multi-Stage Transimpedance Amplifiers in Thin-Film

*RoutA*.*CoutT*

For a well designed voltage amplifier with sufficiently large gain A and small output impe‐

*<sup>A</sup>* ) <sup>+</sup> *<sup>s</sup>* <sup>2</sup>

This compares well with the simplified transfer function of a system with two well separat‐

The TIA dominant pole *p1* can theoretically be situated either at the input or at the output node. In between those two extreme cases, both poles approach each other and give rise to a complex conjugated pole pair. This intermediate poles placement is best avoided as it results in a bump in the frequency response with overshoot and long settling times of the transients

In the case of high speed circuits where the diode capacitance *Cph* usually dominates the oth‐

crease the transimpedance-gain, the dominant pole is usually located at the input node and

*Rf* .*CinT*

Comparing this bandwidth with that given by the simple resistor amplifier one (eq. 2), we see an improvement by a factor A of the transimpedance-gain-bandwidth product of the transimpedance amplifier. This means that for a given bandwidth, a TIA will have a transi‐ mpedance gain increased by A compared to the simple resistor amplifier. To be stable the

*BWtrans* <sup>≃</sup> *<sup>A</sup>*

*RoutA A* + 1

*<sup>A</sup>* + 1 ) <sup>+</sup> *<sup>s</sup>* <sup>2</sup>

.

.

*Rf* .*CinT* .*RoutA*.*CoutA A*

*Rf* .*CinT* .*RoutA*.*CoutA A* + 1

(4)

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(5)

(6)

(7)

value as high as possible to in‐

*A <sup>A</sup>* + 1 .*Rf* <sup>−</sup>

*RoutA*.*CoutA*

*<sup>T</sup>*2<sup>≃</sup> *To* 1 + *s p*1 + *s* 2 *p*1.*p*<sup>2</sup>

1 + *<sup>s</sup>*.( (*Rf* <sup>+</sup> *RoutA*).*CinT*

*Zcl* <sup>≃</sup> *Rf*

er capacitances and where we try to have the resistance *Rf*

gain A has however to be constrained, as we will see below.

the transimpedance bandwidth is then given by:

*<sup>A</sup>* <sup>+</sup>

1 + *<sup>s</sup>*.( *Rf* .*CinT*

ed real poles *p1* and *p2*, which is given by [24]:

*<sup>A</sup>* + 1 <sup>+</sup>

gain is given by:

*Zcl vout iph* =

[24] (see also fig. 2a).

dance *R* out this can be simplified to:

in which the first term is due to the resistor and the second term to the voltage amplifier. The noise of the latter is concentrated in the equivalent spectral density voltage source at the gate of the input transistor, *SvgAmp*. As the noise is inversely proportional to *RL*, low-noise operation implies that the pole is located at a relatively low frequency. This receiver is there‐ fore not suitable for high speed communication applications. To achieve high speed in com‐ bination with a large resistor, the latter is used as a feedback resistor with an inverting voltage amplifier. The resulting structure is a transimpedance amplifier.

#### **2.2 The Transimpedance Amplifier**

The transimpedance amplifier (TIA) (fig. 1b) is the most widely used preamplifier for highspeed optical receivers. It is based on an inverting voltage amplifier with open-loop gain A and a feedback resistor *Rf* to convert and amplify the input current *iph* from a photodiode to an output voltage *vout*. The transimpedance amplifier is a circuit with shunt-shunt feedback. As a general rule, this reduces both the amplifier input and output impedances by the loopgain of the amplifier [23]. In turn, this reduction of input impedance allows one for improv‐ ing the sensitivity and speed trade-off, we faced in the simple resistor amplifier. In this section, various important aspects of transimpedance amplifiers are analyzed.

**Figure 2.** a) Frequency response shape for 2 distant (�), close (peaking) (-�), and complex conjugate(- -) poles and b) Transimpedance Amplifier divided in direct and feedback paths.

#### *2.2.1 Bandwidth of the Transimpedance Amplifier*

To analyze the TIA frequency behavior, the most important capacitors have been included in fig. 1b. The total input capacitance of the circuit *CinT* consists of the photodiode capaci‐ tance *Cph*, eventually with its associated parasitics, and the voltage amplifier input capaci‐ tance *CinA*. The output capacitance *CoutT* is the sum of the amplifier output capacitance *CoutA* Design of Multi Gb/s Monolithically Integrated Photodiodes and Multi-Stage Transimpedance Amplifiers in Thin-Film SOI CMOS Technology http://dx.doi.org/ 10.5772/50531 335

and the input capacitance of the subsequent stage, *Cnext*. The closed-loop transimpedancegain is given by:

imal transimpedance-gain *RL* and accordingly the achievable sensitivity of this receiver. Indeed, the equivalent input noise current spectral density of this front-end is given by [21]:

> |1 + *<sup>s</sup>*.*RL* .(*Cph* <sup>+</sup> *CinA*)|<sup>2</sup> *RL*

in which the first term is due to the resistor and the second term to the voltage amplifier. The noise of the latter is concentrated in the equivalent spectral density voltage source at the gate of the input transistor, *SvgAmp*. As the noise is inversely proportional to *RL*, low-noise operation implies that the pole is located at a relatively low frequency. This receiver is there‐ fore not suitable for high speed communication applications. To achieve high speed in com‐ bination with a large resistor, the latter is used as a feedback resistor with an inverting

The transimpedance amplifier (TIA) (fig. 1b) is the most widely used preamplifier for highspeed optical receivers. It is based on an inverting voltage amplifier with open-loop gain A

an output voltage *vout*. The transimpedance amplifier is a circuit with shunt-shunt feedback. As a general rule, this reduces both the amplifier input and output impedances by the loopgain of the amplifier [23]. In turn, this reduction of input impedance allows one for improv‐ ing the sensitivity and speed trade-off, we faced in the simple resistor amplifier. In this

**Figure 2.** a) Frequency response shape for 2 distant (�), close (peaking) (-�), and complex conjugate(- -) poles and b)

To analyze the TIA frequency behavior, the most important capacitors have been included in fig. 1b. The total input capacitance of the circuit *CinT* consists of the photodiode capaci‐ tance *Cph*, eventually with its associated parasitics, and the voltage amplifier input capaci‐ tance *CinA*. The output capacitance *CoutT* is the sum of the amplifier output capacitance *CoutA*

<sup>2</sup> .*SvgAmp*

to convert and amplify the input current *iph* from a photodiode to

<sup>2</sup> (3)

*dieq*,*<sup>R</sup>* ¯

334 Photodiodes - From Fundamentals to Applications

**2.2 The Transimpedance Amplifier**

Transimpedance Amplifier divided in direct and feedback paths.

*2.2.1 Bandwidth of the Transimpedance Amplifier*

and a feedback resistor *Rf*

<sup>2</sup> (*w*)=

4.*kT RL* +

voltage amplifier. The resulting structure is a transimpedance amplifier.

section, various important aspects of transimpedance amplifiers are analyzed.

$$Z\_{cl}\frac{\upsilon\_{out}}{i\_{ph}} = \frac{\frac{A}{A+1}R\_f - \frac{R\_{outA}}{A+1}}{1+s.\left[\frac{(R\_f+R\_{outA})A\mathcal{L}\_{inT}}{A+1} + \frac{R\_{outA}\mathcal{L}\_{outT}}{A+1}\right] + s^2} \cdot \frac{R\_f\mathcal{L}\_{inT}\mathcal{R}\_{outA}\mathcal{L}\_{outA}}{A+1} \tag{4}$$

For a well designed voltage amplifier with sufficiently large gain A and small output impe‐ dance *R* out this can be simplified to:

$$Z\_{cl} \simeq \frac{R\_f}{1 + s.\left(\frac{R\_f \cdot \mathbb{C}\_{inT}}{A} + \frac{R\_{outA} \cdot \mathbb{C}\_{outA}}{A}\right) + s^2 \cdot \frac{R\_f \cdot \mathbb{C}\_{inT} \cdot R\_{outA} \cdot \mathbb{C}\_{outA}}{A}}\tag{5}$$

This compares well with the simplified transfer function of a system with two well separat‐ ed real poles *p1* and *p2*, which is given by [24]:

$$T\_2 \simeq \frac{T\_o}{1 + \frac{s}{p\_1} + \frac{s^2}{p\_1 \cdot p\_2}}\tag{6}$$

The TIA dominant pole *p1* can theoretically be situated either at the input or at the output node. In between those two extreme cases, both poles approach each other and give rise to a complex conjugated pole pair. This intermediate poles placement is best avoided as it results in a bump in the frequency response with overshoot and long settling times of the transients [24] (see also fig. 2a).

In the case of high speed circuits where the diode capacitance *Cph* usually dominates the oth‐ er capacitances and where we try to have the resistance *Rf* value as high as possible to in‐ crease the transimpedance-gain, the dominant pole is usually located at the input node and the transimpedance bandwidth is then given by:

$$BW\_{trans} \simeq \frac{A}{\mathcal{R}\_f \cdot \mathcal{C}\_{inT}} \tag{7}$$

Comparing this bandwidth with that given by the simple resistor amplifier one (eq. 2), we see an improvement by a factor A of the transimpedance-gain-bandwidth product of the transimpedance amplifier. This means that for a given bandwidth, a TIA will have a transi‐ mpedance gain increased by A compared to the simple resistor amplifier. To be stable the gain A has however to be constrained, as we will see below.

#### *2.2.2 Stability of the Transimpedance Amplifier*

As the transimpedance amplifier contains a feedback loop, its stability has to be assured. To analyze this problem, the shunt-shunt feedback amplifier is presented by its equivalent cir‐ cuit of fig. 2b [23]. From this figure, the open-loop gain and the feedback factor are easily derived:

$$T\_{openLoop} \simeq -A.R\_f \cdot \frac{1}{1 + s.R\_f \cdot C\_{inT}} \cdot \frac{1}{1 + s.R\_{outA} \cdot C\_{outT}} \beta = -\frac{1}{R\_f} \tag{8}$$

The loop gain, which is an important factor in the amplifier stability analysis is given by:

$$T\_{loop} = T\_{openLoop}, \beta \simeq A. \frac{1}{1 + \text{s.} \, R\_f. \, \text{C}\_{inT}}. \frac{1}{1 + \text{s.} \, R\_{outA}. \, \text{C}\_{outT}} \tag{9}$$

To obtain a stable system, the non-dominant pole of the amplifier loop gain has to be suffi‐ ciently higher than the 0 dB crossing frequency, which is given (the dominant pole is as‐ sumed at the input node) by:

$$\text{Cov}\_{T\_{\text{loop}}, \text{0dB}} \simeq \frac{A}{\mathcal{R}\_f \cdot \mathcal{C}\_{\text{int}T}} \tag{10}$$

**2.3 Comparison of Transimpedance Amplifiers**

**2.4 Architecture of Transimpedance Amplifiers**

**Figure 3.** Schematic view of a 3 stages a) SVTA and b) CMOS inverter TIA.

(*Rf*

time frequencies [1].

[27] and [7].

In analogy with the gain-bandwidth product used for an amplifier, the transimpedance-gain

Design of Multi Gb/s Monolithically Integrated Photodiodes and Multi-Stage Transimpedance Amplifiers in Thin-Film

In a given device, ZBW is a constant. This tells us that, to some extent, transimpedance gain can simply be traded for bandwidth and vice-versa by tuning the feedback resistor. This substitution is only limited by stability considerations. The maximal achievable bandwidth has to be a factor smaller than the first non-dominant pole of the receiver to maintain suffi‐ cient phase-margin. This factor of merit also emphasizes the need in critical high speed ap‐ plications for photodiodes integrated on chip along with the receivers which can reduce the photodiode capacitance drastically (by a factor up to ten times) by removing the bonding capacitor. SOI has here an advantage over other Si integrated technologies for high speed applications (e.g. 10 GBps) because both the photodiode and the amplifier will have smaller capacitances, and also because SOI photodiodes themselves can achieve such high transit

Transimpedance amplifier may differ by the kind of voltage amplifiers they use. In the highspeed communications field, two amplifier architectures are mostly used: the single transis‐ tor voltage amplifier (STVA) and the CMOS inverter used as an amplifier. A three stages TIA version of both cases is shown in fig. 3a and b. The inverter case has the advantage of auto biasing (the current depends on the gate voltage and the size of the P and NMOS tran‐ sistor) and then requires no additional bias circuit. The inverter based amplifier has, howev‐ er, less design flexibility as the gate voltages of the PMOS and NMOS transistors are equal, on the contrary to the case of the SVTA circuit. In very high speed applications, in order to improve crosstalk immunity, differential versions of the transimpedances are also employed and then differential pairs or two single inverters with a dummy branch can be used [26],

*ZBW* <sup>≃</sup>*Rf* .*BWtrans* <sup>≃</sup> *<sup>A</sup>*

) - bandwidth (*BWtrans*) product or ZBW has been proposed as the parameter that meas‐ ures both the speed and the sensitivity performance of the transimpedance amplifier [21]:

*CinT*

(12)

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The latter is equal to the TIA closed-loop bandwidth (Eq. 7). Actually, the equivalence of these two equations demonstrates that a TIA behaves as a voltage amplifier in unity-gain feedback configuration. The stability analysis of both structures is therefore identical [21]. To achieve a reasonable phase-margin, non-dominant poles have to be sufficiently higher than the receiver bandwidth. This implies for the second pole in this structure [24]:

$$\frac{1}{\mathcal{R}\_{outA} \cdot \mathcal{C}\_{outT}} \ge X\_{A^\*} \frac{A}{\mathcal{R}\_f \cdot \mathcal{C}\_{inT}} \tag{11}$$

where *XA* is a factor ranging from 2 to 3 depending on the required phase margin [25]. In general, some extra poles may be present on the internal nodes of the voltage amplifier. These must obviously also be considered during the design and be placed at sufficiently high frequencies to guarantee stability. These requirements ultimately limit the maximal achievable transimpedance-gain and bandwidth.

To summarize, the transimpedance amplifier allows one, owing to its feedback mechanism, to increase the frequency of the dominant pole to a value that is A times higher that the one we would have with a simple resistor. However, by increasing the gain A, the dominant pole approaches the second pole. In order to avoid stability problems, we have to limit the gain A such that the dominant pole stays around 3 times smaller that the second pole (the factor 3 corresponds to the classical 60° phase margin condition in open loop configuration).

#### **2.3 Comparison of Transimpedance Amplifiers**

*2.2.2 Stability of the Transimpedance Amplifier*

336 Photodiodes - From Fundamentals to Applications

sumed at the input node) by:

*TopenLoop* ≃ − *<sup>A</sup>*.*Rf* . <sup>1</sup>

*Tloop* <sup>=</sup>*TopenLoop*.*<sup>β</sup>* <sup>≃</sup> *<sup>A</sup>*. <sup>1</sup>

derived:

As the transimpedance amplifier contains a feedback loop, its stability has to be assured. To analyze this problem, the shunt-shunt feedback amplifier is presented by its equivalent cir‐ cuit of fig. 2b [23]. From this figure, the open-loop gain and the feedback factor are easily

> . <sup>1</sup> 1 + *s*.*RoutA*.*CoutT*

> > . <sup>1</sup> 1 + *s*.*RoutA*.*CoutT*

*<sup>β</sup>* <sup>=</sup> <sup>−</sup> <sup>1</sup> *Rf*

(8)

(9)

(10)

(11)

1 + *s*.*Rf* .*CinT*

The loop gain, which is an important factor in the amplifier stability analysis is given by:

1 + *s*.*Rf* .*CinT*

*wTloop*,0*dB* <sup>≃</sup> *<sup>A</sup>*

the receiver bandwidth. This implies for the second pole in this structure [24]:

1 *RoutA.CoutT*

achievable transimpedance-gain and bandwidth.

To obtain a stable system, the non-dominant pole of the amplifier loop gain has to be suffi‐ ciently higher than the 0 dB crossing frequency, which is given (the dominant pole is as‐

*Rf* .*CinT*

The latter is equal to the TIA closed-loop bandwidth (Eq. 7). Actually, the equivalence of these two equations demonstrates that a TIA behaves as a voltage amplifier in unity-gain feedback configuration. The stability analysis of both structures is therefore identical [21]. To achieve a reasonable phase-margin, non-dominant poles have to be sufficiently higher than

> <sup>≥</sup> *<sup>X</sup> A. <sup>A</sup> Rf .CinT*

where *XA* is a factor ranging from 2 to 3 depending on the required phase margin [25]. In general, some extra poles may be present on the internal nodes of the voltage amplifier. These must obviously also be considered during the design and be placed at sufficiently high frequencies to guarantee stability. These requirements ultimately limit the maximal

To summarize, the transimpedance amplifier allows one, owing to its feedback mechanism, to increase the frequency of the dominant pole to a value that is A times higher that the one we would have with a simple resistor. However, by increasing the gain A, the dominant pole approaches the second pole. In order to avoid stability problems, we have to limit the gain A such that the dominant pole stays around 3 times smaller that the second pole (the factor 3 corresponds to the classical 60° phase margin condition in open loop configuration).

In analogy with the gain-bandwidth product used for an amplifier, the transimpedance-gain (*Rf* ) - bandwidth (*BWtrans*) product or ZBW has been proposed as the parameter that meas‐ ures both the speed and the sensitivity performance of the transimpedance amplifier [21]:

$$
\mathbb{Z}\,\mathbb{Z}\mathbb{W} \simeq \mathbb{R}\mathbb{f}\,\,\mathbb{A}\mathbb{W}\_{\text{trans}} \simeq \frac{A}{\mathbb{C}\_{\text{in}\,T}}\tag{12}
$$

In a given device, ZBW is a constant. This tells us that, to some extent, transimpedance gain can simply be traded for bandwidth and vice-versa by tuning the feedback resistor. This substitution is only limited by stability considerations. The maximal achievable bandwidth has to be a factor smaller than the first non-dominant pole of the receiver to maintain suffi‐ cient phase-margin. This factor of merit also emphasizes the need in critical high speed ap‐ plications for photodiodes integrated on chip along with the receivers which can reduce the photodiode capacitance drastically (by a factor up to ten times) by removing the bonding capacitor. SOI has here an advantage over other Si integrated technologies for high speed applications (e.g. 10 GBps) because both the photodiode and the amplifier will have smaller capacitances, and also because SOI photodiodes themselves can achieve such high transit time frequencies [1].

#### **2.4 Architecture of Transimpedance Amplifiers**

Transimpedance amplifier may differ by the kind of voltage amplifiers they use. In the highspeed communications field, two amplifier architectures are mostly used: the single transis‐ tor voltage amplifier (STVA) and the CMOS inverter used as an amplifier. A three stages TIA version of both cases is shown in fig. 3a and b. The inverter case has the advantage of auto biasing (the current depends on the gate voltage and the size of the P and NMOS tran‐ sistor) and then requires no additional bias circuit. The inverter based amplifier has, howev‐ er, less design flexibility as the gate voltages of the PMOS and NMOS transistors are equal, on the contrary to the case of the SVTA circuit. In very high speed applications, in order to improve crosstalk immunity, differential versions of the transimpedances are also employed and then differential pairs or two single inverters with a dummy branch can be used [26], [27] and [7].

**Figure 3.** Schematic view of a 3 stages a) SVTA and b) CMOS inverter TIA.

One can distinguish different type of TIAs by their number of stages. Typical designs use either a single-stage or multi-stage approach. It can be shown [21] and will be further devel‐ oped that applications requesting a high bandwidth compared to the technology's *ft* are lim‐ ited to single-stage amplifiers as there is no room for placing the extra poles that are inevitably introduced by the multiple-stage designs. However, for frequencies at least 20 to 30 times lower than *ft* , a multi-stage design is the way to go.

#### **3. Design of Multistage Transimpedance Amplifiers**

#### **3.1 Optimizing the number of stages of STVA transimpedance amplifiers**

We will now describe our methodology to optimize the stages number N that maximizes the voltage gain in transimpedance amplifiers based on N identical STVA amplifiers. It is based on the *gm id* methodology and generalizes to all regimes of inversion the methodology of In‐ gels [21] that was developed for strong inversion (when we can assume that *Cgs* <sup>=</sup> <sup>2</sup> <sup>3</sup> <sup>⋅</sup>*Cox* ). Extension to the CMOS Inverter or the differential pair TIA is quite straightforward. The gain of a single SVTA stage is given by:

$$A\_{Nsi} = \frac{\mathcal{g}\,m\_1}{\mathcal{g}\,out} = \left(\frac{\mathcal{g}\,m}{Id}\right) \mathbf{1}.\\ V\_{ea}. L\_{eq} \tag{13}$$

As *XA* has to be larger than 2 to 3, *XN* is approximately equal to N while:

*gouti*

+ *Cgs*1,*i*+1

on the right side, we obtain that to be stable the gain of 1 stage has to be lower than:

.*BWN si*

*gm I d*<sup>1</sup> *i dn*1

2*πCgso*<sup>1</sup>

*ov* + *Cxjo*.*Xj* + *Cdgo*<sup>1</sup>

*Cgso*<sup>1</sup> *L* <sup>1</sup>

*GBWN Si*

*L* <sup>1</sup> 2 =

gm/Id, is a technological curve for a given length which tends towards a maximum in strong inversion. *XC* is also a technological curve which depends on the transistor inversion degree and is minimum in strong inversion. We can then rewrite *GBWNsi* and the stability condition on the maximum value of the gain as a function of a technological curve *vs*. the inversion

> <sup>=</sup> 2.*π*. *<sup>f</sup> <sup>t</sup>* 1 + *XC*

<sup>=</sup> *gm*1,*<sup>i</sup> Cd*1,*<sup>i</sup>*

+ *Cgs*1,*i*+1

*<sup>f</sup>* 1(( *gm Id* )1 )

> *L* <sup>1</sup> 2

<sup>=</sup> *<sup>f</sup>* <sup>2</sup>(( *gm Id* ) 1

in function of the normalized drain current, *idn*, or of the parameter

.*L* <sup>1</sup>

*GBWN Si XN* .*XA*.*BWtrans*

*Cd*1,*<sup>i</sup>*

By multiplying both sides of this equation by the gain of 1 stage, *ANsi*

*AN si* ≤

is the gain-bandwidth product of an individual stage i:

= *AN si*

=

*GBWN Si*

*ft* <sup>=</sup> *gm*<sup>1</sup> 2*πCgs*<sup>1</sup>

*XC* ≃

where the parameter *ft*

degree of the transistor:

*Cd*1 *Cgs*<sup>1</sup> = *Cox*.*l*

at least (the drain capacitance of transistor M2, *Cd2*

*BWN si* =

dressed latter):

*GBWNsi*

By introducing:

As a result, the i*th* stage bandwidth of the N-stages voltage amplifier used in a TIA has to be

Design of Multi Gb/s Monolithically Integrated Photodiodes and Multi-Stage Transimpedance Amplifiers in Thin-Film

tan(*x*)≃ *x x*≪1 (17)

has been neglected here. This will be ad‐

, and isolating the gain

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, *L* 1) (22)

(19)

(20)

(21)

(23)

≥ *XN* .*XA*.*BWtrans* (18)

where *Vea* is the Early voltage by *μm* of length and *Leq* is an equivalent length in *μm*. In the case of the amplifier of figure 3a, we have:

$$L\_{eq} = \frac{L \text{ 1.1 L 2}}{L \text{ 1} + L \text{ 2}} \tag{14}$$

The whole gain of the amplifier is then:

$$\mathbf{A}\_{\rm Ns} = \mathbf{A}\_{\rm N}^{\rm N}{}\_{s\_i} \tag{15}$$

For the single stage amplifier, with the dominant pole at the input and only one non-domi‐ nant pole at the output, the condition of stability was given by eq. 11. In the case of a multistages amplifier, we now have a multiple pole roll-off. To achieve same phase margin with a N pole roll-off than with a single pole, we must now place each of these N poles at a fre‐ quency *XN.XA* higher than the dominant pole frequency. *XN* is given by [21]:

$$\arctan\left(\frac{1}{X\_A}\right) = N \cdot \arctan\left(\frac{1}{X\_N \cdot X\_A}\right) \tag{16}$$

Design of Multi Gb/s Monolithically Integrated Photodiodes and Multi-Stage Transimpedance Amplifiers in Thin-Film SOI CMOS Technology http://dx.doi.org/ 10.5772/50531 339

As *XA* has to be larger than 2 to 3, *XN* is approximately equal to N while:

$$
\tan(\mathbf{x}) \simeq \mathbf{x} \quad \mathbf{x} \ll 1 \tag{17}
$$

As a result, the i*th* stage bandwidth of the N-stages voltage amplifier used in a TIA has to be at least (the drain capacitance of transistor M2, *Cd2* has been neglected here. This will be ad‐ dressed latter):

$$BW\_{Ns\_i} = \frac{\mathcal{S}\_{out\_i}}{\mathcal{C}\_{d\_{1,i}} + \mathcal{C}\_{\mathcal{S}^{s\_{1,i+1}}}} \ge X\_N.X\_A.BW\_{trans} \tag{18}$$

By multiplying both sides of this equation by the gain of 1 stage, *ANsi* , and isolating the gain on the right side, we obtain that to be stable the gain of 1 stage has to be lower than:

$$A\_{Ns\_i} \leq \frac{GBW\_{NS\_i}}{X\_N.X\_A.BW\_{trans}} \tag{19}$$

*GBWNsi* is the gain-bandwidth product of an individual stage i:

$$\text{GBVW}\_{NS\_i} = A\_{Ns\_i} \cdot \text{BW}\_{Ns\_i} = \frac{\text{g } m\_{1,i}}{\text{C}\_{d\_{1,i}} + \text{C}\_{\text{g } s\_{1,i+1}}} \tag{20}$$

By introducing:

One can distinguish different type of TIAs by their number of stages. Typical designs use either a single-stage or multi-stage approach. It can be shown [21] and will be further devel‐

ited to single-stage amplifiers as there is no room for placing the extra poles that are inevitably introduced by the multiple-stage designs. However, for frequencies at least 20 to

We will now describe our methodology to optimize the stages number N that maximizes the voltage gain in transimpedance amplifiers based on N identical STVA amplifiers. It is based

Extension to the CMOS Inverter or the differential pair TIA is quite straightforward. The

where *Vea* is the Early voltage by *μm* of length and *Leq* is an equivalent length in *μm*. In the

gels [21] that was developed for strong inversion (when we can assume that *Cgs* <sup>=</sup> <sup>2</sup>

*gout* =( *gm*

*<sup>L</sup> eq* <sup>=</sup> *<sup>L</sup>* 1.*<sup>L</sup>* <sup>2</sup>

*ANs* = *AN si*

quency *XN.XA* higher than the dominant pole frequency. *XN* is given by [21]:

*XA*

arctan ( <sup>1</sup>

For the single stage amplifier, with the dominant pole at the input and only one non-domi‐ nant pole at the output, the condition of stability was given by eq. 11. In the case of a multistages amplifier, we now have a multiple pole roll-off. To achieve same phase margin with a N pole roll-off than with a single pole, we must now place each of these N poles at a fre‐

) <sup>=</sup> *<sup>N</sup>* .arctan ( <sup>1</sup>

*XN* .*XA*

*id* methodology and generalizes to all regimes of inversion the methodology of In‐

*Id* )1.*Vea*.*<sup>L</sup> eq* (13)

*<sup>L</sup>* 1 + *<sup>L</sup>* <sup>2</sup> (14)

*<sup>N</sup>* (15)

) (16)

are lim‐

<sup>3</sup> <sup>⋅</sup>*Cox* ).

oped that applications requesting a high bandwidth compared to the technology's *ft*

, a multi-stage design is the way to go.

**3. Design of Multistage Transimpedance Amplifiers**

*ANsi* <sup>=</sup> *gm*<sup>1</sup>

**3.1 Optimizing the number of stages of STVA transimpedance amplifiers**

30 times lower than *ft*

338 Photodiodes - From Fundamentals to Applications

on the *gm*

gain of a single SVTA stage is given by:

case of the amplifier of figure 3a, we have:

The whole gain of the amplifier is then:

$$f = \frac{g \, m\_1}{2 \pi \, \text{C}\_{\text{g} \text{s}\_1}} = \frac{\frac{\text{g} m}{\text{Id}\_1} \mathbf{i}\_{dn1}}{2 \pi \, \text{C}\_{\text{g} \text{s}\_1} \, \text{L}\_1} = \frac{f\_1 \left( \left( \frac{\text{g} m}{\text{Id}} \right)\_1 \right)}{\text{L}\_1 \text{s}\_1^2} \tag{21}$$

$$X\_{\mathcal{C}} \simeq \frac{\mathbb{C}\_{d\_1}}{\mathbb{C}\_{\mathcal{S}^{s\_1}}} = \frac{\mathbb{C}\_{\alpha \alpha} L\_{\alpha \upsilon} + \mathbb{C}\_{\text{x} \circ \upsilon} X\_{\mathcal{j}} + \mathbb{C}\_{\text{d} \circ \alpha\_1} L\_{\text{-} 1}}{\mathbb{C}\_{\mathcal{S}^{s\_0}} L\_{\text{-} 1}} = f\_2(\left(\frac{\mathbb{S}^{\mathfrak{M}}}{Id}\right)\_{\mathbf{1}'} L\_{\text{-} 1}) \tag{22}$$

where the parameter *ft* in function of the normalized drain current, *idn*, or of the parameter gm/Id, is a technological curve for a given length which tends towards a maximum in strong inversion. *XC* is also a technological curve which depends on the transistor inversion degree and is minimum in strong inversion. We can then rewrite *GBWNsi* and the stability condition on the maximum value of the gain as a function of a technological curve *vs*. the inversion degree of the transistor:

$$
GBW\_{NS\_i} = \frac{2.\pi.f\_t}{1 + X\_{\odot}} \tag{23}
$$

$$A\_{N \cdot s\_i} \le \frac{2.\pi.f\_t}{\{1 + X\_C\}.X\_N.X\_A.BW\_{trms}}\tag{24}$$

**Figure 4** {a) *fNstab* vs.( *gm*

**Figure 5.** a) Evolution of ( *gm*

0.13μm PD-SOI technology.

*Cd2*

*Id* )1

curve is below the *fNstab* curve, the system is stable. The optimal ( *gm*

any more and only a single stage transimpedance with low ( *gm*

*Id* )1max

M1 and M2 are the same, we can relate W2 to W1 by:

**3.2 Current mirror impact on optimal stages number and gain**

We have neglected so far the current mirror drain capacitance, *Cd2*

*W* 2= *i dn*1 *i dn*2 . *L* 2

and then introduce a factor *XC2* independent of W1 and W2 to add to Xc:

(eq. 25) for *BWtrans*=2.π.1GHz, *XA*=3 and ST 0.13μm PD-SOI technology. While the ( *gm*

*Id* )1

the intersection of these two curves. As the *fNstab* curves are shifted down by increasing N, the optimal value of ( *gm*

decreases with the number of stages. b) same but for *BWtrans*=2.π.10GHz. As the *fNstab* curves have been shifted down by a factor of 10 due to the 10 times higher transimpedance bandwidth compared to a), increasing N is not possible

Design of Multi Gb/s Monolithically Integrated Photodiodes and Multi-Stage Transimpedance Amplifiers in Thin-Film

output pole as it gave us useful indications on the maximal gain vs. the number of stages for a given transimpedance bandwidth without having to choose neither W1 nor W2. However,

can lead to significant and unacceptable loss in phase margin. As the drain currents of

*Id* )1

*Id* )1

SOI CMOS Technology

341

http://dx.doi.org/ 10.5772/50531

*Id* )1

that is related to the maximum voltage gain is at

, in the calculation of the

can fulfill the stability requirements.

and b) total amplifier voltage gain *ANs* (b) vs. N for *BWtrans*=2.π.1GHz, *XA*=3 and ST

*<sup>L</sup>* <sup>1</sup> .*<sup>W</sup>* <sup>1</sup> (26)

This last equation combined with the equation of the gain *ANsi* (eq. 13) allows us to write the following condition on ( *gm Id* )1 for a given *BWtrans*, a given N, and a given *XA*:

$$f\left(\frac{\mathcal{g}m}{Id}\right)\_1 \le \frac{2.\pi.f\_t}{\{1+X\_C\}.X\_N.X\_A.B\mathcal{W}\_{\text{trans}}.V\_{eu}.L\_{\text{eq}}} = f\_{\text{Nstab}}\left(\left(\frac{\mathcal{g}m}{\dot{\mathcal{u}}}\right)\_1\right) \tag{25}$$

This implicit equation of ( *gm Id* )1 can be solved recursively. We start with a minimum value of ( *gm Id* )1 , imposed when the gate to source voltage is at is maximum value, i.e. Vdd, com‐ pute *fNstab* for this ( *gm Id* )1 and then compare the two values. If ( *gm Id* )1 is lower than *fNstab*, we then increase ( *gm Id* )1 , compute a new *fNstab* and compare and iterate while ( *gm Id* )1 stays lower than *fNstab* or while ( *gm Id* )1 is lower than the maximum ( *gm Id* )1 available in the technology. In this last case the gain will not be limited by the stability but by the feasibility.

The method is illustrated graphically in fig. 4. As the *fNstab* vs. ( *gm Id* )1 curves are shifted down by increasing N, the optimal value of ( *gm Id* )1 , i.e. ( *gm Id* )1max , related to the maximum voltage gain decreases with the number of stages. The gain of each single stage is then decreased (eq. 13), while the overall gain can still increase as we add more stages (eq. 15). We see that in term of voltage gain, an optimal value of stages *Nopt* exists. In fig. 4a, we can see that for a bandwidth of 1GHz in a typical 0.13*μm* PD-SOI technology, eq. 25 features a solution in terms of ( *gm Id* )1max for N greater than 1 owing to the sufficient value of the ratio *ft* over *fttrans* (This ratio is not constant over the ( *gm Id* )1 range but is around 130 for its maximum value (*ftmax*/*fttrans*)). Therefore, the curve of ( *gm Id* )1max vs. N can be calculated (fig. 5 (a)). The total volt‐ age gain, *ANs*, vs. N and the optimal number of stages, *Nopt*, can be deduced from there (fig. 5 (b)). In the case of fig. 5 (b), *Nopt* is equal to 9. In the case of fig. 4b, if we increase the transi‐ mpedance bandwidth specification to 10 GHz and then work at *ftmax*/*fttrans* ratio of about 10, eq. 25 has no solution for N greater than 1 and *Nopt* is then equal to 1 (To have stable solutions for N greater than 1 would require in fact to have ( *gm Id* )1 lower than its minimum value).

Design of Multi Gb/s Monolithically Integrated Photodiodes and Multi-Stage Transimpedance Amplifiers in Thin-Film SOI CMOS Technology http://dx.doi.org/ 10.5772/50531 341

*AN si* ≤

*Id* )1

*Id* )1

following condition on ( *gm*

( *gm Id* )1 ≤

340 Photodiodes - From Fundamentals to Applications

This implicit equation of ( *gm*

*Id* )1

*Id* )1

by increasing N, the optimal value of ( *gm*

(This ratio is not constant over the ( *gm*

for N greater than 1 would require in fact to have ( *gm*

(*ftmax*/*fttrans*)). Therefore, the curve of ( *gm*

*Id* )1

pute *fNstab* for this ( *gm*

than *fNstab* or while ( *gm*

then increase ( *gm*

terms of ( *gm*

*Id* )1max

of ( *gm Id* )1

2.*π*. *f <sup>t</sup>* (1 + *XC*).*XN* .*XA*.*BWtrans*

This last equation combined with the equation of the gain *ANsi* (eq. 13) allows us to write the

2.*π*. *f <sup>t</sup>* (1 + *XC*).*XN* .*XA*.*BWtrans*.*Vea*.*L eqi*

for a given *BWtrans*, a given N, and a given *XA*:

, imposed when the gate to source voltage is at is maximum value, i.e. Vdd, com‐

, compute a new *fNstab* and compare and iterate while ( *gm*

and then compare the two values. If ( *gm*

*Id* )1 , i.e. ( *gm*

gain decreases with the number of stages. The gain of each single stage is then decreased (eq. 13), while the overall gain can still increase as we add more stages (eq. 15). We see that in term of voltage gain, an optimal value of stages *Nopt* exists. In fig. 4a, we can see that for a bandwidth of 1GHz in a typical 0.13*μm* PD-SOI technology, eq. 25 features a solution in

age gain, *ANs*, vs. N and the optimal number of stages, *Nopt*, can be deduced from there (fig. 5 (b)). In the case of fig. 5 (b), *Nopt* is equal to 9. In the case of fig. 4b, if we increase the transi‐ mpedance bandwidth specification to 10 GHz and then work at *ftmax*/*fttrans* ratio of about 10, eq. 25 has no solution for N greater than 1 and *Nopt* is then equal to 1 (To have stable solutions

is lower than the maximum ( *gm*

this last case the gain will not be limited by the stability but by the feasibility.

*Id* )1

*Id* )1max

The method is illustrated graphically in fig. 4. As the *fNstab* vs. ( *gm*

<sup>=</sup> *<sup>f</sup> Nstab*(( *gm*

can be solved recursively. We start with a minimum value

*Id* )1

*Id* )1max

for N greater than 1 owing to the sufficient value of the ratio *ft*

*Id* )1

*id* )1

*Id* )1

*Id* )1

range but is around 130 for its maximum value

vs. N can be calculated (fig. 5 (a)). The total volt‐

lower than its minimum value).

) (25)

is lower than *fNstab*, we

curves are shifted down

stays lower

over *fttrans*

*Id* )1

available in the technology. In

, related to the maximum voltage

(24)

**Figure 4** {a) *fNstab* vs.( *gm Id* )1 (eq. 25) for *BWtrans*=2.π.1GHz, *XA*=3 and ST 0.13μm PD-SOI technology. While the ( *gm Id* )1 curve is below the *fNstab* curve, the system is stable. The optimal ( *gm Id* )1 that is related to the maximum voltage gain is at the intersection of these two curves. As the *fNstab* curves are shifted down by increasing N, the optimal value of ( *gm Id* )1 decreases with the number of stages. b) same but for *BWtrans*=2.π.10GHz. As the *fNstab* curves have been shifted down by a factor of 10 due to the 10 times higher transimpedance bandwidth compared to a), increasing N is not possible any more and only a single stage transimpedance with low ( *gm Id* )1 can fulfill the stability requirements.

**Figure 5.** a) Evolution of ( *gm Id* )1max and b) total amplifier voltage gain *ANs* (b) vs. N for *BWtrans*=2.π.1GHz, *XA*=3 and ST 0.13μm PD-SOI technology.

#### **3.2 Current mirror impact on optimal stages number and gain**

We have neglected so far the current mirror drain capacitance, *Cd2* , in the calculation of the output pole as it gave us useful indications on the maximal gain vs. the number of stages for a given transimpedance bandwidth without having to choose neither W1 nor W2. However, *Cd2* can lead to significant and unacceptable loss in phase margin. As the drain currents of M1 and M2 are the same, we can relate W2 to W1 by:

$$\mathcal{W}\mathcal{Z} = \frac{\dot{l}\_{dn1}}{\dot{l}\_{dn2}} \cdot \frac{L}{L-1} \mathcal{W}\mathbf{1} \tag{26}$$

and then introduce a factor *XC2* independent of W1 and W2 to add to Xc:

$$\begin{aligned} X\_{C2} &= \frac{\mathsf{C}\_{d\_2}}{\mathsf{C}\_{gs\_1}} \cdot \frac{\mathsf{C}\_{gds\_2} \mathsf{L}\_{\bot} + \mathsf{C}\_{ox} \mathsf{L}\_{ov} + \mathsf{C}\_{xjo} \mathsf{X}\_j}{\mathsf{C}\_{gs\_1} \mathsf{L} \ \mathsf{L}} \cdot \frac{i\_{dm1}}{i\_{dm2}} \cdot \frac{\mathsf{L} \ \mathsf{L}}{\mathsf{L} \ \mathsf{L}} \\\ X\_{C2} &= f\left( \left| \frac{\mathcal{g}m}{Id} \right| \mathsf{1}, \left( \frac{\mathcal{g}m}{Id} \right) 2, \mathsf{L} \ \mathsf{1}, \mathsf{L} \ \mathsf{2} \right) \end{aligned} \tag{27}$$

performances. Once the number of stages has been chosen, we still have to choose W1. This can

Design of Multi Gb/s Monolithically Integrated Photodiodes and Multi-Stage Transimpedance Amplifiers in Thin-Film

*Id* )1max

, thermal noise, modeled by the voltage noise source, *SvRf*

<sup>2</sup> ( *<sup>f</sup>* )=4*kT* .*Rf* (30)

, and c) total amplifier voltage gain *ANs* vs. N.

2 and

2 . The power

SOI CMOS Technology

343

http://dx.doi.org/ 10.5772/50531

<sup>2</sup> (31)

2

and express:

be done by optimizing noise, area and power consumption.

1 (eq. 28), b) evolution of ( *gm*

= 2.5 *V-1*, and ST 0.13μm PD-SOI technology.

of the input transistor of the amplifier (gate of M1 of the first stage), *SvgAmp*

*SvRf*

2 is then given by:

<sup>2</sup> ( *<sup>f</sup>* )≃*Svg*<sup>1</sup>

comparison with the thermal noise, we can neglect the 1/f terms in *Svg*<sup>i</sup>

To analyze the TIA noise performance, we have to consider its major noise sources which

the voltage amplifier noise. The latter is concentrated in the voltage noise source at the gate

For the amplifier power spectral density referred to its input, in a first approximation, we can only take into account the noise of the first stage, as, from stage to stage, the relative im‐ portance of the noise of each subsequent stage is approximatively divided by the gain of

<sup>2</sup> + 2.( ( *gm*

ces at the gate of first stage transistors M1 and M2 respectively. A factor 2 was introduced

simpedance design where the TIA bandwidth is usually high compared to the corner fre‐ quency, i.e. the frequency at which the 1/f noise of the transistors becomes negligible in

<sup>2</sup> terms, as we assumed that M2 was biased by an identical mirror transistor. In tran‐

*Id* )2 ( *gm Id* )1 )

2

.*Svg*<sup>2</sup>

are the power spectral densities of the equivalent voltage noise sour‐

**Figure 6.** a) *f Nstab*

**3.3 Noise**

*BWtrans*=2.π.1GHz, *XA*=3, ( *gm*

are the feedback resistor, *Rf*

each preceding stage. *SvgAmp*

where *Svg*<sup>1</sup>

for *Svg*<sup>2</sup>

2

and *Svg*<sup>2</sup>

2

\* vs. ( *gm*

*Id* )i

*Id* )2

spectral density of the feedback noise source is given by:

*SvgAmp*

As L1 and L2 are usually kept to their minimum value in order to minimize capacitances and area and to maximize speed performances, the maximum value of ( *gm Id* )1 has now a de‐ pendency on ( *gm Id* )2 due to the term *XC2*:

$$f\left(\frac{\text{g}m}{\text{Id}}\right)1 \le \frac{2.\pi.f\_l}{\{1 + X\_{\text{C}} + X\_{\text{C2}}\}X\_N.X\_A.BW\_{\text{trans}}, V\_{\text{eu}}.L\_{\text{eq}\_i}} = f\_{\text{Nstab}}^\*\left(\left|\frac{\text{g}m}{\text{Id}}\right|1, \left|\frac{\text{g}m}{\text{Id}}\right|2\right) \tag{28}$$

The selection of ( *gm Id* )2 results in a trade-off between dynamic range and other performan‐ ces. To keep W2 small compared to W1, and then keep negligible the effect of the degrada‐ tion of *XC2* on ( *gm Id* )1max , and thus on the gain and on *Rf* , we see that we need *idn2* to be large compared to *idn1*. This implies to have ( *gm Id* )1 larger than ( *gm Id* )2 and bias the mirror in strong inversion. However, this reduces the dynamic range by increasing the saturation voltage of the mirror *Vdssat2* . In strong inversion, the latter can be approximated by:

$$Vds\_{sat\_2} = \frac{2}{\left(\frac{\mathcal{G}^m}{Id}\right)2} \tag{29}$$

Once ( *gm Id* )2 has been chosen, we can deduce ( *gm Id* )1max and the maximum number of stages from the maximum voltage gain as done earlier. As can be seen on fig. 6, the optimal number of stages for the gain is now reduced from 9 to 3 when taking into account the correction due to the capacitance of the mirror. Indeed, ( *gm Id* )1max now decreases more rapidly with N as, for a fixed ( *gm Id* )2 , *XC2* increases with N due to the decrease of the ratio *idn1*/*idn2* with ( *gm Id* )1 . This in‐ dicates that the mirror has a more detrimental effect when increasing the number of stages, which can be observed when comparing the values of ( *gm Id* )1max *vs*. N on fig. 6c) and fig. 5b). These values are nearly identical until N=3. This indicates that, as long as its size is kept small because of a good ( *gm Id* ) ratio, the mirror has a relatively small influence while for N greater than 3, the capacitance of the mirror dominates the output capacitance and totally degrades the performances. Once the number of stages has been chosen, we still have to choose W1. This can be done by optimizing noise, area and power consumption.

**Figure 6.** a) *f Nstab* \* vs. ( *gm Id* )i 1 (eq. 28), b) evolution of ( *gm Id* )1max , and c) total amplifier voltage gain *ANs* vs. N. *BWtrans*=2.π.1GHz, *XA*=3, ( *gm Id* )2 = 2.5 *V-1*, and ST 0.13μm PD-SOI technology.

#### **3.3 Noise**

*XC*2≃

342 Photodiodes - From Fundamentals to Applications

pendency on ( *gm*

( *gm Id* )1<sup>≤</sup>

The selection of ( *gm*

tion of *XC2* on ( *gm*

the mirror *Vdssat2*

Once ( *gm*

fixed ( *gm*

*Id* )2

*Id* )2

because of a good ( *gm*

*Id* )2

*Id* )2

*Id* )1max

compared to *idn1*. This implies to have ( *gm*

the capacitance of the mirror. Indeed, ( *gm*

*Cd*2 *Cgs*<sup>1</sup> = *Cgd o*<sup>2</sup>

*Id* )1, ( *gm*

due to the term *XC2*:

and area and to maximize speed performances, the maximum value of ( *gm*

2.*π*. *f <sup>t</sup>* (1 + *XC* + *XC*2).*XN* .*XA*.*BWtrans*.*Vea*.*L eqi*

*XC*<sup>2</sup> <sup>=</sup> *<sup>f</sup>*(( *gm*

.*L* <sup>2</sup> + *Cox*.*l*

*Cgso*<sup>1</sup>

As L1 and L2 are usually kept to their minimum value in order to minimize capacitances

ces. To keep W2 small compared to W1, and then keep negligible the effect of the degrada‐

inversion. However, this reduces the dynamic range by increasing the saturation voltage of

. In strong inversion, the latter can be approximated by:

<sup>=</sup> <sup>2</sup> ( *gm*

from the maximum voltage gain as done earlier. As can be seen on fig. 6, the optimal number of stages for the gain is now reduced from 9 to 3 when taking into account the correction due to

, *XC2* increases with N due to the decrease of the ratio *idn1*/*idn2* with ( *gm*

dicates that the mirror has a more detrimental effect when increasing the number of stages,

These values are nearly identical until N=3. This indicates that, as long as its size is kept small

than 3, the capacitance of the mirror dominates the output capacitance and totally degrades the

*Id* )1max

*Id* )1 larger than ( *gm*

*Id* )1max

, and thus on the gain and on *Rf*

*Vdssat*<sup>2</sup>

has been chosen, we can deduce ( *gm*

which can be observed when comparing the values of ( *gm*

*ov* + *Cxjo*.*Xj*

*i dn*1 *i dn*2 . *L* 2 *L* 1

= *f Nstab* \* (( *gm*

results in a trade-off between dynamic range and other performan‐

*Id* )2, *<sup>L</sup>* 1, *<sup>L</sup>* 2) (27)

*Id* )1

, we see that we need *idn2* to be large

*Id* )2 and bias the mirror in strong

*Id* )1, ( *gm*

*Id* )2 (29)

now decreases more rapidly with N as, for a

*Id* )1max

*Id* ) ratio, the mirror has a relatively small influence while for N greater

and the maximum number of stages

*Id* )1

*vs*. N on fig. 6c) and fig. 5b).

. This in‐

has now a de‐

*Id* )2) (28)

*<sup>L</sup>* <sup>1</sup> .

To analyze the TIA noise performance, we have to consider its major noise sources which are the feedback resistor, *Rf* , thermal noise, modeled by the voltage noise source, *SvRf* 2 and the voltage amplifier noise. The latter is concentrated in the voltage noise source at the gate of the input transistor of the amplifier (gate of M1 of the first stage), *SvgAmp* 2 . The power spectral density of the feedback noise source is given by:

$$\{Sv\_{R\_{\uparrow}}^2(f) = 4kT \, R\_f\} \tag{30}$$

For the amplifier power spectral density referred to its input, in a first approximation, we can only take into account the noise of the first stage, as, from stage to stage, the relative im‐ portance of the noise of each subsequent stage is approximatively divided by the gain of each preceding stage. *SvgAmp* 2 is then given by:

$$\left\| Sv \, g\_{Amp}^2(f) \simeq Sv \, g\_1^2 + 2 \left| \frac{\left(\frac{\mathcal{g}m}{Id}\right)\_2}{\left(\frac{\mathcal{g}m}{Id}\right)\_1} \right|^2 . \, Sv \, g\_2^2 \tag{31}$$

where *Svg*<sup>1</sup> 2 and *Svg*<sup>2</sup> 2 are the power spectral densities of the equivalent voltage noise sour‐ ces at the gate of first stage transistors M1 and M2 respectively. A factor 2 was introduced for *Svg*<sup>2</sup> <sup>2</sup> terms, as we assumed that M2 was biased by an identical mirror transistor. In tran‐ simpedance design where the TIA bandwidth is usually high compared to the corner fre‐ quency, i.e. the frequency at which the 1/f noise of the transistors becomes negligible in comparison with the thermal noise, we can neglect the 1/f terms in *Svg*<sup>i</sup> 2 and express:

$$\operatorname{Svg}\_i^2(f) \simeq \operatorname{Svg}\_{1\_{\text{th}}}^2 = \frac{4kT}{\operatorname{g}m\_i}.n.\alpha\alpha = \frac{2}{3 + \left(\left(\frac{\operatorname{gm}}{\operatorname{id}}\right)\_i.n.U\_t\right)^2} \tag{32}$$

2

*Sv*

*s sR C*

*R*

2 2

*f inT Amp*

*f inT N*

2 2.

*outA outT*

; (37)

which raises it to a maximum plateau value

<sup>2</sup> compared to its low frequency value in the fre‐

ò ; (38)

ò ; (39)

p

*f*

() () . |1 . | .|1 . . |

*A* + +


*s sR C*

quency range between the TIA and amplifier bandwidth. The RMS value of the output noise

2 0 ( ) *nout TIA out v Sv f df* ¥

To simplify the calculations, as was done in [21], the complete integral is approximated by

<sup>2</sup> <sup>0</sup>

*BW*

<sup>1</sup> . .[arctan( )] . 2. <sup>2</sup> 1 ( .) *trans trans*

*<sup>w</sup> df ft ft ft <sup>f</sup> BW*


+

4 . .

*kT R <sup>v</sup> df jw*

*trans*

¥ = =

*trans*

ò (40)

*f*

*Ns*

+ +

*A*

2.*π*.*Rf* .*Cin*

,

, 2

*n*

• the integral of the noise of the feedback resistor, which we can approximate by:

¥

<sup>0</sup> <sup>2</sup> <sup>0</sup>

+

*s R C Svg Sv f R C*

*Ns*

Design of Multi Gb/s Monolithically Integrated Photodiodes and Multi-Stage Transimpedance Amplifiers in Thin-Film

However, at medium frequency in the bandwidth of the transimpedance, the amplifier con‐

2 2.

*outA outA*

SOI CMOS Technology

345

http://dx.doi.org/ 10.5772/50531

*f inT N*

; ; (36)

2 2

2

exhibits a zero at the frequency <sup>1</sup>

2 is increased by a factor *ANs*

the sum of three components. They are, respectively:

*trans*

p

¥

+

*out*

tribution to the noise *Svoutamp*

where *Svoutamp*

is given by:

Since:

we have:

*out out*

*Rf*

*Sv f Sv f R C*

2 which is:

where the parameter α has the well known 2/3 value in strong inversion and 1/2 in weak inversion [28]. We then derive:

$$Sv\,g\_{Amp}^{2}(f) \simeq \frac{4kT}{g\,m\_1}.\ n.\alpha\_1 \left| 1 + 2.\frac{\left(\frac{gm}{Id}\right)\_2}{\left(\frac{gm}{Id}\right)\_1}.\frac{\alpha\_2}{\alpha\_1} \right| = \frac{4kT}{g\,m\_{eq}}.\alpha\_1\tag{33}$$

The total TIA output noise power spectral density is finally given by:

$$\mathrm{Sv}\_{out}^{2}(f) \simeq \frac{\mathrm{Sv}\_{R\_{\uparrow}}^{2} + \left| \mathbf{1} \mathbf{=} \mathbf{s}. \mathbf{R}\_{f}. \mathbf{C}\_{inT} \right|^{2} \cdot \mathrm{Sv} \, \mathrm{g}\_{Amp}^{2}}{\left| \mathbf{1} + \mathbf{s}. \frac{\mathbf{R}\_{f}. \mathbf{C}\_{inT}}{A\_{\mathrm{Ns}}} \right|^{2} \cdot \left| \mathbf{1} + \mathbf{s}. \mathbf{R}\_{outA}. \mathbf{C}\_{outT} \right|^{2.N}} \tag{34}$$

To compare with the noise of the simple resistor system (eq. 3), we can calculate the equiva‐ lent input referred current noise power spectral density of the transimpedance amplifier:

$$\mathrm{S}\dot{i}\_{in}^{2}(f) \simeq \frac{4kT}{R\_{f}} + \frac{|\,1 + s.\mathrm{R}\_{f}.\mathrm{C}\_{iNT}\,|^{2}}{R\_{f}^{2}}.\mathrm{Svg}\_{Amp}^{2} \tag{35}$$

As *Rf* is A (the voltage gain) times higher than *RL* for same bandwidth and same input ca‐ pacitance, the TIA noise power is reduced by about a factor A. The shape of *Svg*out 2 vs. *f* is plotted in fig. 7a. At low frequencies, the noise is usually dominated by the resistor noise (*Rf* > > 1 *gm*<sup>1</sup> ):

**Figure 7.** a) *Svout* <sup>2</sup> ( *<sup>f</sup>* ) vs. *f* for W1=1μm. b) *iph* for W1=4μm. *BWtrans*=2.π.1GHz, *XA*=3, ( *<sup>g</sup>*<sup>m</sup> *Id* )2 = 2.5 *V-1* and ST 0.13μm PD-SOI technology.

Design of Multi Gb/s Monolithically Integrated Photodiodes and Multi-Stage Transimpedance Amplifiers in Thin-Film SOI CMOS Technology http://dx.doi.org/ 10.5772/50531 345

$$\left\| Sv\_{\rm out}^{2}(f) \simeq Sv\_{\rm out\_{\rm y}}^{2}(f) \right\| = \frac{Sv\_{\rm R\_{f}}^{2}}{\left\| \mathbf{1} + \mathbf{s} . \frac{\mathbf{R}\_{f} \cdot \mathbf{C}\_{\rm inT}}{A\_{\rm N}} \right\|^{2} \cdot \left\| \mathbf{1} + \mathbf{s} . R\_{\rm outA} \mathbf{C}\_{\rm outA} \right\|^{2N}} \tag{36}$$

However, at medium frequency in the bandwidth of the transimpedance, the amplifier con‐ tribution to the noise *Svoutamp* 2 which is:

$$\text{Svo}\_{\text{out}\_{\text{Aup}}}^2(f) \simeq \frac{|\mathbf{1} + \mathbf{s}. \mathbf{R}\_f. \mathbf{C}\_{\text{in}T}|^2. \text{Svy}\_{\text{Aup}}^2}{|\mathbf{1} + \mathbf{s}. \frac{\mathbf{R}\_f. \mathbf{C}\_{\text{in}T}}{A\_{\text{Ns}}}|^2 \cdot |\mathbf{1} + \mathbf{s}. \mathbf{R}\_{\text{out}A}. \mathbf{C}\_{\text{out}T}|^{2.N}}\tag{37}$$

exhibits a zero at the frequency <sup>1</sup> 2.*π*.*Rf* .*Cin* which raises it to a maximum plateau value where *Svoutamp* 2 is increased by a factor *ANs* <sup>2</sup> compared to its low frequency value in the fre‐ quency range between the TIA and amplifier bandwidth. The RMS value of the output noise is given by:

$$\upsilon\_{n\_{\text{out},\text{TA}}} = \sqrt{\underset{\upsilon}{\text{Sv}\_{\text{out}}^2(f)df}} \tag{38}$$

To simplify the calculations, as was done in [21], the complete integral is approximated by the sum of three components. They are, respectively:

• the integral of the noise of the feedback resistor, which we can approximate by:

$$\left. \psi \right|\_{n\_{\rm out,F\_f}}^2 = \int\_0^\circ \frac{4kT.R\_f}{\|\mathbf{1} + \frac{jw}{BVV\_{\rm trans}}\|^2} \, df \tag{39}$$

Since:

*Svgi* 2

344 Photodiodes - From Fundamentals to Applications

*SvgAmp*

*Svout* <sup>2</sup> ( *f* )≃

*Siin*

As *Rf*

(*Rf* > >

1 *gm*<sup>1</sup> ):

**Figure 7.** a) *Svout*

SOI technology.

inversion [28]. We then derive:

( *f* )≃*Svg*1*th*

<sup>2</sup> ( *<sup>f</sup>* )<sup>≃</sup> <sup>4</sup>*kT*

*gm*<sup>1</sup>

The total TIA output noise power spectral density is finally given by:

*SvRf*

*Rf* .*CinT ANs*


2( *<sup>f</sup>* )<sup>≃</sup> <sup>4</sup>*kT Rf* +

.*n*.*α*1.(1 + 2.

<sup>2</sup> <sup>=</sup> <sup>4</sup>*kT gmi* .*n*.*αα* <sup>=</sup> <sup>2</sup> 3 + (( *gm id* )*<sup>i</sup>* .*n*.*Ut* )

where the parameter α has the well known 2/3 value in strong inversion and 1/2 in weak

<sup>2</sup> <sup>+</sup> |1=*s*.*Rf* .*CinT* <sup>|</sup><sup>2</sup>

To compare with the noise of the simple resistor system (eq. 3), we can calculate the equiva‐ lent input referred current noise power spectral density of the transimpedance amplifier:

> |1 + *<sup>s</sup>*.*Rf* .*CiNT* <sup>|</sup><sup>2</sup> *Rf*

plotted in fig. 7a. At low frequencies, the noise is usually dominated by the resistor noise

pacitance, the TIA noise power is reduced by about a factor A. The shape of *Svg*out

<sup>2</sup> ( *<sup>f</sup>* ) vs. *f* for W1=1μm. b) *iph* for W1=4μm. *BWtrans*=2.π.1GHz, *XA*=3, ( *<sup>g</sup>*<sup>m</sup>

is A (the voltage gain) times higher than *RL* for same bandwidth and same input ca‐


.*SvgAmp* 2

<sup>2</sup> .*SvgAmp*

.|1 + *<sup>s</sup>*.*RoutA*.*CoutT* <sup>|</sup>2.*<sup>N</sup>* (34)

*Id* )2

= 2.5 *V-1* and ST 0.13μm PD-

( *gm Id* )2 ( *gm Id* )1 . *α*2 *<sup>α</sup>*<sup>1</sup> ) <sup>=</sup> <sup>4</sup>*kT gmeq* 2 (32)

.*α*<sup>1</sup> (33)

<sup>2</sup> (35)

2 vs. *f* is

$$\int\_{0}^{\pi} \frac{1}{1 + (\frac{2.\pi}{BV\_{\text{trans}}}.f)^{2}}.df = f t\_{\text{trans}}.\text{[arctan(\frac{w}{ft\_{\text{trans}}})]\_{0}^{\circ} = \frac{\pi}{2}.ft\_{\text{trans}}\tag{40}$$

we have:

$$\left|\upsilon\_{n\_{\rm out,R\_f}}^2\right.\tag{4kT.R\_f} \left.\frac{\pi}{\cdot \mathbf{2}} f \, t\_{\rm trans} = \frac{kT}{C\_{\rm int}}.A\_{\rm Ns}\tag{41}$$

*vnout*,*TIA* <sup>=</sup> *vnout*,*Rf*

<sup>=</sup> *kT CinT*

<sup>=</sup> *kT Ceq*

The *kT Ceq*

tor. We have:

*i*

**3.4 BER, sensitivity and dynamic range**

*nin*, *ph* = 2.*q*.*I ph* .

other sources of noise. The total input noise is given by:

<sup>2</sup> <sup>+</sup> *vnout*,*amp*<sup>1</sup>

*α*1 *gmeq*.*Rf*

.*ANs* 1 +

. 1 + *f amp*

the equivalent input noise current reduces with *Rf*

<sup>2</sup> <sup>+</sup> *vnout*,*amp*<sup>2</sup> 2

> *i nin*,*TIA* =

*π* <sup>2</sup> *f ttransi*

*i*

.( 2 *π* + *ANs*

<sup>2</sup> (*an*.*XN* .*XA* <sup>−</sup> <sup>2</sup>

dependency of the noise is usual and conform to the theory of system in feedback

and is given by:

loop. To reduce the amplifier contribution (*famp*) to the output noise, we see that we need a value of *gmeq* (and then of *gm1*) as well as a value of *Rf* as high as possible. The RMS value of

Design of Multi Gb/s Monolithically Integrated Photodiodes and Multi-Stage Transimpedance Amplifiers in Thin-Film

*vnout*,*TIA Rf*

It can be easily verify that for same bandwidth and same input capacitance, the input noise current reduces by about a factor *ANs* . This confirms that the input noise power of the transimpedance amplifier is reduced by about a factor *ANs* compared to the simple resistor system. Additional noise sources arise from the photodiode dark current *Idark*, the dark cur‐ rent shot noise, *inin,dark* and the photocurrent shot noise itself *inin,ph*. The latter is inherent to the mechanism of photodetection and set the ultimate detection threshold of the ideal detec‐

*nin*,*dark* = 2.*q*.*Idark* .

*Idark* can be calculated from [17] and is, for a typical SOI diode with a total length and width of 50μm, smaller than 10-12A. From eq. 50), this yields a dark current shot noise of around 10-11 A for a transition frequency of 1GHz. Both are usually negligible when compared to the

As illustrated in fig. 7b, the transimpedance readout noise usually dominates at low input

In order to achieve a given BER (Bit Error Rate), *iph* must be at least a factor Q times larger than the RMS value of the input noise. For a typical BER of 10-12, Q must be equal to 7.

current, while at high input current it is the photocurrent shot noise that dominates.

*π*

*nic* <sup>=</sup> *<sup>i</sup>* <sup>2</sup> <sup>+</sup> *<sup>i</sup>* <sup>2</sup> <sup>+</sup> *<sup>i</sup>* <sup>2</sup> (51)

<sup>2</sup> *f ttrans* (50)

*<sup>π</sup>* .(1<sup>−</sup> <sup>1</sup>

6.*<sup>π</sup>* )))

(48)

347

SOI CMOS Technology

http://dx.doi.org/ 10.5772/50531

(49)

• the integral of the noise of the amplifier up to the transimpedance amplifier bandwidth, which can be approximated by:

$$\left.v\_{\boldsymbol{n}\_{\boldsymbol{m}\_{\boldsymbol{m}},\boldsymbol{\Lambda}\boldsymbol{w}\boldsymbol{1}}}\right\|\_{0} \triangleq \int\_{0}^{\boldsymbol{\Lambda}\_{\text{max}}} \left|\mathbf{1} + j\boldsymbol{m}\boldsymbol{R}\_{f}\mathbf{C}\_{\boldsymbol{\Lambda}\boldsymbol{n}\boldsymbol{T}}\right|^{2} \cdot \mathrm{S} \,\mathrm{v}\mathbf{g}\_{\boldsymbol{A}\boldsymbol{w}\boldsymbol{p}}^{2} \,d\boldsymbol{f} = \mathrm{S} \,\mathrm{v}\mathbf{g}\_{\boldsymbol{A}\boldsymbol{w}\boldsymbol{p}}^{2} \cdot \left(\boldsymbol{f}\mathbf{t}\_{\text{trans}} + \frac{\boldsymbol{f}\mathbf{t}\_{\text{trans}}^{3}}{3} \cdot \left(\boldsymbol{\mathcal{Z}}\boldsymbol{\mathcal{Z}}\right)^{2} \boldsymbol{R}\_{f}^{2} \cdot \boldsymbol{\mathcal{C}}\_{\text{in}\boldsymbol{T}}^{2}\right) \tag{42}$$

This can be rewritten as:

$$
\omega v\_{n\_{\rm out,Amp}}^2 \simeq \frac{kT}{\mathbb{C}\_{\rm int}} \cdot \frac{A\_{\rm NS}}{g \, m\_{\rm eq} \, R\_f} \cdot \alpha\_1 \frac{2}{\pi} \bigg| \mathbf{1} + \frac{A\_{\rm NS}^2}{6.\pi} \right\} \tag{43}
$$

• the integral of the amplifier noise from the transimpedance amplifier bandwidth up to in‐ finity, which we can approximated by:

$$\left. \boldsymbol{\upsilon}\_{n\_{\rm out,Amp}}^2 \right| = \int\_{\boldsymbol{\rho}\_{\rm res}} \frac{A\_{\rm NS}^2 \boldsymbol{S} \boldsymbol{v} \mathbf{g}\_{\rmAmp}^2}{\left| \mathbf{1} + \frac{\boldsymbol{j} \boldsymbol{w}}{\boldsymbol{B} \boldsymbol{V} \boldsymbol{V}\_{\rm NS\_i}} \right|^{2,N}} \boldsymbol{d}f \tag{44}$$

Since [29]:

$$\int\_{0}^{\pi} \frac{1}{\left(1 + \left(\frac{2.\pi}{B\mathcal{W}\_{\mathbb{N}\_{\mathbb{N}}}} f\right)^{2}\right)^{N}}.dw = \frac{2.N - 3}{2.N - 2} \cdot \Big\|\frac{1}{\left(1 + \left(\frac{f}{f\mathbb{1}\_{\mathbb{N}\_{\mathbb{N}}}}\right)^{2}\right)^{N-1}}.df\tag{45}$$

by defining:

$$a\_n = \prod\_{k=2}^{N} \frac{2k-3}{2k-2\operatorname{a}}\tag{46}$$

we have:

$$\left| \boldsymbol{w}\_{n\_{\rm out,mp2}}^2 \simeq \boldsymbol{A}\_{\rm NS}^2. \mathrm{Svg}\_{A\rm imp}^2 \left( \boldsymbol{a}\_n \frac{\pi}{2} \boldsymbol{f} \, \boldsymbol{t}\_{\rm NS} - \boldsymbol{f} \, \boldsymbol{t}\_{\rm trans} \right) \simeq \frac{kT}{\mathbf{C}\_{\rm inT}} \cdot \frac{\boldsymbol{A}\_{\rm NS}^3}{\operatorname{gm}\_{\rm eq} \cdot \mathbf{R}\_f} \cdot \boldsymbol{a}\_1 \Big| \boldsymbol{a}\_n \boldsymbol{X}\_N \, \boldsymbol{X}\_A - \frac{2}{\pi} \right) \tag{47}$$

Finally, the TIA RMS value of the output noise is given by:

Design of Multi Gb/s Monolithically Integrated Photodiodes and Multi-Stage Transimpedance Amplifiers in Thin-Film SOI CMOS Technology http://dx.doi.org/ 10.5772/50531 347

$$\begin{split} \mathbf{v}\_{n\_{\text{out},T\text{in}}} &= \sqrt{\mathbf{v}\_{n\_{\text{out},R\_f}}^2 + \mathbf{v}\_{n\_{\text{out},\text{amp}}}^2 + \mathbf{v}\_{n\_{\text{out},\text{amp}}}^2} \\ &= \sqrt{\frac{kT}{\mathbf{C}\_{\text{in}T}}} \cdot A\_{\text{Ns}} \Big[ 1 + \frac{\alpha\_1}{g m\_{eq} R\_f} \cdot \Big( \frac{2}{\pi} + A\_{\text{Ns}}^2 \Big[ a\_n X\_N, X\_A - \frac{2}{\pi} \Big( 1 - \frac{1}{6.\pi} \Big) \Big) \Big]} \\ &= \sqrt{\frac{kT}{\mathbf{C}\_{eq}}} \cdot \Big[ 1 + f\_{\text{amp}} \Big] \end{split} \tag{48}$$

The *kT Ceq* dependency of the noise is usual and conform to the theory of system in feedback loop. To reduce the amplifier contribution (*famp*) to the output noise, we see that we need a value of *gmeq* (and then of *gm1*) as well as a value of *Rf* as high as possible. The RMS value of the equivalent input noise current reduces with *Rf* and is given by:

$$\dot{\mathbf{u}}\_{\eta\_{\text{in}\_{\text{ITA}}}} = \frac{\boldsymbol{\upsilon}\_{\eta\_{\text{out}\_{\text{ITA}}}}}{\mathbf{R}\_f} \tag{49}$$

It can be easily verify that for same bandwidth and same input capacitance, the input noise current reduces by about a factor *ANs* . This confirms that the input noise power of the transimpedance amplifier is reduced by about a factor *ANs* compared to the simple resistor system. Additional noise sources arise from the photodiode dark current *Idark*, the dark cur‐ rent shot noise, *inin,dark* and the photocurrent shot noise itself *inin,ph*. The latter is inherent to the mechanism of photodetection and set the ultimate detection threshold of the ideal detec‐ tor. We have:

$$\mathbf{i}\_{n\_{\rm in},ph} = \sqrt{2.q \, I\_{ph} \cdot \frac{\pi}{2} \, f \, t\_{\rm trans}} \mathbf{i}\_{n\_{\rm in},ph} = \sqrt{2.q \, I\_{\rm dark} \cdot \frac{\pi}{2} \, f \, t\_{\rm trans}} \tag{50}$$

*Idark* can be calculated from [17] and is, for a typical SOI diode with a total length and width of 50μm, smaller than 10-12A. From eq. 50), this yields a dark current shot noise of around 10-11 A for a transition frequency of 1GHz. Both are usually negligible when compared to the other sources of noise. The total input noise is given by:

$$i\_{n\_{\vec{n}}} = \sqrt{\dot{i}^2 + \dot{i}^2 + \dot{i}^2} \tag{51}$$

As illustrated in fig. 7b, the transimpedance readout noise usually dominates at low input current, while at high input current it is the photocurrent shot noise that dominates.

#### **3.4 BER, sensitivity and dynamic range**

*vnout*,*Rf*

*vnout*,*Amp*<sup>1</sup> <sup>2</sup> <sup>≃</sup> *kT*

finity, which we can approximated by:

which can be approximated by:

346 Photodiodes - From Fundamentals to Applications

0

This can be rewritten as:

*trans*

*ft*

, 1

*out Amp*

Since [29]:

by defining:

we have:

*vnout*,*amp*<sup>2</sup> <sup>2</sup> <sup>≃</sup> *ANs*

<sup>2</sup> .*SvgAmp*

<sup>2</sup> .(*an π* <sup>2</sup> *f tN si*

Finally, the TIA RMS value of the output noise is given by:

<sup>2</sup> <sup>≃</sup>4*kT* .*Rf* .

*ft <sup>v</sup>* + =+ *jw R C Svg df Svg ft*

*CinT*

, 2

¥ ¥

2

p

*π*

2 2 2 2 222

. *ANs gmeq*.*Rf*


<sup>2</sup> 2 1 0 0 <sup>1</sup> 2. 3 1 .. . 2. 2. 2 (1 ( . ) ) (1 ( ) )

> *an* <sup>=</sup>∏ *k*=2

*S i i*

*<sup>N</sup>* 2*k* −3

<sup>−</sup> *f ttrans*) <sup>=</sup> *kT*

*CinT*

. *ANs* 3 *gmeq*.*Rf*

*N Ns <sup>N</sup> dw df <sup>N</sup> <sup>f</sup> <sup>f</sup> BW ft*

¥

*<sup>n</sup> <sup>N</sup> ft*

+

*n f inT Amp Amp trans f inT*

<sup>2</sup> *f ttrans* <sup>=</sup> *kT*

• the integral of the noise of the amplifier up to the transimpedance amplifier bandwidth,


.*α*1. 2 *<sup>π</sup>* (1 +

• the integral of the amplifier noise from the transimpedance amplifier bandwidth up to in‐

2 2

*A Svg <sup>v</sup> df jw*

*BW*

*N N*

*Ns Amp*

2. . .

*i*

*NS*

*R C* ò ; (42)

*CinT*

.*ANs* (41)

3

ò ; (44)


<sup>2</sup>*<sup>k</sup>* <sup>−</sup>2<sup>a</sup> (46)

.*α*1(*an*.*XN* .*XA* <sup>−</sup> <sup>2</sup>

*<sup>π</sup>* ) (47)

*ANs* 2

*trans*

p

6.*<sup>π</sup>* ) (43)

In order to achieve a given BER (Bit Error Rate), *iph* must be at least a factor Q times larger than the RMS value of the input noise. For a typical BER of 10-12, Q must be equal to 7.

By definition, the sensitivity, *S*, is equal to the minimum input power to achieve a given BER. Since *iph*=*R*.*Pin*, the sensitivity is given by:

$$S = \frac{\nabla.\dot{\mathbf{i}}\_{n\_{\text{in}}}}{R} \tag{52}$$

transit time of the carriers in the diode and thus decreases its cut-off frequency *f* ctr

As the amplifier gain is chosen to fulfill the stability requirements, the value of *Rf*

**3.7 Design of a 1GHz, 3 stages SVTA Transimpedance Amplifier in 0.13** *μm* **PD-SOI**

length and width of 50μm, which is typical. We first have to choose a value for ( *gm*

creases, and *XC2* increases compared to *XC*. As a result, the maximum value of ( *gm*

We will now apply the design methodology presented above to the design of a 1GHz, 3 stages SVTA transimpedance amplifier in a typical 0.13 *μm* PD-SOI CMOS technology. The model has been implemented using Matlab. We assume that the photodiode has a total

small with regard to 1, the output voltage swing can be increased significantly by increasing

sure proper dynamic range margin and reliability against statistical variations on *Vth*. How‐

*Id* )1

still have to determine the value of W1 based on model results of fig. 9. If we increase W1,

to keep the transition frequency at the required value of 1GHz. Note that while the output

, the value of ( *gm*

and then *idn2* are constant, W2 also increases with W1. Since W1 and W2 are in‐

, while the other performances are only slightly degraded. This can be useful to en‐

fixes the capacitance *Cph* and the number of finger, m, of the diode, and influences *Cin*.

Design of Multi Gb/s Monolithically Integrated Photodiodes and Multi-Stage Transimpedance Amplifiers in Thin-Film

such that *fctr*

adapted in order to maintain the RC frequency of the dominant pole.

on Matlab results of fig. 8. As explained above, by increasing ( *gm*

can choose to ensure stability also decreases. While the ratio of

*Id* )2

*Id* )1

creased, the input capacitance is increased and then *Rf*

transition. The mirror suddenly becomes too big compared to M1. A ( *gm*

*Id* )2

voltage of the input transistor, M1, of the amplifier, *Li*

will then fix the value of *Li*

the receiver. Note that as *fctr*

**CMOS technology**

of *Li*

( *gm Id* )2

and ( *gm Id* )2

ever, the ratio of

achieve a reasonable trade-off.

the bias current increases as ( *gm*

Once we have chosen the value of ( *gm*

*W*<sup>2</sup> *W*<sup>1</sup>

performances, even the dynamic range (as ( *gm*

vs. ( *gm*

[1]. We

349

SOI CMOS Technology

. The choice

*Id* )2

*Id* )1

remains sufficiently

of 2-2.5 seems to

, the ratio of

based

*W*<sup>2</sup> *W*<sup>1</sup> in‐

that we

is then

> *fttrans* where *fttrans* is the desired cut-off frequency of

and *Cph* depend on ( *gm*

*Id* )2

*W*<sup>2</sup> *W*<sup>1</sup>

collapses), are greatly degraded after this

*Id* )2

must decrease accordingly, in order

is determined by eq. (28). We

has a very sharp transition around 3.1 and all the

*Id* )1

and then *idn1* are constant. As the bias current increases

*Id* )1

http://dx.doi.org/ 10.5772/50531

depends on the bias of the diode [1], which is equal to the gate

where *R* is the responsivity of the photodiode. It can be calculated with the model devel‐ oped in [17]. To ensure that the receiver can achieve the required BER, we must have:

$$S \le P\_{\text{int}\_{\text{max}}} \tag{53}$$

where *Pinmax* is the maximum input power before saturation of the receiver (due to its dynam‐ ic range limitation). In the dark, the current flowing through *Rf* is negligible and the output voltage is about equal to the gate voltage of M1. When a photocurrent *iph* crosses *Rf* , the max‐ imum reachable output voltage is Vdd, the supply voltage, minus the saturation voltage of the transistor M2, *Vdsat2* . We can derive the maximum photocurrent and from there the maxi‐ mum input power before saturation of the receiver:

$$I\_{ph\_{\max}} = \frac{Vdd - Vd\_{sat\_2} - V\mathcal{g}\_1}{Rf} P\_{in\_{\max}} = \frac{I\_{ph\_{\max}}}{R} \tag{54}$$

#### **3.5. Power consumption**

The power consumption of the TIA is equal to the power consumption of the N stages plus the power consumption of the biasing branch:

$$P\_{tot} = \{N+1\}.Vdd.Id = \{N+1\}.Vdd.\frac{W1}{L-1}.i\_{dn1} \tag{55}$$

For a given W1, the power consumption increases with N due to the increased number of stages but also due to the increase of power consumption per stage related to the decrease of ( *gm Id* )1 and the related increase of *idn1* with N for for a given transition frequency. Once N and the related ( *gm Id* )1 have been chosen, the power consumption linearly increases with W1.

#### **3.6 Diode capacitance Optimization**

The diode capacitance *Cph* must be accounted for when optimizing the detector. As dis‐ cussed in [1], *Cph* is proportional to the diode area, *Ad*, which is fixed by the diameter D of the optical fiber that carries the light signal, and inversely proportional to the length *Li* of the intrinsic zone. To decrease this capacitance, we could increase *Li* . However this increases the transit time of the carriers in the diode and thus decreases its cut-off frequency *f* ctr [1]. We will then fix the value of *Li* such that *fctr* > *fttrans* where *fttrans* is the desired cut-off frequency of the receiver. Note that as *fctr* depends on the bias of the diode [1], which is equal to the gate voltage of the input transistor, M1, of the amplifier, *Li* and *Cph* depend on ( *gm Id* )1 . The choice of *Li* fixes the capacitance *Cph* and the number of finger, m, of the diode, and influences *Cin*. As the amplifier gain is chosen to fulfill the stability requirements, the value of *Rf* is then adapted in order to maintain the RC frequency of the dominant pole.

By definition, the sensitivity, *S*, is equal to the minimum input power to achieve a given

where *R* is the responsivity of the photodiode. It can be calculated with the model devel‐

where *Pinmax* is the maximum input power before saturation of the receiver (due to its dynam‐

imum reachable output voltage is Vdd, the supply voltage, minus the saturation voltage of

−*V g*<sup>1</sup> *Rf Pin*max <sup>=</sup>

The power consumption of the TIA is equal to the power consumption of the N stages plus

For a given W1, the power consumption increases with N due to the increased number of stages but also due to the increase of power consumption per stage related to the decrease of

The diode capacitance *Cph* must be accounted for when optimizing the detector. As dis‐ cussed in [1], *Cph* is proportional to the diode area, *Ad*, which is fixed by the diameter D of the optical fiber that carries the light signal, and inversely proportional to the length *Li*

and the related increase of *idn1* with N for for a given transition frequency. Once N

oped in [17]. To ensure that the receiver can achieve the required BER, we must have:

voltage is about equal to the gate voltage of M1. When a photocurrent *iph* crosses *Rf*

*Vdd* −*V dsat*<sup>2</sup>

*Ptot* =(*N* + 1).*Vdd*.*Id* =(*N* + 1).*Vdd*.

intrinsic zone. To decrease this capacitance, we could increase *Li*

*<sup>R</sup>* (52)

*S* ≤*Pin*max (53)

. We can derive the maximum photocurrent and from there the maxi‐

*I ph* max

*W* 1 *<sup>L</sup>* <sup>1</sup> .*<sup>i</sup>*

have been chosen, the power consumption linearly increases with

is negligible and the output

*<sup>R</sup>* (54)

*dn*<sup>1</sup> (55)

. However this increases the

, the max‐

of the

*S* = 7.*i nin*

ic range limitation). In the dark, the current flowing through *Rf*

mum input power before saturation of the receiver:

*I ph* max =

the power consumption of the biasing branch:

*Id* )1

**3.6 Diode capacitance Optimization**

BER. Since *iph*=*R*.*Pin*, the sensitivity is given by:

348 Photodiodes - From Fundamentals to Applications

the transistor M2, *Vdsat2*

**3.5. Power consumption**

and the related ( *gm*

( *gm Id* )1

W1.

#### **3.7 Design of a 1GHz, 3 stages SVTA Transimpedance Amplifier in 0.13** *μm* **PD-SOI CMOS technology**

We will now apply the design methodology presented above to the design of a 1GHz, 3 stages SVTA transimpedance amplifier in a typical 0.13 *μm* PD-SOI CMOS technology. The model has been implemented using Matlab. We assume that the photodiode has a total length and width of 50μm, which is typical. We first have to choose a value for ( *gm Id* )2 based on Matlab results of fig. 8. As explained above, by increasing ( *gm Id* )2 , the ratio of *W*<sup>2</sup> *W*<sup>1</sup> in‐ creases, and *XC2* increases compared to *XC*. As a result, the maximum value of ( *gm Id* )1 that we can choose to ensure stability also decreases. While the ratio of *W*<sup>2</sup> *W*<sup>1</sup> remains sufficiently small with regard to 1, the output voltage swing can be increased significantly by increasing ( *gm Id* )2 , while the other performances are only slightly degraded. This can be useful to en‐ sure proper dynamic range margin and reliability against statistical variations on *Vth*. How‐ ever, the ratio of *W*<sup>2</sup> *W*<sup>1</sup> vs. ( *gm Id* )2 has a very sharp transition around 3.1 and all the performances, even the dynamic range (as ( *gm Id* )1 collapses), are greatly degraded after this transition. The mirror suddenly becomes too big compared to M1. A ( *gm Id* )2 of 2-2.5 seems to achieve a reasonable trade-off.

Once we have chosen the value of ( *gm Id* )2 , the value of ( *gm Id* )1 is determined by eq. (28). We still have to determine the value of W1 based on model results of fig. 9. If we increase W1, the bias current increases as ( *gm Id* )1 and then *idn1* are constant. As the bias current increases and ( *gm Id* )2 and then *idn2* are constant, W2 also increases with W1. Since W1 and W2 are in‐ creased, the input capacitance is increased and then *Rf* must decrease accordingly, in order to keep the transition frequency at the required value of 1GHz. Note that while the output capacitance is also increased by the increase of W1 and W2, the output pole stays at the same frequency as the output impedance is automatically reduced accordingly by the in‐ crease of the bias current. The stability requirement (eq. 18) is thus satisfied. Larger transis‐ tors are intrinsically less noisy as gm is increased (see eq. 32). As a result, the TIA noise is reduced when W1 and W2 are increased. This leads to a better receptor sensitivity. A W1 of 4 *μm* seems to be a good trade-off. Note that the output dynamic range is constant with W1 as it is only a function of ( *gm Id* )1 and ( *gm Id* )2 . Thus the input dynamic range and the maxi‐ mum input power increase with W1 because *Rf* is decreased. However, in any case, S is well

below *Pinmax* and the required sensitivity is then achieved. A very good sensitivity of approxi‐ mately 1μW is achieved at a wavelength of 405 nm. This demonstrates the potential of SOI thin-film photodiodes for blue DVD and short-distance optical applications. The bias cur‐ rent is about 200μA which leads to a power consumption of:

**Table 1.** Model Results for 1GHz 3 stages TIA design in a 0.13μm SOI CMOS technology

cal curves (*ft*

tion. By increasing *Rf*

signal. c) TIA output noise spectral power density, *Svg*out

are given for the Matlab results. *Rf*

and by Eldo numerical simulations. The noise contribution from *Rf*

=332.800k Ω.

Modeled performances are in table 1. Numerical simulations of the designed circuit have then be carried out using Eldo and a BSIMSOI model fitted for ST transistors. Both values of transimpedance gain given by Matlab and by Eldo are very close from each other and around 330 kΩ (fig. 10a). However, the BSIMSOI model used in Eldo is slightly different from that we have used in the Matlab design. In the latter, we have indeed used technologi‐

Design of Multi Gb/s Monolithically Integrated Photodiodes and Multi-Stage Transimpedance Amplifiers in Thin-Film

which were extracted from ST transistors measurements done at UCL. The main differences are slightly higher drain capacitances and higher Early voltages for the BSIMSOI model. The slightly higher drain capacitance lowers the frequency of the non-dominant poles. It also de‐ creases the frequency of the dominant pole, but in this case this effect was more than bal‐ anced by the increase of *Vea,* which results in an increase in *ANs* and in the TIA bandwidth up to 2.5GHz. This reduces the phase margin of the TIA compared to Matlab and leads to a peaking of around 2.5dB in the transfer function given by Eldo. In order to increase the phase margin and reduce the peaking, we can increase the value of *Rf* in the Eldo simula‐

bandwidth reduces to 1.2 GHz, while the TIA transimpedance gain is increased by 2.1.

**Figure 10.** a) Comparison of transimpedance gain in dBΩ vs. frequency given by our model implemented with Matlab and by Eldo numerical simulations. b) TIA output voltage variation, *vout*, to 1ns width photocurrent pulses given by El‐ do transient numerical simulations. The input photocurrent, *iph* multiplied by the TIA gain is also given as reference

*,* transistor capacitances, transconductance, output conductances...) vs. *gm*

up to 700kΩ, the peaking is reduced to a value below 0.1dB, the TIA

2 , *vs.* frequency given by our model implemented with Matlab

and from the amplifier to the total spectral density

*id*

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**Figure 8.** a) Performance of TIA vs. ( *gm Id* )2 b) idem for W1=4μm. *BWtrans*=2.π.1GHz, *XA*=3 and ST 0.13μm PD-SOI tech‐ nology.

**Figure 9.** Performance of TIA vs. W1. *BWtrans*=2.π.1GHz, *XA*=3 and ST 0.13μm PD-SOI technology.

$$P\_{\text{bol}} = 4 \times 1.2V \times 20 \,\mu A = 960 \,\mu W \,\tag{56}$$

Design of Multi Gb/s Monolithically Integrated Photodiodes and Multi-Stage Transimpedance Amplifiers in Thin-Film SOI CMOS Technology http://dx.doi.org/ 10.5772/50531 351


**Table 1.** Model Results for 1GHz 3 stages TIA design in a 0.13μm SOI CMOS technology

capacitance is also increased by the increase of W1 and W2, the output pole stays at the same frequency as the output impedance is automatically reduced accordingly by the in‐ crease of the bias current. The stability requirement (eq. 18) is thus satisfied. Larger transis‐ tors are intrinsically less noisy as gm is increased (see eq. 32). As a result, the TIA noise is reduced when W1 and W2 are increased. This leads to a better receptor sensitivity. A W1 of 4 *μm* seems to be a good trade-off. Note that the output dynamic range is constant with W1

as it is only a function of ( *gm*

350 Photodiodes - From Fundamentals to Applications

**Figure 8.** a) Performance of TIA vs. ( *gm*

nology.

*Id* )1

rent is about 200μA which leads to a power consumption of:

*Id* )2

**Figure 9.** Performance of TIA vs. W1. *BWtrans*=2.π.1GHz, *XA*=3 and ST 0.13μm PD-SOI technology.

and ( *gm*

*Id* )2

mum input power increase with W1 because *Rf* is decreased. However, in any case, S is well below *Pinmax* and the required sensitivity is then achieved. A very good sensitivity of approxi‐ mately 1μW is achieved at a wavelength of 405 nm. This demonstrates the potential of SOI thin-film photodiodes for blue DVD and short-distance optical applications. The bias cur‐

. Thus the input dynamic range and the maxi‐

b) idem for W1=4μm. *BWtrans*=2.π.1GHz, *XA*=3 and ST 0.13μm PD-SOI tech‐

*Ptot* =4×1.2*V* ×20*μA*=960*μW* (56)

Modeled performances are in table 1. Numerical simulations of the designed circuit have then be carried out using Eldo and a BSIMSOI model fitted for ST transistors. Both values of transimpedance gain given by Matlab and by Eldo are very close from each other and around 330 kΩ (fig. 10a). However, the BSIMSOI model used in Eldo is slightly different from that we have used in the Matlab design. In the latter, we have indeed used technologi‐

cal curves (*ft ,* transistor capacitances, transconductance, output conductances...) vs. *gm id*

which were extracted from ST transistors measurements done at UCL. The main differences are slightly higher drain capacitances and higher Early voltages for the BSIMSOI model. The slightly higher drain capacitance lowers the frequency of the non-dominant poles. It also de‐ creases the frequency of the dominant pole, but in this case this effect was more than bal‐ anced by the increase of *Vea,* which results in an increase in *ANs* and in the TIA bandwidth up to 2.5GHz. This reduces the phase margin of the TIA compared to Matlab and leads to a peaking of around 2.5dB in the transfer function given by Eldo. In order to increase the phase margin and reduce the peaking, we can increase the value of *Rf* in the Eldo simula‐ tion. By increasing *Rf* up to 700kΩ, the peaking is reduced to a value below 0.1dB, the TIA bandwidth reduces to 1.2 GHz, while the TIA transimpedance gain is increased by 2.1.

**Figure 10.** a) Comparison of transimpedance gain in dBΩ vs. frequency given by our model implemented with Matlab and by Eldo numerical simulations. b) TIA output voltage variation, *vout*, to 1ns width photocurrent pulses given by El‐ do transient numerical simulations. The input photocurrent, *iph* multiplied by the TIA gain is also given as reference signal. c) TIA output noise spectral power density, *Svg*out 2 , *vs.* frequency given by our model implemented with Matlab and by Eldo numerical simulations. The noise contribution from *Rf* and from the amplifier to the total spectral density are given for the Matlab results. *Rf* =332.800k Ω.

We then performed transient simulation of the transimpedance circuit (fig. 10b) for both *Rf* values. The variation of the output voltage, *vout* to the 1ns width photocurrent pulses con‐ firms that in a simulation point of view, both circuits (identical amplifier, but different *Rf* values) are suitable for 1 GBps applications. Compared to the circuit with *Rf* =700k Ω, that with *Rf* =332.8k Ω has steeper response (as its bandwidth is higher) but higher overshooting that requires a longer time to vanish (as its phase margin is lower). The multistage amplifier voltage gain *ANs* that fixes the TIA bandwidth and phase margin, hence its stability, depends on *Vea <sup>N</sup>* . This Early voltage is difficult to model carefully, especially in deep sub-micron process, as it can quite vary statistically with fabrication process and short channel effects. It is therefore a critical issue in the design of multistage amplifier TIA. In order to handle it, a sufficient phase margin has to be taken into account. In our case, the phase margin seems sufficient despite the increase of *Vea* by about a factor 2. The possibility to tune the feedback resistor in the design is another very interesting and efficient solution. This can be achieved by using a transistor to implement *Rf* and by tuning its gate voltage.

sponds to 10GBps application. As just discussed in the section 3.1, for this kind of applica‐ tions, the optimal number of stages is 1. This is simply due to the fact that there is no room to place extra poles in the feedback loop to achieve stability. In fig. 4b, we can also see that

Design of Multi Gb/s Monolithically Integrated Photodiodes and Multi-Stage Transimpedance Amplifiers in Thin-Film

lengths of the transistors, this will lead to very low achievable voltage gains. If we optimize the design for low voltage gain and high bandwidth, the value of the feedback resistor, *Rf*

will be low and comparable with the value of the output impedance of the amplifier. In this

use an output buffer. In our case, however, this has to be rejected as it would add an extra pole in the feedback loop. We thus have to accordingly adapt our design scheme to take into

the degenerated case compared to the previous one that we will refer as the non-degenerat‐

The schematic view of the single stage transimpedance is presented in fig. 11a. As previously, to simplify the analysis of this shunt-shunt feedback circuit, we can rewrite its small signal schematic in its canonical form [25] (fig. 11b). The amplifier is presented as a controlled cur‐

Ao (fig. 11b). The input capacitance, *Cin*, consists of the amplifier input capacitance, *Cg1*, and the

As previously, assuming that the dominant pole is that of the input, the bandwidth of the

Dynamic range (eq. 54) and power consumption expressions (eq. 55) are not changed com‐ pared to the non-degenerated case, while voltage gain Ao and non dominant output pole,

*BWtrans* =2*π*. *f ttrans* <sup>=</sup> *Ao*

*gout* <sup>+</sup> *gt BW*1*<sup>s</sup>* =2*π*. *f t*1*<sup>s</sup>* <sup>=</sup>

*Couts gout* <sup>+</sup> *gf* ) *Ao* + 1

*Rf Cin*

*gout* + *gf Cout*

photodiode capacitance, *Cph*. The transimpedance gain in closed loop, *Zcl* is then:

*Zel* <sup>=</sup> <sup>−</sup>*Rf*

which is also the bandwidth of the amplifier, *BW1s* now depend on *Rf*

*Ao* <sup>=</sup> *gm*<sup>1</sup>

(1 + *Rf Cins*).(1 +

**4.1 Design Methodology of single-stage Transimpedance Amplifier**

rent source with an output impedance to take account of *Rf*

that we will choose to maximize the gain is low. Combined with the small

,

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(57)

(58)

(59)

. A typical solution to this problem is to

in the expression of the voltage gain

or its inverse *gf*

:

. In the text, we will call this new case of figure

the ( *gm*

ed case.

*Id* )1max

case the voltage gain will become dependent on *Rf*

account the voltage gain dependency on *Rf*

transimpedance is given by:

Noise simulations were also performed with Eldo. Eldo spectral power density of output noise voltage are close to Matlab results (fig. 10c). Below 200kHz, both Matlab and Eldo total power densities are identical and are dominated by the feedback resistance contribution. Above, the high frequency peak values are related to the low voltage amplifier power densi‐ ties multiplied by the voltage gain of the amplifier. The higher peak in Eldo is then ex‐ plained by the higher voltage gain compared to Matlab. The equivalent RMS value of the input integrated noise given by Eldo is 41.5nA for *Rf* =332.8k Ω. This is a little higher than the 27.5nA predicted with Matlab due to the peak. For the Eldo simulations with *Rf* =700k Ω, this noise reduces to 19.1nA. As can be expected, by increasing *Rf* , the input noise and sensitivity performance of the receiver are improved.

#### **3.8 Design methodology Summary**

To summarize, in our multistage top-down design methodology, we first determine the op‐ timal number of stages (which is greater than 1 when the TIA bandwidth is not too close to the transistors frequency limit *ft* of a given technology) to optimize the voltage gain of the amplifier and hence *Rf* and the transimpedance gain. This maximum voltage gain was shown to be limited by stability considerations and to impose a value on ( *gm Id* )1 . The choice of ( *gm Id* )2 results from a trade-off between dynamic range and other performances, while W1 is chosen to compromise power consumption vs. noise and sensitivity.
