**3. Measurement Results for c-Si Solar Cells**

#### **3.1. Wafer Cleaning and Saw Damage Removal**

The scanning electron microscopic (SEM) surface image of one of the cleaned and surface damage removed wafers is shown in Fig. 3. It shows image of untreated as well as wet chemical etched wafer surface where saw damages have been removed.

#### **3.2. Surface Texturing**

The co-firing was carried out in the condition of sufficient dry and filtered air flow into the furnace. It is one of the most sensitive steps of the solar cell fabrication. Any non-uniformity in surface cleaning, texturing, doping, or even ARC can have detrimental effect on the per‐ formance of the fabricated cells as well, especially in industrial process. If co-firing is done at a temperature below optimum temperature profile, it results in high series resistance and hence low FF due to poor Ohmic front contact and poor BSF, whereas over – co-firing at a higher temperature profile may result in junction shunting and degradation in surface and bulk passivation. Thus, finding an optimum co-firing temperature profile should be always

An advantage of an LBSF compared to the standard full Al-BSF is the lower consumption of expensive printing pastes. In order to accomplish the local back contact in solar cells, many techniques have already been employed. It has been shown that the hybrid buried contact solar cell with photo lithographically defined rear contacts achieves an increase in Voc by 30mV [25] as compared with a standard buried contact cell with conventional aluminum al‐ loyed BSF, which may result in a high rear surface recombination velocity. Koschier et al. [26] also demonstrated a 30 to 40mV increase in open circuit voltage relative to conventional buried contact solar cells using the thyristor structure device on the rear which incorporates a grown p+ layer in localized regions of the passivating oxide. However, both these rear con‐ tact schemes require the use of photolithography to remove regions of the oxide to expose the underlying surface for contact, which may not be suitable for large-scale commercial so‐ lar cell fabrication processes. Other techniques of creating small area contacts such as laser

Recombination of charge carriers at the rear surface in a solar cell can be suppressed by dep‐ osition of a silicon dioxide (SiO2) layer at the back surface, grown in a high-temperature (≥900°C) oxidation process [28-29]. Additionally, the SiO2/Al stack at the rear should act as a reflector for the near band gap photons, that leads to improved light trapping properties and hence the Jsc of the solar cell may improve as well. Thermally grown SiO2 layers are manufactured using a time and energy intensive high temperature process, they may not be a good choice for mass production, although they possibly provide a good thermally stable passivation [30]. Hence, an alternative low temperature surface passivation became necessa‐ ry for future industrial production of high efficiency Si solar cells, which should have prop‐

One way of achieving this is deposition of SiNx layer by PECVD technique. It has been ob‐ served that this gives comparably low surface recombination velocity (SRVs) as compared to that with a thermal SiO2 on low resistivity p-type silicon [31-32]. However, conventional studies have mentioned certain limitations of a SiNx layer on p-type substrates [33]. When it was applied to the rear of a PERC (Passivated Emitter and Rear Cell) solar cell, the short cir‐ cuit current density (Jsc) reduced as compared to a SiO2 passivated cell [34]. This effect has been attributed to the large density of the fixed positive charges in the SiNx layer, inducing an inversion layer in the c-Si near the SiNx layer. A capacitance-voltage (C-V) measurement

the first priority in the industrial process.

114 Photodiodes - From Fundamentals to Applications

firing have been demonstrated to be feasible [27].

*2.6.3. Study of rear surface passivation with SiNx film*

erties comparable to the SiO2 passivated solar cells.

Since the concentration limit for anisotropic etching of surface texturing is 1.6 to 4 wt.%, the concentration of NaOH (wt. %) in the etchant solution was chosen as 2 wt.%. At a different etching time the resulting surface texture and specular reflection were different. For an etch‐ ing/texturing time of 25, 30, 35, 40 mins, the average specular reflectivities were 17.2, 17.0, 16.1, 15.1%.

Fig. 4 (a ), (b ), ( c ) and ( d ) shows textured wafers with the four different texturing times and depict the increase in pyramid size with increase in etching time. The average heights of the pyramids on the surface textured for 25, 30, 35, and 40 min were estimated to be ~ 3, 5, 7, and 10 μm, respectively.

**Figure 5.** Variation of phosphorus (P) concentration with the distance from the emitter surface into the wafer, As ob‐

Fabrication of Crystalline Silicon Solar Cell with Emitter Diffusion, SiNx Surface Passivation and Screen Printing of

There is a trade off between good antireflective property and surface passivation. From high frequency capacitance-voltage (C–V) measurements with metal-insulator-semiconductor (MIS) structure as Al/SiN*x*:H /*p*-type Si, one can get the electrical properties of the SiNx film. It was observed that there was a distinct charge accumulation, depletion and inversion re‐ gion in the MIS capacitor. The forward and reverse traces of the C–V curve exhibits anticlockwise hysteresis, which indicates the injection of holes into the silicon nitride film [35-36], which can also be associated with silicon dangling bonds (Si-N3) [37]. The interface state density can be calculated using Terman's analysis [38] from the high frequency C–V measurements. Properties of deposited SiNx films are given in Table 2. The energy depend‐ ent trap densities (Dit) for as deposited SiNx films, and that fired at 600, 700, 800°C tempera‐

thickness 700 Å and refractive index 2.0. The effect of surface passivation on sheet resistance is shown in Table 3. It shows that at a higher O2/POCl3 flow rate the sheet resistance be‐ comes lower. When the wafers were annealed at a temperature of 600°C, the Dit of the SiNx films with refractive indices 1.9, 2.0, 2.1, 2.2, 2.3 were 8.16 × 1010, 1.40 × 1011, 3.36 × 1011, 5.00 ×

/eV respectively, for SiNx film of

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The diffusion profile can be expressed as a complimentary error function.

**3.4. Antireflection Coating and Front Surface Passivation**

tures were 8.0 × 10 11, 1.4 × 1011, 5 × 10 10, 1.1 × 1010 cm2

/eV.

served by SIMS depth profiling.

1011, 8.60 × 1011 cm2

**Figure 4.** SEM micrographs of the silicon surface textured for (a) 25 min, (b) 30 min, ( c ) 35 min, and (d ) 40 min in and solution containing NaOH ( 2 wt. %) in DI-W water and IPA ( 6 wt. %) at 82°C.

#### **3.3. Phosphorus Diffusion for p-n Junction Formation**

After the texturing, the emitter diffusion and PSG removal were carried out. Then the wa‐ fers were rinsed in DI-W and spin dryed. A secondary ion mass spectrometric (SIMS) depth profiling was carried out to measure the emitter junction depth. Fig. 5 shows depth profiling of P atoms observed by (SIMS) into the c-Si wafer. 5×1015 cm-3 seems to be the boron concen‐ tration of the p-type wafer, with junction depth of about 300 nm from the top surface.

Fabrication of Crystalline Silicon Solar Cell with Emitter Diffusion, SiNx Surface Passivation and Screen Printing of Electrode http://dx.doi.org/10.5772/51065 117

**Figure 5.** Variation of phosphorus (P) concentration with the distance from the emitter surface into the wafer, As ob‐ served by SIMS depth profiling.

The diffusion profile can be expressed as a complimentary error function.

#### **3.4. Antireflection Coating and Front Surface Passivation**

ing/texturing time of 25, 30, 35, 40 mins, the average specular reflectivities were 17.2, 17.0,

Fig. 4 (a ), (b ), ( c ) and ( d ) shows textured wafers with the four different texturing times and depict the increase in pyramid size with increase in etching time. The average heights of the pyramids on the surface textured for 25, 30, 35, and 40 min were estimated to be ~ 3, 5, 7,

**(a) (b)**

**(c) (d)**

solution containing NaOH ( 2 wt. %) in DI-W water and IPA ( 6 wt. %) at 82°C.

**3.3. Phosphorus Diffusion for p-n Junction Formation**

**Figure 4.** SEM micrographs of the silicon surface textured for (a) 25 min, (b) 30 min, ( c ) 35 min, and (d ) 40 min in and

After the texturing, the emitter diffusion and PSG removal were carried out. Then the wa‐ fers were rinsed in DI-W and spin dryed. A secondary ion mass spectrometric (SIMS) depth profiling was carried out to measure the emitter junction depth. Fig. 5 shows depth profiling of P atoms observed by (SIMS) into the c-Si wafer. 5×1015 cm-3 seems to be the boron concen‐

tration of the p-type wafer, with junction depth of about 300 nm from the top surface.

16.1, 15.1%.

and 10 μm, respectively.

116 Photodiodes - From Fundamentals to Applications

There is a trade off between good antireflective property and surface passivation. From high frequency capacitance-voltage (C–V) measurements with metal-insulator-semiconductor (MIS) structure as Al/SiN*x*:H /*p*-type Si, one can get the electrical properties of the SiNx film. It was observed that there was a distinct charge accumulation, depletion and inversion re‐ gion in the MIS capacitor. The forward and reverse traces of the C–V curve exhibits anticlockwise hysteresis, which indicates the injection of holes into the silicon nitride film [35-36], which can also be associated with silicon dangling bonds (Si-N3) [37]. The interface state density can be calculated using Terman's analysis [38] from the high frequency C–V measurements. Properties of deposited SiNx films are given in Table 2. The energy depend‐ ent trap densities (Dit) for as deposited SiNx films, and that fired at 600, 700, 800°C tempera‐ tures were 8.0 × 10 11, 1.4 × 1011, 5 × 10 10, 1.1 × 1010 cm2 /eV respectively, for SiNx film of thickness 700 Å and refractive index 2.0. The effect of surface passivation on sheet resistance is shown in Table 3. It shows that at a higher O2/POCl3 flow rate the sheet resistance be‐ comes lower. When the wafers were annealed at a temperature of 600°C, the Dit of the SiNx films with refractive indices 1.9, 2.0, 2.1, 2.2, 2.3 were 8.16 × 1010, 1.40 × 1011, 3.36 × 1011, 5.00 × 1011, 8.60 × 1011 cm2 /eV.


improvement in lifetime, from ~ 6 μs to more than 10 μs, was observed after the phosphorus diffusion. This improvement reflects the increase in bulk as well as surface recombination lifetime during phosphorus diffusion. The thermal oxide passivation step after phosphorus diffusion causes further improvement in lifetime of about ~ 3 μs. This improvement can be attributed to the decrease of surface recombination velocity due to the passivation of surface by the thermally grown SiO2 layer. The subsequent process of edge isolation by SF6 plasma causes degradation in the lifetime by ~ 1 μs. Such a degradation is basically due to plasma induced damages, especially near the edges of the wafers that indicates the formation of re‐ combination centers on the surface during the process. A sharp rise in lifetime by ~ 3 μs was observed after deposition of non-stoichiometric TiOx films [39-40]. It is likely that fixed posi‐ tive charges in these films bend the semiconductor energy bands near the surface of the wa‐ fer, which improves the effective surface passivation [41]. A good surface passivation can be achieved by growing a thin thermal SiO2 passivation layer over TiO2 [39,42,43]. The varia‐ tion in the minority carrier lifetime during the solar cell fabrication, indicates that the sur‐ face conditions play a vital role than the bulk of the Cz-Si wafers. During the solar cell fabrication and before metallization there might have been the improvement in the lifetime due to gettering of the impurities from the bulk during phosphorus doping. The SiNx films had a refractive index between 1.90 and 2.13 and a thickness of 65 nm after annealing in the 673-1173 K temperature range. The effective lifetime of the samples became maximum for the samples annealed at 773 K, while the lifetime of almost all samples, covered with as-

Fabrication of Crystalline Silicon Solar Cell with Emitter Diffusion, SiNx Surface Passivation and Screen Printing of

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The out-diffusion of hydrogen from the Si-SiNx interface might cause degradation of life‐ time of the samples if annealed above 773 K in vacuum. The maximum recorded effective lifetime for the sample passivated with SiNx with a refractive index of 1.94, annealed at 773 K was 55.21 μs whereas a minimum lifetime of 6.3 μs was found for the sample with as-de‐

The minority carrier lifetime with different passivating films as AlON, Bare Si, Poly Si, μc-Si, SiOx, a-Si, SiNx were 9.6, 10.1, 21.5, 23.6, 43.4, 51.0, 55.2 μs respectively, where all the sam‐

The comparison of surface passivation of the electronic grade Cz-Si wafers with the different passivating layers indicates that the SiNx film is superior to other films. In order to identify the appropriate properties and annealing condition of the SiNx films for solar cell applica‐ tion, the effective lifetimes of samples, coated with PECVD grown SiNx film, were measured

900°C in air ambience of a belt furnace. The minority carrier effective lifetime of the silicon wafers, after the surface passivation with SiNx films and annealed at 500, 600, 700, 800, 900°C results in the lifetime of 42, 43, 85, 115, 64μs respectively. The annealing temperature for optimized carrier lifetime was found to be the same (760°C) as the set temperature of the belt furnace at which c-Si solar cell was earlier optimized for co-firing to ensure good Ohmic contact on the front and back surfaces in conjunction with the proper back surface field ( BSF) generation. Minority-carrier lifetime is a critical parameter for all solar cell designs. If the silicon wafers to be used for the fabrication of solar cell has a low minority carrier life‐

Pa for ~ 90sec and at temperatures, varying from 500 to

grown film, showed a minimum value.

posited SiNx film with refractive index 1.9.

ples were annealed at 773 K in vacuum.

after annealing at a pressure of ~ 105

**Table 2.** Gas Composition in the plasma and the corresponding properties of the as- deposited films. Pressure 1 Torr, substrate temperature 450°C, thickness 80nm.


**Table 3.** Comparison of emitter sheet resistance before and after the drive in step for the various different gas flow rates, where [O] is O2 flow rate and [POCl3] is POCl3 flow rate in sccm, Rsb is sheet resistance before passivation, Rsa is sheet resistance after passivation.

#### *3.4.1. Carrier lifetime measurement*

Carrier lifetime measurement can provide valuable information. We used a μ-PCD system of Semilab (WT-1000) in order to measure the carrier lifetime of the silicon wafers at various stages, with a measurement precision of ± 0.01 μs. A 940 nm wavelength laser pulse was used for generation of the photo carriers, and all the measurements were carried out in auto‐ matic parameter setting mode. The minority carrier effective lifetime of the bare wafers were measured first, thereafter (prior to metallization) the measurements of effective lifetime of silicon wafer were carried out.

#### *3.4.2. Effect of different passivating layer on carrier lifetime*

Different passivating layers such as silicon nitride (SiNx), silicon oxide (SiOx), amorphous silicon (a-Si), microcrystalline silicon (μc-Si), oxidized aluminum nitride (AlON), and oxi‐ dized porous silicon (PS) were deposited on the surfaces of the wafers. Minority carrier life‐ time was measured at least three different places of each wafer and mean of the results were taken. The results were then compared with the minority carrier effective lifetime of the bare wafer for further analysis.

We observed that the effective lifetime of each of the wafers increases by ~ 2 μs after clean‐ ing and texturing. This improvement is attributed to the removal of contaminants and struc‐ tural defects from the silicon surface after cleaning and saw damage removal. A significant improvement in lifetime, from ~ 6 μs to more than 10 μs, was observed after the phosphorus diffusion. This improvement reflects the increase in bulk as well as surface recombination lifetime during phosphorus diffusion. The thermal oxide passivation step after phosphorus diffusion causes further improvement in lifetime of about ~ 3 μs. This improvement can be attributed to the decrease of surface recombination velocity due to the passivation of surface by the thermally grown SiO2 layer. The subsequent process of edge isolation by SF6 plasma causes degradation in the lifetime by ~ 1 μs. Such a degradation is basically due to plasma induced damages, especially near the edges of the wafers that indicates the formation of re‐ combination centers on the surface during the process. A sharp rise in lifetime by ~ 3 μs was observed after deposition of non-stoichiometric TiOx films [39-40]. It is likely that fixed posi‐ tive charges in these films bend the semiconductor energy bands near the surface of the wa‐ fer, which improves the effective surface passivation [41]. A good surface passivation can be achieved by growing a thin thermal SiO2 passivation layer over TiO2 [39,42,43]. The varia‐ tion in the minority carrier lifetime during the solar cell fabrication, indicates that the sur‐ face conditions play a vital role than the bulk of the Cz-Si wafers. During the solar cell fabrication and before metallization there might have been the improvement in the lifetime due to gettering of the impurities from the bulk during phosphorus doping. The SiNx films had a refractive index between 1.90 and 2.13 and a thickness of 65 nm after annealing in the 673-1173 K temperature range. The effective lifetime of the samples became maximum for the samples annealed at 773 K, while the lifetime of almost all samples, covered with asgrown film, showed a minimum value.

**NH3 Flow (sccm)**

substrate temperature 450°C, thickness 80nm.

118 Photodiodes - From Fundamentals to Applications

sheet resistance after passivation.

*3.4.1. Carrier lifetime measurement*

silicon wafer were carried out.

wafer for further analysis.

*3.4.2. Effect of different passivating layer on carrier lifetime*

**SiH4 Flow (sccm)**

**Refractive index**

> 1.8 1.9 2.0 2.1 2.2 2.3

**Table 2.** Gas Composition in the plasma and the corresponding properties of the as- deposited films. Pressure 1 Torr,

**[O] [POCl3] Rsb (Ω/sq) Rsa (Ω/sq)** 300 600 70.5 65.5 400 800 69 64.5 500 100 68.7 63.0 600 1200 65.5 62

**Table 3.** Comparison of emitter sheet resistance before and after the drive in step for the various different gas flow rates, where [O] is O2 flow rate and [POCl3] is POCl3 flow rate in sccm, Rsb is sheet resistance before passivation, Rsa is

Carrier lifetime measurement can provide valuable information. We used a μ-PCD system of Semilab (WT-1000) in order to measure the carrier lifetime of the silicon wafers at various stages, with a measurement precision of ± 0.01 μs. A 940 nm wavelength laser pulse was used for generation of the photo carriers, and all the measurements were carried out in auto‐ matic parameter setting mode. The minority carrier effective lifetime of the bare wafers were measured first, thereafter (prior to metallization) the measurements of effective lifetime of

Different passivating layers such as silicon nitride (SiNx), silicon oxide (SiOx), amorphous silicon (a-Si), microcrystalline silicon (μc-Si), oxidized aluminum nitride (AlON), and oxi‐ dized porous silicon (PS) were deposited on the surfaces of the wafers. Minority carrier life‐ time was measured at least three different places of each wafer and mean of the results were taken. The results were then compared with the minority carrier effective lifetime of the bare

We observed that the effective lifetime of each of the wafers increases by ~ 2 μs after clean‐ ing and texturing. This improvement is attributed to the removal of contaminants and struc‐ tural defects from the silicon surface after cleaning and saw damage removal. A significant

**Deposition rate (Å /s)**

> 2.33 2.86 4.10 4.26 4.05 4.00

> > The out-diffusion of hydrogen from the Si-SiNx interface might cause degradation of life‐ time of the samples if annealed above 773 K in vacuum. The maximum recorded effective lifetime for the sample passivated with SiNx with a refractive index of 1.94, annealed at 773 K was 55.21 μs whereas a minimum lifetime of 6.3 μs was found for the sample with as-de‐ posited SiNx film with refractive index 1.9.

> > The minority carrier lifetime with different passivating films as AlON, Bare Si, Poly Si, μc-Si, SiOx, a-Si, SiNx were 9.6, 10.1, 21.5, 23.6, 43.4, 51.0, 55.2 μs respectively, where all the sam‐ ples were annealed at 773 K in vacuum.

> > The comparison of surface passivation of the electronic grade Cz-Si wafers with the different passivating layers indicates that the SiNx film is superior to other films. In order to identify the appropriate properties and annealing condition of the SiNx films for solar cell applica‐ tion, the effective lifetimes of samples, coated with PECVD grown SiNx film, were measured after annealing at a pressure of ~ 105 Pa for ~ 90sec and at temperatures, varying from 500 to 900°C in air ambience of a belt furnace. The minority carrier effective lifetime of the silicon wafers, after the surface passivation with SiNx films and annealed at 500, 600, 700, 800, 900°C results in the lifetime of 42, 43, 85, 115, 64μs respectively. The annealing temperature for optimized carrier lifetime was found to be the same (760°C) as the set temperature of the belt furnace at which c-Si solar cell was earlier optimized for co-firing to ensure good Ohmic contact on the front and back surfaces in conjunction with the proper back surface field ( BSF) generation. Minority-carrier lifetime is a critical parameter for all solar cell designs. If the silicon wafers to be used for the fabrication of solar cell has a low minority carrier life‐

time, therefore a short diffusion length, most of the minority carriers cannot be collected, and the solar cell will suffer from low conversion efficiency.

In the fifth set of experiment, we examined the relationship between the number of grid lines to the series resistance, fill factor, and shading loss in a single-crystal, 5-inch (125mm X

Fabrication of Crystalline Silicon Solar Cell with Emitter Diffusion, SiNx Surface Passivation and Screen Printing of

In order to obtain higher Voc by BSF layer, we observed that it is necessary to have the rampup rate higher than 70°C/s, that resulted in an average Voc higher than 620mV [45], as shown in Table 4. At a higher ramp-up rate and proper belt speed setting made it possible to get a higher Voc by reducing the deterioration caused by the effects of the thermal stress on the wafer. For further improvement in Voc, a densely packed Al layer or uniformly formed BSF

However, as the heat increases, micro-cracks in a wafer or bowing of the wafer may occur, leading to an increase in leakage current. Large defects or poor features of a wafer increase

For sheet resistance of 40, 50, 60Ω/sq, the carrier lifetimes were 14, 14.9, 17.2μs and surface recombination velocities were 660, 480, 425cm/sec respectively. We observed that, as the emitter sheet resistance increases, the carrier lifetime increases with the decrease in surface recombination velocity. To a certain degree, the variation in sheet resistance is dependant upon the surface doping density, which is related to electron mobility and its lifetime in a

> **Sample numbers → #1 #2 #3 #4** Belt Speed (IPM) 170 140 165 160 Temp. Slope (oC/s) 70.82 64.13 69.15 72.8 Peak Temp. (oC) 756.5 759.5 765.0 753.0 Average Voc (mV) 620.3 617.7 619.0 621.7 FF (%) 79.2 78.9 78.1 80.6

To investigate the effects of different drive-in operations, we examine the variation in Voc and the Jsc according to the sheet resistance changes. As different drive-in operations for dopant diffusion can lead to changes in sheet resistance. In this step, we used wafers of 24 μm texture, sheet resistance of 30, 40, 50, or 60Ω/sq. and 80 μm width of finger with 2.2 mm spacing shows the Voc as 621, 622, 623, 627mV and Jsc as 34.6, 34.9, 35.0, 35.3mA/cm2 respec‐ tively. The peak temperature was 759.5°C, the melting duration was 4.5s, and the belt speed

As the emitter layer becomes thinner the sheet resistance increases, it becomes difficult to fire the electrode to a moderate depths (i.e., near the pn junction). So the higher sheet resist‐ ance means thinner emitter and it is more likely to lead to a short circuit of electrodes that penetrate through the emitter. With low sheet resistance (i.e., a heavy doping) by the over-

optimize the grid line design in terms of resistance and shading loss.

layer created by a high ramp-up rate would also be helpful.

the surface recombination and leakage current.

**Table 4.** High temperature firing specifications.

) Czochralski-type solar cell. The grid model, as in ref [44], was used to

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125mm, 154.83cm2

silicon bulk [46].

was 170 IPM.

The results of this study indicate that the proper surface as well as bulk passivation in con‐ junction with gettering of defects during phosphorus diffusion can lead to a substantial gain in minority carrier effective lifetime of silicon wafers, provided the degradation of wafer surface condition during edge isolation is prevented.

#### **3.5. Metallization**

#### *3.5.1. Effect of Co-firing Temperature on Solar Cell Performance*

In order to optimize the co-firing we defined four different temperature zones in the fur‐ nace. We investigated each zone, changed stay time of the wafers in each zone, by varying the belt speed and the temperature of the zones. Emitters were formed with the sheet resist‐ ance in the range of 30 to 60Ω/sq. A uniform 80nm thick SiNx layer deposited on the front side served as an anti-reflection coating. Back and front contacts were screen printed on the wafers and baked. The back contacts were screen printed first, using Al paste, and then the wafers were dried at 150°C for 4min in a belt dryer. Then the front contacts were printed with Ag paste and the same post-printing treatment was carried out. Then the wafers were co-fired in a conventional belt-type furnace with four different temperature zones. For the maximization of the Suns-Voc we varied the temperatures T1, T2, T3, and T4 of the four ther‐ mal zones. When an optimum temperature distribution was found, we investigated differ‐ ent belt speeds keeping the temperature unchanged. By measuring Suns-Voc, we determine the effect of peak temperature change on the FF and Voc. We measured the co-firing temper‐ atures on the wafers directly in the belt-type furnace with a Datapaq 9000 system, which has a thin, sensitive thermo couple tip and a thermally insulated measuring system pack for re‐ cording the firing conditions of a wafer with a thermo couple tip on it. In the first set of ex‐ periment, without a front electrode, we varied the temperatures T1, T2, T3, and T4 in the four thermal zones and measured the Suns-Voc.

In the second set of experiments, we examined the effect of varying only the belt speed 170, 140, 165 and 160 inch per minute (IPM) on the Voc for the same sheet resistance. In this step, we used wafers of 2–4 μm texture, sheet resistance of 35 to 40 Ω/sq. and 80μm width of fin‐ ger with 2.4mm spacing metallization.

In the third set of experiments, we investigated the variation in the Voc with the changes in the sheet resistance, as obtained in different drive-in operations. In this step, we used wafers that have 2–4μm texture, sheet resistance of 30, 40, 50, and 60Ohm/sq and 80μm as width of finger with 2.2mm spacing of the metallization. The peak temperature was 759.5°C, the melting duration was 4.5s, and the belt speed was 170 IPM.

In the fourth set of experiment, we investigated firing conditions that determines sheet re‐ sistance, by varying belt speed, and temperature. We found a co-firing process window that resulted in a fill factor greater than 77%. For the metallization of the front side, we used Fer‐ ro 33-501 Ag paste with a peak temperature 700°C and a firing time <1–3s.

In the fifth set of experiment, we examined the relationship between the number of grid lines to the series resistance, fill factor, and shading loss in a single-crystal, 5-inch (125mm X 125mm, 154.83cm2 ) Czochralski-type solar cell. The grid model, as in ref [44], was used to optimize the grid line design in terms of resistance and shading loss.

In order to obtain higher Voc by BSF layer, we observed that it is necessary to have the rampup rate higher than 70°C/s, that resulted in an average Voc higher than 620mV [45], as shown in Table 4. At a higher ramp-up rate and proper belt speed setting made it possible to get a higher Voc by reducing the deterioration caused by the effects of the thermal stress on the wafer. For further improvement in Voc, a densely packed Al layer or uniformly formed BSF layer created by a high ramp-up rate would also be helpful.

However, as the heat increases, micro-cracks in a wafer or bowing of the wafer may occur, leading to an increase in leakage current. Large defects or poor features of a wafer increase the surface recombination and leakage current.

For sheet resistance of 40, 50, 60Ω/sq, the carrier lifetimes were 14, 14.9, 17.2μs and surface recombination velocities were 660, 480, 425cm/sec respectively. We observed that, as the emitter sheet resistance increases, the carrier lifetime increases with the decrease in surface recombination velocity. To a certain degree, the variation in sheet resistance is dependant upon the surface doping density, which is related to electron mobility and its lifetime in a silicon bulk [46].


**Table 4.** High temperature firing specifications.

time, therefore a short diffusion length, most of the minority carriers cannot be collected,

The results of this study indicate that the proper surface as well as bulk passivation in con‐ junction with gettering of defects during phosphorus diffusion can lead to a substantial gain in minority carrier effective lifetime of silicon wafers, provided the degradation of wafer

In order to optimize the co-firing we defined four different temperature zones in the fur‐ nace. We investigated each zone, changed stay time of the wafers in each zone, by varying the belt speed and the temperature of the zones. Emitters were formed with the sheet resist‐ ance in the range of 30 to 60Ω/sq. A uniform 80nm thick SiNx layer deposited on the front side served as an anti-reflection coating. Back and front contacts were screen printed on the wafers and baked. The back contacts were screen printed first, using Al paste, and then the wafers were dried at 150°C for 4min in a belt dryer. Then the front contacts were printed with Ag paste and the same post-printing treatment was carried out. Then the wafers were co-fired in a conventional belt-type furnace with four different temperature zones. For the maximization of the Suns-Voc we varied the temperatures T1, T2, T3, and T4 of the four ther‐ mal zones. When an optimum temperature distribution was found, we investigated differ‐ ent belt speeds keeping the temperature unchanged. By measuring Suns-Voc, we determine the effect of peak temperature change on the FF and Voc. We measured the co-firing temper‐ atures on the wafers directly in the belt-type furnace with a Datapaq 9000 system, which has a thin, sensitive thermo couple tip and a thermally insulated measuring system pack for re‐ cording the firing conditions of a wafer with a thermo couple tip on it. In the first set of ex‐ periment, without a front electrode, we varied the temperatures T1, T2, T3, and T4 in the

In the second set of experiments, we examined the effect of varying only the belt speed 170, 140, 165 and 160 inch per minute (IPM) on the Voc for the same sheet resistance. In this step, we used wafers of 2–4 μm texture, sheet resistance of 35 to 40 Ω/sq. and 80μm width of fin‐

In the third set of experiments, we investigated the variation in the Voc with the changes in the sheet resistance, as obtained in different drive-in operations. In this step, we used wafers that have 2–4μm texture, sheet resistance of 30, 40, 50, and 60Ohm/sq and 80μm as width of finger with 2.2mm spacing of the metallization. The peak temperature was 759.5°C, the

In the fourth set of experiment, we investigated firing conditions that determines sheet re‐ sistance, by varying belt speed, and temperature. We found a co-firing process window that resulted in a fill factor greater than 77%. For the metallization of the front side, we used Fer‐

and the solar cell will suffer from low conversion efficiency.

surface condition during edge isolation is prevented.

120 Photodiodes - From Fundamentals to Applications

four thermal zones and measured the Suns-Voc.

melting duration was 4.5s, and the belt speed was 170 IPM.

ro 33-501 Ag paste with a peak temperature 700°C and a firing time <1–3s.

ger with 2.4mm spacing metallization.

*3.5.1. Effect of Co-firing Temperature on Solar Cell Performance*

**3.5. Metallization**

To investigate the effects of different drive-in operations, we examine the variation in Voc and the Jsc according to the sheet resistance changes. As different drive-in operations for dopant diffusion can lead to changes in sheet resistance. In this step, we used wafers of 24 μm texture, sheet resistance of 30, 40, 50, or 60Ω/sq. and 80 μm width of finger with 2.2 mm spacing shows the Voc as 621, 622, 623, 627mV and Jsc as 34.6, 34.9, 35.0, 35.3mA/cm2 respec‐ tively. The peak temperature was 759.5°C, the melting duration was 4.5s, and the belt speed was 170 IPM.

As the emitter layer becomes thinner the sheet resistance increases, it becomes difficult to fire the electrode to a moderate depths (i.e., near the pn junction). So the higher sheet resist‐ ance means thinner emitter and it is more likely to lead to a short circuit of electrodes that penetrate through the emitter. With low sheet resistance (i.e., a heavy doping) by the overfired sites such a situation is less likely. Fig. 6 shows a safe operating zone for the range of belt speed (Fig. 6(a)) and firing temperature (Fig. 6(b)), it gets narrower as the sheet resist‐ ance increases. While the duration of firing was investigated, we found that the shorter the firing time, the more was the minority carriers lifetime. Thus shorter firing time results in increased number of minority carriers and as a result increased Voc. It is known that mobility is dependent on the effective minority carrier lifetime. We also investigated the relationship between the number of fingers and the series resistance, fill factor, and shading loss in a sin‐ gle-crystal, 5inch (125mm×125mm, 154.83cm2 ) Czochralski-type solar cell. We used two dif‐ ferent finger spacings 1.8mm and 2.4mm.

**Figure 7.** The relation between the sheet resistance with finger spacing for the available range of more than 77% of

Fabrication of Crystalline Silicon Solar Cell with Emitter Diffusion, SiNx Surface Passivation and Screen Printing of

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**Cell Condition Carrier Lifetime (μs) Cell Condition Carrier Lifetime (μs) SiNx ARC PECVD ONO** As-deposited 100 As-deposited 110 FGA 125 FGA 70 Co-firing 180 Co-firing 165 **Si rich SiNx SiON/Si-rich SiNx**

As-deposited 205 As-deposited 120 FGA 320 FGA 225 Co-firing 11 Co-firing 20

**Table 5.** Temperature dependence of different passivating films. FGA – forming gas annealing, ONO – silicon -oxide -

For the fabrication of local back contact structure with little modification on conventional cell process, adaptation of rear passivating film on c-Si solar cell should address two issues

In order to carry out a comparative investigation about the effectiveness of Al-BSF and die‐ lectric passivation on rear surface, solar cells were fabricated with and without dielectric passivation in conjunction with screen printed Al grid pattern with different rear metal cov‐ ered area. Comparative analysis show that the role of the rear surface passivation with SiNx film becomes dominant when the metal coverage area is below 45% of total surface area. But, as the metal coverage area goes above 45%, the quality of passivation degrades first

the fill factor.

nitride -oxide.

which are

*3.5.2. Study of rear surface passivation with SiNx film*

**1.** temperature dependence as shown in Table 5,

**2.** grid pattern on rear metallization.

**Figure 6.** Firing process window from the firing conditions according to the variations of the sheet resistances, the (a) belt speeds and (b) the firing temperatures. Hatched area indicates the range (min.–max.) that has larger than 77% of the fill factor by the combination of variations of the sheet resistances (drive-in operations), the belt speeds and the firing temperatures.

The screen printed and metalized front side shading loss is relatively large, in the range of 8–10% [47]. A grid model suggested in [44] can be used to optimize the grid line design, con‐ sidering resistance and shading loss. The finger width was as usual 80 μm in the case of the fired Ferro 33-501 Ag paste grid lines. Consequently, the number of grid lines compared to the original grid line design increased by 17. With the new grid line design, the finger spac‐ ing decreased from 2.4 to 1.8 mm. This led to a decrease in the total series resistance and an improvement in the fill factor. The design of the metal grid line was essentially a matter of finding the separation between the fingers that resulted in the best compromise between shading losses and resistive ones [48]. The contribution to the series resistance from the dif‐ fused sheet was 0.192Ω.cm<sup>2</sup> for 2.4mm spacing and 0.108Ω.cm<sup>2</sup> for 1.8mm spacing, so that emitter resistance (Re) improved by 0.084Ω.cm<sup>2</sup> . Each 1Ω.cm<sup>2</sup> in series resistance caused a decrease of about 0.041 in the fill factor (assuming a moderately high shunt resistance) [48], the total calculated improvement in fill factor due to the increase in emitter sheet resistance was 0.0078Ω. We also investigated the relation between the variations of Rsheet and spacing for the available range of more than 77% of the fill factor. As shown in Fig. 7, the narrower the spacing, the wider range of Rsheet can give a better solar cell. By shortening the spacing between the grid lines, the series resistance decreased and the FF increased, but the addition of extra fingers caused a 1% increase in shading loss as well as lowering the short circuit cur‐ rent. As a result of these drops, cell efficiency reduced from 17.18% to 16.92%.

Fabrication of Crystalline Silicon Solar Cell with Emitter Diffusion, SiNx Surface Passivation and Screen Printing of Electrode http://dx.doi.org/10.5772/51065 123

**Figure 7.** The relation between the sheet resistance with finger spacing for the available range of more than 77% of the fill factor.

*3.5.2. Study of rear surface passivation with SiNx film*

fired sites such a situation is less likely. Fig. 6 shows a safe operating zone for the range of belt speed (Fig. 6(a)) and firing temperature (Fig. 6(b)), it gets narrower as the sheet resist‐ ance increases. While the duration of firing was investigated, we found that the shorter the firing time, the more was the minority carriers lifetime. Thus shorter firing time results in increased number of minority carriers and as a result increased Voc. It is known that mobility is dependent on the effective minority carrier lifetime. We also investigated the relationship between the number of fingers and the series resistance, fill factor, and shading loss in a sin‐

**Figure 6.** Firing process window from the firing conditions according to the variations of the sheet resistances, the (a) belt speeds and (b) the firing temperatures. Hatched area indicates the range (min.–max.) that has larger than 77% of the fill factor by the combination of variations of the sheet resistances (drive-in operations), the belt speeds and the

The screen printed and metalized front side shading loss is relatively large, in the range of 8–10% [47]. A grid model suggested in [44] can be used to optimize the grid line design, con‐ sidering resistance and shading loss. The finger width was as usual 80 μm in the case of the fired Ferro 33-501 Ag paste grid lines. Consequently, the number of grid lines compared to the original grid line design increased by 17. With the new grid line design, the finger spac‐ ing decreased from 2.4 to 1.8 mm. This led to a decrease in the total series resistance and an improvement in the fill factor. The design of the metal grid line was essentially a matter of finding the separation between the fingers that resulted in the best compromise between shading losses and resistive ones [48]. The contribution to the series resistance from the dif‐

decrease of about 0.041 in the fill factor (assuming a moderately high shunt resistance) [48], the total calculated improvement in fill factor due to the increase in emitter sheet resistance was 0.0078Ω. We also investigated the relation between the variations of Rsheet and spacing for the available range of more than 77% of the fill factor. As shown in Fig. 7, the narrower the spacing, the wider range of Rsheet can give a better solar cell. By shortening the spacing between the grid lines, the series resistance decreased and the FF increased, but the addition of extra fingers caused a 1% increase in shading loss as well as lowering the short circuit cur‐

rent. As a result of these drops, cell efficiency reduced from 17.18% to 16.92%.

for 2.4mm spacing and 0.108Ω.cm<sup>2</sup> for 1.8mm spacing, so that

in series resistance caused a

. Each 1Ω.cm<sup>2</sup>

) Czochralski-type solar cell. We used two dif‐

gle-crystal, 5inch (125mm×125mm, 154.83cm2

ferent finger spacings 1.8mm and 2.4mm.

122 Photodiodes - From Fundamentals to Applications

firing temperatures.

fused sheet was 0.192Ω.cm<sup>2</sup>

emitter resistance (Re) improved by 0.084Ω.cm<sup>2</sup>


**Table 5.** Temperature dependence of different passivating films. FGA – forming gas annealing, ONO – silicon -oxide nitride -oxide.

For the fabrication of local back contact structure with little modification on conventional cell process, adaptation of rear passivating film on c-Si solar cell should address two issues which are


In order to carry out a comparative investigation about the effectiveness of Al-BSF and die‐ lectric passivation on rear surface, solar cells were fabricated with and without dielectric passivation in conjunction with screen printed Al grid pattern with different rear metal cov‐ ered area. Comparative analysis show that the role of the rear surface passivation with SiNx film becomes dominant when the metal coverage area is below 45% of total surface area. But, as the metal coverage area goes above 45%, the quality of passivation degrades first then starts improving due to the dominating effect of Al BSF over the passivation with SiNx. As the metal coverage area on the rear surface reaches as high as 85%, an improvement in infrared response with net improvement in Isc by ~ 0.16 A has been observed. This indicates that there is dominance of Al-BSF passivation in comparison to the dielectric passivation on the cells fabricated with screen printed local back contact, especially when the rear metal coverage reaches 45% or more but when the metal coverage comes below 45%, the effect of the dielectric passivation becomes dominant.

When the cells were co-fired keeping peak temperature below 875°C, the problem of Al bead formation was found to have reduced but the cells were found to have under-fired due to which the series resistance of the cells increased appreciably. The comparison of LIV char‐ acteristics of the cells with local back contact through the opening in SiNx film, fabricated by varying the peak co-firing temperature is shown in Fig. 8 and the comparative analysis of the performance parameters of the cells is shown in Table 6. The co-firing profile with peak temperature of 875°C was found to be the best for SiNx passivation layer in terms of per‐ formance parameters despite the formation of the Al beads on the rear surface when the cell

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The minimum Rs of 8 mΩ and maximum FF of 75% among the cells compared are the evi‐ dences of the improved front metal contact without over-heating of Ag finger lines in the case of the cell co-fired with a peak temperature 875°C. The bead formation could be mini‐ mized with the increased belt speed keeping peak temperature fixed at 875°C but that test could not be carried out in our system because of the limitation to increase the belt speed

**4. Summary and Future Direction for Thin Silicon Wafer Processing**

**Figure 9.** Process sequence of wafer cleaning, saw damage removal and surface texturing of c-Si wafer.

Wafer cleaning for saw damage removal is a fundamental step for c-Si solar cell fabrication. Texturing the top surface of the wafer reduces reflection loss of incident light, as well as in‐ creased effective surface area of the wafer for light trapping, light absorption, carrier collec‐ tion inside the wafer. Surface passivation with silicon nitride layer increases carrier lifetime and further reduces reflectivity of the top surface as it also works as an anti-reflection coat‐

was co-fired at this temperature.

beyond 180 IPM.

**4.1. Summary**

All the results suggest that the passivation with dielectric film on the rear surface is a must for local back contact formation by screen printing of Al paste whereas the role of such die‐ lectric passivation becomes significant for Al printed local back contact only if the metal cov‐ ered area on the rear surface goes below 45%. These results indicate a suitable rear metal covered area for high efficiency thin c-Si solar cells with local back contact in conjunction with dielectric passivation with dielectric film of SiNx and were found to be in accordance with the results obtained by simulation in ref [28].

**Figure 8.** Comparison of the illuminated current-voltage (LIV) characteristics of the cells fabricated with local back contact through the opening in SiNx film on rear surface by varying the peak temperature of the co-firing profile, as indicated with the traces.


**Table 6.** Comparison of the performance parameters of the cells fabricated with local back contact through the opening window on SiNx film on rear surface by varying the peak temperature of the co-firing profile, where Tp is peak firing temperature.

When the cells were co-fired keeping peak temperature below 875°C, the problem of Al bead formation was found to have reduced but the cells were found to have under-fired due to which the series resistance of the cells increased appreciably. The comparison of LIV char‐ acteristics of the cells with local back contact through the opening in SiNx film, fabricated by varying the peak co-firing temperature is shown in Fig. 8 and the comparative analysis of the performance parameters of the cells is shown in Table 6. The co-firing profile with peak temperature of 875°C was found to be the best for SiNx passivation layer in terms of per‐ formance parameters despite the formation of the Al beads on the rear surface when the cell was co-fired at this temperature.

The minimum Rs of 8 mΩ and maximum FF of 75% among the cells compared are the evi‐ dences of the improved front metal contact without over-heating of Ag finger lines in the case of the cell co-fired with a peak temperature 875°C. The bead formation could be mini‐ mized with the increased belt speed keeping peak temperature fixed at 875°C but that test could not be carried out in our system because of the limitation to increase the belt speed beyond 180 IPM.
