**4. Single-stage Transimpedance Amplifier Modeling**

In this section we will focus on the design of a high-speed transimpedance receiver. The term "high-speed" is in fact here related to technology and means that we have to design at a ratio (*ftmax*/*fttrans*)) close to ten or less. In a 0.13*μm* SOI CMOS technology as used here, it corre‐ sponds to 10GBps application. As just discussed in the section 3.1, for this kind of applica‐ tions, the optimal number of stages is 1. This is simply due to the fact that there is no room to place extra poles in the feedback loop to achieve stability. In fig. 4b, we can also see that the ( *gm Id* )1max that we will choose to maximize the gain is low. Combined with the small lengths of the transistors, this will lead to very low achievable voltage gains. If we optimize the design for low voltage gain and high bandwidth, the value of the feedback resistor, *Rf* , will be low and comparable with the value of the output impedance of the amplifier. In this case the voltage gain will become dependent on *Rf* . A typical solution to this problem is to use an output buffer. In our case, however, this has to be rejected as it would add an extra pole in the feedback loop. We thus have to accordingly adapt our design scheme to take into account the voltage gain dependency on *Rf* . In the text, we will call this new case of figure the degenerated case compared to the previous one that we will refer as the non-degenerat‐ ed case.

#### **4.1 Design Methodology of single-stage Transimpedance Amplifier**

We then performed transient simulation of the transimpedance circuit (fig. 10b) for both *Rf* values. The variation of the output voltage, *vout* to the 1ns width photocurrent pulses con‐ firms that in a simulation point of view, both circuits (identical amplifier, but different *Rf*

=332.8k Ω has steeper response (as its bandwidth is higher) but higher overshooting that requires a longer time to vanish (as its phase margin is lower). The multistage amplifier voltage gain *ANs* that fixes the TIA bandwidth and phase margin, hence its stability, depends

*<sup>N</sup>* . This Early voltage is difficult to model carefully, especially in deep sub-micron

and by tuning its gate voltage.

process, as it can quite vary statistically with fabrication process and short channel effects. It is therefore a critical issue in the design of multistage amplifier TIA. In order to handle it, a sufficient phase margin has to be taken into account. In our case, the phase margin seems sufficient despite the increase of *Vea* by about a factor 2. The possibility to tune the feedback resistor in the design is another very interesting and efficient solution. This can be achieved

Noise simulations were also performed with Eldo. Eldo spectral power density of output noise voltage are close to Matlab results (fig. 10c). Below 200kHz, both Matlab and Eldo total power densities are identical and are dominated by the feedback resistance contribution. Above, the high frequency peak values are related to the low voltage amplifier power densi‐ ties multiplied by the voltage gain of the amplifier. The higher peak in Eldo is then ex‐ plained by the higher voltage gain compared to Matlab. The equivalent RMS value of the

To summarize, in our multistage top-down design methodology, we first determine the op‐ timal number of stages (which is greater than 1 when the TIA bandwidth is not too close to

*Id* )2 results from a trade-off between dynamic range and other performances, while W1

In this section we will focus on the design of a high-speed transimpedance receiver. The term "high-speed" is in fact here related to technology and means that we have to design at a ratio (*ftmax*/*fttrans*)) close to ten or less. In a 0.13*μm* SOI CMOS technology as used here, it corre‐

27.5nA predicted with Matlab due to the peak. For the Eldo simulations with *Rf*

shown to be limited by stability considerations and to impose a value on ( *gm*

is chosen to compromise power consumption vs. noise and sensitivity.

**4. Single-stage Transimpedance Amplifier Modeling**

=700k Ω, that

=700k Ω, this

. The choice

=332.8k Ω. This is a little higher than the

of a given technology) to optimize the voltage gain of the

and the transimpedance gain. This maximum voltage gain was

, the input noise and sensitivity

*Id* )1

values) are suitable for 1 GBps applications. Compared to the circuit with *Rf*

with *Rf*

on *Vea*

by using a transistor to implement *Rf*

352 Photodiodes - From Fundamentals to Applications

input integrated noise given by Eldo is 41.5nA for *Rf*

performance of the receiver are improved.

**3.8 Design methodology Summary**

the transistors frequency limit *ft*

amplifier and hence *Rf*

of ( *gm*

noise reduces to 19.1nA. As can be expected, by increasing *Rf*

The schematic view of the single stage transimpedance is presented in fig. 11a. As previously, to simplify the analysis of this shunt-shunt feedback circuit, we can rewrite its small signal schematic in its canonical form [25] (fig. 11b). The amplifier is presented as a controlled cur‐ rent source with an output impedance to take account of *Rf* in the expression of the voltage gain Ao (fig. 11b). The input capacitance, *Cin*, consists of the amplifier input capacitance, *Cg1*, and the photodiode capacitance, *Cph*. The transimpedance gain in closed loop, *Zcl* is then:

$$Z\_{el} = \frac{-R\_f}{\left(1 + R\_f \, \mathrm{C}\_{in} \mathrm{s}\right) \left(1 + \frac{\mathrm{C}\_{out} \mathrm{s}}{\mathrm{g}\_{out} + \mathrm{g} f}\right)}\tag{57}$$

As previously, assuming that the dominant pole is that of the input, the bandwidth of the transimpedance is given by:

$$BW\_{trans} = 2\pi. \, f \, t\_{trans} = \frac{Ao}{R\_f \, \overline{C}\_{in}} \tag{58}$$

Dynamic range (eq. 54) and power consumption expressions (eq. 55) are not changed com‐ pared to the non-degenerated case, while voltage gain Ao and non dominant output pole, which is also the bandwidth of the amplifier, *BW1s* now depend on *Rf* or its inverse *gf* :

$$Ao = \frac{\mathcal{g}\,m\_1}{\mathcal{g}\_{out} + \mathcal{g}f} \mathcal{B}\mathcal{W}\_{1s} = 2\pi. \,f \,t\_{1s} = \frac{\mathcal{g}\_{out} + \mathcal{g}f}{\mathcal{C}\_{out}}\tag{59}$$

By making these substitutions, however, noise analysis stays essentially the same. The total output noise power spectral density of the transimpedance (eq. 34), is now given by:

$$\left| S\boldsymbol{\upsilon}\_{\rm out}^{2}(f) \right| \simeq \frac{S\boldsymbol{\upsilon}\_{\rm R\_{f}}^{2} + |\:\mathtt{1} = \mathtt{s}.\mathtt{R}\_{f}.\mathtt{C}\_{\rm inT}|^{2}.\operatorname{Scy}\_{\rm Aump}^{2}}{|\:\mathtt{1} + \mathtt{s}.\mathtt{C}\_{\rm A}\boldsymbol{\mathit{C}}\_{\rm inT}|^{2}.\left| \:\mathtt{1} + \mathtt{s}.\mathtt{R}\_{\rm outA}.\mathtt{C}\_{\rm outT} \right|^{2N}}\tag{60}$$

as the gain depends on *Rf*

where *gf*

the *Rf*

We can write:

related to ( *gm*

*Id* )1

increasing function of ( *gm*

ievable against ( *gm*

*Id* )1

*Aospec* =

*W* 1=

( *gm Id* )1

*Id* )1

1

(see fig. 11c):

*i d n*<sup>1</sup> *W*<sup>1</sup> *VeaL eqL* <sup>1</sup>

*Cin* product to satisfy the temporal specification:

, we cannot directly specify a value of ( *gm*

Design of Multi Gb/s Monolithically Integrated Photodiodes and Multi-Stage Transimpedance Amplifiers in Thin-Film

(28) for the non-degenerated case. Moreover, nothing now guarantees that this maximum

+ *gf*

cation on the bandwidth. From these considerations we can derive the maximum gain ach‐

is unknown and linked to the gain by eq. (58). As we will now see, for a fixed gain

. Indeed, fixing Ao equal to *Aospec*, we find by eq. (58) a condition on

gain is achievable. Indeed, the gain given by eq. (59) can be rewritten:

*Ao* =

( *gm Id* )1<sup>⋅</sup> *I d*<sup>1</sup>

*I d*<sup>1</sup> *VeaL eq*

*Aospec*, one can derive the input transistor width, W1, from its length, *L1*, its *gm*

*Rf Cin* <sup>=</sup> *Aospec*

By injecting this equation in the expression of the gain eq. (63), we find:

+

( *gm Id* )1 · *<sup>i</sup> d n*<sup>1</sup> . *W* 1 *L* 1

*BWtrans*

*Cph* .*BWT*

where *Cg1o* is equal to the input capacitor of the amplifier, *Cg1*, divided by W1 and L1 and is

this expression stay strictly positive. This gives the maximum achievable gain, which is an

. In order to keep W1 positive and finite, we need that the denominator of

*<sup>L</sup>* <sup>1</sup> <sup>−</sup>*Cg*1*<sup>o</sup>BWT* .*<sup>L</sup>* <sup>1</sup><sup>−</sup> *Aospec*

*BWtrans*(*Cph* + *Cg*1*o*.*W* 1.*L* 1) *Aospec*

> 1 *L* 1.*Vea*;

*L eq*

*Id* )1

(63) (63)

(64) (64)

(65) (65)

(66)

as it was done in eq.

http://dx.doi.org/ 10.5772/50531

SOI CMOS Technology

355

*id* and specifi‐

where *SvRf* 2 and *SvgAmp* <sup>2</sup> are still given by eq. (30) and eq. (33). The RMS value of the noise is still obtained by integration of *Svg*out <sup>2</sup> (eq. 38). Again the integral can be approximated by the sum of three fragments (see eq. 41, 42, 47 and eq. 48) from which, only the expression of the amplifier high frequency noise has to be modified accordingly. Eq. (47) now becomes:

$$
\omega \,\,\omega^2 \simeq A o^2. \, S \nu \, g^2. \Big(\frac{\pi}{2} \, f \, t\_{1s} - f \, t\_{trans}\Big) \tag{61}
$$

**Figure 11.** a) Photodiode and its transimpedance. b) Small signal diagram of the photodiode and the transimpe‐ dance. Above, with noise sources . Below, equivalent diagram in its canonical feedback form. c) *Aomaxstab*, *Aomaxgain* et *Aospec* in function of ( *gm Id* )1 for *fttrans*=0.5GHz and k=0.75, 0.5μm FD-SOI technology.

Even though the gain and the non-dominant pole now both depend on the value of *Rf* , the dependence of one compensating the other, the condition of stability can be rewritten as a condition on a maximum gain *Aomaxstab* exactly as in the non-degenerated case:

$$Ao \le \frac{ft}{\{X\_c + X\_{c2}\} . X\_A . f \, t\_{trans}} = Ao\_{\max\_{sab}} \tag{62}$$

Again, we see that, for a given bandwidth and a given phase margin, i.e. for a given *XA*, the maximal achievable amplifier gain dictated by stability conditions is imposed by technology and inversion degree but is independent of *Rf* . It is this gain, which is maximum near strong inversion (*ft* is decreasing, *XC* is increasing and *XC2* is decreasing with ( *gm Id* )1 ) (figure 11c), that we would like to choose in order to optimize the performances of the circuit. However, as the gain depends on *Rf* , we cannot directly specify a value of ( *gm Id* )1 as it was done in eq. (28) for the non-degenerated case. Moreover, nothing now guarantees that this maximum gain is achievable. Indeed, the gain given by eq. (59) can be rewritten:

$$Ao = \frac{\left(\frac{\mathcal{g}m}{Id}\right)1 \cdot Id\_1}{\frac{Id\_1}{V\_{ea}L\_{eq}} + \mathcal{g}f} \\ \text{(63)}$$

where *gf* is unknown and linked to the gain by eq. (58). As we will now see, for a fixed gain *Aospec*, one can derive the input transistor width, W1, from its length, *L1*, its *gm id* and specifi‐ cation on the bandwidth. From these considerations we can derive the maximum gain ach‐ ievable against ( *gm Id* )1 . Indeed, fixing Ao equal to *Aospec*, we find by eq. (58) a condition on the *Rf Cin* product to satisfy the temporal specification:

$$R\_f \ C\_{in} = \frac{A o\_{spec}}{B W\_{trans}} \text{(64)}\tag{64}$$

By injecting this equation in the expression of the gain eq. (63), we find:

$$Ao\_{spec} = \frac{\left(\frac{\mathcal{g}m}{Id}\right) \mathbf{1} \cdot i\_{dn\_i} \frac{\mathcal{W}1}{L}}{\frac{i\_{dn\_i}\mathcal{W}\_1}{\mathcal{V}\_{en}L} \mathbf{1}\_1 + \frac{\mathcal{B}W\_{trans}\{\mathcal{C}\_{pl} + \mathcal{C}\_{\mathcal{G}1o}, \mathcal{W}1.L\ 1\}}{Ao\_{spec}}} \\ \tag{65}$$

We can write:

By making these substitutions, however, noise analysis stays essentially the same. The total

2 2 2

*s sR C*

sum of three fragments (see eq. 41, 42, 47 and eq. 48) from which, only the expression of the

**Figure 11.** a) Photodiode and its transimpedance. b) Small signal diagram of the photodiode and the transimpe‐ dance. Above, with noise sources . Below, equivalent diagram in its canonical feedback form. c) *Aomaxstab*, *Aomaxgain* et

for *fttrans*=0.5GHz and k=0.75, 0.5μm FD-SOI technology.

Even though the gain and the non-dominant pole now both depend on the value of *Rf*

condition on a maximum gain *Aomaxstab* exactly as in the non-degenerated case:

(*Xc* + *Xc*2).*XA*. *f ttrans*

*Ao* <sup>≤</sup> *ft*

dependence of one compensating the other, the condition of stability can be rewritten as a

Again, we see that, for a given bandwidth and a given phase margin, i.e. for a given *XA*, the maximal achievable amplifier gain dictated by stability conditions is imposed by technology

that we would like to choose in order to optimize the performances of the circuit. However,

is decreasing, *XC* is increasing and *XC2* is decreasing with ( *gm*

amplifier high frequency noise has to be modified accordingly. Eq. (47) now becomes:

.*Sυg* <sup>2</sup> .( *π*

*υ* <sup>2</sup>≃ *Ao* <sup>2</sup>

*Rf f inT Amp*

2 2.

*outA outT*

<sup>2</sup> are still given by eq. (30) and eq. (33). The RMS value of the noise is

; (60)

<sup>2</sup> (eq. 38). Again the integral can be approximated by the

<sup>2</sup> *f t*1*<sup>s</sup>* <sup>−</sup> *f ttrans*) (61)

= *Ao*max *stab* (62)

. It is this gain, which is maximum near strong

*Id* )1

) (figure 11c),

, the

*f inT N*

output noise power spectral density of the transimpedance (eq. 34), is now given by:


*Ns*

+ +

*Sv s R C Svg Sv f R C*

+ =

*A*

2

2 and *SvgAmp*

354 Photodiodes - From Fundamentals to Applications

still obtained by integration of *Svg*out

where *SvRf*

*Aospec* in function of ( *gm*

inversion (*ft*

*Id* )1

and inversion degree but is independent of *Rf*

*out*

$$BW1 = \frac{\mathbb{C}\_{ph}\,BW\_T}{\left(\frac{gm}{Id}\right)1\,\frac{1}{L}\,\frac{1}{1} - \mathbb{C}\_{\gtrless}\,BW\_T.L\ 1 - Ao\_{\text{spec}}\frac{1}{L\ 1.V\_{\text{ex}}L\_{\text{eq}}}} \tag{66}$$

where *Cg1o* is equal to the input capacitor of the amplifier, *Cg1*, divided by W1 and L1 and is related to ( *gm Id* )1 . In order to keep W1 positive and finite, we need that the denominator of this expression stay strictly positive. This gives the maximum achievable gain, which is an increasing function of ( *gm Id* )1 (see fig. 11c):

$$A o\_{\text{max}\_{\text{gas}}} = V\_{\text{av}} L\_{\text{eq}} \text{I} \{ \frac{\text{gm}}{Id} \text{I} - B V\_{\text{T}} \text{C} L\_{\text{g1o}}, L \text{1}^2 \} \tag{67}$$

tonic one as *ft*

The curve presents then a flat maximum between ( *gm*

and, then, a minimum in sensitivity in the range of ( *gm*

*Id* )2

*Id* )1

*fttrans*=10GHz, ( *gm*

for *fttrans*=10GHz, ( *gm*

around ( *gm*

*Id* )2

*Id* )1

the fact that *Cph* is increased (and then also *Cin*) by a decrease in *Li* in order to maintain the

*Id* )1

up to these values as both *idn1* and W1 decrease. When further increasing ( *gm*

creasing but more slowly, as *idn1* still decreases but W1 now increases. The input noise also presents a minimum value of around 1.5μA that is mainly related to the maximum value of *Rf*

minimum in W1 and a maximum in *Rf*

**Figure 12.** Performance of TIA vs. ( *gm*

**Figure 13.** Performance of TIA vs. ( *gm*

Note that the small decrease in *Rf*

CMOS technology, Vdd=1.2V.

technology, Vdd=1.2V.

and *XC2* (as the ratio of W2/W1) mainly decrease, while *XC* decreases with ( *gm*

Design of Multi Gb/s Monolithically Integrated Photodiodes and Multi-Stage Transimpedance Amplifiers in Thin-Film

*Id* )1

*Id* )1

*Id* )1 . 357

*Id* )1

, Id1 keeps de‐

SOI CMOS Technology

http://dx.doi.org/ 10.5772/50531

=4.5 to 6.5 *V-1*, which corresponds to a

*Id* )1

= 5 V-1, k=0.75, *XA*=3, *Ad*=2500μm2, 0.13μm PD-SOI CMOS

= 2 *V-1*, kc=0.75, *XA*=3, *Ad*=2500μm2, 0.13 μm PD-SOI

=4.5 V-1, while *Aospec* still increases is due to

(eq. 58). The current Id1 strongly decreases with ( *gm*

of 4 to 5 V-1.

Finally, we choose to satisfy the constraints and to optimize the performances of the circuit:

$$Ao\_{sync} = \min(kc.Ao\_{max\_{gain}}Ao\_{max\_{stat}})\tag{68}$$

where kc is a proportionality factor strictly smaller than 1 according to eq. (67). fig. 11c shows the evolution of the gain in function of the ( *gm Id* )1 for kc=0.75. The maximum reacha‐ ble gain will then be close to the intersection of the two gain characteristics.

#### **4.2 Design of a 10GHz single stage TIA in a 0.13***μm* **PD-SOI CMOS technology**

We now apply the design methodology presented in subsection 4.1 to the design of a 10GHz, single stage SVTA transimpedance amplifier in a typical 0.13*μm* PD-SOI CMOS technology. The model has been implemented using Matlab. Again we used a typical photo‐ diode with a total length and width of 50μm. We first have to choose a value for ( *gm Id* )2 based on Matlab results of fig. 12. As explained above, by increasing ( *gm Id* )2 , the ratio of *W*<sup>2</sup> *W*<sup>1</sup> increases as well as the ratio of the drain capacitance of M2 to the gate to source capacitance of M1, *XC2* , compared to *XC* (the *Cd*1 *Cgs*<sup>1</sup> ratio) for a given ( *gm Id* )1 . Then the maximum value of *Aomaxstab* that we can choose to ensure stability also decreases. As a result, *Aospec* decreases. As we are working at the technology frequency limit, the stability limitations prevail over the feasibility (which is by the way independent on ( *gm Id* )2 ). This reduction of *Aospec* induces a reduction of W1 (see eq. 66) and then of Id1 and *Cin*. The reduction of *Cin* is however not suf‐ ficient to compensate the decrease of the value of *Rf* due to the reduction of *Aospec* (eq. 64). Noise and then sensitivity performances are also degraded when increasing ( *gm Id* )2 . The noise in the mirror then increases (see eq. 33). However, in order to have acceptable dynam‐ ic range, a ( *gm Id* )2 larger than 2 V-1 is required. Increasing ( *gm Id* )2 is also beneficial for power consumption. Finally a ( *gm Id* )2 of 2.5 V-1 seems to be a good trade-off in between all these considerations for a ( *gm Id* )1 of 5 V-1.

However, we also have to determine the value of ( *gm Id* )1 . This can be done using model results of fig. 13. Again, the maximum gain is mainly dominated by *Aomaxstab*. The curve is a non-mono‐ Design of Multi Gb/s Monolithically Integrated Photodiodes and Multi-Stage Transimpedance Amplifiers in Thin-Film SOI CMOS Technology http://dx.doi.org/ 10.5772/50531 357

tonic one as *ft* and *XC2* (as the ratio of W2/W1) mainly decrease, while *XC* decreases with ( *gm Id* )1 . The curve presents then a flat maximum between ( *gm Id* )1 =4.5 to 6.5 *V-1*, which corresponds to a minimum in W1 and a maximum in *Rf* (eq. 58). The current Id1 strongly decreases with ( *gm Id* )1 up to these values as both *idn1* and W1 decrease. When further increasing ( *gm Id* )1 , Id1 keeps de‐ creasing but more slowly, as *idn1* still decreases but W1 now increases. The input noise also presents a minimum value of around 1.5μA that is mainly related to the maximum value of *Rf* and, then, a minimum in sensitivity in the range of ( *gm Id* )1 of 4 to 5 V-1.

2

*Id* <sup>=</sup> - (67)

) *gain stab Ao kc Ao Ao spec* = (68)

for kc=0.75. The maximum reacha‐

*Id* )2 , the ratio of

*Id* )2

is also beneficial for power

. The

. Then the maximum value of

). This reduction of *Aospec* induces a

due to the reduction of *Aospec* (eq. 64).

. This can be done using model results

*Id* )2

*W*<sup>2</sup> *W*<sup>1</sup>

*Id* )1

max <sup>1</sup> . [( )1 . . 1 ] *gain ea eq T go gm Ao V L BW CL L*

Finally, we choose to satisfy the constraints and to optimize the performances of the circuit:

min( . max max '

where kc is a proportionality factor strictly smaller than 1 according to eq. (67). fig. 11c

We now apply the design methodology presented in subsection 4.1 to the design of a 10GHz, single stage SVTA transimpedance amplifier in a typical 0.13*μm* PD-SOI CMOS technology. The model has been implemented using Matlab. Again we used a typical photo‐ diode with a total length and width of 50μm. We first have to choose a value for ( *gm*

increases as well as the ratio of the drain capacitance of M2 to the gate to source capacitance

*Aomaxstab* that we can choose to ensure stability also decreases. As a result, *Aospec* decreases. As we are working at the technology frequency limit, the stability limitations prevail over the

reduction of W1 (see eq. 66) and then of Id1 and *Cin*. The reduction of *Cin* is however not suf‐

noise in the mirror then increases (see eq. 33). However, in order to have acceptable dynam‐

of fig. 13. Again, the maximum gain is mainly dominated by *Aomaxstab*. The curve is a non-mono‐

Noise and then sensitivity performances are also degraded when increasing ( *gm*

larger than 2 V-1 is required. Increasing ( *gm*

ratio) for a given ( *gm*

*Id* )2

*Id* )1

*Id* )1

*Id* )2

of 2.5 V-1 seems to be a good trade-off in between all these

ble gain will then be close to the intersection of the two gain characteristics.

based on Matlab results of fig. 12. As explained above, by increasing ( *gm*

*Cd*1 *Cgs*<sup>1</sup>

**4.2 Design of a 10GHz single stage TIA in a 0.13***μm* **PD-SOI CMOS technology**

shows the evolution of the gain in function of the ( *gm*

356 Photodiodes - From Fundamentals to Applications

, compared to *XC* (the

feasibility (which is by the way independent on ( *gm*

ficient to compensate the decrease of the value of *Rf*

*Id* )2

of 5 V-1.

*Id* )1

However, we also have to determine the value of ( *gm*

of M1, *XC2*

ic range, a ( *gm*

*Id* )2

consumption. Finally a ( *gm*

considerations for a ( *gm*

**Figure 12.** Performance of TIA vs. ( *gm Id* )2 *fttrans*=10GHz, ( *gm Id* )1 = 5 V-1, k=0.75, *XA*=3, *Ad*=2500μm2, 0.13μm PD-SOI CMOS technology, Vdd=1.2V.

**Figure 13.** Performance of TIA vs. ( *gm Id* )1 for *fttrans*=10GHz, ( *gm Id* )2 = 2 *V-1*, kc=0.75, *XA*=3, *Ad*=2500μm2, 0.13 μm PD-SOI CMOS technology, Vdd=1.2V.

Note that the small decrease in *Rf* around ( *gm Id* )1 =4.5 V-1, while *Aospec* still increases is due to the fact that *Cph* is increased (and then also *Cin*) by a decrease in *Li* in order to maintain the transit time in the diode despite the reduction of *Vg1* due to the increase of ( *gm Id* )1 . The dy‐ namic range increases as *Vdssat1* decreases with ( *gm Id* )1 and calls for a high value of ( *gm Id* )1 . A ( *gm Id* )1 of 5 to 6 *V-1* seems a good trade off. Finally, in this range, results shows that it is better in terms of performances (*Rf* , noise, ...) to take a higher value of ( *gm Id* )1 in order to gain on dynamic range margin and then to be able to further decrease the value of ( *gm Id* )2 . We then take a ( *gm Id* )1 of 6 *V-1* and a ( *gm Id* )2 of 2 V-1. Modeled performances are summarized in table 2.

performed with Eldo. Eldo spectral power density of output noise voltage is in very good agreement with Matlab results (fig. 14c). Below a few GHz, the total power densities are do‐ minated by the feedback resistance contribution. Above, the high frequency peak values are related to the low voltage amplifier power densities multiplied by the voltage gain of the amplifier. The equivalent RMS value of the input noise integrated up to 1013 Hz given by

Design of Multi Gb/s Monolithically Integrated Photodiodes and Multi-Stage Transimpedance Amplifiers in Thin-Film

Eldo is 1.76μA which is in perfect agreement with the 1.75μA predicted with Matlab.

**perspectives**

the performances with ( *gm*

*Id* )1

stages instead of one owing to a better *ft*

and ( *gm*

*Id* )2

**4.3. Design of a 1GHz single stage TIA in a 0.5***μm* **SOI CMOS technology and scaling**

In order to compare technologies and draw some conclusions on scaling, we have applied the Matlab model to the design of a 1GHz single stage transimpedance in a fully depleted 0.5 *μm* SOI CMOS technology [30]. Again we are working at the technology frequency limit here such that the stability limitation prevails compared to the feasibility. The evolution of

previous design and will not be explained here again. As expected, the most suitable ( *gm*

is near that enabling the maximum gain. Modeled performances are summarized in table 2. When comparing 0.13 and 0.5 *μm* technologies for the design of 1GHz TIA (see table 1 and table 3), we first notice that the use of a more advanced technology has allowed to use 3

the transimpedance (transimpedance gain *Zcl* increased by more than 16 times, sensitivity improved by 7.5 times). The total transimpedance area should not increase since the use of more stages should be compensated by a reduction of the length of the transistors while the width is about the same. The power consumption is however increased in the 0.13*μm* tech‐

the higher number of stages while these are however partially compensated by the decrease of Vdd. The power consumption can even be reduced by 4 in the 0.13*μm* design by reducing

increase leading to a slightly reduced sensitivity of 1.56μW (see fig. 9) but still more than 5 times better than the sensitivity of the 0.5*μm* design. The use of 0.13*μm* technology also al‐ lows for an increase of the photodiode performance (smaller capacitance and higher photo‐

In a similar way, the uses of very advanced technology nodes with improved *fT*, such as the 22nm CMOS one with typical *fT* of about 400 to 500GHz (improved by about a factor 4 com‐ pared to that of a 0.13*μm* technology), could allow for improving the sensitivity of the re‐ ceiver at 10GHz by allowing for a multi-stage approach and a further reduction of *Cph*. Also a single stage 40Gb/s could be attempted. A SOI integrated PIN photodiode with an intrinsic length reduced to below 1*μm* could fulfill such requirements in terms of transit time cutoff frequency, but with an increased capacitance [1]. This, coupled with the reduced intrinic voltage gain of the single stage amplifier related to the reduced early voltage of ultra short transistor, might result in too low *Rf* and sensitivity values. To compensate a reduced photo‐

sensitive to total area ratio owing to the reduction of the size of the P+ and N+ areas).

nology by a factor of 4. The higher bias current is mainly due to a much higher *<sup>W</sup>*

W1 by 4 and then be equal to the 0.5*μm* design. In this case *Rf*

in their principles are very similar to those of the

. This allows for a real increase in performance of

*Id* )1

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*L* 1

but also the input noise will

ratio and


**Table 2.** Model results for 10GHz single stage TIA design in a 0.13μm SOI CMOS technology

**Figure 14.** a) Transimpedance gain in dBΩ vs. frequency. b) Transimpedance output voltage variation, *vout*, to 0.1ns width photocurrent pulses given by Eldo transient numerical simulations. The input photocurrent, *iph* multiplied by the TIA gain is also given as reference signal. c) TIA output noise spectral power density, *Svg*out 2 , *vs*. frequency given by our model implemented with Matlab and by Eldo numerical simulations. The noise contribution from *Rf* and from the am‐ plifier to the total spectral density are given for the Matlab results.

Numerical simulations of the designed circuit have then be carried out using Eldo and a BSIMSOI model fitted for the ST transistors. The simulated transimpedance gain is around 600 Ω, while the transimpedance bandwidth is 10 GHz (fig. 14a). We then performed transi‐ ent simulation of the transimpedance circuit (fig. 14b). The variation of the output voltage, *vout* related to the 0.1ns width photocurrent pulses confirms that in a simulation point of view, the designed circuit is suitable for 10 Gb/s applications. Noise simulations were also performed with Eldo. Eldo spectral power density of output noise voltage is in very good agreement with Matlab results (fig. 14c). Below a few GHz, the total power densities are do‐ minated by the feedback resistance contribution. Above, the high frequency peak values are related to the low voltage amplifier power densities multiplied by the voltage gain of the amplifier. The equivalent RMS value of the input noise integrated up to 1013 Hz given by Eldo is 1.76μA which is in perfect agreement with the 1.75μA predicted with Matlab.

transit time in the diode despite the reduction of *Vg1* due to the increase of ( *gm*

dynamic range margin and then to be able to further decrease the value of ( *gm*

of 5 to 6 *V-1* seems a good trade off. Finally, in this range, results shows that it is better

, noise, ...) to take a higher value of ( *gm*

namic range increases as *Vdssat1* decreases with ( *gm*

of 6 *V-1* and a ( *gm*

*Id* )2

**Table 2.** Model results for 10GHz single stage TIA design in a 0.13μm SOI CMOS technology

TIA gain is also given as reference signal. c) TIA output noise spectral power density, *Svg*out

plifier to the total spectral density are given for the Matlab results.

**Figure 14.** a) Transimpedance gain in dBΩ vs. frequency. b) Transimpedance output voltage variation, *vout*, to 0.1ns width photocurrent pulses given by Eldo transient numerical simulations. The input photocurrent, *iph* multiplied by the

model implemented with Matlab and by Eldo numerical simulations. The noise contribution from *Rf* and from the am‐

Numerical simulations of the designed circuit have then be carried out using Eldo and a BSIMSOI model fitted for the ST transistors. The simulated transimpedance gain is around 600 Ω, while the transimpedance bandwidth is 10 GHz (fig. 14a). We then performed transi‐ ent simulation of the transimpedance circuit (fig. 14b). The variation of the output voltage, *vout* related to the 0.1ns width photocurrent pulses confirms that in a simulation point of view, the designed circuit is suitable for 10 Gb/s applications. Noise simulations were also

in terms of performances (*Rf*

358 Photodiodes - From Fundamentals to Applications

( *gm Id* )1

take a ( *gm*

*Id* )1

*Id* )1

in order to gain on

*Id* )2

2 , *vs*. frequency given by our

*Id* )1 and calls for a high value of ( *gm*

*Id* )1

of 2 V-1. Modeled performances are summarized in table 2.

. The dy‐

*Id* )1 . A

. We then

#### **4.3. Design of a 1GHz single stage TIA in a 0.5***μm* **SOI CMOS technology and scaling perspectives**

In order to compare technologies and draw some conclusions on scaling, we have applied the Matlab model to the design of a 1GHz single stage transimpedance in a fully depleted 0.5 *μm* SOI CMOS technology [30]. Again we are working at the technology frequency limit here such that the stability limitation prevails compared to the feasibility. The evolution of

the performances with ( *gm Id* )1 and ( *gm Id* )2 in their principles are very similar to those of the

previous design and will not be explained here again. As expected, the most suitable ( *gm Id* )1

is near that enabling the maximum gain. Modeled performances are summarized in table 2. When comparing 0.13 and 0.5 *μm* technologies for the design of 1GHz TIA (see table 1 and table 3), we first notice that the use of a more advanced technology has allowed to use 3 stages instead of one owing to a better *ft* . This allows for a real increase in performance of the transimpedance (transimpedance gain *Zcl* increased by more than 16 times, sensitivity improved by 7.5 times). The total transimpedance area should not increase since the use of more stages should be compensated by a reduction of the length of the transistors while the width is about the same. The power consumption is however increased in the 0.13*μm* tech‐

nology by a factor of 4. The higher bias current is mainly due to a much higher *<sup>W</sup> L* 1 ratio and

the higher number of stages while these are however partially compensated by the decrease of Vdd. The power consumption can even be reduced by 4 in the 0.13*μm* design by reducing W1 by 4 and then be equal to the 0.5*μm* design. In this case *Rf* but also the input noise will increase leading to a slightly reduced sensitivity of 1.56μW (see fig. 9) but still more than 5 times better than the sensitivity of the 0.5*μm* design. The use of 0.13*μm* technology also al‐ lows for an increase of the photodiode performance (smaller capacitance and higher photo‐ sensitive to total area ratio owing to the reduction of the size of the P+ and N+ areas).

In a similar way, the uses of very advanced technology nodes with improved *fT*, such as the 22nm CMOS one with typical *fT* of about 400 to 500GHz (improved by about a factor 4 com‐ pared to that of a 0.13*μm* technology), could allow for improving the sensitivity of the re‐ ceiver at 10GHz by allowing for a multi-stage approach and a further reduction of *Cph*. Also a single stage 40Gb/s could be attempted. A SOI integrated PIN photodiode with an intrinsic length reduced to below 1*μm* could fulfill such requirements in terms of transit time cutoff frequency, but with an increased capacitance [1]. This, coupled with the reduced intrinic voltage gain of the single stage amplifier related to the reduced early voltage of ultra short transistor, might result in too low *Rf* and sensitivity values. To compensate a reduced photo‐ diode total surface but with no reduction of input power (i.e. relying on progress at the emitter side: better focused optical signal, higher power density emission at the source,...) might be necessary.

higher diode capacitance. The *gm*

*id* 's taken for the actual design are also a little bit more con‐

SOI CMOS Technology

361

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servative, leading to larger value of the widths of M1 and M2 and then to a larger amplifier input capacitance. The total input capacitance is then larger in the implemented design, *Rf*

Design of Multi Gb/s Monolithically Integrated Photodiodes and Multi-Stage Transimpedance Amplifiers in Thin-Film

and *Zcl* are decreased which in turn also reduces the noise performances of the TIA.

**Table 4.** Model results for the realized 10GHz single stage TIA design in a 0.13μ*m* SOI CMOS technology

**Figure 15.** Schematic of the fabricated TIA and its output buffer a) with the co-integrated PIN photodiode and b) with

A DC transimpedance gain of 212Ω was measured which is in very good agreement with the 214Ω gain predicted by the model. For the AC measurements, we used a modulated 1mW 830 nm laser. The remaining available optical power at the fiber output after modula‐ tion and fiber coupling losses was less than 0.01mW which is far below the sensitivity of our receiver and made these measurements impossible. One solution could be to use a femtosec‐ ond pulsed laser either at 850nm or 425nm by frequency doubling for example. Because we expected the problem of sensitivity with opto-electrical measurements, we had also de‐ signed a "photodiode emulator". The latter was a single transistor voltage amplifier with its output connected at the input of the transimpedance (fig. 15b). The output capacitance of this amplifier was designed to be very similar to that of the PIN diode while its output im‐ pedance was kept sufficiently larger than *Rf* in order to have an equivalent input TIA pole as close as possible to the real case. By varying the gate voltage of the input transistor of this

the photodiode emulator used for the S parameter measurements


**Table 3.** Model Results for 1GHz single stage TIA design in a 0.5μm SOI CMOS technology

#### **4.4 Design methodology Summary**

To summarize our single-stage top-down design methodology, we have shown that, as the voltage gain is now dependent on *Rf* , the maximum voltage gain is limited, on one hand, by stability considerations (which usually prevail in weak or moderate inversion regime), and on a second hand, by feasibility considerations (which usually prevail in strong inversion) and that this results on a constraint on W1. The choice of ( *gm Id* )2 results from a trade-off between dynamic range and power consumption vs. voltage gain, *Rf* , noise and then sensitivity per‐ formance. The choice of ( *gm Id* )1 results on a trade-off between dynamic range, which is maxi‐ mum towards the weak inversion, and the other performances, which are maximum near the maximum gain (resulting of the stability and feasibility curves) in moderate inversion.

## **5. TIA experimental characterization**

A single-stage 10GHz SVTA Amplifier was realized in the ST 0.13*μm* SOI CMOS technolo‐ gy. It is co-integrated with a PIN photodiode and a 50Ω output buffer for the RF measure‐ ments (fig. 15a). The latter has a 3mA bias current, a 0.79 voltage gain and a 1μA equivalent input noise. Modeled and simulated receiver bandwidths were 10GHz, both before and after insertion of the output buffer. TIA modeled performances are presented in table 4. These ex‐ pected performances are not as good as those reported in table 2. This is mainly because, in the actual design, we imposed a transit time frequency of the photodiode 1.5 times higher (i.e. 15 GHz) than the bandwidth of the TIA itself in order to make sure to measure the TIA cutoff frequency. This in turn imposed a smaller intrinsic length to the photodiode and a higher diode capacitance. The *gm id* 's taken for the actual design are also a little bit more con‐ servative, leading to larger value of the widths of M1 and M2 and then to a larger amplifier input capacitance. The total input capacitance is then larger in the implemented design, *Rf* and *Zcl* are decreased which in turn also reduces the noise performances of the TIA.

diode total surface but with no reduction of input power (i.e. relying on progress at the emitter side: better focused optical signal, higher power density emission at the source,...)

To summarize our single-stage top-down design methodology, we have shown that, as the

stability considerations (which usually prevail in weak or moderate inversion regime), and on a second hand, by feasibility considerations (which usually prevail in strong inversion) and

mum towards the weak inversion, and the other performances, which are maximum near the

A single-stage 10GHz SVTA Amplifier was realized in the ST 0.13*μm* SOI CMOS technolo‐ gy. It is co-integrated with a PIN photodiode and a 50Ω output buffer for the RF measure‐ ments (fig. 15a). The latter has a 3mA bias current, a 0.79 voltage gain and a 1μA equivalent input noise. Modeled and simulated receiver bandwidths were 10GHz, both before and after insertion of the output buffer. TIA modeled performances are presented in table 4. These ex‐ pected performances are not as good as those reported in table 2. This is mainly because, in the actual design, we imposed a transit time frequency of the photodiode 1.5 times higher (i.e. 15 GHz) than the bandwidth of the TIA itself in order to make sure to measure the TIA cutoff frequency. This in turn imposed a smaller intrinsic length to the photodiode and a

maximum gain (resulting of the stability and feasibility curves) in moderate inversion.

, the maximum voltage gain is limited, on one hand, by

results from a trade-off between

, noise and then sensitivity per‐

*Id* )2

results on a trade-off between dynamic range, which is maxi‐

**Table 3.** Model Results for 1GHz single stage TIA design in a 0.5μm SOI CMOS technology

that this results on a constraint on W1. The choice of ( *gm*

*Id* )1

**5. TIA experimental characterization**

dynamic range and power consumption vs. voltage gain, *Rf*

might be necessary.

360 Photodiodes - From Fundamentals to Applications

**4.4 Design methodology Summary**

voltage gain is now dependent on *Rf*

formance. The choice of ( *gm*


**Table 4.** Model results for the realized 10GHz single stage TIA design in a 0.13μ*m* SOI CMOS technology

**Figure 15.** Schematic of the fabricated TIA and its output buffer a) with the co-integrated PIN photodiode and b) with the photodiode emulator used for the S parameter measurements

A DC transimpedance gain of 212Ω was measured which is in very good agreement with the 214Ω gain predicted by the model. For the AC measurements, we used a modulated 1mW 830 nm laser. The remaining available optical power at the fiber output after modula‐ tion and fiber coupling losses was less than 0.01mW which is far below the sensitivity of our receiver and made these measurements impossible. One solution could be to use a femtosec‐ ond pulsed laser either at 850nm or 425nm by frequency doubling for example. Because we expected the problem of sensitivity with opto-electrical measurements, we had also de‐ signed a "photodiode emulator". The latter was a single transistor voltage amplifier with its output connected at the input of the transimpedance (fig. 15b). The output capacitance of this amplifier was designed to be very similar to that of the PIN diode while its output im‐ pedance was kept sufficiently larger than *Rf* in order to have an equivalent input TIA pole as close as possible to the real case. By varying the gate voltage of the input transistor of this diode emulator, an equivalent photocurrent is created at the TIA input. This allows for the electrical characterization of the TIA bandwidth. A photograph of the chip is shown in Fig 16a. S parameters measurements were done in the 40MHz-40GHz band. These measure‐ ments were obtained after a calibration to remove the impedance effect of the RF probes and cables used to connect the device to the spectrum analyzer.

feedback resistor *Rf*

pendent on *Rf*

validated by Eldo numerical simulations.

. We have shown that this happens when the bandwidth of the transi‐

and leads to multi-stages approach. Our systematic design procedure was then applied to the design of a 3-stages 1GHz bandwidth transimpedance amplifier in a 0.13 *μm* PD-SOI CMOS technology. It has allowed us to determine the optimal number of stages (3) to opti‐ mize the voltage gain of the amplifier and hence *Rf* and the transimpedance gain. This maxi‐ mum voltage gain was shown to be limited by stability considerations. Model Results were

Design of Multi Gb/s Monolithically Integrated Photodiodes and Multi-Stage Transimpedance Amplifiers in Thin-Film

Finally, in the Single-stage Transimpedance Amplifier Modeling section, we have presented a top-down methodology to design transimpedance amplifiers when the voltage gain is de‐

In this case we showed that the maximum voltage gain was limited, on one hand, by stabili‐ ty considerations (which usually prevail in weak or moderate inversion regime), and on a second hand, by feasibility considerations (which usually prevail in strong inversion). Our design procedure was applied to the design of a single-stage 10GHz bandwidth transimpe‐ dance amplifier in a 0.13 *μm* PD-SOI CMOS technology and to the design of a 1GHz band‐ width single-stage transimpedance amplifier in a 0.5 *μm* FD-SOI CMOS technology. Model

Model results for the 3-stage 1GHz bandwidth transimpedance amplifier in a 0.13 *μm* PD-SOI CMOS technology showed that *Cin* was very low owing to 1) very good AC performan‐ ces of thin-film SOI photodiodes (the monolithic integration which avoid bonding capacitor is possible due to the availability of thin-film SOI diodes with 1GHz bandwidth and the very low capacitance of the SOI PIN photodiodes themselves) and 2) the low capacitances of MOS transistors in SOI technology. This fact combined with the high technology *<sup>f</sup> <sup>t</sup>*

ratio which has enabled the multi-stages approach, has allowed for chosing a very high feedback resistor and then to achieve very high transimpedance gain and low noise opera‐ tion and this with a very low power consumption. Coupled with the very good responsivity at 405nm (0.25 A/W) and the very low dark current (DC performances) of the thin-film SOI photodiodes, a record sensitivity of 1μW (with a BER of 10-12) is projected. This shows the adequacy of 0.13 *μm* PD-SOI CMOS technology for Blue-DVD applications where the todays specifications are to be able to read input optical power of a few μW [9] but at a 4 times low‐ er bandwidth (250MHz). Coupled with the low responsivity of the thin-film SOI photodio‐ des at 850nm (0.005A/W), a sensitivity of 50μW or -13dBm is still achieved which is considered as an adequate sensitivity receiver for optical communications and comparable to CMOS realization reported in the literature using non integrated diodes with a 90 time better responsivity [31]. This shows the potential interest of this technology for monolithical‐ ly integrated 1Gb/s optical communication receivers at 850nm or even to realize a blue DVD

The design of a 1GHz bandwidth single-stage transimpedance amplifier in a 0.5 *μm* FD-SOI CMOS technology has allowed us to draw conclusions on the evolution of the performances vs. the CMOS technology scaling down, when compared to the previous design. We first no‐

. This is the case for very high speed single stage transimpedance amplifiers.

of a given technology

http://dx.doi.org/ 10.5772/50531

SOI CMOS Technology

363

*BWtrans*

mpedance amplifier is not too close to the transistors frequency limit *ft*

Results were validated by Eldo numerical simulations and measurements.

player which is compatible with the previous red standard.

**Figure 16.** a) Photograph of the TIA chip. On the left: the TIA with the output buffer and the photodiode emulator used for the S parameter measurements. On the right: TIA with the PIN photodiode and the output buffer. b) Meas‐ ured and Eldo-simulated curves of *S21vs*. frequency. Vdd=1.2V. *VinDC*=0.35V. *VB*=0.3V. *Vbias*=0.35V.

The bandwidth of the TIA is characterized by the *S21* parameter which is equal to *gma.Zcl.Avout*. It is dominated in the frequency band of interest by the transimpedance poles. *Avout* is the gain of the output buffer which is a little less than one (-1.8dB) in the bandwidth of interest. Measured curve of *S21 vs*. frequency is compared to the Eldo simulated curve in fig. 16b. Both are very similar and have a bandwidth slightly exceeding 10GHz. The few dB difference between the low frequency plateau of *S21* is related to a small difference in bias currents. The measured current consumption (equal to 2x*IdB*+2x*Id2*+*Idout*) is equal to 5mA while the simulated one is equal to 6mA. This confirms experimentally the ability of 0.13 μm CMOS SOI technology for 10Gb/s transimpedance circuits.

#### **6. Conclusions**

In this chapter the design of the transimpedance amplifier, which is the most used receiver front-end for high speed optical applications, has been investigated.

In the Optical Receivers Basics section, the simple resistor system was first presented as well as its limitations. The transimpedance amplifier was then introduced and its basic theory and concepts such as transimpedance gain, bandwidth and stability were derived. Impor‐ tant figures of merit to compare transimpedance amplifiers were also discussed as well as some architectures most often used in the high speed communication area.

Then in the Design of Multistage Transimpedance Amplifiers section, we have presented our top-down methodology to design transimpedance amplifiers in the case where the volt‐ age gain of the voltage amplifier used in the transimpedance amplifier is independent of the feedback resistor *Rf* . We have shown that this happens when the bandwidth of the transi‐ mpedance amplifier is not too close to the transistors frequency limit *ft* of a given technology and leads to multi-stages approach. Our systematic design procedure was then applied to the design of a 3-stages 1GHz bandwidth transimpedance amplifier in a 0.13 *μm* PD-SOI CMOS technology. It has allowed us to determine the optimal number of stages (3) to opti‐ mize the voltage gain of the amplifier and hence *Rf* and the transimpedance gain. This maxi‐ mum voltage gain was shown to be limited by stability considerations. Model Results were validated by Eldo numerical simulations.

diode emulator, an equivalent photocurrent is created at the TIA input. This allows for the electrical characterization of the TIA bandwidth. A photograph of the chip is shown in Fig 16a. S parameters measurements were done in the 40MHz-40GHz band. These measure‐ ments were obtained after a calibration to remove the impedance effect of the RF probes and

**Figure 16.** a) Photograph of the TIA chip. On the left: the TIA with the output buffer and the photodiode emulator used for the S parameter measurements. On the right: TIA with the PIN photodiode and the output buffer. b) Meas‐

The bandwidth of the TIA is characterized by the *S21* parameter which is equal to *gma.Zcl.Avout*. It is dominated in the frequency band of interest by the transimpedance poles. *Avout* is the gain of the output buffer which is a little less than one (-1.8dB) in the bandwidth of interest. Measured curve of *S21 vs*. frequency is compared to the Eldo simulated curve in fig. 16b. Both are very similar and have a bandwidth slightly exceeding 10GHz. The few dB difference between the low frequency plateau of *S21* is related to a small difference in bias currents. The measured current consumption (equal to 2x*IdB*+2x*Id2*+*Idout*) is equal to 5mA while the simulated one is equal to 6mA. This confirms experimentally the ability of 0.13 μm

In this chapter the design of the transimpedance amplifier, which is the most used receiver

In the Optical Receivers Basics section, the simple resistor system was first presented as well as its limitations. The transimpedance amplifier was then introduced and its basic theory and concepts such as transimpedance gain, bandwidth and stability were derived. Impor‐ tant figures of merit to compare transimpedance amplifiers were also discussed as well as

Then in the Design of Multistage Transimpedance Amplifiers section, we have presented our top-down methodology to design transimpedance amplifiers in the case where the volt‐ age gain of the voltage amplifier used in the transimpedance amplifier is independent of the

ured and Eldo-simulated curves of *S21vs*. frequency. Vdd=1.2V. *VinDC*=0.35V. *VB*=0.3V. *Vbias*=0.35V.

CMOS SOI technology for 10Gb/s transimpedance circuits.

front-end for high speed optical applications, has been investigated.

some architectures most often used in the high speed communication area.

**6. Conclusions**

cables used to connect the device to the spectrum analyzer.

362 Photodiodes - From Fundamentals to Applications

Finally, in the Single-stage Transimpedance Amplifier Modeling section, we have presented a top-down methodology to design transimpedance amplifiers when the voltage gain is de‐ pendent on *Rf* . This is the case for very high speed single stage transimpedance amplifiers. In this case we showed that the maximum voltage gain was limited, on one hand, by stabili‐ ty considerations (which usually prevail in weak or moderate inversion regime), and on a second hand, by feasibility considerations (which usually prevail in strong inversion). Our design procedure was applied to the design of a single-stage 10GHz bandwidth transimpe‐ dance amplifier in a 0.13 *μm* PD-SOI CMOS technology and to the design of a 1GHz band‐ width single-stage transimpedance amplifier in a 0.5 *μm* FD-SOI CMOS technology. Model Results were validated by Eldo numerical simulations and measurements.

Model results for the 3-stage 1GHz bandwidth transimpedance amplifier in a 0.13 *μm* PD-SOI CMOS technology showed that *Cin* was very low owing to 1) very good AC performan‐ ces of thin-film SOI photodiodes (the monolithic integration which avoid bonding capacitor is possible due to the availability of thin-film SOI diodes with 1GHz bandwidth and the very low capacitance of the SOI PIN photodiodes themselves) and 2) the low capacitances of

MOS transistors in SOI technology. This fact combined with the high technology *<sup>f</sup> <sup>t</sup> BWtrans*

ratio which has enabled the multi-stages approach, has allowed for chosing a very high feedback resistor and then to achieve very high transimpedance gain and low noise opera‐ tion and this with a very low power consumption. Coupled with the very good responsivity at 405nm (0.25 A/W) and the very low dark current (DC performances) of the thin-film SOI photodiodes, a record sensitivity of 1μW (with a BER of 10-12) is projected. This shows the adequacy of 0.13 *μm* PD-SOI CMOS technology for Blue-DVD applications where the todays specifications are to be able to read input optical power of a few μW [9] but at a 4 times low‐ er bandwidth (250MHz). Coupled with the low responsivity of the thin-film SOI photodio‐ des at 850nm (0.005A/W), a sensitivity of 50μW or -13dBm is still achieved which is considered as an adequate sensitivity receiver for optical communications and comparable to CMOS realization reported in the literature using non integrated diodes with a 90 time better responsivity [31]. This shows the potential interest of this technology for monolithical‐ ly integrated 1Gb/s optical communication receivers at 850nm or even to realize a blue DVD player which is compatible with the previous red standard.

The design of a 1GHz bandwidth single-stage transimpedance amplifier in a 0.5 *μm* FD-SOI CMOS technology has allowed us to draw conclusions on the evolution of the performances vs. the CMOS technology scaling down, when compared to the previous design. We first no‐ tice that the use of a more advanced technology has allowed us to use 3 stages instead of one owing to its better *ft* for same TIA bandwidth. This has naturally allowed a real increase of the performances of the transimpedance: transimpedance gain *Zcl* by more than 16 times, sensitiv‐ ity improved by 7.5 times, but at a 4 times higher power consumption in the 0.13*μm* technolo‐ gy. At same power consumption the receiver sensitivity in the 0.13*μm* technology, if slightly reduced, still remains more than 5 times better than the sensitivity of the 0.5*μm* design.

sensitivity of -13dBm. In order to increase the sensitivity at 850nm wavelength however, we can try to increase the diode responsivity. Promising solutions such as the use of SOI CMOS compatible GeOI photodiodes have been discussed in [1]. We can also try to further de‐

Design of Multi Gb/s Monolithically Integrated Photodiodes and Multi-Stage Transimpedance Amplifiers in Thin-Film

width of 7.5GHz, our model predicts a 850nm sensitivity of -1.25dBm. Combining this with an avalanche gain of 4 that has been demonstrated with thin-film SOI PIN diodes at 10 Gb/s [18], adequate sensitivity of at least -7dbm [8] should be achieved at 10Gb/s. To further im‐ prove the sensitivity, we think that the best solution is to attempt a multistage approach so that the voltage gain (and hence ZBW) could be improved. By reducing the bandwidth to about 7.5GHz and using inductive or capacitive peaking if necessary this could be achieved.

 of about 400 to 500GHz (improved by about a factor 4 compared to that of a 0.13*μm* technology), could allow for improving the sensitivity of the receiver at 10GHz by allowing for a multi-stage approach and a further reduction of *Cph*. Finally, in such technologies high‐ er data rate could be attempted, e.g. a single stage 40Gb/s. A SOI integrated PIN photodiode with a shorter intrinsic length could fulfill such requirements in terms of transit time cutoff frequency [1], but with an increased capacitance value. This, coupled with the reduced in‐ trinic voltage gain of the single stage amplifier related to the reduced early voltage of ultra short transistor, might result in too low *Rf* and sensitivity values. To compensate a reduced photodiode total surface but with no reduction of input power (i.e. relying on progress at

ICTEAM Institute Université catholique de Louvain, Louvain-La-Neuve, Belgium

Dalla Betta (Ed.). ISBN: 978-953-307-163-3, InTech, 153-172.

*and Systems I: Regular Papers*, Vol. 53(No. 7), 1458-1467.

[1] Afzalian, Aryan, & Flandre, Denis. (2011). Design of Thin-Film Lateral SOI PIN Pho‐ todiodes with up to Tens of GHz Bandwidth, Advances in Photodiodes, Gian Franco

[2] Schneider, K., & Zimmermann, H. (July 2006). "Three-stage burst-mode transimpe‐ dance amplifier in deep-sub-*μm* CMOS technology",. *IEEE Transactions on Circuits*

[3] Hermans, C., & Steyaert, M. (July 2006). "A high-speed 850-nm optical receiver frontend in 0.18- *μm* CMOS". *IEEE J. Solid-State Circuits*, Vol. 41(No.7), 1606-1614.

[4] Zimmermann, H. (2000). "Integrated Silicon Opto-electronics". Springer, Berlin.

. With a single-stage approach at a band‐

, such as 22nm CMOS ones

SOI CMOS Technology

365

http://dx.doi.org/ 10.5772/50531

crease the transimpedance noise by increasing *Rf*

the emitter side) might be necessary.

Aryan Afzalian and Denis Flandre

**Author details**

**References**

with *ft*

If not, the uses of very advanced technologies with improved *ft*


**Table 5.** Overview of 10 Gb/s Transimpedance receivers in the literature. LP and CP stand respectively for inductive and capacitive peaking techniques

Concerning the design of a single stage 10GHz bandwidth transimpedance amplifier in a 0.13 *μm* PD-SOI CMOS technology, the low *Cin*, due as previously to the monolithic SOI inte‐ gration, has enabled us to achieve the highest feedback resistor and one of the highest gain and then the highest transimpedance gain-bandwidth product ZBW (see table 5), as we are achieving one of the highest bandwidth reported for 10Gb/s (theoretically a bandwidth of about 3/4 the data rate is sufficient so that 10 GHz could be related to 13Gb/s operation)). This is achieved without using inductive (LP) or capacitive (CP) peaking techniques which allows to increase ZBW (or the bandwidth for same *Rf* ) but at the expense of chip area (in‐ ductors or capacitors to integrate), design complexity, need for tuning... Noise performances are also very good, especially compared to other CMOS designs. The power consumption of the TIA preamplifier (not the complete receiver) is one of the best achieved so far. However, coupled with the low responsivity of thin-film SOI photodiodes at 850nm, a sensitivity of 1.35*mW* or +1.3dBm is achieved for this monolithically integrated receiver for 10Gb/s optical communications at 850nm. At 405nm on the other hand, the same receiver achieves a high sensitivity of -13dBm. In order to increase the sensitivity at 850nm wavelength however, we can try to increase the diode responsivity. Promising solutions such as the use of SOI CMOS compatible GeOI photodiodes have been discussed in [1]. We can also try to further de‐ crease the transimpedance noise by increasing *Rf* . With a single-stage approach at a band‐ width of 7.5GHz, our model predicts a 850nm sensitivity of -1.25dBm. Combining this with an avalanche gain of 4 that has been demonstrated with thin-film SOI PIN diodes at 10 Gb/s [18], adequate sensitivity of at least -7dbm [8] should be achieved at 10Gb/s. To further im‐ prove the sensitivity, we think that the best solution is to attempt a multistage approach so that the voltage gain (and hence ZBW) could be improved. By reducing the bandwidth to about 7.5GHz and using inductive or capacitive peaking if necessary this could be achieved. If not, the uses of very advanced technologies with improved *ft* , such as 22nm CMOS ones with *ft* of about 400 to 500GHz (improved by about a factor 4 compared to that of a 0.13*μm* technology), could allow for improving the sensitivity of the receiver at 10GHz by allowing for a multi-stage approach and a further reduction of *Cph*. Finally, in such technologies high‐ er data rate could be attempted, e.g. a single stage 40Gb/s. A SOI integrated PIN photodiode with a shorter intrinsic length could fulfill such requirements in terms of transit time cutoff frequency [1], but with an increased capacitance value. This, coupled with the reduced in‐ trinic voltage gain of the single stage amplifier related to the reduced early voltage of ultra short transistor, might result in too low *Rf* and sensitivity values. To compensate a reduced photodiode total surface but with no reduction of input power (i.e. relying on progress at the emitter side) might be necessary.
