**2. Cu and Cu/CNT pillars for flip chip interconnect assembly**

Historically, IC chips have been electrically connected to the substrate by a wire bond meth‐ od. In this method, the chip faces up and is attached to the package via wires. This connec‐ tion has limited electrical performance and reliability problems in addition to requiring pad location at the edge of the die. Flip chip, also known as 'Controlled Collapse Chip Connec‐ tion, C4', replaced the traditional wire bond method. In this method, solder bumps are de‐ posited on the chip pads over the full area of the top side of the wafer during the final wafer processing step. In order to mount the chip to external circuitry (e.g., a circuit board or an‐ other chip or wafer), it is flipped over so that its top side faces down, aligned to the sub‐ strate and then the solder is reflowed to complete the interconnect. Generally, Sn-Pb based solder bumps have been used in flip chip packaging to connect chips to external circuitry. According to the International Technology Roadmap for Semiconductors the total number of I/Os will reach up to 10,000 cm2 chip area by 2014 which require finer interconnect with a pitch size less than 20 µm. To fabricate such fine pitch interconnect, conventional solder bump requires fine solder deposition or paste particle which are not readily available [67]. It is also important to reduce lead-based solders for environmental concerns (RoHS compli‐ ance). As circuit density increases, devices are also more vulnerable to non-uniform thermal distribution.

Cu has higher thermal conductivity than most binary or ternary solders. Cu bumps in flip chip assembly offer increased reliability, extended temperature range capability, greater me‐ chanical strength, higher connection density, improved manufacturability, better electrical and heat dissipating performance over Pb-Sn solder. It is also less expensive and decreases the amount of solder needed to create bumps. Cu pillars do not change shape during reflow so they do not encounter any volumetric redistribution which can lead to voids in the sol‐ der. Because of these advantages the semiconductor industry is adopting Cu pillar bump by electrodeposition for flip-chip attachment to replace the typical Pb solder [67, 68]. Power and thermal non-uniformity in devices are increasing steadily with each new device genera‐ tion leading to serious concerns for the industry regarding thermal issues. Mechanical stress on Cu bumps generated by the difference in thermal expansion coefficients between the chip and the substrate materials can lead to device failures. This differential thermal expansion also creates shearing forces at the bump. As a result bumps are most vulnerable to damage. Repeated thermal expansion and contraction leads to fatigue cracking of the bump.

ties must include mechanical strength, good thermal conductivity and stability with thermal

Carbon Nanotube Composites for Electronic Interconnect Applications

http://dx.doi.org/10.5772/52731

379

The key issues for 3D integration are process reliability, die degradation, electrical continui‐ ty, bump to pad electrical contact and thermal management. Temperature cycling and ther‐ mal shock accelerate fatigue failures. Also, non-uniform temperature distribution may influence the operation of circuits and sensing elements dramatically. Stress fields resulting from differential thermal expansion of Cu-based TSV may cause serious problems. The relia‐ bility problems of high aspect ratio TSV interconnect may be alleviated by the codeposition of carbon nanotubes (CNTs) with Cu as a suitable composite material. CNTs have high me‐ chanical strength, thermal conductivity and low coefficient of thermal expansion which may alleviate the issues related to die degradation and non-uniform temperature distribution in

In this work the Cu/CNT composites codeposition process was assessed and the deposited materials characterised. Electrochemical analysis of the deposition requires an analysis of the nucleation and growth characteristics for the candidate materials. MWCNTs have been added to the typical Cu sulphate plating bath to achieve homogeneous Cu/MWCNT compo‐ sites. Here, we will report electrochemical analysis and kinetics of electrodeposited Cu when MWCNTs were present in the bath. Solubilisation or suspension of the CNTs in the Cu bath is also a key requirement. Composite plating bath chemistries for Cu/CNT deposition were investigated. The influence of typical additives in the Cu bath on the deposit characteristics was determined for optimised electrodeposition in vias and trenches. The influence of dif‐ ferent surfactants on the deposition and electrical properties of composite films was also an‐ alyzed. Cu and Cu/CNT composites were electrodeposited on planar and structured substrates. Microstructure characterization of the deposit employed scanning electron mi‐ croscopy (SEM), focussed ion beam microscopy (FIB) and x-ray diffraction (XRD). The sheet resistance of Cu/CNTs film and changes due to self-annealing and high temperature anneal‐ ing were monitored by 4 point probe resistivity techniques. Cu/CNT composites were also deposited in test structures. After chemical mechanical polishing of the test structures, the

The amount of CNTs in the deposit was determined by dissolving the deposit in a concen‐ trate HNO3 solution. The Cu/CNT films were deposited on 1 cm X 1 cm thin film sputtered Cu on Si. The deposition current was 1 A and deposition time was 1 h. The concentration of CNTs in the bath was 10 or 100 mg/l. After deposition, the sample was dipped in hot con‐ centrate acidic solution (65% HNO3, 65°C). The diluted acid solution was then vacuum fil‐ tered using PTFE filter paper. The filtration process was repeated at least 5 times to ensure all CNTs were left on filter residue. After filtration, the PTFE membrane was dried in an oven at 80°C for at least 30 minutes to ensure the membrane was completely dried. The weight difference of the PTFE membrane before and after filtration gives the amount of

cycling.

the TSVs.

**4. Experimental methods**

line resistance was measured using a Cascade probe station.

Cu/CNT composites could be a suitable candidate material to resolve these issues for next generation flip chip assembly. CNTs have high mechanical strength (10-60 GPa, c.f. Cu 70 MPa) and thermal conductivity (>3000 W/m.K, c.f. Cu 400 W/m.K) which may alleviate the issues related to die degradation and non-uniform temperature distribution in the pillars. CNTs have a negative temperature coefficient of resistivity (- 1.5 х10-3/ºC, c.f. Cu + 4 х10-3/ºC) and low coefficient of thermal expansion (- 1.5 ppm/ºC, c.f. Cu + 17 ppm/ºC) which can make the Cu/CNT composites material more reliable against thermal cycling and fatigue with less risk of stress induced failure. Typical photolithography techniques can be utilised to fabri‐ cate Cu/CNT pillar bumps on chip. Arai et al [64] recently demonstrated Cu/CNT pillar emitters deposited by electrodeposition on a patterned substrate.

### **3. Cu and Cu/CNT in through Si via (TSV) for 3D interconnect**

Cu electrodeposition in TSV features is a key component of new 3D integration approaches that are of great interest in the semiconductor industry [69]. 3D integration increases per‐ formance and lowers power consumption due to reduced length of electrical connections. Cu has been selected as the TSV interconnect because of its low electrical resistance and compatibility with conventional multilayer interconnection in large-scale integration (LSI) and back-end processes. The key challenges for TSV plating processes are to fill the vias across the entire wafer and to complete the fill as fast as possible to minimize cost. TSV in‐ terconnect shortens the interconnect requirements and reduces signal delay. However, it is difficult to fill high aspect ratio vias without voids through conventional damascene electro‐ plating. Perfect filling without voids is required to minimise interconnect failure and relia‐ bility issues. TSVs have been extensively studied because of their ability to achieve chip stacking for enhanced system performance. This is a very promising technology that may replace wire bonding in chips or single chip solder bumping. Metal filled TSVs allow devi‐ ces to be connected using a 3D approach [69]. Cu is the best low cost conductor for TSV in‐ terconnect and an extension of the damascene plating in smaller features. Recently enormous attention has been given to bottom up filling of TSVs to fill high aspect ratio vias without voids like conventional damascene electroplating [70-72]. However, there are key issues that need to be resolved, such as process reliability, electrical continuity and thermal management. TSVs should have the ability to maintain operation over a wide range of tem‐ peratures and to withstand these temperatures in a cyclic manner. The TSV material proper‐ ties must include mechanical strength, good thermal conductivity and stability with thermal cycling.

The key issues for 3D integration are process reliability, die degradation, electrical continui‐ ty, bump to pad electrical contact and thermal management. Temperature cycling and ther‐ mal shock accelerate fatigue failures. Also, non-uniform temperature distribution may influence the operation of circuits and sensing elements dramatically. Stress fields resulting from differential thermal expansion of Cu-based TSV may cause serious problems. The relia‐ bility problems of high aspect ratio TSV interconnect may be alleviated by the codeposition of carbon nanotubes (CNTs) with Cu as a suitable composite material. CNTs have high me‐ chanical strength, thermal conductivity and low coefficient of thermal expansion which may alleviate the issues related to die degradation and non-uniform temperature distribution in the TSVs.
