**MATLAB as a Design and Verification Tool for the Hardware Prototyping of Wireless Communication Systems**

Oriol Font-Bach, Antonio Pascual-Iserte, Nikolaos Bartzoudis and David López Bueno

Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/48706

## **1. Introduction**

The ability to verify the capacity gains of novel signal processing techniques or the performance of new communication standards is one of the main research and development drivers of both academic and industrial entities. In this context, the signal processing community has adopted MATLAB as a flexible modelling, simulating and testing software development environment. MATLAB includes numerous toolboxes, open-source code and pre-compiled libraries, which facilitate the design of complex systems using high-level models and provides the means for rapid verification of signal processing algorithms and systems in a user-controlled environment. The growing number of its add-on features allows MATLAB to fill the gap between these high-level models and the physical implementation of systems; e.g., a real-time Field Programmable Array (FPGA)-based prototype. Moreover, the functionality of MATLAB is significantly extended with the use of Simulink [1], which serves as a schematic-entry design and programming environment. The integration of the System Generator blockset of Xilinx [2] to Simulink and the direct linking of the latter with the Xilinx FPGA-design toolchain enriches the target use-cases of the software. This approach allows the creation of FPGA binary executables from high-level models. MATLAB is also one of the most popular software-modelling environments, whose functionality is commonly interfaced nowadays with instruments to provide connectivity, control and programming solutions for rapid prototyping and testing. In fact, MATLAB scripts are increasingly used to program a wide variety of testing, signal generation and signal analysis hardware instruments. Thus, the programming versatility of MATLAB allows it to be used as a key software component in complex testbeds, which comprise a multitude of software programming interfaces and heterogeneous hardware instruments. The role of such testbeds is crucial because they enable the prototyping and validation of advanced research concepts under realistic conditions,

©2012 Bartzoudis et al., licensee InTech. This is an open access chapter distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0),which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. ©2012 Bartzoudis et al., licensee InTech. This is a paper distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

providing at the same time a detailed account of hardware requirements and implementation feasibility.

communication systems. Therefore, an incremental design approach based on custom-HDL coding is once again expected to be the most reliable solution to sort out well-established digital design problems (i.e., dense FPGA designs with compute intensive requirements and hard to achieve timing constraints [8]). The only difference is that the complexity of such problems is scaled because of the massive amount of FPGA logic, memories and embedded components that need to be addressed. Custom HDL coding provides the means to control every important aspect of the design, which requires an in-depth knowledge of the low-level

MATLAB as a Design and Veri cation Tool for the Hardware Prototyping of Wireless Communication Systems 189

The design and validation principles presented herein could be applied in many digital-design cases. Nonetheless, the application-domain will be narrowed down to well-characterized case studies, in order to help the reader to assimilate the described concepts, methodology and examples. Thus, this chapter explores the uses of MATLAB when the custom-HDL design flow is employed for the prototyping of systems with design and implementation

• *Advanced wireless communication system*: Algorithms and hardware technologies able to offer data rates higher than current systems are needed to cope with the requirements of emerging wireless communication systems. The MIMO technology, using multiple antennas both at the transmitter and receiver sides, combined with Orthogonal Frequency Division Multiplexing (OFDM) constitute a suitable technique for the implementation of advanced wireless communication systems. Additionally, the Orthogonal Frequency Division Multiple Access (OFDMA) is used to target Multi-User (MU) scenarios in high mobility conditions. A prominent MIMO configuration scheme proposed in OFDMA systems is the closed-loop one, where the receiver is providing information to the transmitter related to the current channel conditions by means of a dedicated feedback link. This improves the performance and usage of resources in scenarios with multiple competing users and fast channel fading (e.g., it is applied adaptive carrier allocation, Adaptive Modulation and Coding - AMC). The scenario can be augmented by contemplating an adaptive power-aware PHY-layer that takes into account the interaction with higher layers of the communication stack and user requirements (e.g., in terms of quality of service, monetary cost or battery constraints). The compliance with a modern wireless communication standard (e.g., mobile WiMAX, Long Term Evolution - LTE) also adds

• *Real-time operation*: The real-time operation implies transmission and reception of an uninterrupted data flow. To tackle the challenges of real-time operation, especially when accounting for wide bandwidth at baseband, a low-latency pipelined processing structure has to be designed. The latter requires a large amount of memory resources for the intermediate data storage and implies a complex control plane, which usually features multiple clock domains. Moreover, the operation of high performance wireless communication systems results in a growth of the design, implementation and validation complexity. Notwithstanding, the real-time operation gives the opportunity to realize closed-loop strategies requiring dynamic adaptation of the

RTL architecture.

requirements similar to the ones described next:

I Real-time system prototyping

strict design requirements.

system in response to the actual channel conditions.

The present chapter aims at describing how MATLAB can be used as a design and verification tool in the different phases of migrating a high-level model to a real-time hardware prototype, using as a case study the implementation of a real-life wireless communication system. The chapter proposes a generic design methodology and, finally, provides a practical case study related to the implementation of a real-time Multiple Input Multiple Output (MIMO) mobile WiMAX (i.e., IEEE 802.16e) system [3, 4].

## **1.1. Considered development scenarios**

Real-time system-prototyping using FPGA devices is a painstaking and time-consuming process that goes beyond a controlled computer simulation. In this context, MATLAB is having a manifold contribution as a design and validation tool. In order to successfully leverage the advices, techniques and design methodology, it is required to define the specific development scenarios that have to be considered by digital design developers.

It is important to note that this chapter will not cover model-based, MATLAB-to-Register Transfer Level (RTL) design flows (e.g., by using the Simulink and System Generator tools). Adversely, a custom-code programming strategy will be followed, where the user carefully designs each component of the system and takes into account the constraints of real-world hardware and signals. Our focus is to unveil the key role that MATLAB plays when the design objective is the creation of custom Hardware Description Language (HDL) code (e.g., Very High Speed Integrated Circuit - VHSIC - HDL, VHDL) that targets high-performance wireless communication prototypes. In fact, converting a MATLAB model into a working VHDL code for such FPGA-based prototypes requires a considerable effort. Although the automatic MATLAB-to-HDL conversion is becoming increasingly popular, its efficiency is still under scrutiny by the FPGA designer community [5]. The main concern raised is that the MATLAB-to-HDL automatic conversion is not yet mature enough to cover the needs of processing demanding FPGA-based systems, where performance and constraints imposed by the size and the embedded resources of the target device, may occasionally render this option unsuitable. The direct MATLAB-to-HDL translation accepts only very limited constructs that can be automatically translated into hardware [6]. Other approaches, involving an intermediate stage of Matlab-to-C code generation, can be used as an alternative. The produced C code is consequently processed by C-to-HDL synthesis tools subject to certain modifications (i.e., the generated C code contains unsupported constructs that prevent a seamless translation to HDL code).

As already mentioned, the automatically-produced HDL code is usually not as efficient as the custom hand-written HDL one. This difference is becoming a significant factor to be considered when stringent FPGA area utilization conditions apply or when performance and achievable clock frequencies do matter [7]. The modern FPGA devices and the corresponding synthesis tools seem to address the issues mentioned before. This is due to the extraordinary capacities of the new devices in terms of embedded resources (logic, memories dedicated Digital Signal Processing - DSP - logic) and the significant improvement of the FPGA design and implementation tools. However, it is anticipated that the FPGA-based prototyping and the respective FPGA design tools are due to be challenged soon by the constantly aggregated performance requirements and algorithmic complexity of next generation wireless communication systems. Therefore, an incremental design approach based on custom-HDL coding is once again expected to be the most reliable solution to sort out well-established digital design problems (i.e., dense FPGA designs with compute intensive requirements and hard to achieve timing constraints [8]). The only difference is that the complexity of such problems is scaled because of the massive amount of FPGA logic, memories and embedded components that need to be addressed. Custom HDL coding provides the means to control every important aspect of the design, which requires an in-depth knowledge of the low-level RTL architecture.

The design and validation principles presented herein could be applied in many digital-design cases. Nonetheless, the application-domain will be narrowed down to well-characterized case studies, in order to help the reader to assimilate the described concepts, methodology and examples. Thus, this chapter explores the uses of MATLAB when the custom-HDL design flow is employed for the prototyping of systems with design and implementation requirements similar to the ones described next:

### I Real-time system prototyping

2 Will-be-set-by-IN-TECH

providing at the same time a detailed account of hardware requirements and implementation

The present chapter aims at describing how MATLAB can be used as a design and verification tool in the different phases of migrating a high-level model to a real-time hardware prototype, using as a case study the implementation of a real-life wireless communication system. The chapter proposes a generic design methodology and, finally, provides a practical case study related to the implementation of a real-time Multiple Input Multiple Output (MIMO) mobile

Real-time system-prototyping using FPGA devices is a painstaking and time-consuming process that goes beyond a controlled computer simulation. In this context, MATLAB is having a manifold contribution as a design and validation tool. In order to successfully leverage the advices, techniques and design methodology, it is required to define the specific

It is important to note that this chapter will not cover model-based, MATLAB-to-Register Transfer Level (RTL) design flows (e.g., by using the Simulink and System Generator tools). Adversely, a custom-code programming strategy will be followed, where the user carefully designs each component of the system and takes into account the constraints of real-world hardware and signals. Our focus is to unveil the key role that MATLAB plays when the design objective is the creation of custom Hardware Description Language (HDL) code (e.g., Very High Speed Integrated Circuit - VHSIC - HDL, VHDL) that targets high-performance wireless communication prototypes. In fact, converting a MATLAB model into a working VHDL code for such FPGA-based prototypes requires a considerable effort. Although the automatic MATLAB-to-HDL conversion is becoming increasingly popular, its efficiency is still under scrutiny by the FPGA designer community [5]. The main concern raised is that the MATLAB-to-HDL automatic conversion is not yet mature enough to cover the needs of processing demanding FPGA-based systems, where performance and constraints imposed by the size and the embedded resources of the target device, may occasionally render this option unsuitable. The direct MATLAB-to-HDL translation accepts only very limited constructs that can be automatically translated into hardware [6]. Other approaches, involving an intermediate stage of Matlab-to-C code generation, can be used as an alternative. The produced C code is consequently processed by C-to-HDL synthesis tools subject to certain modifications (i.e., the generated C code contains unsupported constructs that prevent a

As already mentioned, the automatically-produced HDL code is usually not as efficient as the custom hand-written HDL one. This difference is becoming a significant factor to be considered when stringent FPGA area utilization conditions apply or when performance and achievable clock frequencies do matter [7]. The modern FPGA devices and the corresponding synthesis tools seem to address the issues mentioned before. This is due to the extraordinary capacities of the new devices in terms of embedded resources (logic, memories dedicated Digital Signal Processing - DSP - logic) and the significant improvement of the FPGA design and implementation tools. However, it is anticipated that the FPGA-based prototyping and the respective FPGA design tools are due to be challenged soon by the constantly aggregated performance requirements and algorithmic complexity of next generation wireless

development scenarios that have to be considered by digital design developers.

feasibility.

WiMAX (i.e., IEEE 802.16e) system [3, 4].

seamless translation to HDL code).

**1.1. Considered development scenarios**


#### 4 Will-be-set-by-IN-TECH 190 MATLAB – A Fundamental Tool for Scienti c Computing and Engineering Applications – Volume 2 MATLAB as a Design and Verication Tool for the Hardware Prototyping of Wireless Communication Systems <sup>5</sup>

• *FPGA-based prototyping*: The inherent parallelism of FPGA devices is providing the means to prototype bit-intensive systems following an RTL-design approach. In this context, the designer has to evaluate the computational, storage and timing requirements of the target FPGA-based platform, in order to ensure that the implementation is feasible. Additionally, the FPGA-based prototyping of baseband DSP algorithms using a custom HDL design flow, typically implies the use of fixed-point logic. Therefore, an optimum trade-off between the implementation complexity and the precision of the internal calculations has to be defined (i.e., maximizing the dynamic range at baseband). The effort of interfacing the user design with the on-board buses, peripherals and components residing outside the FPGA device (e.g., Analog-to-Digital - ADC - and Digital-to-Analog - DAC - circuitry) is a critical part of the on-board validation, because it can be proved quite costly in terms of time. Finally, the losses introduced by the ADCs, DACs and baseband digital logic can be calculated to quantify the precision of the FPGA-based prototype.

algorithms. However, certain data capturing and post-processing limitations apply, especially when the testing requires reception of long data frames under high mobility conditions. In fact, although offline prototyping accelerates the design and testing of algorithms, it is important to understand its foundations and design particularities e.g., unconstrained computational and storage resources, unlimited precision using floating-point implementation, no need to account for real-life implementation constraints or the complexity of the control plane, perfectly synchronized signals or ideal channels are typically assumed. Thus it is clear that in order to achieve a thorough analysis of the implementation cost and feasibility of the target system (especially in scenarios requiring dynamic responsiveness or high mobility), real-time

MATLAB as a Design and Veri cation Tool for the Hardware Prototyping of Wireless Communication Systems 191

• *Hardware/software partitioning*: the flexibility of non real-time prototyping in terms of resource requirements allows the designer to select an optimum hardware/software partitioning accounting for the implementation cost. It is a common practice to maintain the algorithms in MATLAB space, while only the RF section and the data capturing operates in real-time. Alternatively, a subset of the signal processing algorithms can be mapped to a DSP or a FPGA implementation, following a

• *Hybrid prototyping*: the granularity of the prototyping strategy can be adjusted to fit the specific design and budget requirements. For instance a reduction in the prototyping complexity can be achieved by implementing/emulating more features in MATLAB-space or by making assumptions and system-wide simplifications. In hybrid prototypes a portion of the design resides in a computer simulation, while at the same time dedicated memory interfaces facilitate the communication with the bit-intensive portion of the design that runs on a FPGA device. This prototyping method downscales the real-time processing requirements in order to cope with the data-exchange constraints between the software and hardware processing domain.

As it has been described in the previous section, system-prototyping involving FPGAs and other specialized hardware equipment is subject to non idealities and certain signal impairments, which are not usually considered in a computer-based simulation (i.e., high-level models). Moreover, the heterogeneous hardware boards used for the prototyping of high performance real-time systems impose a series of hardware constraints in terms of processing capacity, available memory, maximum achievable clock frequency, I/O interfacing,

In the following sections, it will be shown how the previously described operating conditions and constraints can be either modelled or considered in MATLAB throughout the design and implementation process. The goal is to demonstrate the plural contribution of MATLAB in the FPGA-based rapid prototyping, beyond its well-established function as a high-level

I *Definition of system requirements*: Apart from its traditional operating perception, MATLAB can be used as a key companion throughout the analysis of system requirements in terms of computational resources and cost (e.g., implementation complexity, optimal hardware platform selection). Once the deployment scenario and specifications are

prototyping has to be employed.

DAC/ADC resolution and power consumption.

modelling tool:

co-simulation or hardware-in-the-loop testing approach.

**1.2. The role of MATLAB in the design and validation process**

	- *Advanced wireless communication system*: The goal in this case is the rapid prototyping of advanced techniques able to satisfy the requirements of future wireless communication systems. As it will be detailed in the following lines, the prototypes that principally operate offline make a series of assumptions to simplify the testing and deployment conditions and remove or ignore real-life implementation constraints. This inevitably results in a partial validation of the systems under test, especially for those cases where exhaustive offline data processing is practically impossible. Nonetheless, their contribution is also significant because they enable the design and preliminary experimental evaluation of algorithms beyond the state-of-the-art.
	- *Off-line operation*: One of the main drivers of rapid prototyping is based on hybrid experimental testbeds that combine real-time processing and offline software-based post-processing. Such platforms, make use of commercial Vector Signal Generator (VSG) instruments equipped with arbitrary waveform generators. These are configured with user-generated MATLAB vectors, which represent the output of a baseband transmitter and eventually produce a real-time RF signal that is transmitted using either antennas or a direct cable connection. Offline testbeds may also use a RF channel emulator or other instruments that combine signal generation and channel fading. On the receiver side the data is stored in large buffers (e.g., FPGA) and retrieved in order to be post-processed offline. The captured signals are used as test vectors that facilitate the modelling of the baseband signal processing algorithms of the receiver (i.e., MATLAB high-level model of the system). This prototyping methodology allows the rapid verification of the functionality and performance of

4 Will-be-set-by-IN-TECH

can be calculated to quantify the precision of the FPGA-based prototype.

post-processing and metric calculation in MATLAB-space).

II Offline system prototyping

• *Heterogeneous hardware setup*: The validation of high performance FPGA-based prototypes requires close to real-world testing conditions, which provide the means to properly tune the operating behaviour according to the defined deployment-scenarios. This in turn implies the use of a testbed which features a heterogeneous hardware setup. A real-time testbed typically comprises Radio-Frequency (RF) front-ends, signal generation and signal acquisition hardware boards, FPGA-DSP based baseband boards and other specialized equipment (e.g., radio channel emulator, digital oscilloscope). Moreover, testbeds have data-capturing interfaces that enable the performance characterization of the system (i.e., off-line data

• *Advanced wireless communication system*: The goal in this case is the rapid prototyping of advanced techniques able to satisfy the requirements of future wireless communication systems. As it will be detailed in the following lines, the prototypes that principally operate offline make a series of assumptions to simplify the testing and deployment conditions and remove or ignore real-life implementation constraints. This inevitably results in a partial validation of the systems under test, especially for those cases where exhaustive offline data processing is practically impossible. Nonetheless, their contribution is also significant because they enable the design and preliminary experimental evaluation of algorithms beyond the state-of-the-art. • *Off-line operation*: One of the main drivers of rapid prototyping is based on hybrid experimental testbeds that combine real-time processing and offline software-based post-processing. Such platforms, make use of commercial Vector Signal Generator (VSG) instruments equipped with arbitrary waveform generators. These are configured with user-generated MATLAB vectors, which represent the output of a baseband transmitter and eventually produce a real-time RF signal that is transmitted using either antennas or a direct cable connection. Offline testbeds may also use a RF channel emulator or other instruments that combine signal generation and channel fading. On the receiver side the data is stored in large buffers (e.g., FPGA) and retrieved in order to be post-processed offline. The captured signals are used as test vectors that facilitate the modelling of the baseband signal processing algorithms of the receiver (i.e., MATLAB high-level model of the system). This prototyping methodology allows the rapid verification of the functionality and performance of

• *FPGA-based prototyping*: The inherent parallelism of FPGA devices is providing the means to prototype bit-intensive systems following an RTL-design approach. In this context, the designer has to evaluate the computational, storage and timing requirements of the target FPGA-based platform, in order to ensure that the implementation is feasible. Additionally, the FPGA-based prototyping of baseband DSP algorithms using a custom HDL design flow, typically implies the use of fixed-point logic. Therefore, an optimum trade-off between the implementation complexity and the precision of the internal calculations has to be defined (i.e., maximizing the dynamic range at baseband). The effort of interfacing the user design with the on-board buses, peripherals and components residing outside the FPGA device (e.g., Analog-to-Digital - ADC - and Digital-to-Analog - DAC - circuitry) is a critical part of the on-board validation, because it can be proved quite costly in terms of time. Finally, the losses introduced by the ADCs, DACs and baseband digital logic

algorithms. However, certain data capturing and post-processing limitations apply, especially when the testing requires reception of long data frames under high mobility conditions. In fact, although offline prototyping accelerates the design and testing of algorithms, it is important to understand its foundations and design particularities e.g., unconstrained computational and storage resources, unlimited precision using floating-point implementation, no need to account for real-life implementation constraints or the complexity of the control plane, perfectly synchronized signals or ideal channels are typically assumed. Thus it is clear that in order to achieve a thorough analysis of the implementation cost and feasibility of the target system (especially in scenarios requiring dynamic responsiveness or high mobility), real-time prototyping has to be employed.


## **1.2. The role of MATLAB in the design and validation process**

As it has been described in the previous section, system-prototyping involving FPGAs and other specialized hardware equipment is subject to non idealities and certain signal impairments, which are not usually considered in a computer-based simulation (i.e., high-level models). Moreover, the heterogeneous hardware boards used for the prototyping of high performance real-time systems impose a series of hardware constraints in terms of processing capacity, available memory, maximum achievable clock frequency, I/O interfacing, DAC/ADC resolution and power consumption.

In the following sections, it will be shown how the previously described operating conditions and constraints can be either modelled or considered in MATLAB throughout the design and implementation process. The goal is to demonstrate the plural contribution of MATLAB in the FPGA-based rapid prototyping, beyond its well-established function as a high-level modelling tool:

I *Definition of system requirements*: Apart from its traditional operating perception, MATLAB can be used as a key companion throughout the analysis of system requirements in terms of computational resources and cost (e.g., implementation complexity, optimal hardware platform selection). Once the deployment scenario and specifications are strictly defined (e.g., operating frequencies, channel bandwidth, channel specifications, sampling frequencies, DAC-ADC resolution) the high-level MATLAB model of the system can be modified to satisfy real-life system characteristics, according to the following key points:

The process of mapping a high-level MATLAB model to HDL logic and consequently to FPGA-based hardware is a complex and costly process, where many crucial decisions need to be taken. These include among others the environment where the system will be deployed, the expected operating conditions and the target implementation technology. MATLAB can be easily interfaced with third-party EDA tools and hardware equipment [14], a fact that facilitates this decision-making process. Additionally, the use of MATLAB in all prototyping-stages makes easier the interaction between different design-teams by providing

MATLAB as a Design and Veri cation Tool for the Hardware Prototyping of Wireless Communication Systems 193

The design, implementation and on-board testing of high performance wireless communication systems under realistic conditions implies an undertaking with high stakes. Thus, the adoption of a well-structured design, implementation and validation methodology is a paramount requirement. The aim of this section is to offer an insight to a robust, yet generic, methodology, which demonstrates the contribution of MATLAB during the FPGA prototyping stages using a custom HDL design entry. The effectiveness of the proposed methodology is analysed using a practical case study, which involves the

A fundamental guideline that applies throughout the design, implementation and on-board validation phases is a multi-stage testing strategy (Fig. 1). This starts from a baseband-to-baseband system testing under ideal conditions. The latter is performed both in simulation-time (MATLAB and consequently HDL-based) and at real-time in the target hardware platform using a direct connection of the transmitter and receiver. The scenario can then be augmented by adding the conversion stages (i.e., ADC and DAC). This implies re-simulating the MATLAB and HDL code and finally validate the FPGA implementation in real-time (i.e., connecting via a cable the output of the DAC device with the input of the ADC device). The final testing stage can be divided in two sub-stages; the first includes a direct cable connection of the RF front-ends and the second the inclusion of channel either by using antennas or a real-time channel emulator (both sub-stages can be priorly simulated in MATLAB and in HDL). This incremental testing approach allows the

The development of a processing demanding real-time wireless communication system requires a wide range of skills, resources and time. A commonly accepted commencing point is the design of a baseline version of the target system, which complies with the following

• *Modularity:* This feature facilitates the substitution, modification, extension and/or reuse

• *Downscaled specifications:* The initial design-efforts should focus on the core signal processing algorithms and on the most critical aspects of the overall system architecture (e.g., high-throughput pipeline structures combined with efficient memory and control

a common working framework.

**2. Design methodology**

prototyping of a real-time MIMO mobile WiMAX system.

step-by-step characterization of the system.

of specific parts of the design.

**2.1. Starting point**

design requirements:

planes).


The process of mapping a high-level MATLAB model to HDL logic and consequently to FPGA-based hardware is a complex and costly process, where many crucial decisions need to be taken. These include among others the environment where the system will be deployed, the expected operating conditions and the target implementation technology. MATLAB can be easily interfaced with third-party EDA tools and hardware equipment [14], a fact that facilitates this decision-making process. Additionally, the use of MATLAB in all prototyping-stages makes easier the interaction between different design-teams by providing a common working framework.

## **2. Design methodology**

6 Will-be-set-by-IN-TECH

following key points:

FPGA-re-sources).

planes.

processing chain (baseband, RF and channel).

performance and computational load.

performance validation of the RTL-algorithms.

imported in MATLAB.

strictly defined (e.g., operating frequencies, channel bandwidth, channel specifications, sampling frequencies, DAC-ADC resolution) the high-level MATLAB model of the system can be modified to satisfy real-life system characteristics, according to the

• Account for system-wide signal impairments introduced by the complete hardware

• Identify the most critical signal-processing blocks that play a definitive role in system's

• Select the optimum algorithms satisfying a trade-off between resulting precision, hardware specifications and implementation complexity (e.g., required

• Account for the specifications, operation and functionality of the memory and control

II *Co-simulation*: A very useful practice during the early stages of prototype development is to implement and simulate different parts of the target system using different design approaches and tools; i.e., one part of the system remains modelled and simulated in MATLAB, while the rest is designed using lower-level HDL simulation tools. The co-simulation of the differently modelled parts requires the communication of MATLAB with third party simulation environments. This can be realised by utilizing the data importing and exporting capabilities of MATLAB, or as it will be discussed later, by exploiting the interfaces of MATLAB with certain third-party tools. For instance, the prototyping of systems or algorithms using offline testbeds typically implies that the complex signal processing algorithms, and other emulated functionalities that serve the testing scenario, remain modelled in MATLAB. Using standard I/O functions, binary data can be read, written and quantized in MATLAB-space, providing a direct way to communicate with the remaining portion of the system which resides in an HDL-based simulation (i.e., using equivalent I/O connectivity options). The same co-simulation methodology can be used to test an algorithm, an independent processing block or a complete system designed in MATLAB against its HDL-based counterpart (designed in third party RTL simulation tools). This type of co-simulations have a critical contribution in the prototyping of real-life FPGA-based systems, because they provide the means to assess the fixed-point precision of the independent processing blocks comprising a digital baseband system and also because they produce reliable test vectors, which enable the

III *Verification of the hardware-produced results*: MATLAB supports data importing and exporting in various formats and includes a series of pre-compiled libraries and mathematical functions. The latter facilitate the post-processing of data captured by baseband processing boards and assist the verification of the results produced by a FPGA-based prototype. The only requirement as far as the baseband signal processing platform is concerned is its ability to capture large amount of data in files that could be

IV *Rapid-prototyping*: the previously described features and design-capacities of MATLAB are making it a prime candidate for the off-line prototyping and validation of wireless communication systems. Indeed, MATLAB plays a key role in off-line testbeds that are

used to prototype state-of-the-art MIMO-OFDM systems [9–13].

• Adjust the data quantization at the different baseband processing stages.

The design, implementation and on-board testing of high performance wireless communication systems under realistic conditions implies an undertaking with high stakes. Thus, the adoption of a well-structured design, implementation and validation methodology is a paramount requirement. The aim of this section is to offer an insight to a robust, yet generic, methodology, which demonstrates the contribution of MATLAB during the FPGA prototyping stages using a custom HDL design entry. The effectiveness of the proposed methodology is analysed using a practical case study, which involves the prototyping of a real-time MIMO mobile WiMAX system.

A fundamental guideline that applies throughout the design, implementation and on-board validation phases is a multi-stage testing strategy (Fig. 1). This starts from a baseband-to-baseband system testing under ideal conditions. The latter is performed both in simulation-time (MATLAB and consequently HDL-based) and at real-time in the target hardware platform using a direct connection of the transmitter and receiver. The scenario can then be augmented by adding the conversion stages (i.e., ADC and DAC). This implies re-simulating the MATLAB and HDL code and finally validate the FPGA implementation in real-time (i.e., connecting via a cable the output of the DAC device with the input of the ADC device). The final testing stage can be divided in two sub-stages; the first includes a direct cable connection of the RF front-ends and the second the inclusion of channel either by using antennas or a real-time channel emulator (both sub-stages can be priorly simulated in MATLAB and in HDL). This incremental testing approach allows the step-by-step characterization of the system.

## **2.1. Starting point**

The development of a processing demanding real-time wireless communication system requires a wide range of skills, resources and time. A commonly accepted commencing point is the design of a baseline version of the target system, which complies with the following design requirements:


8 Will-be-set-by-IN-TECH 194 MATLAB – A Fundamental Tool for Scienti c Computing and Engineering Applications – Volume 2 MATLAB as a Design and Verication Tool for the Hardware Prototyping of Wireless Communication Systems <sup>9</sup>

**Figure 1.** Multi-stage testing strategy

Once the baseline system-model is designed and validated, the proposed methodology can adjust the granularity of the system by accommodating more advanced features.

## **2.2. Proposed methodology**

This section gives the details of the proposed design methodology, which is depicted in Fig. 2.

I *Basic transmitter modelling*: The first vital requirement for the design of any wireless communication system is the definition of the transmitted signal. The modelling of the transmitted signal is in most cases bound to the specifications of a wireless communication standard, which indicatively includes the OFDM parameters, the duplexing mode, the format and length of the frame, the number, value and location of the pilot tones, the guard-band size, the inter-carrier spacing, the available bandwidth sizes and the RF operating bands. At this initial stage the model of the transmitted signal is based on certain ideal conditions i.e., using floating-point logic, assuming unlimited processing resources during design-time and not accounting for signal-impairments (e.g., channel effects, noise).

**Figure 2.** Proposed design, implementation and validation methodology

is directly interfaced with advanced instrumentation to produce a real-time signal. This signal can be then processed by specific testing hardware (e.g., signal analysers, digital oscilloscopes), which communicate with proprietary third-party software in order to perform standard-compliance tests. Additionally, the transmitted signal can be introduced via a cable connection to the receiver's RF down-converters (i.e., no channel should be used at this initial design stage) and after passing from the ADC stage at the receiver's acquisition boards, it can be retrieved using the FPGA devices and dedicated external memories of the baseband signal processing boards. The captured data constitute realistic test vectors that can be used for the development of the MATLAB model of the receiver, whereas the whole testing procedure permits a refinement of the initial transmitter model (see points IV and V). The testing setup described before could also include specialized equipment that add realistic signal impairments (e.g., real-time emulation of a selected channel, addition of noise or of Carrier Frequency Offset - CFO). However, such operating conditions make unreliable the capturing of test-vectors until the digital front-end of the receiver is developed and tested at the target FPGA board. III *Basic receiver modelling*: The next step is the modelling of the signal processing algorithms at the receiver side. As in the case of the transmitter, the ideal MATLAB model of the receiver uses floating-point logic and does not have any design limitations in terms of processing and memory resources. The functional testing of the complete system is conducted by running a MATLAB simulation of the transmitter and receiver models

MATLAB as a Design and Veri cation Tool for the Hardware Prototyping of Wireless Communication Systems 195

II *Hardware-validation of the baseband transmitter model*: The output of the MATLAB model has two vectorial components, namely the in-phase and quadrature (I/Q). By writing the I and Q outputs in a MATLAB file (i.e., with file extension .mat), it is possible to make a direct hardware validation of the baseband transmitter model. As it was previously described, this is made feasible considering that numerous modern VSG instruments1, provide the necessary API to download such files to an internal memory of the instruments. The latter with the help of an arbitrary waveform generator provides the real-time baseband digital I/Q signals, which then pass from the required DACs and RF conversion stages to produce the desired signal at the selected RF band. This is an indicative test and verification flow where MATLAB

<sup>1</sup> The described functionality is available, for instance, on the VSGs provided by Agilent (*http://www.agilent.com*) or Rode & Schwarz (*http://www.rohde-schwarz.com)*. Further information on other hardware manufacturers supporting MATLAB communication may be found in *http://www.mathworks.com/products/instrument/hardware*.

**Figure 2.** Proposed design, implementation and validation methodology

8 Will-be-set-by-IN-TECH

Once the baseline system-model is designed and validated, the proposed methodology can

This section gives the details of the proposed design methodology, which is depicted in Fig.

I *Basic transmitter modelling*: The first vital requirement for the design of any wireless communication system is the definition of the transmitted signal. The modelling of the transmitted signal is in most cases bound to the specifications of a wireless communication standard, which indicatively includes the OFDM parameters, the duplexing mode, the format and length of the frame, the number, value and location of the pilot tones, the guard-band size, the inter-carrier spacing, the available bandwidth sizes and the RF operating bands. At this initial stage the model of the transmitted signal is based on certain ideal conditions i.e., using floating-point logic, assuming unlimited processing resources during design-time and not accounting for signal-impairments (e.g.,

II *Hardware-validation of the baseband transmitter model*: The output of the MATLAB model has two vectorial components, namely the in-phase and quadrature (I/Q). By writing the I and Q outputs in a MATLAB file (i.e., with file extension .mat), it is possible to make a direct hardware validation of the baseband transmitter model. As it was previously described, this is made feasible considering that numerous modern VSG instruments1, provide the necessary API to download such files to an internal memory of the instruments. The latter with the help of an arbitrary waveform generator provides the real-time baseband digital I/Q signals, which then pass from the required DACs and RF conversion stages to produce the desired signal at the selected RF band. This is an indicative test and verification flow where MATLAB

<sup>1</sup> The described functionality is available, for instance, on the VSGs provided by Agilent (*http://www.agilent.com*) or Rode & Schwarz (*http://www.rohde-schwarz.com)*. Further information on other hardware manufacturers supporting

MATLAB communication may be found in *http://www.mathworks.com/products/instrument/hardware*.

adjust the granularity of the system by accommodating more advanced features.

**Figure 1.** Multi-stage testing strategy

**2.2. Proposed methodology**

channel effects, noise).

2.

is directly interfaced with advanced instrumentation to produce a real-time signal. This signal can be then processed by specific testing hardware (e.g., signal analysers, digital oscilloscopes), which communicate with proprietary third-party software in order to perform standard-compliance tests. Additionally, the transmitted signal can be introduced via a cable connection to the receiver's RF down-converters (i.e., no channel should be used at this initial design stage) and after passing from the ADC stage at the receiver's acquisition boards, it can be retrieved using the FPGA devices and dedicated external memories of the baseband signal processing boards. The captured data constitute realistic test vectors that can be used for the development of the MATLAB model of the receiver, whereas the whole testing procedure permits a refinement of the initial transmitter model (see points IV and V). The testing setup described before could also include specialized equipment that add realistic signal impairments (e.g., real-time emulation of a selected channel, addition of noise or of Carrier Frequency Offset - CFO). However, such operating conditions make unreliable the capturing of test-vectors until the digital front-end of the receiver is developed and tested at the target FPGA board.

III *Basic receiver modelling*: The next step is the modelling of the signal processing algorithms at the receiver side. As in the case of the transmitter, the ideal MATLAB model of the receiver uses floating-point logic and does not have any design limitations in terms of processing and memory resources. The functional testing of the complete system is conducted by running a MATLAB simulation of the transmitter and receiver models

#### 10 Will-be-set-by-IN-TECH 196 MATLAB – A Fundamental Tool for Scienti c Computing and Engineering Applications – Volume 2 MATLAB as a Design and Verication Tool for the Hardware Prototyping of Wireless Communication Systems <sup>11</sup>

(i.e., ideal baseband-to-baseband signal). This could be extended by using the test vectors captured in the previous step (i.e., hardware-validated MATLAB model of the transmitter). Although the design is still not constrained by the limitations of the entire hardware processing platform, the performance of different algorithms could be studied, including those whose computational complexity makes their real-time prototyping challenging. The designer has therefore the opportunity to estimate the ideal performance of the overall system.

• *Translation to fixed-point arithmetic*: the FPGA-based prototyping of wireless communication systems implies the use of fixed-point logic at baseband. This is a significant design constraint that has to be evaluated considering that MATLAB modelling is based by default on floating point arithmetic. In general terms the floating-point operations dramatically increase the FPGA logic utilization and result in lower clock speeds and longer pipelined structures when compared to fixed-point logic2. The designers are responsible for mapping the MATLAB algorithms to an HDL-based fixed-point logic, which in fact is a demanding and non-trivial task. The latter implies that all internal processing stages of the transmitter and receiver (both in MATLAB-space and HDL-design space) have to be appropriately simulated to tune them at an optimum fixed-point dynamic range, applying numerous truncation and scaling steps to achieve the best arithmetic precision. Additionally, each of the implemented HDL blocks has to be co-tested with the equivalent portion of the floating point Matlab model to ensure that the system performance is not compromised (see point VI). A very handy modification of the MATLAB model that assists the comparison with the equivalent RTL code is to apply quantization at the outputs of selected processing blocks that represent functional partitions of the design.

MATLAB as a Design and Veri cation Tool for the Hardware Prototyping of Wireless Communication Systems 197

• *Hardware constraints and specifications awareness*: the functionality of the MATLAB model of the transmitter and receiver can be further adapted to account for hardware-introduced constraints, brining it more close to real-life testing conditions. For instance, the MATLAB model can be adjusted to the Dynamic Range (DR) of the DAC/ADC circuitry of the target boards. The system DR depends on the modulation scheme, the modelled signal-impairments and the DAC/ADC specifications (i.e., number of bits of the produced samples and applicable amplifier gains). Additionally, a number of pre-compiled HDL IP cores used in the prototyping stage of FPGA-based DSP algorithms (e.g., FFT, Digital Down Converter - DDC, pipelined divider) are offering a limited range of input/output data-width options. This results in further quantization analysis, assuming that the reception of samples is scaled within a certain dynamic range. The on-board FPGA implementation entails a series of other design limitation, which are hard to be emulated at MATLAB space. Indicative examples of such hardware implementation features include the interfacing of the FPGA design with high-speed buses and the latencies introduced by several FPGA IP cores; the latter increase the intermediate storage requirements and add more complexity to the

• *Satisfy a trade-off between numerical complexity and system performance*: The system designer has to discover the optimal achieved performance of the designed system (i.e., baseband, RF and channel propagation stages) through a recursive process, taking into account the processing and memory resources of the target FPGA device, the additional inherent constraints of the hardware platform and the minimum required yield of the system. The latter is subject to specific prerequisites related to numeric precision, throughput and compliance with certain performance metrics (e.g., Bit Error Rate - BER, average data rate). This means that the MATLAB model will be adjusted until the designer achieves the desired performance, which eventually will

<sup>2</sup> It is useful to mention that specific floating-point arithmetic libraries, Intellectual Property (IP) cores, embedded microprocessors and other dedicated processing components can be used in FPGA devices to serve the needs of

This quantization process emulates the fixed-point logic.

allow him to pass to the next design stage of RTL coding.

particular applications that require this type of arithmetic operations [15, 16]

control plane.

	- *RTL-implementation awareness*: it is widely known that not all MATLAB structures or functions are implementable in an FPGA. Even if equivalent HDL constructs exist, they are used during simulation time but do not serve for logic synthesis (e.g., a for-loop construct with undefined number of iterations). Moreover, MATLAB includes several pre-compiled DSP functions (e.g., Fast Fourier Transform - FFT) and provides abstract arithmetic operators (i.e., the user calls the same operator independently of the type of the operands). For instance, the '∗' operator provides the multiplication for integer, real or complex numbers, arrays and matrices. Although these MATLAB features provide a powerful workbench for users, it is common quite a mistake to underestimate the computational complexity and the internal arithmetic calculations of such operations, especially when they are meant to be mapped on a real-time RTL-based implementation (see example 2.1). It is therefore a key design requirement to evaluate the implementability and arithmetic complexity of the algorithms comprising the target system, in relation to the maximum processing and memory capacity of the target FPGA device. This usually gives a first idea of which design partitioning strategy can be followed (e.g., using various FPGA devices or a combination of FPGA devices and DSP microprocessors). The importance of this evaluation stage for the mapping of the MATLAB model to RTL code is crucial and may result in selecting different algorithms and lightweight versions of pre-compiled arithmetic functions. Another important task is to estimate the storage and intercommunication needs. This is made feasible by including in the MATLAB model a high-level representation of the memory and control planes.

196 MATLAB – A Fundamental Tool for Scienti c Computing and Engineering Applications – Volume 2 MATLAB as a Design and Verication Tool for the Hardware Prototyping of Wireless Communication Systems <sup>11</sup> MATLAB as a Design and Veri cation Tool for the Hardware Prototyping of Wireless Communication Systems 197

10 Will-be-set-by-IN-TECH

IV *Signal impairment modelling*: After finishing the ideal MATLAB model of the entire system, it is time to start adding real-world impairments. The latter are inherent features of hardware components and effects applied to analogue signals when propagating in physical mediums. This implies modifications of the originally designed MATLAB model to meet new operating conditions. The most indicative impairments that need to be modelled in MATLAB is the transmission over a defined channel, the addition of noise and CFO, the coupling of the baseband signal with the Local Oscillator (LO) and the introduction of a Direct Current (DC) level by the hardware platform. As a result, it is obtained a model of the transmitted signal that is significantly closer to real-world conditions. The signal processing algorithms at the receiver have to be modified and

V *System model refinement*: Additional modifications are required to the MATLAB baseband model of the system, before starting the challenging stage of mapping it to RTL code. The MATLAB models of the transmitter and receiver have to account for the the hardware platform specifications (i.e., ADC/DAC features, internal buses, I/Os, available FPGA-resources - including embedded memory and specialized digital signal processing - DSP - blocks, etc.). Thus, the signal processing algorithms must be refined as

• *RTL-implementation awareness*: it is widely known that not all MATLAB structures or functions are implementable in an FPGA. Even if equivalent HDL constructs exist, they are used during simulation time but do not serve for logic synthesis (e.g., a for-loop construct with undefined number of iterations). Moreover, MATLAB includes several pre-compiled DSP functions (e.g., Fast Fourier Transform - FFT) and provides abstract arithmetic operators (i.e., the user calls the same operator independently of the type of the operands). For instance, the '∗' operator provides the multiplication for integer, real or complex numbers, arrays and matrices. Although these MATLAB features provide a powerful workbench for users, it is common quite a mistake to underestimate the computational complexity and the internal arithmetic calculations of such operations, especially when they are meant to be mapped on a real-time RTL-based implementation (see example 2.1). It is therefore a key design requirement to evaluate the implementability and arithmetic complexity of the algorithms comprising the target system, in relation to the maximum processing and memory capacity of the target FPGA device. This usually gives a first idea of which design partitioning strategy can be followed (e.g., using various FPGA devices or a combination of FPGA devices and DSP microprocessors). The importance of this evaluation stage for the mapping of the MATLAB model to RTL code is crucial and may result in selecting different algorithms and lightweight versions of pre-compiled arithmetic functions. Another important task is to estimate the storage and intercommunication needs. This is made feasible by including in the MATLAB

model a high-level representation of the memory and control planes.

of the overall system.

follows:

upgraded to account for these signal impairments.

(i.e., ideal baseband-to-baseband signal). This could be extended by using the test vectors captured in the previous step (i.e., hardware-validated MATLAB model of the transmitter). Although the design is still not constrained by the limitations of the entire hardware processing platform, the performance of different algorithms could be studied, including those whose computational complexity makes their real-time prototyping challenging. The designer has therefore the opportunity to estimate the ideal performance


<sup>2</sup> It is useful to mention that specific floating-point arithmetic libraries, Intellectual Property (IP) cores, embedded microprocessors and other dedicated processing components can be used in FPGA devices to serve the needs of particular applications that require this type of arithmetic operations [15, 16]

**Example 2.1**: let's consider the simple multiplication of two complex numbers, *a* = 2.5 + 3.2*i* and *b* = 1.7 − 4.5*i*. In MATLAB a user would simply type 'c=a \* b' abstracting away the underlying calculation. However, when considering a RTL design many other aspects must be considered.

VI *MATLAB/HDL co-simulation*: Each portion of the implemented HDL code that forms a functional component of the system has to be co-simulated with the equivalent partition of the MATLAB model. This allows to assess both the functional correctness and the achieved performance. As already mentioned before, there are several ways to use the co-simulation methodology. An indicative example is when part of the system simulation resides in MATLAB space, whereas another portion is hosted in a third party HDL design tool; the output of the MATLAB model can be quantized and saved to a file, which can be inserted to the HDL-based simulation. The results produced by the HDL simulation can also be quantized and written to a file, which is fed back to MATLAB. This is a very useful way to verify the functionality and inter-working of the system that is implemented in different simulation domains. In addition, it also enables the evaluation of the precision achieved by the HDL model by comparing its performance with the non-quantized results produced by the MATLAB model. It is important to highlight the vital role of co-simulations for selecting an optimum quantization that satisfies a trade-off between precision and computational complexity. Finally, the MATLAB/HDL co-simulations provide the best means to evaluate and test HDL IP cores and common signal processing operations (e.g., optimizing the trade-off between implementation complexity and result

MATLAB as a Design and Veri cation Tool for the Hardware Prototyping of Wireless Communication Systems 199

precision requires the calculation and truncation of the produced outputs).

metrics (i.e., mean value over thousands of data samples).

hardware platform which is already thoroughly studied and characterized.

**3. A practical case study**

table 1.

VII *Data post-processing*: Data can be captured at different baseband processing stages once the system (or parts of it) is implemented in a target FPGA board. This data can be inserted in MATLAB after using the proper quantization to enable the off-line calculation of the required performance metrics (e.g., BER, Signal-to-Noise Ratio - SNR, Error Vector Magnitude - EVM). MATLAB can also be used to automate the post-processing of the captured data-frames, and provide a reliable calculation of the desired performance

The end of a major design cycle is reached when the performance of the RTL prototype is finally validated on real-time hardware and does not require any further modifications. This gives the opportunity to the system designer to introduce additional features by iterating over the previously described methodology. The proposed incremental design approach implies a relative low effort to augment the features of a working prototype. This is mainly due to the fact that a modular and reusable code is already available, while at the same time the critical parts of the design and the system bottlenecks are well defined. The same applies to the

This final section presents a practical case study of the manifold contribution of MATLAB throughout the entire design, development and prototyping stages of a real-time mobile WiMAX system [3, 4]. The use-cases focus on the Single Input Single Output (SISO) configuration of the system [17] that features one antenna at the transmitter and receiver sides respectively. Taking as an exemplar basis the development of the SISO system, the presented incremental design methodology can be reused to develop the MIMO system, which however is not covered in this chapter. The main specifications of the target system are summarized in

The GEDOMIS® testbed (see Fig. 3), was used to prototype and validate the system described in this chapter. GEDOMIS® features multiple APIs, dedicated signal analysis software tools

First, let us assume a dynamic range of input samples that satisfy the (−8, 8) margin. Also let us consider a binary representation of samples with 16 bits, where 4 bits are used to represent the sign and the integer part and the remaining bits are used to represent the fractional part. The I and Q components of the complex numbers have to be represented separately. This can be modelled in MATLAB using the quantizer, num2bin and bin2num functions of the fixed-point toolbox:

q = quantizer([16 12]); I\_a = num2bin(q,real(a)); Q\_a = num2bin(q,imag(a)); I\_b = num2bin(q,real(b)); Q\_b = num2bin(q,imag(b));

Furthermore, the complex multiplication has to be broken down to basic operations. In MATLAB this can be done as follows:

```
I_c = bin2num(q,I_a)*bin2num(q,I_b) - bin2num(q,Q_a)*
bin2num(q,Q_b);
Q_c = bin2num(q,Q_a)*bin2num(q,I_b) + bin2num(q,I_a)*
bin2num(q,Q_b);
```
A first approximation of the error introduced by quantization can be measured with a simple subtraction: quant\_loss\_I = real(c) - I\_c; quant\_loss\_Q = imag(c) - Q\_c;

Moreover, each arithmetic operation in RTL coding results in a bit-width grow: e.g., the multiplication of two *N*-bit operands results in *2N* bits and the addition of two *N*-bit operands results in *N+1* bits. Therefore, RTL coding implies that each of the previously described intermediate operations has to be considered separately:

intermediate\_op1 = I\_a \* I\_b, results in 32 bits intermediate\_op2 = Q\_a \* Q\_b, results in 32 bits intermediate\_op3 = intermediate\_op1 - intermediate\_op2, results in 33 bits

To sum up, a quantization adjustment (i.e., bit-alignment in case the bit-width of the different operands grows differently) and/or a data-truncation will be required between the different intermediate calculations to limit the overall computational complexity. Additionally, in order to achieve a better timing performance of the FPGA design, the intermediate calculations of complex operations are placed in different clocked-processes: i.e., the calculation of 'intermediate\_op3' 'intermediate\_op1' and 'intermediate\_op2' would be placed in a different clocked process. Therefore, a latency of one clock cycle would be introduced at each intermediate calculation. Although the bit-width growth and the introduced latencies are not modelled in MATLAB, it is highly recommended to analyse such aspects in order to assess the system's complexity. A complex calculation may result in a change of the quantization, which in turn will require further modifications of the MATLAB model.

198 MATLAB – A Fundamental Tool for Scienti c Computing and Engineering Applications – Volume 2 MATLAB as a Design and Verication Tool for the Hardware Prototyping of Wireless Communication Systems <sup>13</sup> MATLAB as a Design and Veri cation Tool for the Hardware Prototyping of Wireless Communication Systems 199


The end of a major design cycle is reached when the performance of the RTL prototype is finally validated on real-time hardware and does not require any further modifications. This gives the opportunity to the system designer to introduce additional features by iterating over the previously described methodology. The proposed incremental design approach implies a relative low effort to augment the features of a working prototype. This is mainly due to the fact that a modular and reusable code is already available, while at the same time the critical parts of the design and the system bottlenecks are well defined. The same applies to the hardware platform which is already thoroughly studied and characterized.

## **3. A practical case study**

12 Will-be-set-by-IN-TECH

aspects must be considered.

q = quantizer([16 12]);

bin2num(q,Q\_b);

bin2num(q,Q\_b);

imag(c) - Q\_c;

bits

MATLAB this can be done as follows:

bin2num functions of the fixed-point toolbox:

I\_a = num2bin(q,real(a)); Q\_a = num2bin(q,imag(a)); I\_b = num2bin(q,real(b)); Q\_b = num2bin(q,imag(b));

I\_c = bin2num(q,I\_a)\*bin2num(q,I\_b) - bin2num(q,Q\_a)\*

Q\_c = bin2num(q,Q\_a)\*bin2num(q,I\_b) + bin2num(q,I\_a)\*

described intermediate operations has to be considered separately:

intermediate\_op1 = I\_a \* I\_b, results in 32 bits intermediate\_op2 = Q\_a \* Q\_b, results in 32 bits

require further modifications of the MATLAB model.

**Example 2.1**: let's consider the simple multiplication of two complex numbers, *a* = 2.5 + 3.2*i* and *b* = 1.7 − 4.5*i*. In MATLAB a user would simply type 'c=a \* b' abstracting away the underlying calculation. However, when considering a RTL design many other

First, let us assume a dynamic range of input samples that satisfy the (−8, 8) margin. Also let us consider a binary representation of samples with 16 bits, where 4 bits are used to represent the sign and the integer part and the remaining bits are used to represent the fractional part. The I and Q components of the complex numbers have to be represented separately. This can be modelled in MATLAB using the quantizer, num2bin and

Furthermore, the complex multiplication has to be broken down to basic operations. In

A first approximation of the error introduced by quantization can be measured with a simple subtraction: quant\_loss\_I = real(c) - I\_c; quant\_loss\_Q =

Moreover, each arithmetic operation in RTL coding results in a bit-width grow: e.g., the multiplication of two *N*-bit operands results in *2N* bits and the addition of two *N*-bit operands results in *N+1* bits. Therefore, RTL coding implies that each of the previously

intermediate\_op3 = intermediate\_op1 - intermediate\_op2, results in 33

To sum up, a quantization adjustment (i.e., bit-alignment in case the bit-width of the different operands grows differently) and/or a data-truncation will be required between the different intermediate calculations to limit the overall computational complexity. Additionally, in order to achieve a better timing performance of the FPGA design, the intermediate calculations of complex operations are placed in different clocked-processes: i.e., the calculation of 'intermediate\_op3' 'intermediate\_op1' and 'intermediate\_op2' would be placed in a different clocked process. Therefore, a latency of one clock cycle would be introduced at each intermediate calculation. Although the bit-width growth and the introduced latencies are not modelled in MATLAB, it is highly recommended to analyse such aspects in order to assess the system's complexity. A complex calculation may result in a change of the quantization, which in turn will

This final section presents a practical case study of the manifold contribution of MATLAB throughout the entire design, development and prototyping stages of a real-time mobile WiMAX system [3, 4]. The use-cases focus on the Single Input Single Output (SISO) configuration of the system [17] that features one antenna at the transmitter and receiver sides respectively. Taking as an exemplar basis the development of the SISO system, the presented incremental design methodology can be reused to develop the MIMO system, which however is not covered in this chapter. The main specifications of the target system are summarized in table 1.

The GEDOMIS® testbed (see Fig. 3), was used to prototype and validate the system described in this chapter. GEDOMIS® features multiple APIs, dedicated signal analysis software tools


**Figure 4.** Basic architecture of the SISO transmitter and receiver systems.

MATLAB usage in each prototyping stage.

**3.1. PHY-layer prototype of a single antenna mobile WiMAX transceiver**

Fig. 4 shows a simplified functional block diagram of the SISO mobile WiMAX system. Taking as a reference the design methodology presented before, this section gives an example of the

MATLAB as a Design and Veri cation Tool for the Hardware Prototyping of Wireless Communication Systems 201

I *Basic transmitter modelling*: The first task is the accurate definition of the OFDM-based frame structure. Thus, it has to be identified the basic function of the different frequency subcarriers within each OFDM symbol. In our case, the frame is structured according to the Partial Used Subcarrier (PUSC) and the AMC subcarrier permutation schemes, which are defined in the mobile WiMAX standard [19]. The main characteristics of both OFDM symbol structures are summarized in table 2. Example 3.1 shows the MATLAB-modelling of the processing block responsible for inserting the pilot subcarriers, the DC and the guard bands, according to the mobile WiMAX specifications. The additional subcarrier organization and permutation operations required by the WiMAX standard can be easily designed in MATLAB-space. Finally, the use of a standard inverse FFT function provides

the ideal I/Q baseband outputs of the transmitter (i.e., floating-point values).

Scheme Parameter (per OFDM symbol) Value PUSC Data subcarriers 1440

> Pilot subcarriers 240 Null subcarriers 368 Clusters 120 Subcarriers per cluster 14 Subchannels 60

Pilot subcarriers 192 Null subcarriers 320 Bands 48 Bins per band 4 Subcarriers per bin 9 Subchannels 32

Data subcarriers per subchannel 24 AMC Data subcarriers 1536

Data subcarriers per subchannel 48

**Table 2.** Principal parameters of the PUSC and AMC permutation schemes.

14 Will-be-set-by-IN-TECH 200 MATLAB – A Fundamental Tool for Scienti c Computing and Engineering Applications – Volume 2 MATLAB as a Design and Verication Tool for the Hardware Prototyping of Wireless Communication Systems <sup>15</sup>

**Table 1.** Basic OFDM and PHY-layer specifications of the described system.

and a heterogeneous hardware setup. The latter comprises signal generation equipment, multi-channel signal conversion boards, a real-time radio channel emulator and FPGA-based baseband signal processing boards [18]. The examples detailed in the remaining of the chapter do follow the previously proposed multi-stage testing strategy (see Fig. 1) and do not always require the use of the full set-up of this testbed.

**Figure 3.** The GEDOMIS® testbed setup.

**Figure 4.** Basic architecture of the SISO transmitter and receiver systems.

14 Will-be-set-by-IN-TECH

Parameter Value Wireless telecommunication standard IEEE 802.16e-2005 Antenna schemes: SISO, SIMO, MIMO 1x1, 1x2, 2x2

> RF band (GHz) 2.595 IF (MHz) 156.8

Cyclic prefix (samples) 512 (1/4 of the symbol) Modulation type QPSK Duplex mode TDD FFT size 2048

Channel bandwidth (MHz) 20 Baseband sampling frequency (MHz) 22.4 ADC sampling frequency (MHz) 89.6

OFDM symbols per frame 48 Supported permutation schemes PUSC and AMC (DL) Diversity scheme (2x2 MIMO) Matrix-A (Alamouti)

and a heterogeneous hardware setup. The latter comprises signal generation equipment, multi-channel signal conversion boards, a real-time radio channel emulator and FPGA-based baseband signal processing boards [18]. The examples detailed in the remaining of the chapter do follow the previously proposed multi-stage testing strategy (see Fig. 1) and do not always

**Table 1.** Basic OFDM and PHY-layer specifications of the described system.

require the use of the full set-up of this testbed.

**Figure 3.** The GEDOMIS® testbed setup.

## **3.1. PHY-layer prototype of a single antenna mobile WiMAX transceiver**

Fig. 4 shows a simplified functional block diagram of the SISO mobile WiMAX system. Taking as a reference the design methodology presented before, this section gives an example of the MATLAB usage in each prototyping stage.

I *Basic transmitter modelling*: The first task is the accurate definition of the OFDM-based frame structure. Thus, it has to be identified the basic function of the different frequency subcarriers within each OFDM symbol. In our case, the frame is structured according to the Partial Used Subcarrier (PUSC) and the AMC subcarrier permutation schemes, which are defined in the mobile WiMAX standard [19]. The main characteristics of both OFDM symbol structures are summarized in table 2. Example 3.1 shows the MATLAB-modelling of the processing block responsible for inserting the pilot subcarriers, the DC and the guard bands, according to the mobile WiMAX specifications. The additional subcarrier organization and permutation operations required by the WiMAX standard can be easily designed in MATLAB-space. Finally, the use of a standard inverse FFT function provides the ideal I/Q baseband outputs of the transmitter (i.e., floating-point values).


**Table 2.** Principal parameters of the PUSC and AMC permutation schemes.

16 Will-be-set-by-IN-TECH 202 MATLAB – A Fundamental Tool for Scienti c Computing and Engineering Applications – Volume 2 MATLAB as a Design and Verication Tool for the Hardware Prototyping of Wireless Communication Systems <sup>17</sup>

```
Example 3.1: Fig. 5 shows the pilot distribution in the PUSC permutation scheme,
described in the mobile WiMAX standard.
Figure 5. Location of the pilot symbols in the PUSC permutation scheme.
Taking into account this pilot distribution, the following MATLAB code represents the
insertion of the pilot tones in a PUSC-structured OFDM frame:
%The PUSC-formatted OFDM symbols (i.e., outputs of the block in
charge of the IEEE 802.16e-related operations) are loaded in the
variable 'mWiMAX_PUSC_data'.
load('mWiMAX_PUSC_data')
PUSC_zone_length=30;
%There will be 240 pilots per OFDM symbol.
pilot=4/3+j*0; %Pilot value defined by the WiMAX standard.
%Each PUSC OFDM symbol contains 120 clusters of 12 contiguous
data subcarriers, where 2 pilots will be added.
evenSymb=1;
data_and_pilots=[];
for symb_index=0:PUSC_zone_length-1
symb_offset=symb_index*120*12;
ofdm_symbol=mWiMAX_PUSC_data(symb_offset+1:symb_offset+120*12);
cluster=[];
pilotCluster=[];
for cluster_index=0:119
subc_offset=cluster_index*12+1;
cluster=ofdm_symbol(subc_offset:subc_offset+11);
if evenSymb
pilotClus=[cluster(1:4) pilot cluster(5:7) pilot cluster(8:12)];
else
pilotClus=[pilot cluster(1:11) pilot cluster(12)];
end
ofdm_symbol=[ofdm_symbol pilotClus];
end
data_and_pilots=[data_and_pilots ofdm_symbol];
evenSymb=mod(evenSymb+1,2);
end
%A total of 368 null subcarriers are inserted.
ofdm_symbol=[zeros(1,184) ofdm_symbol(1:840) 0
ofdm_symbol(841:1680) zeros(1,183)];
```
II *Hardware-validation of the baseband transmitter model*: As already described before, the I/Q output vectors of the MATLAB model of the ideal transmitter can be stored (separately) in a MATLAB file. The latter can be downloaded to an internal memory of a VSG instrument (as described in Example 3.2). The VSG can be programmed to use these vectors in order to produce a real-time RF signal. This is made feasible by exploiting its embedded arbitrary waveform generator, DAC devices and RF upconversion circuitry. The validation of this signal using third party software tools and hardware instruments is very important, considering that several signal impairments and hardware constraints

MATLAB as a Design and Veri cation Tool for the Hardware Prototyping of Wireless Communication Systems 203

**Example 3.2**: The first step for the prototyping and testing of the ideal transmitter MATLAB model using off-line testbed principles, requires the storage of the output I/Q

%The frequency-domain data produced by the baseband transmitter (i.e., before the IFFT) is loaded in the variable 'BB\_data'.

can be identified during early design stages.

%A short silence period precedes each frame.

%Conversion from frequency to time domain.

time\_ofdm\_symbol(513:end)=ifft(BB\_ofdm\_symbol);

time\_ofdm\_symbol=zeros(512+2048,1);

custom\_Tx\_I=real(transmitted\_signal); custom\_Tx\_Q=imag(transmitted\_signal);

symbols of the OFDMA symbol).

%I/Q component extraction.

'custom\_Tx\_frame.mat' file.

transmitted\_signal=zeros(silence\_period\_length,1);

%The frame is composed by a preamble and 48 OFDM symbols.

%Inclusion of the CP (i.e, the CP is a copy of the last 512

time\_ofdm\_symbol(1:preamble\_length)=time\_ofdm\_symbol(1537:end); transmitted\_signal=[transmitted\_signal; time\_ofdm\_symbol];

%Creation of the 'custom\_Tx\_frame.mat' file to stimulate the VSG.

Fig. 6, 7 and 8 show the configuration of the Agilent Signal Studio Toolkit. The latter is the software programming interface used to configure an Agilent E4438C VSG with the

save('custom\_Tx\_frame.mat', 'custom\_Tx\_I', 'custom\_Tx\_Q');

BB\_ofdm\_symbol=BB\_data(2048\*(symb\_index-1)+1:(2048\*symb\_index));

components in two files.

load('BB\_data')

silence\_length=2560\*5;

for symb\_index = 1:49

preamble\_length=512;

end

202 MATLAB – A Fundamental Tool for Scienti c Computing and Engineering Applications – Volume 2 MATLAB as a Design and Verication Tool for the Hardware Prototyping of Wireless Communication Systems <sup>17</sup> MATLAB as a Design and Veri cation Tool for the Hardware Prototyping of Wireless Communication Systems 203

16 Will-be-set-by-IN-TECH

**Figure 5.** Location of the pilot symbols in the PUSC permutation scheme.

insertion of the pilot tones in a PUSC-structured OFDM frame:

%There will be 240 pilots per OFDM symbol.

for symb\_index=0:PUSC\_zone\_length-1 symb\_offset=symb\_index\*120\*12;

data subcarriers, where 2 pilots will be added.

cluster=ofdm\_symbol(subc\_offset:subc\_offset+11);

pilotClus=[pilot cluster(1:11) pilot cluster(12)];

data\_and\_pilots=[data\_and\_pilots ofdm\_symbol];

%A total of 368 null subcarriers are inserted. ofdm\_symbol=[zeros(1,184) ofdm\_symbol(1:840) 0

described in the mobile WiMAX standard.

variable 'mWiMAX\_PUSC\_data'. load('mWiMAX\_PUSC\_data') PUSC\_zone\_length=30;

evenSymb=1;

cluster=[]; pilotCluster=[];

if evenSymb

else

end

end

end

data\_and\_pilots=[];

for cluster\_index=0:119

subc\_offset=cluster\_index\*12+1;

ofdm\_symbol=[ofdm\_symbol pilotClus];

ofdm\_symbol(841:1680) zeros(1,183)];

evenSymb=mod(evenSymb+1,2);

**Example 3.1**: Fig. 5 shows the pilot distribution in the PUSC permutation scheme,

Taking into account this pilot distribution, the following MATLAB code represents the

%The PUSC-formatted OFDM symbols (i.e., outputs of the block in charge of the IEEE 802.16e-related operations) are loaded in the

pilot=4/3+j\*0; %Pilot value defined by the WiMAX standard.

%Each PUSC OFDM symbol contains 120 clusters of 12 contiguous

ofdm\_symbol=mWiMAX\_PUSC\_data(symb\_offset+1:symb\_offset+120\*12);

pilotClus=[cluster(1:4) pilot cluster(5:7) pilot cluster(8:12)];

II *Hardware-validation of the baseband transmitter model*: As already described before, the I/Q output vectors of the MATLAB model of the ideal transmitter can be stored (separately) in a MATLAB file. The latter can be downloaded to an internal memory of a VSG instrument (as described in Example 3.2). The VSG can be programmed to use these vectors in order to produce a real-time RF signal. This is made feasible by exploiting its embedded arbitrary waveform generator, DAC devices and RF upconversion circuitry. The validation of this signal using third party software tools and hardware instruments is very important, considering that several signal impairments and hardware constraints can be identified during early design stages.

**Example 3.2**: The first step for the prototyping and testing of the ideal transmitter MATLAB model using off-line testbed principles, requires the storage of the output I/Q components in two files.

```
%The frequency-domain data produced by the baseband transmitter
(i.e., before the IFFT) is loaded in the variable 'BB_data'.
load('BB_data')
%A short silence period precedes each frame.
silence_length=2560*5;
transmitted_signal=zeros(silence_period_length,1);
%The frame is composed by a preamble and 48 OFDM symbols.
for symb_index = 1:49
BB_ofdm_symbol=BB_data(2048*(symb_index-1)+1:(2048*symb_index));
%Conversion from frequency to time domain.
time_ofdm_symbol=zeros(512+2048,1);
time_ofdm_symbol(513:end)=ifft(BB_ofdm_symbol);
%Inclusion of the CP (i.e, the CP is a copy of the last 512
symbols of the OFDMA symbol).
```

```
preamble_length=512;
time_ofdm_symbol(1:preamble_length)=time_ofdm_symbol(1537:end);
transmitted_signal=[transmitted_signal; time_ofdm_symbol];
end
```

```
%I/Q component extraction.
custom_Tx_I=real(transmitted_signal);
custom_Tx_Q=imag(transmitted_signal);
```

```
%Creation of the 'custom_Tx_frame.mat' file to stimulate the VSG.
save('custom_Tx_frame.mat', 'custom_Tx_I', 'custom_Tx_Q');
```
Fig. 6, 7 and 8 show the configuration of the Agilent Signal Studio Toolkit. The latter is the software programming interface used to configure an Agilent E4438C VSG with the 'custom\_Tx\_frame.mat' file.

18 Will-be-set-by-IN-TECH 204 MATLAB – A Fundamental Tool for Scienti c Computing and Engineering Applications – Volume 2 MATLAB as a Design and Verication Tool for the Hardware Prototyping of Wireless Communication Systems <sup>19</sup>

**Figure 9.** As it can be observed, the deviation between the ideal and the estimated channel is notable when using a linear interpolation, which accounts only for the two closest pilots for each subcarrier. On the contrary, the obtained results are better when applying a quadratic interpolation approach which

Using a RF-to-RF cable connection data can be captured at the receiver baseband boards. This provides realistic test vectors that will be later used to design and debug the

MATLAB as a Design and Veri cation Tool for the Hardware Prototyping of Wireless Communication Systems 205

III *Basic receiver modelling*: The first step is to model the ideal received signal. In this sense, it is assumed that the received signal is identical with the transmitted one, without making use of quantizations or accounting for signal-impairments. In other words, an ideal

The modelling of the receiver is based on WiMAX-defined processing functions (e.g., permutation of the subcarriers) and common signal processing operations (e.g., FFT). MATLAB provides the ideal modelling environment to compare the performance tradeoffs of different signal processing algorithms. As an example, Fig. 9 shows the comparison of a linear and a quadratic interpolation for a pilot-based channel estimation algorithm. This type of algorithm design and benchmarking allows the designer to make early decisions tailored for the specifications of the target hardware platform. Nonetheless, the validation of the critical parts of the receiver, such as the synchronization or the channel estimation requires a signal model that is closer to real-world conditions (i.e., accounting for impairments and hardware constraints). Once this modified version of the received signal is available, the designer is able to make a precise selection of algorithms that are suitable for the anticipated channel conditions and the characteristics

IV *Signal impairment modelling*: Having already modelled the ideal system, the next step is to modify the signal model to include the expected signal impairments. This requires the analysis of the main specifications and performance of the target hardware. In the test-case described herein, certain signal impairments such as the I/Q gain and phase imbalances or LO drifts are ignored because of the performance indicators and specifications of the equipment comprising the GEDOMIS® testbed. It is important however that each designer exhaustively examines the complete set of potential signal impairments and ignore only those that have negligible effects to the received signal. This procedure is subject to generic signal processing and propagation principles, but

*c*(*t*) = *x*˜(*t*), (1)

baseband-to-baseband communication is modelled as follows:

where *x*(*t*) represents the equivalent transmitted baseband signal.

uses three neighbouring pilots in the calculations.

MATLAB model of the receiver.

of the target hardware platform.

**Figure 8.** Agilent Signal Studio Toolkit configuration: loading of the I/Q components of the MATLAB model of the ideal transmitter.

18 Will-be-set-by-IN-TECH

**Figure 6.** Agilent Signal Studio Toolkit configuration: ADC sampling frequency.

**Figure 7.** Agilent Signal Studio Toolkit configuration: RF band.

MATLAB model of the ideal transmitter.

provide a realistic RF signal.

The principal parameters that need to be defined by the user to properly conduct the hardware-validation of the ideal transmitter, are the DAC sampling frequency, the desired RF band and the names of the variables of the MATLAB-generated file containing the I/Q components. The VSG is then able to apply the required IF-to-RF upconversion and

**Figure 8.** Agilent Signal Studio Toolkit configuration: loading of the I/Q components of the

**Figure 9.** As it can be observed, the deviation between the ideal and the estimated channel is notable when using a linear interpolation, which accounts only for the two closest pilots for each subcarrier. On the contrary, the obtained results are better when applying a quadratic interpolation approach which uses three neighbouring pilots in the calculations.

Using a RF-to-RF cable connection data can be captured at the receiver baseband boards. This provides realistic test vectors that will be later used to design and debug the MATLAB model of the receiver.

III *Basic receiver modelling*: The first step is to model the ideal received signal. In this sense, it is assumed that the received signal is identical with the transmitted one, without making use of quantizations or accounting for signal-impairments. In other words, an ideal baseband-to-baseband communication is modelled as follows:

$$
\mathfrak{c}(t) = \mathfrak{x}(t),
\tag{1}
$$

where *x*(*t*) represents the equivalent transmitted baseband signal.

The modelling of the receiver is based on WiMAX-defined processing functions (e.g., permutation of the subcarriers) and common signal processing operations (e.g., FFT). MATLAB provides the ideal modelling environment to compare the performance tradeoffs of different signal processing algorithms. As an example, Fig. 9 shows the comparison of a linear and a quadratic interpolation for a pilot-based channel estimation algorithm. This type of algorithm design and benchmarking allows the designer to make early decisions tailored for the specifications of the target hardware platform. Nonetheless, the validation of the critical parts of the receiver, such as the synchronization or the channel estimation requires a signal model that is closer to real-world conditions (i.e., accounting for impairments and hardware constraints). Once this modified version of the received signal is available, the designer is able to make a precise selection of algorithms that are suitable for the anticipated channel conditions and the characteristics of the target hardware platform.

IV *Signal impairment modelling*: Having already modelled the ideal system, the next step is to modify the signal model to include the expected signal impairments. This requires the analysis of the main specifications and performance of the target hardware. In the test-case described herein, certain signal impairments such as the I/Q gain and phase imbalances or LO drifts are ignored because of the performance indicators and specifications of the equipment comprising the GEDOMIS® testbed. It is important however that each designer exhaustively examines the complete set of potential signal impairments and ignore only those that have negligible effects to the received signal. This procedure is subject to generic signal processing and propagation principles, but also requires a hardware-specific analysis of potential impairments (i.e., different for each testbed). In our case, the resulting refined received signal model at the output of the RF down-converters can be expressed as follows:

$$\mathcal{L}\left(t\right) = \Re\{\mathbf{x}(t) \cdot e^{j2\Pi\left(f\_{IF} + \Delta f\right)t}\} + A \cdot \cos\left(2\Pi\left(f\_{IF} + \Delta f\right)t + \varphi\right) + w(t),\tag{2}$$

where *x*(*t*) represents the useful part of the received baseband signal, *fIF* is the Intermediate Frequency (IF), Δ*f* is the Carrier Frequency Offset (CFO), *A* · *cos*(2Π(*fIF* + Δ*f*)*t* + *ϕ*) represents the unwanted residual carrier located at the center of the useful signal-spectrum (i.e., introduced by the LO coupling at the transmitter) and, finally, *w*(*t*) is the Gaussian noise. The useful part of the received baseband signal can be expressed as:

$$\mathfrak{x}(t) = \mathfrak{x}(t) \star H(t),\tag{3}$$

%Conversion from frequency to time domain.

symbols of the OFDMA symbol - oversampled by 4).

first\_sample=silence\_length+preamble\_length+1;

received\_signal = conv(transmitted\_signal,channel);

%The modelled CFO will be equivalent to a third of the

time\_ofdm\_symbol(2049:end)=ifft\_x4oversamp(BB\_ofdm\_symbol); %Inclusion of the CP (i.e, the CP is a copy of the last 512

time\_ofdm\_symbol(1:preamble\_length)=time\_ofdm\_symbol(8193:end); transmitted\_signal=[transmitted\_signal; time\_ofdm\_symbol];

MATLAB as a Design and Veri cation Tool for the Hardware Prototyping of Wireless Communication Systems 207

%Convolution of the frequency domain signal with the channel and

mean\_power = mean(abs(transmitted\_signal(first\_sample:end)).ˆ2);

received\_signal = received\_signal+sqrt(noise\_power/2)\*(rand\_I +

received\_signal = real(received\_signal.\*exp(j\*2\*pi\*((156.8 + (eps\_freq\*22.4/2048))\*(1:length(received\_signal))'/89.6)));

V *System model refinement*: In order to have a MATLAB model that provides a close match to the prerequisites of RTL coding, further modifications and refinements have to be conducted. This principally involves the emulation of fixed-point arithmetic in specific outputs of the MATLAB model. The trade-off between resulting precision and computational complexity has to be investigated. The more bits used to represent the fixed-point data, the more precision is achieved in the arithmetic operations. Considering that the prototyping target is a high performance real-time wireless communication system, it is required to use additional bits for the representation of signals, which consequently increases the FPGA processing and memory requirements. Different quantizations can be tested to analyse their effect both on independent processing stages, as well as on the overall system performance. An indicative example is when 16-bit words are used for the intermediate calculations of a custom MATLAB FFT function, featuring a radix-2 butterfly structure. This results in an aggregate quantization loss of 87 · 10<sup>−</sup>2. The equivalent loss when using 32-bit words is reduced down to 13 · 10<sup>−</sup>7. By inserting the quantized results to each of the remaining processing stages of the signal processing chain, it can be evaluated the performance-loss of the overall system. Hence, retaking the example mentioned before, the 16-bit quantized outputs of the FFT result in a performance degradation of the channel estimation (i.e., the precision-loss of

time\_ofdm\_symbol=zeros(2048+8192,1);

inclusion of the CFO and the noise.

noise\_power = mean\_power/(10ˆ(SNR/10));

rand\_I=randn(size(received\_signal)); rand\_Q=randn(size(received\_signal));

preamble\_length=512\*4;

intercarrier separation.

eps\_freq=-1/3;

SNR=25;

j\*rand\_Q);

end

where *x*˜(*t*) is the equivalent transmitted baseband signal and *H*(*t*) is the equivalent baseband of the time impulse response of the channel between the transmit and receive antennas. Example 3.3 shows the MATLAB model of the refined signal shown in equation (2). Additionally, other aspects related to the RF transmission, reception and downconversion of the signal are also contemplated (e.g., oversampling).

**Example 3.3**: MATLAB code for the signal impairment modelling.

```
%A custom IFFT function, providing an oversampled output is
required (i.e., the ADCs are oversampling by 4).
function samples = ifft_x4oversamp(BB_ofdm_symbol)
temp_symbols = zeros(8192,1);
temp_symbols(1:1024) = BB_ofdm_symbol(1:1024);
temp_symbols((8192-1024+1):8192) = BB_ofdm_symbol(1025:2048);
samples = ifft(temp_symbols,8192);
%----- function end -----
%To simulate the channel a coefficients file will be used. The
channel will be loaded in the variable 'channel'.
load('channel_coefficients')
%The frequency-domain data produced by the baseband transmitter
(i.e., before the IFFT) is loaded in the variable 'BB_data'.
load('BB_data')
%A short silence period precedes each frame: now we have to
account for the over-sampling of the ADCs.
silence_length=2560*5*4;
transmitted_signal=zeros(silence_period_length,1);
%The frame is composed by a preamble and 48 OFDM symbols.
for symb_index = 1:49
BB_ofdm_symbol=BB_data(2048*(symb_index-1)+1:(2048*symb_index));
%Introduction of the LO coupling (i.e., DC carrier is not 0).
BB_ofdm_symbol(1)=2;
```
206 MATLAB – A Fundamental Tool for Scienti c Computing and Engineering Applications – Volume 2 MATLAB as a Design and Verication Tool for the Hardware Prototyping of Wireless Communication Systems <sup>21</sup> MATLAB as a Design and Veri cation Tool for the Hardware Prototyping of Wireless Communication Systems 207

20 Will-be-set-by-IN-TECH

down-converters can be expressed as follows:

as:

*c*(*t*) = �{*x*(*t*) · *ej*2Π(*fI F*+Δ*f*)*<sup>t</sup>*

also requires a hardware-specific analysis of potential impairments (i.e., different for each testbed). In our case, the resulting refined received signal model at the output of the RF

where *x*(*t*) represents the useful part of the received baseband signal, *fIF* is the Intermediate Frequency (IF), Δ*f* is the Carrier Frequency Offset (CFO), *A* · *cos*(2Π(*fIF* + Δ*f*)*t* + *ϕ*) represents the unwanted residual carrier located at the center of the useful signal-spectrum (i.e., introduced by the LO coupling at the transmitter) and, finally, *w*(*t*) is the Gaussian noise. The useful part of the received baseband signal can be expressed

where *x*˜(*t*) is the equivalent transmitted baseband signal and *H*(*t*) is the equivalent baseband of the time impulse response of the channel between the transmit and receive antennas. Example 3.3 shows the MATLAB model of the refined signal shown in equation (2). Additionally, other aspects related to the RF transmission, reception and

downconversion of the signal are also contemplated (e.g., oversampling). **Example 3.3**: MATLAB code for the signal impairment modelling.

required (i.e., the ADCs are oversampling by 4). function samples = ifft\_x4oversamp(BB\_ofdm\_symbol)

temp\_symbols(1:1024) = BB\_ofdm\_symbol(1:1024);

channel will be loaded in the variable 'channel'.

transmitted\_signal=zeros(silence\_period\_length,1);

account for the over-sampling of the ADCs.

temp\_symbols = zeros(8192,1);

%----- function end -----

load('channel\_coefficients')

silence\_length=2560\*5\*4;

for symb\_index = 1:49

BB\_ofdm\_symbol(1)=2;

load('BB\_data')

samples = ifft(temp\_symbols,8192);

%A custom IFFT function, providing an oversampled output is

temp\_symbols((8192-1024+1):8192) = BB\_ofdm\_symbol(1025:2048);

%To simulate the channel a coefficients file will be used. The

%The frequency-domain data produced by the baseband transmitter (i.e., before the IFFT) is loaded in the variable 'BB\_data'.

%A short silence period precedes each frame: now we have to

%The frame is composed by a preamble and 48 OFDM symbols.

BB\_ofdm\_symbol=BB\_data(2048\*(symb\_index-1)+1:(2048\*symb\_index)); %Introduction of the LO coupling (i.e., DC carrier is not 0).

} + *A* · *cos*(2Π(*fIF* + Δ*f*)*t* + *ϕ*) + *w*(*t*), (2)

*x*(*t*) = *x*˜(*t*) *H*(*t*), (3)

```
%Conversion from frequency to time domain.
time_ofdm_symbol=zeros(2048+8192,1);
time_ofdm_symbol(2049:end)=ifft_x4oversamp(BB_ofdm_symbol);
%Inclusion of the CP (i.e, the CP is a copy of the last 512
symbols of the OFDMA symbol - oversampled by 4).
preamble_length=512*4;
time_ofdm_symbol(1:preamble_length)=time_ofdm_symbol(8193:end);
transmitted_signal=[transmitted_signal; time_ofdm_symbol];
end
%The modelled CFO will be equivalent to a third of the
intercarrier separation.
eps_freq=-1/3;
%Convolution of the frequency domain signal with the channel and
inclusion of the CFO and the noise.
SNR=25;
first_sample=silence_length+preamble_length+1;
mean_power = mean(abs(transmitted_signal(first_sample:end)).ˆ2);
noise_power = mean_power/(10ˆ(SNR/10));
received_signal = conv(transmitted_signal,channel);
rand_I=randn(size(received_signal));
rand_Q=randn(size(received_signal));
received_signal = received_signal+sqrt(noise_power/2)*(rand_I +
j*rand_Q);
received_signal = real(received_signal.*exp(j*2*pi*((156.8 +
(eps_freq*22.4/2048))*(1:length(received_signal))'/89.6)));
```
V *System model refinement*: In order to have a MATLAB model that provides a close match to the prerequisites of RTL coding, further modifications and refinements have to be conducted. This principally involves the emulation of fixed-point arithmetic in specific outputs of the MATLAB model. The trade-off between resulting precision and computational complexity has to be investigated. The more bits used to represent the fixed-point data, the more precision is achieved in the arithmetic operations. Considering that the prototyping target is a high performance real-time wireless communication system, it is required to use additional bits for the representation of signals, which consequently increases the FPGA processing and memory requirements. Different quantizations can be tested to analyse their effect both on independent processing stages, as well as on the overall system performance. An indicative example is when 16-bit words are used for the intermediate calculations of a custom MATLAB FFT function, featuring a radix-2 butterfly structure. This results in an aggregate quantization loss of 87 · 10<sup>−</sup>2. The equivalent loss when using 32-bit words is reduced down to 13 · 10<sup>−</sup>7. By inserting the quantized results to each of the remaining processing stages of the signal processing chain, it can be evaluated the performance-loss of the overall system. Hence, retaking the example mentioned before, the 16-bit quantized outputs of the FFT result in a performance degradation of the channel estimation (i.e., the precision-loss of

22 Will-be-set-by-IN-TECH 208 MATLAB – A Fundamental Tool for Scienti c Computing and Engineering Applications – Volume 2 MATLAB as a Design and Verication Tool for the Hardware Prototyping of Wireless Communication Systems <sup>23</sup>

the estimated coefficients for the pilot tones increases the error during the interpolation stage). Example 3.4 presents the modified version of the MATLAB signal, which accounts for hardware constraints and applies the desired quantization. It is assumed a 14-bit ADC, a QPSK modulation and a value of the pilot signals of ±4/3 (defined in the WiMAX standard). For this testing scenario the DR is set to [−1.9, 1.9]: i.e., 2 bits represent the sign and the integer part and the remaining bits represent the fractional part.

VI *MATLAB/HDL co-simulation*: this section gives representative examples of the MATLAB versus HDL co-simulations, which is a vital procedure that has to be applied in all FPGA prototyping cases. Continuing from the previous example, the digitized IF signal at the receiver (i.e., ADC outputs) will be processed by the DDC component, which comprises a programmable digital synthesizer and a complex Finite Impulse Response (FIR) lowpass filter that eliminates out-of-band components. The input signal at the DDC is multiplied with a sine and a cosine (produced by the digital synthesizer). This multiplication results in the I and Q vector components, which are finally filtered and decimated in order to produced the desired baseband signal. This procedure is considered a key functionality of the Software Defined Radio (SDR). The digital synthesizer can be tuned on-the-fly by accessing a digitally-controlled register. This fact allows designers to correct the CFO, an inherent impairment of real-life RF front-end systems.

**Example 3.4**: MATLAB code that models the constraints introduced by the utilization of a particular ADC.

**Figure 10.** Utilization of the fdatool to design a FIR low-pass filter.

**Figure 11.** Exporting the FIR low-pass filter coefficients.

returned by the synchronization block.

by fdatool is the following:

the 'hfilter' variable.

(1:length(ADC\_samples))/89.6);

load('hfilter')

The code of the equivalent MATLAB model of the DDC, using the coefficients generated

MATLAB as a Design and Veri cation Tool for the Hardware Prototyping of Wireless Communication Systems 209

%The 'eps\_freq' parameter represents the estimated CFO, as

%The FIR-coefficients generated with 'fdatool' are loaded onto

%Modelling of the DDC functions (including CFO-correction). cos\_samples = ADC\_samples.\*cos(2\*pi\*(22.4-eps\_freq\*22.4/2048)\*

function baseband\_signal = DDC(ADC\_samples, eps\_freq)

```
ADC_quantization=quantizer([14 12]);
gain=1.9/max(abs(received_signal));
ADC_samples = (received_signal.*gain)';
ADC_samples_binary = num2bin(ADC_quantization, ADC_samples);
ADC_samples_quantized = bin2num(ADC_quantization,
ADC_samples_binary);
```
Example 3.5 describes how the Xilinx DDC IP core was configured using MATLAB. In more details, we have used the Filter Design and Analysis Tool (fdatool), to design the required low-pass filter and produce the filter coefficients required for configuring the DDC core. Considering the importance of the DDC for the correct operation of the receiver, the MATLAB versus HDL co-simulation provided a crucial contribution for the evaluation of the fixed-point precision and guided the tuning of the configurable parameters featured in the DDC IP core.

**Example 3.5**: the SISO mobile WiMAX receiver requires the design of a low-pass filter with a decimation stage (denoted as polyphase decimator filter in the DDC IP). The configuration parameters of the fdatool are shown in Fig. 10.

The resulting filter has 103 coefficients, which can be quantized and exported to a file (i.e., with file extension .coe). The latter can be used to configure the Xilinx DDC IP core, as depicted in Fig. 11.

22 Will-be-set-by-IN-TECH

VI *MATLAB/HDL co-simulation*: this section gives representative examples of the MATLAB versus HDL co-simulations, which is a vital procedure that has to be applied in all FPGA prototyping cases. Continuing from the previous example, the digitized IF signal at the receiver (i.e., ADC outputs) will be processed by the DDC component, which comprises a programmable digital synthesizer and a complex Finite Impulse Response (FIR) lowpass filter that eliminates out-of-band components. The input signal at the DDC is multiplied with a sine and a cosine (produced by the digital synthesizer). This multiplication results in the I and Q vector components, which are finally filtered and decimated in order to produced the desired baseband signal. This procedure is considered a key functionality of the Software Defined Radio (SDR). The digital synthesizer can be tuned on-the-fly by accessing a digitally-controlled register. This fact allows designers to correct the CFO, an

**Example 3.4**: MATLAB code that models the constraints introduced by the utilization of

ADC\_samples\_binary = num2bin(ADC\_quantization, ADC\_samples);

Example 3.5 describes how the Xilinx DDC IP core was configured using MATLAB. In more details, we have used the Filter Design and Analysis Tool (fdatool), to design the required low-pass filter and produce the filter coefficients required for configuring the DDC core. Considering the importance of the DDC for the correct operation of the receiver, the MATLAB versus HDL co-simulation provided a crucial contribution for the evaluation of the fixed-point precision and guided the tuning of the configurable

**Example 3.5**: the SISO mobile WiMAX receiver requires the design of a low-pass filter with a decimation stage (denoted as polyphase decimator filter in the DDC IP). The

The resulting filter has 103 coefficients, which can be quantized and exported to a file (i.e., with file extension .coe). The latter can be used to configure the Xilinx DDC IP

ADC\_samples\_quantized = bin2num(ADC\_quantization,

configuration parameters of the fdatool are shown in Fig. 10.

and the integer part and the remaining bits represent the fractional part.

inherent impairment of real-life RF front-end systems.

ADC\_quantization=quantizer([14 12]); gain=1.9/max(abs(received\_signal)); ADC\_samples = (received\_signal.\*gain)';

a particular ADC.

ADC\_samples\_binary);

core, as depicted in Fig. 11.

parameters featured in the DDC IP core.

the estimated coefficients for the pilot tones increases the error during the interpolation stage). Example 3.4 presents the modified version of the MATLAB signal, which accounts for hardware constraints and applies the desired quantization. It is assumed a 14-bit ADC, a QPSK modulation and a value of the pilot signals of ±4/3 (defined in the WiMAX standard). For this testing scenario the DR is set to [−1.9, 1.9]: i.e., 2 bits represent the sign

```
%Modelling of the DDC functions (including CFO-correction).
cos_samples = ADC_samples.*cos(2*pi*(22.4-eps_freq*22.4/2048)*
(1:length(ADC_samples))/89.6);
```

```
sin_samples = -ADC_samples.*sin(2*pi*(22.4-eps_freq*22.4/2048)*
(1:length(ADC_samples))/89.6);
filter_cos = conv(cos_samples,hfilter);
filter_sin = conv(sin_samples,hfilter);
baseband_signal = filter_cos(1:4:end)+j*filter_sin(1:4:end);
%----- function end -----
```
for k = 1:length(ADC\_samples\_quantized)

fprintf(fileOut,'%s\n',DIN);

as inputs to the DDC IP core.

used to stimulate the MATLAB model.

DDC\_core\_ins : DDC\_core PORT MAP (

WE => prog\_DDS\_write\_enable,

RFD => ready\_for\_data, RDY => output\_ready, DOUT\_I => BB\_I\_comp, DOUT\_Q => BB\_Q\_comp);

VARIABLE L\_IN : LINE;

data\_valid\_in <= '0';

data\_valid\_in <= '1';

WAIT FOR 44.64 ns; reset <= '0';

data\_in <= (others => '0');

prog\_DDS\_addr <= cnt\_DDCreg;


fclose(fileOut);



PROCESS

BEGIN

reset <= '1';

end

DIN = num2bin(ADC\_quantization,(ADC\_samples\_quantized(k)));

In the following simplified version of the VHDL code of the DDC block, the MATLAB-generated signal will be used as input to the RTL code. Additionally, the results produced by the HDL simulation are written to a file. This is used in recursive manner for the MATLAB simulation of the remaining processing blocks of the receiver:

MATLAB as a Design and Veri cation Tool for the Hardware Prototyping of Wireless Communication Systems 211




VARIABLE DATA : STD\_LOGIC\_VECTOR(13 DOWNTO 0);

FILE inputFile : TEXT OPEN READ\_MODE IS "DDC\_core.in";

FILE outputFile : TEXT OPEN WRITE\_MODE IS "DDC\_RTL.out";

Fig. 12 shows how the digital filtering stage of the Xilinx DDC IP can be configured using the coefficients file produced in MATLAB.


**Figure 12.** Configuration of the digital filtering stage of the DDC IP core using the MATLAB-generated coefficients.

Example 3.6 covers the main steps required to verify the behaviour and performance of an independent processing block (built using HDL code), by interfacing it with the MATLAB model of the remaining components of the system. The one-to-one comparison of the HDL model with its MATLAB counterpart provides a reliable analysis of the implementation losses (i.e., fixed-point versus floating point) and facilitates the selection of an optimum quantization (i.e., trade-off between precision and computational complexity, optimization of the bit-alignment and truncation operations).

**Example 3.6**: The MATLAB and VHDL code of the DDC processing stage that is required to run the co-simulation is quoted next. The output of the MATLAB model is written to a file, which is later used as a test vector of the RTL-simulation:

```
%The quantized outputs of the ADC are written to a file, which
will be used to stimulate the DDC IP core.
fileOut=fopen('DDC_core.in','w');
```
210 MATLAB – A Fundamental Tool for Scienti c Computing and Engineering Applications – Volume 2 MATLAB as a Design and Verication Tool for the Hardware Prototyping of Wireless Communication Systems <sup>25</sup> MATLAB as a Design and Veri cation Tool for the Hardware Prototyping of Wireless Communication Systems 211

```
for k = 1:length(ADC_samples_quantized)
DIN = num2bin(ADC_quantization,(ADC_samples_quantized(k)));
fprintf(fileOut,'%s\n',DIN);
end
fclose(fileOut);
```
24 Will-be-set-by-IN-TECH

sin\_samples = -ADC\_samples.\*sin(2\*pi\*(22.4-eps\_freq\*22.4/2048)\*

baseband\_signal = filter\_cos(1:4:end)+j\*filter\_sin(1:4:end);

**Figure 12.** Configuration of the digital filtering stage of the DDC IP core using the

complexity, optimization of the bit-alignment and truncation operations).

file, which is later used as a test vector of the RTL-simulation:

will be used to stimulate the DDC IP core.

fileOut=fopen('DDC\_core.in','w');

Example 3.6 covers the main steps required to verify the behaviour and performance of an independent processing block (built using HDL code), by interfacing it with the MATLAB model of the remaining components of the system. The one-to-one comparison of the HDL model with its MATLAB counterpart provides a reliable analysis of the implementation losses (i.e., fixed-point versus floating point) and facilitates the selection of an optimum quantization (i.e., trade-off between precision and computational

**Example 3.6**: The MATLAB and VHDL code of the DDC processing stage that is required to run the co-simulation is quoted next. The output of the MATLAB model is written to a

%The quantized outputs of the ADC are written to a file, which

Fig. 12 shows how the digital filtering stage of the Xilinx DDC IP can be configured using

(1:length(ADC\_samples))/89.6);

the coefficients file produced in MATLAB.

%----- function end -----

MATLAB-generated coefficients.

filter\_cos = conv(cos\_samples,hfilter); filter\_sin = conv(sin\_samples,hfilter);

> In the following simplified version of the VHDL code of the DDC block, the MATLAB-generated signal will be used as input to the RTL code. Additionally, the results produced by the HDL simulation are written to a file. This is used in recursive manner for the MATLAB simulation of the remaining processing blocks of the receiver:

```
as inputs to the DDC IP core.
FILE inputFile : TEXT OPEN READ_MODE IS "DDC_core.in";
used to stimulate the MATLAB model.
FILE outputFile : TEXT OPEN WRITE_MODE IS "DDC_RTL.out";
DDC_core_ins : DDC_core PORT MAP (
 -Input ports
CLK => clock_adc,
SEL => reset,
DIN => data_in,
ND => data_valid_in,
LD_DIN => prog_DDS_value,
ADDR => prog_DDS_addr,
WE => prog_DDS_write_enable,
 -Output ports
RFD => ready_for_data,
RDY => output_ready,
DOUT_I => BB_I_comp,
DOUT_Q => BB_Q_comp);
PROCESS
VARIABLE L_IN : LINE;
VARIABLE DATA : STD_LOGIC_VECTOR(13 DOWNTO 0);
BEGIN
reset <= '1';
data_in <= (others => '0');
data_valid_in <= '0';
prog_DDS_addr <= cnt_DDCreg;
WAIT FOR 44.64 ns;
reset <= '0';
data_valid_in <= '1';
```
26 Will-be-set-by-IN-TECH 212 MATLAB – A Fundamental Tool for Scienti c Computing and Engineering Applications – Volume 2 MATLAB as a Design and Verication Tool for the Hardware Prototyping of Wireless Communication Systems <sup>27</sup>

```
FOR k IN 0 TO cnt_lengthDDC LOOP
READLINE(inputFile,L_IN);
READ(L_IN, DATA); data_in <= <= DATA;
WAIT FOR 11.16 ns;
END LOOP;
WAIT;
END PROCESS;
PROCESS(clock_adc)
VARIABLE L_OUT : LINE;
BEGIN
IF RISING_EDGE(clock_adc) THEN
IF output_ready = '1' THEN
WRITE(L_OUT, BB_I_comp);
WRITELINE(outputFile, L_OUT);
WRITE(L_OUT, BB_Q_comp);
WRITELINE(outputFile, L_OUT);
END IF;
END IF;
END PROCESS;
```

MATLAB as a Design and Veri cation Tool for the Hardware Prototyping of Wireless Communication Systems 213

VII *Data post-processing*: Once the FPGA-based prototype presents a stable operation, data can be captured in different parts of the system to evaluate its performance. This data could then be processed in MATLAB to calculate the desired metrics. When the goal is to characterize the performance of a system under mobility conditions, hundreds of data captures (e.g., generated with different channel seeds) containing several complete frames have to be captured and processed under different operating conditions (e.g., modify the SNR). MATLAB can be used to automate the calculation of the performance

**Example 3.7**: A simplified version of a MATLAB function, which automates the calculation of the EVM. The function relies on a predefined name-structure for reading

%Function to automate the calculation of the EVM from real-time

function automatic\_EVM\_calculation(channel\_spec, initial\_rep,

file\_name=['postequal\_' channel\_spec '\_' SNR\_step '\_'

%Calculation of the mean value, conversion to dB and storage EVM\_experiment(index,scenario)=10\*log10(mean(EVM\_array));

EVM\_array=EVM\_calculation\_HW\_capture(file\_name);

save(['postequal\_' channel\_spec '\_' SNR\_step '\_' num2str(initial\_rep) '\_to\_' num2str(final\_rep)

(i.e., q([16 14]) -> (27 DOWNTO 12) in RTL).

BB\_I\_trunc=[]; BB\_Q\_trunc=[];

end

the files:

end

end

index=index+1;

for l=1:(cnt\_lengthDDC+1)/2 BB\_I\_trunc(l)=BB\_I\_comp(5:20); BB\_Q\_trunc(l)=BB\_Q\_comp(5:20);

metrics, as shown in example 3.7.

final\_rep, SNR\_steps)

num2str(repetition)];

for scenario = 1:SNR\_steps

'.mat'],'EVM\_experiment'); %----- function end -----

EVM\_experiment=[];

post-equalization data captures.

for repetition = initial\_rep:final\_rep

%Generation of a predefined 'file\_name'

%Call to the function calculating the EVM

When comparing the 32-bit words at the output of the HDL-based DDC processing block with the equivalent stage of the MATLAB model, we realize that we may truncate this word to 16 bits with negligible precision losses. The required quantization is also obtained during this stage. Finally, in order to use the HDL-generated outputs in the MATLAB-simulation of the remaining blocks of the receiver, the following MATLAB code is required:

```
inputs to the MATLAB receiver.
fileIn=fopen('DDC_RTL.out','r');
VHDLResult=fscanf(fileIn,'fclose(fileIn);
DDC_quantization=quantizer([32 26]);
BB_I_comp=[];
BB_Q_comp=[];
k=1;
for l=1:(cnt_lengthDDC+1)/2
binTmp=VHDLResult(k:k+31);
BB_I_comp(l)=bin2num(DDC_quantization,binTmp);
k=k+32;
binTmp=VHDLResult(k:k+31);
BB_Q_comp(l)=bin2num(DDC_quantization,binTmp);
k=k+32;
end
```
212 MATLAB – A Fundamental Tool for Scienti c Computing and Engineering Applications – Volume 2 MATLAB as a Design and Verication Tool for the Hardware Prototyping of Wireless Communication Systems <sup>27</sup> MATLAB as a Design and Veri cation Tool for the Hardware Prototyping of Wireless Communication Systems 213

26 Will-be-set-by-IN-TECH


When comparing the 32-bit words at the output of the HDL-based DDC processing block with the equivalent stage of the MATLAB model, we realize that we may truncate this word to 16 bits with negligible precision losses. The required quantization is also obtained during this stage. Finally, in order to use the HDL-generated outputs in the MATLAB-simulation of the remaining blocks of the receiver, the following MATLAB


FOR k IN 0 TO cnt\_lengthDDC LOOP

IF RISING\_EDGE(clock\_adc) THEN IF output\_ready = '1' THEN WRITE(L\_OUT, BB\_I\_comp); WRITELINE(outputFile, L\_OUT); WRITE(L\_OUT, BB\_Q\_comp); WRITELINE(outputFile, L\_OUT);

inputs to the MATLAB receiver. fileIn=fopen('DDC\_RTL.out','r');

for l=1:(cnt\_lengthDDC+1)/2 binTmp=VHDLResult(k:k+31);

binTmp=VHDLResult(k:k+31);

VHDLResult=fscanf(fileIn,'fclose(fileIn);

BB\_I\_comp(l)=bin2num(DDC\_quantization,binTmp);

BB\_Q\_comp(l)=bin2num(DDC\_quantization,binTmp);

DDC\_quantization=quantizer([32 26]);

READ(L\_IN, DATA); data\_in <= <= DATA;

READLINE(inputFile,L\_IN);

WAIT FOR 11.16 ns;

PROCESS(clock\_adc) VARIABLE L\_OUT : LINE;

END LOOP; WAIT;

BEGIN

END IF; END IF; END PROCESS;

code is required:

BB\_I\_comp=[]; BB\_Q\_comp=[];

k=1;

k=k+32;

k=k+32; end

END PROCESS;

```
(i.e., q([16 14]) -> (27 DOWNTO 12) in RTL).
BB_I_trunc=[];
BB_Q_trunc=[];
for l=1:(cnt_lengthDDC+1)/2
BB_I_trunc(l)=BB_I_comp(5:20);
BB_Q_trunc(l)=BB_Q_comp(5:20);
end
```
VII *Data post-processing*: Once the FPGA-based prototype presents a stable operation, data can be captured in different parts of the system to evaluate its performance. This data could then be processed in MATLAB to calculate the desired metrics. When the goal is to characterize the performance of a system under mobility conditions, hundreds of data captures (e.g., generated with different channel seeds) containing several complete frames have to be captured and processed under different operating conditions (e.g., modify the SNR). MATLAB can be used to automate the calculation of the performance metrics, as shown in example 3.7.

```
Example 3.7: A simplified version of a MATLAB function, which automates the
calculation of the EVM. The function relies on a predefined name-structure for reading
the files:
%Function to automate the calculation of the EVM from real-time
post-equalization data captures.
function automatic_EVM_calculation(channel_spec, initial_rep,
final_rep, SNR_steps)
EVM_experiment=[];
for repetition = initial_rep:final_rep
for scenario = 1:SNR_steps
%Generation of a predefined 'file_name'
file_name=['postequal_' channel_spec '_' SNR_step '_'
num2str(repetition)];
%Call to the function calculating the EVM
EVM_array=EVM_calculation_HW_capture(file_name);
%Calculation of the mean value, conversion to dB and storage
EVM_experiment(index,scenario)=10*log10(mean(EVM_array));
end
index=index+1;
end
save(['postequal_' channel_spec '_' SNR_step '_'
num2str(initial_rep) '_to_' num2str(final_rep)
'.mat'],'EVM_experiment');
%----- function end -----
```
28 Will-be-set-by-IN-TECH 214 MATLAB – A Fundamental Tool for Scienti c Computing and Engineering Applications – Volume 2 MATLAB as a Design and Verication Tool for the Hardware Prototyping of Wireless Communication Systems <sup>29</sup>

The EVM calculation of the FPGA-based prototype is made possible by comparing the files captured in the equalization block with the equivalent ones of the ideal MATLAB receiver. To achieve this we have to feed the MATLAB model with all the different test vectors captured in the post AGC stage of the FPGA prototype and produce the same amount of files at the output of the equalization stage. For each OFDM symbol in each captured frame, we would apply the following MATLAB operations (a mean value for each captured-file has to be calculated in the end):

Antonio Pascual-Iserte

*(MobiLight)*, May 2011.

**5. References**

2007.

*Spain*

*Centre Tecnològic de Telecomunicacions de Catalunya (CTTC), Spain*

[1] *The MathWorks, Simulink*. http://www.mathworks.com, 2012. [2] *Xilinx, System Generator for DSP*. http://www.xilinx.com, 2012.

*European Signal Processing Conference (EUSIPCO)*, September 2007.

Testbed. *EURASIP Journal on Applied Signal Processing*, 2006, 2006.

*Reconfigurable Computing (ARC)*, March 2011.

White paper, Xilinx, October 2010.

8(9):1149–1164, November 2008.

*Communications (ICC)*, June 2009.

paper, Altera, October 2009.

*Technology and Systems*, 3(3):12:1–12:28, September 2010.

*Systems and Computers (ASILOMAR)*, November 2009.

*Department of Signal Theory and Communications, Universitat Politècnica de Catalunya (UPC),*

MATLAB as a Design and Veri cation Tool for the Hardware Prototyping of Wireless Communication Systems 215

[3] O. Font-Bach, N. Bartzoudis, A. Pascual-Iserte, and D. López Bueno. A Real-Time MIMO-OFDM Mobile WiMAX Receiver: Architecture, Design and FPGA Implementation. *Elsevier Journal of Computer Networks*, 55(16):3634–3647, November 2011. [4] O. Font-Bach, N. Bartzoudis, A. Pascual-Iserte, and D. López Bueno. A Real-Time FPGA-based Implementation of a High-Performance MIMO-OFDM Mobile WiMAX Transmitter. In *Proc. International ICST Conference on Mobile Lightweight Wireless Systems*

[5] M. Rupp, S. Caban, and C. Mehlführer. Challenges in Building MIMO Testbeds. In *Proc.*

[6] A. Engel, B. Liebig, and A. Koch. Feasibility Analysis of Reconfigurable Computing in Low-Power Wireless Sensor Applications. In *Proc. International Symposium on Applied*

[7] A. Sghaier, S. Areibi, and R. Dony. Implementation Approaches Trade-Offs for WiMax OFDM Functions on Reconfigurable Platforms. *ACM Transactions on Reconfigurable*

[8] M. Fernandez and P. Abusaidi. Virtex-6 FPGA Routing Optimization Design Techniques.

[9] S. Caban, C. Mehlführer, R. Langwieser, A. L. Scholtz, and M. Rupp. Vienna MIMO

[10] S. Hu, G. Wu, Y. L. Guan, C. L. Law, Y. Yan, and S. Li. Development and Performance Evaluation of Mobile WiMAX Testbed. In *Proc. IEEE Mobile WiMAX Symposium*, March

[11] D. Ramírez, I. Santamaría, J. Pérez, J. Vía, J. A. García-Naya, T. M. Fernández-Caramés, H. J. Pérez-Iglesias, M. González-López, L. Castedo, and J. M. Torres-Royo. A comparative study of STBC transmissions at 2.4 GHz over indoor channels using a 2 x 2 MIMO testbed. *Wireless Communications and Mobile Computing, John Wiley and Sons*,

[12] G. Wang, B. Yin, K. Amiri, Y. Sun, M. Wu, and Jo. R. Cavallaro. FPGA Prototyping of a High Data Rate LTE Uplink Baseband Receiver. In *Proc. Asilomar Conference on Signals,*

[13] M. S. Khairy, M. M. Abdallah, and S. E. D. Habib. Efficient FPGA Implementation of MIMO Decoder for Mobile WiMAX System. In *Proc. IEEE International Conference on*

[15] M. Parker. Taking Advantage of Advances in FPGA Floating-Point IP Cores. White

[16] T. Vanevenhoven. High-Level Implementation of Bit- and Cycle-Accurate Floating-Point

[14] *The MathWorks, Instrument Control Toolbox*. http://www.mathworks.com, 2012.

DSP Algorithms with Xilinx FPGAs. White paper, Xilinx, October 2011.

```
deviation=[];
for index=1:cnt_data_carriers_per_symbol
deviation(index)=equal_out_RTL(index)-ideal_equal(index);
end
EVM_symbol=mean(abs(deviation).ˆ2)/1;
```
## **4. Conclusion**

The message that this chapter intended to convey is that MATLAB is having nowadays a diverse usage that goes beyond its initial conception as a generic mathematic modeling environment. Its functionality is valuable because it can be directly interfaced with various third party software/hardware design tools and instruments. Moreover, MATLAB has a multi-level contribution in the conceptual high-level modeling of a system, and it is an ideal candidate for rapid prototyping, since it can emulate the baseband signal processing when used in instrumentation-based offline testbeds. MATLAB is also used to emulate real-life hardware constraints and it can be adapted to serve HDL co-simulations. Its role is particularly important for the prototyping of bit-intensive systems such as the PHY-layer of modern wireless communication systems. This chapter proposed a comprehensive design methodology and quoted indicative examples, in order to highlight the previously mentioned benefits of MATLAB. In concrete, this chapter provided a guideline for the use of MATLAB during the prototyping of a FPGA-based real-time transceiver based on the mobile WiMAX standard. Finally, its critical contribution was contemplated by quoting extracts of the source code of the previously mentioned system prototyping phases.

## **Acknowledgements**

The research leading to the published work was partially supported by the European Commission under projects BuNGee (248267) and BeFEMTO (248523); by the Catalan Government under grant 2009 SGR 891; and by the Spanish Ministry of Economy and Competitiveness under projects TEC2011-29006-C03-01 (GRE3N-PHY) and TEC2011-29006-C03-02 (GRE3N-LINK-MAC).

## **Author details**

Oriol Font-Bach, Nikolaos Bartzoudis and David López Bueno *Centre Tecnològic de Telecomunicacions de Catalunya (CTTC), Spain* 214 MATLAB – A Fundamental Tool for Scienti c Computing and Engineering Applications – Volume 2 MATLAB as a Design and Verication Tool for the Hardware Prototyping of Wireless Communication Systems <sup>29</sup> MATLAB as a Design and Veri cation Tool for the Hardware Prototyping of Wireless Communication Systems 215

Antonio Pascual-Iserte

*Centre Tecnològic de Telecomunicacions de Catalunya (CTTC), Spain Department of Signal Theory and Communications, Universitat Politècnica de Catalunya (UPC), Spain*

## **5. References**

28 Will-be-set-by-IN-TECH

deviation(index)=equal\_out\_RTL(index)-ideal\_equal(index);

The message that this chapter intended to convey is that MATLAB is having nowadays a diverse usage that goes beyond its initial conception as a generic mathematic modeling environment. Its functionality is valuable because it can be directly interfaced with various third party software/hardware design tools and instruments. Moreover, MATLAB has a multi-level contribution in the conceptual high-level modeling of a system, and it is an ideal candidate for rapid prototyping, since it can emulate the baseband signal processing when used in instrumentation-based offline testbeds. MATLAB is also used to emulate real-life hardware constraints and it can be adapted to serve HDL co-simulations. Its role is particularly important for the prototyping of bit-intensive systems such as the PHY-layer of modern wireless communication systems. This chapter proposed a comprehensive design methodology and quoted indicative examples, in order to highlight the previously mentioned benefits of MATLAB. In concrete, this chapter provided a guideline for the use of MATLAB during the prototyping of a FPGA-based real-time transceiver based on the mobile WiMAX standard. Finally, its critical contribution was contemplated by quoting extracts of the source

The research leading to the published work was partially supported by the European Commission under projects BuNGee (248267) and BeFEMTO (248523); by the Catalan Government under grant 2009 SGR 891; and by the Spanish Ministry of Economy and Competitiveness under projects TEC2011-29006-C03-01 (GRE3N-PHY) and

each captured-file has to be calculated in the end):

EVM\_symbol=mean(abs(deviation).ˆ2)/1;

code of the previously mentioned system prototyping phases.

Oriol Font-Bach, Nikolaos Bartzoudis and David López Bueno *Centre Tecnològic de Telecomunicacions de Catalunya (CTTC), Spain*

TEC2011-29006-C03-02 (GRE3N-LINK-MAC).

for index=1:cnt\_data\_carriers\_per\_symbol

deviation=[];

end

**4. Conclusion**

**Acknowledgements**

**Author details**

The EVM calculation of the FPGA-based prototype is made possible by comparing the files captured in the equalization block with the equivalent ones of the ideal MATLAB receiver. To achieve this we have to feed the MATLAB model with all the different test vectors captured in the post AGC stage of the FPGA prototype and produce the same amount of files at the output of the equalization stage. For each OFDM symbol in each captured frame, we would apply the following MATLAB operations (a mean value for

	- [17] O. Font-Bach, N. Bartzoudis, A. Pascual-Iserte, and D. López Bueno. Prototying Processing-Demanding Physical Layer Systems Featuring Single Or Multi-Antenna Schemes. In *Proc. European Signal Processing Conference (EUSIPCO)*, September 2011.

**DVB-S2 Model in Matlab:**

**Issues and Impairments**

Bahman Azarbad and Aduwati Binti Sali

http://dx.doi.org/10.5772/46473

**1. Introduction**

Additional information is available at the end of the chapter

maintain the growth rate required by the various market sectors.

these tools are often incomplete or too simplistic.

above mentioned capabilities.

Geostationary (GEO) satellite as a broadcasting media.

For the past two decades, the wide coverage and the reliable bandwidth offered by the broadband satellite systems has made them a promising media for IP streaming. Meanwhile, the demand for exploring new solutions concerning this industry has kept increasing to

**Chapter 10**

In order to minimize the design time as well as implementation costs, the initial steps in researches concerning satellite systems are often taken in simulation environments. In contrast with the actual satellite system test-beds which are expensive or sometimes not available to the academic research community, the simulation software packages like Mathworks MATLAB are widely used at the early stages of modeling and design process.However, such packages are mostly designed as general purpose tools and therefore, the built-in models provided by

The main objective of this research is to use MATLAB simulator for study of issues and impairments of Digital Video Broadcasting-Second generation (DVB-S2) standard in

In this study we model DVB-S2 standard using Matlab communication toolbox and built in DVB-S2 model in Simulink. However, it is noted that the model in Matlab does not include higher order modulations: 16APSK and 32APSK and also the main novelty of DVB-S2 which is the ACM algorithm. Therefore we need to rebuild the model using toolboxes to add the

In the following sections, we first provide background of DVB-S2 Standard and in the next section a brief overview on DVB-S2 Model in Matlab will be presented , and then we will go through the model improvement on the following section and afterwards we will analyze presented solution by means of BER performance of the system and the provided ACM

> ©2012 Azarbad and Binti Sali, licensee InTech. This is an open access chapter distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original

©2012 Azarbad and Binti Sali, licensee InTech. This is a paper distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use,

distribution, and reproduction in any medium, provided the original work is properly cited.

engine. Finally, in the last section ,we will discuss the results and future work.

work is properly cited.


216 MATLAB – A Fundamental Tool for Scienti c Computing and Engineering Applications – Volume 2 **Chapter 0 Chapter 10**

## **DVB-S2 Model in Matlab: Issues and Impairments**

Bahman Azarbad and Aduwati Binti Sali

Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/46473

## **1. Introduction**

30 Will-be-set-by-IN-TECH

[17] O. Font-Bach, N. Bartzoudis, A. Pascual-Iserte, and D. López Bueno. Prototying Processing-Demanding Physical Layer Systems Featuring Single Or Multi-Antenna Schemes. In *Proc. European Signal Processing Conference (EUSIPCO)*, September 2011.

[19] IEEE 802.16e-2005. IEEE Standard for Local and Metropolitan Area Networks. Part 16: Air Interface for Fixed Broadband Wireless Access Systems. Amendment 2: Physical and Medium Access Control Layer for Combined Fixed and Mobile Operation in Licensed

[18] *CTTC, GEDOMIS® testbed*. http://engineering.cttc.es/gedomis, 2012.

Bands, 2005.

For the past two decades, the wide coverage and the reliable bandwidth offered by the broadband satellite systems has made them a promising media for IP streaming. Meanwhile, the demand for exploring new solutions concerning this industry has kept increasing to maintain the growth rate required by the various market sectors.

In order to minimize the design time as well as implementation costs, the initial steps in researches concerning satellite systems are often taken in simulation environments. In contrast with the actual satellite system test-beds which are expensive or sometimes not available to the academic research community, the simulation software packages like Mathworks MATLAB are widely used at the early stages of modeling and design process.However, such packages are mostly designed as general purpose tools and therefore, the built-in models provided by these tools are often incomplete or too simplistic.

The main objective of this research is to use MATLAB simulator for study of issues and impairments of Digital Video Broadcasting-Second generation (DVB-S2) standard in Geostationary (GEO) satellite as a broadcasting media.

In this study we model DVB-S2 standard using Matlab communication toolbox and built in DVB-S2 model in Simulink. However, it is noted that the model in Matlab does not include higher order modulations: 16APSK and 32APSK and also the main novelty of DVB-S2 which is the ACM algorithm. Therefore we need to rebuild the model using toolboxes to add the above mentioned capabilities.

In the following sections, we first provide background of DVB-S2 Standard and in the next section a brief overview on DVB-S2 Model in Matlab will be presented , and then we will go through the model improvement on the following section and afterwards we will analyze presented solution by means of BER performance of the system and the provided ACM engine. Finally, in the last section ,we will discuss the results and future work.

©2012 Azarbad and Binti Sali, licensee InTech. This is an open access chapter distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. ©2012 Azarbad and Binti Sali, licensee InTech. This is a paper distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

## **2. Background**

The evolution of digital multimedia broadcasting over broadband communication systems in early 90's ,initiated the first stages of standardizing the digital TV broadcasting.In 1993, European Telecommunication Standards Institute (ETSI) started a project named Digital Video Broadcasting(DVB).The main objective of this standard was to introduce standards for digital multimedia services. DVB-S,the first standard for satellite video broadcasting over GEO satellite systems hired an outer shortened Reed Solomon(RS) and inner variable length convolutional code as its Forward Error Correction(FEC) technique[1].

The satellite communication channel mostly suffers from signal fading mainly resulted from atmospheric rain attenuation and ionospheric scintillation.Rain attenuation affects these signals severely by absorbing properties of the water,while amplitude and phase of the received signal will be distorted frequently by scintillation in ionosphere caused by electron

Since scintillation effects rapidly occurs cannot be compensated by mode adaptation because of the long propagation delay in GEO satellite systems. But rain attenuation time scale is larger comparing to scintillation, hence deploying mode adaptation techniques is convincing to tackle these effects.ACM threshold offsets define thresholds for every ModCod a certain level of safe SNR to guarantee a quasi-zero BER transmission.Making the decision of switching among ModCods is the Gateways's responsibility. In one hand,this adaptation is crucial to tolerate fade attenuations by choosing an adequate ModCod according to the safe threshold defined in the ACM table,on the other hand very frequent changes in channel states due to scintillation may cause in recurrent crossing of thresholds subsequently frequent switchings

Provided that with 11 coding rate and 4 modulation order available in the standard , there will be 44 possible combinations. Only 28 of them are covered by DVB-S2 standard.Considering complexity of terminal design and limited usage of some of these ModCods,there is some proposals suggesting a reduced subset of ModCods.A subset of less than one forth(5 or 7 out of 28)has been investigated in[7].They showed a close to optimum performance can be achieved using these reduced subset and consequently complexity of the terminal will be decreased.This reduced set of ModCods avoid system oscillations and will increase systems

The tradeoff between terminal design complexity and achievable spectral efficiency has also been investigated in[9].In this research they proposed subsets of 8 and 5 Modcods with equidistant separation of adjacent ModCods.A simulated time series of one month was their

they assumed that a frame is corrupted if the SNR of received signal is less than the threshold offset and it means that comparison between sent and received signal has not been carried out.They obviously ignored the PSNR of received signal and effects of error concealment

The design of different ACM thresholds and safety margins also play a significant role in the performance of the system.Although the zero-quasi BER offered by DVB-S2 standard is excellent,recent advances in audio and video codecs reduced their need for such outstanding BER level.About 15% packet loss can be accommodated without severe degradation in speech and also modern video codecs like MPEG-4 are capable of concealing errors in input stream by hiring error correction techniques (eg.interframe interpolation)they can accept a higher BER providing acceptable video quality[10].Hence BER rates as high as given below can be

Considering the variation in application requirements of different threshold offsets can be implemented in ACM tables.As mentioned above , some applications can tolerate higher BER, so it is reasonable to decrease quality of the transmission in terms of allowing higher BER

*BER* <sup>=</sup><sup>≤</sup> <sup>10</sup>−<sup>5</sup> (1)

DVB-S2 Model in Matlab: Issues and Impairments 219

*BER* <sup>=</sup><sup>≤</sup> <sup>10</sup>−<sup>3</sup> (2)

density irregularities[5].

which is not desirable[6].

SNR pattern targeting a BER at :

resulting in higher spectrum efficiency in the system.

provided by other layers .

stability[8]

acceptable:

For interactive applications and adaptive transmissions presence of a return link is compulsory.One return link can be established using terrestrial networks which has its own disadvantages like higher cost and unavailability of the link. The more interesting option would be using the same antenna at the receiver for the return link via satellite.This was the motivation for defining a new standard called Digital Video Broadcasting Return channel satellite (DVB-RCS).At the same time that ETSI was providing this standard , they had another project runing for second generation of satellite broadcasting,DVB-S2. In 2003, DVB-S2 specifications was provided by ETSI.

DVB-S2 standard exploits 30% channel efficiency improvement using same power and bandwidth as its ancestor DVB-S[2]. This improvement was resulted from the usage of new FEC techniques: Low Density Parity Check (LDPC) and Bose-Chaudhuri-Hochquenghem (BCH), higher order modulations: 16APSK, 32APSK and a dynamic selection of coding and modulations using instantaneous Channel State Information (CSI) so called Adaptive Coding and Modulation (ACM).

Fade mitigation techniques (FMT) are widely applied on satellite communication to tackle transmission errors and losses caused by atmospheric effects on these systems. Time variant nature of channel states in a Ka band channel affects severely performance of a satellite link,hence it necessitates a dynamic adjustment of Modulation and Coding (ModCods)used by physical layer for transmission. This dynamic adjustment is performed by an adaptive coding and modulation algorithm augmented in DVB-S2 systems deploying a feedback link via DVB-RCS terminals. ACM algorithm uses CSI sent by DVB-RCS return link from individual Earth Stations (ES) to Gate-way ,so called Network Control Center (NCC). NCC is responsible for making the proper selection of ModCods aiming best spectrum efficiency and the desired Bit Error Rate (BER) at the same time[3].

To overcome influences of fading events on transmission quality one of the Well-Known techniques among FMT's is ACM.ACM algorithm will make the proper switching in physical layer transmission mode to maintain channel quality.Different combinations of coding rates and modulation orders are given by ETSI standard.A low coding rate and modulation order will increase robustness of transmission in poor channel quality conditions with a lower spectral efficiency indeed. In case of clear sky by choosing higher coding rate and higher modulation orders spectral efficiency will be increased and system provides a higher throughput.The trade-off between spectral efficiency and BER is crucial in system performance and also transmission cost.In one hand, keeping in to account that although a spectral efficiency higher than appropriate according to channel state will increase system throughput ,it will introduce excessive BER to the system as well. On the other hand, if a ModCod with too low spectral efficiency is selected when the channel quality is in a good condition then capacity of the system will be wasted[4].

The satellite communication channel mostly suffers from signal fading mainly resulted from atmospheric rain attenuation and ionospheric scintillation.Rain attenuation affects these signals severely by absorbing properties of the water,while amplitude and phase of the received signal will be distorted frequently by scintillation in ionosphere caused by electron density irregularities[5].

2 Will-be-set-by-IN-TECH

The evolution of digital multimedia broadcasting over broadband communication systems in early 90's ,initiated the first stages of standardizing the digital TV broadcasting.In 1993, European Telecommunication Standards Institute (ETSI) started a project named Digital Video Broadcasting(DVB).The main objective of this standard was to introduce standards for digital multimedia services. DVB-S,the first standard for satellite video broadcasting over GEO satellite systems hired an outer shortened Reed Solomon(RS) and inner variable length

For interactive applications and adaptive transmissions presence of a return link is compulsory.One return link can be established using terrestrial networks which has its own disadvantages like higher cost and unavailability of the link. The more interesting option would be using the same antenna at the receiver for the return link via satellite.This was the motivation for defining a new standard called Digital Video Broadcasting Return channel satellite (DVB-RCS).At the same time that ETSI was providing this standard , they had another project runing for second generation of satellite broadcasting,DVB-S2. In 2003, DVB-S2

DVB-S2 standard exploits 30% channel efficiency improvement using same power and bandwidth as its ancestor DVB-S[2]. This improvement was resulted from the usage of new FEC techniques: Low Density Parity Check (LDPC) and Bose-Chaudhuri-Hochquenghem (BCH), higher order modulations: 16APSK, 32APSK and a dynamic selection of coding and modulations using instantaneous Channel State Information (CSI) so called Adaptive Coding

Fade mitigation techniques (FMT) are widely applied on satellite communication to tackle transmission errors and losses caused by atmospheric effects on these systems. Time variant nature of channel states in a Ka band channel affects severely performance of a satellite link,hence it necessitates a dynamic adjustment of Modulation and Coding (ModCods)used by physical layer for transmission. This dynamic adjustment is performed by an adaptive coding and modulation algorithm augmented in DVB-S2 systems deploying a feedback link via DVB-RCS terminals. ACM algorithm uses CSI sent by DVB-RCS return link from individual Earth Stations (ES) to Gate-way ,so called Network Control Center (NCC). NCC is responsible for making the proper selection of ModCods aiming best spectrum efficiency and

To overcome influences of fading events on transmission quality one of the Well-Known techniques among FMT's is ACM.ACM algorithm will make the proper switching in physical layer transmission mode to maintain channel quality.Different combinations of coding rates and modulation orders are given by ETSI standard.A low coding rate and modulation order will increase robustness of transmission in poor channel quality conditions with a lower spectral efficiency indeed. In case of clear sky by choosing higher coding rate and higher modulation orders spectral efficiency will be increased and system provides a higher throughput.The trade-off between spectral efficiency and BER is crucial in system performance and also transmission cost.In one hand, keeping in to account that although a spectral efficiency higher than appropriate according to channel state will increase system throughput ,it will introduce excessive BER to the system as well. On the other hand, if a ModCod with too low spectral efficiency is selected when the channel quality is in a good

convolutional code as its Forward Error Correction(FEC) technique[1].

**2. Background**

specifications was provided by ETSI.

the desired Bit Error Rate (BER) at the same time[3].

condition then capacity of the system will be wasted[4].

and Modulation (ACM).

Since scintillation effects rapidly occurs cannot be compensated by mode adaptation because of the long propagation delay in GEO satellite systems. But rain attenuation time scale is larger comparing to scintillation, hence deploying mode adaptation techniques is convincing to tackle these effects.ACM threshold offsets define thresholds for every ModCod a certain level of safe SNR to guarantee a quasi-zero BER transmission.Making the decision of switching among ModCods is the Gateways's responsibility. In one hand,this adaptation is crucial to tolerate fade attenuations by choosing an adequate ModCod according to the safe threshold defined in the ACM table,on the other hand very frequent changes in channel states due to scintillation may cause in recurrent crossing of thresholds subsequently frequent switchings which is not desirable[6].

Provided that with 11 coding rate and 4 modulation order available in the standard , there will be 44 possible combinations. Only 28 of them are covered by DVB-S2 standard.Considering complexity of terminal design and limited usage of some of these ModCods,there is some proposals suggesting a reduced subset of ModCods.A subset of less than one forth(5 or 7 out of 28)has been investigated in[7].They showed a close to optimum performance can be achieved using these reduced subset and consequently complexity of the terminal will be decreased.This reduced set of ModCods avoid system oscillations and will increase systems stability[8]

The tradeoff between terminal design complexity and achievable spectral efficiency has also been investigated in[9].In this research they proposed subsets of 8 and 5 Modcods with equidistant separation of adjacent ModCods.A simulated time series of one month was their SNR pattern targeting a BER at :

$$BER = \le 10^{-5} \tag{1}$$

they assumed that a frame is corrupted if the SNR of received signal is less than the threshold offset and it means that comparison between sent and received signal has not been carried out.They obviously ignored the PSNR of received signal and effects of error concealment provided by other layers .

The design of different ACM thresholds and safety margins also play a significant role in the performance of the system.Although the zero-quasi BER offered by DVB-S2 standard is excellent,recent advances in audio and video codecs reduced their need for such outstanding BER level.About 15% packet loss can be accommodated without severe degradation in speech and also modern video codecs like MPEG-4 are capable of concealing errors in input stream by hiring error correction techniques (eg.interframe interpolation)they can accept a higher BER providing acceptable video quality[10].Hence BER rates as high as given below can be acceptable:

$$BER = \le 10^{-3} \tag{2}$$

Considering the variation in application requirements of different threshold offsets can be implemented in ACM tables.As mentioned above , some applications can tolerate higher BER, so it is reasonable to decrease quality of the transmission in terms of allowing higher BER resulting in higher spectrum efficiency in the system.

## **3. DVB-S2 model in Matlab**

## **3.1. Introduction**

Matlab includes some of important digital video transmission models such as Digital Video Broadcasting-Terrestrial (DVB-T), Digital Video Broadcasting-Cable (DVB-C) and Digital Video Broadcasting-Satellite Second Generation (DVB-S2). Representation of these models are all based on European Telecommunication Standardization Institute (ETSI), in our case of study EN 302 307 [11].

.Information bits or called Data FieLd (DFL)can be calculated as given in below formula:

Number of MPEG packets that can be fitted in one BBFRAME can be shown as:

Kldpc. The structure of whole FECFRAME is shown in the Figure 3.

*Numbero f Packets* = [*Kbch* <sup>−</sup> <sup>80</sup>

To fulfill BBFRAME size to match BCH encoder input ,post zero padding will be applied.At the receiver side Unbuffering block is responsible for excluding added zero pads and the BBHeader to generate MPEG packets from received frame.Number of zero pad added can

One of DVB-S2 standard advances is the forward error correction which is deployed to reduce BER in transmissions is BCH error correction. Output of BBFrame buffering block at the sender side, as above mentioned ,are frames of kbch bits where a BCH(Nbch,Kbch) error correction with the correcting power of t will be applied to them . For each of 11 rate of coding presented in the standard Kbch and Nbch values are defined including the t-error correcting parameter. In tables 1 and 2 these values are shown for normal and short frames respectively. The output of BCH encoder called BCHFEC frame will be created by adding parity check bits to make a frame with Nbch size.Nbch is the input of inner LDPC encoder which is also named

Nbch,the BCH encoder out put as the input of inner FEC encoder will be processed at LDPC encoder to be protected from error with parity bits.The number of parity bits are given in

LDPC encoder supports 11 coding rates.These coding rates are the ratio between information bits(Nbch bits) and LDPC coded block bits which is the FECFRAME. Fore example for rate

*ZeroPadNo* = *Kbch* − ((*Numbero f Packets* ∗ 1504) + 80) (5)

*numbero f LDPCparitybits* = *Nldpc* − *Nbch* (6)

size.Structure of a BBFRAME is shown In Figure 2.

**Figure 2.** BBFRAME Structure[11]

be shown as:

*3.2.3. BCH encoder/decoder*

*3.2.4. LDPC encoder/decoder*

tables 1 and 2, as :

Where Kbch is the size of outer FEC Encoder BCH input,and 80 is the BBFrame header

*DataField* = *Kbch* − 80 (3)

<sup>1504</sup> ] (4)

DVB-S2 Model in Matlab: Issues and Impairments 221

Simulink function blocks are hired for this implementation which will be discussed in detail in the following sections and lack of some parts will be mentioned indeed.

## **3.2. Matlab DVB-S2 model hierarchy**

Figure 1 shows block diagram of DVB-S2 model in Matlab . Each block and its functionalities are given in subsequent sections.

**Figure 1.** DVB-S2 Block Diagram in Matlab

## *3.2.1. Bernoulli sequence generator*

The very first block is responsible for generating a balanced, in terms of probability of incidents, random binary sequence. Bernoulli sequence is a distribution of zeroes and ones by probabilities of p and (p-1) respectively. In this model, p equals to 0.5 resulting in equal probability of happening for 0 and 1. Output of this block is frame based with the same size as a MPEG-TS packet which is 188 bytes of 8 bits making it 1504 bits.

### *3.2.2. BBFRAME buffering/unbuffering*

Output of packet source generator is buffered to make a Base Band Frame (BBFRAME).The size of this frame is related to the coding rate being used ,equal to BCH encoder input size .Information bits or called Data FieLd (DFL)can be calculated as given in below formula:

$$DataField = K\_bch - 80\tag{3}$$

Where Kbch is the size of outer FEC Encoder BCH input,and 80 is the BBFrame header size.Structure of a BBFRAME is shown In Figure 2.

#### **Figure 2.** BBFRAME Structure[11]

4 Will-be-set-by-IN-TECH

Matlab includes some of important digital video transmission models such as Digital Video Broadcasting-Terrestrial (DVB-T), Digital Video Broadcasting-Cable (DVB-C) and Digital Video Broadcasting-Satellite Second Generation (DVB-S2). Representation of these models are all based on European Telecommunication Standardization Institute (ETSI), in our case of

Simulink function blocks are hired for this implementation which will be discussed in detail

Figure 1 shows block diagram of DVB-S2 model in Matlab . Each block and its functionalities

The very first block is responsible for generating a balanced, in terms of probability of incidents, random binary sequence. Bernoulli sequence is a distribution of zeroes and ones by probabilities of p and (p-1) respectively. In this model, p equals to 0.5 resulting in equal probability of happening for 0 and 1. Output of this block is frame based with the same size

Output of packet source generator is buffered to make a Base Band Frame (BBFRAME).The size of this frame is related to the coding rate being used ,equal to BCH encoder input size

as a MPEG-TS packet which is 188 bytes of 8 bits making it 1504 bits.

in the following sections and lack of some parts will be mentioned indeed.

**3. DVB-S2 model in Matlab**

**3.2. Matlab DVB-S2 model hierarchy**

are given in subsequent sections.

**Figure 1.** DVB-S2 Block Diagram in Matlab

*3.2.1. Bernoulli sequence generator*

*3.2.2. BBFRAME buffering/unbuffering*

**3.1. Introduction**

study EN 302 307 [11].

Number of MPEG packets that can be fitted in one BBFRAME can be shown as:

$$Number of Packets = \left[\frac{K\_bch - 80}{1504}\right] \tag{4}$$

To fulfill BBFRAME size to match BCH encoder input ,post zero padding will be applied.At the receiver side Unbuffering block is responsible for excluding added zero pads and the BBHeader to generate MPEG packets from received frame.Number of zero pad added can be shown as:

$$Zero\text{PadNo} = K\_bch - ((NumberofPackets \* 1504) + 80) \tag{5}$$

#### *3.2.3. BCH encoder/decoder*

One of DVB-S2 standard advances is the forward error correction which is deployed to reduce BER in transmissions is BCH error correction. Output of BBFrame buffering block at the sender side, as above mentioned ,are frames of kbch bits where a BCH(Nbch,Kbch) error correction with the correcting power of t will be applied to them . For each of 11 rate of coding presented in the standard Kbch and Nbch values are defined including the t-error correcting parameter. In tables 1 and 2 these values are shown for normal and short frames respectively.

The output of BCH encoder called BCHFEC frame will be created by adding parity check bits to make a frame with Nbch size.Nbch is the input of inner LDPC encoder which is also named Kldpc. The structure of whole FECFRAME is shown in the Figure 3.

#### *3.2.4. LDPC encoder/decoder*

Nbch,the BCH encoder out put as the input of inner FEC encoder will be processed at LDPC encoder to be protected from error with parity bits.The number of parity bits are given in tables 1 and 2, as :

$$numberof\text{LDPC}\_{\text{parity}}bits = \text{N}\_{\text{l}}dpc - \text{N}\_{\text{b}}ch\tag{6}$$

LDPC encoder supports 11 coding rates.These coding rates are the ratio between information bits(Nbch bits) and LDPC coded block bits which is the FECFRAME. Fore example for rate


**Figure 3.** FECFRAME Structure[11]

**Table 3.** Bit Interleaver structure

*3.2.5. Interleaver/deinterleaver*

input.

later.The interleaver structure is given in table 3.

processes are shown in figures 4 and 5.

1/4 in a normal frame it shows:

Modulation Rows(for nldpc=64800) Rows(for nldpc=16200) Columns 8PSK 21600 5400 3 16APSK 16200 4050 4 32APSK 12960 3240 5

*Nbch*

*nldpc* <sup>=</sup> <sup>16200</sup>

This means that for every 1 bit of information sent from outer FEC coder(BCH),there will be 3 bits of parity checks added in LDPC encoder. The lower this ratio the more protection of data against error has been carried out in LDPC encoder. This will result in more robust data transmission,and it will reduce system throughput indeed. At the receiver side,LDPC decoder will check the received sequence till the parity checks are satisfied up to 50 iterations.This error correction uses the sparse parity-check matrices with a hard decision making algorithm.

Interleaving process is the next step in DVB-S2 for modulations 8PSK,16APSK and 32APSK. Interleaving on QPSK is not going to be done and as for DVB-S2 model in Matlab ,16APSK and 32APSK modulations are not included so we will discuss them in our proposed model

Interleaver block in Matlab will make this on 8PSK by writing column wise serially the output of LDPC encoder in a 3 by nldpc(21600 for 8PSK) matric and then will read it out row wise.The MSB of BBHeader will be read-out first since for rate 3/5 it will be read-out as third.These

Interleaving process creates rows in a matric from the LDPC encoder output according to the modulation order M, so each row will contain a symbol ready to be mapped in the next block ,modulation.At the receiver side Deinterleaver block will receive the output of demodulator block as input and will apply the reverse process to create a serial output for the LDPCdecoder

<sup>64800</sup> <sup>=</sup> <sup>1</sup>

<sup>4</sup> (7)

DVB-S2 Model in Matlab: Issues and Impairments 223

**Table 1.** Coding parameters for normal FECFRAMEnldpc=64800


**Table 2.** Coding parameters for short FECFRAMEnldpc=16200

**Figure 3.** FECFRAME Structure[11]

6 Will-be-set-by-IN-TECH

LDPC BCH Uncoded BCH coded block Nbch BCH t-error LDPC Coded Block

LDPC BCH Uncoded BCH coded block Nbch BCH Effective LDPC Coded Code Block Kbch LDPC Uncoded t-error LDPC Rate Block identifier Block kldpc correction kldpc/16 200 nldpc 1/4 3072 3240 12 1/5 16200 1/3 5232 5400 12 1/3 16200 2/5 6312 6480 12 2/5 16200 1/2 7032 7200 12 4/9 16200 3/5 9552 9720 12 3/5 16200 2/3 10632 10800 12 2/3 16200 3/4 11712 11880 12 11/15 16200 4/5 12432 12600 12 7/9 16200 5/6 13152 13320 12 37/45 16200 8/9 14232 14400 12 8/9 16200 9/10 NA NA NA NA NA

Code Block Kbch LDPC Uncoded Block kldpc correction nldpc 1/4 16008 16200 12 64800 1/3 21408 21600 12 64800 2/5 25728 25920 12 64800 1/2 32208 32400 12 64800 3/5 38688 38880 12 64800 2/3 43040 43200 10 64800 3/4 48408 48600 12 64800 4/5 51648 51840 12 64800 5/6 53840 54000 10 64800 8/9 57472 57600 8 64800 9/10 58192 58320 8 64800

**Table 1.** Coding parameters for normal FECFRAMEnldpc=64800

**Table 2.** Coding parameters for short FECFRAMEnldpc=16200


**Table 3.** Bit Interleaver structure

1/4 in a normal frame it shows:

$$\frac{N\_bch}{n\_ldpc} = \frac{16200}{64800} = \frac{1}{4} \tag{7}$$

This means that for every 1 bit of information sent from outer FEC coder(BCH),there will be 3 bits of parity checks added in LDPC encoder. The lower this ratio the more protection of data against error has been carried out in LDPC encoder. This will result in more robust data transmission,and it will reduce system throughput indeed. At the receiver side,LDPC decoder will check the received sequence till the parity checks are satisfied up to 50 iterations.This error correction uses the sparse parity-check matrices with a hard decision making algorithm.

#### *3.2.5. Interleaver/deinterleaver*

Interleaving process is the next step in DVB-S2 for modulations 8PSK,16APSK and 32APSK. Interleaving on QPSK is not going to be done and as for DVB-S2 model in Matlab ,16APSK and 32APSK modulations are not included so we will discuss them in our proposed model later.The interleaver structure is given in table 3.

Interleaver block in Matlab will make this on 8PSK by writing column wise serially the output of LDPC encoder in a 3 by nldpc(21600 for 8PSK) matric and then will read it out row wise.The MSB of BBHeader will be read-out first since for rate 3/5 it will be read-out as third.These processes are shown in figures 4 and 5.

Interleaving process creates rows in a matric from the LDPC encoder output according to the modulation order M, so each row will contain a symbol ready to be mapped in the next block ,modulation.At the receiver side Deinterleaver block will receive the output of demodulator block as input and will apply the reverse process to create a serial output for the LDPCdecoder input.

8 Will-be-set-by-IN-TECH 224 MATLAB – A Fundamental Tool for Scienti c Computing and Engineering Applications – Volume 2 DVB-S2 Model in Matlab: Issues and Impairments <sup>9</sup>

*Phaseo f f set* <sup>=</sup> *<sup>π</sup>*

At the receiver side,demodulator will analyze the received signal from the channel and will

approximately calculate LLR's using soft decision making LLR algorithm.Demodulator needs noise variance of the signal or at least an estimation of it. Noise variance calculation is given

*Noisevariance* <sup>=</sup> *SignalPower* <sup>∗</sup> *SymbolTime*

Additive Gaussian White Noise(AWGN) block in Matlab comply with Transmission channel in Ka band.This block adds a noise to the complex signal sent from modulator based on a

*SampleTime* ∗ 10

( *Es No* ) 10

(10)

**Figure 6.** Bit mapping into QPSK constellation[11]

**Figure 7.** Bit mapping into 8PSK constellation[11]

in below formula:

*3.2.7. AWGN channel*

<sup>4</sup> (9)

DVB-S2 Model in Matlab: Issues and Impairments 225

**Figure 4.** Bit Interleaving scheme for 8PSK and normal FECFRAME length (all rates except 3/5)[11]

**Figure 5.** Bit Interleaving scheme for 8PSK and normal FECFRAME length (rate 3/5 only)[11]

#### *3.2.6. Modulator/demadulator*

Modulation block will process the interleaved vector by first mapping each row to a symbol which in our case is a gray mapping,then the mapped symbols will be assigned to constellations.Constellation and mapping for QPSK and 8PSK are given in figures 6 and 7 respectively.Modulator for QPSK and 8psk both orders have a phase offset given below and the average energy for normalized constellation per symbol should correspond to :

$$
\rho^2 = 1 \tag{8}
$$

#### 224 MATLAB – A Fundamental Tool for Scienti c Computing and Engineering Applications – Volume 2 DVB-S2 Model in Matlab: Issues and Impairments <sup>9</sup> DVB-S2 Model in Matlab: Issues and Impairments 225

$$PhaseOffset = \frac{\pi}{4} \tag{9}$$

At the receiver side,demodulator will analyze the received signal from the channel and will

**Figure 6.** Bit mapping into QPSK constellation[11]

8 Will-be-set-by-IN-TECH

**Figure 4.** Bit Interleaving scheme for 8PSK and normal FECFRAME length (all rates except 3/5)[11]

**Figure 5.** Bit Interleaving scheme for 8PSK and normal FECFRAME length (rate 3/5 only)[11]

the average energy for normalized constellation per symbol should correspond to :

Modulation block will process the interleaved vector by first mapping each row to a symbol which in our case is a gray mapping,then the mapped symbols will be assigned to constellations.Constellation and mapping for QPSK and 8PSK are given in figures 6 and 7 respectively.Modulator for QPSK and 8psk both orders have a phase offset given below and

*ρ*<sup>2</sup> = 1 (8)

*3.2.6. Modulator/demadulator*

**Figure 7.** Bit mapping into 8PSK constellation[11]

approximately calculate LLR's using soft decision making LLR algorithm.Demodulator needs noise variance of the signal or at least an estimation of it. Noise variance calculation is given in below formula:

$$\text{Noisevariance} = \frac{\text{SignalPower} \ast \text{SymbolTime}}{\text{SampleTime} \ast 10^{\frac{\left(\frac{\text{Es}}{\text{No}}\right)}{\text{10}}}} \tag{10}$$

#### *3.2.7. AWGN channel*

Additive Gaussian White Noise(AWGN) block in Matlab comply with Transmission channel in Ka band.This block adds a noise to the complex signal sent from modulator based on a manual parameter being set by the user.This parameter can be defined as Es/No,Eb/No or SNR,any how the block will calculate the noise variance and will add a noise with zero mean to the signal.The relation between Es/No,Eb/No and SNR is as follows:

$$\frac{E\_s}{N\_o} = \left(\frac{T\_s \text{sym}}{T\_s amp}\right) \* SNR \tag{11}$$

**4.1. MPEG-TS input/output blocks**

estimation[12].MSE computation is expressed as:

**4.2. PSNR calculation**

**4.3. Interleaver/deinterleaver**

**4.4. Modulator/demodulator**

band signal for transmission.

*4.4.1. 16 APSK modulator*

In Matlab DVB-S2 model as mentioned earlier they use a random Bernoulli sequence generator for input of the model.To analyze the effect of ACM algorithm on the quality of transmission of a real MPEG stream, we used MPEG-TS stored in a matrix with 188 columns (one MPEG packet) and 100000 rows(number of packets).This is used as the input of the

Peak Signal to Noise Ratio(PSNR)which is a well-known metric for quality measurement of received video, is added to the proposed model.The computation of PSNR is in decibels and uses the Mean Square Error(MSE) which is also an error metric often used for video quality

*<sup>N</sup>* ∑(*P<sup>s</sup>*

where N represents the number of pixels in the image while P and P are the original image

*PSNR* <sup>=</sup> <sup>10</sup>*log* (2*<sup>n</sup>* <sup>−</sup> <sup>1</sup>)<sup>2</sup>

Interleaving for 16 and 32 APSK are two blocks included to the model based on ETSI instructions.The number of rows and columns of this interleaver are given in table 3.In figure 9 the structure of Interleaver for 16 APSK is given , the only difference with 32 APSK is the number of columns which is 5 instead of 4, consequently number of rows also will be different.

Higher order modulations presented by DVB-S2,provides higher spectrum efficiency comparing to the earlier generation,DVB-S.To analyze the BER performance of DVB-S2 and also adding the ACM algorithm to our model, we include Modulations for 16 and 32 APSK. Modulation block is responsible for mapping and constellation generation to prepare the base

The modulation constellation for 16 APSK as described in ETSI uses two concentric rings R1 and R2.These rings are uniformly spaced with 4 and 12 points.The constellation is given in the

> *<sup>γ</sup>* <sup>=</sup> *<sup>R</sup>*<sup>2</sup> *R*1

*<sup>i</sup>* <sup>−</sup> *<sup>P</sup><sup>r</sup>*

*<sup>i</sup>* )<sup>2</sup> (13)

DVB-S2 Model in Matlab: Issues and Impairments 227

*MSE*(*I*) (14)

(15)

*MSE* <sup>=</sup> <sup>1</sup>

and received image respectively.The PSNR then is computed as follows:

where n is the number of luminance bits used in the image.

Figure 10.The ratio between R1 and R2,gamma,is defined as:

system and at receiver side will be again stored for PSNR calculation.

$$\frac{E\_s}{N\_o} = \left(\frac{E\_b}{N\_o}\right) + 10\log(k)\tag{12}$$

Where Es is the signal energy in Joules ,Eb is bit energy in Joules, No is noise power spectral density,Tsym is the symbol period ,K is the information bits per symbol and Tsamp is the sample time.

## **4. Proposed DVB-S2 model**

The most important motivation of this project was to implement a DVB-S2 link layer model in matlab which includes ACM algorithm with a complete set of ModCods and also video quality measurement system . To do so we added modulations for 16APSK and 32APSK and PSNR calculation to the system.Specificaly, we used communication toolbox in Matlab for this approach.The model is depicted in Figure 8.The model is defined in the following sections.

**Figure 8.** DVB-S2 proposed model

#### **4.1. MPEG-TS input/output blocks**

In Matlab DVB-S2 model as mentioned earlier they use a random Bernoulli sequence generator for input of the model.To analyze the effect of ACM algorithm on the quality of transmission of a real MPEG stream, we used MPEG-TS stored in a matrix with 188 columns (one MPEG packet) and 100000 rows(number of packets).This is used as the input of the system and at receiver side will be again stored for PSNR calculation.

#### **4.2. PSNR calculation**

10 Will-be-set-by-IN-TECH

manual parameter being set by the user.This parameter can be defined as Es/No,Eb/No or SNR,any how the block will calculate the noise variance and will add a noise with zero mean

Where Es is the signal energy in Joules ,Eb is bit energy in Joules, No is noise power spectral density,Tsym is the symbol period ,K is the information bits per symbol and Tsamp is the

The most important motivation of this project was to implement a DVB-S2 link layer model in matlab which includes ACM algorithm with a complete set of ModCods and also video quality measurement system . To do so we added modulations for 16APSK and 32APSK and PSNR calculation to the system.Specificaly, we used communication toolbox in Matlab for this approach.The model is depicted in Figure 8.The model is defined in the following sections.

*Tsamp* ) <sup>∗</sup> *SNR* (11)

) + 10 log(*k*) (12)

= ( *Tsym*

= ( *Eb No*

to the signal.The relation between Es/No,Eb/No and SNR is as follows:

*Es No*

*Es No*

sample time.

**4. Proposed DVB-S2 model**

**Figure 8.** DVB-S2 proposed model

Peak Signal to Noise Ratio(PSNR)which is a well-known metric for quality measurement of received video, is added to the proposed model.The computation of PSNR is in decibels and uses the Mean Square Error(MSE) which is also an error metric often used for video quality estimation[12].MSE computation is expressed as:

$$MSE = \frac{1}{N} \sum (P\_i^s - P\_i^r)^2 \tag{13}$$

where N represents the number of pixels in the image while P and P are the original image and received image respectively.The PSNR then is computed as follows:

$$PSNR = 10 \log \frac{(2^n - 1)^2}{MSE(I)} \tag{14}$$

where n is the number of luminance bits used in the image.

#### **4.3. Interleaver/deinterleaver**

Interleaving for 16 and 32 APSK are two blocks included to the model based on ETSI instructions.The number of rows and columns of this interleaver are given in table 3.In figure 9 the structure of Interleaver for 16 APSK is given , the only difference with 32 APSK is the number of columns which is 5 instead of 4, consequently number of rows also will be different.

#### **4.4. Modulator/demodulator**

Higher order modulations presented by DVB-S2,provides higher spectrum efficiency comparing to the earlier generation,DVB-S.To analyze the BER performance of DVB-S2 and also adding the ACM algorithm to our model, we include Modulations for 16 and 32 APSK. Modulation block is responsible for mapping and constellation generation to prepare the base band signal for transmission.

#### *4.4.1. 16 APSK modulator*

The modulation constellation for 16 APSK as described in ETSI uses two concentric rings R1 and R2.These rings are uniformly spaced with 4 and 12 points.The constellation is given in the Figure 10.The ratio between R1 and R2,gamma,is defined as:

$$
\gamma = \frac{R\_2}{R\_1} \tag{15}
$$

12 Will-be-set-by-IN-TECH 228 MATLAB – A Fundamental Tool for Scienti c Computing and Engineering Applications – Volume 2 DVB-S2 Model in Matlab: Issues and Impairments <sup>13</sup>

**Figure 9.** Bit Intereaving scheme for 16APSK and normal FECFRAME length

**Figure 10.** 16APSK Signal Constellation[11]

#### *4.4.2. 32 APSK modulator*

Three uniformly spaced rings are defined in the standard using 4 ,12 and 16 PSK points for 32 APSK modulator constellation :R1 ,R2 and R3.The outer ring R3 should be equal to one and gamma1 and gamma2 will define the ratio between rings as follows:

$$
\gamma\_1 = \frac{R\_2}{R\_1} \tag{16}
$$

The symbol order and constellation defined by ETSI is given in Figure 11.

DVB-S2 Model in Matlab: Issues and Impairments 229

At the receiver side,demodulator will receive the signal from AWGN channel which is the noisy signal.To demodulate the signal ,demodulator needs noise variance of the channel for computation of the signal LLR's. For this computation we used approximate LLR algorithm.

In the current DVB-S2 model in Matlab,a Constant Coding and Modulation strategy has been developed .This strategy is based on the worst case adjustment for physical layer which will waste spectral efficiency at most of the time .This waste is costly and can be avoided by using state of the art ACM algorithm ,so any individual user can be treated according to its present

The last step of design in the proposed model is the implementation of the ACM engine.ACM algorithm included in this model is based on the standard required Es/No by ETSI to support a Quasi Error Free transmission.As depicted in table 4,for all 28 combinations of ModCods there is a required level of Es/No.To make decisions among ModCods threshold offsets are provided as equidistance thresholds between adjacent ModCods. The SNR of received signal at the receiver will be sent to ACM block to be used for next frame mode of transmission.

We run simulations for different values of Es/No ranging from -3 to 17 dB and for each ModCod. The LDPC decoder was set to 50 iterations and normal frame size (64,800 bits)

**Figure 11.** 32APSK Signal Constellation[11]

*4.4.3. Demodulator*

**4.5. ACM algorithm**

**5. Simulation and results**

channel state.

$$
\gamma\_2 = \frac{R\_3}{R\_1} \tag{17}
$$

The symbol order and constellation defined by ETSI is given in Figure 11.

**Figure 11.** 32APSK Signal Constellation[11]

### *4.4.3. Demodulator*

12 Will-be-set-by-IN-TECH

Three uniformly spaced rings are defined in the standard using 4 ,12 and 16 PSK points for 32 APSK modulator constellation :R1 ,R2 and R3.The outer ring R3 should be equal to one and

> *<sup>γ</sup>*<sup>1</sup> <sup>=</sup> *<sup>R</sup>*<sup>2</sup> *R*1

> *<sup>γ</sup>*<sup>2</sup> <sup>=</sup> *<sup>R</sup>*<sup>3</sup> *R*1

(16)

(17)

**Figure 9.** Bit Intereaving scheme for 16APSK and normal FECFRAME length

gamma1 and gamma2 will define the ratio between rings as follows:

**Figure 10.** 16APSK Signal Constellation[11]

*4.4.2. 32 APSK modulator*

At the receiver side,demodulator will receive the signal from AWGN channel which is the noisy signal.To demodulate the signal ,demodulator needs noise variance of the channel for computation of the signal LLR's. For this computation we used approximate LLR algorithm.

### **4.5. ACM algorithm**

In the current DVB-S2 model in Matlab,a Constant Coding and Modulation strategy has been developed .This strategy is based on the worst case adjustment for physical layer which will waste spectral efficiency at most of the time .This waste is costly and can be avoided by using state of the art ACM algorithm ,so any individual user can be treated according to its present channel state.

The last step of design in the proposed model is the implementation of the ACM engine.ACM algorithm included in this model is based on the standard required Es/No by ETSI to support a Quasi Error Free transmission.As depicted in table 4,for all 28 combinations of ModCods there is a required level of Es/No.To make decisions among ModCods threshold offsets are provided as equidistance thresholds between adjacent ModCods. The SNR of received signal at the receiver will be sent to ACM block to be used for next frame mode of transmission.

## **5. Simulation and results**

We run simulations for different values of Es/No ranging from -3 to 17 dB and for each ModCod. The LDPC decoder was set to 50 iterations and normal frame size (64,800 bits)

Simulation Parameters Settings

LDPC Decoder output Type Information Part LDPC Decoder Decision Input Type Hard Decision

LDPC Encoder Input Type Bit

Modulator Input Type Bit Modulator Symbol Order Gray Demodulator Output Type Bit Demodulator Decision Type Soft Decision

Channel Noise Factor SNR

is used. Simulation parameters and settings are presented in Table 5. At the LDPC decoder

To evaluate performance of the presented model in terms of BER we run simulation for all ModCods .The results are shown in Figure 12.It can be perceived,that the model performs

In order to analyze the video quality ,instead of sending a Bernoulli sequence , we send MPEG-TS and considering PSNR of received video and QEF requirements.In Figure 13, we showed that deploying the standardized ACM thresholds the model can perform the

transmission with the desired quality with almost 0.3 dB less Es/No required.

**Table 5.** Simulation Parameters and Settings

**Figure 12.** BER Vs. Es/No For Different ModCods

output we calculate BER and number of violated parity checks.

transmissions with the expected BER levels for all ModCods.

LDPC Decoder Number Of Iterations 50

Frame size 64800(Normal)

DVB-S2 Model in Matlab: Issues and Impairments 231

LLR Algorithm Approximate LLR


**Table 4.** Es/No performance at Quasi Error Free PER


**Table 5.** Simulation Parameters and Settings

14 Will-be-set-by-IN-TECH

Mode Spectral efficiency Ideal Es/No(dB)

QPSK1/4 0.490243 -2.35 QPSK1/3 0.656448 -1.24 QPSK2/5 0.789412 -0.30 QPSK1/2 0.988858 1.00 QPSK3/5 1.188304 2.23 QPSK2/3 1.322253 3.10 QPSK3/4 1.487473 4.03 QPSK4/5 1.587196 4.68 QPSK5/6 1.654663 5.18 QPSK8/9 1.766451 6.20 QPSK9/10 1.788612 6.42 8PSK3/5 1.779991 5.50 8PSK2/3 1.980636 6.62 8PSK3/4 2.228124 7.91 8PSK5/6 2.478562 9.35 8PSK8/9 2.646012 10.69 8PSK9/10 2.679207 10.98 16APSK2/3 2.637201 8.97 16APSK3/4 2.966728 10.21 16APSK4/5 3.165623 11.03 16APSK5/6 3.300184 11.61 16APSK8/9 3.523143 12.89 16APSK9/10 3.567342 13.13 32APSK3/4 3.703295 12.73 32APSK4/5 3.951571 13.64 32APSK5/6 4.119540 14.28 32APSK8/9 4.397854 15.69 32APSK9/10 4.453027 16.05

**Table 4.** Es/No performance at Quasi Error Free PER

for FECFRAME Length 64800

is used. Simulation parameters and settings are presented in Table 5. At the LDPC decoder output we calculate BER and number of violated parity checks.

To evaluate performance of the presented model in terms of BER we run simulation for all ModCods .The results are shown in Figure 12.It can be perceived,that the model performs transmissions with the expected BER levels for all ModCods.

**Figure 12.** BER Vs. Es/No For Different ModCods

In order to analyze the video quality ,instead of sending a Bernoulli sequence , we send MPEG-TS and considering PSNR of received video and QEF requirements.In Figure 13, we showed that deploying the standardized ACM thresholds the model can perform the transmission with the desired quality with almost 0.3 dB less Es/No required.

**6. Conclusion**

**Acknowledgement**

codes.

**Author details**

**7. References**

services., 1994.

Bahman Azarbad and Aduwati Binti Sali *University Putra Malaysia, Malaysia*

Radiotelevisione Italiana, 2004.

*Workshop on*, pages 13 –17, oct. 2008.

*Networking*, 2007:10, 2007.

pages 334–356, portland usa, september 2003.

*International Conference on*, pages 1 –5, may 2010.

In this study, we proposed a complete DVB-S2 model for GEO satellite communication system implemented in Matlab.Specifically, we added high order modulation schemes, 16APSK and 32APSK.On top of that, we include ACM algorithm with standard threshold offsets provided by ETSI.Instead of random inputs we used MPEG-TS and we analyzed the quality of the received video streams.By running extensive simulation runs, we showed that the model corresponds to the standard in terms of BER performance.Then we investigate the model performance according to the PSNR of received video and we compared the results with some results in the literature.The results show a 0.3 dB improvement in the required Es/No defined in ACM offsets by ETSI.For future work, we address the study of different ACM thresholds

DVB-S2 Model in Matlab: Issues and Impairments 233

and their performance in terms of spectral efficiency versus PSNR of received video.

This project was funded by Malaysian Ministry of Science, Technology and Innovation (MOSTI) under its eScience fund program '3D Video Transmission over GEO Satellite Networks for Disaster Management Applications' (Project code: 01-01-04-SF1047). We would also take this opportunity to thank Mr Bernhard Shcmidt for his kind cooperation in some

[1] ETSI. Ets 200 421 v1.2.2 digital broadcasting system for television, sound, and data

[2] Alberto Morello and Vittoria Mignone. Dvb-s2 ready for lift off. Technical report, RAI,

[3] B. Azarbad, A. Sali, B.M. Ali, and H.A. Karim. Study of ber in dvb-s2 satellite implemented in matlab. In *Space Science and Communication (IconSpace), 2011 IEEE International Conference on DOI - 10.1109/IConSpace.2011.6015887*, pages 221–224, 2011. [4] J.E. Barcelo, G. Giambene, and M. Castro. Cross-layer optimization of tcp throughput for dvb-s2 links. In *Satellite and Space Communications, 2008. IWSSC 2008. IEEE International*

[5] S. Datta-Barua, P. H. Doherty, S. H. Delay, T. Dehel, and J. A. Klobuchar. Ionospheric scintillation effects on single and dual frequency gps positioning. In *16th international technical meeting of the satellite division of the institute of navigation(ION GPS/GNSS'03)*,

[6] Matteo Berioli, Christian Kissling, and Rémi Lapeyre. Capacity versus bit error rate trade-off in the dvb-s2 forward link. *EURASIP Journal on Wireless Communications and*

[7] V. Boussemart, H. Brandt, and M. Berioli. Subset optimization of adaptive coding and modulation schemes for broadband satellite systems. In *Communications (ICC), 2010 IEEE*

16 Will-be-set-by-IN-TECH 232 MATLAB – A Fundamental Tool for Scienti c Computing and Engineering Applications – Volume 2 DVB-S2 Model in Matlab: Issues and Impairments <sup>17</sup>

**Figure 13.** Es/No Comparison with ETSI Standard

In[8],the authors proposed SNR intervals for different ModCods based on ETSI standard.We also compared SNR performance of our proposed model with their intervals.We consider the PSNR of received video in conjunction with BER.The comparison result is given in Figure 14.

**Figure 14.** SNR Comparison with D.Moad et. al Offsets

## **6. Conclusion**

16 Will-be-set-by-IN-TECH

In[8],the authors proposed SNR intervals for different ModCods based on ETSI standard.We also compared SNR performance of our proposed model with their intervals.We consider the PSNR of received video in conjunction with BER.The comparison result is given in Figure 14.

**Figure 13.** Es/No Comparison with ETSI Standard

**Figure 14.** SNR Comparison with D.Moad et. al Offsets

In this study, we proposed a complete DVB-S2 model for GEO satellite communication system implemented in Matlab.Specifically, we added high order modulation schemes, 16APSK and 32APSK.On top of that, we include ACM algorithm with standard threshold offsets provided by ETSI.Instead of random inputs we used MPEG-TS and we analyzed the quality of the received video streams.By running extensive simulation runs, we showed that the model corresponds to the standard in terms of BER performance.Then we investigate the model performance according to the PSNR of received video and we compared the results with some results in the literature.The results show a 0.3 dB improvement in the required Es/No defined in ACM offsets by ETSI.For future work, we address the study of different ACM thresholds and their performance in terms of spectral efficiency versus PSNR of received video.

## **Acknowledgement**

This project was funded by Malaysian Ministry of Science, Technology and Innovation (MOSTI) under its eScience fund program '3D Video Transmission over GEO Satellite Networks for Disaster Management Applications' (Project code: 01-01-04-SF1047). We would also take this opportunity to thank Mr Bernhard Shcmidt for his kind cooperation in some codes.

## **Author details**

Bahman Azarbad and Aduwati Binti Sali *University Putra Malaysia, Malaysia*

## **7. References**

	- [8] D. Moad, Y. Hadjadj-Aoul, and F. Nait-Abdesselam. Predictive channel estimation for optimized resources allocation in dvb-s2 networks. In *Personal, Indoor and Mobile Radio Communications, 2009 IEEE 20th International Symposium on*, pages 2608 –2612, sept. 2009.
	- [9] M. Smolnikar, T. Javornik, and M. Mohorcic. Target ber driven adaptive coding and modulation in hap based dvb-s2 system. In *Advanced Satellite Mobile Systems, 2008. ASMS 2008. 4th*, pages 262 –267, aug. 2008.
	- [10] ETSI. Tr 126 975 v10.0.0 "digital cellular telecommunications system (phase 2+);universal mobile telecommunications system (umts);lte;performance characterization of the adaptive multi-rate (amr) speech codec" (3gpp tr 26.975 version 10.0.0 release 10), 04 2011.
	- [11] ETSI. En 302 307 v1.2.1 (2009-08)-digital video broadcasting (dvb);second generation framing structure, channel coding and modulation systems for broadcasting,interactive services, news gathering and other broadband satellite applications (dvb-s2), 2009.
	- [12] D. Pradas, Lei Jiang, M.A. Vazquez Castro, P. Barsocchi, and F. Potorti. Satellite phy-layer selector design for video applications in tropical areas. In *Satellite and Space Communications, 2009. IWSSC 2009. International Workshop on*, pages 407 –411, sept. 2009.

© 2012 Sánchez-Salas et al., licensee InTech. This is an open access chapter distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

© 2012 Sánchez-Salas licensee InTech. This is a paper distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

2

(1)

**Wireless Channel Model with** 

**Markov Chains Using MATLAB** 

José Luis Cuevas-Ruíz and Miguel González-Mendoza

Emerging technology developed in last years is the result of the necessity of human to communicate in an effective and fast way from any point of the world. Since some type of loss is always present in a wireless link, new transmission and reception techniques for wireless

Channel modeling is the characterization of the wireless channel; it describes how the characteristics of the sent signal can be affected or what the conditions of the environment are, i.e. frequency, obstacles in the path, etc. The channel model helps to evaluate the performance of the system and to compare different techniques to mitigate the perturbations

The simplest model is the free space loss which considers no obstacles between transmitter and receptor. (Parsons, 2000) However this is an ideal model that does not exist in real scenario because there are other losses in the wireless channel. Another option to describe a channel is by using statistical models which are based on probability density functions (pdf). Although they do not describe the behavior of the sent signal in a complete way, they give a good approximation of the conditions of the channel in a certain moment. (Nakagami, 1960; Abouraddy & Elnoubi, 2000) The main statistical channels and their corresponding pdf are:

Additive White Gaussian Noise, AWGN. This channel only includes the sum of the

<sup>2</sup>

σ 2π 2σ

p x = exp -

1 x-μ

white noise that follows a normal or Gaussian density.

communication systems require the study and characterization of the wireless channel.

so the best fitted solution can be implemented according to the presented problem.

Additional information is available at the end of the chapter

Diana Alejandra Sánchez-Salas,

http://dx.doi.org/10.5772/3338

**1. Introduction** 
