**5.1 Simulation of experimental results**

284 Solar Cells – Thin-Film Technologies

solar cell output is little affected. From this we may conclude that the defect density on the back wafer surface in the experimental as-deposited condition is probably ≤ 1012 cm-2, as also

Voc

1011 37.50 672 0.770 19.40 1012 37.48 662 0.752 18.66 2x1012 37.34 625 0.666 15.54 3x1013 5.47 572 0.156 0.49

Table 5. Calculated values of the solar cell output parameters for different values of the defect density (Nss) on that (rear) surface of the crystalline silicon wafer that is away from the incoming light, indicating that the maximum sensitivity is to the short circuit current density and fill factor. The defect density at the front surface of the c-Si wafer is 1011 cm-2.

In order to understand the sensitivity of the solar cell output to Nss on the RS, we turn to Fig. 6. We note that when Nss on the rear c-Si wafer surface is highest (3x1013 cm-2), there is a huge concentration of trapped holes at the crystalline- amorphous interface on the c-Si wafer side where the high surface defect density exists (dashed line, Fig. 6a). The hole pile-up at the crystalline-amorphous interface slows down the arrival of holes to the back contact (the collector of holes), and encourages the back diffusion of photo-generated electrons in the absorber c-Si wafer. The result is that the electron current is negative over most of the device (Fig. 6b – electron current towards the back contact is negative according to our sign convention). Thus little electron current is collected at the front contact (the collector of electrons, Fig. 6b). In addition, the back-diffusing electrons recombine with the photogenerated holes over most of the absorber c-Si, resulting in poor hole current collection at the back contact. Thus Jsc and FF fall sharply for very high values of Nss at RS. More details

Fig. 5. Effect of changing the defect density (shown in units of cm-2) on the rear surface of the c-Si wafer on (a) the illuminated current density versus voltage characteristics and (b) the band diagram at 0 volts as a function of position in the device under 100 mW cm-2 AM1.5 light. Results are shown for double heterojunction solar cells having a 4 nm P+-a-SiC:H/ 19 nm P+-a-Si:H BSF structure. The defect density on the front surface is 1011 cm-2 for

**Energy (eV)**

**-2 -1.5 -1 -0.5 0 0.5 1 1.5**

**0.001 0.01 0.1 1 10 100 1000**

**(b)**

**Position (micron)**

(mV) FF (%)

obtained by modeling the experimental characteristics (Table 2).

Jsc (mA cm-2)

Nss on RS (cm-2)

can be found in Datta et al (2008).

**-0.2 0 0.2 0.4 0.6 0.8**

**V (Volts)**

**13**

**10<sup>11</sup> 2x10<sup>12</sup> 3x10**

**J (mA cm**

**-2)**

all cases.

**-40 -30 -20 -10 0 10 20**

**(a)**

Simulation of a range of experimental results on HIT cells developed by the Sanyo group and available in the literature (Maruyama et al, 2006, Takahama et al, 1992, Sawada et al, 1994, Taguchi et al, 2008) has been undertaken to extract typical parameters that characterize state-of-the-art HIT cells on N-type c-Si substrates, as well as to gain an insight into carrier transport and the general functioning of these cells. Both "front" HIT cells having an amorphous/ crystalline heterojunction on the emitter side only - where the light enters (Takahama et al, 1992), and "double" HIT cells having heterojunctions on both ends of the c-Si wafer (Maruyama et al, 2006, Sawada et al, 1994, Taguchi et al, 2008) have been simulated. The cells have the structure: ITO/ P-a-Si:H/ I-a-Si:H/ textured N-c-Si/ N-c-Si BSF/ metal (front HIT) (Takahama et al, 1992) and ITO/ P-a-Si:H/ I-a-Si:H/ textured N-c-Si/ I-a-Si:H/ N++-a-Si:H/ metal (double HIT) (Maruyama et al, 2006, Sawada et al, 1994, Taguchi et al, 2008). In Taguchi et al (2008), after depositing the undoped and doped a-Si:H layers on both ends of the c-Si wafer, ITO films were sputtered on both sides, followed by screen-printed silver grid electrodes. Simulation of these cells (Maruyama et al, 2006, Takahama et al, 1992, Sawada et al, 1994) gives us an insight into the parameters that play a crucial role in improving HIT cell performance. On the other hand, the article by Taguchi et al (2008) gives the temperature dependence of the dark current density - voltage characteristics and the solar cell output parameters as a function of the thickness of the intrinsic amorphous layer sandwiched between the emitter P-a-Si:H and the main absorber N-c-Si. A study of the temperature dependence of the dark J-V characteristics is particularly important to understand the carrier transport mechanism in these devices. The parameters extracted by such modeling (Table 3) will be used in the following sections to calculate the sensitivity of the solar cell performance to various controlling factors.

In Table 6 we compare our simulation and experimental results of various HIT cells on Ntype c-Si substrates (Takahama et al, 1992, Sawada et al, 1994, Maruyama et al, 2006). Modeling indicates that improvements in Voc could be brought about (a) by going from a

Computer Modeling of Heterojunction

<sup>n</sup> p) cm2/volt-sec

I-a-Si:H thickness(nm)

Half 30 (6) 1.5 4x1011

Normal 25 (5) 3.0 1.5x1011

Double 15 (3) 6.0 1010

Triple 15 (3) 9.0 1010

m m) (Taguchi et al, 2008).

**288.1 K 298.2 K 308.2 K 317.0 K 327.0 K 336.6 K**

**10-8**

**10-6**

**10-4**

**Current density (A cm-2)**

**10-2**

**10<sup>0</sup>**

Cell name

with Intrinsic Thin Layer "HIT" Solar Cells: Sensitivity Issues and Insights Gained 287

Jsc (mA cm-2) Voc

E 37.4 0.699 0.776 20.3 M 37.2 0.702 0.803 21.0

E 37.2 0.711 0.773 20.4 M 37.0 0.712 0.799 21.0

E 36.5 0.718 0.747 19.6 M 36.7 0.717 0.766 20.2

E 36.4 0.715 0.717 18.7 M 36.6 0.714 0.750 19.6

> **283 K 295 K 300 K 311 K 323 K 345 K**

**0 0.2 0.4 0.6 0.8**

**Voltage (volts)**

**(b) Model**

**1.006< n < 1.05**

(volts) FF (%)

0.775\* 20.2\*

0.774\* 20.4\*

0.747\* 19.7\*

0.718\* 18.8\*

**n = 1.25**

Nss (cm-2)

Table 7. Modeling (M) of the experimental (E) results of N-type HIT solar cells, having different thickness of the I-a-Si:H layer on the emitter side. Nss is the defect density on that surface of the c-Si wafer that faces the emitter. The quantities given with astericks are the calculated values of FF and efficiency corrected for the series resistance of the contacts (2.8

**n = 1.20**

Fig. 7. (a) Experimental (Taguchi et al, 2008) and (b) simulated dark J-V characteristics of the cell with "Normal" thickness I-a-Si:H layer at the P-a-Si:H/ N-c-Si interface at various temperatures, and (c) the IQE of the same cell under AM1.5 illumination and 0 volts compared to the experimental IQE of a typical Sanyo cell (Maruyama et al,2004).

**0.4 0.6 0.8 1 1.2**

**10-13**

**10-10**

**10-7**

**10-4**

**0.1**

**Wavelength (microns)**

**Model Experiment** 

**0 0.2 0.4 0.6 0.8 1 1.2**

**(c)**

**IQE**

**0 0.2 0.4 0.6 0.8**

**(a) Experiment**

**Voltage (volts)**

**n > 2**


Table 6. Comparison between measured (E): and modeled (M) solar cell output of front (F) and double (D) N-c-Si HIT cells with textured ITO front contact, developed by Sanyo over the years. "" is the lifetime of the minority carriers in the c-Si wafer.

front HIT to a double HIT structure, (b) by decreasing the defects on the front surface of the c-Si wafer that faces the emitter layer and (c) by improving the lifetime of the minority carriers in crystalline silicon. Results indicate that it is by decreasing Nss on the front surface of the c-Si wafer, that the largest increase in Voc could be achieved, without any fall in FF.

We next used ASDMP to simulate the experimental results of Taguchi et al (2008). Here we have concentrated on the effect of varying the thickness of the intrinsic amorphous silicon layer at the P-amorphous emitter/ N-c-Si heterojunction. The terminology "normal" has been used to represent the thickness of the front I-a-Si:H buffer layer in the cell that yields the highest efficiency (Table 7). Modeling reveals that the I-a-Si:H thickness for this case is 3 nm. The I-a-Si:H buffer layers (front) in the cells named "Half", "Double" and "Triple" by Taguchi et al (2008) have therefore been assigned thicknesses of 1.5 nm, 6 nm and 9 nm respectively in the simulations. Results of our simulation of the experimental light J-V characteristics (Taguchi et al, 2008) as a function of this I-a-Si:H layer thickness are given in Table 7 and the input parameters extracted by such modeling, and also of the dark J-V characteristics (Figs. 7a and 7b) and typical internal quantum efficiencies of Sanyo N-c-Si HIT cells (Fig. 7c, Maruyama et al, 2006 ), are given in Table 3 (the same table that contains the extracted parameters of P-type HIT cells). Since modeling does not consider the resistance of the contacts; these results had to be modified by taking into account the series resistance of the contacts. The addition of the series resistance did not modify Voc and Jsc but allowed to perfectly match the experimental fill factor and therefore the efficiency of the Sanyo HIT solar cells (Taguchi et al, 2008). In Table 7 we show the solar cell output parameters as obtained directly by modeling, without resistive losses (which gives an upper limit for the FF and therefore the efficiency) and the values of the FF and efficiency after considering the constant series resistance (marked by astericks). This resistance, comprising resistive losses in the TCO, the silver grid and the contacts, was estimated by Taguchi et al (2008) to be ~2.8 m.

Table 6. Comparison between measured (E): and modeled (M) solar cell output of front (F) and double (D) N-c-Si HIT cells with textured ITO front contact, developed by Sanyo over

front HIT to a double HIT structure, (b) by decreasing the defects on the front surface of the c-Si wafer that faces the emitter layer and (c) by improving the lifetime of the minority carriers in crystalline silicon. Results indicate that it is by decreasing Nss on the front surface of the c-Si wafer, that the largest increase in Voc could be achieved, without any fall in FF. We next used ASDMP to simulate the experimental results of Taguchi et al (2008). Here we have concentrated on the effect of varying the thickness of the intrinsic amorphous silicon layer at the P-amorphous emitter/ N-c-Si heterojunction. The terminology "normal" has been used to represent the thickness of the front I-a-Si:H buffer layer in the cell that yields the highest efficiency (Table 7). Modeling reveals that the I-a-Si:H thickness for this case is 3 nm. The I-a-Si:H buffer layers (front) in the cells named "Half", "Double" and "Triple" by Taguchi et al (2008) have therefore been assigned thicknesses of 1.5 nm, 6 nm and 9 nm respectively in the simulations. Results of our simulation of the experimental light J-V characteristics (Taguchi et al, 2008) as a function of this I-a-Si:H layer thickness are given in Table 7 and the input parameters extracted by such modeling, and also of the dark J-V characteristics (Figs. 7a and 7b) and typical internal quantum efficiencies of Sanyo N-c-Si HIT cells (Fig. 7c, Maruyama et al, 2006 ), are given in Table 3 (the same table that contains the extracted parameters of P-type HIT cells). Since modeling does not consider the resistance of the contacts; these results had to be modified by taking into account the series resistance of the contacts. The addition of the series resistance did not modify Voc and Jsc but allowed to perfectly match the experimental fill factor and therefore the efficiency of the Sanyo HIT solar cells (Taguchi et al, 2008). In Table 7 we show the solar cell output parameters as obtained directly by modeling, without resistive losses (which gives an upper limit for the FF and therefore the efficiency) and the values of the FF and efficiency after considering the constant series resistance (marked by astericks). This resistance, comprising resistive losses in the TCO, the silver grid and the contacts, was estimated by Taguchi et al

τ ms

Voc **mV** 

M FS- 4x1011 0.23 643 37.89 0.775 18.88

Jsc

— — 638 37.90 0.775 18.74

— — 644 39.40 0.790 20.05

— 1.20 718 38.52 0.790 21.85

<sup>1011</sup>2.00 713 38.60 0.797 21.93

RS -1011 0.5 658 39.03 0.783 20.11

mA cm-2 FF

%

Nss (cm-2) in defective layers

HIT Reference

D-I

D-II

(2008) to be ~2.8 m.

<sup>F</sup>Takahama et al,

Swada et al,

Maruyama et al,

<sup>1992</sup><sup>E</sup> —

<sup>1994</sup><sup>E</sup> —

<sup>2006</sup><sup>E</sup> —

M FS-4x1011

<sup>M</sup>FS & RS -

the years. "" is the lifetime of the minority carriers in the c-Si wafer.


Table 7. Modeling (M) of the experimental (E) results of N-type HIT solar cells, having different thickness of the I-a-Si:H layer on the emitter side. Nss is the defect density on that surface of the c-Si wafer that faces the emitter. The quantities given with astericks are the calculated values of FF and efficiency corrected for the series resistance of the contacts (2.8 m m) (Taguchi et al, 2008).

Fig. 7. (a) Experimental (Taguchi et al, 2008) and (b) simulated dark J-V characteristics of the cell with "Normal" thickness I-a-Si:H layer at the P-a-Si:H/ N-c-Si interface at various temperatures, and (c) the IQE of the same cell under AM1.5 illumination and 0 volts compared to the experimental IQE of a typical Sanyo cell (Maruyama et al,2004).

Computer Modeling of Heterojunction

**0.8 ,**

 **, , ,** **Half Normal Double Triple**

**(d) 0.66**

**0 20 40 60 80**

**Temperature (°C)**

**0.6**

**0.7**

**(c)**

**0.74**

**FF**

**0.78**

**0.82**

**(a)**

**0.65**

**V**

 **(volts)**

**oc**

**0.7**

**0.75**

symbols correspond to measured data.

and absorption coefficient of the materials.

with Intrinsic Thin Layer "HIT" Solar Cells: Sensitivity Issues and Insights Gained 289

**32**

**22**

**16**

**0 20 40 60 80**

**Temperature (°C)**

**18**

**Efficiency (%)**

**20**

**(b)**

**34**

**J**

 **(mA cm-2)**

**sc**

**36**

**38**

**40**

Fig. 8. Variation of (a) Voc, (b) Jsc, (c) FF and (d) Efficiency as a function of temperature in Nc-Si HIT solar cells having different thickness of the undoped a-Si:H layer (half, normal, double, triple) at the P-a-Si:H/ N-c-Si interface. The lines are modeling results, while

lower temperatures, also means that the cell is now more resistive, resulting in a fall in the FF for the cells "double" and "triple" (Fig. 8c), where performance is dominated by the undoped a-Si:H layer. Also, for the value of the band gap assumed for the I-a-Si:H layer (Table 8), the holes are able to overcome the positive field barrier at the a-Si/ c-Si interface by thermionic emission to get collected at the front contact. Thermionic emission decreases at lower temperatures, resulting in a loss of FF for cells "double" and "triple". For cells "Normal" and "Half", performance is dominated by the temperature-independent resistance of the contacts; therefore no fall in FF is seen. Finally Fig. 8 (b), indicates that the calculated Jsc is constant with temperature, while the measured Jsc increases slightly. This is because the model does not take account of the temperature dependence of the band gap

**5.2 Effect of I-a-Si:H buffer layers on the performance of N- type HIT solar cells** 

HIT solar cells give efficiencies comparable to those of c-Si cells because of the amazing passivating properties of the intrinsic a-Si:H layers. In fact it is this layer that gives this group of solar cells its name – "HIT". We have already discussed that it is very effective in passivating the defects on the surface the c-Si wafer. However, it must be kept as thin as possible, as it reduces the fill factor when thick (Table 7). We have next studied the effect on

The dangling bond defect density in the I-a-Si:H layer, as extracted from modeling, is 9x1016 cm-3 and its Urbach enegy is 70 meV (Table 8). We have assumed the same values for these quantities, as well as of the capture cross-sections of the defect states inside the I-a-Si:H layer in all the cases of Table 7. Modeling indicates that in order to simulate the lower Voc's of the Taguchi et al (2008) cells "Normal" and "Half", the defect density on the surface of the c-Si wafer itself in these cases, must be higher (Table 7). We may justify this fact by assuming that a very thin buffer layer may not be as effective in passivating the defects on the surface of the c-Si wafer as a thicker buffer layer. In Table 7, we also had to assume higher carrier motilities in the front amorphous layers for the cases Half and Normal to match both the higher FF and lower Voc for these cases. Increasing carrier mobilities over the front amorphous layers improves hole collection and therefore the FF. However, higher electron mobility allows more electrons to recto-diffuse towards the front contact (collector of photogenerated holes) and recombine with holes, thus reducing Voc. However the main reason for the lower Voc for thinner I-a-Si:H layers (Half and Normal) is our assumption of higher surface defect density on the c-Si wafer in these cases (Table 7).

The experimental dark J-V characteristics of the cell "Normal" is shown in Fig. 7 (a) and the model curves in Fig. 7 (b). The diode ideality factor, n, calculated in the voltage range 0.4 volts V< 0.8 volts, from the model dark characteristics is 1.25 and compares well with the experimental value of 1.2. This value of "n" indicates that it is the diffusion current that dominates transport in this voltage range for N-c-Si HIT cells, as is also the case for homojunction c-Si solar cells. On the other hand, in the voltage range 0.1 volts< V< 0.4 volts, "n" calculated from the modeling data (Fig. 7b) is ~1, which indicates that the conductivity continues to be dominated by diffusion. The value of the slope, calculated from the experimental curves of Taguchi et al (2008) in the voltage range 0.1 volts < V < 0.4 is smaller than that of the recombination current model and remained almost constant for each temperature. The corresponding value of "n" derived from the experimental curves is greater than 2 (Fig. 7a). Taguchi et al (2008) therefore assumed that this is tunneling-limited current. If the value of "n" extracted from the experimental curves, had been due to current dominated by recombination, ASDMP would also have been able to reproduce this value of 'n', since the recombination current model is included in ASDMP. In fact ASDMP has already been used to successfully model forward and dark reverse bias characteristics of a-Si:H based PIN solar cells, where recombination plays a dominant role (Tchakarov et al, 2003). The fact that the value of "n" calculated from the ASDMP-generated dark J-V curves is ~1, while that from experiments is different, indicates that the current over this region is dominated by a phenomenon *not* taken account of by ASDMP (e.g. tunneling). Over this voltage region therefore the current could be dominated by the tunneling of electrons. However, as pointed out by Taguchi et al (2008), "the current density in this region is sufficiently low compared to the levels of short-circuit current density and does not affect solar cell performance". It therefore appears that cell performance under AM1 or AM1.5 light is not affected by tunnelling of electrons, although this phenomenon probably exists for V< 0.4 volts.

Fig. 8 shows the temperature dependence of the solar cell output parameters. We have made the comparison between experiments (Taguchi et al, 2008) and modeling, after taking account of the series resistance of the contacts that is independent of temperature. As the temperature decreases, carrier density decreases. It means less carrier recombination and therefore a higher Voc at lower temperatures (Fig. 8a). However lower carrier density at

The dangling bond defect density in the I-a-Si:H layer, as extracted from modeling, is 9x1016 cm-3 and its Urbach enegy is 70 meV (Table 8). We have assumed the same values for these quantities, as well as of the capture cross-sections of the defect states inside the I-a-Si:H layer in all the cases of Table 7. Modeling indicates that in order to simulate the lower Voc's of the Taguchi et al (2008) cells "Normal" and "Half", the defect density on the surface of the c-Si wafer itself in these cases, must be higher (Table 7). We may justify this fact by assuming that a very thin buffer layer may not be as effective in passivating the defects on the surface of the c-Si wafer as a thicker buffer layer. In Table 7, we also had to assume higher carrier motilities in the front amorphous layers for the cases Half and Normal to match both the higher FF and lower Voc for these cases. Increasing carrier mobilities over the front amorphous layers improves hole collection and therefore the FF. However, higher electron mobility allows more electrons to recto-diffuse towards the front contact (collector of photogenerated holes) and recombine with holes, thus reducing Voc. However the main reason for the lower Voc for thinner I-a-Si:H layers (Half and Normal) is our assumption of higher

The experimental dark J-V characteristics of the cell "Normal" is shown in Fig. 7 (a) and the model curves in Fig. 7 (b). The diode ideality factor, n, calculated in the voltage range 0.4 volts V< 0.8 volts, from the model dark characteristics is 1.25 and compares well with the experimental value of 1.2. This value of "n" indicates that it is the diffusion current that dominates transport in this voltage range for N-c-Si HIT cells, as is also the case for homojunction c-Si solar cells. On the other hand, in the voltage range 0.1 volts< V< 0.4 volts, "n" calculated from the modeling data (Fig. 7b) is ~1, which indicates that the conductivity continues to be dominated by diffusion. The value of the slope, calculated from the experimental curves of Taguchi et al (2008) in the voltage range 0.1 volts < V < 0.4 is smaller than that of the recombination current model and remained almost constant for each temperature. The corresponding value of "n" derived from the experimental curves is greater than 2 (Fig. 7a). Taguchi et al (2008) therefore assumed that this is tunneling-limited current. If the value of "n" extracted from the experimental curves, had been due to current dominated by recombination, ASDMP would also have been able to reproduce this value of 'n', since the recombination current model is included in ASDMP. In fact ASDMP has already been used to successfully model forward and dark reverse bias characteristics of a-Si:H based PIN solar cells, where recombination plays a dominant role (Tchakarov et al, 2003). The fact that the value of "n" calculated from the ASDMP-generated dark J-V curves is ~1, while that from experiments is different, indicates that the current over this region is dominated by a phenomenon *not* taken account of by ASDMP (e.g. tunneling). Over this voltage region therefore the current could be dominated by the tunneling of electrons. However, as pointed out by Taguchi et al (2008), "the current density in this region is sufficiently low compared to the levels of short-circuit current density and does not affect solar cell performance". It therefore appears that cell performance under AM1 or AM1.5 light is not affected by tunnelling of electrons, although this phenomenon probably exists

Fig. 8 shows the temperature dependence of the solar cell output parameters. We have made the comparison between experiments (Taguchi et al, 2008) and modeling, after taking account of the series resistance of the contacts that is independent of temperature. As the temperature decreases, carrier density decreases. It means less carrier recombination and therefore a higher Voc at lower temperatures (Fig. 8a). However lower carrier density at

surface defect density on the c-Si wafer in these cases (Table 7).

for V< 0.4 volts.

Fig. 8. Variation of (a) Voc, (b) Jsc, (c) FF and (d) Efficiency as a function of temperature in Nc-Si HIT solar cells having different thickness of the undoped a-Si:H layer (half, normal, double, triple) at the P-a-Si:H/ N-c-Si interface. The lines are modeling results, while symbols correspond to measured data.

lower temperatures, also means that the cell is now more resistive, resulting in a fall in the FF for the cells "double" and "triple" (Fig. 8c), where performance is dominated by the undoped a-Si:H layer. Also, for the value of the band gap assumed for the I-a-Si:H layer (Table 8), the holes are able to overcome the positive field barrier at the a-Si/ c-Si interface by thermionic emission to get collected at the front contact. Thermionic emission decreases at lower temperatures, resulting in a loss of FF for cells "double" and "triple". For cells "Normal" and "Half", performance is dominated by the temperature-independent resistance of the contacts; therefore no fall in FF is seen. Finally Fig. 8 (b), indicates that the calculated Jsc is constant with temperature, while the measured Jsc increases slightly. This is because the model does not take account of the temperature dependence of the band gap and absorption coefficient of the materials.

## **5.2 Effect of I-a-Si:H buffer layers on the performance of N- type HIT solar cells**

HIT solar cells give efficiencies comparable to those of c-Si cells because of the amazing passivating properties of the intrinsic a-Si:H layers. In fact it is this layer that gives this group of solar cells its name – "HIT". We have already discussed that it is very effective in passivating the defects on the surface the c-Si wafer. However, it must be kept as thin as possible, as it reduces the fill factor when thick (Table 7). We have next studied the effect on

Computer Modeling of Heterojunction

(dashed line, Fig. 10b).

**0**

**-6x105**

**-4x105**

**Field on holes (volt cm-1)**

**-2x105**

**-40**

**-20**

**(a)**

**0**

**J (mA cm-2**

**)**

**20**

**40**

with Intrinsic Thin Layer "HIT" Solar Cells: Sensitivity Issues and Insights Gained 291

**Energy (eV)**

Fig. 9. (a) The light J-V characteristics and (b) the band diagram under AM1.5 light bias and

**-1.5 -1 -0.5 0 0.5 1 1.5**

**(b)**

**0.001 0.01 0.1 1 10 100 1000**

**0 0.005 0.01 0.015 0.02**

**Position (microns)**

**Position (microns)**

**1.5x1011 cm-2 1012 cm-2 1013 cm-2**

In Fig. 10 (b) we plot the trapped hole population over the front part in N-c-Si double HIT cells under AM1.5 bias light at 0 volts. We note that when Nss on the front c-Si wafer surface is the highest (1013 cm-2), there is a huge concentration of holes at the amorphous / crystalline (a-c) interface on the c-Si wafer side, where the high surface defect density exists

Fig. 10. Plots of (a) the electric field on the holes and (b) the trapped hole density over the front part of the device as a function of position in the entire device under illumination and short-circuit conditions, in N-c-Si HIT cells for different densities of defects on the front face of the c-Si wafer. The amorphous/crystalline (a-c) interface is indicated on (a) and (b).

**1010**

**(b)**

**a-c interface**

**1012**

**1014**

**Trapped hole density (cm**

**-3)**

**1016**

**1018**

**1020**

**0.01 0.1**

**(a) a-c interface**

**Position (microns)**

**1.5x1011 cm-2 1012 cm-2 1013 cm-2**

The hole pile-up at the amorphous / crystalline interface slows down the arrival of holes to the front contact (the collector of holes), and attracts photo-generated electrons, i.e., encourages their back diffusion towards the front contact. The result is that the electrns back-diffuse towards the front contact and recombine with the photo-generated holes resulting in poor carrier collection (Rahmouni et al, 2010). Thus Jsc and FF fall sharply for high values of Nss on the front surface of c-Si (Table 8). In fact we may arrive at the same conclusion also from Fig. 9 (b), which shows that for Nss = 1013 cm-2, there is almost no band bending or electric field in the c-Si wafer (the main absorber layer) so that carriers cannot be collected, resulting in the general degradation of all aspects of solar cell performance.

0 volts for different values of Nss on the front face of the N type c-Si wafer..

**0 0.2 0.4 0.6 0.8**

**V (volts)**

**1.5x1011 cm-2 1012 cm-2 1013 cm-2**

solar cell performance of varying the defect density in this layer itself. For this purpose, we have assumed its thickness to be 6 nm (as in case "Double") where the best passivation of Nss has been attained (Table 7). An increase in the defect density in the I-a-Si:H layer may affect the defect density (Nss) on c-Si, but in this study we assume Nss to be constant. We have found (Rahmouni et al, 2010) that unless the defect density of this intrinsic layer is greater than 3x1017 cm-3, no significant loss of cell performance occurs. Similar conclusions have been reached in the case of HIT cells on P-type c-Si wafers.
