**Author details**

Bo Yuan *University of Minnesota-Twin Cities, USA* 

Li Li *Nanjing University, China* 

Zhongfeng Wang *Broadcom Corporation, USA* 

## **7. References**


[8] K. Seth, K. N. Viswajith, S. Srinivasan, and V. Kamakoti. Ultra folded high-speed architectures for Reed-Solomon decoders: proceeding of International. Conference on VLSI Design, 3-7 Jan. 2006.

286 Optical Communication

**6. Conclusion** 

**Author details** 

Zhongfeng Wang

**7. References** 

*Nanjing University, China* 

*Broadcom Corporation, USA* 

975.1, Feb. 2004.

Circuits and Systems II 2006; 53(11) 1245-1249.

*University of Minnesota-Twin Cities, USA* 

Bo Yuan

Li Li

With the evolution of optical network, the employed FEC scheme has been developed in several generations. The requirement on high data rata and large coding gain is always challenging the design for efficient FEC decoder. In this chapter, targeted to different types of optical transmission networks, ranging from local Ethernet to long-haul backbone system, different FEC solutions with efficient VLSI implementations are discussed. For shortdistance networks, two kinds of area-efficient high-speed RS decoders are analyzed for the scenario. For mediate distance networks, which require some tradeoff between decoding performance and hardware efficiency, the introduced RS burst-error decoder can be employed to meet such requirement. For long-haul systems, which have stringent requirement on decoding performance, some candidate FEC schemes targeted to the future 100Gbps era are discussed. In summary, these various FEC architectures and schemes are

good candidates for their specific targeted optical transmission applications.

[1] 100G Forward Error Correction White Paper, OIF, OIF-FEC-100G-01.0, May. 2010. [2] Forward Error Correction for high bit-rate DWDM Submarine System, Telecommunication Standardization Section, International Telecom Union, ITU-T G.

[4] E. R. Berlekamp. Algebraic coding theory. Newyork: McGraw-Hill; 1968.

decoders. IEEE Transactions on VLSI Systems 2001; 9(5) 641-655.

[3] H. -Y. Hsu, A.-Y. Wu and J. -C. Yeo. Area-efficient VLSI design of Reed-Solomon decoder for 10Gbase-LX4 optical communication systems. IEEE Transactions on

[5] D. V. Sarwate and N. R. Shanbhag. High-speed architectures for Reed-Solomon

[6] H. M. Shao, T. K. Truong, L. J. Deutsch, J. H. Yuen and I. S. Reed. A VLSI design of a pipeline Reed-Solomon decoder. IEEE Transactions on Computer 1985; 34(5) 393-403. [7] H. Lee. A High-speed low-complexity Reed-Solomon decoder for optical communications. IEEE Transactions on Circuits and Systems II 2005; 52(8) 461-465.

