**1. Introduction**

14 Optical Communication

profile, Y-shaped branch waveguide and Mach-Zehnder interferometer in photonic crystal structure with triangular lattice were numerically demonstrated. The CIP method showed reasonable results of branch circuit and the filtering characteristics by using cavity. Also for Mach-Zehnder interferometer, numerical results of electric field profile by CIP method

For example, designing of filtering device for microwave communication or guiding device for optical fiber communication system, the CIP method is expected to show superior performance in accuracy compared with conventional FDTD method. Application of CIP method to design electromagnetic or optical signal processing devices with some defects in

Author would like to express his thanks to Mr. H. Terashima, Ms. Y. Zhang, Mr. T. Maruyama, and Mr. S. Hironaka for their engagement as master course research in Graduate School of

[1] Yasumoto, K. ed. (2006). *Electromagnetic Theory and Applications for Photnic Crystals*, CRC

[2] Noda, S. & Baba, T. ed. (2003). *Roadmap on Photonic Crystals*, Kluwer Academic

[3] Bjarklev, A., Broeng, J. & Bjarklev, A. S. (2003). *Photonic Crystal Fibres*, Kluwer Academic

[4] Yee, K. S. "Numerical solution of initial boundary value problems involving Maxwell's equations in isotropic media, "*IEEE Transactions on Antennas and Propagation*, Vol.AP-14,

[5] Taflove, A. ed.(1998) *Advances in Computational Electrodynamics - The Finite-Difference*

[6] Yabe, T., Feng X. & Utsumi T. "The constrained interpolation profile method for multiphase analysis, "*Journal of Computational Physics*, Vol.169, 2001, pp.556-593. [7] Okubo, K. & Takeuchi, N. "Analysis of an electromagnetic field created by line current using constrained interpolation profile method, "*IEEE Transactions on Antennas and*

[8] Ishimaru, A. (1991). *Electromagnetic Wave Propagation, Radiation, and Scattering*, Chap. 11,

[9] Maeda, H., Terashima, H., Maruyama, T. & Zhang, Y. (2011). *Numerical Analysis of Electromagnetic Wave Scattered by High-Contrast Dielectric Cylinder Using CIP Method*, *Proc. of The 1st International Workshop on Information Networking and Wireless Communications (INWC 2011), in conjunction with The 14th International Conference on Network-Based*

*Time-Domain Method*, Artech House Publishers, 0-89006-834-8, Boston.

implemented experimental result of the structure for typical frequencies.

Fukuoka Institute of Technology, Fukuoka, Japan from 2010 to 2012.

*Dept. of Information and Communication Eng., Fukuoka Institute of Technology, Japan*

periodic structure can be designed by CIP method.

Press, 0-84933677-5, New York.

Publishers, 1-4020-7464-6, Boston.

Publishers, 1-4020-7610-X, Boston.

*Propagation*, Vol. 55, No. 1, Jan. 2007, pp.111-119.

*Information Systems (NBiS 2011)*, pp. 491-496.

Prentice-Hall International, 0-13-273871-6, New Jersey.

No.4, May 1966, pp.302-307.

**Acknowledgment**

**Author details** Hiroshi Maeda

**5. References**

Today's microelectronics, whose main driving force of development has always been the needs in computing devices, has achieved exceptionally great results over the last decade.

The exponential growth in performance of microelectronic devices, predicted in 1965 by Gordon Moore and formulated as an empirical law, was sufficiently accurate for more than 45 years: the computing power of single-chip microprocessor-based systems increased almost by a factor of four every three years. Simultaneously with the improvement of parameters of ICs the performance of supercomputers has increased. The performance has increased both due to a reduced duration of a cycle and due to pipelining and parallelization of computations. Currently, petaflops computers are built on the basis of 105 - 106 single-chip processors with a clock frequency of 10 GHz.

At the same time, the analysis of the element base of microelectronics has shown that the main obstacle to improve the performance of computer devices is the problem of connections, both on the surface of individual substrates, and between them. The area occupied by conductors is about 70% of the overall area of a crystal itself in modern VLSI. The total length of conductors exceeds the linear dimensions of a crystal by more than a thousand times. The energy spent on charging the conductors is 60-70% of all energy losses. Placement of the conductors on the surface of a crystal requires significant technical efforts, while the limit value of capacitance of a conductor, which is 10-11 F/m., is attainable [1]. On schematic level, there is also a problem of RC propagation delay in the connections. And consequently, the velocity of signal propagation in ICs is much lower than that of light (5-30 times) depending on the degree of integration.

Thus, the main source of increasing the performance of computers at the previous period of their evolution, which is concluded in increasing the performance of a single gate and the degree of integration, is nearly exhausted. Thus, it can be stated that the clock frequency of computers is determined by circuit limitations, rather than by physical and technological ones.

© 2012 Kostsov et al., licensee InTech. This is an open access chapter distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. © 2012 Kostsov et al., licensee InTech. This is a paper distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

No less complicated problems arise while exchanging information between processor chips. With an increase in their size the number of inter-chip connections increases as well. And this reduces the clock speed by almost an order of magnitude. With decreasing the cycle duration, the above-mentioned connections play an increasingly significant role.

From the stated-above it can be concluded that the solution to the problem of connections and thus further improvement of the performance of computer devices can be obtained by the following ways:


It follows from general physical considerations that a simple way of introducing the "third dimension" into the structure of communications is using optical links. Such channels have the following advantages:


There is always an interest in the use of optics for high-performance computer devices. Recently, a special attention of developers of such devices has been drawn to the development of a new element base, creation of optoelectronic integrated circuits (OEIC), for the organization of inter-IC and inter-processor connections in order to attain high throughput and low power consumption [1-4].

The optical communication bandwidth over short distances within a few millimeters already competes with electric conductors with sufficiently low energy consumption, up to 1 pJ/bit/m or less. The placement of optical communication channels directly on the chip surface can significantly reduce this bandwidth. The reports are already known about the first experimental data on providing the density of the bandwidth 37 Gbit/s/mm2 and higher by using a switched CMOS pair of a vertical-cavity surface-emitting laser (VCSEL) and a CMOS-compatible avalanche photodetector (CMOS-APD) system. The frequency of switching light sources VCSEL, electro-optic modulators MQW based on superlattices GaAs / GaAlAs, InGaAsP, etc. as well as that of their corresponding photodetectors has already reached values of 20 50 GHz, which in the short term, can grow up to 70 80 GHz. The level of technology of constructing field-programmable smart-pixel arrays and FP-SPA systems based on the use of optical channels in free space, is now able to provide the exchange of information between the two surfaces at a rate exceeding 10 Tbit/cm2.

56 Optical Communication

the following ways:

the following advantages:

No less complicated problems arise while exchanging information between processor chips. With an increase in their size the number of inter-chip connections increases as well. And this reduces the clock speed by almost an order of magnitude. With decreasing the cycle

From the stated-above it can be concluded that the solution to the problem of connections and thus further improvement of the performance of computer devices can be obtained by

 increasing the degree of parallelization of information processing at all levels down to elementary operations (a maximum depth of parallelization) and increasing the decentralization of functions of storage, control, and data processing, and transition from long logical links within the surface of a chip to the local relations between the

It follows from general physical considerations that a simple way of introducing the "third dimension" into the structure of communications is using optical links. Such channels have

 A high degree of parallelism of the information transfer from plane to plane makes possible to use highly parallel algorithms for processing (down to elementary

 Capability of optical synchronization allowing delivering a synchronization signal to any point of a chip practically without delay, e.g. from one light source outside an IC. Optical communications channels are free from parasitic effects of the mutual influence because of the neutrality of photons. With increasing the clock frequencies (especially in the gigahertz frequency range), the advantages of optical signals grow as capacitive coupling between electronic conductors with increasing frequency grows as well.

There is always an interest in the use of optics for high-performance computer devices. Recently, a special attention of developers of such devices has been drawn to the development of a new element base, creation of optoelectronic integrated circuits (OEIC), for the organization of inter-IC and inter-processor connections in order to attain high

The optical communication bandwidth over short distances within a few millimeters already competes with electric conductors with sufficiently low energy consumption, up to 1 pJ/bit/m or less. The placement of optical communication channels directly on the chip surface can significantly reduce this bandwidth. The reports are already known about the first experimental data on providing the density of the bandwidth 37 Gbit/s/mm2 and higher by using a switched CMOS pair of a vertical-cavity surface-emitting laser (VCSEL) and a CMOS-compatible avalanche photodetector (CMOS-APD) system. The frequency of switching light sources VCSEL, electro-optic modulators MQW based on superlattices GaAs / GaAlAs, InGaAsP, etc. as well as that of their corresponding photodetectors has already

operations), and thus to create high-performance computing.

neighboring gates, i.e. by transition to a VLSI with a homogeneous structure; transition from connecting chips placed in a plane to 3D packs of VLSIs from these

chips and to their vertical interconnections.

throughput and low power consumption [1-4].

duration, the above-mentioned connections play an increasingly significant role.

Currently, however, optical communication channels are used only for the information transfer problems. Their application directly to the microelectronic structures and in the channels of information processing virtually does not evolve. The main reason is that the size of components of gates (modulators and light sources) due to the wave nature of the optical signal is much larger than that of the active elements of modern microelectronics. Entirely optical computers performing massively parallel computations typically contain rather large elements: lenses, shadowgrams, spatial light modulators, etc. and cannot be created using microelectronics technology.

At the same time, it may also be noted that with the development of nanophotonics, the advent of the light sources and receivers with nanometer dimensions (see, e.g. [5-7]), the optical channels could be used not only for the exchange of information between ICs, but also for the information processing, with the 3D logic devices. Thus, the construction of optoelectronic schemes, whose implementation fits well into the existing technology of building semiconductor circuits, is actual.

The *objectives* of this paper are: a) to consider the possibility of creating high performance and manufacturable multi-layer (3D) chips in which a processing of information and its mass exchange between the layers is performed using optical communication channels and whose parameters are compatible with those of microelectronic circuits, b) to represent the algorithmic and computer tools providing the design and research of simulation models of such 3D algorithms and structures with massive parallelism that are oriented to an optoelectronic implementation.

The principles of the gate, where logic signals are represented by the presence or absence of a light flux driven by an electric field are described in the paper. The possibility of the physical implementation of 3D logic circuits based on such elements is analyzed and its advantages are discussed. The methods and means of the algorithmic design of 3D ICs with a homogeneous structure for execution of algorithms with fine-grain parallelism are described. These tools include a formal model of fine-grained computing, Parallel Substitution Algorithm (PSA) and a simulation system (WinALT), which is based on PSA and provides the construction of models of devices with a 3D architecture. Features of the system are demonstrated by constructing models of 3D optoelectronic matrices for parallel data processing. Matrices can be characterized by a high performance, simplicity of cells, homogeneity and simplicity of the topology. Simulation models help in acquiring an objective view of the complexity and performance of the matrices and confirm the reasonability of the transition to 3D VLSI in order to overcome the problem of connections that arises in modern 2D VLSI. The WinALT system is available in Internet. The expediency of transforming WinALT to an online environment for supporting the simulation of 3D computational structures with the users' participation in the network (virtual) community is discussed.
