**1. Introduction**

The continuous miniaturization of complementary metal-oxide-semiconductor (CMOS) technologies has led to unacceptable tunneling current leakage levels for conventional thermally grown SiO2 gate dielectrics [1,2]. During the last years, many efforts have been devoted to investigate alternative high-permittivity (high-k) dielectrics that could replace SiO2 and SiON as gate insulators in MOS transistors [3]. The higher dielectric constant provides higher gate capacitances with moderated thickness layers; however, other requirements such as lower leakage currents, high breakdown fields, prevention of dopant diffusion, and good thermodynamic stability must also be fulfilled. A number of high-k materials have been investigated as candidates to replace the SiO2 as gate dielectric, being Al2O3 and HfO2 among the most studied ones [3–5], since both have a larger permittivity than SiO2 and are thermodynamically stable in contact with silicon. The electrical characteristics of the as-deposited layers of these materials, however, exhibit large negative fixed charge and interface state densities and charge trapping as compared to SiO2, although these characteristics can be improved by including an intermediate oxide between the highk layer and the silicon substrate [6–8] or by high-temperature post-deposition processes.[9– 13]. In addition to binary oxides, laminates of them show an improvement of the electrical characteristics as compared to the single oxide layers [14]. In particular, Al2O3–HfO2 laminates and alloys benefit from the higher k of HfO2 and the higher crystallization temperature of Al2O3 [15,16]

In this chapter we review the standard techniques as well as the new ones which we have developed for the electrical characterization of very thin insulating films of high k dielectrics for metal-insulator-semiconductor (MIS) gate and metal-insulator-metal (MIM) capacitor applications. These techniques have been conceived to provide detailed information of defects existing in the insulator bulk itself and interface traps appearing at the insulator-

© 2012 Dueñas et al., licensee InTech. This is an open access chapter distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. © 2012 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

#### 214 Dielectric Material

semiconductor substrate interface. Several methods exist to obtain defect densities at insulator/semiconductor interface, such as deep level transient technique (DLTS), high and low (quasi static) frequency capacitance-voltage measurements and admittance spectroscopy.

Electrical Characterization of High-K Dielectric Gates for Microelectronic Devices 215

summarizes the atomic elements used as precursors of the high-k dielectrics we have studied in our laboratory. An extended summary of the more relevant results obtained will be also included in the chapter. Another topics covered in this chapter include: high-k fabrication methods: ALD, CVD, High Pressure Sputtering, etc., influence of the process parameters on the quality of as-grown and thermally annealed materials, or charge trapping

**Figure 1.** Periodic table with marks on the atomic elements from which high-k materials (mainly oxides

Capacitance-Voltage is the most frequently used electrical technique to assess the properties of both the thin oxide layer and its interface with the semiconductor substrate. In thicker oxide layers (more than 4-5 nm) C–V curves can be fitted satisfactorily with classical models, described in textbooks. The C–V technique can be used to determine flatband and threshold voltage, fixed charge, and interface state density. It is also often used to calculate the oxide

effects in MOS capacitors include fixed charge, mobile charge and surface states. Performing a capacitance-voltage measurement allows identifying all three types of charge. Charge existing in the dielectric film shifts the measured curve. Trapping and detrapping of defects

*ac*

*ox k A <sup>C</sup> t* 

. Non-ideal

The ideal expression of a MIS structure in accumulation regime is: <sup>0</sup>

at the inner interface layers on gate-stacks and multilayer films.

and silicates) have been fabricated.

thickness.

**2. Standard characterization methods** 

**2.1. Capacitance-Votage measurements** 

However, the study of defects existing inside the gate dielectric bulk is not so widely established. Two techniques have been developed by us to accomplish it: conductance transient technique (GTT) and Flat-Band Voltage transients (FBT) measurements.

GTT is very useful when exploring disordered-induced gap states (DIGS) defects distributed inside the dielectric. This technique has been successfully applied to many high-k dielectric films on silicon. From conductance transient measurements we have obtained 3D profiles or contour maps showing the spatial and energetic distribution of electrically active defects inside the dielectric, preferentially located at regions close to the dielectric/semiconductor interface.

The FBT approach consists of a systematic study of flat-band voltage transients occurring in high-k dielectric-based metal-insulator-semiconductor (MIS) structures. While high-k material can help to solve gate leakage problems with leading-edge processes, there are still some remaining challenges. There are, indeed, several technical hurdles such as threshold voltage instability, carrier channel mobility degradation, and long-term device reliability. One important factor attributed to these issues is charge trapping in the pre-existing traps inside the high-k gate dielectrics. Dependencies of the flat-band voltage transients on the dielectric material, the bias history, and the hysteresis sign of the capacitance-voltage (C-V) curves are demonstrated. Flat bat voltage transients provide the soft optical phonon energy of dielectric thin-films. This energy usually requires chemical-physical techniques in bulk material. In contrast, FBT provides this magnitude for thin film materials and from electrical measurements, so adding an extra value to our experimental facilities.

Throughout the chapter we will give detailed information about the theoretical basis, experimental set-up and how to interpret the experimental results for all the above techniques.

Another topic widely covered will be the current mechanisms observed on high k materials. The above-mentioned methods allow determining the density and location of defects on the dielectric. These defects are usually responsible for the conduction mechanisms. The correlation between conduction mechanisms, defect location and preferential energy values provides very relevant information about the very nature of defects and how these defects can be removed or diminished.

We have studied many high-k materials during the last years, covering all proposed around the world as gate dielectric on silicon. These dielectrics consist of single layers of metal oxides and silicates (e.g.: HfO2, ZrO2, HfSiOx, Gd2O3, Al2O3, TiO2, and much more) directly deposited on n- and p- type silicon, combination of them in the form of multilayers, and gate stacks with silicon oxide or silicon nitride acting as interface layers which prevent from thermodynamic instabilities of directly deposited high-k films on silicon substrates. Figure 1 summarizes the atomic elements used as precursors of the high-k dielectrics we have studied in our laboratory. An extended summary of the more relevant results obtained will be also included in the chapter. Another topics covered in this chapter include: high-k fabrication methods: ALD, CVD, High Pressure Sputtering, etc., influence of the process parameters on the quality of as-grown and thermally annealed materials, or charge trapping at the inner interface layers on gate-stacks and multilayer films.

**Figure 1.** Periodic table with marks on the atomic elements from which high-k materials (mainly oxides and silicates) have been fabricated.
