**2.2. Current measurements and conduction mechanisms**

216 Dielectric Material

sweeping the gate voltage back and forth.

inside the insulator produce hysteresis in the high frequency capacitance curve when

Finally, surface states at the semiconductor-insulator interface also modify the CV curves. As the applied voltage varies the Fermi level at the interface changes and affects the occupancy of the surface states. The interface states cause the transition in the capacitance measurement to be stretched out In Figure 2 we show experimental high frequency C-V results for hafnium oxide MIS structures measured at room temperature. Atomic Layer

Deposition technique was used to grow these 20 nm-thick HfO2 films

**Figure 2.** 1MHz C-V curves of Al/HfO2/n-Si capacitors obtained by Atomic Layer Deposition

terminal. Interface state density is obtained according the following expression:

<sup>q</sup> <sup>൬</sup> CLF Cox-CLF

In sub-4 nm oxide layers, C–V measurements provide the same information, but the interpretation of the data requires considerable caution. The assumptions needed to construct the ''classical model'' are no longer valid, and quantum mechanical corrections become mandatory, thus increasing the complexity of the analytical treatment: Maxwell– Boltzman statistics no longer describe the charge density in the inversion and accumulation layers satisfactorily, and should be replaced by Fermi–Dirac statistics. In addition, band


൰ (1)

Dit= Cox

The combination of the low and high frequency capacitance (HLCV) [17] allows calculating the surface state density. This method provides the surface state density over a limited (but highly relevant) range of energies within the bandgap. Measurements on n-type and p-type capacitors at different temperatures provide the surface state density throughout the bandgap. A capacitance meter is usually employed to measure the high-frequency capacitance, *CHF*. The quasi-static measurement of the low frequency capacitance, *CLF*, consists on recording the gate current whereas a ramp-voltage is applied to the gate The performance of MOS devices strongly depends on the breakdown properties and the current transport behaviors of the gate dielectric films. The conduction mechanisms are very sensitive to the film composition, film processing, film thickness, and energy levels and densities of trap in the insulator films. Therefore, the analysis of the dominant conduction mechanisms may provide relevant information on the physical nature of the dielectric film and complements other characterization techniques when optimizing fabrication process. The most commonly found mechanisms as well as the voltage and temperature laws for each one are summarized in Figure 3.

**Figure 3.** Main conduction mechanisms on Metal-Insulator- Semiconductor devices

 **Electrode-limited mechanisms**: When the dielectric has high bandgap, high energy barrier with electrodes and low trap density, conduction is more electrode-limited than bulk limited. For a large applied bias, the silicon surface is n-type degenerated regardless of the bulk doping. Hence, for a large applied voltage the current is limited by tunneling (independent of the temperature) from the vicinity of the silicon conduction band edge through the triangular barrier into the oxide conduction band (*Fowler-Nordheim effect*). When barriers are no so high, conduction may occur when electrons or holes are promoted from the corresponding band to the insulator bands (*Schottky effect*). That occurs at lower voltages than Fowler-Nordheim mechanisms.

Electrical Characterization of High-K Dielectric Gates for Microelectronic Devices 219

1+(ωτit)<sup>2</sup> (2)

is the emission time constant of interface traps with energy

the loss mechanism due to interface trap capture and emission of carriers, is a measure of the interface trap density. Interface traps at the insulator-Si interface, however, are continuously distributed in energy throughout the Si band gap. Capture and emission occurs primarily by traps located within a few kT/q above and below the Fermi level,

<sup>q</sup>ωτitDit

The conductance is measured as a function of frequency and plotted as *G/ω* versus *ω*. *G /ω* has a maximum at *ω =*1/*τit* and at that maximum *Dit = 2G /qω.* For equation (2) we find *ω ≈*

It is also possible to make measurements by varying the temperature and keeping the frequency constant [19], instead of changing the frequency at constant temperature. This has the advantage of not requiring measurements over a wide frequency range and one can chose a frequency for which series resistance is negligible. Elevated temperature measurements enhance the sensitivity near mid-gap allowing the detection of trap energy levels and capture cross sections [20]. It also is possible to use transistors instead of capacitors and measure the transconductance instead of the conductance but still use the concepts of the conductance method [21]. This allows interface trap density determination on devices with the small gate areas associated with transistors without the need for

In this section we include several electrical characterization techniques that are useful for probing microscopic bonding structures, defects, and impurities in high-k dielectrics, as

IETS is a novel technique that can probe phonons, traps, microscopic bonding structures, and impurities in high-k gate dielectrics with a superior versatility and sensitivity when compared with other techniques. This technique basically takes the second derivative of the tunneling I–V characteristic of an ultrathin MOS structure. The basic principle of the IETS technique is illustrated in Figure 5. Without any inelastic interaction, the I–V characteristic is smooth and its second derivative is zero. When the applied voltage causes the Fermi-level separation to be equal to the characteristic interaction energy of an inelastic energy loss event for the tunneling electron, then an additional conduction channel (due to inelastic tunneling) is established, causing the slop of the I–V characteristic to increase at that voltage, and a peak in its second derivative plot, where the voltage location of the peak corresponds

leading to a time constant dispersion and giving the normalized conductance as

where *τit=* �*vthσpNA exp* �*-*

capacitance test structures.

**2.4. Other thecniques** 

described in [22].

*2/τit* and *Dit =2.5 G/qω* at the maximum.

*S*. *qS kT* ��*-1*

*2.4.1. Inelastic electron tunneling spectroscopy (IETS)* 

G ω =


In Figure 4 we draw the I-V characteristics at different temperatures of an Al2O3–based MIS sample fabricated by Atomic Layer Deposition. Leakage current clearly increases with temperature at lower gate voltages. I-V curves of all the samples were fitted according to the Poole-Frenkel emission, so indicating that the main conduction mechanism is bulk related.

**Figure 4.** I-V curves at several temperatures and Poole-Frenkel fitting of an ALD Al2O3–based MIS sample

#### **2.3. Admittance spectroscopy**

The admittance spectroscopy or conductance method, proposed by Nicollian and Goetzberger in 1967, is one of the most sensitive methods to determine *Dit* [18]. Interface trap densities of 109 cm**−**2 eV**−**1 and lower can be measured. It is also the most complete method, because it yields *Dit* in the depletion and weak inversion portion of the bandgap, the capture cross-sections for majority carriers, and information about surface potential fluctuations. The technique is based on measuring the equivalent parallel conductance of an MIS capacitor as a function of bias voltage and frequency. The conductance, representing the loss mechanism due to interface trap capture and emission of carriers, is a measure of the interface trap density. Interface traps at the insulator-Si interface, however, are continuously distributed in energy throughout the Si band gap. Capture and emission occurs primarily by traps located within a few kT/q above and below the Fermi level, leading to a time constant dispersion and giving the normalized conductance as

$$\frac{\mathbf{G}}{\omega\omega} = \frac{\mathbf{q}\omega\tau\_{\text{it}}\mathbf{D}\_{\text{it}}}{1 + (\omega\tau\_{\text{it}})^2} \tag{2}$$

where *τit=* �*vthσpNA exp* � *qS kT* ��*-1* is the emission time constant of interface traps with energy *S*.

The conductance is measured as a function of frequency and plotted as *G/ω* versus *ω*. *G /ω* has a maximum at *ω =*1/*τit* and at that maximum *Dit = 2G /qω.* For equation (2) we find *ω ≈ 2/τit* and *Dit =2.5 G/qω* at the maximum.

It is also possible to make measurements by varying the temperature and keeping the frequency constant [19], instead of changing the frequency at constant temperature. This has the advantage of not requiring measurements over a wide frequency range and one can chose a frequency for which series resistance is negligible. Elevated temperature measurements enhance the sensitivity near mid-gap allowing the detection of trap energy levels and capture cross sections [20]. It also is possible to use transistors instead of capacitors and measure the transconductance instead of the conductance but still use the concepts of the conductance method [21]. This allows interface trap density determination on devices with the small gate areas associated with transistors without the need for capacitance test structures.

#### **2.4. Other thecniques**

218 Dielectric Material

sample

**2.3. Admittance spectroscopy** 

0,0

Al2 O3

2,0µ

4,0µ

6,0µ

**I (A)**

8,0µ

10,0µ

12,0µ

(*Fowler-Nordheim effect*). When barriers are no so high, conduction may occur when electrons or holes are promoted from the corresponding band to the insulator bands (*Schottky effect*). That occurs at lower voltages than Fowler-Nordheim mechanisms. **Bulk limited mechanisms:** As the insulators become more defective, as is the case of practically all high-k dielectrics, bulk-limited conduction predominates due to traps inside the insulator. Sometimes current density is due to field enhanced thermal excitation of trapped electrons into the conduction band. This process is known as the *Internal Schottky or Poole Frenkel effect*. The *hopping* of thermally excited between isolated states gives an ohmic I–V characteristic, exponentially dependent on temperature. **Tunnel limited mechanisms**: As dielectric films become thinner, tunneling conduction gradually dominates the conduction mechanisms. It may occur via defects in a two-step (or trap-assisted) tunneling or by direct tunneling from one electrode to the other.

In Figure 4 we draw the I-V characteristics at different temperatures of an Al2O3–based MIS sample fabricated by Atomic Layer Deposition. Leakage current clearly increases with temperature at lower gate voltages. I-V curves of all the samples were fitted according to the Poole-Frenkel emission, so indicating that the main conduction mechanism is bulk related.


**ln(I / E)**


90 K 295K

**Figure 4.** I-V curves at several temperatures and Poole-Frenkel fitting of an ALD Al2O3–based MIS


**VG (V)**

= 8.99

2000 2100 2200

**E 1/2 (V 1/2cm -1/2)**

[ ] = x 10 - 5 eV m 1/2 V - 1/2

295 K

90 K

The admittance spectroscopy or conductance method, proposed by Nicollian and Goetzberger in 1967, is one of the most sensitive methods to determine *Dit* [18]. Interface trap densities of 109 cm**−**2 eV**−**1 and lower can be measured. It is also the most complete method, because it yields *Dit* in the depletion and weak inversion portion of the bandgap, the capture cross-sections for majority carriers, and information about surface potential fluctuations. The technique is based on measuring the equivalent parallel conductance of an MIS capacitor as a function of bias voltage and frequency. The conductance, representing In this section we include several electrical characterization techniques that are useful for probing microscopic bonding structures, defects, and impurities in high-k dielectrics, as described in [22].

#### *2.4.1. Inelastic electron tunneling spectroscopy (IETS)*

IETS is a novel technique that can probe phonons, traps, microscopic bonding structures, and impurities in high-k gate dielectrics with a superior versatility and sensitivity when compared with other techniques. This technique basically takes the second derivative of the tunneling I–V characteristic of an ultrathin MOS structure. The basic principle of the IETS technique is illustrated in Figure 5. Without any inelastic interaction, the I–V characteristic is smooth and its second derivative is zero. When the applied voltage causes the Fermi-level separation to be equal to the characteristic interaction energy of an inelastic energy loss event for the tunneling electron, then an additional conduction channel (due to inelastic tunneling) is established, causing the slop of the I–V characteristic to increase at that voltage, and a peak in its second derivative plot, where the voltage location of the peak corresponds to the characteristic energy of the inelastic interaction, and the area under the peak is proportional to the strength of the interaction.

Electrical Characterization of High-K Dielectric Gates for Microelectronic Devices 221

**2.5. Lateral profiling of threshold voltages, interface traps, and oxide trapped** 

Lateral profiling is a charge-pumping technique that enables one to profile the lateral distribution of threshold voltages of a MOSFET, and the lateral distributions of interface traps and oxide trapped charge generated by hot-carrier damage [23-24]. Figure 7(a) shows the Icp–Vh curves for the source (curve 1) and the drain junction (curve 2) prior to hot-carrier damage, from which one can obtain the threshold voltage distributions near the two junctions (Figure 7(b)) using the Vh-Vt(x) relationship as described in [25, 26]. Then a channel hot-carrier (CHC) stressing for 300 s to damage the device is used. Comparing curves 2 and 1 in Figure 8(a), one can see that the CHC stressing is not only generated Nit but also caused by positive charge inside the insulator gate, Qot. Therefore, one must neutralize this Qot before proceeding, and this was accomplished by a light hot electron injection as shown by curve 3 in Fig. 8. Note that this step did not cause any increase in Nit as evidenced by the

**Figure 7.** (a) Single-junction charge pumping curves measured either with the source floating (curve 1) or with the drain floating (curve 2). (b) Local Vt distribution across the channel as deduced from the

These three Icp curves were then used to extract the Nit(x) from the difference between curves 3 and 1 at a given Vh, and Qot(x) , from the voltage shift between 2 and 3 at a given Icp

**charge** 

unchanged Icp,max.

data in (a).(From Reference [22])

(Figure 8(b)).

**Figure 5.** Principles of IETS technique [22].

In a typical MOS sample, there are more than one inelastic mode, as a wide variety of inelastic interactions may take place, including interactions with phonons, various bonding vibrations, bonding defects, and impurities. Figure 6 shows an actual IETS spectrum taken on an Al/HfO2/Si sample, where the features below 80 meV correspond to Si phonons and Hf–O phonons, and the features above 120 meV correspond to Hf–Si–O and Si–O phonons. The significance of this IETS spectrum is that it confirms the strong electron–phonon interactions involving optical phonons in HfO2, and that the Hf–O phonons have very similar energy range as Si phonons which we know are a source of scattering centers that degrade the channel mobility.

**Figure 6.** IETS for HfO2 on Si under different bias polarities: (a) forward bias (gate electrode positive), (b) reverse bias (gate electrode negative) [22].
