**6. References**


[7] S. M. Holik, T. D. Drysdale.: 'Simplified model of a layer of interconnects under a spiral inductor,' Journal of Electromagnetic Analysis and Applications, 2011, 3, (6), pp. 187- 190.

208 Dielectric Material

**5. Conclusion** 

**Author details** 

*University of Glasgow, United Kingdom* 

Sonia M. Holik

**6. References** 

pp. 589-593

pp. 541-544.

415

The empirical model which allows a single layer of on-chip interconnects to be accurately replaced by homogeneous material slab in electromagnetic simulations containing integrated circuits was presented. The model is applicable to a wide range of interconnect dimensions (metal fill 20 - 60%, aspect ratio 1.4 – 3 and host permittivity 1 – 11.7) and is accurate to better than 2.5% (0.2%) error for reflection (transmission) when illuminated by plane waves with frequency 1 - 10 GHz, incident at up to 30 off the normal. The error does not increase with respect to the change in the grating profile and it can be applied to trapezoidal gratings with sidewall angles up to 5. Our approach allows the behaviour of on-chip interconnects to be accurately captured in full vector electromagnetic simulations without incurring the significant computational penalties associated with a finely detailed mesh. The experimental data supports the conception that the metal-dielectric grating structure specified for interconnects can be homogenised. The validation was carried out by

[1] Fontanelli, A.: 'System-in-Package technology: opportunities and challenges', Proc. IEEE 9th Int. Sym. Quality Electronic Design (ISQED'08), San Jose, CA, USA, 2008,

[2] Trigas, C.: 'Design challenges for System-in-Package vs System-on-Chip', Proc. IEEE Custom Integrated Circuits Conference (CICC'03), Munich, Germany, 2003, pp. 663-666 [3] Sham, M. L., Chen, Y. C., Leung, J. R., Chung, T.: 'Challenges and opportunities in System-in-Package business', Proc. IEEE 7th Int. Conf. Electronics Packaging

[4] Holik, S. M., Drysdale, T. D.: 'Simplified model for on-chip interconnects in electromagnetic modelling of System-in-Package', Proc. 12th International Conference on Electromagnetics in Advanced Applications (ICEAA'10), Sydney, Australia, 2010,

[5] Holik, S. M, Arnold, J. M, Drysdale, D. D.: 'Empirical mixing model for the electromagnetic modelling of on-chip interconnects', PIER Journal of Electromagnetic

[6] Holik, S. M, Drysdale, D. D.: 'Effective Medium Approximation for Electromagnetic Compatibility Analysis of Integrated Circuits', Proc. 2nd Int. Congress Advanced Electromagnetic Materials in Microwaves and Optics, Pamplona, Spain, 2008, pp. 413-

comparing the numerical results with experimental data.

Technology (ICEPT'06), Shanghai, China, 2006, pp. 1-5

Waves and Applications, 2011, 26, pp. 1-9.


#### 210 Dielectric Material

[23] Ghodgaonkar, D. K., Varadan, V. V., Varadan, V. V.: 'A free-space method for measurement of dielectric constants and loss tangents at microwave frequencies', IEEE Trans. Instrum. Meas., 1989, 37, (3), pp. 789-793

**Section 4** 

**Electrical Characterization** 

**of Microelectronic Devices** 

[24] Ansoft High Frequency Structure Simulator (HFSS), http://www.ansoft.com, accessed September 2010

**Electrical Characterization of Microelectronic Devices** 

210 Dielectric Material

September 2010

[23] Ghodgaonkar, D. K., Varadan, V. V., Varadan, V. V.: 'A free-space method for measurement of dielectric constants and loss tangents at microwave frequencies', IEEE

[24] Ansoft High Frequency Structure Simulator (HFSS), http://www.ansoft.com, accessed

Trans. Instrum. Meas., 1989, 37, (3), pp. 789-793

**Chapter 10** 

© 2012 Dueñas et al., licensee InTech. This is an open access chapter distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

© 2012 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution,

**Electrical Characterization of High-K Dielectric** 

The continuous miniaturization of complementary metal-oxide-semiconductor (CMOS) technologies has led to unacceptable tunneling current leakage levels for conventional thermally grown SiO2 gate dielectrics [1,2]. During the last years, many efforts have been devoted to investigate alternative high-permittivity (high-k) dielectrics that could replace SiO2 and SiON as gate insulators in MOS transistors [3]. The higher dielectric constant provides higher gate capacitances with moderated thickness layers; however, other requirements such as lower leakage currents, high breakdown fields, prevention of dopant diffusion, and good thermodynamic stability must also be fulfilled. A number of high-k materials have been investigated as candidates to replace the SiO2 as gate dielectric, being Al2O3 and HfO2 among the most studied ones [3–5], since both have a larger permittivity than SiO2 and are thermodynamically stable in contact with silicon. The electrical characteristics of the as-deposited layers of these materials, however, exhibit large negative fixed charge and interface state densities and charge trapping as compared to SiO2, although these characteristics can be improved by including an intermediate oxide between the highk layer and the silicon substrate [6–8] or by high-temperature post-deposition processes.[9– 13]. In addition to binary oxides, laminates of them show an improvement of the electrical characteristics as compared to the single oxide layers [14]. In particular, Al2O3–HfO2 laminates and alloys benefit from the higher k of HfO2 and the higher crystallization

In this chapter we review the standard techniques as well as the new ones which we have developed for the electrical characterization of very thin insulating films of high k dielectrics for metal-insulator-semiconductor (MIS) gate and metal-insulator-metal (MIM) capacitor applications. These techniques have been conceived to provide detailed information of defects existing in the insulator bulk itself and interface traps appearing at the insulator-

and reproduction in any medium, provided the original work is properly cited.

**Gates for Microelectronic Devices** 

Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/50399

temperature of Al2O3 [15,16]

**1. Introduction** 

Salvador Dueñas, Helena Castán, Héctor García and Luis Bailón
