**3. Advanced techniques**

In this section we show three techniques set up in our laboratory: Single shot DLTS , which provides interface state densities), Conductance transient technique used to profile disorder induced gap states in the insulator zones close to the interface, and Flat-band voltage transient technique from which slow traps distribution inside the insulator is obtained.

Electrical Characterization of High-K Dielectric Gates for Microelectronic Devices 225

(5)

(6)

(7)

(8)

2

*t t*

2 1

*t t*

max 1

If we assume that capture cross section has not strong variations with energy, we can find the energy of interface traps which have the maximum contribution to the correlation

max 2 1)

*C(ET)* has a maximum at the energy given by equation (6) and decays very sharply when energy varies from the maximum. Only interface traps with energies close to the maximum

> <sup>3</sup> 1 2 max

*N C t*

( ) ln *it T*

*C t kT <sup>t</sup> <sup>C</sup> D E*

*N C D E <sup>C</sup>*

Equation (6) indicates that for a given window rate the energy is proportional to temperature. Therefore, low temperature transients provide *Dit* for states close to the majority carriers semiconductor band (conduction band for n-type or valence band for ptype). As temperature increases deeper states densities are obtained. Equation (8) says that

a differential technique, its sensitivity is much higher than Capacitance-Voltage or Conductance-Voltage Techniques. Typical sensitivities are in the range of 109 eV-1 cm-2, which are lower than the state-of-the-art of thermal silicon oxide with silicon interface. Figure 11 is an example of SS-DLTS applied to the case of a hafnium silicate/silicon oxide on n-type silicon. The silicate was deposited by atomic layer deposition. In this case, we studied

All gate dielectrics exhibit conductance transients in MIS structures when are driven from deep to weak inversion [32]. This behavior is explained in terms of disorder-induced gap states (DIGS) continuum model suggested by Hasegawa et al.[33]. These authors proposed that lattice breaking at semiconductor/insulator interface causes defects with a continuous

the effect of post deposition thermal annealing on the quality of the interface.

contribute to the DLTS signal, and a more simple form equation (3) can be obtained:

*S D OX*

And the interface state density at the energy of the maximum:

*it T*

max

( ln

ln *nn C*

2 1

1

3

2 1 1 ( ) ln *S D OX*

*C/T*, that is, the sensitivity is lower for deeper states. Since SS-DLTS is

*<sup>t</sup> C t kT <sup>t</sup>*

*vN t t*

*t t*

*n*

*e*

*T C*

*E E kT*

function:

*Dit* is proporcional to

**3.2. Conductance transient technique** 

ln
