*4.2.2. Influence of the setup conditions*

In this section we show how the VFB transients are different depending on the bias regime of the sample just before the transient were recording. Transients are different depending if the samples are biased in accumulation or in inversion regimes. Setup time under these previous conditions also affect to the transient amplitude. To illustrate these influences we analyze here two cases based in HfO2 films. The first one is an HfO2 film directly grown on n-type silicon, and the second is a HfO2/SiO2 stack deposited on n-type silicon. Figure 26(a) shows the C-V curves at room and low temperature for an Al/HfO2/Si sample with a 250 Å HfO2 layer grown by atomic layer deposition (ALD). We observe that blat band voltage is positive in all curves indicating the existence of negative charge in the dielectric. Moreover, C-V shows hysteresis at both temperatures. Both flat band voltage and hysteresis are bigger for low temperature. The amount of negative charge and hysteresis are higher at low temperature.

To explain that we suggest that there are positive and negative charges inside the dielectric having different activation energies. At low temperatures positively charged traps (PCT) are not ionized, whereas this temperature is high enough to ionize traps yielding negative charge (NCT). When temperature increases positive traps are ionized by emitting electrons that moves by hopping to the gate or to substrate, so partially compensating the total negative charge. Another point is that hysteresis is clockwise at all temperatures, that is, accumulation bias give places to an increase of the total negative charge. When sample is in accumulation, detrapping mechanisms occurs and traps remain ionized. At inversion, PCT trap electrons coming from the gate and NCTs trap holes coming from the inversion layer at the substrate. Since NCTs predominates the whole effect is that negative charge increases during accumulation and decreases at inversion. These arguments are also observed in the flat-band voltage transients (Figures 26(b) and (c)).

240 Dielectric Material

localized states: Phonons produce the ionization of traps existing in the bandgap of the insulator. Electrons and/or holes generated in this way move by hopping from trap to trap until they reach a defect location and neutralize the charge state of this defect. It is important to point out that the electrons (or holes) do not enter the conduction (or valence) band of the

**Figure 25.** Flat-band voltage transients at different temperatures (a) and Arrhenius plot of the transient

In this section we show how the VFB transients are different depending on the bias regime of the sample just before the transient were recording. Transients are different depending if the samples are biased in accumulation or in inversion regimes. Setup time under these previous conditions also affect to the transient amplitude. To illustrate these influences we analyze here two cases based in HfO2 films. The first one is an HfO2 film directly grown on n-type silicon, and the second is a HfO2/SiO2 stack deposited on n-type silicon. Figure 26(a) shows the C-V curves at room and low temperature for an Al/HfO2/Si sample with a 250 Å HfO2 layer grown by atomic layer deposition (ALD). We observe that blat band voltage is positive in all curves indicating the existence of negative charge in the dielectric. Moreover, C-V shows hysteresis at both temperatures. Both flat band voltage and hysteresis are bigger for low temperature. The amount of negative charge and hysteresis are higher at low

To explain that we suggest that there are positive and negative charges inside the dielectric having different activation energies. At low temperatures positively charged traps (PCT) are not ionized, whereas this temperature is high enough to ionize traps yielding negative charge (NCT). When temperature increases positive traps are ionized by emitting electrons that moves by hopping to the gate or to substrate, so partially compensating the total negative charge. Another point is that hysteresis is clockwise at all temperatures, that is, accumulation bias give places to an increase of the total negative charge. When sample is in accumulation, detrapping mechanisms occurs and traps remain ionized. At inversion, PCT trap electrons coming from the gate and NCTs trap holes coming from the inversion layer at

dielectric and the conduction takes place within the band gap.

amplitude at 10 minutes (b) for an Al/Gd2O3/SiO2/Si sample.

*4.2.2. Influence of the setup conditions* 

temperature.

**Figure 26.** Normalized C-V curves (a) and Flat-band voltage transients at room temperature (b) and 77 K (c) of an Al/HfO2 /Si sample grown by ALD

We see that transients are decreasing when coming from accumulation and increasing when the sample is previously biased in inversion. At flat-band conditions traps previously charged (PCTs in accumulation and NCTs at inversion) can emit the trapped charge giving place to the corresponding flat-band voltage variation. We see also that these effects are more important as the setup time is higher indicating that trapping and detrapping are not instantaneous because the time needed by free carriers to reach the trap locations. Another important point is that decreasing and increasing transients seem to reach the same final values but after very long times (very much longer than those used in our experimental records).

Electrical Characterization of High-K Dielectric Gates for Microelectronic Devices 243

for passivation of defects (dangling bonds) on Si surface. Figure 29(a) shows DIGS density corresponding to post-metallization annealed (400ºC, 30 min) Al/HfO2/p-Si sample. Lower DIGS density is achieved, but *Dit* density is increased in this sample [59], indicating that thermal treatment partially moves the insulator defects to the interface. Ioannou-Sougleridis et al. [60] attributed instabilities observed in as-grown Y2O3 samples to slow traps, which

**Figure 27.** Normalized C-V curves and Flat-band voltage transients at room temperature (b) and 77 K

(c) for an Al/HfO2/SiO2/n-Si sample grown by HPRS

were mostly removed after FGA. The same behaviour can affect our results.

The second case presented here is a sample in which the dielectric is a stack of an 21 nm HfO2 film grown by High-Pressure Reactive Sputtering (HPRS) and a SiO2 buffer layer (3.4 nm-thick). In this case (Figure 27), C-V curves indicate that at room temperature there is positive charge at the dielectric, that is PCTs predominates over NCTs. Consequently, in accumulation the positive charge increases and decreases in inversion regime, giving place to the counter clock-wise hysteresis cycle observed at room temperature. At 77 K the PCTs are not ionized and the hysteresis cycles are due only to NCTs and, then, a clock-wise hysteresis cycle is obtained. This model is confirmed by the opposite trends shown by the flat-band voltage transients obtained at room and low temperature (Figures 27(b) and (c)). Low temperature curves are similar to those obtained in the previous case (Figure 26).
