**4.1. Effect of interlayer trapping and detrapping on the determination of interface state densities on high-k dielectric stacks**

HfO2 is among the most promising high-k dielectrics, but before qualifying, the nature and formation of electrically active defects existing in these emerging materials should be known. In fact, hafnium based high-k dielectris are already in production [41-43]. While not identified, it is most likely the dielectrics used by these companies are some form of nitrided hafnium silicates (HfSiON). HfO2 and HfSiO are susceptible to crystallize during dopant activation annealing. However, even HfSiON is susceptible to trap-related leakage currents, which tend to increase with stress over device lifetime. This drawback increases with the hafnium concentration. It is known that defects in SiO2 are passivated by hydrogen, but this can cause some problems in HfO2 [44]. Moreover, as most of the high-k materials, when HfO2 is deposited in direct contact with Si a silicon oxide (SiOx) interfacial layer (few nanometres thick) is formed [45, 46]. Because of the non-controlled nature of this silicon dioxide layer, its quality is poor and the interfacial state density (Dit) and leakage current increase. Moreover, this barrier layer leads to a reduction of the dielectric constant and, hence, to the effective capacitance of the gate dielectric stack. The use of silicon nitride instead of silicon oxide as barrier layer can improve the effective capacitance of the gate dielectric stack, since silicon nitride has a higher permittivity (≈ 7) than silicon oxide (≈ 3.9). Moreover, SiNx is stable when deposited on Si, preventing the growth of silicon oxides, and the use of nitrides greatly reduces boron diffusion from the heavily doped poly-Si gate electrode to the lightly doped Si channel [3].

230 Dielectric Material

When the charge density inside the insulator film, ߩ௫ሺݐሻ, varied with time, *t,* or with the distance from the interface, *x*, the flat band voltage varies. In particular, trapping and detrapping on defects existing inside the dielectric will produce transient variations of the flat-band voltage. According equation (11) these variations are oposite in sign to the charge variation. As it has been suggested elsewhere [40] at flat-band voltage conditions there are not electrons or holes directly injected form the gate or semiconductor, i.e., free charges move by hopping from trap to trap. Moreover, since no optical neither electrical external stimulus are applied, free charges must be originated from trapping or detrapping mechanisms of defects existing inside the dielectric and the energy needed to activate this

The experimental setup of this technique is identical to that used to capacitance-voltage technique. The only difference is that in order to obtain the flat-band voltage transients, a feedback system that varies the applied gate voltage accordingly to keep the flat-band

The experimental flat band voltage transients become faster when the dielectric thickness diminishes. Time dependences appear to be independent of the temperature. These two facts suggest that there are tunnelling assisted process involved. The amplitude of the transients is thermally activated with energies in the range of soft-optical phonons usually reported for high-k dielectrics. We have proved that the flat-band voltage transients increase or decrease depending on the previous bias history (accumulation or inversion) and the hysteresis sign (clockwise or counter-clockwise) of the capacitance-voltage (C-V) characteristics of MOS structures. In the next section we illustrate all these finger prints.

To illustrate the technique, we have included in Figure 15 some experimental results for the case of a sample of a 20 nm film of hafnium oxide deposited by ALD on silicon. The amplitude of the flat-band voltage transients depends on temperature according an

> ( , ) exp *ph V Tt FB kT*

This section includes a selection of different cases to show the applicability of our

HfO2 is among the most promising high-k dielectrics, but before qualifying, the nature and formation of electrically active defects existing in these emerging materials should be

**4.1. Effect of interlayer trapping and detrapping on the determination of** 

where *ph* is the energy of the soft optical phonons of the dielectric.

**interface state densities on high-k dielectric stacks** 

(12)

mechanisms only can be provided as thermal energy, that is, phonons.

capacitance value was implemented.

Arrhenius type law:

**4. Some examples** 

techniques.

**Figure 15.** Example of DIGS profile: Atomic Layer Deposited hafnium oxide films.

In a previous work [47] we studied the influences of the silicon nitride blocking-layer thickness on the Interface State densities (*Dit*) of HfO2/SiNx:H gate-stacks on n-type silicon. The blocking layer consisted of 3 to 7 nm thick silicon nitride films directly grown on the silicon substrates by electron-cyclotron-resonance assisted chemical-vapour-deposition (ECR-CVD). Afterwards, 12 nm thick hafnium oxide films were deposited by high-pressure reactive sputtering (HPS). Interface state densities were determined by deep-level transient spectroscopy (DLTS) and by the high and low frequency capacitance-voltage (HLCV) method. The HLCV measurements provide interface trap densities in the range of 1011 cm-2 eV-1 for all the samples. However, a significant increase of about two orders of magnitude was obtained by DLTS for the thinnest silicon nitride barrier layers. In this work we probe that this increase is an artefact due to the effect of traps located at the internal interface existing between the HfO2 and SiNx:H films. Because charge trapping and discharging are tunnelling assisted, these traps are more easily charged or discharged as lower the distance from this interface to the substrate, that is, as thinner the SiNx:H blocking layer. The trapping/detrapping mechanisms increase the amplitude of the capacitance transient and, in consequence, the DLTS signal, which have contributions not only from the insulator/substrate interface states but also from the HfO2/SiNx:H interlayer traps.

Electrical Characterization of High-K Dielectric Gates for Microelectronic Devices 233

**× 1011 (cm-2eV-1)** 

**Dit from HLCV × 1011 (cm-2eV-1)** 

focused our attention in the traps existing at the surface between the SiNx:H interface layer

**Tickness (nm) RTA Dit from DLTS**

Asd\_1 90 6,6 ± 0,4 As-deposited 3 – 5 3.0 RTA\_1 600 ºC – 30s 2 - 5 2.2 Asd\_2 60 5,9 ± 0,4 As-deposited 0.8 – 1 1.3 RTA\_2 600 ºC – 30s 1 - 2 2.7 Asd\_3 30 3,9 ± 0,2 As-deposited Not measured 4.5 RTA\_3 600 ºC – 30s 100 - 200 4.4 Asd\_4 15 3,0 ± 0,4 As-deposited 50 - 100 2.0 RTA\_4 600 ºC - 30s 50 - 100 1.9

**Table 1.** ECR-CVD deposition time, silicon nitride thickness and interface state densities provided by

**Figure 17.** 1 MHz C-V curves measured for the as-deposited samples at room temperature.

To study these discrepancies in depth, we have focused our attention on the sample showing the biggest discrepancies on the *Dit* values measured by HLCV and DLTS. The one selected was the Asd\_4 sample, which has the lowest barrier layer thickness (3 nm). First, we recorded the interface state density profiles obtained by DLTS when varying the bias conditions. Figure 18(a) shows important variations in the *Dit* profiles when the accumulation filling pulse voltage is varied while keeping constant the reverse voltage. On the contrary, no significant differences are obtained when varying the reverse voltage (Figure 18(b). Therefore, the mechanisms responsible for these variations must occur during the trap-filling pulse but not under reverse (detrapping) bias conditions, when the

and the HfO2 film.

**Sample ECR-CVD**

**time (s)** 

DLTS and HLCV measurements.

capacitance transients are recorded.

**Silicon nitride**

**Figure 16.** Interface state density measured by DLTS

To determine the interface trap densities we used DLTS and HLCV techniques in order to contrast the results obtained by the two techniques. HLCV measurements are summarized in table 1. This technique provides similar interface density (*Dit*) values (2-4 1011 cm-2eV-1) for all the samples, regardless the silicon nitride layer thickness. Therefore, interface quality seems not to depend on the blocking layer thickness, as one could expect for these not ultrathin films. In contrast, DLTS results (Figure 16) can be clearly separated in two groups: one corresponding to the thickest samples which has Dit densities from 9 1010 cm-2eV-1 to 4 1011 cm-2eV-1, in good agreement with HLCV results, and the other group corresponding o the thinnest samples wit Dit values (from 61012 cm-2eV-1 to 21013 cm-2eV-1) much higher than those obtained by HLCV. In order to explain these discrepancies we carried out an exhaustive analysis which leads us to conclude that charging and discharging mechanisms of inner traps existing at the HfO2/SiNx interface affect the DLTS results.

Figure 17 plots the normalized C-V curves measured at room temperature for the asdeposited samples. The stretch-out is similar for all the samples, meaning a similar trap density, contrary to the DLTS results. Vuillame et al. [48] reported variations in the DLTS signal due to slow traps located inside the insulator, but these changes are only observed for very short filling accumulation pulses times under 50 s, much lower than the 15 ms used in our experiments. On the other hand, changes were much smaller than those observed in this work. Moreover, slow traps induce hysteresis at the C-V curves and conductance transients. However, a clockwise hysteresis is observed only in the thickest samples and conductance transients have not been detected in any of the thinnest samples. The only difference between the samples is the HfO2/SiNx:H interface distance from the substrate, so that we


focused our attention in the traps existing at the surface between the SiNx:H interface layer and the HfO2 film.

232 Dielectric Material

tunnelling assisted, these traps are more easily charged or discharged as lower the distance from this interface to the substrate, that is, as thinner the SiNx:H blocking layer. The trapping/detrapping mechanisms increase the amplitude of the capacitance transient and, in consequence, the DLTS signal, which have contributions not only from the

To determine the interface trap densities we used DLTS and HLCV techniques in order to contrast the results obtained by the two techniques. HLCV measurements are summarized in table 1. This technique provides similar interface density (*Dit*) values (2-4 1011 cm-2eV-1) for all the samples, regardless the silicon nitride layer thickness. Therefore, interface quality seems not to depend on the blocking layer thickness, as one could expect for these not ultrathin films. In contrast, DLTS results (Figure 16) can be clearly separated in two groups: one corresponding to the thickest samples which has Dit densities from 9 1010 cm-2eV-1 to 4 1011 cm-2eV-1, in good agreement with HLCV results, and the other group corresponding o the thinnest samples wit Dit values (from 61012 cm-2eV-1 to 21013 cm-2eV-1) much higher than those obtained by HLCV. In order to explain these discrepancies we carried out an exhaustive analysis which leads us to conclude that charging and discharging mechanisms

Figure 17 plots the normalized C-V curves measured at room temperature for the asdeposited samples. The stretch-out is similar for all the samples, meaning a similar trap density, contrary to the DLTS results. Vuillame et al. [48] reported variations in the DLTS signal due to slow traps located inside the insulator, but these changes are only observed for very short filling accumulation pulses times under 50 s, much lower than the 15 ms used in our experiments. On the other hand, changes were much smaller than those observed in this work. Moreover, slow traps induce hysteresis at the C-V curves and conductance transients. However, a clockwise hysteresis is observed only in the thickest samples and conductance transients have not been detected in any of the thinnest samples. The only difference between the samples is the HfO2/SiNx:H interface distance from the substrate, so that we

of inner traps existing at the HfO2/SiNx interface affect the DLTS results.

insulator/substrate interface states but also from the HfO2/SiNx:H interlayer traps.

**Figure 16.** Interface state density measured by DLTS

**Table 1.** ECR-CVD deposition time, silicon nitride thickness and interface state densities provided by DLTS and HLCV measurements.

**Figure 17.** 1 MHz C-V curves measured for the as-deposited samples at room temperature.

To study these discrepancies in depth, we have focused our attention on the sample showing the biggest discrepancies on the *Dit* values measured by HLCV and DLTS. The one selected was the Asd\_4 sample, which has the lowest barrier layer thickness (3 nm). First, we recorded the interface state density profiles obtained by DLTS when varying the bias conditions. Figure 18(a) shows important variations in the *Dit* profiles when the accumulation filling pulse voltage is varied while keeping constant the reverse voltage. On the contrary, no significant differences are obtained when varying the reverse voltage (Figure 18(b). Therefore, the mechanisms responsible for these variations must occur during the trap-filling pulse but not under reverse (detrapping) bias conditions, when the capacitance transients are recorded.

**Figure 18.** DLTS profiles obtained keeping constant the voltage of the reverse-emptying-pulse (a) and the accumulation-filling pulse (b).

In Figure 19 we show the DLTS values obtained for different energies as a function of gate voltage and the electric field at the Silicon Nitride film. The electric field has been evaluated according the expression:

$$F\_{\rm SiNx} = \frac{V\_G - V\_{FB}}{\frac{\mathcal{E}\_{\rm SiN\_x}}{\mathcal{E}\_{\rm HfO\_2}} t\_{\rm HfO\_2} + t\_{\rm SiN\_x}} \tag{13}$$

Electrical Characterization of High-K Dielectric Gates for Microelectronic Devices 235

.

(16)

is a parameter

*EE E E* (15)

The slope of Equation (14) is a function of energy. This dependency is plotted in Figure 20 and we have observed that the experimental points fit very well the following dependency.

**Figure 19.** Experimental DLTS signal as a function of accumulation voltage and SiNx electric field for

**Figure 20.** Variation with energy of the electric field barrier lowering parameter,

state density profile that is the obtained at low electric filed values.

( ) *cT CT*

 

In summary, we can state that experimental DLTS profiles obey the following expression:

\* *D D F D EEF it it SiNx it c T SiNx*

where *Dit\** is the as-measured apparent interface state profile. Dit is the true trap interface

 

different energies.

We clearly observed that for all the energies the relationship between *Dit* and electric field is linear:

$$\frac{dD\_{it}}{dF\_{SiNx}} = \eta (E\_c - E\_T) \tag{14}$$

The slope of Equation (14) is a function of energy. This dependency is plotted in Figure 20 and we have observed that the experimental points fit very well the following dependency.

234 Dielectric Material

the accumulation-filling pulse (b).

1012

10<sup>12</sup>

10<sup>13</sup>

1013

**(a)**

**Dit (cm-2eV-1**

**(b)**

**Dit (cm-2eV-1)** 

**)**

according the expression:

linear:

**Figure 18.** DLTS profiles obtained keeping constant the voltage of the reverse-emptying-pulse (a) and

**EC-ET (eV)**

0,1 0,2 0,3 0,4 0,5 0,6 0,7

**EC-ET (eV)**

VR=-0.5 V

**VACC**

 1.2 V 1.1 V 1.0 v 0.9 V 0.8 V 0.7 V 0.6 V

> -1 V -0.9 V -0.8 V -0.7 V -0.6 V -0.5 V -0.4 V -0.3 V

In Figure 19 we show the DLTS values obtained for different energies as a function of gate voltage and the electric field at the Silicon Nitride film. The electric field has been evaluated

> 2 *x*

We clearly observed that for all the energies the relationship between *Dit* and electric field is

( ) *it c T*

*dD E E dF* 

*SiN*

*SiNx*

*HfO*

*SiNx*

*F*

2

*t t*

*HfO SiN*

0,2 0,3 0,4 0,5 0,6 0,7

VACC= +1.1 V VR

*G FB*

*V V*

*x*

(13)

(14)

**Figure 19.** Experimental DLTS signal as a function of accumulation voltage and SiNx electric field for different energies.

**Figure 20.** Variation with energy of the electric field barrier lowering parameter, .

$$
\sigma(E\_c - E\_T) = \alpha - \beta \sqrt{E\_C - E\_T} \tag{15}
$$

In summary, we can state that experimental DLTS profiles obey the following expression:

$$D\_{it}^{\*} = D\_{it} + \eta F\_{\text{SiNx}} = D\_{it} + \left(\alpha - \beta \sqrt{E\_c - E\_T} \right) F\_{\text{SiNx}} \tag{16}$$

where *Dit\** is the as-measured apparent interface state profile. Dit is the true trap interface state density profile that is the obtained at low electric filed values. is a parameter associated to the electric field lowering of the energy barrier between the silicon conduction band and traps located at the inner layer interface. This barrier is lower as higher the energy of the traps at the inner interface layer and this fact is included at the second term of parameter.

Electrical Characterization of High-K Dielectric Gates for Microelectronic Devices 237

IL states and the interface states (B). These interface states can emit electrons to the conduction band in a similar way as occurs in conventional DLTS (C). Electrons emitted according the (B)+(C) sequence increase the capacitance transient, obtaining an apparent increase in the measured interfacial state densities. Since all these mechanisms are tunnelling assisted, as thinner the silicon nitride films as higher their probability. In our experiment, the SiNx:H layer thickness has been varied from around 3 to 6.6 nm. To roughly estimate the relationship between the tunnelling charging/discharging probabilities for two samples with different silicon nitride thickness (*t1* and *t2*), we can use the following quantum

<sup>1</sup>

are the barrier thickness and *h* is the Plank's constant. For the h-well triangular barrier, *<sup>v</sup>*

*ΔEV/2*, where *ΔEV* is the valence band offset of silicon nitride relative to silicon. Gritsenko et al. [55] reported values of *ΔEV* ≈ 1.5 eV and *mh /m0* =(0.3±0.1). Here *m0* is the free electron mass. These values yield a relation of *p1/p2 =10-4* for two layers of 6 and 3 nm, respectively, so indicating that the IL trapping/detrapping mechanisms effect is negligible for thicker samples in comparison with the 3 nm-thick blocking layer samples where the very thin silicon nitride layer allows electron tunnelling from IL traps to the channel interface, so

Moreover, as higher the electric field In Figure 22(b) higher filling-pulse (higher bias in the accumulation regime). In this case, a larger number IL traps has been filled. When biasing the sample in the inversion regime, a higher number of IL traps can contribute to the capacitance transient by direct tunnelling. This result agrees with results shown in Figure

On the contrary, variations of the inversion bias do not change the total filled traps, and the emitted charge from the IL traps does not change significantly. The results shown in Figure 18(b) confirm this hypothesis: the measured *Dit* values hardly change when varying the

In samples with thicker SiNx:H layer, IL traps cannot contribute to the DLTS capacitance transients, which take place in a relatively short time. However, the IL traps in these samples do exchange charge with the substrate in longer times, giving rise to the hysteresis phenomena not observed in the two thinnest samples. In fact, we can measure slow states inside the MIS insulator by the conductance transient technique (GTT) [56]. We measured the slow states inside the insulator and we observed only slow states in the two thickest samples: if these slow states were due to traps in the bulk SiNx:H, they would appear in all

 

2 2 exp *<sup>p</sup> mh V t t*

*p h*

2

increasing the total charge emitted during the DLTS reverse pulses.

18(a): the higher the filling pulse the higher the DLTS *Dit* results.

where *mh* is the hole effective mass inside the barrier, *<sup>v</sup>*

1 2

(17)

=

is the mean barrier height, *t1* and *t2*

mechanics expression:

reverse bias.

the samples.

The true interface state density, *Dit*, is plotted at Figure 21 as obtained for the lowest accumulation voltage values. These values do agree with those obtained when using HLCV technique. Moreover, this distribution show a profile consisting on broad gaussian peaks, as is usually reported for silicon nitride films [49-53].

**Figure 21.** True interface state density profile as obtained at low electric fields (<1 MV.cm-1)

### *4.1.1. Band energy model*

The energy diagrams of the MIS structures under accumulation and inversion are displayed in Figure 22. To construct them, we have included the published values of the bandgap and the conduction and valence band offsets of hafnium oxide and silicon nitride relative to silicon [54]. We also assume that defects exist at the HfO2/SiNx:H inner layer interface (IL). DLTS measurements consist of applying accumulation pulses to fill the interface states in the upper half of the semiconductor bandgap followed by reverse pulses in which the interface states emit electrons to the conduction band yielding capacitance transients that are conveniently recorded and processed to obtain the *Dit* distribution. If the SiNx:H film is thin enough, tunnelling between the semiconductor and the inner layer interface (IL) may occur. At accumulation, capturing electrons coming from the semiconductor band by direct tunnelling fills IL states. Then, when the reverse pulse is applied these defects emit the captured electrons to the semiconductor band. The emission process may occur in two different ways: IL states with energies above the silicon conduction band (light grey area) emit electrons by direct tunnelling (A). On the other hand, for energies ranging from the Fermi level to the semiconductor conduction band (dark grey area) tunnelling between the IL states and the interface states (B). These interface states can emit electrons to the conduction band in a similar way as occurs in conventional DLTS (C). Electrons emitted according the (B)+(C) sequence increase the capacitance transient, obtaining an apparent increase in the measured interfacial state densities. Since all these mechanisms are tunnelling assisted, as thinner the silicon nitride films as higher their probability. In our experiment, the SiNx:H layer thickness has been varied from around 3 to 6.6 nm. To roughly estimate the relationship between the tunnelling charging/discharging probabilities for two samples with different silicon nitride thickness (*t1* and *t2*), we can use the following quantum mechanics expression:

236 Dielectric Material

parameter

.

*4.1.1. Band energy model* 

is usually reported for silicon nitride films [49-53].

associated to the electric field lowering of the energy barrier between the silicon conduction band and traps located at the inner layer interface. This barrier is lower as higher the energy of the traps at the inner interface layer and this fact is included at the second term of

The true interface state density, *Dit*, is plotted at Figure 21 as obtained for the lowest accumulation voltage values. These values do agree with those obtained when using HLCV technique. Moreover, this distribution show a profile consisting on broad gaussian peaks, as

**Figure 21.** True interface state density profile as obtained at low electric fields (<1 MV.cm-1)

The energy diagrams of the MIS structures under accumulation and inversion are displayed in Figure 22. To construct them, we have included the published values of the bandgap and the conduction and valence band offsets of hafnium oxide and silicon nitride relative to silicon [54]. We also assume that defects exist at the HfO2/SiNx:H inner layer interface (IL). DLTS measurements consist of applying accumulation pulses to fill the interface states in the upper half of the semiconductor bandgap followed by reverse pulses in which the interface states emit electrons to the conduction band yielding capacitance transients that are conveniently recorded and processed to obtain the *Dit* distribution. If the SiNx:H film is thin enough, tunnelling between the semiconductor and the inner layer interface (IL) may occur. At accumulation, capturing electrons coming from the semiconductor band by direct tunnelling fills IL states. Then, when the reverse pulse is applied these defects emit the captured electrons to the semiconductor band. The emission process may occur in two different ways: IL states with energies above the silicon conduction band (light grey area) emit electrons by direct tunnelling (A). On the other hand, for energies ranging from the Fermi level to the semiconductor conduction band (dark grey area) tunnelling between the

$$\frac{p\_1}{p\_2} = \exp\left[\frac{2\pi\sqrt{2m\_h\overline{\phi\_V}}}{h}(t\_1 - t\_2)\right] \tag{17}$$

where *mh* is the hole effective mass inside the barrier, *<sup>v</sup>* is the mean barrier height, *t1* and *t2* are the barrier thickness and *h* is the Plank's constant. For the h-well triangular barrier, *<sup>v</sup>* = *ΔEV/2*, where *ΔEV* is the valence band offset of silicon nitride relative to silicon. Gritsenko et al. [55] reported values of *ΔEV* ≈ 1.5 eV and *mh /m0* =(0.3±0.1). Here *m0* is the free electron mass. These values yield a relation of *p1/p2 =10-4* for two layers of 6 and 3 nm, respectively, so indicating that the IL trapping/detrapping mechanisms effect is negligible for thicker samples in comparison with the 3 nm-thick blocking layer samples where the very thin silicon nitride layer allows electron tunnelling from IL traps to the channel interface, so increasing the total charge emitted during the DLTS reverse pulses.

Moreover, as higher the electric field In Figure 22(b) higher filling-pulse (higher bias in the accumulation regime). In this case, a larger number IL traps has been filled. When biasing the sample in the inversion regime, a higher number of IL traps can contribute to the capacitance transient by direct tunnelling. This result agrees with results shown in Figure 18(a): the higher the filling pulse the higher the DLTS *Dit* results.

On the contrary, variations of the inversion bias do not change the total filled traps, and the emitted charge from the IL traps does not change significantly. The results shown in Figure 18(b) confirm this hypothesis: the measured *Dit* values hardly change when varying the reverse bias.

In samples with thicker SiNx:H layer, IL traps cannot contribute to the DLTS capacitance transients, which take place in a relatively short time. However, the IL traps in these samples do exchange charge with the substrate in longer times, giving rise to the hysteresis phenomena not observed in the two thinnest samples. In fact, we can measure slow states inside the MIS insulator by the conductance transient technique (GTT) [56]. We measured the slow states inside the insulator and we observed only slow states in the two thickest samples: if these slow states were due to traps in the bulk SiNx:H, they would appear in all the samples.

Electrical Characterization of High-K Dielectric Gates for Microelectronic Devices 239

**Figure 23.** Normalized C-V curves of Al/Gd2O3/HF-etched-Si (a) and Al/Gd2O3/SiO2/Si (b) with

To characterize the time dependence of the transients, we have normalized them (Figure 24(b)) by dividing the experimental values by their value at 600 seconds. It is clear that the time constant is independent of the temperature, indicating that tunnelling mechanisms are involved in the conduction. As for temperature dependency of VFB transients, we recorded transients at several temperatures (Figure 25(a)) and we observed that their magnitude follows an Arrhenius plot (Figure 25(b)) with activation energy in the range of the softoptical phonon energies (*WPH*) usually reported for high-k dielectrics. From our fits for different samples we have obtained that for Gd2O3 these energies are of about 55±10 meV. These values were obtained for both annealed and as-deposited samples and for Gd2O3 film

**Figure 24.** Flat-band voltage transients at different Gd2O3 thickness, tox, (a) and temperature (b) of

From all these observations we concluded that the flat band voltage transients under conditions without external stress are originated by phonon-assisted tunnelling between

different Gd2O3 thicknesses, measured at room temperature.

thicknesses from about 2 to 20 nm.

Gd2O3-based MIS structures.

**Figure 22.** Energy band diagram of the HfO2/SiNx:H/n-Si MIS structures under accumulation (a) and inversion (b)

### **4.2. Flat-band voltage transients: Main fingerprints**

In this section we summarize the main finger-prints of the flat-band voltage transients. We have obtained *VFB* transients for many high-k dielectrics (HfO2, hafnium silicate, Al2O3, TiO2 and Gd2O3). In all cases, there is a direct relationship between the C-V curve hysteresis and the transient amplitude. Here we present a selection of our experimental work to show the information that can be extracted from the transients as well as the parameters affecting to their amplitude, shape, and time constant. We have observed that the main parameters affecting the transients are the experimental temperature, the dielectric film thickness, the dielectric material itself and, finally, the bias voltage and the setup time just before the flat band voltage condition is established in the sample.

### *4.2.1. Temperature and thickness dependencies*

Figure 23 shows capacitance-voltage curves obtained at room temperature for as-deposited Al/Gd2O3/HF-etched-Si (a) and Al/Gd2O3/SiO2/Si (b) MIS structures with different Gd2O3 thickness. *VFB* is negative in all cases indicating the existence of positive charge in the dielectric. In Figure 23(a) we see that *VFB* moves to less negative values with thickness indicating that the charge centroid is closer to the interface for thicker films. That means that traps are preferentially created in the very first dielectric layers. Moreover, in Figure 23(b) we see that when a SiO2 film is present, *VFB* shows more negative values and weaker thickness dependence than when Gd2O3 films are directly deposited on HF-etched silicon. That must be due to the existence of non-mobile charge trapped at the interface between the high-k and SiO2 films. *VFB* transients for different thicknesses (Figure 24(a)) reveal time constants increasing with thickness below 5.7 nm. That indicates the existence of charge displacement mechanisms: the thinner the films the lower the distances to be covered for the mobile charges to reach the gate and/or the insulator-semiconductor interface.

238 Dielectric Material

inversion (b)

**Figure 22.** Energy band diagram of the HfO2/SiNx:H/n-Si MIS structures under accumulation (a) and

In this section we summarize the main finger-prints of the flat-band voltage transients. We have obtained *VFB* transients for many high-k dielectrics (HfO2, hafnium silicate, Al2O3, TiO2 and Gd2O3). In all cases, there is a direct relationship between the C-V curve hysteresis and the transient amplitude. Here we present a selection of our experimental work to show the information that can be extracted from the transients as well as the parameters affecting to their amplitude, shape, and time constant. We have observed that the main parameters affecting the transients are the experimental temperature, the dielectric film thickness, the dielectric material itself and, finally, the bias voltage and the setup time just before the flat

Figure 23 shows capacitance-voltage curves obtained at room temperature for as-deposited Al/Gd2O3/HF-etched-Si (a) and Al/Gd2O3/SiO2/Si (b) MIS structures with different Gd2O3 thickness. *VFB* is negative in all cases indicating the existence of positive charge in the dielectric. In Figure 23(a) we see that *VFB* moves to less negative values with thickness indicating that the charge centroid is closer to the interface for thicker films. That means that traps are preferentially created in the very first dielectric layers. Moreover, in Figure 23(b) we see that when a SiO2 film is present, *VFB* shows more negative values and weaker thickness dependence than when Gd2O3 films are directly deposited on HF-etched silicon. That must be due to the existence of non-mobile charge trapped at the interface between the high-k and SiO2 films. *VFB* transients for different thicknesses (Figure 24(a)) reveal time constants increasing with thickness below 5.7 nm. That indicates the existence of charge displacement mechanisms: the thinner the films the lower the distances to be covered for the

mobile charges to reach the gate and/or the insulator-semiconductor interface.

**4.2. Flat-band voltage transients: Main fingerprints** 

band voltage condition is established in the sample.

*4.2.1. Temperature and thickness dependencies* 

**Figure 23.** Normalized C-V curves of Al/Gd2O3/HF-etched-Si (a) and Al/Gd2O3/SiO2/Si (b) with different Gd2O3 thicknesses, measured at room temperature.

To characterize the time dependence of the transients, we have normalized them (Figure 24(b)) by dividing the experimental values by their value at 600 seconds. It is clear that the time constant is independent of the temperature, indicating that tunnelling mechanisms are involved in the conduction. As for temperature dependency of VFB transients, we recorded transients at several temperatures (Figure 25(a)) and we observed that their magnitude follows an Arrhenius plot (Figure 25(b)) with activation energy in the range of the softoptical phonon energies (*WPH*) usually reported for high-k dielectrics. From our fits for different samples we have obtained that for Gd2O3 these energies are of about 55±10 meV. These values were obtained for both annealed and as-deposited samples and for Gd2O3 film thicknesses from about 2 to 20 nm.

**Figure 24.** Flat-band voltage transients at different Gd2O3 thickness, tox, (a) and temperature (b) of Gd2O3-based MIS structures.

From all these observations we concluded that the flat band voltage transients under conditions without external stress are originated by phonon-assisted tunnelling between localized states: Phonons produce the ionization of traps existing in the bandgap of the insulator. Electrons and/or holes generated in this way move by hopping from trap to trap until they reach a defect location and neutralize the charge state of this defect. It is important to point out that the electrons (or holes) do not enter the conduction (or valence) band of the dielectric and the conduction takes place within the band gap.

Electrical Characterization of High-K Dielectric Gates for Microelectronic Devices 241

the substrate. Since NCTs predominates the whole effect is that negative charge increases during accumulation and decreases at inversion. These arguments are also observed in the

**Figure 26.** Normalized C-V curves (a) and Flat-band voltage transients at room temperature (b) and 77

K (c) of an Al/HfO2 /Si sample grown by ALD

flat-band voltage transients (Figures 26(b) and (c)).

**Figure 25.** Flat-band voltage transients at different temperatures (a) and Arrhenius plot of the transient amplitude at 10 minutes (b) for an Al/Gd2O3/SiO2/Si sample.
