**6. References**


**Chapter 9** 

© 2012 Holik, licensee InTech. This is an open access chapter distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use,

© 2012 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution,

distribution, and reproduction in any medium, provided the original work is properly cited.

and reproduction in any medium, provided the original work is properly cited.

From a package-level point of view, the on-chip interconnects can be seen as a mixture of metal inclusions located in a host dielectric [4-8]. Most of the current studies based on numerical analysis of 2-D or 3-D structures with two constituents show that the effective properties of the mixture strongly depend on the volume fraction, its geometrical profile

**Empirical Mixing Model for the Electromagnetic** 

**Compatibility Analysis of On-Chip Interconnects** 

For over four decades the evolution of electronic technology has followed Moore's low where the number of transistors in an integrated circuit (IC) approximately doubles every two years. This naturally increases the number of internal interconnections needed to complete the system. The increase in chip complexity is achieved by a combination of dimensional scaling and technology advances. A variety of chip types exist, including memory, microprocessors and application specific circuits such as System-on-Chip (SoC). Since it is expensive to fabricate the large and simple passive components such as on-chip capacitors and inductors on the same die as the active circuits, it is desirable to fabricate these on separate dies then combine them in System-in-Package (SiP). The main advantage of SiP technology is the ability to combine ICs with other components, including passive lumped elements already mentioned but also antennas, high speed chips for radio frequency communication etc., into one fully functional package. The high complexity of SiP brings many challenges to the design process and physical verification of the system. In many cases the design process relies on detailed 3-D numerical electromagnetic simulations that tend to be slow and computationally demanding [1,2,3] in many cases limited by the available computer memory capacity and computational speed. Therefore, directly including the detail of the dense interconnect networks into the numerical model is demanding due to the amount of memory required to hold the detailed mesh, and numerical penalties associated with small mesh cell sizes relative to the wavelengths of the

Sonia M. Holik

**1. Introduction** 

signals being modelled.

http://dx.doi.org/10.5772/50435

Additional information is available at the end of the chapter

