**3.1. Single shot deep-level transient spectroscopy**

Deep-level transient spectroscopy (DLTS) has been widely used to characterize localized deep levels in semiconductor junctions. This technique is also useful to measure interface traps in the insulator-semiconductor interface. The instrumentation for interface trapped charge DLTS is identical to that for bulk deep level DLTS. However, the data interpretation is different because interface traps are continuously distributed in energy through the band gap, whereas bulk traps have discrete energy levels.

Single-shot DLTS measurements consist on recording and processing 1-MHz isothermal capacitance transients at temperatures from 77 K to room temperature. A programmable source is used together with a pulse generator to introduce the quiescent bias and the filling pulse, respectively. *Dit* is obtained by first applying a pulse which drives the MIS capacitor to accumulation, in order to fill the interface traps. Afterwards, the bias quickly returns to the limit between depletion and weak inversion, then traps formerly filled are emptied yielding the capacitance transients which are recorded for the DLTS processing. The isothermal capacitance transients are captured by a 1 MHz capacitance meter and a digital oscilloscope. The digital oscilloscope allows us to record the entire capacitance transient and, in this way, we can process the entire energy spectrum with only one temperature scan.

Once the capacitance transients have been captured, we process them as follows: we chose two times t1 and t2 (the window rate). The difference in the capacitance value at these times is the DLTS correlation signal which is given by [30, 31]:

$$
\Delta \mathbf{C} = -\frac{\mathbf{C}(\mathbf{t}\_1)^3}{\epsilon\_5 \mathbf{N}\_\mathrm{D}} \frac{1}{\mathbf{C}\_\mathrm{ox}} \int\_{\mathrm{E}\_\mathrm{F}^{\mathrm{II}}}^{\mathrm{E}\_\mathrm{F}^{\mathrm{I}\_2}} \left[ \exp\left( -\mathbf{e}\_\mathrm{n} \mathbf{t}\_1 \right) \cdot \exp\left( -\mathbf{e}\_\mathrm{n} \mathbf{t}\_2 \right) \right] \mathbf{D}\_\mathrm{lt} \tag{3}
$$

The emission rate, *en*, depends on temperature and on energy, *ET*, according the well-known Arrhenius law:

$$\mathbf{e}\_{\mathrm{n}} \mathbf{w}\_{\mathrm{n}} \mathbf{v}\_{\mathrm{n}} \mathbf{N}\_{\mathrm{c}} \exp\left[\frac{\mathrm{E}\_{\mathrm{T}} \mathrm{E}\_{\mathrm{C}}}{\mathrm{kT}}\right] \tag{4}$$

Where *σ<sup>n</sup>* is the capture cross section, *vn* is the electron thermal velocity and *NC* is the efective state density at the silicon conduction band. According equation (3), all the interface states contribute to the correlation function, but only those with emission rates in the range of the window rate have non negligible contribution. Indeed, the correlation function has a maximum for:

Electrical Characterization of High-K Dielectric Gates for Microelectronic Devices 225

$$e\_n^{\text{max}} = \frac{\ln\left(\frac{t\_2}{t\_1}\right)}{t\_2 - t\_1} \tag{5}$$

If we assume that capture cross section has not strong variations with energy, we can find the energy of interface traps which have the maximum contribution to the correlation function:

$$E\_T^{\text{max}} = E\_C - kT \ln \left[ \frac{\sigma\_n v\_n N\_C (t\_2 - t\_1)}{\ln \left( \frac{t\_2}{t\_1} \right)} \right] \tag{6}$$

*C(ET)* has a maximum at the energy given by equation (6) and decays very sharply when energy varies from the maximum. Only interface traps with energies close to the maximum contribute to the DLTS signal, and a more simple form equation (3) can be obtained:

$$
\Delta \mathcal{C} = -\frac{\mathcal{C}(t\_1)^3}{\varepsilon\_S N\_D} \frac{kT}{C\_{OX}} D\_{it} \left( E\_T^{\text{max}} \right) \ln \left( \frac{t\_2}{t\_1} \right) \tag{7}
$$

And the interface state density at the energy of the maximum:

224 Dielectric Material

scan.

Arrhenius law:

maximum for:

**3. Advanced techniques** 

**3.1. Single shot deep-level transient spectroscopy** 

gap, whereas bulk traps have discrete energy levels.

is the DLTS correlation signal which is given by [30, 31]:

3 εSND 1 Cox

t2 EF

∆C = - C(t1)

en=σnvnNcexp

In this section we show three techniques set up in our laboratory: Single shot DLTS , which provides interface state densities), Conductance transient technique used to profile disorder induced gap states in the insulator zones close to the interface, and Flat-band voltage transient technique from which slow traps distribution inside the insulator is obtained.

Deep-level transient spectroscopy (DLTS) has been widely used to characterize localized deep levels in semiconductor junctions. This technique is also useful to measure interface traps in the insulator-semiconductor interface. The instrumentation for interface trapped charge DLTS is identical to that for bulk deep level DLTS. However, the data interpretation is different because interface traps are continuously distributed in energy through the band

Single-shot DLTS measurements consist on recording and processing 1-MHz isothermal capacitance transients at temperatures from 77 K to room temperature. A programmable source is used together with a pulse generator to introduce the quiescent bias and the filling pulse, respectively. *Dit* is obtained by first applying a pulse which drives the MIS capacitor to accumulation, in order to fill the interface traps. Afterwards, the bias quickly returns to the limit between depletion and weak inversion, then traps formerly filled are emptied yielding the capacitance transients which are recorded for the DLTS processing. The isothermal capacitance transients are captured by a 1 MHz capacitance meter and a digital oscilloscope. The digital oscilloscope allows us to record the entire capacitance transient and, in this way, we can process the entire energy spectrum with only one temperature

Once the capacitance transients have been captured, we process them as follows: we chose two times t1 and t2 (the window rate). The difference in the capacitance value at these times

The emission rate, *en*, depends on temperature and on energy, *ET*, according the well-known

Where *σ<sup>n</sup>* is the capture cross section, *vn* is the electron thermal velocity and *NC* is the efective state density at the silicon conduction band. According equation (3), all the interface states contribute to the correlation function, but only those with emission rates in the range of the window rate have non negligible contribution. Indeed, the correlation function has a

<sup>ቂ</sup>exp <sup>ቀ</sup>-ent1<sup>ቁ</sup> - exp <sup>ቀ</sup>-ent2ቁቃ EF

ET-EC

t1 Dit (3)

kT ൨ (4)

$$D\_{ii} \left( E\_{\rm T}^{\rm max} \right) = -\frac{\varepsilon\_s N\_D}{kT \ln \binom{t\_2}{\prime}} \frac{\mathcal{C}\_{\rm ox}}{\mathcal{C}(t\_1)^3} \Delta \mathcal{C} \tag{8}$$

Equation (6) indicates that for a given window rate the energy is proportional to temperature. Therefore, low temperature transients provide *Dit* for states close to the majority carriers semiconductor band (conduction band for n-type or valence band for ptype). As temperature increases deeper states densities are obtained. Equation (8) says that *Dit* is proporcional to *C/T*, that is, the sensitivity is lower for deeper states. Since SS-DLTS is a differential technique, its sensitivity is much higher than Capacitance-Voltage or Conductance-Voltage Techniques. Typical sensitivities are in the range of 109 eV-1 cm-2, which are lower than the state-of-the-art of thermal silicon oxide with silicon interface. Figure 11 is an example of SS-DLTS applied to the case of a hafnium silicate/silicon oxide on n-type silicon. The silicate was deposited by atomic layer deposition. In this case, we studied the effect of post deposition thermal annealing on the quality of the interface.

#### **3.2. Conductance transient technique**

All gate dielectrics exhibit conductance transients in MIS structures when are driven from deep to weak inversion [32]. This behavior is explained in terms of disorder-induced gap states (DIGS) continuum model suggested by Hasegawa et al.[33]. These authors proposed that lattice breaking at semiconductor/insulator interface causes defects with a continuous distribution both in energy and in space. Conductance transient phenomena are due to charge and discharge of DIGS states assisted by majority carriers coming from the corresponding semiconductor band by means of a tunneling assisted mechanism. Transients can be understood looking at Figure 12 which is referred to a MIS structure over an n-type semiconductor substrate. When the bias pulse is applied, empty DIGS trap electrons coming from the conduction band (n-MIS structure). *EF* and *E'* are the locations of the Fermi level before and after the pulse. Capture process is assisted by tunneling and is, thus, time consuming, so empty states near the interface capture electrons before the states deep in the dielectric. *xC* is the distance covered by the front of tunneling electrons during the time *t* . It is important to note here that only those states with emission and capture rates of the same order of magnitude than the frequency have non-zero contributions to the conductance [34]. If an experimental frequency *<sup>b</sup>* is assumed, only those states with emission rates in the range *b ±∆* can contribute to the conductance (those located over equiemission line *en = <sup>b</sup>*), so only when the front of tunneling electrons reaches point A conductance increases. Then, when point B is reached, conductance transient follows the DIGS states distribution which is typically decreasing as we move away from interface, in agreement with Hasegawa's model [33]. Finally, conductance returns to its initial value when the front reaches point C, since after this point DIGS states susceptible to contribute to the conductance signal have energies strongly apart of the Fermi level and, then, they remain empty. Figure 12 is a schematic of the conductance transient principle.

Electrical Characterization of High-K Dielectric Gates for Microelectronic Devices 227

(9)

*<sup>0</sup>* is the carrier capture cross-section value

[36] where *GSS* is the stationary value of the conductance.

*SS*

*qA* *, Dit* is related to

, where

**Figure 12.** (a) Schematic band diagram of an I–S interface illustrating the capture electrons by DIGS continuum states during a conductance transient. (b) General shape of the conductance transient.

interface state density, *Dit* , in MIS devices. For an angular frequency,

Variations of this value are due to the DIGS contribution to the conductance:

*DIGS C*

tunneling electrons during the time *t, and* is given by ln *c on o th s x t x v nt*

conductance by *Dit= GSS*

*eff eff*

*h*

2 2 *on*

*x*

*0.4qAω*

*m H* is the tunneling decay length,

In the following, we show the model developed by us [35] to obtain DIGS states as a function of the spatial distance to the interface and the energy position by measuring conductance transients at different frequencies and temperatures. The calculation details presented here are for the case of an n-MIS structure. Similar equations can be derived for p-MIS devices. Our model departs from the conductance method typically used to obtain the

( ) ( ( ), ( )) 0.4

*G t N Et x t*

where *E(t)* is the energy of the DIGS states which a given time *t* during the transient contribute to the conductance variation*. xC(t)* is the distance covered by the front of

for x = 0, vth is the carrier thermal velocity in the semiconductor, and *ns* is the free carrier density at the interface. Finally, *meff* is the electron effective mass at the dielectric and *Heff* is the insulator semiconductor energy barrier for majority carriers, that is, the dielectric to semiconductor conduction band offset. Figure 13 shows *xon* for some high-k dielectrics (electron effective mass and barrier height values have been obtained from References [3] and [37] respectively). One can see that *xon* is higher for dielectrics in which *Heff* and *meff* are low. In these cases, the tunneling front xC is faster and, consequently, transients reach deeper locations in the dielectric. An important trend can be derived from this figure: as permittivity increases, tunneling decay length increases providing deeper DIGS profiles.

**Figure 11.** Interface state profiles for *Al/HfSixOy/SiO2/n-Si* capacitors.

226 Dielectric Material

range *b ±∆*

If an experimental frequency

empty. Figure 12 is a schematic of the conductance transient principle.

**Figure 11.** Interface state profiles for *Al/HfSixOy/SiO2/n-Si* capacitors.

distribution both in energy and in space. Conductance transient phenomena are due to charge and discharge of DIGS states assisted by majority carriers coming from the corresponding semiconductor band by means of a tunneling assisted mechanism. Transients can be understood looking at Figure 12 which is referred to a MIS structure over an n-type semiconductor substrate. When the bias pulse is applied, empty DIGS trap electrons coming from the conduction band (n-MIS structure). *EF* and *E'* are the locations of the Fermi level before and after the pulse. Capture process is assisted by tunneling and is, thus, time consuming, so empty states near the interface capture electrons before the states deep in the dielectric. *xC* is the distance covered by the front of tunneling electrons during the time *t* . It is important to note here that only those states with emission and capture rates of the same order of magnitude than the frequency have non-zero contributions to the conductance [34].

*<sup>b</sup>* is assumed, only those states with emission rates in the

can contribute to the conductance (those located over equiemission line *en =* 

*<sup>b</sup>*), so only when the front of tunneling electrons reaches point A conductance increases. Then, when point B is reached, conductance transient follows the DIGS states distribution which is typically decreasing as we move away from interface, in agreement with Hasegawa's model [33]. Finally, conductance returns to its initial value when the front reaches point C, since after this point DIGS states susceptible to contribute to the conductance signal have energies strongly apart of the Fermi level and, then, they remain

**Figure 12.** (a) Schematic band diagram of an I–S interface illustrating the capture electrons by DIGS continuum states during a conductance transient. (b) General shape of the conductance transient.

In the following, we show the model developed by us [35] to obtain DIGS states as a function of the spatial distance to the interface and the energy position by measuring conductance transients at different frequencies and temperatures. The calculation details presented here are for the case of an n-MIS structure. Similar equations can be derived for p-MIS devices. Our model departs from the conductance method typically used to obtain the interface state density, *Dit* , in MIS devices. For an angular frequency,*, Dit* is related to conductance by *Dit= GSS 0.4qAω* [36] where *GSS* is the stationary value of the conductance. Variations of this value are due to the DIGS contribution to the conductance:

$$N\_{DIGS}(E(t), x\_C(t)) = \frac{\Delta G\_{SS}(t)}{0.4qAo} \tag{9}$$

where *E(t)* is the energy of the DIGS states which a given time *t* during the transient contribute to the conductance variation*. xC(t)* is the distance covered by the front of tunneling electrons during the time *t, and* is given by ln *c on o th s x t x v nt* , where

2 2 *on eff eff h x m H* is the tunneling decay length, *<sup>0</sup>* is the carrier capture cross-section value

for x = 0, vth is the carrier thermal velocity in the semiconductor, and *ns* is the free carrier density at the interface. Finally, *meff* is the electron effective mass at the dielectric and *Heff* is the insulator semiconductor energy barrier for majority carriers, that is, the dielectric to semiconductor conduction band offset. Figure 13 shows *xon* for some high-k dielectrics (electron effective mass and barrier height values have been obtained from References [3] and [37] respectively). One can see that *xon* is higher for dielectrics in which *Heff* and *meff* are low. In these cases, the tunneling front xC is faster and, consequently, transients reach deeper locations in the dielectric. An important trend can be derived from this figure: as permittivity increases, tunneling decay length increases providing deeper DIGS profiles.

**Figure 13.** Tunneling decay length versus permittivity for several dielectrics.

Finally, to obtain the energy position of DIGS states in the band gap of the dielectric, we use equi-emission line equations [33] , and considering that the measurement frequency is related to emission rate by en = /1.98 [36] , we obtain the following equation:

$$E'-E(\mathbf{x}\_{\circ},t) = H\_{\circ \circ} + kT \ln \frac{\sigma\_0 \upsilon\_{\circ \circ} N\_{\circ}}{a \mathcal{V}\_{1.98}} - \frac{kT}{\mathcal{x}\_{\circ \circ}} \mathbf{x}\_{\circ} \text{(}t\text{)}\tag{10}$$

Electrical Characterization of High-K Dielectric Gates for Microelectronic Devices 229

When temperature decreases the emission rates of all interface states exponentially decrease, and the equi-emission lines shift approaching the interface. Thus, transients are modified in a similar way as when frequency is increased while keeping constant the temperature. DIGS three-dimensional profile or contour line maps can be obtained using Equations (9) and (10). As for the experimental sensitivity, temperature measurement involves an error of 0.1 K. Estimated errors of energy and defect concentration values on DIGS profiles are of about 10 meV and 5x109 eV-1cm-2 , respectively. Estimated precision on DIGS depth is of about 2 Å.

The experimental set-up consists of a pulse generator to apply bias pulses, a lock-in analyzer to measure the conductance, and a digitizing oscilloscope to record conductance transients. Samples are cooled in darkness from room temperature to 77 K in a cryostat. Figure 14 is an example of DIGS profiles obtained from conductance transients on MIS structures fabricated

In section IV.C we review results obtained for several high-k dielectrics grown by atomic

Several problems must be fixed before the high-k dielectric materials could be extensively used in fabrication. One of them is the instability caused by charge trapping and detrapping inside the dielectric. Fixed and trapped charges cause serious performance degradation by shifting the threshold voltage, limiting transistor mobility and reducing device lifetimes. Threshold voltage shifts are observed under positive bias, negative bias and hot-carrier stressing in high-gate stacks. Charge trapping under positive bias stressing is known to be more severe compared to conventional SiO2-based gate dielectrics [38]. It is believed to happen due to filling of pre-existing bulk traps. Charge trapping causes threshold voltage shifts and drive current degradation over device operation time. It also precludes accurate mobility (inversion charge) measurements due to a distortion of C-V curves. Negative bias temperature instability (NBTI) induced threshold voltage shifts in high-k devices are also

observed and are comparable to those observed for silicon-based oxide devices.

The flat-band voltage, VFB, of a MIS capacitance is given by:

In a previous work [39], we showed the existence of flat band voltage transients in ultra-thin high-k dielectrics on silicon. To obtain these transients, we recorded the gate voltage while keeping the capacitance constant at the initial flat band condition (*CFB*). Therefore, samples were kept under no external stress conditions: zero electric field in the substrate, darkness conditions and no external charge injection. Under these conditions, the only mechanism for defect trapping or detrapping is thermal activation, that is, phonons. We proved that the energy of soft-optical phonons in high k dielectric is obtained with this experimental

<sup>1</sup> ( ) ( ,)

*ox ox <sup>Q</sup> V t x t xdx C*

*i FB MS ox*

0

(11)

*tox*

with ALD Gadolinium oxide as dielectric.

**3.3. Flat-Band Transient Technique (FBT)** 

approach.

layer deposition (ALD) under different processing conditions.

**Figure 14.** Example of DIGS profile: atomic layer deposited Gadolinium oxide films.

When temperature decreases the emission rates of all interface states exponentially decrease, and the equi-emission lines shift approaching the interface. Thus, transients are modified in a similar way as when frequency is increased while keeping constant the temperature. DIGS three-dimensional profile or contour line maps can be obtained using Equations (9) and (10). As for the experimental sensitivity, temperature measurement involves an error of 0.1 K. Estimated errors of energy and defect concentration values on DIGS profiles are of about 10 meV and 5x109 eV-1cm-2 , respectively. Estimated precision on DIGS depth is of about 2 Å.

The experimental set-up consists of a pulse generator to apply bias pulses, a lock-in analyzer to measure the conductance, and a digitizing oscilloscope to record conductance transients. Samples are cooled in darkness from room temperature to 77 K in a cryostat. Figure 14 is an example of DIGS profiles obtained from conductance transients on MIS structures fabricated with ALD Gadolinium oxide as dielectric.

In section IV.C we review results obtained for several high-k dielectrics grown by atomic layer deposition (ALD) under different processing conditions.

#### **3.3. Flat-Band Transient Technique (FBT)**

228 Dielectric Material

**Figure 13.** Tunneling decay length versus permittivity for several dielectrics.

related to emission rate by en = /1.98 [36] , we obtain the following equation:

**Figure 14.** Example of DIGS profile: atomic layer deposited Gadolinium oxide films.

Finally, to obtain the energy position of DIGS states in the band gap of the dielectric, we use equi-emission line equations [33] , and considering that the measurement frequency is

<sup>0</sup> ' ( , ) ln ( )

*v N kT E E x t H kT x t*

*C eff C*

1.98 *th C*

*on*

*x*

(10)

Several problems must be fixed before the high-k dielectric materials could be extensively used in fabrication. One of them is the instability caused by charge trapping and detrapping inside the dielectric. Fixed and trapped charges cause serious performance degradation by shifting the threshold voltage, limiting transistor mobility and reducing device lifetimes. Threshold voltage shifts are observed under positive bias, negative bias and hot-carrier stressing in high-gate stacks. Charge trapping under positive bias stressing is known to be more severe compared to conventional SiO2-based gate dielectrics [38]. It is believed to happen due to filling of pre-existing bulk traps. Charge trapping causes threshold voltage shifts and drive current degradation over device operation time. It also precludes accurate mobility (inversion charge) measurements due to a distortion of C-V curves. Negative bias temperature instability (NBTI) induced threshold voltage shifts in high-k devices are also observed and are comparable to those observed for silicon-based oxide devices.

In a previous work [39], we showed the existence of flat band voltage transients in ultra-thin high-k dielectrics on silicon. To obtain these transients, we recorded the gate voltage while keeping the capacitance constant at the initial flat band condition (*CFB*). Therefore, samples were kept under no external stress conditions: zero electric field in the substrate, darkness conditions and no external charge injection. Under these conditions, the only mechanism for defect trapping or detrapping is thermal activation, that is, phonons. We proved that the energy of soft-optical phonons in high k dielectric is obtained with this experimental approach.

The flat-band voltage, VFB, of a MIS capacitance is given by:

$$V\_{FB}(t) = \Phi\_{MS} - \frac{Q\_i}{\mathcal{C}\_{ox}} - \frac{1}{\mathcal{E}\_{ox}} \int \rho\_{ox}(\mathbf{x}, t) \mathbf{x} d\mathbf{x} \tag{11}$$

#### 230 Dielectric Material

When the charge density inside the insulator film, ߩ௫ሺݐሻ, varied with time, *t,* or with the distance from the interface, *x*, the flat band voltage varies. In particular, trapping and detrapping on defects existing inside the dielectric will produce transient variations of the flat-band voltage. According equation (11) these variations are oposite in sign to the charge variation. As it has been suggested elsewhere [40] at flat-band voltage conditions there are not electrons or holes directly injected form the gate or semiconductor, i.e., free charges move by hopping from trap to trap. Moreover, since no optical neither electrical external stimulus are applied, free charges must be originated from trapping or detrapping mechanisms of defects existing inside the dielectric and the energy needed to activate this mechanisms only can be provided as thermal energy, that is, phonons.

The experimental setup of this technique is identical to that used to capacitance-voltage technique. The only difference is that in order to obtain the flat-band voltage transients, a feedback system that varies the applied gate voltage accordingly to keep the flat-band capacitance value was implemented.

The experimental flat band voltage transients become faster when the dielectric thickness diminishes. Time dependences appear to be independent of the temperature. These two facts suggest that there are tunnelling assisted process involved. The amplitude of the transients is thermally activated with energies in the range of soft-optical phonons usually reported for high-k dielectrics. We have proved that the flat-band voltage transients increase or decrease depending on the previous bias history (accumulation or inversion) and the hysteresis sign (clockwise or counter-clockwise) of the capacitance-voltage (C-V) characteristics of MOS structures. In the next section we illustrate all these finger prints.

To illustrate the technique, we have included in Figure 15 some experimental results for the case of a sample of a 20 nm film of hafnium oxide deposited by ALD on silicon. The amplitude of the flat-band voltage transients depends on temperature according an Arrhenius type law:

$$\Delta V\_{\rm FB}(T, t) \, a \, \exp\left(\begin{matrix} \Phi\_{\rm ph} \\ \nearrow \& T \end{matrix}\right) \tag{12}$$

Electrical Characterization of High-K Dielectric Gates for Microelectronic Devices 231

known. In fact, hafnium based high-k dielectris are already in production [41-43]. While not identified, it is most likely the dielectrics used by these companies are some form of nitrided hafnium silicates (HfSiON). HfO2 and HfSiO are susceptible to crystallize during dopant activation annealing. However, even HfSiON is susceptible to trap-related leakage currents, which tend to increase with stress over device lifetime. This drawback increases with the hafnium concentration. It is known that defects in SiO2 are passivated by hydrogen, but this can cause some problems in HfO2 [44]. Moreover, as most of the high-k materials, when HfO2 is deposited in direct contact with Si a silicon oxide (SiOx) interfacial layer (few nanometres thick) is formed [45, 46]. Because of the non-controlled nature of this silicon dioxide layer, its quality is poor and the interfacial state density (Dit) and leakage current increase. Moreover, this barrier layer leads to a reduction of the dielectric constant and, hence, to the effective capacitance of the gate dielectric stack. The use of silicon nitride instead of silicon oxide as barrier layer can improve the effective capacitance of the gate dielectric stack, since silicon nitride has a higher permittivity (≈ 7) than silicon oxide (≈ 3.9). Moreover, SiNx is stable when deposited on Si, preventing the growth of silicon oxides, and the use of nitrides greatly reduces boron diffusion from the heavily doped poly-Si gate

electrode to the lightly doped Si channel [3].

**Figure 15.** Example of DIGS profile: Atomic Layer Deposited hafnium oxide films.

In a previous work [47] we studied the influences of the silicon nitride blocking-layer thickness on the Interface State densities (*Dit*) of HfO2/SiNx:H gate-stacks on n-type silicon. The blocking layer consisted of 3 to 7 nm thick silicon nitride films directly grown on the silicon substrates by electron-cyclotron-resonance assisted chemical-vapour-deposition (ECR-CVD). Afterwards, 12 nm thick hafnium oxide films were deposited by high-pressure reactive sputtering (HPS). Interface state densities were determined by deep-level transient spectroscopy (DLTS) and by the high and low frequency capacitance-voltage (HLCV) method. The HLCV measurements provide interface trap densities in the range of 1011 cm-2 eV-1 for all the samples. However, a significant increase of about two orders of magnitude was obtained by DLTS for the thinnest silicon nitride barrier layers. In this work we probe that this increase is an artefact due to the effect of traps located at the internal interface existing between the HfO2 and SiNx:H films. Because charge trapping and discharging are

where *ph* is the energy of the soft optical phonons of the dielectric.
