**2. Standard characterization methods**

#### **2.1. Capacitance-Votage measurements**

214 Dielectric Material

spectroscopy.

interface.

techniques.

can be removed or diminished.

semiconductor substrate interface. Several methods exist to obtain defect densities at insulator/semiconductor interface, such as deep level transient technique (DLTS), high and low (quasi static) frequency capacitance-voltage measurements and admittance

However, the study of defects existing inside the gate dielectric bulk is not so widely established. Two techniques have been developed by us to accomplish it: conductance

GTT is very useful when exploring disordered-induced gap states (DIGS) defects distributed inside the dielectric. This technique has been successfully applied to many high-k dielectric films on silicon. From conductance transient measurements we have obtained 3D profiles or contour maps showing the spatial and energetic distribution of electrically active defects inside the dielectric, preferentially located at regions close to the dielectric/semiconductor

The FBT approach consists of a systematic study of flat-band voltage transients occurring in high-k dielectric-based metal-insulator-semiconductor (MIS) structures. While high-k material can help to solve gate leakage problems with leading-edge processes, there are still some remaining challenges. There are, indeed, several technical hurdles such as threshold voltage instability, carrier channel mobility degradation, and long-term device reliability. One important factor attributed to these issues is charge trapping in the pre-existing traps inside the high-k gate dielectrics. Dependencies of the flat-band voltage transients on the dielectric material, the bias history, and the hysteresis sign of the capacitance-voltage (C-V) curves are demonstrated. Flat bat voltage transients provide the soft optical phonon energy of dielectric thin-films. This energy usually requires chemical-physical techniques in bulk material. In contrast, FBT provides this magnitude for thin film materials and from electrical

Throughout the chapter we will give detailed information about the theoretical basis, experimental set-up and how to interpret the experimental results for all the above

Another topic widely covered will be the current mechanisms observed on high k materials. The above-mentioned methods allow determining the density and location of defects on the dielectric. These defects are usually responsible for the conduction mechanisms. The correlation between conduction mechanisms, defect location and preferential energy values provides very relevant information about the very nature of defects and how these defects

We have studied many high-k materials during the last years, covering all proposed around the world as gate dielectric on silicon. These dielectrics consist of single layers of metal oxides and silicates (e.g.: HfO2, ZrO2, HfSiOx, Gd2O3, Al2O3, TiO2, and much more) directly deposited on n- and p- type silicon, combination of them in the form of multilayers, and gate stacks with silicon oxide or silicon nitride acting as interface layers which prevent from thermodynamic instabilities of directly deposited high-k films on silicon substrates. Figure 1

transient technique (GTT) and Flat-Band Voltage transients (FBT) measurements.

measurements, so adding an extra value to our experimental facilities.

Capacitance-Voltage is the most frequently used electrical technique to assess the properties of both the thin oxide layer and its interface with the semiconductor substrate. In thicker oxide layers (more than 4-5 nm) C–V curves can be fitted satisfactorily with classical models, described in textbooks. The C–V technique can be used to determine flatband and threshold voltage, fixed charge, and interface state density. It is also often used to calculate the oxide thickness.

The ideal expression of a MIS structure in accumulation regime is: <sup>0</sup> *ac ox k A <sup>C</sup> t* . Non-ideal

effects in MOS capacitors include fixed charge, mobile charge and surface states. Performing a capacitance-voltage measurement allows identifying all three types of charge. Charge existing in the dielectric film shifts the measured curve. Trapping and detrapping of defects inside the insulator produce hysteresis in the high frequency capacitance curve when sweeping the gate voltage back and forth.

Electrical Characterization of High-K Dielectric Gates for Microelectronic Devices 217

bending in the inversion layer near the semiconductor–insulator interface becomes very strong, and a potential well is formed by the interface barrier and the electrostatic potential in the semiconductor. The correct analytical treatment requires solving the complex coupled

The performance of MOS devices strongly depends on the breakdown properties and the current transport behaviors of the gate dielectric films. The conduction mechanisms are very sensitive to the film composition, film processing, film thickness, and energy levels and densities of trap in the insulator films. Therefore, the analysis of the dominant conduction mechanisms may provide relevant information on the physical nature of the dielectric film and complements other characterization techniques when optimizing fabrication process. The most commonly found mechanisms as well as the voltage and temperature laws for

effective mass Schroedinger and Poisson equations self-consistently.

**Figure 3.** Main conduction mechanisms on Metal-Insulator- Semiconductor devices

 **Electrode-limited mechanisms**: When the dielectric has high bandgap, high energy barrier with electrodes and low trap density, conduction is more electrode-limited than bulk limited. For a large applied bias, the silicon surface is n-type degenerated regardless of the bulk doping. Hence, for a large applied voltage the current is limited by tunneling (independent of the temperature) from the vicinity of the silicon conduction band edge through the triangular barrier into the oxide conduction band

**2.2. Current measurements and conduction mechanisms** 

each one are summarized in Figure 3.

Finally, surface states at the semiconductor-insulator interface also modify the CV curves. As the applied voltage varies the Fermi level at the interface changes and affects the occupancy of the surface states. The interface states cause the transition in the capacitance measurement to be stretched out In Figure 2 we show experimental high frequency C-V results for hafnium oxide MIS structures measured at room temperature. Atomic Layer Deposition technique was used to grow these 20 nm-thick HfO2 films

**Figure 2.** 1MHz C-V curves of Al/HfO2/n-Si capacitors obtained by Atomic Layer Deposition

The combination of the low and high frequency capacitance (HLCV) [17] allows calculating the surface state density. This method provides the surface state density over a limited (but highly relevant) range of energies within the bandgap. Measurements on n-type and p-type capacitors at different temperatures provide the surface state density throughout the bandgap. A capacitance meter is usually employed to measure the high-frequency capacitance, *CHF*. The quasi-static measurement of the low frequency capacitance, *CLF*, consists on recording the gate current whereas a ramp-voltage is applied to the gate terminal. Interface state density is obtained according the following expression:

$$\mathbf{D}\_{\mathrm{fl}} = \frac{\mathbf{C}\_{\mathrm{ox}}}{\mathrm{q}} \left( \frac{\mathbf{C}\_{\mathrm{LF}}}{\mathbf{C}\_{\mathrm{ox}} \cdot \mathbf{C}\_{\mathrm{LF}}} \, \frac{\mathbf{C}\_{\mathrm{HF}}}{\mathbf{C}\_{\mathrm{ox}} \cdot \mathbf{C}\_{\mathrm{HF}}} \right) \tag{1}$$

In sub-4 nm oxide layers, C–V measurements provide the same information, but the interpretation of the data requires considerable caution. The assumptions needed to construct the ''classical model'' are no longer valid, and quantum mechanical corrections become mandatory, thus increasing the complexity of the analytical treatment: Maxwell– Boltzman statistics no longer describe the charge density in the inversion and accumulation layers satisfactorily, and should be replaced by Fermi–Dirac statistics. In addition, band bending in the inversion layer near the semiconductor–insulator interface becomes very strong, and a potential well is formed by the interface barrier and the electrostatic potential in the semiconductor. The correct analytical treatment requires solving the complex coupled effective mass Schroedinger and Poisson equations self-consistently.
