**6. Conclusion**

192 Advances in Wavelet Theory and Their Applications in Engineering, Physics and Technology

According to data in Table 2 it may be seen that the PNN1 classification is consistent with the magnitude values calculated for the SDVV. It is observed that in most cases voltage sags were detected in all three phases (classification 1.1.1), and for signals 267 and 268 voltage sags were detected only in phase C, while phase A, and B exhibited adequate voltage magnitudes (classification 2.2.1). It is also worth noting that all these results were compared with the real original voltage waveforms, which proved the results correctness as obtained

Phase A Phase B Phase C

Magnitude (pu)

Time Duration (Cycles)

Magnitude (pu)

Time Duration (Cycles)

18 1 1 1 5.5729 0.8331 5.3542 0.8388 5.1979 0.8696 19 1 1 1 5.5729 0.8275 5.3542 0.8556 5.1875 0.8473 58 1 1 1 2.9583 0.4949 2.8646 0.8710 2.8333 0.8449 59 1 1 1 2.9688 0.4929 2.8646 0.8701 2.5313 0.8393 138 1 1 1 5.5729 0.8331 5.3542 0.8388 5.1979 0.8696 139 1 1 1 5.5729 0.8275 5.3542 0.8556 5.1875 0.8473 249 1 1 1 5.5729 0.8275 5.3542 0.8556 5.1875 0.8473 250 1 1 1 5.5729 0.8331 5.3542 0.8388 5.1979 0.8696 251 1 1 1 5.5729 0.8331 5.3542 0.8388 5.1979 0.8696 252 1 1 1 5.5729 0.8275 5.3542 0.8556 5.1875 0.8473 253 1 1 1 2.9583 0.4949 2.8646 0.8710 2.8333 0.8449 254 1 1 1 2.9688 0.4929 2.8646 0.8701 2.5313 0.8393 255 1 1 1 5.5729 0.8331 5.3542 0.8388 5.1979 0.8696 256 1 1 1 5.5729 0.8275 5.3542 0.8556 5.1875 0.8473 257 1 1 1 5.5729 0.8275 5.3542 0.8556 5.1875 0.8473 258 1 1 1 5.5729 0.8331 5.3542 0.8388 5.1979 0.8696 267 2 2 1 5.1667 0.9317 4.5729 0.9153 5.0313 0.6424 268 2 2 1 5.4792 0.9486 4.5729 0.9140 5.0313 0.6393 279 1 1 1 4.9896 0.4158 5.1771 0.8556 4.8854 0.8942 280 1 1 1 4.8750 0.4171 4.5729 0.8523 4.8125 0.8910 287 1 1 1 3.6875 0.8693 3.4479 0.5332 3.2917 0.8789 288 1 1 1 3.6979 0.8699 3.4479 0.5343 3.3542 0.8906 302 1 1 1 5.5729 0.8331 5.3542 0.8388 5.1979 0.8696 303 1 1 1 5.5729 0.8275 5.3542 0.8556 5.1875 0.8473

Table 2. SDVV classification and quantification results for three-phase voltage signals

For the fault type classification and the faulted phase identification the same 230 kV/500 kV electrical power system was used in which short-circuits were simulated along the transmission lines by varying the incidence angle, and the short-circuit resistance to obtaining a set of voltage waveforms corresponding to the different simulated fault types,

obtained from oscillographic records in a real electrical power system.

using the simulation software ATP.

by the wavelet multiresolution analysis and by the PNN1 classification mechanism.

Magnitude (pu)

Voltage Signal Number

PNN 1 Output

Time Duration (Cycles)

> This work presented a methodology for automatic SDVV classification as well as fault type identification using digital signal processing and computational intelligence techniques. Real power system data were used and satisfactory results for both SDVV and fault type classification were obtained. The implementation of the proposed methodology as part of a computational tool and its integration with the post-operational utility analysis routines will enable the automatic analysis of a larger number of signals waveforms, allowing the methodology proposed here to serve as a basis for future applications where automatic analysis procedures are needed.

> One should also note that the wavelet used in this work was chosen due to its good performance in determining the disturbance location in the signal waveform. Various wavelets orders from db2 to db16 were tested and the db4 wavelet presented the best performance, and considering also the fact that it has filters with few coefficients, the processing time for the signals decomposition is greatly reduced, which is an important characteristic when a large number of signals are to be analyzed.

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**10** 

*Poland* 

Lukas Chruszczyk

*Silesian University of Technology* 

**Wavelet Transform in Fault** 

**Diagnosis of Analogue Electronic Circuits** 

The aim of the chapter is description of a wavelet transform utilisation in fault diagnosis of analogue electronic circuits. The wavelet transform plays a key role in the presented

The chapter, among wavelet transform, contains also applications of other modern computational technique: evolutionary optimisation on example of a genetic algorithm, which has proven to be robust and effective optimisation tool for this kind of problems (Bernier et al. 1995; Goldberg, 1989; Grefenstette, 1981, 1986; Holland 1968; De Jong, 1975,

The author's intention is presentation of a practical utilisation of abovementioned methods (and their combination) in field of testing (fault diagnosis) of analogue electronic circuits.

An electrical and electronic circuit testing is an inseparable part of manufacturing process. Depending on circuit type (analogue, digital, mixed), function (amplifier, oscillator, filter, mixer, nonlinear etc.) and implementation (tube or semiconductor, discrete, integrated) there have been proposed variety of testing methods. Together with development of modern electronic circuits, test engineers face more and more difficult problems related with testing procedures. Common problems are constant grow of complexity, density, functionality, speed and precision of circuits. At the same time contradictory factors like time-to-market, manufacturing and testing cost must be minimised while testing speed maximised. Important problem is also limited access to internal nodes of integrated circuits. All these problems are related to any "life epoch" of electronic circuit: from design itself, through design validation, prototype characterisation, manufacturing, post-production test (quality control) and finally board/field testing (Huertas, 1993). It must be noted: the later a fault is detected, the faster grows related cost. While final functional testing is unavoidable, there is still an effort in finding fast and simple methods detecting at least the most probable

The proposed description of testing methods is limited to fault diagnosis of analogue electronic circuits (AEC). Testing of such circuits meets specific problems (i.e. components tolerance, fault masking, measurement inaccuracy) not presented in testing other circuits

methods and is located in important step of a feature extraction.

1980; Pettey et al., 1987; Suh & Gucht, 1987; Tanese, 1987).

**2. Fault diagnosis of analogue electronic circuits** 

faults in early life stage of a circuit.

**1. Introduction** 

