**2. Fault diagnosis of analogue electronic circuits**

An electrical and electronic circuit testing is an inseparable part of manufacturing process. Depending on circuit type (analogue, digital, mixed), function (amplifier, oscillator, filter, mixer, nonlinear etc.) and implementation (tube or semiconductor, discrete, integrated) there have been proposed variety of testing methods. Together with development of modern electronic circuits, test engineers face more and more difficult problems related with testing procedures. Common problems are constant grow of complexity, density, functionality, speed and precision of circuits. At the same time contradictory factors like time-to-market, manufacturing and testing cost must be minimised while testing speed maximised. Important problem is also limited access to internal nodes of integrated circuits. All these problems are related to any "life epoch" of electronic circuit: from design itself, through design validation, prototype characterisation, manufacturing, post-production test (quality control) and finally board/field testing (Huertas, 1993). It must be noted: the later a fault is detected, the faster grows related cost. While final functional testing is unavoidable, there is still an effort in finding fast and simple methods detecting at least the most probable faults in early life stage of a circuit.

The proposed description of testing methods is limited to fault diagnosis of analogue electronic circuits (AEC). Testing of such circuits meets specific problems (i.e. components tolerance, fault masking, measurement inaccuracy) not presented in testing other circuits

Wavelet Transform in Fault Diagnosis of Analogue Electronic Circuits 199

than the smallest time constant of a linear CUT. This ensures good approximation of a continuous excitation x(t) by its discrete equivalent. Maximal time length tmax of excitation x(t) (so its discrete approximation x(n) as well) is set to be 5 times greater than the longest time constant of a linear CUT. Value of each sample xn is quantised to *K* levels (fig. 3):

> �� � �(��) ���� � �� � �� � ������� � � �, �, … , ��

*x(t)*

*x(n)*

*t2 t3*

In order to consider influence of real digital-to-analogue (A/D) converters, there have been

*x4,t4*

*x5,t5 x7,t7*

*t6*

There have been analysed only single catastrophic (hard) and parametric (soft) circuit faults,

Fig. 2. General form of an input excitation

Fig. 3. Input excitation sampling

used two types of x(n) approximations:

because such faults are the most probable.

1. "step-shape" (0th-order polynomial), fig. 4, 2. piece-wise linear (1st-order polynomial), fig. 5.

*x1,t1*

*x6*

*x2*

*x3*

{�(��), �(��), �(��), … } � �(�) (2)

*tmaks*

*t*

*n*

*x8,t8*

(3)

types (e.g. digital). Utilisation of a wavelet transform can greatly improve efficiency of selected fault diagnosis and, in some cases, makes the diagnosis feasible at all. The wavelet transform is used here as a feature extraction procedure. It must be noted that despite of dominant role of a digital and microprocessor electronic devices, there will never be escape from analogue circuits. Growing complexity of analogue and mixed-level electronic systems (e.g. system-on-chip – SoC) still rises the bar for testing methods (Baker et al., 1996; Balivada et al., 1996; Chruszczyk et al. 2006, 2007; Chruszczyk & Rutkowski 2008, 2009, 2011; Chruszczyk 2011; Dali & Souders 1989; Kilic & Zwolinski, 1999; Milne et al., 1997; Milor & Sangiovanni-Vincentelli, 1994; Pecenka et al., 2008; Saab et al. 2001; Savir & Guo, 2003; Somayajula et al., 1996).

#### **2.1 Test environment**

There have been taken following assumptions on the test procedure:

	- a. output voltage y1(t),
	- b. input current y2(t),
	- c. supply currents y3(t) and y4(t).

Fig. 1. Assumed test procedure

There are only measured output voltage y1(t) and input current y2(t) in case of a passive circuits.

The optimisation goal is the best shape of input excitation voltage (in time-domain). Generally, it can be described as a continuous time function x(t) (fig. 2):

$$\mathbf{x}(t) \in \mathbb{R}; \quad t \in [0, t\_{\max}] \tag{1}$$

Due to practical reasons, there has been assumed discrete form of excitation x(n) described by sequence of NP samples xn with constant sampling period Ts. The sampling period always conforms Whittaker-Nyquist-Kotelnikov-Shannon sampling theorem for excitation x(t) and all measured CUT responses. Additionally, value of Ts is set to be 10 times smaller

types (e.g. digital). Utilisation of a wavelet transform can greatly improve efficiency of selected fault diagnosis and, in some cases, makes the diagnosis feasible at all. The wavelet transform is used here as a feature extraction procedure. It must be noted that despite of dominant role of a digital and microprocessor electronic devices, there will never be escape from analogue circuits. Growing complexity of analogue and mixed-level electronic systems (e.g. system-on-chip – SoC) still rises the bar for testing methods (Baker et al., 1996; Balivada et al., 1996; Chruszczyk et al. 2006, 2007; Chruszczyk & Rutkowski 2008, 2009, 2011; Chruszczyk 2011; Dali & Souders 1989; Kilic & Zwolinski, 1999; Milne et al., 1997; Milor & Sangiovanni-Vincentelli, 1994; Pecenka et al., 2008; Saab et al. 2001; Savir & Guo, 2003;

There have been taken following assumptions on the test procedure:

*y2(t)*  Input current

1. the only available test nodes of a circuit under test (CUT) are the external nodes, 2. CUT is excited by aperiodic excitation and its shape is optimised for given circuit, 3. the only available information about CUT state is read from measurement of four

There are only measured output voltage y1(t) and input current y2(t) in case of a passive

Circuit under test *x(t) y1(t)* 

*y4(t)* 

*y3(t)* 

The optimisation goal is the best shape of input excitation voltage (in time-domain).

Due to practical reasons, there has been assumed discrete form of excitation x(n) described by sequence of NP samples xn with constant sampling period Ts. The sampling period always conforms Whittaker-Nyquist-Kotelnikov-Shannon sampling theorem for excitation x(t) and all measured CUT responses. Additionally, value of Ts is set to be 10 times smaller

�(�) � �� � � ��� ����] (1)

Supply current "**–**"

Supply current "**+**"

Circuit response (output voltage)

Generally, it can be described as a continuous time function x(t) (fig. 2):

Somayajula et al., 1996).

**2.1 Test environment** 

quantities (fig. 1): a. output voltage y1(t), b. input current y2(t),

Excitation (input voltage)

Fig. 1. Assumed test procedure

circuits.

c. supply currents y3(t) and y4(t).

than the smallest time constant of a linear CUT. This ensures good approximation of a continuous excitation x(t) by its discrete equivalent. Maximal time length tmax of excitation x(t) (so its discrete approximation x(n) as well) is set to be 5 times greater than the longest time constant of a linear CUT. Value of each sample xn is quantised to *K* levels (fig. 3):

$$\{\mathbf{x}(t\_1), \mathbf{x}(t\_2), \mathbf{x}(t\_3), \dots\} \in \mathfrak{x}(t) \tag{2}$$

$$\begin{array}{c} \mathfrak{x}\_n = \mathfrak{x}(t\_n) \\ t\_{n+1} - t\_n = T\_s = \text{const} \end{array} ; \quad n = 1, 2, \dots, N\_p \end{array} \tag{3}$$

#### Fig. 2. General form of an input excitation

Fig. 3. Input excitation sampling

In order to consider influence of real digital-to-analogue (A/D) converters, there have been used two types of x(n) approximations:


There have been analysed only single catastrophic (hard) and parametric (soft) circuit faults, because such faults are the most probable.

Wavelet Transform in Fault Diagnosis of Analogue Electronic Circuits 201

The L–Tester (fault location) points which circuit element is faulty or decision "?", if proper

The deepest level: fault identification (information about faulty element value or at least its

Response

Decision

*NO GO ?* 

*?* 

*?* 

*margin* 

analyser Decision

*GO* 

} *NO GO* 

*Faulty element ID* 

*Faulty element value or its shift outside the tolerance* 

shift – represented by I–Tester) has not been analysed in this work.

TESTER

Generator *(excitation)*

> Fault detection

D-TESTER – fault detector

L-TESTER – fault locator I-TESTER – fault identificator

> Fault location

Fault identification

Response measurement

classification cannot be performed.

Fig. 6. General tester structure

Information

Circuit under test

Circuit under test

Fig. 7. Fault diagnosis levels
