**6.2. Experimental demonstrator device**

## *6.2.1. Device concept and aim*

The aim of an experimental demonstrator device is to investigate the impact of individual sub-components on the performance of the whole device, as well as to have the opportunity to flexibly perform device modifications without the need of redesigning complex RF-PCBs. The device is organized in a modular concept as symbolically depicted in Fig. 51. Fig. 52 shows an example of a demonstrator implementation of such kind.

The individual sub-components as e.g. shift register for stimulus generation, T&H-circuits, RF-power distribution, RF-synchronization etc. are organized as plug-ins. Hence, one can simply replace a device component by a new one if improved circuits, better IC-housing or 422 Ultra-Wideband Radio Technologies for Communications, Localization and Sensor Applications

RF-PCBs are available. Furthermore, the various modules may be interconnected to different device structures as shown in Fig. 4 or Fig. 55.

HaLoS – Integrated RF-Hardware Components for Ultra-Wideband Localization and Sensing 423

The clock synchronization unit which precisely defines the receiver sampling points is a 9*th* order binary divider with a maximal toggle rate of 24 GHz. Random fluctuations of the sampling point (jitter) could be reduced down to some tens of femtoseconds [48] due to the balanced circuit topology and the optimized architecture of the timing system (see [2], [49] detailed discussions). Note, that the time position uncertainty of the measured impulse response (compare Fig. 5) is father decreased as consequence of the impulse compression

The clock distribution plug-in is an active device which recovers and distributes the sampling clock among the receivers and the analog-to-digital converters. The unit can handle clock pulses with 20 ps falling/rising edges and features wideband reverse signal

The receivers are ultra wideband sampling gates with an 18 GHz analog input bandwidth, better than -40 dB signal feed-through over the full bandwidth, -15 dBm input compression points and a decay rate of about 20 % per ms relative to full scale (i.e. 5…200 ppm per sampling cycle depending on the clock rate (0.5 – 20 GHz) of the system). Other potential

The transmitter-receiver and receiver-receiver cross-talk is better than 130 dB over the full operational band. In order to achieve this value, attention was paid to RF-housing, clock signal distribution and power supply decoupling (see also Fig. 57). The recent configuration of the demonstrator RF electronics is able to handle (internally) up to about 70 000 IRFs per second ( 9*th* order M-sequence at 18 GHz system clock). The data transfer to a host PC (based on commercial standard interfaces like USB and LAN) reduces, however, the actually achievable update rate to about 300 IRFs/s. The corresponding gap is filled by synchronous averaging in order to use the available data amount for noise suppression. The achievable receiver dynamic is about 114 dB @ 1 IRF/s. It has to be noted that device non-linearity is classically qualified by the intercept point which is based on a Taylor-series model of the device under test and sine wave stimulation. In order to keep this established philosophy,

This is illustrated by Fig. 53. In the example at the top, the Tx- and RX-port of an Msequence device were connected via a variable attenuator and the impulse response was recorded for attenuator values between 0 and 120 dB. In the case of very weak input signals (large attenuation), we can only observe noise and device internal cross-talk. If we reduce the attenuation, the wanted signal peak (it is called "main pulse" in Fig. 53) appears and increases linearly with the signal level while the cross-talk level remains constant. By reducing the attenuation further, other signal parts become to protrude from noise. They also increase linearity at the beginning. These signals are caused from device internal reflections, deviations from the ideal time shape of an M-sequence and misalignments of the ADC timing (refer to Fig. 54). We call them device internal clutter. For very high signal levels, the receiver will tend to saturate which leads to the compression of the main peak and the internal clutter signals. Furthermore, the appearing non-linear distortions create

components of the experimental demonstrator are discussed in sub-chapters 3 to 5.

(i.e. correlation; see [2] for discussion).

rejection better than 40 dB per branch.

the approach was extended to wideband signals [48].

**Figure 51.** Modular concept of the experimental system.

**Figure 52.** Photograph of the demonstrator implementation example.
