**8.2. Development framework**

The FPGA-based hybrid hardware-in-the-loop research and design space exploration (DSE) framework created in this work combines high-level tools (e.g. MATLAB/Simulink) and optimized hardware blocks [17]. Its application domain ranges from the design, optimization and verification of efficient and optimized signal processing blocks for computationally demanding next-generation wireless communication systems to system characterization and DSE.

**Figure 10.** Emulation framework block diagram

The framework consists of a host PC, FPGA-based emulation systems, a generic fully synthesizeable VHDL SoC infrastructure, dedicated processors, processor softcores and a software library providing a transparent communication application programming interface (API). This allows signal processing blocks to be split and run distributed on a highly heterogeneous signal processing system. Software API libraries provide unified transparent communication between MATLAB, C/C+, embedded software and the hardware on-chip multilayer bus system. The same resources are accessible from all components, enabling a flexible partitioning and migration of processing task between high-level software, embedded software and dedicated hardware modules. The framework block diagram is shown in Figure 10. The properties of the optimized on-chip infrastructure template make it suitable for usage in final ASIC targets and thus enable the test, debugging and characterization of signal processing blocks in their target environment. Using standard FPGA design flows, new computationally intensive processing cores are directly implemented as the optimized hardware target modules. Instrumentation is used to enable dynamic, software controlled parameter adjustment. The remaining blocks may continue to run as high-level models, enabling a divide-and-conquer implementation and verification approach. The framework provides transparent data transport between the substituted MATLAB modules and multiple parallel instances of their FPGA hardware counterparts. The same interfaces are available for hardware simulation via the Modelsim foreign language interface (FLI), effectively also providing a verification and debugging environment at minimal extra effort.

The PC is connected to the emulation systems via Gigabit Ethernet. The generic FPGA infrastructure template comprises an OCP multilayer bus, the ethernet DMA interface, SDRAM controllers, on-chip memories and massively parallel parameterized softcore processors [20]. It has been adapted to and tested on a Xilinx Virtex-6 LX550T based BEE4 rapid prototyping system, the Xilinx Virtex-6 ML605 Evaluation Kit and the Virtex-5 LX220 based MCPA board [2] developed at IMS, see Fig. 11.

**Figure 11.** FPGA-based emulation system developed at IMS
