**4. Transmitter circuits**

### **4.1. Introduction**

396 Ultra-Wideband Radio Technologies for Communications, Localization and Sensor Applications

reduction in output signal power can be observed for all frequencies.

**Figure 17.** Signal subtraction enabled by the feedback-sampling amplifier.

The feedback-sampling amplifier of the preceding subsection is expected to perform well as long as the assumption of (reasonable) small input signals is justified. A key requirement in the feedback-sampling concept is linearity preceding the signal subtraction in order not to distort the zero crossings which are sampled by the analog-to-digital converter. However, as soon as array operation is considered, antenna cross-talk is likely to violate this assumption. In addition, a dense antenna array requires the antennas to have small outer dimensions. This can be achieved by dielectrically scaling the antennas, which - in turn - leads to a low (7 Ω) feeding point impedance. The latter has to be interfaced by the subtraction circuit. The topology shown in Fig. 18 is a first approach towards an analog subtractor which provides appropriate single-ended inputs to interface with both, a dielectrically scaled antenna and

*3.4.2. Subtractor with Low Impedance antenna interface* 

7 Rhode & Schwarz SMJ100A 8 Rhode & Schwarz FSV

Those measurements were obtained from a test set-up incorporating the PM 8 probe station with GSSG-probes, in which two signal generators7 synchronized by a frequency standard provided the input signals to both inputs at appropriate power levels via two hybrid couplers. The differential output signal of the DUT was recombined by a third hybrid coupler and displayed by a signal analyzer8. In Fig. 17, no loss compensation is applied and results are clipped to 100 kHz span. Two cases can be distinguished: First, the digital prediction signal has been switched off (DAC*off*) and only the RF signal has been present at the inputs. Then, also the prediction signal has been applied (DAC*on*) and a notable

> The circuits introduced in this section serve for the M-sequence topology. They have been implemented in a cost-efficient 0.25 µm Silicon Germanium BiCMOS technology, which opens up new fields of ultra-wideband radar applications. In the following sub-chapters, the design of different hardware blocks for the ultra-wideband radar front-end is presented. The design of a multi-purpose M-Sequence generator is presented which acts as a pulse compression modulator and exhibits an up-conversion mixer. A highly efficient powerdistributed amplifier has been implemented utilizing a novel cascode power matching

approach to achieve superior output power performance. Additionally, a fully differential broadband amplifier using cascaded emitter followers has been designed that exhibits a variable gain control and excellent broadband performance.

HaLoS – Integrated RF-Hardware Components for Ultra-Wideband Localization and Sensing 399

Output

**Figure 19.** Nine bit linear feedback shift register for 9*th* order M-Sequence.

Modulo 2 adder

voltage swing in a wide range.

of up-conversion for the radar signal.

sequences with a mutual shift of half the word length. Those are multiplexed to yield the same M-sequence at twice the data rate. The input for the multiplexer is set between the two latches of the fifth flip-flop highlighted Fig. 20. This leads to a phase shift of half the pulse width in order to achieve the maximum voltage swing at the input of the multiplexer. Thus, the proposed architecture makes it possible to boost the circuit performance at the cost of an additional adder and a multiplexer. The architecture is extended to provide the possibility of upconversion for the generated M-sequence. This has been facilitated by implementing a mixer core at the output of the multiplexed LFSR. The mixer performs a BPSK modulation of the 9*th* order M-sequence signal generated by the multiplexed shift register. The circuit was implemented as an XOR gate instead of a conventional Gilbert cell as opposed to [34]. The actual circuit is nearly identical but the XOR operates in the limiting region compared to the small-signal operation of the Gilbert cell. The limiting behavior simplifies the design and requirements of the mixer, and results in lower power consumption. No emitter degeneration has to be implemented to increase linearity for large signal inputs. The XOR gate is driven by a LO buffer that can be digitally controlled to allow the generation of baseband M-sequence signals without the need for up-conversion. An additional output buffer with a resistively matched output has been included in order to control the output

1 2 4 3 5 6 7 8 9

**Figure 20.** Circuit architecture of the proposed <sup>9</sup> 2 1 M-sequence generator providing the possibility

### **4.2. M-sequence generator**

The well-known very broadband spectrum of M-sequences is widely used for testing the correct functionality of broadband integrated circuits, such as amplifiers, multiplexers, and transceivers. The run for higher data rates and amplifiers with broader bandwidth often outperforms commercially available test equipment and necessitates some sources to test these circuits. The measurement equipment vendors cannot supply data sources as fast as the technology evolves. The application which is targeted in this chapter is that M-sequences are used for pulse compression in ultra-wideband radar systems. For this application, it is important that the generator consumes little energy only, and it should generate a sequence of appropriate length (see (2)). Early high-speed PRBS generators for high data rates have been employed in III/V HBT technologies [28]. Moreover, a 110 Gb/s PRBS generator has been published in [29] using InP HBT technology with a transit frequency ( *<sup>T</sup> f* ) more than 300 GHz. Recently, several PRBS generator circuits have been published in SiGe bipolar technology for test purposes in fiber-optic communications. In [30] a 100 Gb/s <sup>7</sup> 2 1 PRBS generator has been implemented in a 200 GHz *<sup>T</sup> f* SiGe bipolar technology. As in the 80 Gb/s <sup>31</sup> 2 1 pseudo random binary sequence generator introduced in [31], the output of the shift register has been multiplexed to achieve a higher maximum data rate. However, these circuits have a power consumption of 1.9-9.8W and utilize cost-intensive high-end processes. A 4 23 Gb/s <sup>7</sup> 2 1 PRBS generator with a power consumption of 60 mW per lane has been publicized in [32] utilizing a 150 GHz *<sup>T</sup> f* SiGe BiCMOS technology. A <sup>7</sup> 2 1 multiplexed PRBS generator in 0.13 µm bulk CMOS exhibits 24 Gb/s output data rate [33]. In the following section, the circuit implementation with measurement results of the M-Sequence generator is presented.

### *4.2.1. Upconverted M-sequence generator*

A simple way to generate M-sequences is to utilize a digital linear feedback shift register (LFSR), as depicted in Fig. 19. This device generates a binary pseudo-random code of length 2 1 *<sup>n</sup>* , where n is the number of stages in the shift register. Feedback is provided by adding the output of the shift register, modulo two, to the output of one of the previous stages. The actual sequence obtained depends on both the feedback connections and the initial loading of the register.

The proposed architecture depicted in Fig. 20 consists of serially connected shift registers with the characteristic polynomial

$$f\left(\mathbf{x}\right) = \mathbf{x}^{\mathcal{Y}} \oplus \mathbf{x}^{\mathcal{Y}} \oplus \mathbf{l} \tag{23}$$

an additional XOR gate acting as a modulo-2 adder to yield the delayed sequence, and one multiplexer. The selected feedback in the proposed architecture enables to generate two M-

**Figure 19.** Nine bit linear feedback shift register for 9*th* order M-Sequence.

398 Ultra-Wideband Radio Technologies for Communications, Localization and Sensor Applications

published in [29] using InP HBT technology with a transit frequency ( *<sup>T</sup>*

variable gain control and excellent broadband performance.

**4.2. M-sequence generator** 

implemented in a 200 GHz *<sup>T</sup>*

*4.2.1. Upconverted M-sequence generator* 

with the characteristic polynomial

utilizing a 150 GHz *<sup>T</sup>*

of the register.

approach to achieve superior output power performance. Additionally, a fully differential broadband amplifier using cascaded emitter followers has been designed that exhibits a

The well-known very broadband spectrum of M-sequences is widely used for testing the correct functionality of broadband integrated circuits, such as amplifiers, multiplexers, and transceivers. The run for higher data rates and amplifiers with broader bandwidth often outperforms commercially available test equipment and necessitates some sources to test these circuits. The measurement equipment vendors cannot supply data sources as fast as the technology evolves. The application which is targeted in this chapter is that M-sequences are used for pulse compression in ultra-wideband radar systems. For this application, it is important that the generator consumes little energy only, and it should generate a sequence of appropriate length (see (2)). Early high-speed PRBS generators for high data rates have been employed in III/V HBT technologies [28]. Moreover, a 110 Gb/s PRBS generator has been

Recently, several PRBS generator circuits have been published in SiGe bipolar technology for test purposes in fiber-optic communications. In [30] a 100 Gb/s <sup>7</sup> 2 1 PRBS generator has been

random binary sequence generator introduced in [31], the output of the shift register has been multiplexed to achieve a higher maximum data rate. However, these circuits have a power consumption of 1.9-9.8W and utilize cost-intensive high-end processes. A 4 23 Gb/s <sup>7</sup> 2 1 PRBS generator with a power consumption of 60 mW per lane has been publicized in [32]

µm bulk CMOS exhibits 24 Gb/s output data rate [33]. In the following section, the circuit

A simple way to generate M-sequences is to utilize a digital linear feedback shift register (LFSR), as depicted in Fig. 19. This device generates a binary pseudo-random code of length 2 1 *<sup>n</sup>* , where n is the number of stages in the shift register. Feedback is provided by adding the output of the shift register, modulo two, to the output of one of the previous stages. The actual sequence obtained depends on both the feedback connections and the initial loading

The proposed architecture depicted in Fig. 20 consists of serially connected shift registers

an additional XOR gate acting as a modulo-2 adder to yield the delayed sequence, and one multiplexer. The selected feedback in the proposed architecture enables to generate two M-

implementation with measurement results of the M-Sequence generator is presented.

*f* SiGe bipolar technology. As in the 80 Gb/s <sup>31</sup> 2 1 pseudo

9 5 *fx x x* 1 (23)

*f* SiGe BiCMOS technology. A <sup>7</sup> 2 1 multiplexed PRBS generator in 0.13

*f* ) more than 300 GHz.

sequences with a mutual shift of half the word length. Those are multiplexed to yield the same M-sequence at twice the data rate. The input for the multiplexer is set between the two latches of the fifth flip-flop highlighted Fig. 20. This leads to a phase shift of half the pulse width in order to achieve the maximum voltage swing at the input of the multiplexer. Thus, the proposed architecture makes it possible to boost the circuit performance at the cost of an additional adder and a multiplexer. The architecture is extended to provide the possibility of upconversion for the generated M-sequence. This has been facilitated by implementing a mixer core at the output of the multiplexed LFSR. The mixer performs a BPSK modulation of the 9*th* order M-sequence signal generated by the multiplexed shift register. The circuit was implemented as an XOR gate instead of a conventional Gilbert cell as opposed to [34]. The actual circuit is nearly identical but the XOR operates in the limiting region compared to the small-signal operation of the Gilbert cell. The limiting behavior simplifies the design and requirements of the mixer, and results in lower power consumption. No emitter degeneration has to be implemented to increase linearity for large signal inputs. The XOR gate is driven by a LO buffer that can be digitally controlled to allow the generation of baseband M-sequence signals without the need for up-conversion. An additional output buffer with a resistively matched output has been included in order to control the output voltage swing in a wide range.

**Figure 20.** Circuit architecture of the proposed <sup>9</sup> 2 1 M-sequence generator providing the possibility of up-conversion for the radar signal.

### 400 Ultra-Wideband Radio Technologies for Communications, Localization and Sensor Applications

Once the functional simulations have been completed, each individual block is designed on the transistor level. As the multiplexing architecture has been chosen, the flip-flops only have to work at half the operation speed. Standard CML flip-flops have been designed consisting of two latches, which inhibit two differential pairs. A schematic diagram of a CML flip-flop is depicted in Fig. 21. The flip-flops used in the LFSR are designed to offer a differential output voltage of 2 300 mV. According to [31], the tail current *TI* and the emitter area *Ae* are related by

$$A\_e = l\_e \times \pi v\_e = \frac{I\_T}{1.5 I\_{peak \, f\_T}} \tag{24}$$

HaLoS – Integrated RF-Hardware Components for Ultra-Wideband Localization and Sensing 401

the output is not an M-sequence. A simulated waveform of a 25 Gb/s M-sequence is shown in Fig. 22 using the techniques described above. It can be seen that every bit can be distinguished from each other. A single bit has a slightly lower output voltage than a bit sequence with the same value, which is caused by the limited output bandwidth. As mentioned before, the mixer and the output buffer both have a limiting character which attenuates the flip-flop glitches. Thus, the waveform exhibits low ripple, actually at sequences with a series of equal bits, which indicates that the clock feed through is very low. However, the output waveform exhibits some deviations, which is quite common for circuits at this high data rate. This behavior may result from the slightly inductive behavior of an emitter follower in the signal chain. As long as the circuit is stable, this does not cause

The M-sequence generator chip is placed on a Rogers TMM10i ceramic substrate for wire bonding. In order to protect the circuit mechanically and keep the bond wires as short as possible, it is placed in a topside cavity and fixed utilizing an electrical and thermal conductive epoxy glue, as shown in Fig. 23. The thickness of the ceramic substrate has been chosen to be 381 µm, which is almost equal to the chip height of 370 µm and the glue. Thus, the distance between the substrate edge and the bond pad can be reduced. The continuous ground plane below ensures a good thermal conduction, and 1.2 mm thick *FR*4 stabilize

time (ns)

0.5 2 2.5 3

1 1.5

The correct function of the generator can be checked through calculation of the normalized autocorrelation function of one complete M-sequence. The calculation of the ACF has been implemented in Matlab. As the correlation properties are of substantial interest for radar applications utilizing pulse compressed waveforms, the PRBS signal is measured with an Agilent DSO 91204A oscilloscope and compared with the simulation results. The simulated and measured 10 Gb/s waveforms together with the normalized cross correlation function of

**Figure 22.** Simulated M-sequence waveform at 25 Gb/s data rate.




differential

 output voltage

 (V)

0

0.3

0.2

0.1

the brittle ceramic substrate.

the measured signal are presented in Fig. 24.

problems.

for fastest switching time such that *<sup>T</sup> peak f <sup>J</sup>* is the current density for maximum *<sup>T</sup> f* . The lowest tail current is set by the minimum allowed transistor size, which is 0.84 0.42 *e e l w m µm* . Thus, the tail current is chosen to be 0.85 mA whereby the collector current for the maximum transit frequency *<sup>T</sup> f* is 1.25 mA for a 84 0.42 *µm µm* transistor. The output voltage swing of each flip-flop was set to 2 250 mV. Simulations indicate that the latches work up to 12.5 Gb/s, which is sufficient for a 25 Gb/s multiplexed M-sequence.

**Figure 21.** Schematic diagram of a CML flip-flop.

### *4.2.2. Simulated and measured results*

The M-sequence generator has been simulated in time domain to find out the maximum data rate and to verify the correct function of the register. At clock frequencies higher than the maximum allowable clock frequency, the PRBS register does not work as expected and the output is not an M-sequence. A simulated waveform of a 25 Gb/s M-sequence is shown in Fig. 22 using the techniques described above. It can be seen that every bit can be distinguished from each other. A single bit has a slightly lower output voltage than a bit sequence with the same value, which is caused by the limited output bandwidth. As mentioned before, the mixer and the output buffer both have a limiting character which attenuates the flip-flop glitches. Thus, the waveform exhibits low ripple, actually at sequences with a series of equal bits, which indicates that the clock feed through is very low. However, the output waveform exhibits some deviations, which is quite common for circuits at this high data rate. This behavior may result from the slightly inductive behavior of an emitter follower in the signal chain. As long as the circuit is stable, this does not cause problems.

**Figure 22.** Simulated M-sequence waveform at 25 Gb/s data rate.

400 Ultra-Wideband Radio Technologies for Communications, Localization and Sensor Applications

emitter area *Ae* are related by

0.84 0.42 *e e l w m µm* 

M-sequence.

Dp

RL RL

Dn

Vref

Once the functional simulations have been completed, each individual block is designed on the transistor level. As the multiplexing architecture has been chosen, the flip-flops only have to work at half the operation speed. Standard CML flip-flops have been designed consisting of two latches, which inhibit two differential pairs. A schematic diagram of a CML flip-flop is depicted in Fig. 21. The flip-flops used in the LFSR are designed to offer a differential output voltage of 2 300 mV. According to [31], the tail current *TI* and the

*<sup>T</sup> ee e*

lowest tail current is set by the minimum allowed transistor size, which is

transistor. The output voltage swing of each flip-flop was set to 2 250 mV. Simulations indicate that the latches work up to 12.5 Gb/s, which is sufficient for a 25 Gb/s multiplexed

The M-sequence generator has been simulated in time domain to find out the maximum data rate and to verify the correct function of the register. At clock frequencies higher than the maximum allowable clock frequency, the PRBS register does not work as expected and

Cp Cp

Cn

Qn

Rdc Rdc

*<sup>I</sup> A lw*

for fastest switching time such that *<sup>T</sup> peak f <sup>J</sup>* is the current density for maximum *<sup>T</sup>*

Vcc

collector current for the maximum transit frequency *<sup>T</sup>*

**Figure 21.** Schematic diagram of a CML flip-flop.

*4.2.2. Simulated and measured results* 

1.5 *<sup>T</sup>*

*peak f*

. Thus, the tail current is chosen to be 0.85 mA whereby the

RL RL

*<sup>J</sup>* (24)

*f* is 1.25 mA for a 84 0.42 *µm µm*

Qp

Qn

*f* . The

The M-sequence generator chip is placed on a Rogers TMM10i ceramic substrate for wire bonding. In order to protect the circuit mechanically and keep the bond wires as short as possible, it is placed in a topside cavity and fixed utilizing an electrical and thermal conductive epoxy glue, as shown in Fig. 23. The thickness of the ceramic substrate has been chosen to be 381 µm, which is almost equal to the chip height of 370 µm and the glue. Thus, the distance between the substrate edge and the bond pad can be reduced. The continuous ground plane below ensures a good thermal conduction, and 1.2 mm thick *FR*4 stabilize the brittle ceramic substrate.

The correct function of the generator can be checked through calculation of the normalized autocorrelation function of one complete M-sequence. The calculation of the ACF has been implemented in Matlab. As the correlation properties are of substantial interest for radar applications utilizing pulse compressed waveforms, the PRBS signal is measured with an Agilent DSO 91204A oscilloscope and compared with the simulation results. The simulated and measured 10 Gb/s waveforms together with the normalized cross correlation function of the measured signal are presented in Fig. 24.

402 Ultra-Wideband Radio Technologies for Communications, Localization and Sensor Applications

HaLoS – Integrated RF-Hardware Components for Ultra-Wideband Localization and Sensing 403

1

*j C*

*a*

(25)

*a*

(27)

(26)

*f* of the LC low pass can be

amplifier performance, which is limited by the characteristics of the active cells used [35], alternative structures are investigated. The cascode cell is an appealing circuit due to its higher output impedance, higher breakdown voltage, and reduced Miller effect. Moreover, loading the two transistors by the required impedance for optimum power leads to an output power twice as high as compared to a single transistor. However, the conventional cascode configuration does not meet these conditions since the common base transistor's ( *cb T* ) low-input impedance restricts the output voltage excursion of the common emitter transistor ( *ce T* ). Therefore, it does not see its optimum power load impedance. In addition, the power performance of the cascode cell becomes one of the most important challenges to obtain maximum output power over the required bandwidth. To be power optimized, another series capacitor *Ca* is inserted on the base of *cb T* to avoid its early power saturation compared to *ce T* . A small signal model of the modified cascode gain cell is depicted in Fig. 25. The input impedance of the common base transistor can be calculated as follows:

, ,2 ,2

The capacitor *Ca* and input impedance *in cb* , *z* act as a voltage divider between the optimum

In order to achieve higher gain and greater bandwidth, an additional inductor is added between the collector of *ce T* and the emitter of *cb T* . The influence of a 1.5 nH inductor and various capacitances on the voltage gain of the cascode cell is demonstrated in Fig. 26. The small-signal schematic diagram of the modified cascode cell with inductive peaking is presented in Fig. 27a. The output resistance of the modified cascode circuit can be written as

> ,2 ,1 ,2 ,2 1 || *out ce a ce be b*

neglecting the influence of miller capacitance *cb c* . This leads to a resonance effect which is

1

*C c*

The resonant frequency shows good agreement with the theoretical considerations set out in

Another effect is that the output impedance of the cascode cell increases significantly from 2 to 15 GHz under the influence of the 1.5 nH inductor. The initial values for *La* and *Ca* are then optimized under large-signal conditions using nonlinear simulations of the inductively

*<sup>f</sup> LCc*

*a a be a be*

,.2 ,2

*z z jL z z R j C*

*r*

dominated by *<sup>a</sup> L* , *Ca* and *be c* . The self-resonant frequency *<sup>r</sup>*

*in cb be b*

*z rR*

values for *ce*,1 *v* and *be*,2 *v* .

calculated as

(27).

**Figure 23.** Photograph of the bonded M-sequence generator chip placed in a topside cavity on a ceramic substrate.

**Figure 24.** Simulated (top) and measured (middle) time domain representation of the proposed 10 Gb/s M-Sequence and their normalized cross correlation function.

### **4.3. Distributed power amplifier**

The transmitted random sequence is subjected to high losses especially when transmitted through human body cells. Thus, a power amplifier is required to be placed directly before the antenna to increase the signal power. Distributed amplifiers (DAs) are appealing aspirants for UWB systems due to their inherently large bandwidth. The two major challenges in designing distributed power amplifiers are maintaining high linearity over the entire bandwidth, since narrowband linearization techniques cannot be utilized, and achieving high output power and efficiency. In order to increase the HBT distributed power amplifier performance, which is limited by the characteristics of the active cells used [35], alternative structures are investigated. The cascode cell is an appealing circuit due to its higher output impedance, higher breakdown voltage, and reduced Miller effect. Moreover, loading the two transistors by the required impedance for optimum power leads to an output power twice as high as compared to a single transistor. However, the conventional cascode configuration does not meet these conditions since the common base transistor's ( *cb T* ) low-input impedance restricts the output voltage excursion of the common emitter transistor ( *ce T* ). Therefore, it does not see its optimum power load impedance. In addition, the power performance of the cascode cell becomes one of the most important challenges to obtain maximum output power over the required bandwidth. To be power optimized, another series capacitor *Ca* is inserted on the base of *cb T* to avoid its early power saturation compared to *ce T* . A small signal model of the modified cascode gain cell is depicted in Fig. 25. The input impedance of the common base transistor can be calculated as follows:

402 Ultra-Wideband Radio Technologies for Communications, Localization and Sensor Applications

GND GND

VbVccRst

out+

out-

fc+

fc-



0

1

amplitude

amplitude

norm. CCF

 (V)

 (V)

**Figure 23.** Photograph of the bonded M-sequence generator chip placed in a topside cavity on a

GND fr+ fr- GND

0 2 4 6 8 10

time (ns)

0 2 4 6 8 10

time (ns)


time (ns)

**Figure 24.** Simulated (top) and measured (middle) time domain representation of the proposed 10 Gb/s

The transmitted random sequence is subjected to high losses especially when transmitted through human body cells. Thus, a power amplifier is required to be placed directly before the antenna to increase the signal power. Distributed amplifiers (DAs) are appealing aspirants for UWB systems due to their inherently large bandwidth. The two major challenges in designing distributed power amplifiers are maintaining high linearity over the entire bandwidth, since narrowband linearization techniques cannot be utilized, and achieving high output power and efficiency. In order to increase the HBT distributed power

M-Sequence and their normalized cross correlation function.

**4.3. Distributed power amplifier** 

ceramic substrate.

$$r\_{in,cb} = r\_{be,2} + R\_{b,2} + \frac{1}{j\alpha C\_a} \tag{25}$$

The capacitor *Ca* and input impedance *in cb* , *z* act as a voltage divider between the optimum values for *ce*,1 *v* and *be*,2 *v* .

In order to achieve higher gain and greater bandwidth, an additional inductor is added between the collector of *ce T* and the emitter of *cb T* . The influence of a 1.5 nH inductor and various capacitances on the voltage gain of the cascode cell is demonstrated in Fig. 26. The small-signal schematic diagram of the modified cascode cell with inductive peaking is presented in Fig. 27a. The output resistance of the modified cascode circuit can be written as

$$z\_{out} \approx z\_{ce,2} + \left[ \left( joL\_a + z\_{ce,1} \right) \mid \left( z\_{be,2} + R\_{b,2} + \frac{1}{joC\_a} \right) \right] \tag{26}$$

neglecting the influence of miller capacitance *cb c* . This leads to a resonance effect which is dominated by *<sup>a</sup> L* , *Ca* and *be c* . The self-resonant frequency *<sup>r</sup> f* of the LC low pass can be calculated as

$$f\_r = \frac{1}{\pi \sqrt{\frac{L\_a \ C\_a \ c\_{be,2}}{C\_a + c\_{be,2}}}} \tag{27}$$

The resonant frequency shows good agreement with the theoretical considerations set out in (27).

Another effect is that the output impedance of the cascode cell increases significantly from 2 to 15 GHz under the influence of the 1.5 nH inductor. The initial values for *La* and *Ca* are then optimized under large-signal conditions using nonlinear simulations of the inductively

404 Ultra-Wideband Radio Technologies for Communications, Localization and Sensor Applications

HaLoS – Integrated RF-Hardware Components for Ultra-Wideband Localization and Sensing 405

peaked cascode circuit close to 1 dB compression point in order to obtain the maximum output power and efficiency. Accordingly, one single cell of a simple common emitter stage is used to synthesize the required ratio between the values of the inductor and capacitor. The test circuit is terminated with a 200 Ω resistor. The goal is to have equal deflections of the load lines both for the common emitter and the common base transistor. These results demonstrate that the proposed cascode configuration can obtain twice the output voltage swing compared to a single common emitter transistor at the same collector current so that

A demonstrator chip has been implemented utilizing the methodology described previously. Fig. 28 depicts a schematic diagram of the four-stage tapered collector-line traveling wave amplifier with capacitive coupling and power-matched cascode gain cells. Each gain cell consists of two 26.4 µm² standard purpose transistors with *BVceo* of 4 V and a peak *<sup>t</sup> f* value of 45 GHz, which are connected by a 1 nH inductor *La* . A single gain cell is depicted in Fig. 27b. The octagonal spiral inductor exhibits a Q-factor of 20 at 12 GHz.

**Figure 28.** Complete schematic representation of the implemented distributed amplifier structure.

The tapered collector line has been realized using staggered inductors *LCC CC* <sup>1234</sup> *LLL* together with shunt capacitances *C C ci ce* ; (1 3) *i* in order to achieve a coherent addition of the collector currents and a flat gain over the entire bandwidth. Biasing is implemented using three transistor current mirrors with ratio of 32:1 and a low dropout (LDO) voltage reference driven by a band-gap voltage source. A chip microphotograph of the complete circuit is shown in Fig. 29. The transistors are biased through the collector line by means of an external bias-tee. The bias point was selected at *VCC V* 5 and *VDD V* 2.6 . A power and ground grid facilitates a low impedance connection and - due to the low distance between the congruent metal grids - a large capacitor is shaped. The chip size of the

twice the output power can be achieved.

amplifier circuit is 2.1mm².

**Figure 25.** Small signal equivalent circuit of the modified cascode gain cell.

**Figure 26.** Voltage gain of different cascode cells with and without additional inductor 1.5 *La nH* and various capacitances *Ca* .

**Figure 27.** a) Small signal model of the modified cascode gain cell with inductive peaking and b) the schematic view.

peaked cascode circuit close to 1 dB compression point in order to obtain the maximum output power and efficiency. Accordingly, one single cell of a simple common emitter stage is used to synthesize the required ratio between the values of the inductor and capacitor. The test circuit is terminated with a 200 Ω resistor. The goal is to have equal deflections of the load lines both for the common emitter and the common base transistor. These results demonstrate that the proposed cascode configuration can obtain twice the output voltage swing compared to a single common emitter transistor at the same collector current so that twice the output power can be achieved.

404 Ultra-Wideband Radio Technologies for Communications, Localization and Sensor Applications

**Figure 25.** Small signal equivalent circuit of the modified cascode gain cell.

and various capacitances *Ca* .

schematic view.

**Figure 26.** Voltage gain of different cascode cells with and without additional inductor 1.5 *La nH*

**Figure 27.** a) Small signal model of the modified cascode gain cell with inductive peaking and b) the

A demonstrator chip has been implemented utilizing the methodology described previously. Fig. 28 depicts a schematic diagram of the four-stage tapered collector-line traveling wave amplifier with capacitive coupling and power-matched cascode gain cells. Each gain cell consists of two 26.4 µm² standard purpose transistors with *BVceo* of 4 V and a peak *<sup>t</sup> f* value of 45 GHz, which are connected by a 1 nH inductor *La* . A single gain cell is depicted in Fig. 27b. The octagonal spiral inductor exhibits a Q-factor of 20 at 12 GHz.

**Figure 28.** Complete schematic representation of the implemented distributed amplifier structure.

The tapered collector line has been realized using staggered inductors *LCC CC* <sup>1234</sup> *LLL* together with shunt capacitances *C C ci ce* ; (1 3) *i* in order to achieve a coherent addition of the collector currents and a flat gain over the entire bandwidth. Biasing is implemented using three transistor current mirrors with ratio of 32:1 and a low dropout (LDO) voltage reference driven by a band-gap voltage source. A chip microphotograph of the complete circuit is shown in Fig. 29. The transistors are biased through the collector line by means of an external bias-tee. The bias point was selected at *VCC V* 5 and *VDD V* 2.6 . A power and ground grid facilitates a low impedance connection and - due to the low distance between the congruent metal grids - a large capacitor is shaped. The chip size of the amplifier circuit is 2.1mm².

406 Ultra-Wideband Radio Technologies for Communications, Localization and Sensor Applications

HaLoS – Integrated RF-Hardware Components for Ultra-Wideband Localization and Sensing 407

**Figure 32.** Output power *Pout* and power added efficiency PAE at a center frequency of 7 GHz.

the maximum power-added efficiency is 22.1%.

**4.4. Differential broad band amplifier** 

[38].

The distributed power amplifier chip was tested via on-wafer probing. The measurements of the circuit were carried out using an Agilent N5242A PNA-X vector network analyzer. Fig. 30 shows the simulated and measured small signal gain S21 and input return loss S11. The traveling wave power amplifier exhibits a measured gain of 11 dB with a gain ripple of ±1 dB up to 12 GHz and a 3 dB bandwidth of 13 GHz. The simulated and measured output return loss <sup>22</sup> *S* and the reverse isolation <sup>12</sup> *S* are illustrated in Fig. 31. Both the input and output return loss are below -12 dB over the entire frequency range. The measured reverse isolation S12 remains below -35 dB. The circuit is unconditionally stable, also verified for large RF input signals. Fig. 32 shows the output power Pout and power-added efficiency PAE at a center frequency of 7 GHz. The 1 dB compression point is at 17.45 dBm with an associated power-added efficiency of 13.9%. The saturated output power *Psat* is 20 dBm and

Broadband variable gain amplifiers are key components for ultra-wideband radar applications and important building blocks to increase the dynamic range. Especially for Msequence based radar systems without upconversion, the lower frequency range, which contains most of the signal energy [36], has to be considered. Biomedical and ground penetrating radar systems necessitate a lower frequency boundary of less than 1 GHz [37],

Moreover, the broadband variable gain amplifier (VGA) should be fully differential. Great care has to be taken to avoid the distortion of the signal shape through gain ripple and group delay variation. In this section, the analysis, design and measurement results of a fully differential broadband VGA are presented. After some considerations about mismatching in broadband amplifiers have been made, the frequency behavior of cascaded emitter followers is investigated, and the implementation of a variable gain control is explained. Finally, the implementation of the broadband amplifier is presented, introducing the circuit architecture and presenting measurement results. The amplifier is

**Figure 29.** Microphotograph of the manufactured 2.1 mm² traveling wave power amplifier.

**Figure 30.** Simulated and measured small signal gain <sup>21</sup> *S* and input reflection coefficient <sup>11</sup> *S* .

**Figure 31.** Simulated and measured output reflection coefficient <sup>22</sup> *S* and isolation <sup>12</sup> *S* .

**Figure 32.** Output power *Pout* and power added efficiency PAE at a center frequency of 7 GHz.

The distributed power amplifier chip was tested via on-wafer probing. The measurements of the circuit were carried out using an Agilent N5242A PNA-X vector network analyzer. Fig. 30 shows the simulated and measured small signal gain S21 and input return loss S11. The traveling wave power amplifier exhibits a measured gain of 11 dB with a gain ripple of ±1 dB up to 12 GHz and a 3 dB bandwidth of 13 GHz. The simulated and measured output return loss <sup>22</sup> *S* and the reverse isolation <sup>12</sup> *S* are illustrated in Fig. 31. Both the input and output return loss are below -12 dB over the entire frequency range. The measured reverse isolation S12 remains below -35 dB. The circuit is unconditionally stable, also verified for large RF input signals. Fig. 32 shows the output power Pout and power-added efficiency PAE at a center frequency of 7 GHz. The 1 dB compression point is at 17.45 dBm with an associated power-added efficiency of 13.9%. The saturated output power *Psat* is 20 dBm and the maximum power-added efficiency is 22.1%.

### **4.4. Differential broad band amplifier**

406 Ultra-Wideband Radio Technologies for Communications, Localization and Sensor Applications

**Figure 29.** Microphotograph of the manufactured 2.1 mm² traveling wave power amplifier.

**Figure 30.** Simulated and measured small signal gain <sup>21</sup> *S* and input reflection coefficient <sup>11</sup> *S* .

**Figure 31.** Simulated and measured output reflection coefficient <sup>22</sup> *S* and isolation <sup>12</sup> *S* .

Broadband variable gain amplifiers are key components for ultra-wideband radar applications and important building blocks to increase the dynamic range. Especially for Msequence based radar systems without upconversion, the lower frequency range, which contains most of the signal energy [36], has to be considered. Biomedical and ground penetrating radar systems necessitate a lower frequency boundary of less than 1 GHz [37], [38].

Moreover, the broadband variable gain amplifier (VGA) should be fully differential. Great care has to be taken to avoid the distortion of the signal shape through gain ripple and group delay variation. In this section, the analysis, design and measurement results of a fully differential broadband VGA are presented. After some considerations about mismatching in broadband amplifiers have been made, the frequency behavior of cascaded emitter followers is investigated, and the implementation of a variable gain control is explained. Finally, the implementation of the broadband amplifier is presented, introducing the circuit architecture and presenting measurement results. The amplifier is

408 Ultra-Wideband Radio Technologies for Communications, Localization and Sensor Applications

HaLoS – Integrated RF-Hardware Components for Ultra-Wideband Localization and Sensing 409

 

 

*o o* <sup>22</sup> (28)

*o o* <sup>22</sup> (29)

where the imaginary parts, which are the reactances of the series resonator, cancel each

The core of the broadband amplifier is a signal summing VGA as illustrated in Fig. 33, where the gain is controlled by applying an analog dc voltage at *VC* . The amplifier gain can be set from 0 to maximum gain whereby it behaves like a cascode differential stage when the control voltage is set to 0 and all current flows through the load resistors *RL* . Furthermore, capacitive emitter degeneration is used to attain additional gain at high frequencies for a higher cut-off frequency. Tuning the values of *Re* and *Ce* , introduces trade-off between high gain, bandwidth and stability, because *Ce* influences the capacitive load of the cascaded emitter followers. Inductive peaking is carefully applied using small inductors *LC* in the collector branches in order to avoid high group delay [41]. In order to

*Re Z Re Z* <sup>11</sup> 

*Im Z Im Z* <sup>11</sup> 

achieve a high output swing, high currents in the differential amplifier are necessary.

**Figure 35.** Simulated impedances *Z*11 and *Z*22 illustrating the stability relations of the emitter

Fig. 36a illustrates the differential simulated and measured gain Sdd21 as well as the input and output return loss at 100 Ω differential source and load impedance. The measured differential gain is 11.5 dB with a gain flatness of ±1.5 dB. The 3 dB cut-off frequency is 30 GHz, which results in a gain-bandwidth product (GBP) of 113 GHz which is 1.5 times the

The circuit is implemented in the 0.25 µm IHP SGB25V value technology. A chip photograph of the broadband variable gain amplifier is depicted in Fig. 34. The circuit elements composing the amplifier core have been arranged symmetrically to maximize the even mode suppression. The mixed-mode S-Parameters are measured on-wafer using

other out:

150 µm GSGSG probes.

followers.

**Figure 33.** Simplified schematic diagram of the proposed broadband variable gain amplifier.

**Figure 34.** Microphotograph of the manufactured 0.75 mm² variable gain amplifier.

fully differential and based on a cascode configuration as depicted in Fig. 33. This is useful for high frequency circuit design, because this multi device configuration has small highfrequency feedback, achieved by the negligible Miller effect, and a large bandwidth. Driving the cascode stage with cascaded emitter-followers leads to an enhancement of bandwidth and provides dc level shifting [39].

The voltage gain of the cascaded emitter-followers has a frequency dependence that is similar to the frequency dependence of the transfer function of an RLC series resonance circuit [40]. This can be used to provide gain peaking at the desired frequency. The transfer function depends on the transistor parameters, the biasing current, the resistors, and the load. The main problem using emitter-followers to drive cascode stages is that the circuit might become unstable. This will be the case if the negative input resistance of the second emitter-follower stage becomes larger than the positive output resistance of the first stage at a certain frequency, which is shown in Fig. 35. The frequency is determined by the point where the imaginary parts, which are the reactances of the series resonator, cancel each other out:

408 Ultra-Wideband Radio Technologies for Communications, Localization and Sensor Applications

**Figure 33.** Simplified schematic diagram of the proposed broadband variable gain amplifier.

**Figure 34.** Microphotograph of the manufactured 0.75 mm² variable gain amplifier.

and provides dc level shifting [39].

fully differential and based on a cascode configuration as depicted in Fig. 33. This is useful for high frequency circuit design, because this multi device configuration has small highfrequency feedback, achieved by the negligible Miller effect, and a large bandwidth. Driving the cascode stage with cascaded emitter-followers leads to an enhancement of bandwidth

The voltage gain of the cascaded emitter-followers has a frequency dependence that is similar to the frequency dependence of the transfer function of an RLC series resonance circuit [40]. This can be used to provide gain peaking at the desired frequency. The transfer function depends on the transistor parameters, the biasing current, the resistors, and the load. The main problem using emitter-followers to drive cascode stages is that the circuit might become unstable. This will be the case if the negative input resistance of the second emitter-follower stage becomes larger than the positive output resistance of the first stage at a certain frequency, which is shown in Fig. 35. The frequency is determined by the point

$$\operatorname{Re}\left\{Z\_{11}\left(o\_o\right)\right\} = -\operatorname{Re}\left\{Z\_{22}\left(o\_o\right)\right\} \tag{28}$$

$$\operatorname{Im}\left\{Z\_{11}\left(\boldsymbol{\phi}\_{o}\right)\right\} = \operatorname{Im}\left\{Z\_{22}\left(\boldsymbol{\phi}\_{o}\right)\right\} \tag{29}$$

The core of the broadband amplifier is a signal summing VGA as illustrated in Fig. 33, where the gain is controlled by applying an analog dc voltage at *VC* . The amplifier gain can be set from 0 to maximum gain whereby it behaves like a cascode differential stage when the control voltage is set to 0 and all current flows through the load resistors *RL* . Furthermore, capacitive emitter degeneration is used to attain additional gain at high frequencies for a higher cut-off frequency. Tuning the values of *Re* and *Ce* , introduces trade-off between high gain, bandwidth and stability, because *Ce* influences the capacitive load of the cascaded emitter followers. Inductive peaking is carefully applied using small inductors *LC* in the collector branches in order to avoid high group delay [41]. In order to achieve a high output swing, high currents in the differential amplifier are necessary.

The circuit is implemented in the 0.25 µm IHP SGB25V value technology. A chip photograph of the broadband variable gain amplifier is depicted in Fig. 34. The circuit elements composing the amplifier core have been arranged symmetrically to maximize the even mode suppression. The mixed-mode S-Parameters are measured on-wafer using 150 µm GSGSG probes.

**Figure 35.** Simulated impedances *Z*11 and *Z*22 illustrating the stability relations of the emitter followers.

Fig. 36a illustrates the differential simulated and measured gain Sdd21 as well as the input and output return loss at 100 Ω differential source and load impedance. The measured differential gain is 11.5 dB with a gain flatness of ±1.5 dB. The 3 dB cut-off frequency is 30 GHz, which results in a gain-bandwidth product (GBP) of 113 GHz which is 1.5 times the

*<sup>t</sup> f* of the transistor. The corresponding measured and simulated group delay is shown in Fig. 36b. The measured group delay variation is 35 ps, which is higher than that in the simulation and also induced by the stronger resonance behavior.

HaLoS – Integrated RF-Hardware Components for Ultra-Wideband Localization and Sensing 411

To overcome this limitation, a more complicated method of data capture based on "stroboscopic feedback loop" can be used. This method utilizes a feedback loop to relax accuracy requirements of the ADC (see [2] and chapter 6.2.3). The digital output of the data capturing device is represented by two summands: the value of the first summand is measured by the ADC; the value of the second summand is calculated based on its previous state and on the first one. The ratio between predicted and measured summands, i.e. between the resolution of the ADC and DAC can be calculated from the conversion

The block diagram of the data capturing device with feedback is depicted in Fig. 38. It consists of 3 logical parts, highlighted in colors in Fig. 38: Signal Processing, ADC and DAC, and LNA with subtraction amplifier. Although the subtraction amplifier belongs to the data capturing block, it has been integrated into LNA and moved to the receiver part of the

 A capturing block digitizes a difference (residue) between the received and predicted values. This function is performed by a high-speed low-resolution analog-to-digital

A digital predictor evaluates the data from the ADC and makes a prognosis about the

In analog domain, the predicted value is subtracted from the received signal with a

The fastest type of the A/D converters is a full flash ADC. A block diagram of a typical full flash converter is shown in Fig. 39. It consists of a reference network, a bank of comparators, correction and encoding logic and test buffers. The challenges of the implementation of the ADC are usually related to the analog part of the converter, namely to the reference network and to the bank of the comparators. It is possible to implement the high-speed comparator in the selected technology which will satisfy all requirements, but the reference network is a

The predicted value is converted into an analog form with a high-speed DAC.

efficiency of the both converters [42].

value to be expected next.

subtraction amplifier.

The data capturing device works as following:

**Figure 38.** Block diagram of the data capturing device

*5.2.1. High-speed analog-to-digital converter* 

bottle-neck of the converter.

**5.2. High-speed 4-bit analog-to-digital converter** 

sensor.

converter.

**Figure 36.** a) Simulated and measured mixed mode S-parameters. b) Simulated and measured group delay.

As depicted in Fig. 37, the amplifier gain can be adjusted between 0 and 11.5 dB. The large signal behavior is measured on-wafer. An output 1 dB compression point of 12 dBm has been measured up to 20 GHz.

**Figure 37.** Measured gain by sweeping the control voltage *Vc* from 0 to 1.25 V
