**8. Hardware requirements of IA systems**

High throughput wireless communication systems including LTE, ECMA-368 (WiMedia) and IEEE 802.11ac are built around sophisticated digital signal processing algorithms. Among the research goals for future communication standards are higher spectral efficiency, higher

12 Will-be-set-by-IN-TECH

Before the above mentioned real world UWB antennas are used, the IA algorithm is tested with a narrowband multimode antenna with orthogonal channels. The narrowband antenna system is designed for use at 5.9 GHz to 6.15 GHz, consisting of four monopoles built on a finite ground plane as shown in Fig. 8(a). This antenna system is capable of radiating four different orthogonal modes based on the amplitude and phase of the excitation signals to the

Two modes as shown in Fig. 8(c) and (d) were chosen and the antenna system was simulated with a ray-tracing software within the scenario shown in Fig. 8(b). The simulation has been performed for 1000 different transmit and receive nodes locations. Simulation results shown in Fig. 9 illustrates that the overall BER system performance has been significantly improved with the multimode antenna system compared to the half wave dipoles (HWD). That is due

(a) Multimode narrowband antennas (b) Ray-tracing scenario for Interference

(c) Orthogonal radiation patterns of the multimode antennas (left) mode 1,

**Figure 8.** Multimode narrowband antennas for preliminary Interference Alignment algorithm analysis

High throughput wireless communication systems including LTE, ECMA-368 (WiMedia) and IEEE 802.11ac are built around sophisticated digital signal processing algorithms. Among the research goals for future communication standards are higher spectral efficiency, higher

multimode antennas

Alignment test using the narrowband

**7.1. Orthogonal channels multimode antenna selection criteria**

antenna ports. More details about this antenna can be found in [15].

to the additional path diversity to the communication system.

(right) mode 2

**8. Hardware requirements of IA systems**

**Figure 9.** Comparison of the average BER vs. *Eb*/*No* of the IA system by applying multimode antenna systems and comparing to HWDs.

energy efficiencies towards the Shannon limit and increased data rates. Naturally, these benefits come at the price of higher computational complexity. The demand for flexible realtime hardware platforms capable of delivering the required huge number of operations per second at a severely limited power and silicon area budget has led to the development of specialized hardware platforms for software defined radio (SDR) applications. Techniques from FPGA-based ASIC verification and rapid prototyping are combined in this project for the design space exploration of highly optimized hardware architectures.

In a typical implementation scenario for complex designs, high level reference models are used. The choice of optimization-blocks is often based on profiling results, with those blocks contributing significantly to the overall resource requirements being chosen for optimization. This leads to a hybrid design consisting of a mixture of high level blocks and highly optimized blocks, running on hardware ranging from general purpose processors (GPP), application specific instruction set processors, FPGA-based rapid prototyping systems and dedicated hardware accelerators. The presented design space exploration framework reflects this structure and allows the designer to freely move processing blocks between the different layers of optimization.

The design space exploration framework created within this project is presented in Section 8.2. A hardware implementation case study of a closed-form 3-user IA algorithm has been selected for presentation in Section 8.3. Cost functions for an iterative IA algorithm are given in Section 8.4.
