**2.1. Multi-conductor interconnects**

2 Will-be-set-by-IN-TECH

Thereby, an analytical field-theoretical modeling of multi-conductor interconnects is needed. Moreover, modifications to standard signal processing techniques which make them suitable for medium-low resolution quantization are developed and analyzed, and their performance

As a promising alternative solution, wireless Ultrawideband (UWB) enables high speed communication at short distances. In fact, it is anticipated that even higher performance is achievable in chip-to-chip and on-chip communication, when multi-conductor interconnects are replaced by wireless ultra-wideband multi-antenna interconnects. Hereby, the signal pulses do not necessarily increasingly disperse as they travel along their way to the receiving end of the interconnect. The propagating nature of the wireless interconnect, the extreme high available bandwidth and the very short distances can offer a much more attractive channel for chip-to-chip and on-chip communications. In addition, applying multiple antennas at the transmitter side as well as the receiver side can drastically improve the data rate and the reliability of UWB systems at the cost of certain computational complexity. This chapter provides theoretical and empirical foundations for the application of ultra-wideband multi-antenna wireless interconnects for chip-to-chip communication. Appropriate structures for integrated ultra-wideband antennas shall be developed, their properties theoretically analyzed and verified against measurements performed on manufactured prototypes. Qualified coding and signal processing techniques, which aim at efficient use of available resources of bandwidth, power, and chip area shall be developed. Since Analog-to-Digital Converters (ADCs) are considered critical components for the UWB, main focus is hereby given to low resolution signal quantization and processing. Therefore, the analysis and the design of UWB systems with low resolution signal quantization (less than 4 bits) is a vital part

of this chapter, where optimized receive and transmit strategies are obtained.

On the other hand, detailed cost-models for the digital hardware architecture, which are based on signal flow charts and VLSI implementations of dedicated functional blocks shall be developed, which allow for an informative analysis of elementary trade-offs between computational speed, required chip area, and power consumption. In fact, quantitative optimization in terms of silicon area (manufacturing costs) and even more important in terms of energy dissipation (usage costs) is mandatory already in the standardization and conception phase of digital systems to be highly integrated as System-on-Chips (SoC). This is especially true for digital communication systems where e.g. in the optimization of channel coding traditionally only the transmission power has been considered. In general this leads to highly complex and energy intensive receivers. Actually a proper optimization of such systems requires a joint optimization of the transmitter and receiver cost features, e.g. the minimization of the total energy per transmitted bit. For such a quantitative optimization quite accurate cost models for the components of the transmitter and receiver are required. Instead, if any, only oversimplified cost models are applied today. While quite accurate cost models are available for many communication system components there is a lack of such models for channel decoders like Viterbi, Turbo, and Low-Density-Parity-Check (LDPC) decoders. Out of these, especially the derivation of sufficiently accurate cost models for LDPC decoders is challenging: The realization of the extensive internal exchange of messages between the so-called bit and check nodes in such a decoder results in non-linear dependencies between decoder features and code parameters. For example in high-throughput decoders the data exchange is performed via a complex dedicated interconnect structure. Its realization frequently requires an artificial expansion

is studied.

With the increase of the on-chip data transfer rate to several 10 Gbit/s the spatio-temporal intersymbol interference (auto-interference) within the multiwired bus systems becomes a limiting factor for the circuit performance. Due to the limited available space for the bus systems shielding between the wires of the bus should be omitted. This allows for larger wire cross sections and thereby to reduce the signal distortion. An appropriate signal coding and signal processing will compensate for the effects of the coupling between the wires.

The wiring inside high speed MOS circuits exhibits sub-micron cross-sectional dimensions and conductor width and conductor thickness are of similar size. Within the signal frequency band the cross sectional dimensions are in the order of the skin effect penetration depth. The signal transmission properties of the bus system is detrained by the capacitances per unit of length and the resistance per unit of length.

The TEM modes of a lossless multiconductor transmission line with equidistant conductors of equal cross section and filled with homogenous isotropic dielectric material used for bus have been discussed in [18]. Figure 1 a shows the cross-sectional drawing of the bus. The quasi-electrostatic parameters of the bus embedded in the substrate between two ground planes have been computed. The bus capacitance per unit of length – matrix, describing capacitances with respect to ground and mutual capacitances, has been derived from the conductor geometry using an analytical technique based on even-odd mode analysis [10, 18]. The analytical technique is based on the inversion of the Schwarz-Christoffel conformal mapping [5, pp. 191–201]. The advantages of the proposed method are its accuracy, the lack of geometrical limitations and the algorithm efficiency. The results for the ground and coupling

4 Will-be-set-by-IN-TECH 78 Ultra-Wideband Radio Technologies for Communications, Localization and Sensor Applications Chip-to-Chip and On-Chip Communications <sup>5</sup>

a) b)

<sup>100</sup> Coupling voltage vs. Frequency

<sup>104</sup> <sup>106</sup> <sup>108</sup> <sup>1010</sup> 10−8

Frequency, Hz

a) b)

<sup>0</sup> 0.02 0.04 0.06 0.08 0.1 <sup>0</sup>

Analytical solution MoM Simulation

0 200 400 600 800

<sup>0</sup> <sup>1</sup> <sup>3</sup> <sup>4</sup> <sup>0</sup>

2

Uncoded

x 2.12

Time, ps

Coded

x 1/24

Pulse Shape at Line End

Excitation Pulse Analytical Solution SPICE Data

Chip-to-Chip and On-Chip Communications 79

−0.2 0 0.2 0.4 0.6 0.8 1 1.2

0.1

0.2

Available Rate, x

Bus Clock Frequency, *f*c x *RC*<sup>s</sup> Dissipated Power, *P*diss x *R/V*dd2

**Figure 4.** a) Maximum permissible noise-voltage at the receiver of a four-conductor bus as function of the bus clock frequency, b) achievable information rates of coded and uncoded transmission as function

The space-time intersymbol interference present in on-chip interconnection buses is a limiting factor of the performance of digital integrated circuits. This effect has greater influence as the transfer data rate increases and the circuit dimensions decrease. In order to be able to develop coding techniques for reducing the detrimental effects of intersymbol interference, an efficient and precise method for calculating the impulse response of the interconnect is required [31]. In [7] a quasi-analytical method was applied for computing the impulse response of a digital interconnection bus. The fundamental performance limits of bus systems due to information theory have been analyzed. Figure 3 shows the maximum permissible noise-voltage *V*Noise at the receiver of a four-conductor bus as function of the bus clock frequency *f*c and the achievable information rates of coded and uncoded transmission as function of the dissipated power *P*diss. The clock frequency for the coded transmission is set to 0.11/(*RC*s), which is above the cutoff of the uncoded bus and proves to work well with the coded system. Here *V*dd, *R* and *C*<sup>s</sup> are the magnitude of the signal voltage at the input, the total resistance, and the total average substrate capacitance, respectively. Here, *C*<sup>c</sup> = 6*C*<sup>s</sup> is assumed, but similar

 *RC*s/bit

0.3

0.4

0.5

Line Voltage, V

**Figure 3.** a) Frequency response of the crosstalk voltage at the end of the line, b) pulse response at the

10−6

end of the line [18].

0.02 0.04 0.06 0.08 0.1 0.12 0.14

of the dissipated power [7].

results are obtained for other ratios.

Available Noise Voltage,

*V*Noise/*V*dd

10−4

Voltage, V

10−2

**Figure 1.** a) A cross section of three-wire digital bus with a coupling and a ground capacitance [10] and b) equivalent lumped element circuit [8].

capacitances per unit length for the multi conductor transmission line, filled in with silicon, are presented in Fig. 2. Since the capacitance depends only on the ratio of the line dimensions, all geometrical data are normalized to the distance *h* between the ground planes.

**Figure 2.** a) Ground capacitance vs. geometry for digital transmission line, filled in with Si, *d*/*h* = 0.125, b) Coupling capacitance vs. geometry for digital transmission line, filled in with Si, *a*/*h* = 0.25 [10].

The obtained results have been used to compute the transmission line parameters of the bus [7, 8, 10, 18]. The bus model is based on multiconductor TEM transmission line theory [5, pp. 356–363]. In case of the TEM transmission line the inductance per unit of length matrix follows directly from the capacitance per unit of length matrix and the material [18]. in case of small conductor cross sections the resistance per unit of length becomes such high that the inductance per unit of length matrix can be neglected in comparison with the resistantce per unit of length. In this case the impedance per unit of length matrix becomes diagonal [8]. The ohmic losses in the conductors are modeled by resistance per unit length *R* . These parameters determine the lumped element equivalent circuit of the bus shown in Fig. 1 b.

The crosstalk between the conductors of the bus has been investigated in [18]. Figure 3 a shows the response of the crosstalk voltage at the end of the line. The results, obtained by solving the transmission line equations have been compared with numerical Method of Moment (MoM) full-wave simulations. The analytic model exhibits good accuracy up to frequencies beyond 10 GHz. Figure 3 b shows the pulse distortion at the end of the transmission line. Analytical data computed with the transmission line model have been compared with numerical data obtained from SPICE simulation.

#### 78 Ultra-Wideband Radio Technologies for Communications, Localization and Sensor Applications Chip-to-Chip and On-Chip Communications <sup>5</sup> Chip-to-Chip and On-Chip Communications 79

4 Will-be-set-by-IN-TECH

*V*2

*V*1

*V*n

**Figure 1.** a) A cross section of three-wire digital bus with a coupling and a ground capacitance [10] and

capacitances per unit length for the multi conductor transmission line, filled in with silicon, are presented in Fig. 2. Since the capacitance depends only on the ratio of the line dimensions,

**Figure 2.** a) Ground capacitance vs. geometry for digital transmission line, filled in with Si, *d*/*h* = 0.125, b) Coupling capacitance vs. geometry for digital transmission line, filled in with Si, *a*/*h* = 0.25 [10].

The obtained results have been used to compute the transmission line parameters of the bus [7, 8, 10, 18]. The bus model is based on multiconductor TEM transmission line theory [5, pp. 356–363]. In case of the TEM transmission line the inductance per unit of length matrix follows directly from the capacitance per unit of length matrix and the material [18]. in case of small conductor cross sections the resistance per unit of length becomes such high that the inductance per unit of length matrix can be neglected in comparison with the resistantce per unit of length. In this case the impedance per unit of length matrix becomes diagonal [8]. The

The crosstalk between the conductors of the bus has been investigated in [18]. Figure 3 a shows the response of the crosstalk voltage at the end of the line. The results, obtained by solving the transmission line equations have been compared with numerical Method of Moment (MoM) full-wave simulations. The analytic model exhibits good accuracy up to frequencies beyond 10 GHz. Figure 3 b shows the pulse distortion at the end of the transmission line. Analytical data computed with the transmission line model have been compared with numerical data

ohmic losses in the conductors are modeled by resistance per unit length *R*

determine the lumped element equivalent circuit of the bus shown in Fig. 1 b.

all geometrical data are normalized to the distance *h* between the ground planes.

*Z'*

*Z'*

*Z'*

*C C*<sup>1</sup>

*C C*<sup>1</sup>

b/h = 0.4 b/h = 0.5 b/h = 0.6

. These parameters

*Z'*

0.1 0.2 0.3 0.4 0.5 0.8

d/h

Coupling Capacitance vs. Conductor Spacing

*C*

*Z'*

*C C*<sup>1</sup>

*C C*<sup>1</sup>

*Z'*

1

C'23 pF/cm

*C*

a) b)

2

*h b* 1 3

b) equivalent lumped element circuit [8].

b/h = 0.4 b/h = 0.5 b/h = 0.6

obtained from SPICE simulation.

Symmetry Plane

*a*

C′22 pF/cm

*d*

Ground Plane

Conductor

*C'g*

a) b)

Ground Capacitance vs. Conductor Width

0.1 0.2 0.3 0.4 0.5 <sup>1</sup>

a/h

*C'c*

**Figure 3.** a) Frequency response of the crosstalk voltage at the end of the line, b) pulse response at the end of the line [18].

**Figure 4.** a) Maximum permissible noise-voltage at the receiver of a four-conductor bus as function of the bus clock frequency, b) achievable information rates of coded and uncoded transmission as function of the dissipated power [7].

The space-time intersymbol interference present in on-chip interconnection buses is a limiting factor of the performance of digital integrated circuits. This effect has greater influence as the transfer data rate increases and the circuit dimensions decrease. In order to be able to develop coding techniques for reducing the detrimental effects of intersymbol interference, an efficient and precise method for calculating the impulse response of the interconnect is required [31]. In [7] a quasi-analytical method was applied for computing the impulse response of a digital interconnection bus. The fundamental performance limits of bus systems due to information theory have been analyzed. Figure 3 shows the maximum permissible noise-voltage *V*Noise at the receiver of a four-conductor bus as function of the bus clock frequency *f*c and the achievable information rates of coded and uncoded transmission as function of the dissipated power *P*diss. The clock frequency for the coded transmission is set to 0.11/(*RC*s), which is above the cutoff of the uncoded bus and proves to work well with the coded system. Here *V*dd, *R* and *C*<sup>s</sup> are the magnitude of the signal voltage at the input, the total resistance, and the total average substrate capacitance, respectively. Here, *C*<sup>c</sup> = 6*C*<sup>s</sup> is assumed, but similar results are obtained for other ratios.

6 Will-be-set-by-IN-TECH 80 Ultra-Wideband Radio Technologies for Communications, Localization and Sensor Applications Chip-to-Chip and On-Chip Communications <sup>7</sup>

### *Conclusion*

The developed methods allow to compute the impulse response of the multi-conductor bus, and – building on this ground – to compute information theoretic measures, like mutual information. Those measures allow to quantify the possible gains in performance that can be achieved by employing suitable coding schemes to the multi-conductor interconnection bus. The obtained results reveal a huge potential of coded transmission both in terms of increasing the data rate and in decreasing the dissipated power.

The utilization of the electronic circuit ground planes as radiating elements for the integrated antennas allows for optimal usage of chip area, as the antennas share the chip area with the circuits. It has to be taken care that the interference between the antenna field and the field propagating in the circuit structures stays within tolerable limits. Consider the structure represented schematically in Fig. 5 b. The structure contains two antenna patches 1 and 2. Both antenna patches serve as the ground planes of circuits. These circuits contain line drivers *T*<sup>1</sup> ... *T*<sup>4</sup> driving over symmetrical interconnection lines the line receivers *R*<sup>1</sup> ... *R*4. Furthermore there is a driver *TA*, the output of which is connected to both patches, however only one conductor bridges the gap between the patches. The currents *i*<sup>1</sup> ... *i*<sup>4</sup> all are flowing back over the symmetric lines. The sum of the currents *i*<sup>1</sup> ... *i*<sup>4</sup> flowing in both directions through the transmission line modes vanishes and is not exciting the antenna. Different from this, the current *iA* excites an antenna radiation mode. The circuit for this current is closed via the displacement current in the near-field of the antenna. By exciting the interconnection structures in transmission line modes and the antennas in antenna modes the interference between circuit and antennas can be minimized. We need not to use differential lines between the patches. In general a interconnection structure consisting of *N* conductors can guide up to

Chip-to-Chip and On-Chip Communications 81

*b* = 1.5 μm

*c* = 8 μm

*d* = 3 μm

*e* = 650 μm

*N* − 1 quasi-TEM transmission line modes and one antenna mode. a) b)

*a* = 2 mm

**Figure 6.** Cross-sectional view of integrated on-chip antenna, using the ground planes as antenna

Figure 6 a shows a cross-sectional view of the integrated on-chip antenna, using the ground planes in layer *b* on top of the integrated circuit as the antenna electrodes. Layer *c* with a total thickenss of 8 *μ*m contains the active and passive circuit elements and the interconnect wiring. The low-resistivity layer *d* provides isolation of the circuit elements. The thick substrate layer *e* is of high resistivity. Figure 6 b shows a photograph of the fabricated open-circuit slot antenna with CMOS circuits under the antenna electrode [15]. Figure 7 a shows the simulated current distribution of a two-patch V-band antenna [14, 15]. The current distribution in both patches mainly is concentrated in the neighborhood of the slots. The antenna behaves as an open-circuited slot antenna. The guided wavelength is in the range of a millimeter. The

Antenna Electrode 2

RF Generator

t

High Resistivity Substrate

Low Resistivity Substrate Low Resistivity Substrate

*a* = 2 mm

Antenna Electrode 1

electrodes [11, 14].

### **2.2. On-chip antennas**

An interesting future possibility for handling Gbit/s data streams on chip and from chip to chip will be wireless intra-chip and inter-chip communication. This section describes investigations of integrated on-chip antennas for broad-band intra-chip and inter-chip communications. At frequencies of 60 GHz and beyond antennas can be made sufficiently small to be integrated on monolithic circuits [1, 19]. However, there are still problems when integrating millimeterwave antennas on CMOS circuits. The integration of millimeterwave antennas on silicon requires a high resistivity substrate in order to achieve low losses, whereas for CMOS circuits the substrate resistivity has to be low in order to provide isolation of the circuit elements. Furthermore, chip surface is a cost factor and should not be wasted for antennas.

**Figure 5.** a) Schematic drawing of a chip with an integrated antenna, b) Differential lines, connecting the digital circuits under the separate antenna patches.

An integrated on-chip antenna for chip-to-chip wireless communication, based on the usage of the digital circuits' ground planes as radiating elements was presented in [12–17]. Figure 5 a shows schematically the realization of this principle in slicon technology. The integrated circuit is fabricated on a high resistivity silicon substrate (≥ 1kΩ·cm) with a thickness in the order of of 650 *μ*m. The substrate is backed by a metallic layer. On top of the substrate a low-resistivity layer (≈ 5Ω·cm) of few micrometer thickness is grown. A homogeneous low-resistivity layer of 3 *μ*m to 5 *μ*m thickness is followed by a top with embedded CMOS circuitry and the interconnects. A low resistivity top layer is required for the circuit insulation. The electromagnetic field of the circuits is mainly confined in this top layer. The antenna field is spreading over the whole thickness of the substrate. Due to the high resistivity of the substrate the antenna losses are low. Since only a small fraction of the antenna near-field energy is stored in the low-resistivity layer, the coupling between the antenna near-field and the circuit field is weak. Furthermore, the interference between the CMOS circuits and the antenna field can be reduced when the main part of the circuit is operating in a frequency band distinct from the frequency band used for the wireless transmission.

The utilization of the electronic circuit ground planes as radiating elements for the integrated antennas allows for optimal usage of chip area, as the antennas share the chip area with the circuits. It has to be taken care that the interference between the antenna field and the field propagating in the circuit structures stays within tolerable limits. Consider the structure represented schematically in Fig. 5 b. The structure contains two antenna patches 1 and 2. Both antenna patches serve as the ground planes of circuits. These circuits contain line drivers *T*<sup>1</sup> ... *T*<sup>4</sup> driving over symmetrical interconnection lines the line receivers *R*<sup>1</sup> ... *R*4. Furthermore there is a driver *TA*, the output of which is connected to both patches, however only one conductor bridges the gap between the patches. The currents *i*<sup>1</sup> ... *i*<sup>4</sup> all are flowing back over the symmetric lines. The sum of the currents *i*<sup>1</sup> ... *i*<sup>4</sup> flowing in both directions through the transmission line modes vanishes and is not exciting the antenna. Different from this, the current *iA* excites an antenna radiation mode. The circuit for this current is closed via the displacement current in the near-field of the antenna. By exciting the interconnection structures in transmission line modes and the antennas in antenna modes the interference between circuit and antennas can be minimized. We need not to use differential lines between the patches. In general a interconnection structure consisting of *N* conductors can guide up to *N* − 1 quasi-TEM transmission line modes and one antenna mode.

6 Will-be-set-by-IN-TECH

The developed methods allow to compute the impulse response of the multi-conductor bus, and – building on this ground – to compute information theoretic measures, like mutual information. Those measures allow to quantify the possible gains in performance that can be achieved by employing suitable coding schemes to the multi-conductor interconnection bus. The obtained results reveal a huge potential of coded transmission both in terms of increasing

An interesting future possibility for handling Gbit/s data streams on chip and from chip to chip will be wireless intra-chip and inter-chip communication. This section describes investigations of integrated on-chip antennas for broad-band intra-chip and inter-chip communications. At frequencies of 60 GHz and beyond antennas can be made sufficiently small to be integrated on monolithic circuits [1, 19]. However, there are still problems when integrating millimeterwave antennas on CMOS circuits. The integration of millimeterwave antennas on silicon requires a high resistivity substrate in order to achieve low losses, whereas for CMOS circuits the substrate resistivity has to be low in order to provide isolation of the circuit elements. Furthermore, chip surface is a cost factor and should not be wasted for

> Interconnects and Active Devices

1.5 μm

band distinct from the frequency band used for the wireless transmission.

650 μm 10 μm

**Figure 5.** a) Schematic drawing of a chip with an integrated antenna, b) Differential lines, connecting the

An integrated on-chip antenna for chip-to-chip wireless communication, based on the usage of the digital circuits' ground planes as radiating elements was presented in [12–17]. Figure 5 a shows schematically the realization of this principle in slicon technology. The integrated circuit is fabricated on a high resistivity silicon substrate (≥ 1kΩ·cm) with a thickness in the order of of 650 *μ*m. The substrate is backed by a metallic layer. On top of the substrate a low-resistivity layer (≈ 5Ω·cm) of few micrometer thickness is grown. A homogeneous low-resistivity layer of 3 *μ*m to 5 *μ*m thickness is followed by a top with embedded CMOS circuitry and the interconnects. A low resistivity top layer is required for the circuit insulation. The electromagnetic field of the circuits is mainly confined in this top layer. The antenna field is spreading over the whole thickness of the substrate. Due to the high resistivity of the substrate the antenna losses are low. Since only a small fraction of the antenna near-field energy is stored in the low-resistivity layer, the coupling between the antenna near-field and the circuit field is weak. Furthermore, the interference between the CMOS circuits and the antenna field can be reduced when the main part of the circuit is operating in a frequency

T1 T2 R3 R4 TA

Patch 1

R1 R2 T3 T4

*i*A

Patch 2

*i*1 *i*2 *i*3 *i*4

the data rate and in decreasing the dissipated power.

a) b)

Top Metallization Layers

digital circuits under the separate antenna patches.

*Conclusion*

antennas.

**2.2. On-chip antennas**

High Resistivity Silicon Substrate Ground Metallization

**Figure 6.** Cross-sectional view of integrated on-chip antenna, using the ground planes as antenna electrodes [11, 14].

Figure 6 a shows a cross-sectional view of the integrated on-chip antenna, using the ground planes in layer *b* on top of the integrated circuit as the antenna electrodes. Layer *c* with a total thickenss of 8 *μ*m contains the active and passive circuit elements and the interconnect wiring. The low-resistivity layer *d* provides isolation of the circuit elements. The thick substrate layer *e* is of high resistivity. Figure 6 b shows a photograph of the fabricated open-circuit slot antenna with CMOS circuits under the antenna electrode [15]. Figure 7 a shows the simulated current distribution of a two-patch V-band antenna [14, 15]. The current distribution in both patches mainly is concentrated in the neighborhood of the slots. The antenna behaves as an open-circuited slot antenna. The guided wavelength is in the range of a millimeter. The

8 Will-be-set-by-IN-TECH 82 Ultra-Wideband Radio Technologies for Communications, Localization and Sensor Applications Chip-to-Chip and On-Chip Communications <sup>9</sup>

open-circuited slot with a length of about one millimeter is a transmission line resonator with a resonance frequency in the V-band. The standing wave in the slot excites the radiation field.

antenna model is presented where the antenna near-field is modeled by a reactive two-port and the real resistor *Rr* terminating the two-port models the energy dissipation in the far-field.

> 0.2 0.4 0.6 0.8


**Figure 9.** Comparison of the numerical data of (a) |*Z*11| and (b) |*Z*12| obtained from the full-wave simulation of the wireless transmission link with the data computed from lumped element model

Figure 9 shows the comparison of the numerical data of the magnitudes of the two-port impedance parameters |*Z*11| and |*Z*12| obtained from the full-wave simulation of the wireless transmission link with the data computed from lumped element model. For details of the model see [3]. The numerical full-wave simulations have been performed using CST software. An accurate model of *Z*<sup>11</sup> is achieved for the frequency band from 65 GHz to 69 GHz based on four pairs of poles and two single poles at zero and infinity. The frequency range may be

We have investigated methods for an area-efficient design of on-chip integrated antennas, based on the utilization of the same metallization structures both as a CMOS circuit ground plane and as antenna electrodes. An experimental setup has been designed for validating the computed antenna parameters, as well as the interference between the CMOS interconnects and the antenna. Equivalent circuits have been established to model integrated antennas and

Both multiconductor interconnects and wireless multiantenna interconnects can be interpreted as discrete-time, multi-input-multi-output (MIMO) systems. Such systems have been subject to extensive study in the recent past in the field of digital, especially mobile communications. Starting from the analysis of their promising information theoretic capabilities (e.g., [41]), a large amount of signal processing and coding techniques have been

The common approach to handle spatio-temporal interference in MIMO systems, involves either linear or non-linear transmit and receive signal processing, which job is to transform the original MIMO system into a »virtual« MIMO system, where large amounts of spatio-temporal interference have been removed [48]. All state of the art MIMO signal processing techniques have in common that they assume that either the receiver, the transmitter, or both, have access to, or can generate signals with arbitrary precision. This implies, in practice, the existence of ADC and DAC components with a large enough resolution such that the non-linear effects of signal quantization can be neglected. However, in multiconductor, or wireless

**3. Communication theoretical limits, coding and signal processing**

developed, that aim at achieving the information theoretic bounds (e.g., [42–44, 46]).

<sup>64</sup> <sup>65</sup> <sup>66</sup> <sup>67</sup> <sup>68</sup> <sup>69</sup> <sup>70</sup> <sup>0</sup>

Chip-to-Chip and On-Chip Communications 83

numerical data approximation

frequency / GHz

a) b)

numerical data approximation

<sup>64</sup> <sup>65</sup> <sup>66</sup> <sup>67</sup> <sup>68</sup> <sup>69</sup> <sup>70</sup> <sup>0</sup>

frequency / GHz

extended by increasing the number of poles.

wireless intra-chip and inter-chip transmission links.


*Conclusion*

**Figure 7.** (a) Top view and current distribution of a two-patch dipole antenna, operating at 66 GHz, (b) Measured return loss of the on-chip open slot antenna [14, 15].

**Figure 8.** Antenna orientation with a) collinear and b) parallel slots, c) Measured insertion loss of a wireless chip-to-chip link depending [14, 15].

The antennas have been measured on-wafer and diced. The measured return loss of the diced slot antenna from Fig. 7 a is compared with the simulation results in Fig. 7 b. The insertion loss of a transmission link has been measured for the two antenna alignments shown in Figs. 8 a and b, where the antennas were positioned in each other radiation minima and maxima. Figure 8 s c shows the measured insertion loss of a wireless links formed by two antennas. When the antennas are oriented such that their slots are collinear, they are in each other's direction of minimum radiation. When they are oriented such that their slots are parallel, they are in each other's direction of maximum radiation. Both cases were investigated for on-wafer and for diced chips. The chip-to-chip links with both antennas on different chips exhibit higher insertion loss. The lower insertion loss of links between antennas on the same chip is due to the contribution of surface waves. The worst-case transmission link (gain-chip-to-chip link) in the direction of minimum radiation shows an insertion loss of -47dB, which is sufficient for high-rate data links.

Lumped element circuit models can provide a compact description of wireless transmission links [20–22, 25]. Distributed circuits can be modeled also in a broad frequency band with arbitrary accuracy using lumped element network models. A general way to establish network models is based on modal analysis and similar techniques [2–5]. In the case of wireless transmission links, high insertion losses have to be considered. Therefore methods for the synthesis of lossy multiports have to be applied. In [23, 24] a lumped-element two-port antenna model is presented where the antenna near-field is modeled by a reactive two-port and the real resistor *Rr* terminating the two-port models the energy dissipation in the far-field.

**Figure 9.** Comparison of the numerical data of (a) |*Z*11| and (b) |*Z*12| obtained from the full-wave simulation of the wireless transmission link with the data computed from lumped element model

Figure 9 shows the comparison of the numerical data of the magnitudes of the two-port impedance parameters |*Z*11| and |*Z*12| obtained from the full-wave simulation of the wireless transmission link with the data computed from lumped element model. For details of the model see [3]. The numerical full-wave simulations have been performed using CST software. An accurate model of *Z*<sup>11</sup> is achieved for the frequency band from 65 GHz to 69 GHz based on four pairs of poles and two single poles at zero and infinity. The frequency range may be extended by increasing the number of poles.

### *Conclusion*

8 Will-be-set-by-IN-TECH

open-circuited slot with a length of about one millimeter is a transmission line resonator with a resonance frequency in the V-band. The standing wave in the slot excites the radiation field.

**Figure 7.** (a) Top view and current distribution of a two-patch dipole antenna, operating at 66 GHz, (b)

−50 −45 −40 −35 −30 −25 −20 −15 −10

The antennas have been measured on-wafer and diced. The measured return loss of the diced slot antenna from Fig. 7 a is compared with the simulation results in Fig. 7 b. The insertion loss of a transmission link has been measured for the two antenna alignments shown in Figs. 8 a and b, where the antennas were positioned in each other radiation minima and maxima. Figure 8 s c shows the measured insertion loss of a wireless links formed by two antennas. When the antennas are oriented such that their slots are collinear, they are in each other's direction of minimum radiation. When they are oriented such that their slots are parallel, they are in each other's direction of maximum radiation. Both cases were investigated for on-wafer and for diced chips. The chip-to-chip links with both antennas on different chips exhibit higher insertion loss. The lower insertion loss of links between antennas on the same chip is due to the contribution of surface waves. The worst-case transmission link (gain-chip-to-chip link) in the direction of minimum radiation shows an insertion loss of

Lumped element circuit models can provide a compact description of wireless transmission links [20–22, 25]. Distributed circuits can be modeled also in a broad frequency band with arbitrary accuracy using lumped element network models. A general way to establish network models is based on modal analysis and similar techniques [2–5]. In the case of wireless transmission links, high insertion losses have to be considered. Therefore methods for the synthesis of lossy multiports have to be applied. In [23, 24] a lumped-element two-port

**Figure 8.** Antenna orientation with a) collinear and b) parallel slots, c) Measured insertion loss of a

Insertion Loss, dB

*<sup>c</sup>* = 50 μm 60 62 64 66 68 70 72 −30

−25 −20 −15 −10 −5 0

Return Loss, dB

Frequency, GHz

d

5 10 15 20 25 30 35

Distance, mm

Simulation Measurement

Main dir. wafer Main dir. diced Min dir. wafer Min dir. diced

a) b)

Measured return loss of the on-chip open slot antenna [14, 15].

*a* = 2 mm

a) c)

wireless chip-to-chip link depending [14, 15].


*b* = 1.1 mm

b)

We have investigated methods for an area-efficient design of on-chip integrated antennas, based on the utilization of the same metallization structures both as a CMOS circuit ground plane and as antenna electrodes. An experimental setup has been designed for validating the computed antenna parameters, as well as the interference between the CMOS interconnects and the antenna. Equivalent circuits have been established to model integrated antennas and wireless intra-chip and inter-chip transmission links.
