**5.1. The benchmark circuit: VCO with integrated switch**

To evaluate the efficiency of the SILO approach, a conventional circuit using a VCO with wide tuning range and an output switch was designed. The system with the manufactured IC is shown in Fig. 9.

The schematic of the VCO can be seen in Fig. 10, together with the half-circuit of the designed output switch.


**Table 1.** VCO component parameters

**Figure 9.** Pulsed frequency modulated continuous wave synthesizer system concept using an output switch

The VCO is based on a common collector Colpitts oscillator design, including a second varactor diode pair at the transistor base. It is described in detail in [8]. A short overview is given in the following.

A bipolar current mirror is used to drive the oscillator core. The emitter follower output buffer from [8] was replaced by a differential pair to increase common-mode rejection. The VCO frequency defining series resonant circuit consists of *LB* and *Cin*:

$$f\_{\rm res} = \frac{1}{2\pi\sqrt{L\_b C\_{\rm in}}}\tag{16}$$

12 UKoLoS 354 Ultra-Wideband Radio Technologies for Communications, Localization and Sensor Applications Concepts and Components for Pulsed Angle Modulated Ultra Wideband Communication and Radar Systems <sup>13</sup>

The circuit works by switching the bias currents through branches A and B, implemented by transistors *Q*<sup>1</sup> to *Q*<sup>4</sup> and *Q*<sup>5</sup> to *Q*8, respectively. This is done by alternating the control voltages applied to switching stages *Q*1/*Q*<sup>2</sup> and *Q*5/*Q*6. The differential common base stages (*Q*3/*Q*<sup>4</sup> and *Q*7/*Q*8) provide amplification and isolation, depending on the bias current. Transistor *Q*<sup>9</sup>

Concepts and Components for Pulsed Angle Modulated Ultra Wideband Communication and Radar Systems 355

Fig. 11 shows the transient simulation of the output signal for a single rising *VC* edge with a rise time of 5 ps. The delay between the control edge and a 90% of the output is below 250 ps. The addition of a matching network would improve insertion loss, but at the cost of worse area efficiency. The simulated input-referred noise was between 2.83 nV/√Hz and

As the injection locking property is universally stemming from oscillator theory, any oscillator can in theory be employed for switched-injection locking. There is an interesting trade-off to be made when considering an oscillator configuration for SILO building: The oscillator *Q*-factor should be high and excess loop gain should be low for better phase noise performance on the one hand, but a high-*Q* oscillator with low excess loop gain takes longer to begin oscillation, which is critical for pulsed angle modulated signal generation. A careful

Another consideration has to be put into the point in the oscillator loop where the signal is injected into. In a cross-coupled oscillator, the resonator and gain stages are directly connected to the output. This means that there has to be a buffering circuit for the injected signal which provides backward isolation, in order to ensure the oscillation frequency of the oscillator is

For the design of the SILO circuits, we concentrated on resonator-based oscillators, as they typically show better phase noise performance than inverter-based ring oscillators. A demonstrator implementation in discrete components was used for initial experimentation and verification of the viability of our approach. This circuit was aimed at a frequency range of 6 to 8 GHz. Subsequently, a SILO IC based on a pulse generator and a cross-coupled *LC*-oscillator was designed and manufactured. In a final step, a harmonics generator was combined with a Colpitts oscillator to sample a 5.8 GHz-signal and emit a 63.8 GHz-signal.

For reference and for first experiments, SILO implementations based on surface mounted planar technology were realized. They are based on an ordinary common-collector Colpitts oscillator and designed for a natural frequency of 6 GHz respectively 7.5 GHz. In order to implement injection-locking, a directional coupler was added to apply the injection signal to the oscillator's output (see Fig. 12). The maximum achievable (10 dB) bandwidth is about 600

Apart from parasitic technological limitations of lumped planar implementations, the single-ended design features an inherent source of self-locking to a harmonic of the switched power supply. Therefore, the pulse width is limited to about 10 to 20 ns in order to achieve a good compromise between bandwidth and minimum injection level. In consequence,

A combination of VCO and output switch was simulated and then manufactured.

provides the bias current, which is switched between the branches.

3.67 nV/√Hz.

**5.2. SILO oscillator concepts**

**5.3. 6 and 8 GHz SMT SILO**

MHz at 7.5 ns pulse width.

balance between the two qualities has to be found.

not influenced by the circuitry connected to the tank.

**Figure 10.** Synthesizer key components; left: VCO, right: half-circuit of single-pole double-throw switch

*LB* is realized as a spiral inductor without tuning capability. Tuning is available by varying *Cin*, which has to be tuned over a wide tuning range using variable MOS-capacitance circuits.

For a minimum influence on the tuning range, *CP* has to be minimized. It consists mainly of the collector base capacitance *CCB* of transistor *T* and thus is given by size and bias conditions. *CS*, which is determined mainly by *CBE*, has to be maximized. Additionally, both varactor capacitance ranges have to be maximized. For a more detailed discussion, refer to [15]

The proposed pulsed ultra-wideband signal generation requires a switch after the frequency synthesizing PLL. The switch should have a minimum switching time in both on and off direction to enable the usage of very short pulses (in the 1 − 10 ns range). Additionally, a constant input port impedance is important in order not to change the loading of the oscillator.

A switch circuit was designed based on [10]. The original work was aimed at a 22 − 29 GHz UWB radar for automotive applications. Fig. 10, right, shows the half-circuit.

**Figure 11.** Switch transient simulation: Output voltage signal (blue) in reaction to control voltage (red) change.

The circuit works by switching the bias currents through branches A and B, implemented by transistors *Q*<sup>1</sup> to *Q*<sup>4</sup> and *Q*<sup>5</sup> to *Q*8, respectively. This is done by alternating the control voltages applied to switching stages *Q*1/*Q*<sup>2</sup> and *Q*5/*Q*6. The differential common base stages (*Q*3/*Q*<sup>4</sup> and *Q*7/*Q*8) provide amplification and isolation, depending on the bias current. Transistor *Q*<sup>9</sup> provides the bias current, which is switched between the branches.

Fig. 11 shows the transient simulation of the output signal for a single rising *VC* edge with a rise time of 5 ps. The delay between the control edge and a 90% of the output is below 250 ps. The addition of a matching network would improve insertion loss, but at the cost of worse area efficiency. The simulated input-referred noise was between 2.83 nV/√Hz and 3.67 nV/√Hz.

A combination of VCO and output switch was simulated and then manufactured.
