*5.2.5. Experimental results*

The ADC with the proposed parallel reference network was implemented in 0.25 µm SiGe BiCMOS technology. The Chip micrograph of the ADC is depicted in Fig. 42.

**Figure 42.** ADC's chip micrograph.

**Static measurements:** For measuring static errors of the ADCs, a low frequency 50 MHz sine signal was applied to the input of the converter at 5 GS/s sample rate. A deviation of a transition from the mean value, the differential nonlinearity (DNL), was calculated for each step. A cumulative sum of differential errors represents the integral nonlinearity (INL). The results are graphically presented in Fig. 43.

**Figure 43.** DNL and INL from histogram testing of ADC.

414 Ultra-Wideband Radio Technologies for Communications, Localization and Sensor Applications

**Figure 41.** Master-slave comparator, full schematic diagram.

*5.2.5. Experimental results* 

**Figure 42.** ADC's chip micrograph.

latch.

The master latch has an auxiliary current source *Iaux.* This current source prevents the crosscoupled differential pair from being completely switched off, thus keeping the base-emitter capacitance charged. The time to charge this capacitance is decreased, and as a result the overall speed of the latch is increased. The *Iaux* has to be sufficiently small because it adds hysteresis which decreases the sensitivity of the comparator. Setting the value of *Iaux* equal to 10 % of *IEE2* is a good compromise between speed and sensitivity. In the slave latch, there is no auxiliary current source because the input signal of the slave latch is relatively large, and an auxiliary current source does not have a strong influence as in the case of the master

The ADC with the proposed parallel reference network was implemented in 0.25 µm SiGe

BiCMOS technology. The Chip micrograph of the ADC is depicted in Fig. 42.

**Dynamic measurements**: Signal-to-noise and distortion ratio (SINAD) of the test circuit was measured over the frequency range up to 6 GHz at a constant sample rate of 15.01 GS/s. The small frequency offset of 10 MHz was made to accumulate quantization errors over the whole dynamic range. The measurement results are presented in Fig. 44, which shows SINAD of the converter up to the input frequency of 6 GHz. The dashed line shows a level where SINAD drops 3 dB below its value at low frequency. The frequency where SINAD crosses the 3 dB line indicates the effective resolution bandwidth of the converter, which in this case is greater than 6 GHz.

HaLoS – Integrated RF-Hardware Components for Ultra-Wideband Localization and Sensing 417

The functional diagram of the predictor is depicted in Fig. 45. The predictor consists of the memory where the data from the ADC are accumulated; an averaging block, which makes averaging of the accumulated data; and a block where the output DAC value is calculated. An algorithm to calculate the DAC value is a modified version of the successive

The described functionality is coded using VHDL language and implemented using ECL library available in IHP BiCMOS Technology. For speed purposes, the predictor was divided into several sub-blocks which were implemented separately. This method decreases the complexity of the separate sub-block, and achieves a higher operational speed. The block diagram of the predictor is depicted in Fig. 46. The predictor consists of a demultiplexer, a bank of predicting blocks and a multiplexer. A predicting block carries out three functions: accumulation, averaging, and prediction. The demultiplexer deserializes the M-Sequence and commutates M-Sequence parts (chips) to the individual predicting blocks so that each has to work with only one defined chip. The multiplexer reverses the parallel processing

approximation algorithm with a constant ±LSB step.

and serializes the predicted values which finally fed the DAC.

**5.4. High-speed digital-to-analog converter with off-chip calibration** 

The digital-to-analog converter transforms a digitally predicted value into the analog domain. To prevent information loss, the accuracy of the DAC should correspond to the accuracy of the whole capturing device. Simultaneously, the DAC should work at 10 GS/s. To satisfy both requirements, the converter is implemented using a segmented current steering architecture. The block diagram of the converter is depicted in Fig. 47. It consists of the two segments: A unary sub-converter and an R-2R sub-converter. The current sources of the both sub-converters are connected to the summing node. As will be seen later from measurements relying only on technology, component matching would give insufficient accuracy, which in this particular case is 10 times lower than required. Therefore, an additional calibration of the current sources is implemented. The current sources are

**Figure 46.** Structure diagram of the predictor.

**Figure 44.** Measured SINAD over a frequency range up to 6 GHz.

### **5.3. High-speed predictor**

The main function of the predictor of predicting the part of the received value was described above. The predictor also carries out two additional functions:


**Figure 45.** Functional diagram of the predictor.

The functional diagram of the predictor is depicted in Fig. 45. The predictor consists of the memory where the data from the ADC are accumulated; an averaging block, which makes averaging of the accumulated data; and a block where the output DAC value is calculated. An algorithm to calculate the DAC value is a modified version of the successive approximation algorithm with a constant ±LSB step.

The described functionality is coded using VHDL language and implemented using ECL library available in IHP BiCMOS Technology. For speed purposes, the predictor was divided into several sub-blocks which were implemented separately. This method decreases the complexity of the separate sub-block, and achieves a higher operational speed. The block diagram of the predictor is depicted in Fig. 46. The predictor consists of a demultiplexer, a bank of predicting blocks and a multiplexer. A predicting block carries out three functions: accumulation, averaging, and prediction. The demultiplexer deserializes the M-Sequence and commutates M-Sequence parts (chips) to the individual predicting blocks so that each has to work with only one defined chip. The multiplexer reverses the parallel processing and serializes the predicted values which finally fed the DAC.

**Figure 46.** Structure diagram of the predictor.

416 Ultra-Wideband Radio Technologies for Communications, Localization and Sensor Applications

**Figure 44.** Measured SINAD over a frequency range up to 6 GHz.

0

5

10

15

SINAD, dB

20

25

30

above. The predictor also carries out two additional functions:

Decreasing the data throughput for further data processing.

The main function of the predictor of predicting the part of the received value was described

1 2 3 4 5 6

SINAD

3 dB decay of SINAD

Input frequency, GHz

Making subsequent averaging of the digitized values, increasing signal-to-noise ratio of

*Navg*

**5.3. High-speed predictor** 

the measured signal.

**Figure 45.** Functional diagram of the predictor.

 

### **5.4. High-speed digital-to-analog converter with off-chip calibration**

The digital-to-analog converter transforms a digitally predicted value into the analog domain. To prevent information loss, the accuracy of the DAC should correspond to the accuracy of the whole capturing device. Simultaneously, the DAC should work at 10 GS/s. To satisfy both requirements, the converter is implemented using a segmented current steering architecture. The block diagram of the converter is depicted in Fig. 47. It consists of the two segments: A unary sub-converter and an R-2R sub-converter. The current sources of the both sub-converters are connected to the summing node. As will be seen later from measurements relying only on technology, component matching would give insufficient accuracy, which in this particular case is 10 times lower than required. Therefore, an additional calibration of the current sources is implemented. The current sources are 418 Ultra-Wideband Radio Technologies for Communications, Localization and Sensor Applications

realized as voltage controlled current sources. The controlling voltages are produced by auxiliary low-power µDACs which are externally controlled via SPI interface.

HaLoS – Integrated RF-Hardware Components for Ultra-Wideband Localization and Sensing 419

uncalibrated calibrated

uncalibrated calibrated

**Static measurements**: The DAC test chip was implemented in SiGe 0.25 µm BiCMOS IHP technology. The chip was mounted on a test board and connected to the FPGA board. The results of static tests are given in Fig. 48 where both DNL and INL values before and after calibration are given. INL errors were also recalculated in percent of the input range. To

5 10 15 20 25 30

5 10 15 20 25 30

5 10 15 20 25 30

code

code

code

**Figure 48.** DNL and INL of uncalibrated and calibrated DAC output.




INL, LSB

0 0.5

1

DNL, LSB

**Figure 49.** Static accuracy of the calibrated DAC.

0

0.05

0.1

0.15

error, %

0.2

0.25

*5.4.1. Experimental results* 

The calibration algorithm could be characterized as successive approximation of the DAC output to the reference value. The detailed calibration flow of the each current source is as follows:


A set-up to implement the proposed calibration scheme is depicted in Fig. 47. The calibration algorithm is implemented on a Spartan-3AN Starter Kit board.

**Figure 47.** Off-chip calibration of the DAC.

### *5.4.1. Experimental results*

418 Ultra-Wideband Radio Technologies for Communications, Localization and Sensor Applications

auxiliary low-power µDACs which are externally controlled via SPI interface.

For this purpose, the corresponding digital input is applied to the DAC.

measurement is performed with a 14-bit ADC on an FPGA board.

4. According to a binary search algorithm, the MSB of µDAC is set to "1".

calibration algorithm is implemented on a Spartan-3AN Starter Kit board.

3. The CSUC is connected to the summing node.

value" and the measured value is calculated.

8. Steps 1-7 are repeated for each current source.

**Figure 47.** Off-chip calibration of the DAC.

7. Steps 4-6 are repeated for the remaining 9 bits of µDAC.

follows:

µDAC is made.

realized as voltage controlled current sources. The controlling voltages are produced by

The calibration algorithm could be characterized as successive approximation of the DAC output to the reference value. The detailed calibration flow of the each current source is as

1. The current source under calibration (CSUC) is disconnected from the summing node.

2. The analog output of the DAC is measured and stored in memory as "zero-value". The

5. The output of ADC is measured again, and the difference between the stored "zero-

6. Depending on this difference, the decision concerning the value of the MSB of the

A set-up to implement the proposed calibration scheme is depicted in Fig. 47. The

**Static measurements**: The DAC test chip was implemented in SiGe 0.25 µm BiCMOS IHP technology. The chip was mounted on a test board and connected to the FPGA board. The results of static tests are given in Fig. 48 where both DNL and INL values before and after calibration are given. INL errors were also recalculated in percent of the input range. To

**Figure 48.** DNL and INL of uncalibrated and calibrated DAC output.

**Figure 49.** Static accuracy of the calibrated DAC.

achieve 9-bit overall resolution, the DAC should have an error below 0.2 %. The measured error after calibration is depicted in Fig. 49. The error is below 0.15 %.

HaLoS – Integrated RF-Hardware Components for Ultra-Wideband Localization and Sensing 421

predictor to comply with different system parameters, such as the M-sequence length or

An off-chip calibration was implemented for the high-speed digital-to-analog converter. The calibration is implemented on an FPGA-board. After having been modified slightly, it could be integrated into the DAC. The static errors of the DAC after calibration are lower than 0.15 % which allows the use of a converter in the data capturing device with a target resolution

While previous sections were aimed to discuss specific sub-components such as individual semi-conductor chips of an UWB-sensor, we would like to consider some aspects of the whole sensor electronics here. For that purpose, several M-Sequence devices were implemented at different integration levels, and some Ukolos-partners (*ultraMedis*, *CoLoR*) were provided with demonstrator devices for their own use. In order to have a running sensor system, the device implementation has to cover the whole manufacturing cycle from chip-design and manufacture, chip housing, RF-PCB-design and assembly, design and implementation of the digital components (ADC, FPGA, interfaces etc) up to the programming of sensor internal pre-processing, the data transfer to the host PC and application-specific software for data evaluation and visualization. Furthermore, device specific test and evaluation methods and routines had to be developed and implemented in

In what follows, we will first introduce an experimental device which is aimed to evaluate new concepts or modifications under real conditions. Secondly, we refer to a device configuration which implements the principle depicted in Fig. 4 for the practical use by other Ukolos-projects and finally, there will be some discussions toward single chip

The aim of an experimental demonstrator device is to investigate the impact of individual sub-components on the performance of the whole device, as well as to have the opportunity to flexibly perform device modifications without the need of redesigning complex RF-PCBs. The device is organized in a modular concept as symbolically depicted in Fig. 51. Fig. 52

The individual sub-components as e.g. shift register for stimulus generation, T&H-circuits, RF-power distribution, RF-synchronization etc. are organized as plug-ins. Hence, one can simply replace a device component by a new one if improved circuits, better IC-housing or

order to perform high-resolution device characterization (e.g. [48])

shows an example of a demonstrator implementation of such kind.

**6.2. Experimental demonstrator device** 

*6.2.1. Device concept and aim* 

averaging factor.

**6. M-sequence devices** 

**6.1. Introduction** 

of 9 bits.

solutions.

**Dynamic measurements**: Dynamic characteristics of the DAC were measured together with the 4-bit ADC under the assumption that LSB usually works faster than MSB. The direct measurement of the spurious free dynamic range (SFDR) has no practical sense since the ADC limits the overall performance. For estimating the performance, an envelope test was applied [45]. Proper work of the converters assumes the presence of the all transition steps at the frequency of interest. Fig. 50 shows DAC outputs at 5 GHz and 5.5 GHz. Both converters (ADC and DAC) have all 16 transition levels up to 5.5 GHz input. Only the amplitude at 5.5 GHz starts to decay.

**Figure 50.** Envelope test of ADC-DAC at **a)** 5 GHz and **b)** 5.5 GHz.
