**5. Conclusion**

28 Will-be-set-by-IN-TECH

min search

other bit nodes

other check nodes

realization on arithmetic and circuit level refer to [62].

*4.1.3. Quantitative architecture comparison*

**Figure 22.** Partially bit-serial architecture

accumulator + saturation

accumulator + saturation

*dC dC*

*L(qi,j) L(ri,j)*

*Lk (c,q)*

architecture with a bit-parallel bit node allows for the smallest number of clock cycles per iteration and, thus, promises the highest decoder throughput. As the bit-parallel realization of the bit node would result in a large silicon area and a long critical path, further optimizations on arithmetic level have to be done. Here, it is possible to gain from the bit-serial input data stream by realizing the multi-operand adder in the bit node bit-serially using an MSB-first data flow. Within each clock cycle a partial sum *L<sup>k</sup>* (*c*, *q*) for the received bit-weight is generated which is accumulated subsequently to derive the new estimation *L*(*Qi*) as is shown in the decoder loop in Figure 22. The long ripple path in the accumulator unit running over the complete word length can be reduced using a carry-select principle. For further details of the

The cost models have been adapted to the new architecture concepts to allow for a quantitative evaluation of the architecture design space. Figure 23(a) illustrates the resulting silicon area *A* and iteration period *TIT* of the fully bit-parallel, fully bit-serial, hybrid-cell and partially bit-serial decoder architecture for three different code complexities *n* · *dV* = 5, 000, 10, 000 and 15, 000. For all code complexities the new architecture concepts are Pareto optimal as they allow for a trade-off between silicon area and iteration period in comparison to the bit-parallel and bit-serial architectures. Considering small code complexities the decoder architectures with a bit-parallel interconnect show the smallest area-time (AT) product and, therefore, are most AT-efficient. Considering a specified decoder throughput, the hybrid-cell architecture is promising whenever the timing constraints cannot be met by using bit-serial approaches, as it reduces the silicon area significantly in comparison to the bit-parallel bitand check-node architecture. The new partially bit-serial architecture features the smallest area-time product for all code complexities larger than 9, 000. In comparison to the bit-serial architecture a significantly smaller iteration period with only a slightly increased area is achieved. The architectures with a bit-parallel interconnect are located further and further away from the curve representing the smallest achievable area-time product. Here, the timing advantage of the bit-parallel architectures vanishes for large code complexities. Figure 23(b) depicts the energy per decoding iteration *EIT* of the four decoder architectures for different code complexities. The advantage with respect to energy of the decoder architectures with a

partial sum *dV dV*

> other check nodes

other bit nodes

> This chapter presented results, accomplished within the frame of the DFG priority program »Ultrabreitband Funktechniken für Kommunikation, Lokalisierung und Sensorik«. Focus was put primarily on the analysis and optimization of on-chip and chip-to-chip multi-conductor/multi-antenna interconnects. While we could show that special techniques of physical optimization, coding and signal processing can improve interconnect performance to a remarkable degree, it is expected that even higher performance is achievable in chip-to-chip communication, when multi-conductor interconnects are replaced by wireless ultra-wideband multi-antenna interconnects. Hereby, the signal pulses do not necessarily increasingly disperse as they travel along their way to the receiving end of the interconnect. The propagating nature of the wireless interconnect can make for a much more attractive channel for chip-to-chip communications. The primary goal has been the development of both theoretical and empirical foundations for the application of ultra-wideband multi-antenna wireless interconnects for chip-to-chip communication. Suitable structures for integrated ultra-wideband antennas have been developed, their properties theoretically analyzed and verified against measurements performed on manufactured prototypes. Qualified coding and signal processing techniques, which aim at efficient use of available resources of bandwidth, power, and chip area has been proposed. In addition, attention was given to the implementation of iterative decoding structure for LDPC codes. Detailed cost-models, which are based on signal flow charts and VLSI implementations of dedicated functional blocks

#### 30 Will-be-set-by-IN-TECH 104 Ultra-Wideband Radio Technologies for Communications, Localization and Sensor Applications Chip-to-Chip and On-Chip Communications <sup>31</sup>

have be developed, which allow for an informative analysis of elementary trade-offs between throughput, required chip area, and power consumption. This work has been supported by the German Research Foundation (DFG) under the priority program UKoLoS (SPP1202).

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