**5. References**

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**1. Introduction**

http://dx.doi.org/10.5772/52981

In high-performance integrated circuits manufactured in CMOS deep sub-micron technology, the speed of global information exchange on the chip has developed into a bottleneck, that limits the effective information processing speed. This is caused by standard on-chip communication based on multi-conductor interconnects, e.g., implemented as parallel interconnect buses. The supported clock frequency of such wired interconnects - at best remains constant under scaling, but - for global interconnects - reduces by a factor of four, as the structure size is reduced by half. Such multi-conductor interconnects also exhibit some undesirable properties when used for chip-to-chip communication. The much larger distances that have to be bridged, force the clock frequencies for the chip-to-chip interconnects to much lower values than those for on-chip circuitry. In widening up this bottleneck by increasing the number of parallel wires, the separation between the wires has to decrease. This causes increased mutual coupling between neighboring wires, which reduces the supported clock

**Chip-to-Chip and On-Chip Communications** 

**Chapter 3**

Josef A. Nossek, Peter Russer, Tobias Noll, Amine Mezghani,

Michel T. Ivrlač, Matthias Korb, Farooq Mukhtar,

Hristomir Yordanov, Johannes A. Russer

Additional information is available at the end of the chapter

The high clock frequencies used in on-chip interconnects and the huge information rate of chip-to-chip communication lets possible solutions belong to the domain of ultra-wideband (UWB) technology. Pursuing suitable solutions, we explore firstly the improvement of the multi-conductor interconnect by signal processing and coding. From information theory, it is known that information can be transmitted through a noisy channel with arbitrary low probability of error as long as the rate is lower than the channel capacity given by the Shannon theorem. Achieving this capacity requires, however, sophisticated digital signal processing and coding. In particular, the DAC (Digital-to-analog converters) and the ADC (analog-to-digital converter) components which are formed by the output or the input of a logic CMOS inverter, respectively, turns to be a limiting factor. In fact, the ADC and DAC components, perform a single-bit conversion between the analog and the digital domain. With such coarse quantization, all state of the art techniques for signal processing fail. We provide information theoretic bounds on the improvements possible by coding the transmission, and propose methods to design suitable codes which allow decoding with low latency.

> ©2013 Mezghani et al., licensee InTech. This is an open access chapter distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0),which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly

©2013 Mezghani et al., licensee InTech. This is a paper distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

frequency and counters the effect of having more wires in the first place.

cited.

[23] Yomo, H., Popovski, P., Wijting, C., Kovács, I. Z., Deblauwe, N., Baena, A. F. & Prasad, R. [Sep. 2003]. Medium Access Techniques in Ultra-Wideband Ad Hoc Networks, *in Proc. the 6th Nat. Conf. Society for Electronic, Telecommunication, Automatics, and Informatics (ETAI) of the Republic of Macedonia* .
