**6.3. Prototype devices**

426 Ultra-Wideband Radio Technologies for Communications, Localization and Sensor Applications

digital high-speed system.

10 20

**propagation time**

**Figure 55.** Basic structure of an M-Sequence feedback approach.

**Data out**

0 1 2 3 4 5 6 7

number of stimulus period

1 11

**observation time**

5 5 5

6 6 6

7 7 7 4 4 4

2 2 2

3 3 3

Shot 1 Shot 2 Shot 3

Shot 1 Shot 2 Shot 3

**FPGA DSP Timing,Data Flow, Prediction Filter**

range of the receive electronics can be relaxed.

can be relaxed.

Fig. 56 gives an example of the output signals of the T&H-circuit. The constant voltage during the hold phase must be captured by the ADC. In the open loop example (above), we can observe that the hold voltage jumps from sample to sample. Hence, the ADC must be able to convert voltages within a large range. The second example shows the closed loop operation. Now, the predicted value is subtracted before AD-conversion, and we actually get a voltage during the hold phase which is always at about the same level. Under optimum conditions, the magnitude of the prediction error is determined by the strength of random noise which is usually quit weak. Therefore the requirements onto the dynamic

**ADC**

sampling clock

**T&H**

**Control loop**

**Sync. Unit**

**Clk. Distr.**

master clock

**Clock** fc/2 **Shift**

enable

**Register PA**

**System**

sampling clock

**DAC**

Under optimum conditions, the magnitude of the prediction error is in the same order as random noise. Therefore, the demands made on the dynamic range of the receive electronics

feedback sampling implementation is to deal with high-speed signals (analog and digital) of low dynamic range (i.e. low amplitude) and to exploit the fact that the temporal variations of the scenarios under test are of the orders smaller than the measurement speed. This implies for the radargram (see Fig. 55, on the left) that adjacent samples at a horizontal line undergo only minor variations (instead of consecutive samples in sequential sampling). Thus, it will be possible to predict the measurement values along the observation time axis. This is the reason to insert a DAC into the feedback loop which converts the predicted digital values into analog ones. If the predicted signal levels are subtracted from the received signal, only the prediction error has to be captured by the ADC and processed by a

> Fig. 57 shows a photograph of a primary (1Tx 2Rx) M-sequence RF board and corresponding ADC PCB with PC Interface (USB). The RF board is designed for assembly with the *HaLoS*-project originating ICs. Each of the board layouts corresponds to the architecture shown in Fig. 4, so that both boards connected together represent the basic Msequence working unit. This unit is considered as main integral part of the UWB devices provided for partner projects within the UKoLoS- and other scientific projects.

**Figure 57.** Photograph of the primary 1Tx 2Rx RF board (left-hand side) and corresponding ADC board (right-hand side).

While in the early project phase the sensor devices were finalized in cooperation with Meodat GmbH (Ilmenau, Germany), the final device assembly was performed by ILMSENS (TU Ilmenau service GmbH, Ilmenau, Germany) later. To give the reader an impression, some device examples are depicted in Fig. 58 as well in the chapter 11.

428 Ultra-Wideband Radio Technologies for Communications, Localization and Sensor Applications

HaLoS – Integrated RF-Hardware Components for Ultra-Wideband Localization and Sensing 429

which the second (slave) receive channel can be used for device online calibration purposes. The desired MIMO usability as for instance in novel UWB-arrays for high-resolution nearfield imaging (*ultraMedis*) or localizations (*CoLoR*) with 1Tx 2Rx constellation of primary

**Figure 59.** Simplified architecture of a fully monolithically integrated UWB M-Sequence based

It is apparent that the presented single chip architecture envisages ultra-fast switching cells (i.e. stimulus generator and synchronization unit) with their relatively high signal swing output buffers as well as very sensitive analog input blocks integrated on the same chip substrate. So, the undesired signal coupling or cross-talk can degrade the performance of the sensitive receive circuitry and, consequently, of the whole system. Especially in the case of analog devices, which handle the ultra-wideband signals, the on-chip interferences can be catastrophic. For example, intermodulation/interaction of noise components with the measured signal within the frequency band of interest may cause device saturation. Therefore, special emphasis is put on the isolation of the SoC channels during the design

Particular functional circuit cores of the SoC transceiver components are designed to fulfill at minimum the parameters of the demonstrator plug-in blocks discussed above. Additionally, the SoC transceiver includes additional build-in options to open further functionalities as e.g. (equivalent time) oversampling [51] or frequency conversion in order to meet the UWB radiation rules [52]-[55]. In particular, the SoC concept is intended for very

sensing cells is also given.

transceiver.

*6.4.2. Design philosophy* 

phase ,as discussed in [2] or [49].

*6.4.3. Individual functional block peculiarities* 

**Figure 58.** Left-hand side: 1Tx 2 Rx UWB sensor unit (MEODAT). Middle and right-hand side: 1Tx 2Rx UWB sensor unit with portable power supply and UWB reflectometer (ILMSENS).
