*6.4.2. Design philosophy*

428 Ultra-Wideband Radio Technologies for Communications, Localization and Sensor Applications

UWB sensor unit with portable power supply and UWB reflectometer (ILMSENS).

**6.4. Single-chip sensor head** 

radar electronics into one silicon die.

*6.4.1. UWB single-chip head architecture* 

**Figure 58.** Left-hand side: 1Tx 2 Rx UWB sensor unit (MEODAT). Middle and right-hand side: 1Tx 2Rx

The ability to create an optimized multi chip sensor is apparent, but the manufacturability of such system is much more difficult with a longer parts list and more complex assembly as for instance in the case of the construction of complex MIMO sensing systems (see 8Tx 16Rx system in the chapter 11). One promising way is to realize all active high-frequency system components (i.e. components on the primary RF board – see Fig. 57 left-hand side) onto one chip. This will enhance the overall system performance, reliability, robustness and assembling yields. By contrast, however, increased complexity on the single die means more second-order effects that have not been studied so far. For example, undesired on-chip coupling interactions between the different constituent system components become more pronounced and are more challenging to manage especially because of dealing with ultrawideband signals. Such unwanted signal coupling or cross-talk can degrade the performance of the sensitive receive circuitry and, consequently, of the whole system. The aim to study such interactions which have not been considered so far, the expected advantages but also the knowledge gained from multi-chip approach analyses, have motivated the first monolithic integration of the complete RF-part of the M-sequence UWB

Fig. 59 shows the simplified block topology of the realized M-Sequence based single-chip transceiver head (alias System-on-Chip, SoC head). In correspondence with the system topology depicted in Fig. 4, the M-sequence transceiver SoC contains one transmitter and

According to our experience, the 1Tx-2Rx topology of the primary sensor cell represents the optimum regarding achievable performance and circuit complexity. Moreover, the implementation of 1Tx 2Rx structure on one die has the advantage of permitting both crosstalk investigations between active and passive circuit parts (i.e. transmitter and receiver) as well as between two passive parts (i.e. receiver 1 and 2). From a practical point of view, the stand-alone 1Tx 2Tx devices are suitable for implementations where two receive channels are needed a priori, e.g. for simple localization tasks or in material testing (see chapter 11) in

two receiver circuits (commonly assigned as 1Tx 2Rx configuration).

It is apparent that the presented single chip architecture envisages ultra-fast switching cells (i.e. stimulus generator and synchronization unit) with their relatively high signal swing output buffers as well as very sensitive analog input blocks integrated on the same chip substrate. So, the undesired signal coupling or cross-talk can degrade the performance of the sensitive receive circuitry and, consequently, of the whole system. Especially in the case of analog devices, which handle the ultra-wideband signals, the on-chip interferences can be catastrophic. For example, intermodulation/interaction of noise components with the measured signal within the frequency band of interest may cause device saturation. Therefore, special emphasis is put on the isolation of the SoC channels during the design phase ,as discussed in [2] or [49].

### *6.4.3. Individual functional block peculiarities*

Particular functional circuit cores of the SoC transceiver components are designed to fulfill at minimum the parameters of the demonstrator plug-in blocks discussed above. Additionally, the SoC transceiver includes additional build-in options to open further functionalities as e.g. (equivalent time) oversampling [51] or frequency conversion in order to meet the UWB radiation rules [52]-[55]. In particular, the SoC concept is intended for very

### 430 Ultra-Wideband Radio Technologies for Communications, Localization and Sensor Applications

wideband material investigations and MIMO-applications like in medical microwave imaging [56]-[61].

HaLoS – Integrated RF-Hardware Components for Ultra-Wideband Localization and Sensing 431

an area of about 2000 1200 *µm µm* and the build-in circuits consume in total about 300 mA

**Figure 60.** Microphotograph of the SiGe M-Sequence based transceiver head die with depicted

For the sensor head prototype evaluation, the transceiver chip has been measured on wafer as well as packaged with well-established chip-on-board technology using an optimized composite 4-layer carrier made from Rogers 4003C™, FR4 laminate and ultrasonic bonding procedure with 1-mil aluminum wires. The bond wire landing areas for RF ports on the board are designed to match as closely as possible (i.e. realizable) the pitch on the IC to avoid long wire connections. The cavity approach has not been implemented because of challenging technological realization on the selected carrier board. Fig. 61 shows the test board whereat the wired die is zoomed out for better visualization. The die is located in the center of the photo and top glue is used to protect the bond wires. It is mounted on a metal patch which is connected with VEE. This allows a direct connection between the substrate and the board's lowest potential. The top layer is mainly used for RF signal routing whereas the bottom layer is used for control lines. The inner plane layer below the top layer is the common board GND, and it also provides the GND reference for the RF signal lines. The other inner plane is the supply layer. The supply is bypassed to the GND with a 0.1 µF

A basic test set-up for the sensor head prototype parameter evaluation is symbolically depicted in Fig. 62. The photograph on the right side shows an example of such test assembly. The evaluation board is connected to a 10-bit data "digitizer" (ADC), FPGA control and pre-processing unit which is equipped also with the PC interface. Moreover, for the parameter characterization, stable sinusoidal reference has to be connected to the system

particular functional blocks. The die size is 2 1.2 mm2.

ceramic capacitor placed as close as possible to the die.

*6.4.4. Single chip transceiver head evaluation* 

from 3 V supply.

In summary, the goals of the single-chip integration are:


Thus, to achieve the desired MIMO usability, the shift register may be enabled and disabled, and transmitter buffers can be switched off (power down) by simple TTL-signals so that no external RF-switch is required to operate in a MIMO system. The transceivers are designed in such a way that they may either work while being driven individually or they may be cascaded with respect to the master system clock so that all units of a MIMO array work synchronously. Once the array is calibrated, a power down feature will be used for active transmitter selection. Thus, all receivers of MIMO array work in parallel and capture permanently data in order to get maximum measurement speed. As shown in Fig. 59, the transceiver IC is equipped with a wideband multiplier which optionally allows the sensor stimulus frequency band to be shifted and doubled ([2] or [49], [55]) or the operational band to be adapted to a specific application [50] in conformity with regulation requirements [52] - [54]. The channel is designed for operation up to 18 GHz.

Moreover, the multiplier can invert the stimulus M-sequence by implementing simple ECL signals on the control port. This feature may be useful to provide uncorrelated transmit signals in MIMO arrays. In addition, the sampling timing control chain is equipped with optional switchable shunt path. This add-on allows direct clock supplying from chip periphery. Thereby, user-selectable sampling rates or enhanced signal capturing approaches (e. g. equivalent time oversampling approach [50]) are possible without IC redesign. The analog receivers are designed to operate with wideband signals up to 18 GHz. The maximum linear operation input signal peak-peak swing is 60 mV.

Fig. 60 shows the chip die micrograph of the discussed transceiver with marked particular functional blocks and well visible top metal of a decoupling guard between the transmitter and receiver (line in the middle). The transmitter and receiver cores as well as their particular I/O pads are placed on the opposite die sides to minimize mutual on-chip coupling as well as inductive coupling between the bond wires after packaging. As extensively discussed in [62] or [63], [64], the decoupling guard is a guard well in a trench between the noisy transmitter and sensitive receivers. In the final assembly, the guard is connected to the quiet potential in order to fix the voltage of the substrate between the Tx and Rx die part by absorbing potential substrate fluctuations. The transceiver die occupies an area of about 2000 1200 *µm µm* and the build-in circuits consume in total about 300 mA from 3 V supply.

**Figure 60.** Microphotograph of the SiGe M-Sequence based transceiver head die with depicted particular functional blocks. The die size is 2 1.2 mm2.
