*5.2.1. High-speed analog-to-digital converter*

The fastest type of the A/D converters is a full flash ADC. A block diagram of a typical full flash converter is shown in Fig. 39. It consists of a reference network, a bank of comparators, correction and encoding logic and test buffers. The challenges of the implementation of the ADC are usually related to the analog part of the converter, namely to the reference network and to the bank of the comparators. It is possible to implement the high-speed comparator in the selected technology which will satisfy all requirements, but the reference network is a bottle-neck of the converter.

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Drawbacks of the conventional differential reference network are mainly due to its serial configuration; a change in one component will affect the others. This inherent property of the serial connection makes individual adjustments and compensations impossible. To overcome this limitation, a new configuration of the reference network is proposed. An idea is to build the resistor network in a segmented serial-parallel configuration and substitute one driver (emitter follower) with several drivers, connected in parallel. A full overview of the possible configurations is described in [44]. Among this variety one configuration should be highlighted, namely the configuration illustrated in Fig. 40 where each segment contains one tap resistor and one current source. The reference network is fully parallel, thus

The main feature of the parallel network is the flexibility to choose component values. This freedom gives the possibility of equalizing the bandwidth of an individual segment that

Fig. 40 shows the case when all driver currents are equal. In practice, it is more useful not to keep the currents in all segments equal, but to equalize the bandwidths in each segment instead. The network, however, does not only present good advantages, it also has some drawbacks. Flexibility of adjusting different parameters leads to different geometries of the resistors. In the case of the conventional network, all resistors have the same value and the same geometry. Proper layout minimizes the mismatch between them. The proposed

Signals from the reference network are led to a bank of *n* comparators. Comparators decide if the input is above or below the reference. For decreasing the probability of errors, a master-slave comparator with a preamplifier is used. An overall schematic diagram is shown in Fig. 41. The role of the preamplifier for the comparator is twofold: It works as a limiting amplifier, and it provides an additional amplification of the input signal. Another important function of the preamplifier is isolating the reference network from kick-back noise, produced by the master latch. In this particular example, the Cherry-Hooper amplifier

*5.2.3. Proposed bandwidth enhancement technique* 

allowing the maximum speed to be achieved.

network cannot benefit from this feature.

with emitter follower feedback is used as preamplifier.

*5.2.4. Design of comparator* 

leads to the optimal speed at given power dissipation.

**Figure 40.** Parallel configuration of the network with one resistor per segment.

**Figure 39.** Block diagram of the full flash ADC.

## *5.2.2. Reference network*

The task of the reference network is to provide equidistant reference voltages which will be further processed by the comparators.

There are two conventional implementations of the reference network. First, the simplest way is a Kelvin divider or resistor ladder. It suffers from several drawbacks, such as DCbowing, clock and input feed-through [43]. Furthermore, is not well suited for the highspeed ADCs.

A second configuration is a differential one. It consists of two branches; each has a driver loaded with a chain of serially connected tap resistors. Both branches are equal, only outputs of the second branch are "inverted" or mirrored with respect to the middle point [43]. The main problem related to the differential network is its bandwidth, which often becomes a bottleneck of the system. The reference network has to drive a big parasitic capacitive load caused by the bank of comparators. In the full flash ADC, it is one of the main limitations, because the number of comparators is doubled when increasing the resolution by 1 bit.

The second problem of such network is the non-equal transfer characteristic of the output nodes [42].

### *5.2.3. Proposed bandwidth enhancement technique*

412 Ultra-Wideband Radio Technologies for Communications, Localization and Sensor Applications

The task of the reference network is to provide equidistant reference voltages which will be

There are two conventional implementations of the reference network. First, the simplest way is a Kelvin divider or resistor ladder. It suffers from several drawbacks, such as DCbowing, clock and input feed-through [43]. Furthermore, is not well suited for the high-

A second configuration is a differential one. It consists of two branches; each has a driver loaded with a chain of serially connected tap resistors. Both branches are equal, only outputs of the second branch are "inverted" or mirrored with respect to the middle point [43]. The main problem related to the differential network is its bandwidth, which often becomes a bottleneck of the system. The reference network has to drive a big parasitic capacitive load caused by the bank of comparators. In the full flash ADC, it is one of the main limitations, because the number of comparators is doubled when increasing the resolution by 1 bit.

The second problem of such network is the non-equal transfer characteristic of the output

**Figure 39.** Block diagram of the full flash ADC.

further processed by the comparators.

*5.2.2. Reference network* 

speed ADCs.

nodes [42].

Drawbacks of the conventional differential reference network are mainly due to its serial configuration; a change in one component will affect the others. This inherent property of the serial connection makes individual adjustments and compensations impossible. To overcome this limitation, a new configuration of the reference network is proposed. An idea is to build the resistor network in a segmented serial-parallel configuration and substitute one driver (emitter follower) with several drivers, connected in parallel. A full overview of the possible configurations is described in [44]. Among this variety one configuration should be highlighted, namely the configuration illustrated in Fig. 40 where each segment contains one tap resistor and one current source. The reference network is fully parallel, thus allowing the maximum speed to be achieved.

The main feature of the parallel network is the flexibility to choose component values. This freedom gives the possibility of equalizing the bandwidth of an individual segment that leads to the optimal speed at given power dissipation.

**Figure 40.** Parallel configuration of the network with one resistor per segment.

Fig. 40 shows the case when all driver currents are equal. In practice, it is more useful not to keep the currents in all segments equal, but to equalize the bandwidths in each segment instead. The network, however, does not only present good advantages, it also has some drawbacks. Flexibility of adjusting different parameters leads to different geometries of the resistors. In the case of the conventional network, all resistors have the same value and the same geometry. Proper layout minimizes the mismatch between them. The proposed network cannot benefit from this feature.

### *5.2.4. Design of comparator*

Signals from the reference network are led to a bank of *n* comparators. Comparators decide if the input is above or below the reference. For decreasing the probability of errors, a master-slave comparator with a preamplifier is used. An overall schematic diagram is shown in Fig. 41. The role of the preamplifier for the comparator is twofold: It works as a limiting amplifier, and it provides an additional amplification of the input signal. Another important function of the preamplifier is isolating the reference network from kick-back noise, produced by the master latch. In this particular example, the Cherry-Hooper amplifier with emitter follower feedback is used as preamplifier.

### 414 Ultra-Wideband Radio Technologies for Communications, Localization and Sensor Applications

The master latch has an auxiliary current source *Iaux.* This current source prevents the crosscoupled differential pair from being completely switched off, thus keeping the base-emitter capacitance charged. The time to charge this capacitance is decreased, and as a result the overall speed of the latch is increased. The *Iaux* has to be sufficiently small because it adds hysteresis which decreases the sensitivity of the comparator. Setting the value of *Iaux* equal to 10 % of *IEE2* is a good compromise between speed and sensitivity. In the slave latch, there is no auxiliary current source because the input signal of the slave latch is relatively large, and an auxiliary current source does not have a strong influence as in the case of the master latch.

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DNL

INL

**Static measurements:** For measuring static errors of the ADCs, a low frequency 50 MHz sine signal was applied to the input of the converter at 5 GS/s sample rate. A deviation of a transition from the mean value, the differential nonlinearity (DNL), was calculated for each step. A cumulative sum of differential errors represents the integral nonlinearity (INL). The

2 4 6 8 10 12 14

2 4 6 8 10 12 14

code

code

results are graphically presented in Fig. 43.



error, LSB

0 0.5

1

**Figure 43.** DNL and INL from histogram testing of ADC.



error, LSB

0 0.5

1

this case is greater than 6 GHz.

**Dynamic measurements**: Signal-to-noise and distortion ratio (SINAD) of the test circuit was measured over the frequency range up to 6 GHz at a constant sample rate of 15.01 GS/s. The small frequency offset of 10 MHz was made to accumulate quantization errors over the whole dynamic range. The measurement results are presented in Fig. 44, which shows SINAD of the converter up to the input frequency of 6 GHz. The dashed line shows a level where SINAD drops 3 dB below its value at low frequency. The frequency where SINAD crosses the 3 dB line indicates the effective resolution bandwidth of the converter, which in

**Figure 41.** Master-slave comparator, full schematic diagram.
