*6.2.2. Demonstrator performance*

The particular RF plug-ins of the demonstrator are designed to operate with signals of large fractional bandwidth at the lower end of microwave frequencies or with toggle frequencies up to about 20 GHz. The generator unit provides periodic M-sequences of length 2*m*-1, where *m* represents the order of the sequence. The demonstrator has optionally implemented 9*th* or 12*th* order generators, which accordingly produce signals with periods 511 or 4095 chips. The generator plug-in operates with toggle rates between 500 MHz and 20 GHz for the 9*th* order M-sequence, and the 12*th* order device may be operated between 500 MHz and 16 GHz. In the case of radar applications, the unambiguity range (4) of the measurement may cover values from 3.8 m (related to 9th order M-sequence and 20 GHz clock) up to 1.2 km (12*th* order M-sequence and 500 MHz clock).

The clock synchronization unit which precisely defines the receiver sampling points is a 9*th* order binary divider with a maximal toggle rate of 24 GHz. Random fluctuations of the sampling point (jitter) could be reduced down to some tens of femtoseconds [48] due to the balanced circuit topology and the optimized architecture of the timing system (see [2], [49] detailed discussions). Note, that the time position uncertainty of the measured impulse response (compare Fig. 5) is father decreased as consequence of the impulse compression (i.e. correlation; see [2] for discussion).

422 Ultra-Wideband Radio Technologies for Communications, Localization and Sensor Applications

device structures as shown in Fig. 4 or Fig. 55.

**Figure 51.** Modular concept of the experimental system.

**Figure 52.** Photograph of the demonstrator implementation example.

clock) up to 1.2 km (12*th* order M-sequence and 500 MHz clock).

The particular RF plug-ins of the demonstrator are designed to operate with signals of large fractional bandwidth at the lower end of microwave frequencies or with toggle frequencies up to about 20 GHz. The generator unit provides periodic M-sequences of length 2*m*-1, where *m* represents the order of the sequence. The demonstrator has optionally

511 or 4095 chips. The generator plug-in operates with toggle rates between 500 MHz and 20 GHz for the 9*th* order M-sequence, and the 12*th* order device may be operated between 500 MHz and 16 GHz. In the case of radar applications, the unambiguity range (4) of the measurement may cover values from 3.8 m (related to 9th order M-sequence and 20 GHz

or 12*th* order generators, which accordingly produce signals with periods

*6.2.2. Demonstrator performance* 

implemented 9*th*

RF-PCBs are available. Furthermore, the various modules may be interconnected to different

The clock distribution plug-in is an active device which recovers and distributes the sampling clock among the receivers and the analog-to-digital converters. The unit can handle clock pulses with 20 ps falling/rising edges and features wideband reverse signal rejection better than 40 dB per branch.

The receivers are ultra wideband sampling gates with an 18 GHz analog input bandwidth, better than -40 dB signal feed-through over the full bandwidth, -15 dBm input compression points and a decay rate of about 20 % per ms relative to full scale (i.e. 5…200 ppm per sampling cycle depending on the clock rate (0.5 – 20 GHz) of the system). Other potential components of the experimental demonstrator are discussed in sub-chapters 3 to 5.

The transmitter-receiver and receiver-receiver cross-talk is better than 130 dB over the full operational band. In order to achieve this value, attention was paid to RF-housing, clock signal distribution and power supply decoupling (see also Fig. 57). The recent configuration of the demonstrator RF electronics is able to handle (internally) up to about 70 000 IRFs per second ( 9*th* order M-sequence at 18 GHz system clock). The data transfer to a host PC (based on commercial standard interfaces like USB and LAN) reduces, however, the actually achievable update rate to about 300 IRFs/s. The corresponding gap is filled by synchronous averaging in order to use the available data amount for noise suppression. The achievable receiver dynamic is about 114 dB @ 1 IRF/s. It has to be noted that device non-linearity is classically qualified by the intercept point which is based on a Taylor-series model of the device under test and sine wave stimulation. In order to keep this established philosophy, the approach was extended to wideband signals [48].

This is illustrated by Fig. 53. In the example at the top, the Tx- and RX-port of an Msequence device were connected via a variable attenuator and the impulse response was recorded for attenuator values between 0 and 120 dB. In the case of very weak input signals (large attenuation), we can only observe noise and device internal cross-talk. If we reduce the attenuation, the wanted signal peak (it is called "main pulse" in Fig. 53) appears and increases linearly with the signal level while the cross-talk level remains constant. By reducing the attenuation further, other signal parts become to protrude from noise. They also increase linearity at the beginning. These signals are caused from device internal reflections, deviations from the ideal time shape of an M-sequence and misalignments of the ADC timing (refer to Fig. 54). We call them device internal clutter. For very high signal levels, the receiver will tend to saturate which leads to the compression of the main peak and the internal clutter signals. Furthermore, the appearing non-linear distortions create

### 424 Ultra-Wideband Radio Technologies for Communications, Localization and Sensor Applications

new signal peaks which leave an apparently chaotic mark (see [2] and Fig. 1 for details). While the cross-talk and the internal clutter may be removed by device calibration [50] since they are caused by linear effects, the non-linear distortions should be avoided by respecting corresponding input levels of the measurement signal.

HaLoS – Integrated RF-Hardware Components for Ultra-Wideband Localization and Sensing 425

The effect of ADC timing misalignment is illustrated in Fig. 54. Theoretically, the ADC could capture the voltage sample at any time point within the hold phase of the T&H-circuit since by definition the signal level should keep a constant value during the hold interval. Unfortunately this is not case as demonstrated by Fig. 54. Here, the impulse response (i.e. the correlation function) of the M-sequence device was recorded by insertion a variable delay between the start of the hold phase and the trigger of the ADC. Ideally, we should see only a single pulse as long as the ADC is triggered within the hold phase and noise within the track phase (which is however out of interest here). But actually, some spurious signals appear whose strength and time position depend on the delay between "hold-start" and ADC-trigger. Hence, by selecting a reasonable delay between T&H and ADC, we can

**Figure 54.** Sensor pulse response as a function of delay between T&H and ADC.

Only these variations are captured by that approach (see [2] for details).

This sub-chapter gives an example of the usefulness of the modular experimental device. It deals with feedback sampling. Feedback loops have been used for a long time in sampling circuits. However, they were usually restricted to sequential sampling having very large Nyquist rates so that only minor signal variations between consecutive samples appear.

In our case, this simple method cannot be applied since the voltage steps between two consecutive samples may cover the full receiver input range as we firstly apply Nyquist sampling and secondly, the natural order of the data samples may be disrupted due to interleaved sampling. Hence, we need some modifications of the principle which pose some

For the purpose of feedback sampling, the data capturing & control unit was additionally equipped with a digital-to-analog converter which has to provide the feedback signal. The principle and the device structure are depicted in Fig. 55. The idea behind the digital

minimize these spurious signals.

*6.2.3. M-sequence feedback-sampling* 

challenges to the practical implementation.

The level diagram at the bottom of Fig. 53 refers to the non-compressed receiver signal. It shows the strength of the linear, quadratic and cubic signal parts in dependency from the signal power (see [48] for details).

**Figure 53.** Top: Sensor pulse response of system as a function of the input level. Bottom: Level diagram (see also Fig. 1) of raw data (i.e. without impulse compression). In the shown case, the input related 1dB compression point is -14 dB below the transmitter power.

The effect of ADC timing misalignment is illustrated in Fig. 54. Theoretically, the ADC could capture the voltage sample at any time point within the hold phase of the T&H-circuit since by definition the signal level should keep a constant value during the hold interval. Unfortunately this is not case as demonstrated by Fig. 54. Here, the impulse response (i.e. the correlation function) of the M-sequence device was recorded by insertion a variable delay between the start of the hold phase and the trigger of the ADC. Ideally, we should see only a single pulse as long as the ADC is triggered within the hold phase and noise within the track phase (which is however out of interest here). But actually, some spurious signals appear whose strength and time position depend on the delay between "hold-start" and ADC-trigger. Hence, by selecting a reasonable delay between T&H and ADC, we can minimize these spurious signals.

**Figure 54.** Sensor pulse response as a function of delay between T&H and ADC.
