**4. Fabrication technique**

In this section, the fabrication process of the Si membrane PC technology for THz application is presented. Highly resistive silicon (> 5-10 kΩ-cm) was employed to implement PC based membrane structures for THz applications. Here, a novel PC technology for the THz wave that is a potential candidate as a compact and low loss media for THz wave propagation was introduced. More importantly, this technology has a potential for integration with other optoelectronic and micro-electronic devices. Devices were fabricated in the frequency band of 200 GHz - 1 THz. The thickness of the device layer is chosen between 80 μm and 400 μm based on the design. The thickness of the buried oxide layer that separates the silicon device layer from the silicon handle layer could be varied between 0.5 μm-5 μm. Handle silicon layer is a low resistive silicon that attenuates the THz signal significantly and must be taken into consideration in the fabrication technology design.

The fabrication process consists of both front side and backside processing of the SOI wafer. The front side processing involves etching of deep holes into the silicon layer. Backside processing consists of opening window at the backside of the devices to prevent coupling of the THz wave to the lossy substrate modes and guarantee low loss propagation. To pattern the device layer, standard lithography is utilized as opposed to the optical PC structure that requires nanometer range lithography. In order to etch deep holes (> 100 μm), Deep Reactive Ion Etching (DRIE) is required. Thick photoresist must be utilized for photolithography to stand the long etching process. 4 μm thick photoresist (S1827) was employed as a soft mask for the DRIE process.

The etching of the holes was carried out using an optimized DRIE process to create holes with smooth vertical side walls and the desired aspect ratio. The Bosch process which alternated between two modes of nearly isotropic plasma etching using SF6 for 7 sec and deposition of chemically inert passivation layer using C2F8 for 2 sec was employed. The SF6 and C2F8 flow rates were 300 sccm and 150 sccm, respectively. The process temperature is kept at 20oC. The etching rate is around 5μm/min, and can vary slightly during the etching process. Buried oxide acts as an etch stop.

The second phase of the process is opening a window at the backsides of the SOI wafer to construct the membrane PC structure. Handle silicon is a thick silicon (525 μm), which was removed by wet chemical etching. 30% KOH etching at 90oC, which gave an etching rate of almost 50μm/hr, was used. The front side of the wafer must be protected from the KOH etching. The KOH etching was carried out by a custom made wet etching tool which only exposes the backside of the wafer to hot KOH solution. KOH mask that covers the unetched areas must withstand 10 hours of KOH at 90oC. A thick amorphous silicon nitride film (a-SiN) of 1μm, was deposited using PECVD technique to function as the hard mask at the backside of the SOI wafer. The second lithographic step was performed to pattern the SiN layer for the opening windows at the backside of the SOI wafer. Again buried silicon dioxide functions as the etching stop (Bayat et al., 2009).

The SEM image of a fabricated membrane PC slab waveguide is shown in Fig. 17 (a). It shows that the window under the active area (waveguide area) has been etched nicely. Fig. 17 (b), is SEM picture of the top side showing the air holes close-up. It can be seen that the walls are sharply etched. The backside etching is also very important and critical. Fig. 17 (c)

In this section, the fabrication process of the Si membrane PC technology for THz application is presented. Highly resistive silicon (> 5-10 kΩ-cm) was employed to implement PC based membrane structures for THz applications. Here, a novel PC technology for the THz wave that is a potential candidate as a compact and low loss media for THz wave propagation was introduced. More importantly, this technology has a potential for integration with other optoelectronic and micro-electronic devices. Devices were fabricated in the frequency band of 200 GHz - 1 THz. The thickness of the device layer is chosen between 80 μm and 400 μm based on the design. The thickness of the buried oxide layer that separates the silicon device layer from the silicon handle layer could be varied between 0.5 μm-5 μm. Handle silicon layer is a low resistive silicon that attenuates the THz signal significantly and must be taken into consideration in the fabrication technology design.

The fabrication process consists of both front side and backside processing of the SOI wafer. The front side processing involves etching of deep holes into the silicon layer. Backside processing consists of opening window at the backside of the devices to prevent coupling of the THz wave to the lossy substrate modes and guarantee low loss propagation. To pattern the device layer, standard lithography is utilized as opposed to the optical PC structure that requires nanometer range lithography. In order to etch deep holes (> 100 μm), Deep Reactive Ion Etching (DRIE) is required. Thick photoresist must be utilized for photolithography to stand the long etching process. 4 μm thick photoresist (S1827) was

The etching of the holes was carried out using an optimized DRIE process to create holes with smooth vertical side walls and the desired aspect ratio. The Bosch process which alternated between two modes of nearly isotropic plasma etching using SF6 for 7 sec and deposition of chemically inert passivation layer using C2F8 for 2 sec was employed. The SF6 and C2F8 flow rates were 300 sccm and 150 sccm, respectively. The process temperature is kept at 20oC. The etching rate is around 5μm/min, and can vary slightly during the etching

The second phase of the process is opening a window at the backsides of the SOI wafer to construct the membrane PC structure. Handle silicon is a thick silicon (525 μm), which was removed by wet chemical etching. 30% KOH etching at 90oC, which gave an etching rate of almost 50μm/hr, was used. The front side of the wafer must be protected from the KOH etching. The KOH etching was carried out by a custom made wet etching tool which only exposes the backside of the wafer to hot KOH solution. KOH mask that covers the unetched areas must withstand 10 hours of KOH at 90oC. A thick amorphous silicon nitride film (a-SiN) of 1μm, was deposited using PECVD technique to function as the hard mask at the backside of the SOI wafer. The second lithographic step was performed to pattern the SiN layer for the opening windows at the backside of the SOI wafer. Again buried silicon

The SEM image of a fabricated membrane PC slab waveguide is shown in Fig. 17 (a). It shows that the window under the active area (waveguide area) has been etched nicely. Fig. 17 (b), is SEM picture of the top side showing the air holes close-up. It can be seen that the walls are sharply etched. The backside etching is also very important and critical. Fig. 17 (c)

**4. Fabrication technique** 

employed as a soft mask for the DRIE process.

process. Buried oxide acts as an etch stop.

dioxide functions as the etching stop (Bayat et al., 2009).

shows the SEM picture of the backside. It can be seen that the back is etched uniformly; the oxide at the back can be easily removed by buffered HF (BHF).

(a)

Fig. 17. SEM picture of fabricated (a) PC membrane slab waveguide (b) front side and backside of the PC structure.

Polarization rotation devices for potential applications in the THz frequency band (200 GHz – 1THz) were fabricated. The fabrication of this PC based polarization rotator is more complex in a sense that the front side processing requires two sets of masks. The first mask is employed to create the periodic loading layers. The second mask is for patterning of the PC slab waveguide. The third mask is used to open window at the back side of the structure. Fig. 18(a) shows the SEM picture of the periodic asymmetric loaded PC slab waveguide with square holes. The SEM picture shows that the walls are very sharp. In Fig. 18(b), the SEM picture of the periodic asymmetric loaded PC slab waveguide for circular air holes pattern is presented.

Photonic Crystal for Polarization Rotation 321

19(b). S11 (reflection) and S21 (transmission) are depicted by dashed and solid lines, respectively. The graphs show that the insertion loss is less than 2 dB in the entire band from 190 to 210 GHz. The return loss is higher than 20 dB. Thus, the waveguide can be employed

Fig. 19. (a) The schematic of the characterization setup consisting of PC slab waveguide, input/output tapers and rectangular waveguides (b) S11(blue line)-S21(red line) (return loss-

The same setup as in Fig. 19(a) has been used to characterize the polarization rotator. The input wave is TE10 mode with electric field pointing in y direction (Ey). For 90o polarization rotator, the input polarization rotates by 90o so that at the output plane the x-component of electric field is dominant. The output rectangular metallic waveguide is to be rotated by 90o to support Ex field. Fig. 20(a) shows the schematic of the polarization rotator with two alternating top loaded layers. Previously, it was shown that for this design the rotation angle for each top loaded layer is 6.5o; therefore, the polarization rotator with two top loaded layers rotates the input polarization by an angle of 22\*6.5o=26o. In this design, normalized frequency of a/λ=0.263 (where a and λ are the unit cell size and free space wavelength) is assigned to 200 GHz; thus, it is expected to see approximately 26o polarization rotation in the frequency band of 196-204 GHz corresponding to normalized

If the output taper shown in Fig. 19(a) was placed at the output, Ex component of the field would have been exposed to the geometry variation of the output taper imposing reversed rotation; the width of the taper in x-direction is decreasing along the propagation. To improve the polarization extinction ratio and enhance the coupling of Ex component to the rectangular metallic waveguide, the output taper was rotated by 90o, shown in Fig. 20 (a). Having rotated the output waveguide, it supports only Ex component and Ey component of the field reflects back. Thus, S21 and S11 parameters would provide a good measure of the

(a) (b)

as a wide band low loss transmission line.

insertion loss) plots of the PC slab waveguide

frequency band of a/λ=0.258-0.267.

polarization extinction ratio.

Fig. 18. SEM picture of (a) square hole PC polarization converter (b) circular hole PC and circular hole polarization converter.
