**7. Conclusions**

Comparative studies between Diamond SOI MOSFETs and Conventional ones counterparts by numerical simulations demonstrate that Diamond layout style can improve current drive, transconductance, on-state series resistance, frequency response (voltage gain and unit voltage gain frequency) when it is compared to the Conventional counterpart, considering the same gate area, geometry factor (aspect ratio) and bias conditions.

By using Diamond layout style, instead rectangular gate geometry, the die area of analog integrated circuits can be significantly reduced since the drain current of the Diamond structure is higher than the one observed in the Conventional counterpart, considering the same gate area, geometry factor (aspect ratio) and bias conditions.

Therefore, the Diamond layout style becomes an important device alternative to improve the performance of the transistors and consequently the performance of the analog and digital ICs.

This temperature studyin the Diamond layout structure shows the drain leakage current behavior in the Diamond SOI MOSFETs, in comparison to the conventional one counterpart, regarding these devices operating since room temperature (27oC) up to 300oC. From this investigation it is observed that IDLeak in Diamond SOI MOSFETs is higher than the one observed in Conventional devices operating at same bias and temperatures conditions, because the longitudinal electric field along the Diamond channel length is higher than the one found in the conventional counterpart. On the other hand, the DSM drain current is increased in the same proportion of IDLeak, regarding to the same die area, geometric factor and bias and temperature conditions. So, these results show that also it is possible to analyze and investigate the behavior of devices at high temperatures, through three-dimensional numerical simulations, in order to predict its performance in harsh environments before submit them in such real operation conditions, and thus, even get additional information to improve the design/performance of the ICs in harsh temperature conditions. Therefore, Diamond layout style IDLeak (35 pA and 228 pA for equals to 127o and 53o, respectively) presents practically the same magnitude order than the one observed in the CSM counterpart (67 pA and 28 pA for equals to 127o and 53o, respectively) at 300 oC and therefore when it is used DSM instead of the conventional one, Diamond structure does not degrade the performance the battery time life of the portable electronics equipment operating in harsh (high temperature) environments.
