**4. The TIARA-G4 Monte Carlo simulation code**

This section describes in details the TIARA-G4 code developed these last years conjointly at Aix-Marseille University (IM2NP laboratory) and at STMicroelectronics (Central R&D, Crolles). TIARA-G4 is a general-purpose Monte Carlo simulation code written in C++ and fully based on the Geant4 toolkit for modeling the interaction of Geant4 particles (including neutrons, protons, muons, alpha-particles and heavy ions) with various architectures of electronic circuits. TIARA stands for Tool Suite for Radiation Reliability Assessment. The primary ambition of TIARA is to embed in a unique simulation platform the state-of-the-art knowledge and methodology of SER evaluation.

The initial version of TIARA [26-27] was a standalone C++ native code dynamically linked with IC CAD flow through the coupling with a SPICE solver. The code has been developed such that the addition of new radiation environments, physical models or new circuit architecture should be quite simple. On one hand, this first version was able to treat the

transport and energy deposition of charged particles (heavy ions and alpha particles) without the need for a nuclear code as Geant4 [28]; only SRIM [29] tables were used as input files to compute the transport of the particles in silicon and in a simplified Back-End-Of-Line (BEOL) structure reduced to a single layer. On the other hand, for neutrons, it used separate databases compiled using a specific Geant4 application to generate nuclear events in the simulation flow resulting from the interactions of incident neutrons with the circuit.

Soft-Error Rate of Advanced SRAM Memories: Modeling and Monte Carlo Simulation 317

The first step of the TIARA-G4 simulation is to construct a model of the simulated circuit from Geant4 geometry classes and libraries of elements and materials. In the framework of Geant4, the circuit under simulation is considered as the "particle detector". The structure creation in TIARA is based on 3D circuit geometry information extracted from GDS formatted data classically used in the Computer-Aided Design (CAD) flow of semiconductor circuit manufacturing. To perform such an extraction from the GDS layout description, a separate tool has been developed [30]. It parses the GDS file, obtains coordinate points of CAD layers and using geometrical computations tracks the positions and dimensions of the transistor active areas, cell dimensions, p-type and n-type and Back-End-Of-Line (BEOL) stack geometry. Based on this information and additional data concerning the depth of the wells, junctions, STI regions (obtained from TCAD or SIMS measurements) and BEOL layer composition, TIARA creates a 3D structure of the elementary memory cell and, by repetition, of the complete portion of the simulated circuit. The real 3D geometry is simplified since it is essentially based on the juxtaposition of boxes of different dimensions, each box being associated to a given

material (silicon, insulator, metal, etc.) or doped semiconductor (p-type, n-type).

**Figure 5.** Left and Center**:** ROOT screenshots illustrating the geometry of the complete 65 nm SRAM architecture considered in TIARA-G4 simulation. Right: 3D perspective view of a 10×20 SRAM cell

Figure 5 (left) illustrates the geometry of a complete 65 nm SRAM architecture considered in TIARA-G4 simulation. Sensitive Pmos and Nmos drains regions are connected to the first metal layer (Cu) of the BEOL stack with tungsten plugs. The BEOL structure is composed of 18 uniform stacked layers with exact compositions and thicknesses. The 3D perspective

array covered with the BEOL.

**4.1. Circuit architecture construction module** 

The new version of TIARA, described here, is called TIARA-G4, in reference to the fact that it is totally rewritten in C++ using Geant4 classes and libraries and compiled as a full Geant4 application [28]. The main improvement of TIARA-G4 with respect to the first version of the code comes precisely from this transformation of the code in a Geant4 application, allowing the use of Geant4 classes for the description of the circuit geometry and materials (now including the true BEOL structure) and the integration of the particle transport and tracking directly in the simulation flow, without the need of external databases or additional files. Figure 4 shows a schematics of the TIARA-G4 simulation flow structured in several independent modules. In the following, we present the content of the main modules of the code and illustrate (also in Section 5) their capabilities for the soft error rate evaluation of different SRAM CMOS bulk circuits (65 nm and 40 nm technologies) subjected to natural radiation at ground level.

**Figure 4.** Schematics of the TIARA-G4 simulation flow showing the different code inputs and outputs and the links with Geant4 classes, libraries, models or external modules and visualization tools.
