**3. Three-dimensional simulations results**

The ATLAS (Device Simulation Software) [9] was used to perform the 3D numerical simulations of the Diamond and Conventional SOI nMOSFETs. The curves of IDS versus gate voltage (VGS) and IDS versus drain voltage (VDS) were obtained. Based on these curves, the main parameters of these devices were extracted and compared in order to verify the advantages and disadvantages of the Diamond layout style in relation to the conventional one counterpart.

Basically, the ATLAS device simulator uses two files inputs: the first one is the text file that contains commands for the ATLAS. Usually, these commands are to include a file that define the devices structure (usually built by using DevEdit3D [8]), to define the dimensions, the terminals and the meshof the structure of the device. The second one is responsible to define the physic phenomenon models (mobility, band width, impact ionizations, etc), the solution methods and the bias commands of the terminals that must be taking in account in the simulation of the device [1].

Besides that, ATLAS generates three types of output files. The first one is the "run-time output file" that provides all the error and warning messages. The second one is the "log files", which store allterminal voltages and currents of the device [direct current (DC), small signal alternate current (AC) and transient] generated the command SOLVE. This last file can be seen with the TonyPlot (visualization tool) to visualize the electrical behavior of the device. The last one is the "solution files", and it is responsible to stores the two-dimensional and three-dimensionaldata of the solution variables within the device for a single bias point (electric field, potential, etc.). This last file can be visualized by the use of TonyPlot too [1].

278 Numerical Simulation – From Theory to Industry

**2. Devices used to perform the study** 

**Table 1.** Devices Dimensions used to the study.

**3. Three-dimensional simulations results** 

taking in account in the simulation of the device [1].

and bias conditions.

Synopsys, Inc [9].

one counterpart.

by "Variable Channel Lengths of Transistors Associated in Parallel Effect" (VACLETAPE). So, in the Diamond structure occurs two effects at the same time, i.e., the LCE and the VACLETAPE generating a Diamond drain current higher than the one observed in the conventional (rectangular) SOI nMOSFET counterpart, regarding the same gate area (AG)

So, in order to qualify and quantify the benefits of Diamond layout style to improve the transistor performance, it were implemented three pairs of SOI nMOSFETs, being three Diamond transistors with different α angles and other three conventional SOI nMOSFETs counterparts, regarding the same gate area (AG). Table I presents the devices dimensions used to implement these devices in the DevEdidt3D from (TCAD/Silvaco Inc) [8]. A similar TCAD to implement devices is the Sentaurus Structure Editor of the

Conventional SOI nMOSFET Diamond SOI nMOSFET # W (µm) L (µm) W/L # b (µm) B (µm) (o) CSM1 6.0 7.0 0.86 DSM1 1.0 13.0 53.1 CSM2 6.0 4.0 1.50 DSM2 1.0 7.0 90.0 CSM3 6.0 2.5 2.40 DSM3 1.0 4.0 126.9

The constructive characteristics of these devices are: gate-oxide (tox), silicon-film (tSI) and buried-oxide (tBOX) thickness are 2 nm, 100 nm and 400 nm, respectively, and drain/source

The ATLAS (Device Simulation Software) [9] was used to perform the 3D numerical simulations of the Diamond and Conventional SOI nMOSFETs. The curves of IDS versus gate voltage (VGS) and IDS versus drain voltage (VDS) were obtained. Based on these curves, the main parameters of these devices were extracted and compared in order to verify the advantages and disadvantages of the Diamond layout style in relation to the conventional

Basically, the ATLAS device simulator uses two files inputs: the first one is the text file that contains commands for the ATLAS. Usually, these commands are to include a file that define the devices structure (usually built by using DevEdit3D [8]), to define the dimensions, the terminals and the meshof the structure of the device. The second one is responsible to define the physic phenomenon models (mobility, band width, impact ionizations, etc), the solution methods and the bias commands of the terminals that must be

and channel doping concentrations are 5.5x1017 cm-3 and 1x1020 cm-3, respectively.

The following models are used to perform the 3D numerical simulations of the devices: I. Lombardi's vertical and horizontal electric-field-dependent mobility model, which includes effects of low (surface acoustic phonon scattering, optical inter-valley scattering and surface roughness) and high (Thonber's drift velocity model to calculate the velocity saturation) electric field; II. The Aurora model takes into account mobility degradation due to the lattice temperature; III. The Fowler-Nordheim Tunneling (electron and holes) model considersthe tunneling of electrons from the semiconductor Fermi level into the insulator conduction band, when high electric field across the gate is applied; IV. The Lucky-Electron Hot Carrier Injection model, considers the electrons emissions into the oxide by first gaining enough energy from the electric field in the channel to surmount the insulator/semiconductor barrier [1].

Figure 3 presents the three-dimensional numerical (3D) simulations results of the DSMs and CSMs IDS as a function of VGS,for VDS equal to 10 mV (Triode Region).

**Figure 3.** Curves of three-dimensional numerical simulations of the IDS as a function of VGS for VDS=10mV.

In Figure 3, IDS\_=127o, IDS\_=90o and IDS\_=53o are respectively the differences between the IDS of the DSMs with different angles (127o, 90o and 53o) and the respective CSMs counterparts.

Using Numerical Simulations to Study and Design Semiconductors Devices in Micro and Nanoelectronics 281

Figure 5 presents the three-dimensional numerical (3D) simulations results of DSM (=53o) and CSM counterpart Log(IDS) as a function of gate voltage (VGS),for drain voltage (VDS)

**Figure 5.** Curves of three-dimensional numerical simulations of DSM (α=53o) and CSM Log(IDS) as a

Analyzing Figure 5, we can see that the subthreshold slopes (S) from of the both devices are practically similar around 60 mV/decade. Similar results are found to the others devices

Figure 6 presents IDS as a function of VDS with VGS equal to 0.4 V in the saturation region to DSM with angles equals to 127o (Figure 6.a), 90o (Figure 6.b) and 53o (Figure 6.c)

Analyzing Figure 6, it is possible toobserve that always the IDS in saturation region (IDSsat) of all DSMs with different angles are higher than those found in the CSMs counterpart, considering the same AG, geometric factor and bias conditions. Besides that, IDS of DSMs with angles equals to 127o, 90o and 53o is higher 27%, 52% and 284% (1.84 times) than those observed in CSMs counterparts. This can be justified because of LCE and VACLETAPE effects present in the Diamond structure. Additionally, itcan see that DSMs Early voltages (VEA) are strongly degraded in relation to CSMs counterparts, due to the high resultant longitudinal electric field in the drain region of the Diamond structures, as for example, DSM (=53o) VEA is approximately equal to 5V while CSM counterpart VEA is approximately equal to 36V (around seven times smaller) and

therefore can limit the use of this device to the output stages of analog ICs.

equal to 10 mV.

function of VGS for VDS=10 mV.

studied.

respectively.

By analyzing the Figure 3, considering the same AG and bias conditions in the Triode Region, it can be observe that DSMs IDS with angles equals to 127o, 90o and 53o are respectively 20.3 %, 37.2 % and 126.5 % (2.26 times) higher than those observed in the CSMs counterparts and these differences decreaseswhile the DSM angle increases, due the two effects existents in the Diamond SOI nMOSFET (LCE and VACLETAPE). So, this innovative layout style can be used to increase the fun-out and fun-in capability of the logic gates.

Figure 4 presents the three-dimensional numerical (3D) simulations results of the DSMs and CSMs gm as a function of gate voltage (VGS),for drain voltage (VDS) equal to 10 mV.

**Figure 4.** Curves of three-dimensional numerical simulations of the gm as a function of VGS for VDS=10 mV (Triode Region).

In Figure 4, gm\_=127o, gm\_=90o and gm\_=53o are respectively the differences between the gm of DSMs with different angles (127o, 90o and 53o) and the respective CSMs counterparts.

Basing on Figure 4, we can see that, DSMs gm with angles equals to 127o, 90o and 53o are respectively 20.5 %, 47.6 % and 122.9 % (around 2.23 times) higher than those verified in the CSM counterparts and these differences also decreaseswhile DSM angle increases, due the LCE and VACLETAPE,considering the same AG and bias conditions.So, this Diamond structures can be used to improve significantly the voltage gain (AV) and unit voltage gain frequency (fT) of the amplifiers used in analog ICs.

Figure 5 presents the three-dimensional numerical (3D) simulations results of DSM (=53o) and CSM counterpart Log(IDS) as a function of gate voltage (VGS),for drain voltage (VDS) equal to 10 mV.

280 Numerical Simulation – From Theory to Industry

counterparts.

mV (Triode Region).

frequency (fT) of the amplifiers used in analog ICs.

In Figure 3, IDS\_=127o, IDS\_=90o and IDS\_=53o are respectively the differences between the IDS of the DSMs with different angles (127o, 90o and 53o) and the respective CSMs

By analyzing the Figure 3, considering the same AG and bias conditions in the Triode Region, it can be observe that DSMs IDS with angles equals to 127o, 90o and 53o are respectively 20.3 %, 37.2 % and 126.5 % (2.26 times) higher than those observed in the CSMs counterparts and these differences decreaseswhile the DSM angle increases, due the two effects existents in the Diamond SOI nMOSFET (LCE and VACLETAPE). So, this innovative layout style can be used to increase the fun-out and fun-in capability of the logic gates.

Figure 4 presents the three-dimensional numerical (3D) simulations results of the DSMs and

**Figure 4.** Curves of three-dimensional numerical simulations of the gm as a function of VGS for VDS=10

In Figure 4, gm\_=127o, gm\_=90o and gm\_=53o are respectively the differences between the gm of DSMs with different angles (127o, 90o and 53o) and the respective CSMs counterparts.

Basing on Figure 4, we can see that, DSMs gm with angles equals to 127o, 90o and 53o are respectively 20.5 %, 47.6 % and 122.9 % (around 2.23 times) higher than those verified in the CSM counterparts and these differences also decreaseswhile DSM angle increases, due the LCE and VACLETAPE,considering the same AG and bias conditions.So, this Diamond structures can be used to improve significantly the voltage gain (AV) and unit voltage gain

CSMs gm as a function of gate voltage (VGS),for drain voltage (VDS) equal to 10 mV.

**Figure 5.** Curves of three-dimensional numerical simulations of DSM (α=53o) and CSM Log(IDS) as a function of VGS for VDS=10 mV.

Analyzing Figure 5, we can see that the subthreshold slopes (S) from of the both devices are practically similar around 60 mV/decade. Similar results are found to the others devices studied.

Figure 6 presents IDS as a function of VDS with VGS equal to 0.4 V in the saturation region to DSM with angles equals to 127o (Figure 6.a), 90o (Figure 6.b) and 53o (Figure 6.c) respectively.

Analyzing Figure 6, it is possible toobserve that always the IDS in saturation region (IDSsat) of all DSMs with different angles are higher than those found in the CSMs counterpart, considering the same AG, geometric factor and bias conditions. Besides that, IDS of DSMs with angles equals to 127o, 90o and 53o is higher 27%, 52% and 284% (1.84 times) than those observed in CSMs counterparts. This can be justified because of LCE and VACLETAPE effects present in the Diamond structure. Additionally, itcan see that DSMs Early voltages (VEA) are strongly degraded in relation to CSMs counterparts, due to the high resultant longitudinal electric field in the drain region of the Diamond structures, as for example, DSM (=53o) VEA is approximately equal to 5V while CSM counterpart VEA is approximately equal to 36V (around seven times smaller) and therefore can limit the use of this device to the output stages of analog ICs.

Using Numerical Simulations to Study and Design Semiconductors Devices in Micro and Nanoelectronics 283

The on-state series resistance (RDS\_on) can be extracted from the Figure 6 in the linear region of the triode region. So, notice that, DSMs with different angles RDS\_on are always higher than those observed in CSMs counterparts, as for example, DSM (=53o) RDS\_on is around 82% (6 K) smaller than the one found in CSM counterpart (110 K) and therefore, by using DSM counterpart instead CSM, we can improve significantly the processing clock velocity of

In order to understand the electrical and physical behavior of the Diamond structure in relation the to conventional one counterpart, the longitudinal electrical field vectors picture was extracted of DSM ( =90o) and CSM counterpart structures, regarding VGS and VDS

equals to 0.4 V and 1.2 V, respectively, in saturation region, as illustrated in Figure 7.

**Figure 7.** Vectors of the resultant longitudinal electric field of the DSM (=90o) (Figure 7.a) and CSM counterpart (Figure 7.b) channel regions for VGS and VDS equal to 0.4 V and 1.2 V, respectively

(a) (b)

With the use of TonyPlot3D (Silvaco Inc.) [1] and analyzing Figure 7, it is possible to see

channel region edges (1.5x106 V/cm) is smaller than the one found in the center of the channel from of the middle of the channel length (2.0x106 V/cm), due to the smaller

edges regions. Besides that, it can beverify that DSM ( =90o) average resultant longitudinal electric field (1.9x106 V/cm) is higher than the one observed in CSM counterpart (1.2.104

//

//2

 //1 and ) along of the

 // ) in the

) next to DSM

how is the behavior of DSM ( =90o) resultant longitudinal electric field (

interaction between the longitudinal electric field components (

channel length. Notice that, DSM ( =90o) resultant longitudinal electrical field (

V/cm), due to the presence of LCE and VACLETAPE in the Diamond structure.

digital ICs.

(saturation region).

**4. Electrical and physical analysis** 

**Figure 6.** Curves of three-dimensional numerical simulations of IDS as a function of VDS for VGS=0.4 V (saturation region) for DSMs with different α angles [127o (Figure 6.a), 90o (Figure 6.b) and 53o (Figure 6.c)and CSMs counterparts.

The on-state series resistance (RDS\_on) can be extracted from the Figure 6 in the linear region of the triode region. So, notice that, DSMs with different angles RDS\_on are always higher than those observed in CSMs counterparts, as for example, DSM (=53o) RDS\_on is around 82% (6 K) smaller than the one found in CSM counterpart (110 K) and therefore, by using DSM counterpart instead CSM, we can improve significantly the processing clock velocity of digital ICs.
