**Author details**

286 Numerical Simulation – From Theory to Industry

for all equivalent devices, i.e., for = 53o and 127o.

1E-14

1E-13

1E-12

1E-11

IDLeak/(W/L) [A]

the one present in its CSM counterpart.

**7. Conclusions** 

1E-10

1E-9

1E-8

From Figure 10, it is possible to observe that, as the temperature increases, IDLeak also increases, as expected [11]. Besides that, IDLeak is higher in DSM when compared to CSM devices, independently of the angle and the temperature. It happens since the longitudinal electric field is higher in DSM when compared to CSMs and consequently, its drain leakage current (IDLeak) is also larger. On the other hand, it worthwhile to describe that as reduces, IDLeak difference observed between both devices becomes higher. As for example, when is equal to 127o, DSM IDLeak is 20% higher than the one observed in the CSM counterpart (L= 2.5µm) for VGS=-0.5 V, but providing an IDS also 20% more than rectangular gate transistor, for VGS=1.2V. These increasing proportions between IDLeak and drain currents are maintained

Figure 11 shows DSM IDLeak behavior as a function of the angle α. It is important to comment that this comparison is possible once IDLeak is normalized with the geometric factor (W/L), thus providing a more realistic comparison of IDLeak as α changes. Then, analyzing the results it is possible to observe that, for the same temperature, as α increase, IDLeak becomes smaller.

50 60 70 80 90 100 110 120 130

(degrees)

Anyway, for both CSM and DSM, IDLeak increases when the temperature increases in the same proportion,mainly due to the thermal generation process [15], but in DSM IDLeak is higher because the longitudinal electric field along the DSM channel length is higher than

Comparative studies between Diamond SOI MOSFETs and Conventional ones counterparts by numerical simulations demonstrate that Diamond layout style can improve current drive, transconductance, on-state series resistance, frequency response (voltage gain and unit voltage gain frequency) when it is compared to the Conventional counterpart,

considering the same gate area, geometry factor (aspect ratio) and bias conditions.

 100oC 200oC 300oC

Otherwise, for the same α, IDLeak also increases according to the temperature rises.

VDS=0.1V VGS=-0.5V

**Figure 11.** Diamond SOI nMOSFET IDLeak behavior as a function of α, at high temperatures.

Salvador Pinillos Gimenez and Marcello Bellodi *Department of Electrical Engineering, Centro Universitário da FEI (FEI), São Bernardo do Campo, São Paulo, Brazil* 
