**2.1. Determination of the potential under the gate**

The potential distribution in the active layer under the gate is modeled by solving the Poisson's equation with proper boundary conditions, in two-dimensions this equation is given by:

$$
\Delta\Psi(\mathbf{x},\mathbf{y}) = \frac{\hat{c}^2\nu(\mathbf{x},\mathbf{y})}{\hat{c}\mathbf{x}^2} + \frac{\hat{c}^2\nu(\mathbf{x},\mathbf{y})}{\hat{c}\mathbf{y}^2} = -\frac{\rho(\mathbf{x},\mathbf{y})}{\varepsilon} \tag{1}
$$

where *ψ(x, y)* is the potential in the active-layer.

*ρ (x, y)* is the density of the majority carriers in the channel.

*ε* is the dielectric permittivity of semiconductor.

If the channel doping is homogeneous, the activity area density is written

$$
\rho(\mathbf{x}, \mathbf{y}) = \rho(\mathbf{y}) = eN\_d(\mathbf{y}) \tag{2}
$$

where *Nd(y)* is the doping profile in semiconductor.

To simplify the study, one considers that this equation is a superposition of two simple equations. In this connection, one can write:

Analytical Model and Numerical Simulation

for the Transconductance and Drain Conductance of GaAs MESFETs 261

$$
\varphi(\mathbf{x}, \mathbf{y}) = \mathcal{L}(\mathbf{y}) + \varphi(\mathbf{x}, \mathbf{y}) \tag{3}
$$

where

260 Numerical Simulation – From Theory to Industry

described by Chang and Day (1989).

used some assumptions and approximations.

**2.1. Determination of the potential under the gate** 

*ρ (x, y)* is the density of the majority carriers in the channel.

(,) () () *<sup>d</sup>*

where *Nd(y)* is the doping profile in semiconductor.

equations. In this connection, one can write:

If the channel doping is homogeneous, the activity area density is written

where *ψ(x, y)* is the potential in the active-layer.

*ε* is the dielectric permittivity of semiconductor.

according to the electric field.

dimensional analysis.

iterative method.

simulation methods.

given by:

**2. Analytical model**

with the physical phenomena specific to this device.

references to solved the two dimensional Poisson's equation, this technique gives an acceptable distribution of the space charge and a form of the depletion area in agreement

To determine the depletion-layer width, we have considered first the one-dimensional approximation (Sze and Ng, 2007), then we add the corrective which results from the two-

To determine the electron mobility law in the semiconductor, we have considered that

To calculate the drain current expression as a function of the drain-source and gate-source voltages, we divided the channel under the gate in regions (linear, non-linear and saturated)

In order to simplify the mathematical study and consequently the numerical simulation, we

To determine the *I-V* extrinsic characteristics in different operations regimes, we used the

To determine the transconductance and drain conductance as a function of the drain-source and gate-source voltages in different operations regimes, we based also for the numerical

The potential distribution in the active layer under the gate is modeled by solving the Poisson's equation with proper boundary conditions, in two-dimensions this equation is

> 2 2 (,) (,) (,) (,) *xy xy xy x y x y*

(1)

*x y y eN y* (2)

2 2

 

To simplify the study, one considers that this equation is a superposition of two simple

$$\mathcal{L}I(y) = \iint \frac{-eN\_d(y)}{\varepsilon} dy^2 \tag{4}$$

and

$$
\frac{
\partial^2 \phi
\left(\mathbf{x}, \mathbf{y}\right)
}{
\partial \mathbf{x}^2
} + \frac{
\partial^2 \phi
\left(\mathbf{x}, \mathbf{y}\right)
}{
\partial \mathbf{y}^2
} = 0
\tag{5}
$$

In such a way, according to formula (3 – 5) the process of solving the initial Poisson's equation consists of looking-for of solution to one-dimensional equation (Eq. 4) and solving the two-dimensional equation (Eq. 5).

#### **2.2. Boundary conditions**

The above solution of the Poisson's equation has to verify the equations and boundary conditions expressed as:

$$
\psi(x,0) = 0\tag{6}
$$

$$
\psi(\mathbf{0}, \mathbf{y}) = V\mathbf{b} - V\mathbf{g} \tag{7}
$$

$$
\psi(L, y) = Vd + Vb - Vg \tag{8}
$$

where *Vg* is the intrinsic gate-source voltage, *Vd* is the intrinsic drain-source voltage and *Vb* is the built-in voltage of the Schottky barrier.

If the drain voltage is equal to zero, the symmetry between the two gate-sides leads to the following condition:

$$\left. \psi \left( 0, y \right) \right|\_{Vd=0} = \left. \psi \left( L, y \right) \right|\_{Vd=0} \tag{9}$$

At the first point of the pinch-off, the electron velocity attains its maximum and the electric field with drain side's corresponds to the saturation field *ES*.

$$\left.\frac{\partial \,\nu(\mathbf{x},\mathbf{y})}{\partial \mathbf{x}}\right|\_{\{L,a\}} = E\_{\\$} \tag{10}$$

The electric field must vanish in the depletion-layer edges at both gate-sides; this field may cause a large current flow. Therefore, it may be written:

$$\left.E\_{\vec{n}}\right|\_{\mathcal{S}} = \mathbf{0} \tag{11}$$

and

$$\left.E\_{\vec{n}}\right|\_{D} = 0\tag{12}$$

and

Analytical Model and Numerical Simulation

(20)

(21)

(25)

(26)

(27)

for the Transconductance and Drain Conductance of GaAs MESFETs 263

1/2

1 11 1 *<sup>D</sup> Vd Vb Vg A Vp a b <sup>c</sup>*

source and drain sides of the gate respectively.

**2.5. Depletion-layer width** 

*a1*, *b1* and *c1* are constants related to the device structure.

From (13) and (17), one obtains the expression of total tension *ψ (x, y)*:

dimensional analysis. So the Eqs. (14 ~ 16) becomes respectively as follows:

*X*

*S*

 <sup>1</sup> <sup>1</sup> 1 1

*D*

where the correctives are determinate by:

*AS1* and *AD1* are the first term of Fourier coefficient for the excess sidewall potential at the

 

sinh ( ) sinh (,) () sin 2 sinh sinh *<sup>d</sup> S D eN kL x k x xy h x A <sup>A</sup> k y k L k L*

To calculate the two dimensional width of the depletion layer formed by the Schottky barrier *WX* at any *x* coordinate, we have considered firstly the one-dimensional approximation *hX* then we have added the corrective which results with the two-

*V x Vb Vg x h <sup>W</sup>*

*Vb Vg h <sup>W</sup>*

*Vd Vb Vg L h <sup>W</sup>*

1 1 sinh sinh . ( ) ,() sin sinh( ) sinh( ) 2 *S D kLx k x Vb Vg V x xhx A <sup>A</sup>*

*Vb Vg h A*

*Vd Vb Vg Lh A*

 <sup>1</sup> 0, sin <sup>2</sup> *S*

*S*

 <sup>1</sup> , sin <sup>2</sup> *D*

*D*

 <sup>2</sup> 1 1 1 11 1 1

2 () (, ) *<sup>X</sup>*

*eN*

2 (0, ) *<sup>S</sup>*

*eN*

*d*

2 (, ) *<sup>D</sup>*

*eN*

*d*

 

 

*k L k L Vp*

*Vp*

*Vp*

 

*d*

 

(22)

(23)

(24)

*Vp* 

where *n* is the outward unit vector at the depletion-layer edge.

#### **2.3. 1D approximation**

By integrating the equation (4) from *0* to *h (x)*, we determine the term *U (y)*, and one obtains:

$$\text{LU}(h) = \frac{eN\_d}{2\varepsilon}h(\mathbf{x})^2\tag{13}$$

The one-dimensional depletion layer width *hX* at any *x* coordinate is given by the one-sided abrupt junction depletion approximation (Sze and Ng, 2007).

$$h\_X = \sqrt{\frac{2\varepsilon \left(V(\mathbf{x}) + Vb - Vg\right)}{eN\_d}}\tag{14}$$

where *V(x)* is the potential of the neutral channel with *V(0) = 0* at the source-end and *V(L) = Vd* at the drain-end. So that the one-dimensional depletion widths at the source and drain ends given respectively by:

$$h\_S = \sqrt{\frac{2\varepsilon \left(Vb - Vg\right)}{eN\_d}}\tag{15}$$

$$h\_D = \sqrt{\frac{2\varepsilon \left(Vd + Vb - V\mathbf{g}\right)}{eN\_d}}\tag{16}$$

#### **2.4. 2D analytical model**

To determine the second term, we based for the works Chin and Wu (1992, 1993), Jit et al. (2003, 2011) and Morarka and Mishra. (2005), these studies are used the Green's functions and superposition techniques. In the homogeneous medium, the solution suggested is written in the following form:

$$\varphi(\mathbf{x}, y) = \left[ A\_1^S \frac{\sinh\left(k\_1(L-\mathbf{x})\right)}{\sinh\left(k\_1 L\right)} + A\_1^D \frac{\sinh\left(k\_1 \mathbf{x}\right)}{\sinh\left(k\_1 L\right)} \right] \sin\left(k\_1 y\right) \tag{17}$$

where

$$k\_1 = \frac{\pi}{2a} \tag{18}$$

$$A\_1^S = Vp \left[ a\_1 + b\_1 \left( \frac{Vb - V\_\mathcal{S}}{Vp} - c\_1 \right)^{1/2} \right] \tag{19}$$

and

262 Numerical Simulation – From Theory to Industry

**2.3. 1D approximation** 

ends given respectively by:

**2.4. 2D analytical model** 

written in the following form:

where

is the outward unit vector at the depletion-layer edge.

abrupt junction depletion approximation (Sze and Ng, 2007).

*X*

*S*

*D*

By integrating the equation (4) from *0* to *h (x)*, we determine the term *U (y)*, and one obtains:

<sup>2</sup> () () <sup>2</sup> *<sup>d</sup> eN Uh hx* 

The one-dimensional depletion layer width *hX* at any *x* coordinate is given by the one-sided

*V x Vb Vg <sup>h</sup> eN*

where *V(x)* is the potential of the neutral channel with *V(0) = 0* at the source-end and *V(L) = Vd* at the drain-end. So that the one-dimensional depletion widths at the source and drain

> *Vb Vg <sup>h</sup> eN*

*Vd Vb Vg <sup>h</sup> eN*

To determine the second term, we based for the works Chin and Wu (1992, 1993), Jit et al. (2003, 2011) and Morarka and Mishra. (2005), these studies are used the Green's functions and superposition techniques. In the homogeneous medium, the solution suggested is

 

sinh ( ) sinh (,) sin sinh sinh *S D kL x k x xy A <sup>A</sup> k y k L k L*

 

> <sup>1</sup> 2 *k*

1 11 1 *<sup>S</sup> Vb Vg A Vp a b <sup>c</sup>*

*a* 

*Vp* 

2 ()

2

*d*

2

*d*

*d*

where *n*  <sup>0</sup> *<sup>n</sup> <sup>D</sup> <sup>E</sup>* (12)

(13)

(14)

(15)

(16)

1/2

(18)

(17)

(19)

1 1

1 11 1 1

$$A\_1^D = Vp\left[a\_1 + b\_1\left(\frac{Vd + Vb - Vg}{Vp} - c\_1\right)^{1/2}\right] \tag{20}$$

*AS1* and *AD1* are the first term of Fourier coefficient for the excess sidewall potential at the source and drain sides of the gate respectively.

*a1*, *b1* and *c1* are constants related to the device structure.

From (13) and (17), one obtains the expression of total tension *ψ (x, y)*:

$$\psi(\mathbf{x},y) = \frac{eN\_d}{2\varepsilon}h^2(\mathbf{x})\left[A\_1^S \frac{\sinh\left(k\_1(L-\mathbf{x})\right)}{\sinh\left(k\_1L\right)} + A\_1^D \frac{\sinh\left(k\_1\mathbf{x}\right)}{\sinh\left(k\_1L\right)}\right] \sin\left(k\_1y\right) \tag{21}$$

#### **2.5. Depletion-layer width**

To calculate the two dimensional width of the depletion layer formed by the Schottky barrier *WX* at any *x* coordinate, we have considered firstly the one-dimensional approximation *hX* then we have added the corrective which results with the twodimensional analysis. So the Eqs. (14 ~ 16) becomes respectively as follows:

$$\mathcal{W}\_{\mathbf{X}} = \sqrt{\frac{2\varepsilon \left(V(\mathbf{x}) + Vb - V\mathbf{g} - \varrho(\mathbf{x}, h\_{\mathbf{X}})\right)}{eN\_d}} \tag{22}$$

$$\mathcal{W}\_{\mathcal{S}} = \sqrt{\frac{2\varepsilon \left(Vb - V\mathcal{g} - \varphi(0, h\_{\mathcal{S}})\right)}{eN\_d}}\tag{23}$$

$$\mathcal{W}\_{D} = \sqrt{\frac{2\varepsilon \left( Vd + Vb - Vg - \phi(L, h\_{D}) \right)}{eN\_{d}}} \tag{24}$$

where the correctives are determinate by:

$$\log\left(\mathbf{x}, h(\mathbf{x})\right) = \left[A\_1^S \frac{\sinh\left(k\_1\left(L-\mathbf{x}\right)\right)}{\sinh(k\_1L)} + A\_1^D \frac{\sinh\left(k\_1\mathbf{x}\right)}{\sinh(k\_1L)}\right] \sin\left(\frac{\pi}{2}\sqrt{\frac{Vb - Vg + V\left(\mathbf{x}\right)}{Vp}}\right) \tag{25}$$

$$\log\left(0, h\_S\right) = A\_1^S \sin\left(\frac{\pi}{2}\sqrt{\frac{Vb - Vg}{Vp}}\right) \tag{26}$$

$$\log\left(L\_{\prime}h\_{D}\right) = A\_{1}^{D}\sin\left(\frac{\pi}{2}\sqrt{\frac{Vd + Vb - Vg}{Vp}}\right) \tag{27}$$

and the pinch-off voltage:

$$Vp = \frac{eN\_d}{2\varepsilon}a^2\tag{28}$$

Analytical Model and Numerical Simulation

for the Transconductance and Drain Conductance of GaAs MESFETs 265

(36)

*<sup>a</sup>* (37)

*<sup>a</sup>* (38)

<sup>3</sup> *DS DS Id Ip u u u u* (35)

22 33 <sup>2</sup>

22 3 ( ) 2 *Zq N E a <sup>d</sup> Ip <sup>L</sup>* 

*D*

*S*

*W*

The mobility law makes it possible to obtain the different expressions of the drain-current in the different operation regimes (linear, non-linear and saturated). Fig. 1 shows the structure of a MESFET with the channel under the gate. It can be divided in general into three regions (*LA*, *LB* and *LC*) depending upon the magnitude of the electric field (Shin and Klemer, 1992; Khemissi et al. 2004, 2006). In the region *LA* the electric field is below *E0*, and the electron mobility is given by equation (29), region *LB* correspond the electric field is between *E0* and *ES* and the electron mobility is given by equation (30), the last *LC* is the high field region in which the electric field exceeds *ES* and the mobility is given by

*Lg* 

*Source Gate Drain* 

*Wa* 

*a* 

This regime exists when the applied drain-source voltage is sufficiently low such that the electrical field under the gate is both smaller than *E0*, the mobility is equal to *µ0* and the channel is described by *LA*. The expression of the drain current in this regime is given by:

*LA LB LC*

*D*

*S*

*u*

*u*

*W*

By simple integration, *Id* becomes as:

*uD* and *uS* are the normalized dimensionless units.

**Figure 1.** A cross-sectional view of a biased MESFET channel

*Ws* 

*x* 

*y* 

where

equation (30).

**2.8. Linear regime** 

#### **2.6. The electron mobility law**

For gallium arsenide GaAs, the analytical expression of the electron mobility dependence of the electric field which used in this study is a simplified mathematical relation (Chang and Day, 1989; Shin and Klemer 1992) given as follows:

For the feeble electric fields where *E E0*, the electrons are in thermodynamic balance with their mobility, the later is constant and independent of the electric field, in this connection:

$$
\mu(E) = \mu\_0 \tag{29}
$$

As the electric field becomes more growth where *E E0* the interactions of the carriers with the vibrations of the network involve a reduction in the mobility of the electrons. The law of this mobility in this case is given by:

$$\mu(E) = \frac{\mu\_0}{\left[1 + \left(\frac{E - E\_0}{E\_C}\right)^2\right]^{\frac{1}{2}}}\tag{30}$$

where

$$E\_{\mathbb{C}} = \frac{\upsilon\_{\mathbb{S}}}{\mu\_0} \tag{31}$$

$$E\_0 = \frac{1}{2} \left[ E\_S + \left( E\_S^2 - 4E\_C^2 \right)^{\frac{1}{2}} \right] \tag{32}$$

$$\left. \frac{dv(E)}{dE} \right|\_{E=E\_S} = 0\tag{33}$$

#### **2.7. I-V caractéristics**

In general, it is possible that the channel current is expressed as a function of the intrinsic grille-source and drain-source voltages in terms of physical dimensions. The basic equation used to derive the *I-V* relationship (Sze and Ng, 2007) is given by:

$$Id = \frac{Zq^2 N\_d^2 \mu(E)}{\varepsilon L} \int\_{\mathcal{W}\_S}^{\mathcal{W}\_D} \left(a - \mathcal{W}\right) \mathcal{W} d\mathcal{W} \tag{34}$$

By simple integration, *Id* becomes as:

$$Id = Ip \left[ \left( \mu\_D^2 - \mu\_S^2 \right) - \frac{2}{3} \left( \mu\_D^3 - \mu\_S^3 \right) \right] \tag{35}$$

where

264 Numerical Simulation – From Theory to Industry

**2.6. The electron mobility law** 

For the feeble electric fields where *E* 

this mobility in this case is given by:

where

**2.7. I-V caractéristics** 

Day, 1989; Shin and Klemer 1992) given as follows:

As the electric field becomes more growth where *E* 

2

(28)

 *E0*, the electrons are in thermodynamic balance with

( ) *E µ* (29)

*<sup>µ</sup>* (31)

(33)

 *E0* the interactions of the carriers with

(30)

(32)

2 *<sup>d</sup> eN Vp a* 

For gallium arsenide GaAs, the analytical expression of the electron mobility dependence of the electric field which used in this study is a simplified mathematical relation (Chang and

their mobility, the later is constant and independent of the electric field, in this connection:

the vibrations of the network involve a reduction in the mobility of the electrons. The law of

1

*C <sup>v</sup> <sup>E</sup>*

<sup>1</sup> <sup>4</sup> <sup>2</sup> *SS C E EE E*

> ( ) <sup>0</sup> *<sup>S</sup> E E*

In general, it is possible that the channel current is expressed as a function of the intrinsic grille-source and drain-source voltages in terms of physical dimensions. The basic equation

*S*

2 2 ( ) *<sup>D</sup>*

*L* 

*<sup>W</sup> <sup>d</sup> W Zq N E Id a W WdW*

(34)

*dv E dE*

*<sup>µ</sup> µ E*

0

0

*E E E*

0 *S*

 

*C*

1 2 2 2

( )

0

used to derive the *I-V* relationship (Sze and Ng, 2007) is given by:

and the pinch-off voltage:

$$Ip = \frac{Zq^2N\_d^2\mu(E)a^3}{2\varepsilon L} \tag{36}$$

$$
\mu\_D = \frac{W\_D}{a} \tag{37}
$$

$$
\mu\_S = \frac{W\_S}{a} \tag{38}
$$

*uD* and *uS* are the normalized dimensionless units.

The mobility law makes it possible to obtain the different expressions of the drain-current in the different operation regimes (linear, non-linear and saturated). Fig. 1 shows the structure of a MESFET with the channel under the gate. It can be divided in general into three regions (*LA*, *LB* and *LC*) depending upon the magnitude of the electric field (Shin and Klemer, 1992; Khemissi et al. 2004, 2006). In the region *LA* the electric field is below *E0*, and the electron mobility is given by equation (29), region *LB* correspond the electric field is between *E0* and *ES* and the electron mobility is given by equation (30), the last *LC* is the high field region in which the electric field exceeds *ES* and the mobility is given by equation (30).

**Figure 1.** A cross-sectional view of a biased MESFET channel

#### **2.8. Linear regime**

This regime exists when the applied drain-source voltage is sufficiently low such that the electrical field under the gate is both smaller than *E0*, the mobility is equal to *µ0* and the channel is described by *LA*. The expression of the drain current in this regime is given by:

$$Id = Ip\_0 \left[ \left( \mu\_D^2 - \mu\_S^2 \right) - \frac{2}{3} \left( \mu\_D^3 - \mu\_S^3 \right) \right] \tag{39}$$

where

$$I p\_0 = \frac{Zq^2 N\_d^2 \mu\_0 a^3}{2\varepsilon L} \tag{40}$$

Analytical Model and Numerical Simulation

for the Transconductance and Drain Conductance of GaAs MESFETs 267

*Vgs Vg RsId* (45)

*Vds Vd RdId* (46)

*m d dId g dVg g dVd* (49)

(50)

(47)

(48)

(51)

The characteristics which we have calculated are those of the intrinsic values (*Vg, Vd* and *Id*). To obtain the extrinsic characteristics (*Vgs, Vds,* and *Ids,*) of the device it is necessary to take into account the effect of parasitic resistances (*Rs, Rd* and *Rp*) and substitute the intrinsic terms by the extrinsic terms in all the previous expressions. In this case *Vgs, Vds* and *Ids* can

*Vds Ids Id*

where *Rs* is the resistance of the region from the source contact to the source side of the gate, *Rd* is the resistance of the drain region outside the gate and *Rp* is the parallel resistance

It is obviously necessary to implement an iterative technique to obtain the extrinsic drain current *Ids* for given values of the gate-source and drain-source voltages *Vgs* and *Vds*

The expression of the intrinsic drain current "*Id*" makes it possible to determine the mathematical expressions of the transconductance and the drain conductance. When the transistor is polarized at a point of operation given by the biasing, the expression of the

> *Id Id dId dVg dVd Vg Vd*

> > *Id <sup>g</sup> Vg*

*Id <sup>g</sup> Vd* 

After simple derivations of the current drain expressions in the different operation regimes,

*Vd cst*

*Vg cst*

*Rp*

**2.11. Effect of parasitic resistances** 

be respectively expressed as

associated with the buffer layer.

current "*Id*" can be written as follows:

**2.12. Transconductance and drain conductance** 

The expression of the transconductance is defined by the equation:

And the expression of the drain conductance is given by the equation:

*m*

*d*

one obtains the expressions of the transconductance and the drain conductance.

respectively.

#### **2.9. Pinch-off regime**

As the drain-source voltage increases, the electric field in the channel is not entirely below *E0*. For this case, the channel under the gate consists of two regions: One of the lengths *LA* with the field is below *E0* and the mobility is equal to *µ0*. The other region of the length *LB* with *E* is between *E0* and *ES* and the mobility is given by equation (30). The expression of the current in this regime can be obtained by:

$$Id = Ip\_0 \left[ \left( \mu\_A^2 - \mu\_S^2 \right) - \frac{2}{3} \left( \mu\_A^3 - \mu\_S^3 \right) \right] + Ipm \left[ \left( \mu\_D^2 - \mu\_A^2 \right) - \frac{2}{3} \left( \mu\_D^3 - \mu\_A^3 \right) \right] \tag{41}$$

where

$$Ip\eta = \frac{Zq^2N\_d^2\mu\_0a^3}{2\varepsilon L\left[1+\left(\frac{E-E\_0}{E\_\odot}\right)^2\right]^{1/2}}\tag{42}$$

and *uA* is the normalized dimensionless unit which corresponds to the drain bias equal to (*E0.L*).

#### **2.10. Saturation regime**

As the electric field at the drain side becomes larger than *ES*, the channel is divided into three regions: The first of the length *LA*, the second of the length *LB* and the last of the length *LC* in which the depletion-layer reaches the interface between the activate area and the semiinsulator substrate. The expression of the current in this regime can be obtained by

$$Id = Ip\_0 \left[ \left( \mu\_A^2 - \mu\_S^2 \right) - \frac{2}{3} \left( \mu\_A^3 - \mu\_S^3 \right) \right] + Ips \left[ \frac{1}{3} - \left( \mu\_A^2 - \frac{2}{3} \mu\_A^3 \right) \right] \tag{43}$$

where

$$Ips = \frac{Zq^2N\_d^2\mu\_0a^3}{2\varepsilon L\left[1 + \left(\frac{E\_S - E\_0}{E\_C}\right)^2\right]^{1/2}}\tag{44}$$

#### **2.11. Effect of parasitic resistances**

266 Numerical Simulation – From Theory to Industry

**2.9. Pinch-off regime** 

current in this regime can be obtained by:

0

0

where

where

(*E0.L*).

where

**2.10. Saturation regime** 

22 33

22 3 0

As the drain-source voltage increases, the electric field in the channel is not entirely below *E0*. For this case, the channel under the gate consists of two regions: One of the lengths *LA* with the field is below *E0* and the mobility is equal to *µ0*. The other region of the length *LB* with *E* is between *E0* and *ES* and the mobility is given by equation (30). The expression of the

22 33 22 33

22 3 0

*C*

*d*

<sup>0</sup> 2 1

*E E <sup>L</sup> E*

and *uA* is the normalized dimensionless unit which corresponds to the drain bias equal to

As the electric field at the drain side becomes larger than *ES*, the channel is divided into three regions: The first of the length *LA*, the second of the length *LB* and the last of the length *LC* in which the depletion-layer reaches the interface between the activate area and the semi-

22 33 2 3

22 3 0

*d*

*S C*

3 33 *AS AS A A Id Ip u u u u Ips u u* 

<sup>0</sup> 2 1

*E E <sup>L</sup> E*

*Zq N a Ips*

2 12

1/2 <sup>2</sup>

insulator substrate. The expression of the current in this regime can be obtained by

*Zq N a Ipn*

1/2 <sup>2</sup>

2 2 3 3 *AS AS DA DA Id Ip u u u u Ipn u u u u* 

<sup>0</sup> 2 *Zq N a <sup>d</sup> Ip <sup>L</sup>*

2

<sup>3</sup> *DS DS Id Ip u u u u* (39)

(40)

(41)

(42)

(43)

(44)

0

The characteristics which we have calculated are those of the intrinsic values (*Vg, Vd* and *Id*). To obtain the extrinsic characteristics (*Vgs, Vds,* and *Ids,*) of the device it is necessary to take into account the effect of parasitic resistances (*Rs, Rd* and *Rp*) and substitute the intrinsic terms by the extrinsic terms in all the previous expressions. In this case *Vgs, Vds* and *Ids* can be respectively expressed as

$$V\text{\\$g\\$} = V\text{\\$g} + \text{RsId} \tag{45}$$

$$Vds = Vd + RdId\tag{46}$$

$$Ids = Id + \frac{Vds}{Rp} \tag{47}$$

where *Rs* is the resistance of the region from the source contact to the source side of the gate, *Rd* is the resistance of the drain region outside the gate and *Rp* is the parallel resistance associated with the buffer layer.

It is obviously necessary to implement an iterative technique to obtain the extrinsic drain current *Ids* for given values of the gate-source and drain-source voltages *Vgs* and *Vds* respectively.

#### **2.12. Transconductance and drain conductance**

The expression of the intrinsic drain current "*Id*" makes it possible to determine the mathematical expressions of the transconductance and the drain conductance. When the transistor is polarized at a point of operation given by the biasing, the expression of the current "*Id*" can be written as follows:

$$dIdd = \frac{\partial Id}{\partial V \mathcal{g}} dV \mathcal{g} + \frac{\partial Id}{\partial V d} dV d \tag{48}$$

$$dId = \mathcal{g}\_m dV \mathcal{g} + \mathcal{g}\_d dV d\tag{49}$$

The expression of the transconductance is defined by the equation:

$$\mathcal{g}\_m = \frac{\partial \mathcal{I} d}{\partial \mathcal{V} \mathcal{g}} \bigg|\_{\mathcal{V} \mathcal{d} = \text{cst}} \tag{50}$$

And the expression of the drain conductance is given by the equation:

$$\mathcal{g}\_d = \frac{\partial Id}{\partial Vd}\bigg|\_{V\mathcal{g}=cst} \tag{51}$$

After simple derivations of the current drain expressions in the different operation regimes, one obtains the expressions of the transconductance and the drain conductance.

### **3. Numerical methods**

#### **3.1. Calculation of the drain current**

To calculate the extrinsic characteristics *Ids (Vds, Vgs)*, one needs to put in consideration the effect of parasitic resistances, this effect which is not negligible, is very significant for the exactitude of the analytical model, but the problem of this type of models (model analytical) is that, the effect of parasitic resistances in the hand is requires to calculate the expressions of the drain current and on the other hand the mathematical relations which express this effect are determined also by the drain current. To solve this problem, are thus needed used a sophistical numerical methods. In this study, we used the iterative method represented by the following relations:

At the beginning, the initial extrinsic drain current *Ids* is considered equal to intrinsic current *Id*.

$$Ids^{(0)} = Id\tag{52}$$

Analytical Model and Numerical Simulation

for the Transconductance and Drain Conductance of GaAs MESFETs 269

**3.2. Calculation of transconductance and the drain conductance** 

*k*

*k*

gate voltage and after the following relation:

calculation as follows:

where:

where:

**4. Simulation results** 

interpreted in this section.

**Table 1.** Summary of device dimensions

For the transconductance:

from the following relation:

The expressions of the transconductance and the conductance of drain are simple derivations of the drain current as a function as the drain and gate intrinsic voltages (Eqs. 50, 51), to obtain the values of these significant parameters, we based on numerical

After the fixing of the drain voltage to the given value, the transconductance is obtained

( ) ( 1) ( ) ( )

*Ids Ids Ids*

Same manner as the transconductance, the drain conductance is obtained after fixing of the

*Ids Ids Ids*

In order to illustrate the exposed model, we elaborated simulation software based on different formulas and mathematical equations previously obtained and by using the numerical methods. The study carried out on a submicron gate length GaAs MESFET transistors which parameters shown in the table 1. The results obtained are exposed and

L (µm) a (µm) Z (µm) Nd (At / cm3) µ0 (cm2/ Vs) E0 / Em 0,3 0,145 100 1,2. 1017 3400 0,25 Rs (Ω) Rd (Ω) Rp (Ω) a1 b1 c1 6 6 600 - 0,06 0,12 0,10

In the fig. 3, we have presented the network of the static characteristics in the case of the preceding device. These characteristics illustrate the relation between the extrinsic drain

( ) ( 1) ( ) *k kk*

*Vg cst Vg cst*

 

( ) ( 1) ( ) ( )

*d k kk*

*<sup>g</sup> Vd Vd Vd*

*m k kk*

*<sup>g</sup> Vg Vg Vg*

( ) ( 1) ( ) *k kk*

*Vd cst Vd cst*

(56)

( 1) ( ) 0,01 *k k Vg Vg* (57)

(58)

( 1) ( ) 0,01 *k k Vd Vd* (59)

 

$$\text{Consequently}\\
\text{//}\tag{5}\\
\text{Ids}^{\{1\}} = \text{Ids}^{\{0\}} + \Delta \text{Ids}^{\{1\}}\tag{53}$$

where: *Δ Ids (1)* is on a side the difference between *Ids (1)* and *Ids (0)* and on the other side it results on the effect of parasitic resistances for *Ids = Ids (0)*.

$$\begin{array}{ccccc} \operatorname{Ids}^{(2)} = \operatorname{Ids}^{(1)} + \Delta \operatorname{Id} \operatorname{s}^{(2)} \\\\ \cdot & \cdot & \cdot \\\\ \cdot & \cdot & \cdot \\\\ \cdot & \cdot & \cdot \\\\ \operatorname{Ids}^{(n)} = \operatorname{Ids}^{(n-1)} + \Delta \operatorname{Id} \operatorname{s}^{(n)} \end{array} \tag{54}$$

*0*

The operation is stopped when: ( ) 3 ( 1) 10 *n n Ids Ids* (55)

**Figure 2.** Diagram representative of the method

#### **3.2. Calculation of transconductance and the drain conductance**

The expressions of the transconductance and the conductance of drain are simple derivations of the drain current as a function as the drain and gate intrinsic voltages (Eqs. 50, 51), to obtain the values of these significant parameters, we based on numerical calculation as follows:

For the transconductance:

After the fixing of the drain voltage to the given value, the transconductance is obtained from the following relation:

$$\left. \mathcal{G}\_{m} \stackrel{(k)}{=} \frac{\Delta \text{Id} s^{(k)}}{\Delta V \mathcal{g}^{(k)}} \right|\_{\text{Vd=cst}} = \frac{\text{Ids}^{(k+1)} - \text{Ids}^{(k)}}{V \mathcal{g}^{(k+1)} - V \mathcal{g}^{(k)}} \Big|\_{\text{Vd=cst}} \tag{56}$$

where:

268 Numerical Simulation – From Theory to Industry

**3.1. Calculation of the drain current** 

To calculate the extrinsic characteristics *Ids (Vds, Vgs)*, one needs to put in consideration the effect of parasitic resistances, this effect which is not negligible, is very significant for the exactitude of the analytical model, but the problem of this type of models (model analytical) is that, the effect of parasitic resistances in the hand is requires to calculate the expressions of the drain current and on the other hand the mathematical relations which express this effect are determined also by the drain current. To solve this problem, are thus needed used a sophistical numerical methods. In this study, we used the iterative method represented by

At the beginning, the initial extrinsic drain current *Ids* is considered equal to intrinsic

Consequently, (1) (0) (1) *Ids Ids Ids* (53)

where: *Δ Ids (1)* is on a side the difference between *Ids (1)* and *Ids (0)* and on the other side it

(2) (1) (2)

.. . .. . .. . *nn n*

*Ids Ids Ids*

( ) ( 1) ( )

The operation is stopped when: ( ) 3 ( 1) 10 *n n Ids Ids* (55)

**x** 

**x**

**x**

**x x**

*Ids(n- Ids(n)* 

*0*

*Ids Ids Ids*

results on the effect of parasitic resistances for *Ids = Ids (0)*.

**Figure 2.** Diagram representative of the method

**x**

*ΔIds(1) ΔIds(2*

*Ids(1)* 

**x**

*Ids(2)* 

**x**

*Ids(3)* 

**x**

*Ids(0)* 

(0) *Ids Id* (52)

(54)

**3. Numerical methods** 

the following relations:

current *Id*.

$$V\mathcal{g}^{(k+1)} - V\mathcal{g}^{(k)} = 0,\\ 01\tag{57}$$

Same manner as the transconductance, the drain conductance is obtained after fixing of the gate voltage and after the following relation:

$$\left. \mathcal{G}\_d^{(k)} = \frac{\Delta I ds^{(k)}}{\Delta V d^{(k)}} \right|\_{V\_{\overline{\mathcal{S}}} = cst} = \frac{I ds^{(k+1)} - I ds^{(k)}}{V d^{(k+1)} - V d^{(k)}} \Big|\_{V\_{\overline{\mathcal{S}}} = cst} \tag{58}$$

where:

$$Vd^{(k+1)} - Vd^{(k)} = 0,\\ 01\tag{59}$$

## **4. Simulation results**

In order to illustrate the exposed model, we elaborated simulation software based on different formulas and mathematical equations previously obtained and by using the numerical methods. The study carried out on a submicron gate length GaAs MESFET transistors which parameters shown in the table 1. The results obtained are exposed and interpreted in this section.


**Table 1.** Summary of device dimensions

In the fig. 3, we have presented the network of the static characteristics in the case of the preceding device. These characteristics illustrate the relation between the extrinsic drain current *Ids* and the bias voltages *Vds* and *Vgs*. We notice the presence of three regions which correspond to the three operation regimes (linear, non-linear and saturated).

Analytical Model and Numerical Simulation

for the Transconductance and Drain Conductance of GaAs MESFETs 271

extension of this area ends when this one occupies all the width of the channel. No passage

**Figure 4.** Comparisons of the *I-V* characteristics between the proposed model (solid line) and the experimental data (asterisks) (Chin and Wu, 1993) for the device with dimensions are listed in Table 2.

**Figure 5.** Variation in transconductance as a function of gate-source voltage at different drain-source

voltages for a device with parameters and dimensions are listed in Table 1.

of the current is then theoretically possible.

**Figure 3.** Drain current versus drain-source voltage at a different gate-source voltages for GaAs MESFET with parameters and device dimensions are listed in Table 1.

To demonstrate the validity of the developed model and to compare its performance with the experimental data reported in the literature (Chin and We, 1993) a submicron GaAs MESFET having the parameters and device dimensions selected in Table 2. Fig. 4 represented a comparison between the proposed model and the experimental *I-V* characteristics for this device. It is clearly seen that good agreement between the model and the experimental data are obtained, this is quite interesting to argue the validity of the mathematical analysis and the proposed numerical methods for practical short gate-length GaAs MESFET devices.


**Table 2.**

Fig. 5 and Fig. 6 represent the transconductance as a function of the intrinsic drain voltage *Vd* for a series of intrinsic gate voltage *Vg*. In these figures, we noticed that the transconductance increases on the one hand as the absolute value of the voltage gate decreases, and on the other hand with the increase in the drain voltage until the saturation regime where the transconductance is saturated. This is explained because, more the gate voltage increases in absolute value, more the width of space charge area increases. The extension of this area ends when this one occupies all the width of the channel. No passage of the current is then theoretically possible.

270 Numerical Simulation – From Theory to Industry

current *Ids* and the bias voltages *Vds* and *Vgs*. We notice the presence of three regions which

**Figure 3.** Drain current versus drain-source voltage at a different gate-source voltages for GaAs

To demonstrate the validity of the developed model and to compare its performance with the experimental data reported in the literature (Chin and We, 1993) a submicron GaAs MESFET having the parameters and device dimensions selected in Table 2. Fig. 4 represented a comparison between the proposed model and the experimental *I-V* characteristics for this device. It is clearly seen that good agreement between the model and the experimental data are obtained, this is quite interesting to argue the validity of the mathematical analysis and the proposed numerical methods for practical short gate-length GaAs MESFET devices.

L (µm) a (µm) Z (µm) Nd (At / cm3) µ0 (cm2/ Vs) E0 / Em 0,5 0,143 100 1,31. 1017 3600 0,25 Rs (Ω) Rd (Ω) Rp (Ω) a1 b1 c1 6 6 1000 - 0,06 0,12 0,10

Fig. 5 and Fig. 6 represent the transconductance as a function of the intrinsic drain voltage *Vd* for a series of intrinsic gate voltage *Vg*. In these figures, we noticed that the transconductance increases on the one hand as the absolute value of the voltage gate decreases, and on the other hand with the increase in the drain voltage until the saturation regime where the transconductance is saturated. This is explained because, more the gate voltage increases in absolute value, more the width of space charge area increases. The

MESFET with parameters and device dimensions are listed in Table 1.

**Table 2.**

correspond to the three operation regimes (linear, non-linear and saturated).

**Figure 4.** Comparisons of the *I-V* characteristics between the proposed model (solid line) and the experimental data (asterisks) (Chin and Wu, 1993) for the device with dimensions are listed in Table 2.

**Figure 5.** Variation in transconductance as a function of gate-source voltage at different drain-source voltages for a device with parameters and dimensions are listed in Table 1.

Fig. 7 represents the drain conductance as a function of the drain voltage for a series of gate voltage. We notice that the drain conductance is decreases on the one hand as the drain Analytical Model and Numerical Simulation

for the Transconductance and Drain Conductance of GaAs MESFETs 273

voltage increases and on the other hand when the absolute value of the gate voltage increases. It takes its maximum value in linear regime, and is cancelled in regime of saturation. This explains why, in linear mode, the electrons available for conduction and present in the channel do not reach their speed limit. Also the drain current *Ids* varies in an important and quasi linear way with the drain voltage. On the contrary, for the strong values of *Vd* in the saturated regime, the electrons reached their speed limits and the current

During this work, a comprehensive new model is developed to simulate the static characteristics of short gate-length GaAs MESFET. The validity of the model is established by simulating *Ids*, *gm* and *Gd* characteristics. The performance of the model is compared with experimental results existing in the literature by calculating the I-V characteristics of a device with the gate length is equal to 0,5 µm. It has been demonstrated that the proposed model is a comprehensive one capable of simulating DC characteristics of short gate-length GaAs MESFETs. The transconductance and drain conductance curves obtained by the model have the same behavior with those of the theory, so that it has been shown that proposed

model could be a useful tool for device simulators involving short channel MESFETs.

Chang and Day, USA(1989) "Analytical theory for current- voltage characteristics and field distribution of GaAs mesfet's", *IEEE Trans Elec Dev*, Vol 36, No 2 , pp 269-280. Chin and Wu, Taiwen(1992). "A new two dimensional model for the potential distribution of short gate lenght MESFET's and its applications", *IEEE Tran. Elec Dev*, Vol 39, No 8,

Chin and Wu, Taiwen(1993). "A new I-V model for short gate lenght MESFET's", *IEEE Tran.* 

Jit, Pandey and Pal, India(2003). "A New Two-Dimensional Model for the Drain-Induced Barrier Lowering of Fully Depleted Short-Channel SOI-MESFET's," *Journal of* 

Khemissi, Merabtine, Zaabat, Azizi and Saidi, Algeria(2006). " Influence of physical and geometrical parameters on electrical properties of short gate GaAs MESFET's"**,**  *Semiconductor Physics Quantum Electronics and Optoelectronics*, Vol 9 No 2 pp 34-39. Merabtine, Khemissi, Zaabat and Azizi, Algeria(2004). "Accurate numerical modeling of GaAs MESFET current-voltage characteristics", *Semiconductor Physics Quantum* 

*Ids* progresses slightly with *Vd*.

**5. Conclusion**

**Author details** 

**6. References** 

Saadeddine Khemissi

pp 1928-1937.

*Abbes Laghrour University, Khenchela, Algeria* 

*Elec Dev*, Vol 40, No 4, pp 712- 720.

*Semiconductor Technology and Science*, Vol 3, pp. 217-222.

*Electronics and Optoelectronics*, Vol 7 No 4 pp 389- 394.

**Figure 6.** Variation in transconductance as a function of drain-source voltage at different gate-source voltages for a device with parameters and dimensions are listed in Table 1.

**Figure 7.** Variation in drain conductance as a function of drain-source voltage at different gate-source voltages for a device with parameters and dimensions are listed in Table 1.

voltage increases and on the other hand when the absolute value of the gate voltage increases. It takes its maximum value in linear regime, and is cancelled in regime of saturation. This explains why, in linear mode, the electrons available for conduction and present in the channel do not reach their speed limit. Also the drain current *Ids* varies in an important and quasi linear way with the drain voltage. On the contrary, for the strong values of *Vd* in the saturated regime, the electrons reached their speed limits and the current *Ids* progresses slightly with *Vd*.
