**6. Three-dimensional numerical simulations results at high temperatures**

284 Numerical Simulation – From Theory to Industry

illustrated in Figure 8.

[18-20].

temperature conditions.

Additionally, it is plotted a picture of the DSM ( =53o) total drain current density, considering VGS and VDS equals to 0.4 V and 1.2 V, respectively, in saturation region, as

**Figure 8.** Curves of the total drain current density of DSM (=53o) (Figure 8.a) and CSM counterpart (Figure 8.b) channel regions for VGS and VDS equal to 0.4 V and 1.2 V, respectively (saturation region).

**5. SOI MOSFEts investigationat high temperatures** 

reduction and excessive drain leakage current increases [14-18].

Figure 8 shows that DSM ( =90o) total drain current density is higher in the center of the channel region than in the vertices (source/drain and channel regions interfaces) of the device, indicating that this layout style can be evolved to the octagonal gate geometric [10].

Today, there are much electronic equipments that operate under high-temperature environment (from room temperature up to 300oC) such as avionics, automotive, aircrafts, spacecrafts, ships, train, among other [11-13], where conventional (bulk) CMOS integrated circuits can operate satisfactorily at moderate temperatures (up to 150oC), but when the temperature increases beyond this, the devices present failures arising the threshold voltage

Fortunately, thanks to the advantages of SOI CMOS technology, especially at high temperatures, their applications at high temperatures can be extended up to 300oC, where its electrical performance is less impaired than the one found in the conventional MOSFETs

In this context, the drain leakage current (IDLeak) of the Diamond SOI nMOSFET (DSM) is analyzed from room temperature up to 300oC by the three-dimensional numerical simulator ATLAS [1]. The DSM IDLeakresults are then compared tothe one found in the SOI MOSFETs (CSM) counterpart, taking into account the same die area, geometric factor and bias and To analyze DSM operating at high temperatures, from room temperature up to 300oC, CSM and DSM with different angles are implemented by using DevEdit3D [8].

In order to investigate IDLeak behavior, it is necessary to extract the IDS as a function of VGS curves, at high temperatures. Once IDLeak is obtained in the subthreshold region. In this study, IDLeak is extracted considering VGS equal to -0.5V, as it can be seen in Figure 9, for different temperatures (27oC, 100oC, 200oC and 300oC) and for all devices under evaluation in this work.

**Figure 9.** DSM (=90o) Log(IDS) as a function of VGS with VDS equal to 100 mV, considering different temperatures.

Figure 10 shows some results concerning IDLeakas a function of the temperature, considering DSM with different angles and the CSMs counterparts, operating at same bias and temperature conditions.

**Figure 10.** DSM and CSM counterpart IDLeak as a function of the temperature.

From Figure 10, it is possible to observe that, as the temperature increases, IDLeak also increases, as expected [11]. Besides that, IDLeak is higher in DSM when compared to CSM devices, independently of the angle and the temperature. It happens since the longitudinal electric field is higher in DSM when compared to CSMs and consequently, its drain leakage current (IDLeak) is also larger. On the other hand, it worthwhile to describe that as reduces, IDLeak difference observed between both devices becomes higher. As for example, when is equal to 127o, DSM IDLeak is 20% higher than the one observed in the CSM counterpart (L= 2.5µm) for VGS=-0.5 V, but providing an IDS also 20% more than rectangular gate transistor, for VGS=1.2V. These increasing proportions between IDLeak and drain currents are maintained for all equivalent devices, i.e., for = 53o and 127o.

Using Numerical Simulations to Study and Design Semiconductors Devices in Micro and Nanoelectronics 287

By using Diamond layout style, instead rectangular gate geometry, the die area of analog integrated circuits can be significantly reduced since the drain current of the Diamond structure is higher than the one observed in the Conventional counterpart, considering the

Therefore, the Diamond layout style becomes an important device alternative to improve the performance of the transistors and consequently the performance of the analog and

This temperature studyin the Diamond layout structure shows the drain leakage current behavior in the Diamond SOI MOSFETs, in comparison to the conventional one counterpart, regarding these devices operating since room temperature (27oC) up to 300oC. From this investigation it is observed that IDLeak in Diamond SOI MOSFETs is higher than the one observed in Conventional devices operating at same bias and temperatures conditions, because the longitudinal electric field along the Diamond channel length is higher than the one found in the conventional counterpart. On the other hand, the DSM drain current is increased in the same proportion of IDLeak, regarding to the same die area, geometric factor and bias and temperature conditions. So, these results show that also it is possible to analyze and investigate the behavior of devices at high temperatures, through three-dimensional numerical simulations, in order to predict its performance in harsh environments before submit them in such real operation conditions, and thus, even get additional information to improve the design/performance of the ICs in harsh temperature conditions. Therefore, Diamond layout style IDLeak (35 pA and 228 pA for equals to 127o and 53o, respectively) presents practically the same magnitude order than the one observed in the CSM counterpart (67 pA and 28 pA for equals to 127o and 53o, respectively) at 300 oC and therefore when it is used DSM instead of the conventional one, Diamond structure does not degrade the performance the battery time life of the portable electronics equipment

same gate area, geometry factor (aspect ratio) and bias conditions.

operating in harsh (high temperature) environments.

*Department of Electrical Engineering, Centro Universitário da FEI (FEI),* 

[1] Atlas User's Manual (2011) Device Simulation Software, Silvaco Inc. [2] Sentaurus Device User Guide (2009) Synopsys Inc., v. C-2009.06.

The author would really acknowledge CNPq and FAPESP for the financial support.

[3] Colinge J-P (2008) FinFETs and Other MOSFET Multi-Gate Transistors, Springer.

Salvador Pinillos Gimenez and Marcello Bellodi

*São Bernardo do Campo, São Paulo, Brazil* 

digital ICs.

**Author details** 

**Acknowledgement** 

**8. References** 

Figure 11 shows DSM IDLeak behavior as a function of the angle α. It is important to comment that this comparison is possible once IDLeak is normalized with the geometric factor (W/L), thus providing a more realistic comparison of IDLeak as α changes. Then, analyzing the results it is possible to observe that, for the same temperature, as α increase, IDLeak becomes smaller. Otherwise, for the same α, IDLeak also increases according to the temperature rises.

**Figure 11.** Diamond SOI nMOSFET IDLeak behavior as a function of α, at high temperatures.

Anyway, for both CSM and DSM, IDLeak increases when the temperature increases in the same proportion,mainly due to the thermal generation process [15], but in DSM IDLeak is higher because the longitudinal electric field along the DSM channel length is higher than the one present in its CSM counterpart.
