**1. Introduction**

274 Numerical Simulation – From Theory to Industry

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*semiconductor technology and science*, Vol 5, No 3, pp 173-181.

The survival of the integrated circuits(ICs) industries is directly linked to its ability to innovate in terms of the developing new semiconductor devices (planar and threedimensional) and new manufacturing process technologies (Silicon-On-Insulator, etc), in theircapability to reduce the dimensions of semiconductor devices focusing on the increasing of integration capability of the devices into a single integrated circuit (IC) and in their efficiency to develop new digital and analog ICs applications to attend the market in different forms of consumption. In this context, the numerical simulators represent a very important role for the ICs industries and very high investments have been done in this area of the process and device simulation tools (Technology Computer-Aided Design, TCAD) in order to use the computer simulations to develop and optimize semiconductor processing technologies and devices [1-2].

Significant costs reductions can be achieved through the use of numerical simulators for developing new semiconductor manufacturing technologies and devices that are associated with ICs industries. Thinking on developing new devices, the numerical simulations are able to supply a lot of information about the devices in terms of theirs electrical characteristics curves (drain current as a function of gate voltage for the MOSFETs, etc) and mainly in terms of the internal electrical and physical behaviors of the semiconductor devices (current density, electric field density, potential distribution along of the device structure, mobile carriers density along of the channel width and length of a MOSFET, etc) previously to the physical implementation, which is impossible to be obtained, visualized and understood with only the electrical characterization of the physical devices [1-2]. The involved costs with numerical simulations are associated mainly with human resources and infra-structure (hardware and software) while that, if new devices developing were

© 2012 Gimenez and Bellodi, licensee InTech. This is an open access chapter distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. © 2012 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

associated only with the manufacturing process use, would involve very high production costs, very high lead time and many uncertainties about the efficiency of the proposed devices [1-2].

Using Numerical Simulations to Study and Design Semiconductors Devices in Micro and Nanoelectronics 277

) is given by the vector sum of the longitudinal electric field components (

 //1 and

//2

*B b <sup>L</sup>* (1)

//

) in the center of the gate

//2

) in the

 //1 and

) are generated by

). Last is higher than the one observed in the conventional SOI nMOSFET

In Figure 1, the shorter and longer channel dimensions are represented by b and B, respectively, W is the channel width and Leff is the effective channel length, α angle is the angle of the drain/channel and the channel/source interfaces due to hexagonal gate geometry, tox, tSI and tBOXare gate oxide, silicon film and buried oxide thickness, respectively.

Figure 2 presents the Diamond SOI nMOSFET layout style, where the longitudinal corner effect (LCE) acting in the point P in the channel is shown and the resultant longitudinal

the drain bias (VDS) and are perpendiculars to the metallurgical junctions of the drain/silicon

The effective channel length (Leff) of the Diamond SOI nMOSFET is given by the equation

2 *eff*

Drain Source Gate

 

//1 

W

// //1 //2

 

**Figure 2.** Example of a SOI nMOSFET 3D layout showing the LCE acting in the point P.

P

region is higher than the one observed in the edges of the gate region, due to the higher

b B

//2 

center of the device (LCE) [4-7] than the one found in the edges of the gate region, and therefore the drain current tends to flow more in the center of the gate region than in the edges of the gate region. Besides that, the Diamond structure can be electrically represented by the parallel association of the N transistors, where the channel width of each transistor of this parallel association is given by W/N and the channel length of these transistors varies from b to B. As a consequence of this last feature, the drain current tends to flow more by the edges than by the center of the gate region. This effect is defined here

In this structure, the resultant longitudinal electric field (

interaction between the longitudinal electric field components (

electric field (

 //1 and

(1).

/ /

film (channel region) [4-7].

counterpart. These longitudinal electric field components (

//2

Currently there is two-pronged research in the world focusing on developing new semiconductor devices [3]. The first one is based on designing of the new tridimensional (3D) devices, such as the multi-gates MOSFETs (FinFETs, Three-gates, Four-gates, Surrounding-gate) that involve high cost and investments related to the new techniques of ICs manufacturing process andnew materials. The other tries to explore the many real improvement opportunities of the current planar ICs manufacture technology. One of them, it is to use the "drain/source and channel region interface engineering" (D/SCRIE) approach [4-6], where it can implement new and innovative layout styles with non-conventional geometries, focusing on enhancing the device performance and consequently the performance of analog and digital ICs applications [4-7]. An example is very promising of this layout approach is the "Diamond MOSFET" that it was carefully and specially designed to improve the longitudinal (parallel) electric field ( // ) in order to increase the mobile carriers drift velocity in the channel region ( // ) and consequently the drain current (IDS), transconductance (gm) and to reduce the on-state drain/source series resistance (RDS\_on) by a simple changing of the gate geometry from the conventional (rectangular) to hexagonal, as illustrated in Figure 1, showing an example of a SOI nMOSFET3D structure [4-7].

**Figure 1.** Example of a SOI nMOSFET 3D structure.

In Figure 1, the shorter and longer channel dimensions are represented by b and B, respectively, W is the channel width and Leff is the effective channel length, α angle is the angle of the drain/channel and the channel/source interfaces due to hexagonal gate geometry, tox, tSI and tBOXare gate oxide, silicon film and buried oxide thickness, respectively.

276 Numerical Simulation – From Theory to Industry

to improve the longitudinal (parallel) electric field (

carriers drift velocity in the channel region (

**Figure 1.** Example of a SOI nMOSFET 3D structure.

devices [1-2].

associated only with the manufacturing process use, would involve very high production costs, very high lead time and many uncertainties about the efficiency of the proposed

Currently there is two-pronged research in the world focusing on developing new semiconductor devices [3]. The first one is based on designing of the new tridimensional (3D) devices, such as the multi-gates MOSFETs (FinFETs, Three-gates, Four-gates, Surrounding-gate) that involve high cost and investments related to the new techniques of ICs manufacturing process andnew materials. The other tries to explore the many real improvement opportunities of the current planar ICs manufacture technology. One of them, it is to use the "drain/source and channel region interface engineering" (D/SCRIE) approach [4-6], where it can implement new and innovative layout styles with non-conventional geometries, focusing on enhancing the device performance and consequently the performance of analog and digital ICs applications [4-7]. An example is very promising of this layout approach is the "Diamond MOSFET" that it was carefully and specially designed

> //

transconductance (gm) and to reduce the on-state drain/source series resistance (RDS\_on) by a simple changing of the gate geometry from the conventional (rectangular) to hexagonal, as

illustrated in Figure 1, showing an example of a SOI nMOSFET3D structure [4-7].

//

) in order to increase the mobile

) and consequently the drain current (IDS),

Figure 2 presents the Diamond SOI nMOSFET layout style, where the longitudinal corner effect (LCE) acting in the point P in the channel is shown and the resultant longitudinal electric field ( / / ) is given by the vector sum of the longitudinal electric field components ( //1 and //2 ). Last is higher than the one observed in the conventional SOI nMOSFET counterpart. These longitudinal electric field components ( //1 and //2 ) are generated by the drain bias (VDS) and are perpendiculars to the metallurgical junctions of the drain/silicon film (channel region) [4-7].

The effective channel length (Leff) of the Diamond SOI nMOSFET is given by the equation (1).

**Figure 2.** Example of a SOI nMOSFET 3D layout showing the LCE acting in the point P.

In this structure, the resultant longitudinal electric field ( // ) in the center of the gate region is higher than the one observed in the edges of the gate region, due to the higher interaction between the longitudinal electric field components ( //1 and //2 ) in the center of the device (LCE) [4-7] than the one found in the edges of the gate region, and therefore the drain current tends to flow more in the center of the gate region than in the edges of the gate region. Besides that, the Diamond structure can be electrically represented by the parallel association of the N transistors, where the channel width of each transistor of this parallel association is given by W/N and the channel length of these transistors varies from b to B. As a consequence of this last feature, the drain current tends to flow more by the edges than by the center of the gate region. This effect is defined here by "Variable Channel Lengths of Transistors Associated in Parallel Effect" (VACLETAPE). So, in the Diamond structure occurs two effects at the same time, i.e., the LCE and the VACLETAPE generating a Diamond drain current higher than the one observed in the conventional (rectangular) SOI nMOSFET counterpart, regarding the same gate area (AG) and bias conditions.

Using Numerical Simulations to Study and Design Semiconductors Devices in Micro and Nanoelectronics 279

Besides that, ATLAS generates three types of output files. The first one is the "run-time output file" that provides all the error and warning messages. The second one is the "log files", which store allterminal voltages and currents of the device [direct current (DC), small signal alternate current (AC) and transient] generated the command SOLVE. This last file can be seen with the TonyPlot (visualization tool) to visualize the electrical behavior of the device. The last one is the "solution files", and it is responsible to stores the two-dimensional and three-dimensionaldata of the solution variables within the device for a single bias point (electric field, potential, etc.). This last file can be visualized by the use of TonyPlot too [1].

The following models are used to perform the 3D numerical simulations of the devices: I. Lombardi's vertical and horizontal electric-field-dependent mobility model, which includes effects of low (surface acoustic phonon scattering, optical inter-valley scattering and surface roughness) and high (Thonber's drift velocity model to calculate the velocity saturation) electric field; II. The Aurora model takes into account mobility degradation due to the lattice temperature; III. The Fowler-Nordheim Tunneling (electron and holes) model considersthe tunneling of electrons from the semiconductor Fermi level into the insulator conduction band, when high electric field across the gate is applied; IV. The Lucky-Electron Hot Carrier Injection model, considers the electrons emissions into the oxide by first gaining enough energy from the electric field in the channel to surmount the insulator/semiconductor barrier

Figure 3 presents the three-dimensional numerical (3D) simulations results of the DSMs and

**Figure 3.** Curves of three-dimensional numerical simulations of the IDS as a function of VGS for

CSMs IDS as a function of VGS,for VDS equal to 10 mV (Triode Region).

[1].

VDS=10mV.
