**Computer Science**

192 Petri Nets – Manufacturing and Computer Science

Springer Verlag ; 2005.

Education; 1994.

2008, pp. 139 – 144.

97 – 105.

[2] Adamski, M.A.; Karatkevich, A. & Węgrzyn, M.. *Design of embedded control systems*,

[3] Adamski, M.; Kołopieńczyk, M. & Mielcarek, K.. Perfect Petri Net in parallel control circuits (in Polish), *Measurement Automation and Monitoring*, 2011, Vol. 57, No. 6, pp. 656 – 660.

[5] Andreu, D.; Souquet, G. & Gil, T.. Petri Net based rapid prototyping of digital complex system, *IEEE Computer Society Annual Symposium on VLSI 2008*, pp. 405 – 410.

[10] Emerson, E.A., The Beginning of Model Checking: A Personal Perspective, In: *25 Years of Model Checking: History, Achievements, Perspectives*, O. Grumberg, H. Veith (Ed.),

[11] Fernandes, J.M. ; Adamski, M. & Proenca, A.J., VHDL generation from hierarchical Petri net specifications of parallel controllers, *IEE Proceedings – Computers and Digital* 

[12] Fix, L., Fifteen years of formal property verification in Intel, In: O. Grumberg, H. Veith (Ed.), *25 Years of Model Checking: History, Achievements, Perspectives*, Springer Verlag ;

[13] Grobelna, I., Formal verification of embedded logic controller specification with computer deduction in temporal logic, Electrical Review, 2011, nr 12a, 2011, pp. 47 – 50. [14] Grobelna, I. & Adamski, M., Model Checking of Control Interpreted Petri Nets, *Proceedings of the 18th International Conference Mixed Design of Integrated Circuits and* 

[15] Huth, M. & Ryan, M., *Logic in Computer Science. Modelling and Reasoning about Systems*,

[18] Nemec, J., Stoke the fires of FPGA design, *Electronic design*, 1994, Vol. 42, Issue 22, pp.

[20] Rice, M.V. & Vardi, M.Y., *Branching vs. Linear Time: Final Showdown*, Proceedings of the 2001 Conference on Tools and Algorithms for the Construction and Analysis of Systems,

http://www.xilinx.com/products/silicon-devices/fpga/spartan-6/index.htm(access 15.04.2012)

Lecture Notes in Computer Science, Vol. 2031, Springer Verlag; 2001, pp. 1 – 22. [21] Xilinx homepage. The producer of XILINX ISE and XILINX PlanAhead software.

[16] Kropf, T., *Introduction to Formal Hardware Verification*, Springer Verlag ; 1999. [17] Minns, P. & Elliott, I., *FSM based Digital Design using Verilog HDL*, Wiley ; 2008.

[19] NuSMV model checker homepage: http://nusmv.fbk.eu/ (access 15.04.2012)

[23] Zwoliński, M., *Digital System Design with VHDL*, Prentice Hall; 2004.

[4] Aldec home page. The producer of Active-HLD environment.

[6] Ben-Ari, M., *Mathematical logic for computer science*, Springer Verlag ; 2001.

[7] Clarke, E.M.; Grumberg, O. &Peled, D.A., Model checking, The MIT Press ; 1999. [8] David, R. & Alla, H., *Discrete, Continuous, and Hybrid Petri Nets*, Springer Verlag ; 2010. [9] De Micheli, G., *Synthesis and Optimization of Digital Circuits*, McGraw-Hill Higher

http://www.aldec.com/ (access 15.04.2012)

Springer Verlag ; 2008, pp. 27 – 45.

Cambridge University Press ; 2004.

http://www.xilinx.com (access 15.04.2012) [22] Xilinx FPGA Spartan6 family home page.

*Techniques*, 1997, Vol. 144, No. 2, pp. 127 – 137.

*Systems 2011*, pp. 621 – 626 (available in IEEE Xplore).

**Chapter 9** 

© 2012 Martiník, licensee InTech. This is an open access chapter distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use,

distribution, and reproduction in any medium, provided the original work is properly cited.

© 2012 Martiník, licensee InTech. This is a paper distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

**Sequential Object Petri Nets and the Modeling** 

Sequential object Petri nets are the newly introduced class of Petri nets, whose definition is the main topics of this article; they feature certain original concepts and can be successfully used at a design, modeling and verification of multithreading object-oriented programming systems executing in highly-parallel or distributed environment. In this article basic characteristics of sequential object Petri nets are very briefly presented including possibilities in their definition of newly introduced tokens as non-empty finite recursive sequences over the set of non-negative integer numbers, functionalities of multiarcs and the mechanism of the firing of transitions. These properties significantly increase modeling capabilities of this class of Petri nets at the modeling of multithreading object-oriented programming systems. Sequential object Petri nets can be used also in the area of recursive algorithms modeling and they are also the initial step to explicitly represent paradigms of functional programming. The fusion of object-oriented and functional programming enables

The theory of sequential object Petri nets proceeds from the theories of various types of Petri nets, starting with Place/Transition nets (Diaz, 2009) and their sub-classes, followed by High-Level nets (Jensen & Rozenberg, 1991), (Reisig, 2009) such as Predicate-Transition nets and Coloured nets (Jensen & Kristensen, 2009)*,* enabling to model apart from the management structure of the system even data processing, and in connection with modeling of object-oriented programming systems it is Object nets (Agha et. al., 2001), (Köhler & Rölke, 2007), which are being studied lately. But practical usability of Petri nets (in their original form) in the role of the parallel programming language is mainly impeded by the static nature of their structure. They are missing standard mechanisms for description of methods alone, programming modules, classes, data types, hierarchical structures, etc.

to express new kinds of programming patterns and component abstractions.

**of Multithreading Object-Oriented** 

**Programming Systems** 

Additional information is available at the end of the chapter

Ivo Martiník

http://dx.doi.org/10.5772/48470

**1. Introduction** 
