**7. References**

	- [9] Guangming C., Minghong L., Xianghu W. The Definition of Extended High-level Time Petri Nets. Journal of Computer Science 2006; 2(2):127-143.

**Chapter 8** 

© 2012 Grobelna, licensee InTech. This is an open access chapter distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

© 2012 Grobelna, licensee InTech. This is a paper distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

The chapter presents a novel approach to formal verification of logic controller programs [2], focusing especially on reconfigurable logic controllers (RLCs). Control Interpreted Petri Nets [8] are used as formal specification of logic controller behavior. The approach proposes to use an abstract rule-based logical model presented at RTL-level. A Control Interpreted Petri Net is written as a logical model, and then processed further. Proposed logical model (Figure 1) is suitable both for formal verification [14] (model checking in the NuSMV tool

Model checking [7, 10] of prepared logical model allows to validate the primary specification of logic controller. It is possible to verify some user-defined properties, which

Logical model derived from a Control Interpreted Petri Nets presented at RTL-level (*Register Transfer Level*) in such a way, that it is easily synthesizable as reconfigurable logic controller

Design methodology at RTL-level allows to convert an algorithm into hardware realization and to use the conception of variables and sequential operation performing. Project

[19]) and for logical synthesis (using hardware description language VHDL).

**Figure 1.** Logical model for model checking and synthesis purposes

or PLC (*Programmable Logic Controller*) without additional changes.

are supposed to be satisfied in designed system.

**Control Interpreted Petri Nets –** 

**Model Checking and Synthesis** 

Additional information is available at the end of the chapter

Iwona Grobelna

**1. Introduction** 

http://dx.doi.org/10.5772/47797

