**1. Introduction**

14 Will-be-set-by-IN-TECH

[1] Patterson, D.A., Hennessy, J.L. (2006). *Computer architecture – a quantitative approach* (4-th

[2] Hamilton, S. (1999). "Taking Moore's law into the next century"; *IEEE Computer*, vol.32,

[3] Wilkes, M.V. (2001). "The memory gap and the future of high-performance memories";

[4] Sinharoy B. (1997). "Optimized thread creation for processor multithreading"; *The*

[5] Baer, J-L. (2010). *Microprocessor architecture: from simple pipelines to chip multiprocessors*;

[6] Jesshope, C. (2003). "Multithreaded microprocessors – evolution or revolution"; in

[7] Tseng, J. & Asanovic, K. (2003). "Banked multiport register files for high–frequency superscalar microprocessor"; *Proc. 30-th Int. Annual Symp. on Computer Architecture*, San

[8] Burger, D. & Goodman, J.R. (2004). "Billion–transistor architectures: there and back

[9] Byrd, G.T. & Holliday, M.A. (1995). "Multithreaded processor architecture"; *IEEE*

[10] Dennis, J.B. & Gao, G.R. (1994). "Multithreaded architectures: principles, projects, and issues"; in *Multithreaded Computer Architecture: a Summary of the State of the Art*, Kluwer

[11] Ungerer, T., Robic, G. & Silc, J. (2002). "Multithreaded processors"; *The Computer Journal*,

[12] Eggers, S.J., Emer, J.S., Levy, H.M., Lo, J.L., Stamm, R.L. & Tullsen, D.M. (1997). "Simultaneous multithreading: a foundation for next-generation processors"; *IEEE*

[13] Mutlu, O., Stark, J., Wilkerson, C. & Patt, Y.N. (2003). "Runahead execution: an effective alternative to large instruction windows"; *IEEE Micro*, vol.23, no.6, pp.20-25. [14] Zuberek, W.M. (1991). "Timed Petri nets – definitions, properties and applications"; *Microelectronics and Reliability* (Special Issue on Petri Nets and Related Graph Models),

[15] Murata, T. (1989). "Petri nets: properties, analysis, and applications"; *Proceedings of the*

[16] Reisig, W. (1985). *Petri nets – an introduction* (EATCS Monographs on Theoretical

[17] Zuberek, W.M. (1986). "M–timed Petri nets, priorities, preemptions, and performance evaluation of systems"; in *Advances in Petri Nets 1985* (LNCS 222), Springer-Verlag,

[18] Zuberek, W.M. (1987). "D–timed Petri nets and modelling of timeouts and protocols";

[19] Zuberek, W.M. (1996). "Modeling using timed Petri nets – discrete–event simulation"; Technical Report #9602, Department of Computer Science, Memorial University, St.

[20] Zuberek, W.M. (2007). "Modeling and analysis of simultaneous multithreading"; *Proc. 14-th Int. Conf. on Analytical and Stochastic Modeling Techniques and Applications (ASMTA-07)*, a part of the *21-st European Conference on Modeling and Simulation (ECMS'07)*,

*Transactions of the Society for Computer Simulation*, vol.4, no.4, pp.331-357.

*Advances in Computer Systems Architecture* (LNCS 2823), pp.21-45.

**6. References**

ed.); Morgan Kaufmann.

Cambridge University Press.

*Spectrum*, vol.32, no.8, pp.38-46.

Diego, CA, pp.62-71.

Academic, pp.1-72.

vol.43, no.3, pp.320-348.

vol.31, no.4, pp.627-644.

John's, Canada A1B 3X5.

pp.478-498.

*IEEE*, vol.77, no.4, pp.541-580.

Computer Science 4); Springer-Verlag.

Prague, Czech Republic, pp.115-120.

*Micro*, vol.17, no.5, pp.12-19.

*ACM Architecture News*, vol.29, no.1, pp.2-7.

*Computer Journal*, vol.40, no.6, pp.388-400.

again"; *IEEE Computer*, vol.37, no.3, pp.22-28.

no.1, pp.43-48.

Data center availability and reliability have accomplished greater concern due to increased dependence on Internet services (e.g., Cloud computing paradigm, social networks and e-commerce). For companies that heavily depend on the Internet for their operations, service outages can be very expensive, easily running into millions of dollars per hour [15]. A widely used design principle in fault-tolerance is to introduce redundancy to enhance availability. However, since redundancy leads to additional use of resources and energy, it is expected to have a negative impact on sustainability and the associated cost.

Data center designers need to verify several trade-offs and select the feasible solution considering dependability metrics. In this context, formal models (e.g., Stochastic Petri nets and Reliability Block Diagrams) are important to provide estimates before implementing the data center system. Additionally, a growing concern of data center designers is related to the identification of components that may cause system failure as well as systems parts that must be improved before implementing the architecture.

In this work, we propose a set of formal models for quantifying dependability metrics for data center power infrastructures. The adopted approach takes into account a hybrid modeling technique that considers the advantages of both stochastic Petri nets (SPN) [22] and reliability block diagrams (RBD) [10] to evaluate system dependability. An integrated environment, namely, ASTRO [20] has been developed as one of the results of this work to automate dependability evaluation of data center architectures.
