**5. Summary and conclusions**

190 Petri Nets – Manufacturing and Computer Science

**Table 3.** Resources usage

**Figure 16.** Simulation results in *Active-HDL* 

17], this aspect is however not discussed further in this chapter.

Input signals value changes come from outside and are not modified inside VHDL model

VHDL file can also be simulated i.e. in *Active-HDL* environment [4]. Simulation confirms the proper functionality of designed logic controller (simulation results are presented in Figure 16). It is then possible to perform logic synthesis and implementation, i.e. in *Xilinx PlanAhead* environment, in version *13.1* [21]. Sample resources usage for the *xa6slx4csg225-2* circuit

**Resource Utilization Available Utilization Register** 18 4800 1% **LUT** 18 2400 1% **Slice** 6 600 1% **IO** 27 132 20% **Global Clock Buffer** 1 16 6%

It is also possible to transform logical model into synthesizable code in Verilog language [9,

file. Their values are just read out by conditions related to transition firings.

from *Spartan6* family of *XILINX* [22] is listed in Table 3.

Proposed novel approach to verification of reconfigurable logic controller programs and specification by means of Control Interpreted Petri Nets allows to detect even subtle errors on an early stage of system development. Rule-based representation of Control Interpreted Petri Nets in temporal logic is presented at RTL-level and is easy to formally verify using model checking technique and to synthesize using hardware description languages.

Results of the work include the assurance that verified behavioural specification in temporal logic will be an abstract program of matrix reconfigurable logic controller. Hence, logic controller program (its implementation) will be valid according to its primary specification. This may shorten the duration time of logic controllers development process (as early discovered errors are faster corrected) and, consequently, save money (as project budgets will not be exceeded).

Furthermore, formal verification can improve the quality of final products, making them work more reliable. And even if a logic controller, already delivered to customer, will not work properly (it can always happen that some subtle error was overseen or that the specification was incomplete), it is possible to find error source using available techniques (verification, simulation, etc.). Then, some part of corrected system (or the whole system) may be one more time formally verified using extended requirements list and modified logical model.

Future research directions include i.e. (but are not limited to) model checking of other forms of logic controllers specification and mechanisms for behavioural properties specification.
