**2. Description and illustration of proposed RLCs design system**

Logic controller development process usually starts with specification, further goes through verification [16] and simulation, finally ending with implementation. Schema of proposed system for designing of logic controllers is presented in Figure 2.

**Figure 2.** Schema of proposed system for designing of logic controllers

Formal specification is prepared by means of Control Interpreted Petri Nets [8]. They specify and model the behaviour of concurrent logic controllers and take into account properties of controlled objects. Local states, as in typical P/T Petri nets, may change after firing of transitions, if some events occur. Additionally, transition guards are associated with input signals of controller, while places are associated with its output signals.

Formally, a Control Interpreted Petri Net can be defined as a six-tuple:

$$\text{CIPN} = (\text{PN}, \text{X}, \text{Y}, \text{q}, \lambda, \text{\textasciic}, \text{\textasciic}) \tag{1}$$

where:

178 Petri Nets – Manufacturing and Computer Science

hardware description language VHDL.

in section 4.

description in VHDL language is a specification accepted by synthesis tools at RTL-level [23]. Therefore, logical model is transformed into synthesizable code in VHDL language.

Presented approach to formal verification of reconfigurable logic controllers was tested on several examples of industrial specifications by means of Control Interpreted Petri Nets. Specifications were firstly written as logical models, then transformed into appropriate

As a support for testing, a tool has been developed, which allows automatic transformation of logical model into model description in the NuSMV format and into synthesizable code in

Rules for definition of rule-based logical model and model description in the NuSMV tool are described in section 3, while rules for synthesizable model definition in VHDL are given

Logic controller development process usually starts with specification, further goes through verification [16] and simulation, finally ending with implementation. Schema of proposed

Formal specification is prepared by means of Control Interpreted Petri Nets [8]. They specify and model the behaviour of concurrent logic controllers and take into account properties of controlled objects. Local states, as in typical P/T Petri nets, may change after firing of transitions, if some events occur. Additionally, transition guards are associated with input

formats, and finally formally verified (with some properties added) and synthesized.

**2. Description and illustration of proposed RLCs design system** 

system for designing of logic controllers is presented in Figure 2.

**Figure 2.** Schema of proposed system for designing of logic controllers

signals of controller, while places are associated with its output signals.

