**5. Operational amplifier design**

In order to apply simulated annealing in a more realistic and practical operational amplifier, we syntesized a folded cascode in CMOS IBM 0.18*μm*, regular *Vt*, 1.8*V* technology node. The schematics of this amplifier is shown in Fig. 14.

Variable Final values (our work) Final values - GENOM ([3])

Simulated Annealing to Improve Analog Integrated Circuit Design: Trade-Off s and Implementation Issues 281

*W*<sup>1</sup> 11.58 *μm* 14.91 *μm W*<sup>4</sup> 22.39 *μm* 6.99 *μm W*<sup>5</sup> 14.13 *μm* 36.78 *μm W*<sup>7</sup> 30.72 *μm* 63.04 *μm W*<sup>9</sup> 7.16 *μm* 31.45 *μm W*<sup>11</sup> 6.58 *μm* 7.32 *μm L*<sup>1</sup> 0.73 *μm* 1.38 *μm L*<sup>4</sup> 0.71 *μm* 1.94 *μm L*<sup>5</sup> 0.29 *μm* 0.37 *μm L*<sup>7</sup> 0.52 *μm* 0.91 *μm L*<sup>9</sup> 0.87 *μm* 0.89 *μm L*<sup>11</sup> 4.54 *μm* 2.19 *μm vbnc* 0.0579 *V* 0.001 *V vbpc* -0.0408 *V* -0,0449 *V ib* 36.78 *μA* 48.51 *μA*

**Table 6.** Free variables and final results found for the folded-cascode amplifier optimization.

stage.

similar circuits and design objectives.

dissipated power is 133.2*μW*. The advantages of this approach is that the resulting circuit is already validated by electrical simulations and does not need to be verified in another design

We can make a direct comparison of the results obtained by this work using SA with other approaches, such as the tools that use genetic algorithms as main optimization heuristic. Although it is difficult to perform a fair comparison with other works in the literature, mainly because the experimental setup in general can not be reproduced with the provided information and there is no standard benchmarks in analog design automation, it is still interesting to compare the general performance of our methodology with other results over

In this sense, the results presented by [3] with the GENOM tool are passible to comparison, because the same experimental setup can be reproduced - although some implementation details are not available, such as the parameters of the electrical model. This tool is based on a variation of genetic algorithm as the main optimization heuristic. The folded cascode was implemented in UMC 0.18*μm* technology. The final results obtained by GENOM for the same

We can see that both methodologies present similar results for the design constraints. By the other side, both power dissipation and gate area depicted by our approach using Simulated Annealing are about half the final values provided by GENOM. Power dissipation was decreased in 45.5% and gate area in 49%, a great improvement in circuit performance. These results prove that SA is a powerful heuristic for the design of micro-power operational

circuit synthesized by our approach are summarized in the fiftieth column of Tab. 7.

**Figure 14.** Schematics of a CMOS folded cascode amplifier.

The modeling of this circuit for the proposed optimization process is simple and similar to the previous described modeling of the differential amplifier. The SPICE netlist and the testbench are the information necessary to describe the circuit and bias. The specifications are simulated by an external electrical simulator (HSpice), which returns, for a given set of variables, the electrical characteristics of the circuit. In our design there are 15 free variables, summarized in Tab. 6. It leads to a very large 15-dimensional design space, which is difficult to explore and find the minimum cost value. It is possible to limit the design space inserting constraints in the cost function related to the operation region of each transistor, forcing the devices to operate at saturation (*VDS* > *VGS* − *VT*) and strong inversion (*VGS* > *VT*) regions. The specifications and design goals for this circuit are shown in Tab. 7. In the output is connected a capacitive load of 3*pF*. We expect to size the circuit optimizing gate area and power dissipation while maintaining the constraints of GBW, low-voltage gain, phase margin and slew rate inside a given range.

Using Boltzman for both temperature schedule function and state generation function, followed by local search with interior point algorithm, we find the final results shown in the third and fourth columns of Tab. 7 for global and global followed by local searches, respectively. It is possible to note that all design objectives were reached, while keeping all devices in the specified operation region. There is an improvement in the multi-objective design goal with the post-processing local search. The final gate area is 145.13*μm*<sup>2</sup> and 20 Will-be-set-by-IN-TECH

In order to apply simulated annealing in a more realistic and practical operational amplifier, we syntesized a folded cascode in CMOS IBM 0.18*μm*, regular *Vt*, 1.8*V* technology node. The

M5 M6

*W*5, *L*<sup>5</sup> *W*5, *L*<sup>5</sup>

*VDD*

M7 M8

*vbpc*

*W*7, *L*<sup>7</sup> *W*7, *L*<sup>7</sup>

M9 M10

*W*9, *L*<sup>9</sup> *W*9, *L*<sup>9</sup>

*ib*

Mbp

*Vout*

**5. Operational amplifier design**

*ib*

given range.

schematics of this amplifier is shown in Fig. 14.

M1 M2

*W*1, *L*<sup>1</sup> *W*1, *L*<sup>1</sup>

M4

**Figure 14.** Schematics of a CMOS folded cascode amplifier.

Mbn M11 M12

*vbnc Vin*<sup>+</sup> *Vin*<sup>−</sup>

*W*<sup>4</sup> *W*<sup>4</sup> , *L*<sup>4</sup> , *L*<sup>4</sup> *W*11, *L*<sup>11</sup> *W*11, *L*<sup>11</sup>

*VSS*

The modeling of this circuit for the proposed optimization process is simple and similar to the previous described modeling of the differential amplifier. The SPICE netlist and the testbench are the information necessary to describe the circuit and bias. The specifications are simulated by an external electrical simulator (HSpice), which returns, for a given set of variables, the electrical characteristics of the circuit. In our design there are 15 free variables, summarized in Tab. 6. It leads to a very large 15-dimensional design space, which is difficult to explore and find the minimum cost value. It is possible to limit the design space inserting constraints in the cost function related to the operation region of each transistor, forcing the devices to operate at saturation (*VDS* > *VGS* − *VT*) and strong inversion (*VGS* > *VT*) regions. The specifications and design goals for this circuit are shown in Tab. 7. In the output is connected a capacitive load of 3*pF*. We expect to size the circuit optimizing gate area and power dissipation while maintaining the constraints of GBW, low-voltage gain, phase margin and slew rate inside a

Using Boltzman for both temperature schedule function and state generation function, followed by local search with interior point algorithm, we find the final results shown in the third and fourth columns of Tab. 7 for global and global followed by local searches, respectively. It is possible to note that all design objectives were reached, while keeping all devices in the specified operation region. There is an improvement in the multi-objective design goal with the post-processing local search. The final gate area is 145.13*μm*<sup>2</sup> and


**Table 6.** Free variables and final results found for the folded-cascode amplifier optimization.

dissipated power is 133.2*μW*. The advantages of this approach is that the resulting circuit is already validated by electrical simulations and does not need to be verified in another design stage.

We can make a direct comparison of the results obtained by this work using SA with other approaches, such as the tools that use genetic algorithms as main optimization heuristic. Although it is difficult to perform a fair comparison with other works in the literature, mainly because the experimental setup in general can not be reproduced with the provided information and there is no standard benchmarks in analog design automation, it is still interesting to compare the general performance of our methodology with other results over similar circuits and design objectives.

In this sense, the results presented by [3] with the GENOM tool are passible to comparison, because the same experimental setup can be reproduced - although some implementation details are not available, such as the parameters of the electrical model. This tool is based on a variation of genetic algorithm as the main optimization heuristic. The folded cascode was implemented in UMC 0.18*μm* technology. The final results obtained by GENOM for the same circuit synthesized by our approach are summarized in the fiftieth column of Tab. 7.

We can see that both methodologies present similar results for the design constraints. By the other side, both power dissipation and gate area depicted by our approach using Simulated Annealing are about half the final values provided by GENOM. Power dissipation was decreased in 45.5% and gate area in 49%, a great improvement in circuit performance. These results prove that SA is a powerful heuristic for the design of micro-power operational

#### 22 Will-be-set-by-IN-TECH 282 Simulated Annealing – Single and Multiple Objective Problems Simulated Annealing to Improve Analog Integrated Circuit Design: Trade-Offs and Implementation Issues <sup>23</sup>


**7. References**

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**Table 7.** Design performance and final results found by the optimization process for the folded-cascode amplifier.

amplifiers. Again, it is important to note that the comparison between the results can not be exact because some parameters in the device electrical model and other configurations are not equal. The final values for the free variables are shown in Tab. 6. We can see that the gate widths of the transistors trend to be larger than the gate lengths and that the magnitudes are similar in both approaches.
