**8. Objectives and cost function**

252 Simulated Annealing – Single and Multiple Objective Problems

The move changes the order of a module in *Γ<sup>i</sup>*

**7. Crossover operator for MSA** 

is changed from (0, 3) to (4, 2).

*Fi*

*Fi*

changed to *Γ-*

are the same solution.

the best layout so far (M: mother)

*Γ'm–* are the inverse of *Γm+* – *Γ<sup>f</sup>*

1), *k*–1], respectively.

*<sup>+</sup>*[*0, i*] + *Γ'm+* + *Γ<sup>f</sup>*

given by *Γ<sup>f</sup>*

respectively. For example, if the modules *m3* and the module *m5* are operated by the exchange in Figure 9, then (*F+*(*m5*), *F-*(*m5*)) is changed from (4, 2) to (0, 3), and (*F+*(*m3*), *F-*(*m3*))

(*mi*) is changed to another value, say *j*, and the orders of modules whose order is between

(*mi*) and *j* are shifted accordingly. For example, , if the operation is to move *m5* to *F-*(*m5*) *=* 0

Besides, a special crossover operator is designed to generate a new solution from the current solution and the best solution so far in the rough search based on the representation in section 5.2. The margin and centre of the new solution (child) inherit the margin of the current solution (father) and the reversed centre of the best solution (mother), respectively. The reason to reverse the best solution is to get a different solution even two given solutions

**Figure 11.** An example of two layouts before the crossover operator: the current layout (F: father) and

For the detail of crossover, two sequences *Γ+* and *Γ–* are selected randomly from (*Γ1, Γ2, Γ3*) or

the current solution. The mother (*Γm<sup>+</sup>*, *Γm–*) is from the best solution so far. A number *i* is an

integer randomly produced between 1 and *k/2*–1. The child of sequence pair (*Γ<sup>c</sup>*

*<sup>+</sup>*[(*k*–*i*–1), *k*–1] and *Γ<sup>f</sup>*

*<sup>+</sup>*[*0, i*] – *Γ<sup>f</sup>*

*<sup>+</sup>*, *Γ<sup>f</sup>*

*<sup>+</sup>*[(*k*–*i*–1), *k*–1] and the inverse of *Γm–* – *Γ<sup>f</sup>*

*–*[*0, i*] + *Γ'm–* + *Γf –*[(*k*–*i*–1), *k*–1], where *Γ'm+* and

*–*) which is selected from

*–*[*0, i*] – *Γ<sup>f</sup>*

*<sup>+</sup>*, *Γ<sup>c</sup> –*) is

*–*[(*k*–*i*–

(*Γ1, Γ2, Γ3, Γ4*, *Γ5*) for 3D packing. Let us denote the father as (*Γ<sup>f</sup>*

in *Γ -*, the move will lead to *F-*(*m1*) *= F-*(*m1*) *+* 1 and *F-*(*m2*) *= F-*(*m2*) *+* 1, i.e.*Γ-*

(*m5, m1, m2, m3, m4*) as shown in Figure 10.

. When a move is applied to module *mi* in *Γ<sup>i</sup>*

,

(*m1, m2, m5, m3, m4*) is

To solve multi-objective problem, we are using the total cost function, which includes area of bounding rectangle for 2D case, volume of bounding box for 3D case, interconnect power and maximal delay. Especially, the interconnect power and the maximal delay are two typical conflicting objectives, which need to experiment carefully to satisfy the requirements in real product design.

For the multi-objective optimization of 2D placement in this research, three different objectives are defined by one formula as follow.

$$\mathbf{C} = \alpha \cdot \mathbf{C}\_{\mathcal{P}} + \boldsymbol{\beta} \cdot \mathbf{C} \boldsymbol{u} + \boldsymbol{\mathcal{Y}} \cdot \mathbf{C}\_{\mathcal{u}} \tag{2}$$

where *α+β+γ=1*, and *Ct* is the total cost function, which includes the power function *Cp*, the delay function *Cd* and the area function *Ca*. And α, *β, γ* can be user-defined. As mentioned, *Cp* and *Cd* are normally conflicting in real implementation. That is to say, good *Cp* may lead to bad *Cd*, so we have to consider the trade-off between *Cp* and *Cd* using a lot of random values of α and *β*.

For power estimation, the dynamic power of a net *ni* is proportional to *C(i)*, *Vdd(i)2*, *f(i)* and *S(i)*, where *C(i)* is the capacitance of a net, *Vdd(i)* is the voltage of power supply, *f(i)* is the clock frequency, and *S(i)* is switching probability of the net. Normally *C(i)* is proportional to the length of net, so let *Leni* represent its value. In case of no information, let us assume that *Vdd(i)* and *f(i)* are same for each net and *S(i)* is randomly defined from 0 to 1. So the interconnect power is simplified as the function of *Leni* and *S(i)*.

A Simulated Annealing Based Approach to Integrated Circuit Layout Design 255

For interconnect optimization of 2D placement, let γ be 0 and α+β be 1 in the cost function. The experiment is using ami49\_X benchmarks. To get the figures, α is randomly produced from 0.1 to 0.9. 240 solutions are tested for comparison. For all tested ami49\_X with X from 1 to 12, block number from 49 to 588, and net number from 408 to 4896, the improved results are gotten. Figure 13 shows that MSA obtains at least 13% Pareto improvement with the constraint of less than 108.2% maximal delay. To get the worst cases, we tested more 120 solutions with α given by 0.1, 0.3, 0.5, 0.7, and 0.9. As shown in Figure 14, MSA got near 6% worst-case mitigation on average for the interconnect power with no degradation of

**Benchmarks Best (mm2) Average (mm2) Worst (mm2) Runtime (s)** 

apte 47.08 47.36 47.67 3.2 xerox 19.80 20.50 21.21 1.5 hp 9.03 9.17 9.34 2.3 ami33 1.18 1.23 1.29 17 ami49 36.91 37.79 38.83 37 ami49\_2 73.58 75.48 77.38 142 ami49\_4 147.3 151.1 155.8 547

**Benchmarks Solution(mm2) Runtime (s) Improvement (%)** 

apte 47.38 47.36 4.1 3.2 0.04% 22% xerox 20.51 20.50 1.9 1.5 0.05% 21% hp 9.18 9.17 2.7 2.3 0.11% 15% ami33 1.24 1.23 22 17 0.52% 23% ami49 37.96 37.79 45 37 0.48% 18% ami49\_2 75.98 75.48 194 142 0.71% 27% ami49\_4 152.2 151.0 720 547 0.88% 24%

SA MSA SA MSA **Solution Runtime** 

**Table 1.** Area optimization by MSA for 2D packing

**Table 2.** Average improvement of area for 2D packing

maximal delay.

For performance estimation, the maximal delay among all nets is used. The delay is defined by the wire length of nets. To get the wire length estimation for each net, the half perimeter wire length (*HPWL*) is used for the approximation of wire length. Given any net *ni*, connected with modules {*m1, m2, ..., ms*}, *HPWL* is half perimeter of the minimum bounding box for all centres of module *mi*, where *i* is an integer from *1* to *s*. In case of *ri*=1, *HPWL*[*ni*] is given by *max*[*xi + hi/2*] *– min*[*xi + hi/2*] *+ max*[*yi + wi/2*] *– min*[*yi + wi/2*]. So *HPWL*[*ni*] is gotten from (*hi, wi, ni*)*,* (*xi, yi, ri*). The power and the delay are estimated so far.

For the objective of 2D packing, the area estimation is the minimum bounding rectangle including all modules, which is the total height *H* multiplied by the total width *W*. In practical implementation, we use a relative value as the cost function of area, i.e. the bounding area divided by the area of total modules, because any value with unit would not be scalable to use the experiments by diverse benchmarks.

For the objective of 3D packing, instead of 2D case, the volume estimation is given by the minimum bounding rectangular parallelepiped including all modules, which is the total height *H* multiplied by the total width *W* and multiplied by the total length *L*. In real implementation, the cost function is also using the relative value of volume.
