**3.1. Cell placement problem**

8 Simulated Annealing – Single and Multiple Objective Problems

���� =��������������� = ∑ ��������

�

The total format of MFA for various kind of problem is represented as:

3.1.2. Compute mean field vector corresponding to the *ith* spin: ��� = − ��(�)

���

Inside the algorithm some notes must be considered. Selection of initial temperatures is crucial for obtaining good quality solutions. Typically spin averages initialize with an equal values plus a small disturbing part that is randomly valued but this is not an eternal rule. Adding this disturbing part causes the spins exit their stable states and their movement starts. Selecting balance factors in energy function has important role for efficiency of the

3.1.4. Compute new spin average vector: ���(���) = ����/�/ ∑ � � ���/� ��� 3.1.5. Compute new spin average vector: �� = ∑ ����(���(���) − ���) �

state for a given temperature.

scheme could be used.

be accepted is reduced.

**2.5. Total MFA algorithm** 

3.1. While *E* is decreasing DO: 3.1.1. Select the *ith* spin randomly.

algorithm.

1. Get the initial temperature *T0*, and set *T* = *T0* 2. Initialize the spin averages *V=[v11,…, vik,…,*���� *]* 3. While temperature *T* is in the cooling range DO:

3.1.3. Compute the summation: ∑ � � ���/� ���

3.2. Decrease the temperature: � = �� � � ��

3.1.6. Update the spin average vector: ���(���) = ���

observed after each spin vector update in order to detect the convergence to an equilibrium

If the total energy does not decrease in most of the successive spin vector updates, this means that the system is stabilized for that temperature. Then, *T*is decreased according to the cooling schedule by a decreasing factor and the iterative process restarted again with new temperature. To reduce the complexity of energy difference computation an efficient

Depending to complexity of problem, the cooling program could be in one stage or more stages in order to reach faster and better result. In some problems like circuit partitioning

Actually cooling schedule controls amount of acceptable cost increasing moves and the efficiency of the algorithm. Clearly for very large temperatures almost any change will be accepted while as the temperature is reduced the chance that a positive cost change will also

problem the applied cooling schedule is simply in one stage (�� is decreasing factor):

��� where����� = ���(���) − ����(���) (11)

���� =����� ���������� < �� < 1 (12)

����

Placement is the process of determining the locations of circuit devices on a die surface. ItisanimportantstageintheVLSIdesignflowbecauseitaffectsroutability, performance, heat distribution, and to a less extent, power consumption of a design.

Traditionally, it is applied after the logic synthesis stage and before the routing stage. Since the advent of deep submicron process technology around mid-1990, interconnect delay, which is largely determined by placement, has become the dominating component of circuit delay. As a result, placement information is essential even in early design stages to achieve better circuit performance.

The circuit is presented with a hyper-graph Ω(C, N), that consists of a set C representing the cells circuit, a cell weight function of the circuit, a hyper-edge set *N* representing the nets of the ߱ǣ ܥ ՜ ࣨand a net weight function ߱௧ǣܰ՜ࣨ where ࣨ represents the set of natural numbers. Space of circuit is a rectangular grid of clusters with P rows and Qcolumns where the cells will be placed.

**Figure 2.** Cell location on spin space configuration

As presented before in the K-state Potts model of S spins, the states of spins re represented using S K-dimensional vectors. To apply MFA technique for cell placement problem the circuit layout space is mapped to a grid space with *P* rows and *Q* columns. If the number of

cells be CL, the number of spins that encode the configuration of problem is *CL (P × Q)* dimensional Potts spins so there would be a total of |CL|*×*P*×*Q two-state variables. To decreasing the number of spins that encode the configuration of problem, they are separated to two types: row and column spins. Therefore there would be *P* row spins and *Q* column spins and totally |CL|*×* (*P+Q*) spins[14].For example for a circuit space with 2 rows and 3 columns if the row spin vector of *ith* cell is ��� � = �0,1� and its column spin vector is ��� � = �0,0,1� that means this cell is located at second row and third column of configuration space as Fig. 2.

Mean Field Annealing Based Techniques for Resolving VLSI Automatic Design Problems 11

the perimeter of this box is taken as the net's interconnect length approximation. The *half perimeter wire length* (HPWL) estimation for minimally routed two and three port nets gives

Our method executes local relocation on a model placement where an additional module is added to it for modification with minimum number of displacement. The model placement is a given placement of the circuit that needs modification. MFA based method resolves the problem in less time and hardware in compare to SA-based method. In addition, the runtime of solution is mostly independent of size and complexity of input model placement. Our proposed MFA algorithm is optimized by adding the ability of rotation of modules inside an energy function called *permissible distances preservation energy* that will be defined at section 3.2.6. This in turn allows more options in moving the engaged modules. Finally, a three-phase cooling process governs convergence of problem variables called neurons or

**Input**: A model placement including a set of modules and a net list or hypergraph representation of circuit, the additional module with its coordinates and the incident

**Objective**: Fast relocation with minimum number of displacements and more similarity

There are four classified approaches to the problem of inserting an extra module into a

i. The additional elements are inserted into unoccupied "whitespace" areas as much as

ii. Before additional logic elements are inserted, an effort is made to predict the amount of whitespace area required; this whitespace is distributed over the chip. If the prediction is accurate (or conservative), the added elements can be placed within the available

iii. The third approach is to simply insert or resize the required logic elements, and begin

iv. The fourth approach is to insert additional logic elements without considering

Our approach matched the fourth approach above. The MFA relocation algorithm removes overlaps by moving or rotating modules. Note that all of the movements and rotations must observe some permissible distances that will be explained in the following sections. Feasibility of problem depends on topology of placement and similarity. It is clear that

**Constraint**: No overlap between modules and preservation of permissible distances

an exact value.

spins.

nets.

model placement.

possible.

space.

overlaps.

**3.2. Local relocation using MFA technique** 

The relocation problem is formulated as follows:

the optimization process from scratch.

**Output**: Local relocated placement
