**1. Introduction**

238 Simulated Annealing – Single and Multiple Objective Problems

*Biomechanics*, Vol. 30, No. 6, pp. 555-563.

optimization. M. Phil, Thesis, University of Cambridge.

*1160.*

33, pp. 59.

5, pp. 399-407.

Vol. 80, pp. 146-158.

40, pp. 2377-2385.

301.

Suman, B. & Kumar, P. (2006). A survey of simulated annealing as a tool for single and multi-objective optimization. *Journal of the Operational Research Society, Vol. 57, pp. 1143-*

Suppapitnarm, A., Seffen, K.A., Parks, G.T. & Clarkson, P.J. (2000). Simulated annealing: an alternative approach to true multiobjective optimization. *Engineering Optimization*, Vol.

Suppapitnann, A. (1998). A simulated annealing algorithm for multiobjective design

Turner, C.H., Anne, V. & Pidaparti, R.M.V. (1997). A uniform strain criterion for trabecular bone adaptation: do continuum level strain gradients drive adaptation?. *Journal of* 

Turner, C.H. (1998). Three rules for bone adaptation to mechanical stimuli. *Bone*, Vol. 23, No.

Wang, F., Lee, H.P. & Lu, C. (2007). Thermal-mechanical study of functionally graded dental implants with the finite element method. *Journal of Biomedical Materials Research - Part A*,

Watari, F., Yokoyama, A., Omori, M., Hirai, T., Kondo, H., Uo, M. & Kawasaki, T. (2004). Biocompatibility of materials and development to functionally graded implant for bio-

Weinans, H., Huiskes, R., & Grootenboer, H.J. (1992). The behavior of adaptive bone remodeling simulation models. *Journal of Biomechanics*, Vol. 25, No. 12, pp. 1425–1441. Yang, J. & Xiang, H.J. (2007). A three-dimensional finite element study on the biomechanical behavior of an FGBM dental implant in surrounding bone. *Journal of Biomechanics*, Vol.

Zitzler, E. & Thiele, L. (1998). Multiobjective optimization using evolutionary algorithms: a comperative case study. *Parallel Problem Solving from Nature V*, Vol. 1498/1998, pp. 292-

medical application. *Composites Science and Technology*, Vol. 64, pp. 893-908.

The optimization techniques for integrated circuit (IC) layout design are important. Generally speaking, the basic process of modern hardware engineering includes designing, manufacturing and testing. IC layout is an inevitable stage of designing before manufacturing. There are many applications which are directly related with layout optimization in practice, such as floor plan for very-large-scale integration (VLSI) design, placement for printed circuit board (PCB) design, packing for logistics management, and so on. In this research, we mainly focus on the optimization for three layout problems, which are 2D packing, 3D packing and 2D placement. The 2D/3D packing is to position different modules into a fixed shape, normally rectangular one, with area or volume minimization. The placement can be regarded as the packing problem with interconnect optimization. Since a general placement problem is NP-hard, there are no practical exact algorithms so far to be sure to find optimal solutions. As an alternative to get the optima, heuristics [1-6] are typically used to find near optimal solutions within a given runtime.

As product size keeps shrinking, product lifecycle keeps shortening and product complexity goes up, more electronic components will be integrated into a smaller IC chip or PCB with higher density and shorter time to market. At the same time, multi-objective optimization is common for IC/PCB layout in real product design, so another difficulty is the trade-off between conflicting objectives, such as low power and high performance. Pareto improvement for multiple objectives is one of the biggest challenges we have to face nowadays. The layout problem becomes much harder to find near-optimal or even acceptable solutions with high requirements. In order to improve the best cases and mitigate the worst cases of IC/PCB layout, it becomes increasingly critical and urgent to improve the quality of solution and reduce runtime.

Simulated annealing based algorithm with a good representation for 2D/3D packing is one of the most popular ways to improve the quality of solution. On the one hand, many

© 2012 Sheng and Takahashi, licensee InTech. This is an open access chapter distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. © 2012 Sheng and Takahashi, licensee InTech. This is a paper distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

researches explored different representations [7-12], such as bounded-slice-line grid, sequence pair, FAST sequence pair, Q-sequence, selected sequence pair, etc. In order to code and decode 3D-packing problem, sequence pair for 2D packing is extended to sequence triple and sequence quintuple, and it has been proved that sequence triple could represent the topology of the tractable 3D packing and there are at least one sequence quintuple which can be decoded to a topology as an optimal packing for volume minimization. But the effectiveness to improve solution quality and reduce runtime is quite limited due to huge solution space and complex solution distribution, even if a very good representation is used. The experimental results within a short runtime are still far from near-optimal solutions in real implementation to solve the packing problem. So it is the right time to explore new algorithms in order to solve 2D/3D problem more effectively.

A Simulated Annealing Based Approach to Integrated Circuit Layout Design 241

annealing algorithm in 1983. The annealing is to heat up a solid with a very high temperature and then to cool it down slowly until it reaches or approaches its minimum energy state. Each state of solid represents a feasible solution of problem. The energy of the state is the value of cost function to evaluate the solution. The state with the lowest energy corresponds to the optimal solution with the best value of cost function. SA is a stochastic algorithm with iterative improvement. Each iterative step consists of changing current solution to a new solution, named a move to neighbourhood. The acceptance probability of new solutions depends on the current temperature, which is scheduled from the highest temperature to the lowest temperature. An important point we have to mention here is that, if the physical process is to cool the solid down very quickly, it is known as quenching, instead of annealing. The difference between normal simulated annealing and simulated

In detail, let *S* be the solution space with neighbourhood structure. For any solution S belongs to *S*, we define the cost function *C*(S), i.e. the total cost function (*Ct*) for multiobjective placement problem. A non-optimal solution S is defined by local optimum, if it can not reach better solution by moving to any neighbouring solution S′. That is to day, for any neighbour solution (S′) of local optimal solution (S), the inequality *C*(S) < *C*(S′) is always satisfied. The depth *D*(S) of local optimal solution is defined by the maximum value such that *D*(S) + *C*(S) > *C*(S′). The maximum depth of local optimal solution in *S* is denoted by d(*S*). Let *X*(*Ti*) be a variable of the cost function C(S) at each temperature *Ti*, where *i* is 0, 1, 2, … . Let *Copt* be the minimum cost function. According to [2], the equality lim*<sup>i</sup>*→<sup>∞</sup> *X*(*Ti*) = *Copt* is satisfied with the following conditions: (1) The solution space *S* is finite and irreducible; (2) There exists an equilibrium distribution for the transition probability matrix; (3) *Ti* ≥ *Ti+1*

In real implementation with a given finite runtime, we are using a fast geometric simulated quenching scheduling (*Tk+1 = qTk, 0<q<1*) with repeated inside loop (*p* times) to enhance the

0

where *i* is the iterative step, *Ti* is the variable temperature at the *ith* step, *T0* is the initial temperature when *i* = 0, *p* is the inside loop number and *q* the temperature coefficient near

As shown in Figure 1, it is a typical flow chart of SA, which is used for layout optimization in this research. The initial solution is randomly produced or simply follows past layout designs. The temperature scheduling is used to change the current temperature (*T*). The parameters of the temperature scheduling include the starting temperature *T0*, the ending temperature *Te*, a temperature coefficient and an inside loop number. One of moving methods is selected with given probabilities, for example, the same probability for each moving method in real experiment (near 33% in the case of three moving methods). A new solution is tried by using the current selected moving method. The new solution is evaluated by a cost function (*C*) and compared with the old one. The new solution is

/

*i p*

*<sup>i</sup> T Tq* = ⋅ (1)

quenching is the parameter setting of temperature scheduling.

and *Ti* > 0 for all *i*; (4) lim*<sup>i</sup>*→<sup>∞</sup> *Ti* = 0; (5) *∑<sup>i</sup>*:∈(0, ∞) [exp(-d(*S*)/*Ti*)] = ∞.

efficiency of standard SA [3] as the following equation.

but less than 1.

There are many significant shortcomings of traditional heuristics for IC layout optimization. Let us take simulated annealing (SA) and genetic algorithm (GA) as an example. For SA, firstly, some slight modifications of solution are repeated to get a good convergence. Therefore, the global search is inefficient in general. It is disadvantageous to solve the problem with huge solution space, such as VLSI design. Secondly, SA does not use the past experience, including past good solutions and past moves, and it is a big informational waste. To speed up SA, some researchers [4] proposed two-stage SA for VLSI design. But the search speed is still quite slow, and it is not seriously considered to avoid or reduce informational waste. For GA, it evaluates too many candidates in order to get next generations. The evaluation takes too much runtime. Besides GA selects the next generation according to a ranking function, which is not always necessary but takes much time. So it is possible to improve the solution quality or reduce runtime if we can overcome the mentioned shortcomings.

In this research, a simulated annealing based approach [13-14], named mixed simulated annealing (MSA), is proposed to improve solution quality and reduce runtime by overcoming the shortcomings of inefficient global search and informational waste. In mixed simulated annealing, a special crossover operator is designed to use a part of information from past good solutions and get higher improving efficiency, and the solutions gotten by the crossover are much better than random solutions. To evaluate the effectiveness and the reliability of the proposed mixed simulated annealing, we apply it to three mentioned optimization problems, i.e. 2D packing, 2D placement and 3D packing, and get considerable improvement for all three problems. The experimental results show the runtime, the packing ratio of area for 2D packing, the packing ratio of volume for 3D packing and two more objectives (low power and short maximal delay) for 2D placement are improved considerably by using MCNC, ami49\_X and ami98\_3D benchmarks. For example, the runtime of mixed simulated annealing with sequence quintuple representation is up to 4 times faster than that of 2-stage SA with the same representation, and the packing ratio of volume is improved by up to 12% within 100s runtime.
