**Author details**

Lucas Compassi Severo, Alessandro Girardi,Alessandro Bof de Oliveira, Fabio N. Kepler and Marcia C. Cera *Federal University of Pampa – UNIPAMPA, Alegrete Campus Av. Tiaraju, 810, CEP 97546-550, Alegrete-RS, Brazil*

282 Simulated Annealing – Single and Multiple Objective Problems Simulated Annealing to Improve Analog Integrated Circuit Design: Trade-Offs and Implementation Issues <sup>23</sup> Simulated Annealing to Improve Analog Integrated Circuit Design: Trade-Off s and Implementation Issues 283

## **7. References**

22 Will-be-set-by-IN-TECH

Specification Objective Global (SA Boltz) Global+Local GENOM ([3])

**Table 7.** Design performance and final results found by the optimization process for the folded-cascode

amplifiers. Again, it is important to note that the comparison between the results can not be exact because some parameters in the device electrical model and other configurations are not equal. The final values for the free variables are shown in Tab. 6. We can see that the gate widths of the transistors trend to be larger than the gate lengths and that the magnitudes are

The design of analog integrated blocks and the search for an optimum design point in a highly non-linear design space evolve different approaches and choices. Simulated Annealing and its variations are a good option for the exploration of this kind of problem. This chapter presented some implications of the algorithm tuning over the final results. We could demonstrate that the correct configuration of SA options can lead to good solutions near the optimality in reasonable execution time. Although it is not clear that some configuration is suitable for sizing all types of analog blocks, it is possible to notice that the approach is correct and, with minimum adjusts for different circuits, SA can be used as a general optimization algorithm, providing good solutions. A direct comparison with a tool based on genetic algorithms for the synthesis of a folded cascode operational amplifier showed that better results can be obtained with the correct design space exploration with SA. As future work, the analysis of parameter variation in the optimization methodology for design centering must be

We would like to thank CNPq and Fapergs Brazilian agencies for supporting this work.

*Federal University of Pampa – UNIPAMPA, Alegrete Campus Av. Tiaraju, 810, CEP 97546-550, Alegrete-RS, Brazil*

Lucas Compassi Severo, Alessandro Girardi,Alessandro Bof de Oliveira, Fabio N. Kepler and

amplifier.

similar in both approaches.

**6. Conclusion**

implemented.

**Acknowledgements**

**Author details**

Marcia C. Cera

GBW >12MHz 14.86 MHz 14.98 MHz 15.35 MHz Av0 > 70dB 73.04 dB 70dB 70.61dB PM > 55◦ 76.87◦ 78.76◦ 79.6◦ SR > 10*V*/*μs* 10.98*V*/*μs* 11.37*V*/*μs* 15.36*V*/*μs* Area minimize 188.25*μm*<sup>2</sup> 145.13*μm*<sup>2</sup> 284.7*μm*<sup>2</sup> Power minimize 129.9*μW* 133.2*μW* 244.6*μW*


URL: *http://doi.ieeecomputersociety.org/10.1109/43.905672*

	- [17] Nye, W., Riley, D. C., Sangiovanni-Vincentelli, A. L. & Tits, A. L. [1988]. DELIGHT.SPICE: an optimization-based system for the design of integrated circuits, *IEEE Trans. on CAD of Integrated Circuits and Systems* 7(4): 501–519. URL: *http://doi.ieeecomputersociety.org/10.1109/43.3185*
	- [18] Press, W., Teukolsky, S., Vetterling, W. & Flannery, B. [2007]. *Numerical Recipes: The Art of Scientific Computing*, 3rd edn, Cambridge University Press, New York, chapter Section 10.11. Linear Programming: Interior-Point Methods.
	- [19] Razavi, B. [2000]. *Design of Analog CMOS Integrated Circuits*, 1st edn, McGraw-Hil.
	- [20] Szu, H. & Hartley, R. [1987]. Fast simulated annealing, *Physical Letters A* 122: 157–162.
	- [21] Vytyaz, I., Lee, D. C., Hanumolu, P. K., Moon, U.-K. & Mayaram, K. [2009]. Automated design and optimization of low-noise oscillators, *Transactions on Computer-Aided Design of Integrated Circuits and Systems* 28(5): 609–622.

24 Will-be-set-by-IN-TECH

[17] Nye, W., Riley, D. C., Sangiovanni-Vincentelli, A. L. & Tits, A. L. [1988]. DELIGHT.SPICE: an optimization-based system for the design of integrated circuits, *IEEE Trans. on CAD of*

[18] Press, W., Teukolsky, S., Vetterling, W. & Flannery, B. [2007]. *Numerical Recipes: The Art of Scientific Computing*, 3rd edn, Cambridge University Press, New York, chapter Section

[19] Razavi, B. [2000]. *Design of Analog CMOS Integrated Circuits*, 1st edn, McGraw-Hil. [20] Szu, H. & Hartley, R. [1987]. Fast simulated annealing, *Physical Letters A* 122: 157–162. [21] Vytyaz, I., Lee, D. C., Hanumolu, P. K., Moon, U.-K. & Mayaram, K. [2009]. Automated design and optimization of low-noise oscillators, *Transactions on Computer-Aided Design*

*Integrated Circuits and Systems* 7(4): 501–519.

284 Simulated Annealing – Single and Multiple Objective Problems

URL: *http://doi.ieeecomputersociety.org/10.1109/43.3185*

10.11. Linear Programming: Interior-Point Methods.

*of Integrated Circuits and Systems* 28(5): 609–622.
