**4.1. Case study: Differential amplifier**

A differential amplifier is a basic analog building block used in general as the input stage of operational amplifiers. Perhaps its simplicity, it is very useful as a first voltage

**Figure 2.** Cost function performance metrics: (a) minimum required value specifications and (b) maximum required value specifications.

6 Will-be-set-by-IN-TECH

Simulated Anneling core

Temperature Reduction

**Figure 1.** Analog integrated circuit sizing with Simulated Annealing flow.

**4. Basic analysis of the search space**

**4.1. Case study: Differential amplifier**

discussed in Sec. 4.3 .

No

This section presents a simple case study, a differential amplifier, to introduce and explain the usage of Simulated Annealing to automate the design of analog integrated circuit. Section 4.1 describes the features of the differential amplifier. Sec. 4.2 explains the modeling of the differential amplifier that allows its simulation and the usage of the SA. Finally, to improve the automation process, some optimization options on SA are applied and their results are

A differential amplifier is a basic analog building block used in general as the input stage of operational amplifiers. Perhaps its simplicity, it is very useful as a first voltage

Random Initial Solution Generation

Initialize Temperature

Nest Solution Generation

Cost Function Evaluation

> Electrical Simulation

Acceptance Testing

Stop condition satisfied?

End: Circuit Designed

Yes

Design Constraints

Technology File

SA Options

amplification stage of many electronic devices and has become the dominant choice in today's high-performance analog and mixed-signal circuits [19]. Ideally, it amplifies the difference between two voltages but does not amplify the common-mode voltages. An implementation of the differential amplifier with CMOS transistors and active load is shown in Fig. 3 . It is composed by a differential pair formed by two input transistors (*M*1 and *M*2), an active current mirror (*M*3 and *M*4) and an ideal tail current source *Iref* . The output voltage *Vout* depends on the difference between the input voltages *Vin*<sup>1</sup> and *Vin*2. For a small difference between *Vin*<sup>1</sup> and *Vin*2, both *M*2 and *M*4 are saturated, providing a high gain. Otherwise, if |*Vin*<sup>1</sup> − *Vin*2| is large enough, *M*1 or *M*2 will be off and the output will be stuck at 0*V* or at *VDD*.

The output voltage of the differential amplifier can be expressed in terms of its differential-mode and common-mode input voltages as

$$V\_{out} = A\_{VD}(V\_{in1} - V\_{in2}) \pm A\_{V\mathbb{C}} \left(\frac{V\_{in1} + V\_{in2}}{2}\right) \tag{8}$$

where *AVD* is the differential-mode voltage gain and *AVC* is the common-mode voltage gain. An ideal operational amplifier has an infinite *AVD* and zero *AVC*. Although practical implementations try to find an approximation to these values, the implementation of physical circuits insert some non-idealities that limit *AVD* and *AVC*.

Another important characteristic of a differential amplifier is the input common-mode range (*ICMR*). We can estimate ICMR by setting *Vin*<sup>1</sup> = *Vin*<sup>2</sup> and vary input common-mode voltage (DC component of *Vin*<sup>1</sup> and *Vin*2) until one of the transistors in the circuit is no longer saturated [2]. The highest common-mode input voltage (*ICMR*+) is

$$ICMR^{+} = V\_{DD} - V\_{SG3} + V\_{TN1} \tag{9}$$

Here, *VSG*<sup>3</sup> is the source-voltage of transistor *M*3 and *VTN*<sup>1</sup> is the threshold voltage of *M*1. The lowest input voltage at the gate of *M*1 (or *M*2) is found to be

$$ICMR^{-} = V\_{SS} + V\_1 + V\_{GS2} \tag{10}$$

The voltage at node 1 (*V*1) is determined by the physical implementation of the current source *Iref* , which in general is a single transistor whose drain current is controlled by its gate voltage. *VGS*<sup>2</sup> is the gate-source voltage of transistor *M*2.

#### 8 Will-be-set-by-IN-TECH 268 Simulated Annealing – Single and Multiple Objective Problems Simulated Annealing to Improve Analog Integrated Circuit Design: Trade-Offs and Implementation Issues <sup>9</sup>

The small-signal properties of the differential amplifier can be accomplished with the assistance of the simplified model shown in Fig. 4, which ignores body effect. In this figure, *gm* is the gate transconductance given by the derivative of the drain current in relation to gate-source voltage:

$$\text{g}m = \frac{\partial I\_D}{\partial V\_{GS}}\tag{11}$$

*C*<sup>1</sup> = *Cgd*<sup>1</sup> + *Cbd*<sup>1</sup> + *Cbd*<sup>3</sup> + *Cgs*<sup>3</sup> + *Cgs*<sup>4</sup> (14) *C*<sup>2</sup> = *Cbd*<sup>2</sup> + *Cbd*<sup>4</sup> + *Cgd*<sup>2</sup> + *CL* (15) *C*<sup>3</sup> = *Cgd*<sup>4</sup> (16)

*Vgs*1(*s*) − *Vgs*2(*s*)

 *ω*<sup>2</sup> *s* + *ω*<sup>2</sup>

*GBW* = *Avo* · *<sup>ω</sup>*−3*dB* (21)

*<sup>C</sup>* (22)

*Wi* · *Li* (23)

 *ω*<sup>2</sup> *s* + *ω*<sup>2</sup>

(17)

(18)

(19)

(20)

Considering *C*<sup>3</sup> approximately zero, the voltage-transfer function can be written as

*gm*<sup>3</sup> *C*1

∼=

then the frequency response of the differential amplifier reduces to

and the capacitance from the output node to ac ground and is given by

product of gate width and lenght of all transistors that compose the circuit:

*Vout*(*s*) *Vin*1(*s*) − *Vin*2(*s*)

 *gm*<sup>3</sup> *gm*<sup>3</sup> + *sC*<sup>1</sup>

*<sup>ω</sup>*<sup>2</sup> <sup>=</sup> *gds*<sup>2</sup> <sup>+</sup> *gds*<sup>4</sup> *C*2

The pole *<sup>ω</sup>*<sup>2</sup> determines the cut-off frequency of the amplifier and is also called as *<sup>ω</sup>*−3*dB*.

� *gds*<sup>2</sup> <sup>+</sup> *gds*<sup>4</sup> *C*2

> *gm*<sup>1</sup> *gds*<sup>2</sup> + *gds*<sup>4</sup>

This first-order analysis leads to a single pole at the output given by −(*gds*<sup>2</sup> + *gds*4)/*C*2. Some zeroes occur due to *Cgd*1, *Cgd*<sup>2</sup> and *Cgd*4, but they can be ignored in this analysis. The gain-bandwidth product (GBW), which is the equal to the unity-gain frequency, can be

The slew-rate (SR) performance of the CMOS differential amplifier depends the value of *Iref*

*SR* <sup>=</sup> *Iref*

where C is the total capacitance connected to the output node (approximated by *C*<sup>2</sup> in our

Other important specifications for the electrical behavior of the differential amplifier includes power dissipation *Pdiss* = *Iref* · (*VDD* − *VSS*) and total gate area, calculated as the sum of the

All analog design has a target fabrication technology and a device type, in which the set of transistor model parameters is unique. These parameters determines the electrical characteristics - such as drain current, gate transconductance and output conductance - of the active devices that are part of the circuit. The specifications described before are function of these parameters, together with *W* and *L*. Since the parameters are fixed for a given fabrication

*Area* = ∑ *i*

Simulated Annealing to Improve Analog Integrated Circuit Design: Trade-Off s and Implementation Issues 269

*Vout*(*s*) <sup>∼</sup><sup>=</sup> *gm*<sup>1</sup>

where *ω*<sup>2</sup> is given as

Assuming that

expressed as

analysis).

*gds*<sup>2</sup> + *gds*<sup>4</sup>

The series resistance *rds* is the inverse of the output conductance *gds* and can be estimated in small-signal analysis as

$$\frac{1}{rds} = gds = \frac{\partial I\_D}{\partial V\_{DS}}\tag{12}$$

**Figure 3.** Schematics of a CMOS differential amplifier.

**Figure 4.** Simplified small-signal model for the CMOS differential amplifier.

The small-signal voltage gain *Avo*, *i.e.*, the relationship between *Vout* and the differential input voltage *Vin*<sup>1</sup> − *Vin*2, can be estimated in low frequencies by

$$A\_{v0} = \frac{gm\_1}{gds\_2 + gds\_4} \tag{13}$$

For higher frequencies, the voltage gain is modified due to the various parasitic capacitors at each node of the circuits, modeled by *C*1, *C*<sup>2</sup> and *C*3, which are calculated as follows:

268 Simulated Annealing – Single and Multiple Objective Problems Simulated Annealing to Improve Analog Integrated Circuit Design: Trade-Offs and Implementation Issues <sup>9</sup> Simulated Annealing to Improve Analog Integrated Circuit Design: Trade-Off s and Implementation Issues 269

$$\mathcal{C}\_1 = \mathcal{C}\_{\mathcal{S}^d 1} + \mathcal{C}\_{bd 1} + \mathcal{C}\_{bd 3} + \mathcal{C}\_{\mathcal{S}^{\mathfrak{S} 3}} + \mathcal{C}\_{\mathcal{S}^{\mathfrak{S} 4}} \tag{14}$$

$$\mathbf{C}\_2 = \mathbf{C}\_{bd2} + \mathbf{C}\_{bd4} + \mathbf{C}\_{gd2} + \mathbf{C}\_L \tag{15}$$

$$\mathcal{C}\_3 = \mathcal{C}\_{\mathcal{g}d4} \tag{16}$$

Considering *C*<sup>3</sup> approximately zero, the voltage-transfer function can be written as

$$V\_{out}(s) \cong \frac{gm\_1}{gds\_2 + gds\_4} \left[ \left(\frac{gm\_3}{gm\_3 + s\mathcal{C}\_1}\right) V\_{\mathbb{S}^1}(s) - V\_{\mathbb{S}^2}(s) \right] \frac{\omega\_2}{s + \omega\_2} \tag{17}$$

where *ω*<sup>2</sup> is given as

(11)

(12)

8 Will-be-set-by-IN-TECH

The small-signal properties of the differential amplifier can be accomplished with the assistance of the simplified model shown in Fig. 4, which ignores body effect. In this figure, *gm* is the gate transconductance given by the derivative of the drain current in relation to

> *gm* <sup>=</sup> *<sup>∂</sup>ID ∂VGS*

The series resistance *rds* is the inverse of the output conductance *gds* and can be estimated in

*rds* <sup>=</sup> *gds* <sup>=</sup> *<sup>∂</sup>ID*

M3 M4

M1 M2

*Vin*<sup>1</sup> *Vin*<sup>2</sup>

1

*Iref*

*VSS*

*C*3

The small-signal voltage gain *Avo*, *i.e.*, the relationship between *Vout* and the differential input

For higher frequencies, the voltage gain is modified due to the various parasitic capacitors at

*gds*<sup>2</sup> + *gds*<sup>4</sup>

*Avo* <sup>=</sup> *gm*<sup>1</sup>

each node of the circuits, modeled by *C*1, *C*<sup>2</sup> and *C*3, which are calculated as follows:

*gm*<sup>1</sup> · *vgs*<sup>1</sup>

*I*<sup>3</sup> *rds*<sup>2</sup> *rds*<sup>4</sup> *C*<sup>2</sup>

*Vout*

(13)

*∂VDS*

*VDD*

3 *Vout*

1

2

*gm*<sup>1</sup> · *vgs*<sup>1</sup> *rds*<sup>1</sup> *rds*<sup>3</sup> 1/*gm*<sup>3</sup> *<sup>C</sup>*<sup>1</sup>

**Figure 4.** Simplified small-signal model for the CMOS differential amplifier.

voltage *Vin*<sup>1</sup> − *Vin*2, can be estimated in low frequencies by

**Figure 3.** Schematics of a CMOS differential amplifier.

*D*<sup>1</sup> = *G*<sup>3</sup> = *D*<sup>3</sup> = *G*<sup>4</sup>

*S*<sup>1</sup> = *S*<sup>2</sup> = *S*<sup>3</sup> = *S*<sup>4</sup>

gate-source voltage:

small-signal analysis as

*G*1 +

*vgs*<sup>1</sup> *vgs*<sup>2</sup> +*vin*<sup>1</sup> − *vin*2− *G*2 +

− −

$$
\omega\_2 = \frac{gds\_2 + gds\_4}{\mathcal{C}\_2} \tag{18}
$$

The pole *<sup>ω</sup>*<sup>2</sup> determines the cut-off frequency of the amplifier and is also called as *<sup>ω</sup>*−3*dB*. Assuming that

$$\frac{g m\_3}{\mathcal{C}\_1} \gg \frac{g ds\_2 + g ds\_4}{\mathcal{C}\_2} \tag{19}$$

then the frequency response of the differential amplifier reduces to

$$\frac{V\_{out}(s)}{V\_{in1}(s) - V\_{in2}(s)} \cong \left(\frac{gm\_1}{gds\_2 + gds\_4}\right)\left(\frac{\omega\_2}{s + \omega\_2}\right) \tag{20}$$

This first-order analysis leads to a single pole at the output given by −(*gds*<sup>2</sup> + *gds*4)/*C*2. Some zeroes occur due to *Cgd*1, *Cgd*<sup>2</sup> and *Cgd*4, but they can be ignored in this analysis. The gain-bandwidth product (GBW), which is the equal to the unity-gain frequency, can be expressed as

$$GBW = A\_{\text{t}0} \cdot \omega\_{-\text{3dB}} \tag{21}$$

The slew-rate (SR) performance of the CMOS differential amplifier depends the value of *Iref* and the capacitance from the output node to ac ground and is given by

$$SR = \frac{I\_{ref}}{\mathbb{C}}\tag{22}$$

where C is the total capacitance connected to the output node (approximated by *C*<sup>2</sup> in our analysis).

Other important specifications for the electrical behavior of the differential amplifier includes power dissipation *Pdiss* = *Iref* · (*VDD* − *VSS*) and total gate area, calculated as the sum of the product of gate width and lenght of all transistors that compose the circuit:

$$Area = \sum\_{i} W\_{i} \cdot L\_{i} \tag{23}$$

All analog design has a target fabrication technology and a device type, in which the set of transistor model parameters is unique. These parameters determines the electrical characteristics - such as drain current, gate transconductance and output conductance - of the active devices that are part of the circuit. The specifications described before are function of these parameters, together with *W* and *L*. Since the parameters are fixed for a given fabrication technology, the designer has as free variables only the gate sizes. Gate sizing is, in effect, the task of analog design.

*Rmin*(*S*(*X*), *Sref*) = 0 if *<sup>S</sup>*(*X*) <sup>≥</sup> *Sref S*(*X*)−*Sref Sref*

Simulated Annealing to Improve Analog Integrated Circuit Design: Trade-Off s and Implementation Issues 271

We used in this example the constraint reference values shown in Tab. 1 . In order to simplify the analysis, we consider that all transistors of the circuit are of the same size. It is not a practical approach, since transistor *M*1 must be equal to *M*2, but not necessarily equal to *M*3 and *M*4. However, this simplification allows the 2-D visualization of the problem and can be used to explain design trade-offs and automatic optimal search, providing an intuitive notion of the problem. So, we will consider in this analysis two free variables: *L* = *L*<sup>1</sup> = *L*<sup>2</sup> = *L*<sup>3</sup> =

The design space for Eq. 24 was fully mapped by electrical simulation varying *W* and *L* from 1*μm* to 100*μm* with a step of 1*μm*. The target technology node was 0.35*μm* 3.3*V* CMOS. Fig. 5 shows the plotted design space as a function of *W* and *L*. It is possible to note the highly non-linear nature of the generated function and the existence of a valley in which is localized a minimum value. The optimal solution for this sizing problem, *i.e.*, the minimum value of the design space, is known exactly in this case and is located at *W* = 8*μm* and *L* = 20*μm*, with

Differential Amplifier − cost function

0

**Figure 5.** Two-variables design space for a differential amplifier. The minimum is at *W* = 8*μm* and

0

20

40

60

L (um)

80

*L* = 20*μm*, with the value of −1.9623.

100 −2 −1.5 −1 −0.5 0 0.5 1 1.5 2 2.5 3

20

40

W (um)

60

80

100

*L*<sup>4</sup> and *W* = *W*<sup>1</sup> = *W*<sup>2</sup> = *W*<sup>3</sup> = *W*4. In this case, *X* = [*W L*].

the value of −1.9623.

if *S*(*X*) < *Sref*

(27)

#### **4.2. Modeling the differential amplifier for automatic synthesis**

The modeling of the differential amplifier of Fig. 3 for automatic synthesis is straightforward. Using a simulation-based approach, the circuit specifications are calculated by SPICE electrical simulations. As an example, let us consider the multi-objective design of a differential amplifier that must be optimized in terms of voltage gain *Avo* and positive input common-mode range *ICMR*+. Also, there is a list of constraints containing a series of specifications that must be met hardly. Table 1 summarizes the design objectives and constraints for this problem.


**Table 1.** Design specifications and constraints for the differential amplifier of Fig 3 .

The cost function *fc*(*X*) is than formulated as a sum of design specifications and constraints in terms of the vector of the design variables *X*:

$$f\_{\rm c}(X) = 3 \cdot \frac{I \text{CMR}^+(X)}{I \text{CMR}^+\_{ref}} + \frac{A\_{\rm co}(X)}{A\_{\rm co}(ref)} + R(X) \tag{24}$$

The specifications are calculated for a given *X* and normalized by a reference value. In this example, *ICMR*<sup>+</sup> *ref* = 1.3*V* and *Avo*(*ref*) = 20*dB*. The ponderation of each specification can be implemented with individual weights which indicate the relative importance of the parameter. In this example, we choose a weight of 3 for *ICMR*<sup>+</sup> and 1 for *Avo*. *R*(*X*) is a constraint function which is also a function of *X*, calculated as follows:

$$R(X) = \frac{R\_{\text{max}}(Area(X), Area\_{ref})}{4} + R\_{\text{min}}(PM(X), PM\_{ref}) + R\_{\text{max}}(GBW(X), GBW\_{ref}) \tag{25}$$

Here, *Rmax*(*S*(*X*), *Sref*) and *Rmin*(*S*(*X*), *Sref*) are constraint functions of maximum and minimum, respectively, in terms of the specification *S*(*X*) and the reference value *Sref* . For example, the constraint of gate area is related to *Rmax*(*S*(*X*), *Sref*), because it can not be larger than a reference value of *Arearef* . The same occurs for GBW, which can not be smaller than *GBWref* , whose constraint is modeled by the function *Rmin*(*S*(*X*), *Sref*). Both constraint functions insert a penalty value in the cost function *fc*(*X*) if the specification is outside the expected range. Otherwise, they return zero. The following equations show how the constraint functions are implemented:

$$R\_{\max}(S(X), S\_{ref}) = \begin{cases} 0 & \text{if } S(X) \le S\_{ref} \\ \frac{S(X) - S\_{ref}}{S\_{ref}} & \text{if } S(X) > S\_{ref} \end{cases} \tag{26}$$

270 Simulated Annealing – Single and Multiple Objective Problems Simulated Annealing to Improve Analog Integrated Circuit Design: Trade-Offs and Implementation Issues <sup>11</sup> Simulated Annealing to Improve Analog Integrated Circuit Design: Trade-Off s and Implementation Issues 271

$$R\_{\min}(\mathcal{S}(\mathbf{X}), \mathcal{S}\_{ref}) = \begin{cases} 0 & \text{if } \mathcal{S}(\mathbf{X}) \ge \mathcal{S}\_{ref} \\ \frac{\mathcal{S}(\mathbf{X}) - \mathcal{S}\_{ref}}{\mathcal{S}\_{ref}} & \text{if } \mathcal{S}(\mathbf{X}) < \mathcal{S}\_{ref} \end{cases} \tag{27}$$

We used in this example the constraint reference values shown in Tab. 1 . In order to simplify the analysis, we consider that all transistors of the circuit are of the same size. It is not a practical approach, since transistor *M*1 must be equal to *M*2, but not necessarily equal to *M*3 and *M*4. However, this simplification allows the 2-D visualization of the problem and can be used to explain design trade-offs and automatic optimal search, providing an intuitive notion of the problem. So, we will consider in this analysis two free variables: *L* = *L*<sup>1</sup> = *L*<sup>2</sup> = *L*<sup>3</sup> = *L*<sup>4</sup> and *W* = *W*<sup>1</sup> = *W*<sup>2</sup> = *W*<sup>3</sup> = *W*4. In this case, *X* = [*W L*].

10 Will-be-set-by-IN-TECH

technology, the designer has as free variables only the gate sizes. Gate sizing is, in effect, the

The modeling of the differential amplifier of Fig. 3 for automatic synthesis is straightforward. Using a simulation-based approach, the circuit specifications are calculated by SPICE electrical simulations. As an example, let us consider the multi-objective design of a differential amplifier that must be optimized in terms of voltage gain *Avo* and positive input common-mode range *ICMR*+. Also, there is a list of constraints containing a series of specifications that must be met hardly. Table 1 summarizes the design objectives and

Specification Value

The cost function *fc*(*X*) is than formulated as a sum of design specifications and constraints

The specifications are calculated for a given *X* and normalized by a reference value. In this

can be implemented with individual weights which indicate the relative importance of the parameter. In this example, we choose a weight of 3 for *ICMR*<sup>+</sup> and 1 for *Avo*. *R*(*X*) is a

Here, *Rmax*(*S*(*X*), *Sref*) and *Rmin*(*S*(*X*), *Sref*) are constraint functions of maximum and minimum, respectively, in terms of the specification *S*(*X*) and the reference value *Sref* . For example, the constraint of gate area is related to *Rmax*(*S*(*X*), *Sref*), because it can not be larger than a reference value of *Arearef* . The same occurs for GBW, which can not be smaller than *GBWref* , whose constraint is modeled by the function *Rmin*(*S*(*X*), *Sref*). Both constraint functions insert a penalty value in the cost function *fc*(*X*) if the specification is outside the expected range. Otherwise, they return zero. The following equations show how the

> *S*(*X*)−*Sref Sref*

+

*Avo*(*X*) *Avo*(*ref*)

*ref* = 1.3*V* and *Avo*(*ref*) = 20*dB*. The ponderation of each specification

<sup>4</sup> <sup>+</sup> *Rmin*(*PM*(*X*), *PMref*) + *Rmax*(*GBW*(*X*), *GBWref*) (25)

0 if *<sup>S</sup>*(*X*) <sup>≤</sup> *Sref*

if *S*(*X*) > *Sref*

+ *R*(*X*) (24)

(26)

*Av* maximize *ICMR*<sup>+</sup> maximize *Area* < 120*μm*<sup>2</sup> *PM* > 70◦ *GBW* > 100*MHz*

**4.2. Modeling the differential amplifier for automatic synthesis**

**Table 1.** Design specifications and constraints for the differential amplifier of Fig 3 .

*fc*(*X*) = <sup>3</sup> · *ICMR*+(*X*)

constraint function which is also a function of *X*, calculated as follows:

*Rmax*(*S*(*X*), *Sref*) =

*ICMR*<sup>+</sup> *ref*

in terms of the vector of the design variables *X*:

*Rmax*(*Area*(*X*), *Arearef*)

constraint functions are implemented:

task of analog design.

constraints for this problem.

example, *ICMR*<sup>+</sup>

*R*(*X*) =

The design space for Eq. 24 was fully mapped by electrical simulation varying *W* and *L* from 1*μm* to 100*μm* with a step of 1*μm*. The target technology node was 0.35*μm* 3.3*V* CMOS. Fig. 5 shows the plotted design space as a function of *W* and *L*. It is possible to note the highly non-linear nature of the generated function and the existence of a valley in which is localized a minimum value. The optimal solution for this sizing problem, *i.e.*, the minimum value of the design space, is known exactly in this case and is located at *W* = 8*μm* and *L* = 20*μm*, with the value of −1.9623.

**Figure 5.** Two-variables design space for a differential amplifier. The minimum is at *W* = 8*μm* and *L* = 20*μm*, with the value of −1.9623.
