**9. Experiment and comparison**

To evaluate the effectiveness and reliability of the proposed MSA in practice, a set of experiments was implemented, comparing with traditional SA and 2-stage SA. In the case of 2D packing and placement, we are using ami49\_X and MCNC benchmarks. The ami49\_X is produced by duplicating ami49 circuit X times. In the case of 3D packing, ami98\_3D benchmark is produced by inheriting the height and width of 2D ami49\_2 benchmark and randomly getting the length between the given minimum and maximum dimensions. The implementation for 3D packing is to compare MSA with the mentioned 2-stage SA. MSA is implemented in Python environment on 2.16GHz PC with 3.00GB memory. For a fair comparison, SA and 2-stage SA is also implemented at the same machine. The maximum runtime is within 14,400s (4 hours) each time.

For area optimization of 2D packing, let γ be 1 and α+β be 0 in the cost function. As shown in Table 1, the best, average and worst cases among 50 trials are gotten. The comparison of solution quality and runtime between SA and MSA is gotten. MSA reduced near 21% runtime with better solution quality. As shown in Table 2, a near log-linear trend of average improvement rates from SA to MSA is gotten. That means MSA should be more suitable for the placement with a larger number of modules.

For interconnect optimization of 2D placement, let γ be 0 and α+β be 1 in the cost function. The experiment is using ami49\_X benchmarks. To get the figures, α is randomly produced from 0.1 to 0.9. 240 solutions are tested for comparison. For all tested ami49\_X with X from 1 to 12, block number from 49 to 588, and net number from 408 to 4896, the improved results are gotten. Figure 13 shows that MSA obtains at least 13% Pareto improvement with the constraint of less than 108.2% maximal delay. To get the worst cases, we tested more 120 solutions with α given by 0.1, 0.3, 0.5, 0.7, and 0.9. As shown in Figure 14, MSA got near 6% worst-case mitigation on average for the interconnect power with no degradation of maximal delay.


**Table 1.** Area optimization by MSA for 2D packing

254 Simulated Annealing – Single and Multiple Objective Problems

interconnect power is simplified as the function of *Leni* and *S(i)*.

from (*hi, wi, ni*)*,* (*xi, yi, ri*). The power and the delay are estimated so far.

implementation, the cost function is also using the relative value of volume.

be scalable to use the experiments by diverse benchmarks.

**9. Experiment and comparison** 

runtime is within 14,400s (4 hours) each time.

the placement with a larger number of modules.

For power estimation, the dynamic power of a net *ni* is proportional to *C(i)*, *Vdd(i)2*, *f(i)* and *S(i)*, where *C(i)* is the capacitance of a net, *Vdd(i)* is the voltage of power supply, *f(i)* is the clock frequency, and *S(i)* is switching probability of the net. Normally *C(i)* is proportional to the length of net, so let *Leni* represent its value. In case of no information, let us assume that *Vdd(i)* and *f(i)* are same for each net and *S(i)* is randomly defined from 0 to 1. So the

For performance estimation, the maximal delay among all nets is used. The delay is defined by the wire length of nets. To get the wire length estimation for each net, the half perimeter wire length (*HPWL*) is used for the approximation of wire length. Given any net *ni*, connected with modules {*m1, m2, ..., ms*}, *HPWL* is half perimeter of the minimum bounding box for all centres of module *mi*, where *i* is an integer from *1* to *s*. In case of *ri*=1, *HPWL*[*ni*] is given by *max*[*xi + hi/2*] *– min*[*xi + hi/2*] *+ max*[*yi + wi/2*] *– min*[*yi + wi/2*]. So *HPWL*[*ni*] is gotten

For the objective of 2D packing, the area estimation is the minimum bounding rectangle including all modules, which is the total height *H* multiplied by the total width *W*. In practical implementation, we use a relative value as the cost function of area, i.e. the bounding area divided by the area of total modules, because any value with unit would not

For the objective of 3D packing, instead of 2D case, the volume estimation is given by the minimum bounding rectangular parallelepiped including all modules, which is the total height *H* multiplied by the total width *W* and multiplied by the total length *L*. In real

To evaluate the effectiveness and reliability of the proposed MSA in practice, a set of experiments was implemented, comparing with traditional SA and 2-stage SA. In the case of 2D packing and placement, we are using ami49\_X and MCNC benchmarks. The ami49\_X is produced by duplicating ami49 circuit X times. In the case of 3D packing, ami98\_3D benchmark is produced by inheriting the height and width of 2D ami49\_2 benchmark and randomly getting the length between the given minimum and maximum dimensions. The implementation for 3D packing is to compare MSA with the mentioned 2-stage SA. MSA is implemented in Python environment on 2.16GHz PC with 3.00GB memory. For a fair comparison, SA and 2-stage SA is also implemented at the same machine. The maximum

For area optimization of 2D packing, let γ be 1 and α+β be 0 in the cost function. As shown in Table 1, the best, average and worst cases among 50 trials are gotten. The comparison of solution quality and runtime between SA and MSA is gotten. MSA reduced near 21% runtime with better solution quality. As shown in Table 2, a near log-linear trend of average improvement rates from SA to MSA is gotten. That means MSA should be more suitable for


**Table 2.** Average improvement of area for 2D packing

A Simulated Annealing Based Approach to Integrated Circuit Layout Design 257

2-SA\_k=3

MSA\_k=3

2-SA\_k=5 MSA\_k=5

**Performance Comparison of ami98\_3D Packing**

1 10 100 1000 10000 100000 **Computational Time (sec)**

**Performance Comparison of ami98\_3D Packing**

**12%**

**3X**

**7%**

**Figure 15.** Performance improvement by MSA for 3D packing (sequence triple)

100.0%

100.0% 110.0% 120.0% 130.0% 140.0% 150.0% 160.0% 170.0% 180.0% 190.0% 200.0%

**3D Packing Ratio (%)**

110.0%

120.0%

130.0%

140.0%

**3D Packing Ratio (%)**

150.0%

160.0%

170.0%

180.0%

**Figure 16.** Performance improvement by MSA for 3D packing (sequence quintuple)

1 10 100 1000 10000 100000 **Computational Time (sec)**

**4X**

**Figure 13.** Pareto frontiers and its improvement by MSA for 2D placement (sequence pair)

**Figure 14.** Worst-case mitigation by MSA for 2D placement (sequence pair)

**Figure 15.** Performance improvement by MSA for 3D packing (sequence triple)

100% 102% 104% 106% 108% 110% 112% 114% 116% 118% 120%

> 105% 107% 109% 111% 113% 115% 117% 119% 121% 123% 125%

**Maximal Delay**

**Maximal Delay**

**Figure 13.** Pareto frontiers and its improvement by MSA for 2D placement (sequence pair)

100% 150% 200% 250% 300% **Interconnect Power Consumption**

**Comparison in the worst cases**

100% 150% 200% 250% 300% 350%

**9%**

**Interconnect Power Consumption**

**108.2%**

**Pareto Frontiers**

**13%**

SA MSA

SA

MSA

**1.1%**

**Figure 14.** Worst-case mitigation by MSA for 2D placement (sequence pair)

**Figure 16.** Performance improvement by MSA for 3D packing (sequence quintuple)

For volume optimization of 3D packing, we compare the computational performance of volume ratio using 2-stage SA and MSA. The results show considerable improvement from 2-stage SA to MSA. The improvement of packing ratio is between 2% and 7% for sequence triple representation. The improvement for runtime is up to 3 times, as shown in Figure 15. With regard to sequence quintuple representation, the experiment also shows the improvement from 2-stage SA to MSA. The improvement of packing ratio is between 3% and 12%. The improvement for runtime is up to 4 times with the sequence quintuple representation, as shown in Figure 16. The packing ratio of volume is improved by near 7% with less than 100s runtime, if we select MSA with sequence triple representation, instead of 2-stage SA with the same representation. The packing ratio of volume is improved by near 12% with less than 100s runtime, if we select MSA with sequence quintuple representation, instead of 2-stage SA with the same representation. In short, the overall solution quality and the runtime of MSA algorithm are better than these of 2-stage SA algorithm.

A Simulated Annealing Based Approach to Integrated Circuit Layout Design 259

Zhao at Tokyo Institute of Technology, and to thank Mr. Yamada, Mr. Ando and Mr. Ukon

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