**2. Simulated annealing for integrated circuit layout**

Based on the theory of statistical mechanics and the analogy between solid annealing and optimization problem, S. Kirkpatrick, C. D. Gelatt and M. P. Vecchi [1] proposed simulated annealing algorithm in 1983. The annealing is to heat up a solid with a very high temperature and then to cool it down slowly until it reaches or approaches its minimum energy state. Each state of solid represents a feasible solution of problem. The energy of the state is the value of cost function to evaluate the solution. The state with the lowest energy corresponds to the optimal solution with the best value of cost function. SA is a stochastic algorithm with iterative improvement. Each iterative step consists of changing current solution to a new solution, named a move to neighbourhood. The acceptance probability of new solutions depends on the current temperature, which is scheduled from the highest temperature to the lowest temperature. An important point we have to mention here is that, if the physical process is to cool the solid down very quickly, it is known as quenching, instead of annealing. The difference between normal simulated annealing and simulated quenching is the parameter setting of temperature scheduling.

240 Simulated Annealing – Single and Multiple Objective Problems

algorithms in order to solve 2D/3D problem more effectively.

reduce runtime if we can overcome the mentioned shortcomings.

volume is improved by up to 12% within 100s runtime.

**2. Simulated annealing for integrated circuit layout** 

researches explored different representations [7-12], such as bounded-slice-line grid, sequence pair, FAST sequence pair, Q-sequence, selected sequence pair, etc. In order to code and decode 3D-packing problem, sequence pair for 2D packing is extended to sequence triple and sequence quintuple, and it has been proved that sequence triple could represent the topology of the tractable 3D packing and there are at least one sequence quintuple which can be decoded to a topology as an optimal packing for volume minimization. But the effectiveness to improve solution quality and reduce runtime is quite limited due to huge solution space and complex solution distribution, even if a very good representation is used. The experimental results within a short runtime are still far from near-optimal solutions in real implementation to solve the packing problem. So it is the right time to explore new

There are many significant shortcomings of traditional heuristics for IC layout optimization. Let us take simulated annealing (SA) and genetic algorithm (GA) as an example. For SA, firstly, some slight modifications of solution are repeated to get a good convergence. Therefore, the global search is inefficient in general. It is disadvantageous to solve the problem with huge solution space, such as VLSI design. Secondly, SA does not use the past experience, including past good solutions and past moves, and it is a big informational waste. To speed up SA, some researchers [4] proposed two-stage SA for VLSI design. But the search speed is still quite slow, and it is not seriously considered to avoid or reduce informational waste. For GA, it evaluates too many candidates in order to get next generations. The evaluation takes too much runtime. Besides GA selects the next generation according to a ranking function, which is not always necessary but takes much time. So it is possible to improve the solution quality or

In this research, a simulated annealing based approach [13-14], named mixed simulated annealing (MSA), is proposed to improve solution quality and reduce runtime by overcoming the shortcomings of inefficient global search and informational waste. In mixed simulated annealing, a special crossover operator is designed to use a part of information from past good solutions and get higher improving efficiency, and the solutions gotten by the crossover are much better than random solutions. To evaluate the effectiveness and the reliability of the proposed mixed simulated annealing, we apply it to three mentioned optimization problems, i.e. 2D packing, 2D placement and 3D packing, and get considerable improvement for all three problems. The experimental results show the runtime, the packing ratio of area for 2D packing, the packing ratio of volume for 3D packing and two more objectives (low power and short maximal delay) for 2D placement are improved considerably by using MCNC, ami49\_X and ami98\_3D benchmarks. For example, the runtime of mixed simulated annealing with sequence quintuple representation is up to 4 times faster than that of 2-stage SA with the same representation, and the packing ratio of

Based on the theory of statistical mechanics and the analogy between solid annealing and optimization problem, S. Kirkpatrick, C. D. Gelatt and M. P. Vecchi [1] proposed simulated In detail, let *S* be the solution space with neighbourhood structure. For any solution S belongs to *S*, we define the cost function *C*(S), i.e. the total cost function (*Ct*) for multiobjective placement problem. A non-optimal solution S is defined by local optimum, if it can not reach better solution by moving to any neighbouring solution S′. That is to day, for any neighbour solution (S′) of local optimal solution (S), the inequality *C*(S) < *C*(S′) is always satisfied. The depth *D*(S) of local optimal solution is defined by the maximum value such that *D*(S) + *C*(S) > *C*(S′). The maximum depth of local optimal solution in *S* is denoted by d(*S*). Let *X*(*Ti*) be a variable of the cost function C(S) at each temperature *Ti*, where *i* is 0, 1, 2, … . Let *Copt* be the minimum cost function. According to [2], the equality lim*<sup>i</sup>*→<sup>∞</sup> *X*(*Ti*) = *Copt* is satisfied with the following conditions: (1) The solution space *S* is finite and irreducible; (2) There exists an equilibrium distribution for the transition probability matrix; (3) *Ti* ≥ *Ti+1* and *Ti* > 0 for all *i*; (4) lim*<sup>i</sup>*→<sup>∞</sup> *Ti* = 0; (5) *∑<sup>i</sup>*:∈(0, ∞) [exp(-d(*S*)/*Ti*)] = ∞.

In real implementation with a given finite runtime, we are using a fast geometric simulated quenching scheduling (*Tk+1 = qTk, 0<q<1*) with repeated inside loop (*p* times) to enhance the efficiency of standard SA [3] as the following equation.

$$T\_i = T\_0 \cdot q^{\lfloor i/p \rfloor} \tag{1}$$

where *i* is the iterative step, *Ti* is the variable temperature at the *ith* step, *T0* is the initial temperature when *i* = 0, *p* is the inside loop number and *q* the temperature coefficient near but less than 1.

As shown in Figure 1, it is a typical flow chart of SA, which is used for layout optimization in this research. The initial solution is randomly produced or simply follows past layout designs. The temperature scheduling is used to change the current temperature (*T*). The parameters of the temperature scheduling include the starting temperature *T0*, the ending temperature *Te*, a temperature coefficient and an inside loop number. One of moving methods is selected with given probabilities, for example, the same probability for each moving method in real experiment (near 33% in the case of three moving methods). A new solution is tried by using the current selected moving method. The new solution is evaluated by a cost function (*C*) and compared with the old one. The new solution is

242 Simulated Annealing – Single and Multiple Objective Problems

A Simulated Annealing Based Approach to Integrated Circuit Layout Design 243

**Figure 2.** Orthogonal coordinate system and 3D packing topology represented by *Γ1*(*m2,m1,m3*),

layout in 3D general cases is regarded as a set of the relations of relative location between boxes, i.e. "Top-Bottom", "North-South" and "West-East" (TB-, NS- and WE-) relations. The coding and the decoding are based on TB-, NS- and WE- relation corresponding to the order of modules. In Figure 2, box *m2* is on the west of box *m3*, i.e. WE-relation, since the xcoordinate of any part of box *m2* is always smaller than or equal to that of any part of box *m3*. Similarly box *m1* is on the north of box *m3*, i.e. NS-relation, and box *m2* is on the top of box *m1*, i.e. TB-relation. The 3D packing can be represented by *Γ1*(*m2,m1,m3*), *Γ2*(*m1,m3,m2*), and *Γ3*(*m1,m2,m3*) according to the coding rule. The detail of representation will be introduced in section 5. The solution space of all mentioned representation is finite, instead of infinite solution space of original layout problem. All solutions decoding by the mentioned

For the moving methods, let us take 2D placement as example. Three basic moving methods with small changes are designed to change the current solution by using the sequence-pair representation. The "rotation" changes the orientation of a module. The "exchange" exchanges the order of two modules in all sequences. The "move" changes the order of a module in one of sequences. The detail of each moving method will be discussed in section 6

For the cost function in the case of 2D placement, the total value (*Ct*) includes the dynamic power function (*Cp*), the maximal delay function (*Cd*) and the bounding area function (*Ca*).

For the temperature scheduling, the starting temperature *T0*, the ending temperature *Te*, a temperature coefficient and an inside loop number are set according to the size of module number and the requirement of solution quality. As a reference, a set of parameters in our experiment is set as follows: *T0* = 100000, *Te* = 10, Inside loop number *p* = 500, Temperature

The estimation for each cost function will be discussed in section 8.

*Γ2*(*m1,m3,m2*) and *Γ3*(*m1,m2,m3*) according to relative location

representations are feasible.

and section 7.

coefficient *q* = 0.98.

**Figure 1.** A typical flow chart of simulated annealing

accepted with a calculated acceptance probability *P* = exp[*-∆C/T*], which depends on the difference of cost function (*∆C*) and the current temperature (*T*). The probability *P* is between 0 and 1. The temperature coefficient between 0 and 1 is set to control the speed of temperature reduction. The inside loop number is set to control the repeated moves for each *T*. If the new solution is improved (*∆C < 0*), then *P* = 1, and the best recorder will be implemented: If the new solution is better than the current best, the best record will be replaced. If rejected, the current solution will go back to the old one and continues the next temperature scheduling until reaching the lowest temperature Te. The output is the latest best record. The real implementation of SA algorithm depends on four basic definitions: (1) solution representation, (2) moving methods, (3) cost function, (4) temperature scheduling.

For the solution representation, 2D/3D topology for IC layout is defined by the orthogonal coordinate system, as shown in Figure 2, and is represented by sequence pair for 2D general cases, sequence triple for 3D simple cases or sequence quintuple for 3D general cases. Each

**Figure 1.** A typical flow chart of simulated annealing

accepted with a calculated acceptance probability *P* = exp[*-∆C/T*], which depends on the difference of cost function (*∆C*) and the current temperature (*T*). The probability *P* is between 0 and 1. The temperature coefficient between 0 and 1 is set to control the speed of temperature reduction. The inside loop number is set to control the repeated moves for each *T*. If the new solution is improved (*∆C < 0*), then *P* = 1, and the best recorder will be implemented: If the new solution is better than the current best, the best record will be replaced. If rejected, the current solution will go back to the old one and continues the next temperature scheduling until reaching the lowest temperature Te. The output is the latest best record. The real implementation of SA algorithm depends on four basic definitions: (1) solution representation, (2) moving methods, (3) cost function, (4) temperature scheduling.

For the solution representation, 2D/3D topology for IC layout is defined by the orthogonal coordinate system, as shown in Figure 2, and is represented by sequence pair for 2D general cases, sequence triple for 3D simple cases or sequence quintuple for 3D general cases. Each

**Figure 2.** Orthogonal coordinate system and 3D packing topology represented by *Γ1*(*m2,m1,m3*), *Γ2*(*m1,m3,m2*) and *Γ3*(*m1,m2,m3*) according to relative location

layout in 3D general cases is regarded as a set of the relations of relative location between boxes, i.e. "Top-Bottom", "North-South" and "West-East" (TB-, NS- and WE-) relations. The coding and the decoding are based on TB-, NS- and WE- relation corresponding to the order of modules. In Figure 2, box *m2* is on the west of box *m3*, i.e. WE-relation, since the xcoordinate of any part of box *m2* is always smaller than or equal to that of any part of box *m3*. Similarly box *m1* is on the north of box *m3*, i.e. NS-relation, and box *m2* is on the top of box *m1*, i.e. TB-relation. The 3D packing can be represented by *Γ1*(*m2,m1,m3*), *Γ2*(*m1,m3,m2*), and *Γ3*(*m1,m2,m3*) according to the coding rule. The detail of representation will be introduced in section 5. The solution space of all mentioned representation is finite, instead of infinite solution space of original layout problem. All solutions decoding by the mentioned representations are feasible.

For the moving methods, let us take 2D placement as example. Three basic moving methods with small changes are designed to change the current solution by using the sequence-pair representation. The "rotation" changes the orientation of a module. The "exchange" exchanges the order of two modules in all sequences. The "move" changes the order of a module in one of sequences. The detail of each moving method will be discussed in section 6 and section 7.

For the cost function in the case of 2D placement, the total value (*Ct*) includes the dynamic power function (*Cp*), the maximal delay function (*Cd*) and the bounding area function (*Ca*). The estimation for each cost function will be discussed in section 8.

For the temperature scheduling, the starting temperature *T0*, the ending temperature *Te*, a temperature coefficient and an inside loop number are set according to the size of module number and the requirement of solution quality. As a reference, a set of parameters in our experiment is set as follows: *T0* = 100000, *Te* = 10, Inside loop number *p* = 500, Temperature coefficient *q* = 0.98.
