**Acknowledgement**

The authors would like to thank Prof. Kunihiro Fujiyoshi at Tokyo University of Agriculture and Technology, to thank Prof. Shuichi Ueno, Dr. Tayu, Mr. Shinoda, Mr. Inoue and Mr. Zhao at Tokyo Institute of Technology, and to thank Mr. Yamada, Mr. Ando and Mr. Ukon at Osaka University for their discussion, comment and support.

### **11. References**

258 Simulated Annealing – Single and Multiple Objective Problems

**10. Conclusion and future work** 

**Author details** 

**Acknowledgement** 

Yiqiang Sheng and Atsushi Takahashi

*and Engineering, Tokyo Institute of Technology, Tokyo, Japan* 

For volume optimization of 3D packing, we compare the computational performance of volume ratio using 2-stage SA and MSA. The results show considerable improvement from 2-stage SA to MSA. The improvement of packing ratio is between 2% and 7% for sequence triple representation. The improvement for runtime is up to 3 times, as shown in Figure 15. With regard to sequence quintuple representation, the experiment also shows the improvement from 2-stage SA to MSA. The improvement of packing ratio is between 3% and 12%. The improvement for runtime is up to 4 times with the sequence quintuple representation, as shown in Figure 16. The packing ratio of volume is improved by near 7% with less than 100s runtime, if we select MSA with sequence triple representation, instead of 2-stage SA with the same representation. The packing ratio of volume is improved by near 12% with less than 100s runtime, if we select MSA with sequence quintuple representation, instead of 2-stage SA with the same representation. In short, the overall solution quality and

In summary, the optimization techniques for integrated circuit (IC) layout design with large solution space are facing big challenges to get better solution quality with less runtime. In this research, a new simulated annealing based approach, named mixed simulated annealing (MSA), is proposed to solve three typical layout design problems, which are 2D packing, 2D placement and 3D packing, by using sequence pair, sequence triple and sequence quintuple representations. A new crossover operator is designed to reuse the information of past solutions and get high improving efficiency. Based on experiment, MSA improved both the best and the worst cases of 2D placement for interconnect power and maximal delay. For area minimization, MSA reduced computational runtime with the better solution quality, and a near log-linear trend of average improvement rates from SA to MSA is gotten for both solution quality and runtime. The overall quality of packing by MSA is normally better than the published results. For the volume minimization of 3D packing, MSA improved the solution quality (up to 12% better) and the computational time (up to 4 times faster). For the future work, the proposed MSA has potential to be extended to more

the runtime of MSA algorithm are better than these of 2-stage SA algorithm.

general problems, such as 2D/3D packing or placement with rectilinear boxes.

*Department of Communications and Integrated Systems, Graduate School of Science* 

The authors would like to thank Prof. Kunihiro Fujiyoshi at Tokyo University of Agriculture and Technology, to thank Prof. Shuichi Ueno, Dr. Tayu, Mr. Shinoda, Mr. Inoue and Mr.

	- [14] Y. Sheng, A. Takahashi and S. Ueno, "2-Stage Simulated Annealing with Crossover Operator for 3D-Packing Volume Minimization," *Proceedings of the 17th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI)*, pages 227- 232, 2012.

**Chapter 0**

**Chapter 13**

**Simulated Annealing to Improve Analog**

**Integrated Circuit Design: Trade-Offs and**

Lucas Compassi Severo, Alessandro Girardi, Alessandro Bof de Oliveira,

The design of analog integrated circuits is complex because it involves several aspects of device modeling, computational methodologies, and human experience. Nowadays, the well-stablished CMOS (Complementary Metal-Oxide-Semiconductor) technology is mandatory in most of the integrated circuits. The basic devices are MOS transistors, whose manufacturing process is well understood and constantly updated in the design of small devices. Detailed knowledge of the devices technology is needed for modeling all aspects of analog design, since there is a strong dependency between the circuit behavior and the

Contrary to digital circuits, which are composed by millions (or even billions) of transistors with equal dimensions, analog circuits are formed by tens of transistors, but each one with a particular geometric feature and bias operation point. Digital design is characterized by the high degree of automation, in which the designer has low influence on the resulting physical circuit. The quality of the CAD (Computer-Aided Design) tools used for circuit synthesis is much more important than the designer experience. These tools are able to deal with a large number of devices and interconnections. Digital binary circuits have robustness characteristics in which the influence of non-linearities and non-idealities are not a major concern. Furthermore, mathematical models of devices for digital circuits are relaxed and

On the other hand, analog design still lacks from design automation. This is a consequence of the problem features and the difficulty of implementing generic tools with high design accuracy. Thus, the complex relations between design objectives and design variables result in a highly non-linear n-dimensional system. Technology dependency limits the design automation, since electrical behavior is directly related to physical implementation. In

> ©2012 Girardi et al., licensee InTech. This is an open access chapter distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly

©2012 Girardi et al., licensee InTech. This is a paper distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

**Implementation Issues**

Fabio N. Kepler and Marcia C. Cera

http://dx.doi.org/10.5772//45872

**1. Introduction**

manufacturing process.

computationally very efficient.

cited.

Additional information is available at the end of the chapter

**Chapter 0 Chapter 13**
