**1. Introduction**

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> The quest for higher data rates in state-of-the-art wireless standards and services calls for wideband and high-resolution data-converters in wireless transceivers. While modern integrated circuits (IC) technologies provide high cut-off frequencies (்݂) for transistors and hence allow the operation at higher speeds, the main limitation against increasing speed of operation of data-converters is the problem of clock-jitter. Clock-jitter is a common problem associated with clock generators due to uncertainty in the timing of the clock edges caused by the finite phase-noise (PN) in the generated clock waveform. Particularly, noise components induced by several noise sources in the system providing the clock (e.g. phaselocked loop, PLL) add to the clock waveform and cause uncertainty in the timing of the zero-crossing instants from cycle to cycle. Figure 1 shows a survey chart of the analog-todigital converter (ADC) implementations reported in IEEE International solid-state circuits conference (ISSCC) and VLSI Symposium since 1997 [1]. The straight lines show the limitation on the achievable signal-to-noise ratio (SNR) by clock-jitter for jitter root-mean square (rms) values of 1ps and 0.1ps. As can be seen from the chart, the performance of most ADCs falls below the line corresponding to 1ps rms jitter, few ADCs reside in the range between 1ps and 0.1ps, and almost all ADC implementations reported so far are beyond the 0.1ps rms jitter line. This means that the main limitation on increasing the ADC performance in terms of SNR and speed is the specification on the clock-jitter of 0.1ps.

> Delta-sigma (ΔƩ) ADCs are the convenient choice in low power and state-of-the-art multistandard wireless receivers for two main reasons. First, they trade DSP for relaxed analog circuit complexity. Particularly, ΔƩ ADC implementations span analog and digital domains (ΔƩ pulse density modulation + digital decimation and filtering, as shown in Figure 2) and hence exploit DSP to relax hardware requirements on analog blocks. Thus, the simplified analog part (ΔƩ modulator) and the digital filtering can be efficiently reconfigured to fulfill

© 2012 Saad et al., licensee InTech. This is an open access chapter distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. © 2012 Saad et al., licensee InTech. This is a paper distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

performance requirements of different standards at minimum power consumption. Second, ΔƩ modulators use oversampling and hence trade speed for resolution. Specifically, for a given ΔƩ modulator and channel bandwidth (BW), higher effective number of bits (ENOB) can be achieved by increasing the oversampling ratio (OSR). This qualifies ΔƩ ADCs to benefit from increasing speeds of operation offered by advanced deep submicron CMOS technologies (maximum cutoff-frequency ்݂ ͵ͲͲݖܪܩ in 45nm [2]) to meet higher resolution requirements for modern and future wireless services at minimum power overhead.

**Figure 1.** ADC Performance Survey 1997-2012 [1]

Continuous-time (CT) ΔƩ ADCs are widely used in wideband low power wireless receivers [3, 4]. The CT operation of the loop filter relaxes the requirements on the gain-bandwidth product (GBW) of the adopted amplifiers and hence allows the operation at higher speeds or lower power consumption compared to discrete-time (DT) implementations. Also, CT loop filters offer inherent anti-aliasing and thus save the need for explicit anti-aliasing filter before the ADC. The requirements on the sample-and-hold (S/H) circuitry are also relaxed because the sampling is performed after the loop filter and hence the sampling errors experience the maximum attenuation offered by the loop (similar to quantization noise). However, CT ΔƩ modulators suffer from high sensitivity to clock-jitter in the sampling-clock of the digital-to-analog converters (DACs) in the feedback.

In this context, this chapter is intended to provide a comprehensive background and study for the effects of clock-jitter in the sampling-clocks of ΔƩ modulators. Also, Matlab/Simulink models for additive errors induced by clock-jitter in ΔƩ modulators are given so that to help designers characterize the sensitivities of various types of ΔƩ architectures to clock-jitter. The material in this chapter is organized as follows. Section 2 gives a general background about the types of errors caused by clock-jitter in different classes of switched circuits and signal waveforms. The critical sources of jitter induced errors in a ΔƩ loop are identified for DT and CT ΔƩ modulators and a comparison between the two types, in terms of sensitivity to clock-jitter, is done in Section 3. Section 4 provides detailed sensitivity analysis for CT ΔƩ modulators to clock-jitter in the feedback DAC sampling-clock. In Section 5, Simulink models, based on the analysis of Section 4, for the additive errors generated by clock-jitter in CT ΔƩ modulators are shown and the robustness of these models is verified by CT simulations in Matlab/Simulink. Simulations results show good agreement with the theoretical expectations. Finally, conclusions are drawn in Section 6.

**Figure 2.** ΔƩ ADC (ΔƩ pulse density modulation + digital decimation and filtering).

### **2. Jitter problems: Background**

394 MATLAB – A Fundamental Tool for Scientific Computing and Engineering Applications – Volume 1

overhead.

**Figure 1.** ADC Performance Survey 1997-2012 [1]

of the digital-to-analog converters (DACs) in the feedback.

performance requirements of different standards at minimum power consumption. Second, ΔƩ modulators use oversampling and hence trade speed for resolution. Specifically, for a given ΔƩ modulator and channel bandwidth (BW), higher effective number of bits (ENOB) can be achieved by increasing the oversampling ratio (OSR). This qualifies ΔƩ ADCs to benefit from increasing speeds of operation offered by advanced deep submicron CMOS technologies (maximum cutoff-frequency ்݂ ͵ͲͲݖܪܩ in 45nm [2]) to meet higher resolution requirements for modern and future wireless services at minimum power

Continuous-time (CT) ΔƩ ADCs are widely used in wideband low power wireless receivers [3, 4]. The CT operation of the loop filter relaxes the requirements on the gain-bandwidth product (GBW) of the adopted amplifiers and hence allows the operation at higher speeds or lower power consumption compared to discrete-time (DT) implementations. Also, CT loop filters offer inherent anti-aliasing and thus save the need for explicit anti-aliasing filter before the ADC. The requirements on the sample-and-hold (S/H) circuitry are also relaxed because the sampling is performed after the loop filter and hence the sampling errors experience the maximum attenuation offered by the loop (similar to quantization noise). However, CT ΔƩ modulators suffer from high sensitivity to clock-jitter in the sampling-clock

In this context, this chapter is intended to provide a comprehensive background and study for the effects of clock-jitter in the sampling-clocks of ΔƩ modulators. Also, Matlab/Simulink Since digital data is always available in DT form, then any process of converting information from analog form to digital bit-stream or vice versa entails sampling. However, the clock signals driving sampling switches suffers clock-jitter due to the noise components that accompany the clock waveform. Figure 3 shows the PN density in a typical voltagecontrolled oscillator (VCO)1. In the time-domain, the integrated effect of these noise components results in random variations in the phase of the generated clock signal. In dataconverters, the problem of clock-jitter is a very critical issue and can significantly deteriorate the achievable SNR by several dBs. The problems resulting from clock-jitter are classified as follows:

**<sup>1</sup>** The design of clock generators and the mechanisms of PN generation in PLLs are not within the scope of the material given in this chapter.

$$\begin{aligned} \text{le} \{ \text{n } T\_{\sf s} \} &= A \left\{ \sin \left[ \omega (\!(\!n \, T\_{\sf s} + \!\!n \, t \!\!(\!n \,) \) \right] - \sin \left( \!(\!\omega \, n \, T\_{\sf s}) \right) \right\} \\ &\approx A \, \omega \, \Delta t \text{(n) } \cos \{ \!\!n \, T\_{\sf s} \}. \end{aligned} \tag{1}$$

$$
\sigma\_e^2 = E\left(e^2\right) = \frac{\left(\mathbb{A} \text{ or } \sigma\_l\right)^2}{2} \tag{2}
$$

$$\lceil SNR \rceil\_{\text{Due to aperture filter}} = 10 \log \left( \frac{1}{\omega^2 \sigma\_j^2} \right) = 10 \log \left( \frac{1}{4 \, n^2 \, f^2 \sigma\_j^2} \right) \tag{3}$$

$$I\_n(t) = \begin{cases} I\_p \ e^{-(t-a)T\_s} & , \quad aT\_s < t < \beta T\_s, 0 \le a \le \beta \le 1 \\\\ 0 & , \quad \
otherwise \end{cases},\tag{4}$$

$$Q\_n = \int\_{aT\_\delta}^{\beta T\_\delta} I\_n(t) \, dt = \int\_{aT\_\delta}^{\beta T\_\delta} I\_P \, e^{\frac{-(t-a)T\_\delta}{\tau}} \, dt = -\tau A \, e^{\frac{-(t-a)T\_\delta}{\tau}} \Big|\_{aT\_\delta}^{\beta T\_\delta} = \tau A \left(1 - e^{\frac{-(\beta-a)T\_\delta}{\tau}}\right) \tag{5}$$

$$I\_P = \frac{q\_n}{r\left(1 - e^{\frac{-(\beta - a)T\_S}{t}}\right)}.\tag{6}$$

$$I\_n(t) = \begin{cases} \frac{q\_n}{t\left(1 - e^{\frac{-(\beta - a)T\_s}{t}}\right)} e^{\frac{-(t-a)T\_s}{t}}, aT\_s < t < \beta T\_s, 0 \le a \le \beta \le 1. \\\\ 0, otherwise. \end{cases} \tag{7}$$

$$e\_j(n) = \frac{Q\_n}{\tau \left(1 - e^{\frac{-(\beta - a)T\_s}{\tau}}\right)} \int\_{\beta T\_s}^{\beta T\_s + \Delta t(n)} e^{-\frac{(t-a)T\_s}{\tau}} dt = \frac{-Q\_n}{\left(1 - e^{\frac{-(\beta - a)T\_s}{\tau}}\right)} e^{\frac{-(t-a)T\_s}{\tau}} \Bigg|\_{\beta T\_s}^{\beta T\_s + \Delta t(n)}$$

$$= \frac{Q\_n}{\left(1 - e^{\frac{-(\beta - a)T\_s}{\tau}}\right)} \left[ e^{\frac{-(\beta - a)T\_s}{\tau}} - e^{\frac{-(\beta - a)T\_s - \Delta t(n)}{\tau}} \right]$$

$$= \frac{Q\_n}{\left(1 - e^{\frac{-(\beta - a)T\_s}{\tau}}\right)} e^{\frac{-(\beta - a)T\_s}{\tau}} \Bigg[1 - e^{-\frac{\Delta t(n)}{\tau}}\right]. \tag{8.7}$$

$$e\_f(n) \approx \frac{q\_n}{\pi \left(1 - e^{\frac{-(\beta - a)T\_\xi}{\pi}}\right)} e^{\frac{-(\beta - a)T\_\xi}{\pi}} \Delta t(n). \tag{9}$$

$$\sigma\_e^2 = E\{e^2\} = \left(\frac{q\_{rms}}{\tau \left(1 - e^{\frac{-(\beta - a)T\_s}{\tau}}\right)} e^{\frac{-(\beta - a)T\_s}{\tau}}\right)^2 \sigma\_f^2,\tag{10}$$

$$SNR|\_{Due to charge transfer \, jitter} = 10 \log \left( \frac{Q\_{rms}^2}{\left( \frac{Q\_{rms}}{\tau \left( 1 - e^{\frac{-(\beta - a)T\_2}{\tau}} \right)^2} e^{\frac{-(\beta - a)T\_2}{\tau}} \right)^2} \right)$$

$$= 10 \log \left( \frac{r^2 \left( 1 - e^{\frac{-(\beta - a)T\_2}{\tau}} \right)^2}{\left( e^{\frac{-(\beta - a)T\_2}{\tau}} \right)^2} \frac{1}{\sigma\_f^2} \right). \tag{11}$$

**Figure 7.** SNR variation with the input frequency due to charge transfer jitter for different rms jitter values. (a) � � �� �����. (b) � � �� ����. (c) � � �� ����.

The plots in Figure 7 show the limitation on the achievable SNR vs. the signal frequency due to charge transfer jitter for different values of the rms jitter ��. Typical values of � � ��� and ��� have been considered. The results are provided for � � �������, ������, and ������. As can be seen from the plots in Figure 7, for a given clock frequency, the SNR limitation due to charge transfer jitter is much more relaxed compared to the aperture jitter error (Figure 5). This result was expected because from equation (11), the effect of the jitter induced noise is reduced by an exponential factor indicating that charge transfer error in SC circuits should be less critical. This also can also be explained intuitively by noting that for the exponentially-decaying waveform in Figure 8, the amplitude of the pulse is rather low at the end of the clock-cycle and hence the amount of charge that varies over one clock period due to jitter is significantly reduced. However, for a given rms jitter and sampling frequency, the SNR limitation due to charge transfer jitter degrades as the discharging time-constant � increases. This is because the value of the charge transfer current at the end of the clockcycle (discharge phase) is varying exponentially with �, thus for a given timing error ��, the error in the amount of charge transferred is higher.

$$
\sigma\_e^2 = \sigma\_l^2 \ I\_\mathbb{S} \ ^2. \tag{12}
$$

$$
\sigma\_{signal}^2 = \frac{I\_S^{\ast^2} T\_s^{\ast^2}}{2}.\tag{13}
$$

$$SNR|\_{Due\ to\ pulse-worldth\ filter} = 10\ Log\ \left(\frac{\tau\_s}{2\sigma\_f^2}\right),\tag{14}$$

**(b)**

**(a)**

**(b)**

**Figure 9.** Pulse-width jitter in switched-current circuits.

**Figure 10.** SNR variation with the input frequency due to pulse-width jitter for different rms jitter values.

**Figure 11.** SNR variation with the sampling frequency due to different types of jitter induced errors for a rms jitter of 10 ps.

Thus, the SNR degradation by PWJ is less than that of the aperture jitter by a factor of ���. The plots in Figure 10 show the limitation on the achievable SNR vs. the signal frequency due to PWJ problem for different values of the rms jitter ��.

Figure 11 provides a comparative insight about the SNR limitation imposed by each one of the clock-jitter induced problems discussed above. It is worth noting that these plots are for Nyquist-rate sampling; however the foregoing analysis and results can be easily extended to include the effect of oversampling in oversampled circuits. As can be observed from the plots in Figure 11, for a given sampling frequency, the maximum limitation on the achievable SNR is caused by aperture jitter. However, the charge transfer jitter limits the SNR at very high frequencies; for example for an SNR of 80 dB, the charge transfer jitter starts to limit the achievable SNR at sampling frequency �� ≥ ����� for � � ������, and as mentioned before more robustness to charge transfer jitter at high frequencies can be obtained by reducing the discharging time-constant �.
