**2.4. Power saving and improved efficiency**

Minimization of DC-DC converter power losses is important to accommodate the growing need for a longer battery life and reduced size and weight of portable electronic devices. Power losses are usually dependent on the type of power devices and their conduction losses, the effective series resistance of inductors and capacitors, mode of operation of the converter, switching scheme, and the switching frequency. While diodes are simple in their use, they may reduce the efficiency of the converter due to their high losses in certain modes of operation. The same function of a diode can be achieved by using a switching power device similar to the main energy transfer device of the converter (e.g. GTO or MOSFET). This will require applying switching logic to multiple devices in the same converter. Synchronizing the switching of the devices introduces an additional control challenge and the converter topology is therefore referred to as the "synchronous" topology. The diode topology is then called "asynchronous". A detailed characterization of power losses in DC-DC converters is offered by Gildersleeve, et.al., (2002).

Various techniques were proposed in the literature to reduce power losses in DC-DC converters, including soft-switching (Zhou & Rincon-Mora, 2006), synchronous rectification (Djekic & Brkovic, 1997; Arbetter et al., 1995), mode hopping between CCM and DCM (Wang et al., 1997), Zero-Voltage Switching (Stratakos, 1998), mixed synchronousasynchronous control (Saggini et al., 2007), variable switching frequency (Djekic & Brkovic, 1997; Arbetter et al., 1995), and Hybrid Mode Hopping combined with variable frequency (Wang et al., 1997). These techniques are summarized and compared by Zhou (2003). Djekic et al. (1997) compared synchronous and asynchronous rectification buck converters for efficiency at various loads and switching frequencies. This work was extended to the buckboost converter recently (Fagerstrom & Bengiamin, 2011). The methodologies herein build on that latest work.

The basic asynchronous and synchronous converter topologies are given in Figs. 6.a and 6.b, respectively. Table 1 lists the sources of losses considered assuming a MOS switching device.



**Table 1.** Buck-Boost Converter Losses Considered

Extensive lists of DC-DC converter losses may be found in Zhou, S. (2003) and Djeki, O. & Brkovic, M. (1974). Buck-boost converter losses considered in this work are given in Table 1, as itemized and developed analytically in the following subsections. The PMOS is used for the Source Switch (SS) and NMOS is used for the Load Switch (LS), respectively.

a. PMOS Source Switch Conduction Loss

142 MATLAB – A Fundamental Tool for Scientific Computing and Engineering Applications – Volume 1

DC converters is offered by Gildersleeve, et.al., (2002).

on that latest work.

**Figure 6.** Buck-Boost Converter Architecture

NMOS Body Diode

Dead Time **Table 1.** Buck-Boost Converter Losses Considered

device.

This will require applying switching logic to multiple devices in the same converter. Synchronizing the switching of the devices introduces an additional control challenge and the converter topology is therefore referred to as the "synchronous" topology. The diode topology is then called "asynchronous". A detailed characterization of power losses in DC-

Various techniques were proposed in the literature to reduce power losses in DC-DC converters, including soft-switching (Zhou & Rincon-Mora, 2006), synchronous rectification (Djekic & Brkovic, 1997; Arbetter et al., 1995), mode hopping between CCM and DCM (Wang et al., 1997), Zero-Voltage Switching (Stratakos, 1998), mixed synchronousasynchronous control (Saggini et al., 2007), variable switching frequency (Djekic & Brkovic, 1997; Arbetter et al., 1995), and Hybrid Mode Hopping combined with variable frequency (Wang et al., 1997). These techniques are summarized and compared by Zhou (2003). Djekic et al. (1997) compared synchronous and asynchronous rectification buck converters for efficiency at various loads and switching frequencies. This work was extended to the buckboost converter recently (Fagerstrom & Bengiamin, 2011). The methodologies herein build

The basic asynchronous and synchronous converter topologies are given in Figs. 6.a and 6.b, respectively. Table 1 lists the sources of losses considered assuming a MOS switching

(a) asynchronous (b) synchronous

*Synchronous Asynchronous*  PMOS Conduction PMOS Conduction PMOS Switching PMOS Switching PMOS Gate Drive PMOS Gate Drive NMOS Conduction Diode Conduction NMOS Switching Diode Leakage

NMOS Gate Drive Diode Junction Capacitance

When the PMOS transistor is in forward conduction there is a resistive loss in accordance with Eq.(6). PMOS conduction loss is associated with both asynchronous and synchronous converters (Gildersleeve et al, 2002; Klien, J., 2006).

$$\text{PMOS Condition Loss} \triangleq \text{SScL} = I\_{\text{SS}}^2 R\_{\text{DS}} D \tag{6}$$

Where, ISS=PMOS current (Amp) RDS=PMOS forward conduction ON resistance (Ohm), D=duty ratio

b. PMOS Source Switch Switching Loss

During the transition of voltage rising or falling between the maximum and minimum steady-state values across either switch, and similarly the rise or fall transition of current through the same switch, losses occur. Much work has been done in an effort to correctly model this behavior (Klein, 2006; Xiong et al, 2009), without a highly accurate model still as yet developed. A combination of the work of Klein, (2006) and Xiong et al, (2009) are presented here to develop the switch model loss. The development starts with the following power loss equation.

$$\mathbf{P}\_{\rm SW} = \frac{1}{2} \mathbf{I}\_{\rm SW} \mathbf{V}\_{\rm SW} \mathbf{f}\_{\rm s} \left( \mathbf{t}\_{\rm s\rm \{eff\}} \, \star \mathbf{t}\_{\rm s\rm \{on\}} \right) \tag{7}$$

Where, PSW=MOSFET switching loss power (Watt), ISW=current through MOSFET (Amp), VSW=drain to source voltage across the MOSFET, fs=switching frequency (Hertz), ts(off)=MOSFET switching time transitioning off, ts(on)=MOSFET switching time transitioning on. All parameters of Eq. (7) are readily measurable in a physical circuit except the switching time terms toff and ton which are developed in the following equations.

$$\mathbf{t}\_{\text{s(on)}} = \frac{\mathbf{Q}\_{\text{G(SW)}}}{\mathbf{I}\_{\text{Driver(L-H)}}} \tag{8}$$

$$\mathbf{t}\_{s(\text{off})} = \frac{\mathbf{Q}\_{\text{G(SW)}}}{\mathbf{I}\_{\text{Driver(H-L)}}} \tag{9}$$

$$\mathbf{I}\_{\text{Driver(L-H)}} = \frac{\mathbf{V}\_{\text{DD}} \cdot \mathbf{V}\_{\text{SP}}}{\mathbf{R}\_{\text{Driver(Pull-up)}} + \mathbf{R}\_G} \tag{10}$$

$$\mathbf{I}\_{\text{Driver} \text{(H-L)}} = \frac{\mathbf{V}\_{\text{SP}}}{\mathbf{R}\_{\text{Driver} \text{(Pull-up)}} + \mathbf{R}\_{\text{G}}} \tag{11}$$

$$\mathbf{V\_{SP}} \approx \mathbf{V\_G} + \frac{\mathbf{I\_{SW}}}{\mathbf{G\_m}} \tag{12}$$

Where, QG(SW)=MOSFET switching-point gate charge (Coulomb), IDriver(L-H)=MOSFET gate current while switching on (Amp), IDriver(H-L)=MOSFET gate current while switching off, VDD=gate drive controller voltage, VSP=MOSFET gate voltage at switching point, RDriver(Pullup)=gate drive controller internal resistance, RG=MOSFET gate resistance, VG=MOSFET gate switching voltage, Gm=MOSFET transconductance.

Combining Eqs. (7) through (12) gives the combined switching loss Eq. (13).

$$\mathbf{P\_{sw}} = \frac{1}{2} \mathbf{I\_{SW}} \mathbf{V\_{SW}} \mathbf{f\_{S}} \mathbf{Q\_{G(SW)}} \mathbf{G\_{m}} \left( \mathbf{R\_{Dirver(Full-ap)}} + \mathbf{R\_{G}} \right) \left( \frac{1}{\mathbf{V\_{G}} \mathbf{G\_{m}} + \mathbf{I\_{SW}}} + \frac{1}{\mathbf{V\_{DD}} \mathbf{G\_{m}} - \mathbf{V\_{G}} \mathbf{G\_{m}} - \mathbf{I\_{SW}}} \right) \tag{13}$$

#### c. PMOS Source Switch Gate Drive Loss

Gate drive loss accounts for the energy dissipated by the MOSFET to drive the gate for the switching operation. The loss equation is given in Eq. (14). PMOS gate drive loss is associated with both converters.

$$\text{PMOS Gate Drive Loss} \triangleq \text{gdL} = \mathbf{Q}\_{\text{G(SW)}} \mathbf{V}\_{\text{G}} \mathbf{f} \tag{14}$$

#### d. NMOS Load Switch Conduction Loss

Load switch conduction loss is similar to that of the source switch shown in Eq. (6), differing by the (1-D) factor as this loss occurs during the latter portion of the switching period. This loss is represented in Eq. (15). NMOS conduction loss is associated with only the synchronous converter.

$$\text{NMOS Condition Loss} \triangleq \text{LScL} = \text{I}\_{\text{LS}}^2 \text{R}\_{\text{DS}} \text{(1-D)} \tag{15}$$

Where, ILS=load switch drain to source voltage.

e. NMOS Load Switch Switching Loss

The load switch MOSFET switching loss is calculated with the same model as the source switch shown in Eq. (14). NMOS switching loss is associated with only the synchronous converter.

f. NMOS Load Switch Gate Drive Loss

NMOS gate drive loss is accounted for by simply doubling the gate drive loss Eq. (15) for the synchronous case. NMOS gate drive loss is associated with only the synchronous converter.

#### g. NMOS Load Switch Body Diode Loss

144 MATLAB – A Fundamental Tool for Scientific Computing and Engineering Applications – Volume 1

<sup>V</sup> I =

SP G

<sup>I</sup> V V+

Where, QG(SW)=MOSFET switching-point gate charge (Coulomb), IDriver(L-H)=MOSFET gate current while switching on (Amp), IDriver(H-L)=MOSFET gate current while switching off, VDD=gate drive controller voltage, VSP=MOSFET gate voltage at switching point, RDriver(Pullup)=gate drive controller internal resistance, RG=MOSFET gate resistance, VG=MOSFET gate

2 V G +I V G V G I

Gate drive loss accounts for the energy dissipated by the MOSFET to drive the gate for the switching operation. The loss equation is given in Eq. (14). PMOS gate drive loss is

G(SW) G s PMOS Gate Drive Loss gdL = Q V f (14)

Load switch conduction loss is similar to that of the source switch shown in Eq. (6), differing by the (1-D) factor as this loss occurs during the latter portion of the switching period. This loss is represented in Eq. (15). NMOS conduction loss is associated with only the

<sup>2</sup> NMOS Conduction Loss LScL= I R 1-D LS DS (15)

The load switch MOSFET switching loss is calculated with the same model as the source switch shown in Eq. (14). NMOS switching loss is associated with only the synchronous

NMOS gate drive loss is accounted for by simply doubling the gate drive loss Eq. (15) for the synchronous case. NMOS gate drive loss is associated with only the synchronous

Driver(H-L)

Combining Eqs. (7) through (12) gives the combined switching loss Eq. (13).

<sup>1</sup> 1 1 P = I V f Q G R +R <sup>+</sup>

switching voltage, Gm=MOSFET transconductance.

sw SW SW s G SW m Driver(Pull-up) G

c. PMOS Source Switch Gate Drive Loss

d. NMOS Load Switch Conduction Loss

Where, ILS=load switch drain to source voltage.

e. NMOS Load Switch Switching Loss

f. NMOS Load Switch Gate Drive Loss

associated with both converters.

synchronous converter.

converter.

converter.

SP

Driver(Pull-up) G

SW

m

R +R (11)

<sup>G</sup> (12)

G m SW DD m G m SW

(13)

  The load switch body diode loss occurs only in the load switch due to the reverse bias during the ON portion of the period (Djekic et al., 1997). The reverse-bias voltage and leakage current dissipate power according to the equation shown in Eq. (16). NMOS body diode loss is associated with only the synchronous converter.

$$\text{NMOS Body Diode Loss} \triangleq \text{LSbdL} = \text{i}\_{\text{leakage}} \text{V}\_{\text{LS}} \text{D} \tag{16}$$

Where, *ileakage*=reverse bias leakage current, *VLS*=load switch drain to source voltage.

h. Synchronous Switching Dead-Time Loss

Dead-time loss occurs through the load switch when neither transistor is on as the load switch is in forward conduction (Klien, 2006). A period of dead-time must exist to prevent current "shoot-through" whereby current flows through both switches simultaneously to the load. The value of *tdead* is assumed to be 60 ns as is typical for DC-DC converter controllers (Djekic & Brkovic, 1997). The dead-time loss representation is shown in Eq. (17). Synchronous switching dead-time loss is associated with only the synchronous converter.

$$\text{Deepl-Time Loss} \triangleq \text{deadL} \\ \text{=I}\_{\text{load}} \\ \text{V}\_{\text{LS}} \text{f}\_{\text{s}} \text{t}\_{\text{dead}} \tag{17}$$

Where, *Iload*=load current, *tdead*=time where both switches are off.

i. Diode Conduction Loss

Diode forward conduction losses are found with the equation shown in Eq. (18). Diode conduction loss is associated with only the asynchronous converter.

$$\text{Diode Condition Loss } \triangleq \text{ Dcf} \\ \text{=} \text{I}\_{\text{D}} \text{V}\_{\text{f}} \\ \text{(1-D)} \tag{18}$$

Where, *ID*=current through diode, *Vf*=diode forward voltage.

j. Diode Reverse Bias Loss

During the portion of the period *d*, the diode has a reverse bias across it. There is a certain amount of leakage current under this condition that is listed by the manufacturer on the data sheet. This value is used to calculate diode reverse bias leakage loss in Eq. (19). Diode reverse bias loss is associated with only the asynchronous converter.

$$\text{'Diode Reverese Bias Loss } \triangleq DrbL = V\_D \dot{i}\_{\text{leakage}} D \tag{19}$$

Where, *VD*=voltage across diode.

k. Diode Junction Capacitance Loss

Diodes have a certain capacitance associated with changing voltages across them (Klein, J., 2006). The charging and discharging of this capacitance creates a power loss as modeled by Eq. (20). Diode junction capacitance loss is associated with only the asynchronous converter.

$$\text{Diode Capacity Loss } \triangleq \text{ DcapL} = \frac{\text{CV}\_{\text{D}}^2 \text{f}\_s}{2} \tag{20}$$
