**6. Experimental of 3-phase 4-wire voltage sag generator**

From section 3 the SagWave software generates the parameter file and sends it to the dsPIC microcontroller. The dsPIC uses this file to control the 3-phase 4-leg 4-wire inverter in order to create the actual waveform. Experimental results for voltage sag types A, B and E are shown in Fig. 27-29, respectively.

The experimental results in Fig. 27 are according with simulation results in Fig.24 (Type A). Fig.27 shows the 3-phase voltage and 3-phase current of voltage sag Type A. During voltage sag, the voltage on phase A ( *Va* ), phase B ( *Vb* ) and phase C ( *Vc* ) are reduced to 60%. The current on phase A ( *aI* ), phase B ( *bI* ) and phase C ( *<sup>c</sup> I* ) also are reduced to 60%. Before voltage sag occurs, the neutral current ( *nI* ) has zero currents due to the balanced load condition. However during voltage sag transition, the unbalance load currents causes nonzero in the neutral current ( *nI* ).

**Figure 29.** Voltage sag Type A.

**Figure 30.** Voltage sag Type B.

**Figure 31.** Voltage sag Type E.

**Figure 32.** Experimental result: a) point on wave at 45 b) point on wave at 45 c) point on wave at 270

**Figure 33.** Experimental results: a) 4 repeated voltage sag b) 6 repeated voltage sag

The experimental results in Fig. 28 are according with simulation results in Fig.24(Type B). Fig.28 shows the 3-phase voltage and 3-phase current of voltage sag Type B. During voltage sag, the voltage on phase A ( *Va* ) is reduced to 60%. The current on phase A ( *aI* ) also is reduced to 60%. Before voltage sag occurs, the neutral current ( *nI* ) has zero currents due to the balanced load condition. However during voltage sag, the unbalance load causes an increase in the neutral current ( *nI* ) that the return current in fourth leg of inverter.

The experimental results in Fig. 29 are according with simulation results in Fig.24 (Type E). Fig. 29 shows the 3-phase voltage and 3-phase current of voltage sag Type E. During voltage sag, the voltage on phase B ( *Vb* ) and phase C ( *Vc* ) are reduced to 60%. The current on phase A( *aI* ) is constant, while current on phase B ( *bI* ) and current on phase C ( *<sup>c</sup> I* ) are reduced to 60%. Before voltage sag occurs, the neutral current (In) has zero currents due to the balanced load condition. However during voltage sag, the unbalance load causes an increase in the neutral current ( *nI* ) that the return current in fourth leg of inverter.

The experimental results of point on wave are shown in Fig. 30. The sag generator can generate waveform at any point of wave of sine wave as desired.

The experimental results of repeated voltage sags are shown in Fig. 31. The sag generator can generate repeated voltage sag waveform as many as desired.
