**5. Modeling and simulation of Jitter effects in CT ΔƩ modulators using Matlab/Simulink**

In this section, Matlab/Simulink models for the jitter induced errors in different DAC types are shown. The models are based on the expressions of the additive jitter errors developed in the previous section and will be verified by simulations. Figure 17 shows the Simulink models for RZ, NRZ and SCR DACs, including the additive jitter errors based on the expressions in (15), (19), and (25), respectively. Note that these additive errors in the feedback should be multiplied by the gain coefficient of their respective feedback path. These models are examined through simulations in Matlab/Simulink to verify their accuracy and compliance with the developed analysis. The feed-forward third-order single-bit CT ΔƩ modulator in Figure 18 is used as a test vehicle for the system-level simulations. The modulator operates at an OSR of 100 with a target ENOB of 13 bits over a baseband channel bandwidth of 1.92 MHz for the WCDMA standard. The noise budgeting for the ADC to achieve the required ENOB is given in Table 1. Table 2 lists the specifications and summary of the achievable performance of the modulator when an SCR DAC model is used with DAC time-constant ߬ ൌ ͲǤͳܶௌ. Recall that an SCR DAC is a convenient option to provide robustness to clock-jitter and maintain the low percentage of the jitter induced noise in the noise budget. The dynamic-range (DR) and PSD plots of the modulator are given in Figure 19 and Figure 20. The maximum signal-tonoise-plus-distortion ratio (SNDR) is calculated as 80dB.

To examine the sensitivity of the modulator to clock-jitter for different DAC types by simulations, the appropriate model for the feedback DAC including the additive jitter errors is chosen from the ones in Figure 17, according to the adopted DAC type (RZ, NRZ, or SCR), and is added to the Simulink model of the complete modulator. The plots in Figure 21 imply that for sufficiently large rms jitter in the DAC sampling-clock, the IBJN increases significantly and dominate the total in-band noise (IBN). For the SCR DAC, it can be seen from the plots in Figure 21(c) that the robustness to clock-jitter degrades proportionally with the DAC time-constant ߬, as discussed earlier in the analysis. To compare the robustness to clock-jitter in the three DAC types, IBJN plots are combined together in Figure 22, and it is evident that the SCR DAC is the most tolerant to DAC jitter while RZ DAC is the most sensitive.

**Figure 18.** Adopted modified feed-forward CT single-bit ΔƩ modulator.


**Table 1.** Modulator noise budget

416 MATLAB – A Fundamental Tool for Scientific Computing and Engineering Applications – Volume 1

noise-plus-distortion ratio (SNDR) is calculated as 80dB.

**Figure 18.** Adopted modified feed-forward CT single-bit ΔƩ modulator.

**Matlab/Simulink** 

sensitive.

**5. Modeling and simulation of Jitter effects in CT ΔƩ modulators using** 

In this section, Matlab/Simulink models for the jitter induced errors in different DAC types are shown. The models are based on the expressions of the additive jitter errors developed in the previous section and will be verified by simulations. Figure 17 shows the Simulink models for RZ, NRZ and SCR DACs, including the additive jitter errors based on the expressions in (15), (19), and (25), respectively. Note that these additive errors in the feedback should be multiplied by the gain coefficient of their respective feedback path. These models are examined through simulations in Matlab/Simulink to verify their accuracy and compliance with the developed analysis. The feed-forward third-order single-bit CT ΔƩ modulator in Figure 18 is used as a test vehicle for the system-level simulations. The modulator operates at an OSR of 100 with a target ENOB of 13 bits over a baseband channel bandwidth of 1.92 MHz for the WCDMA standard. The noise budgeting for the ADC to achieve the required ENOB is given in Table 1. Table 2 lists the specifications and summary of the achievable performance of the modulator when an SCR DAC model is used with DAC time-constant ߬ ൌ ͲǤͳܶௌ. Recall that an SCR DAC is a convenient option to provide robustness to clock-jitter and maintain the low percentage of the jitter induced noise in the noise budget. The dynamic-range (DR) and PSD plots of the modulator are given in Figure 19 and Figure 20. The maximum signal-to-

To examine the sensitivity of the modulator to clock-jitter for different DAC types by simulations, the appropriate model for the feedback DAC including the additive jitter errors is chosen from the ones in Figure 17, according to the adopted DAC type (RZ, NRZ, or SCR), and is added to the Simulink model of the complete modulator. The plots in Figure 21 imply that for sufficiently large rms jitter in the DAC sampling-clock, the IBJN increases significantly and dominate the total in-band noise (IBN). For the SCR DAC, it can be seen from the plots in Figure 21(c) that the robustness to clock-jitter degrades proportionally with the DAC time-constant ߬, as discussed earlier in the analysis. To compare the robustness to clock-jitter in the three DAC types, IBJN plots are combined together in Figure 22, and it is evident that the SCR DAC is the most tolerant to DAC jitter while RZ DAC is the most


**Table 2.** Modulator specifications and performance summary

**Figure 19.** Dynamic-range of the adopted ΔƩ modulator.

**Figure 20.** PSD at the modulator output calculated using 32768 FFT points with 16 averages. .ࢠૠ ൌ ,െ ൌ

*SNDR = 80.8dB*

**Figure 20.** PSD at the modulator output calculated using 32768 FFT points with 16 averages.

<sup>10</sup><sup>1</sup> <sup>10</sup><sup>2</sup> <sup>10</sup><sup>3</sup> <sup>10</sup><sup>4</sup> <sup>10</sup><sup>5</sup> <sup>10</sup><sup>6</sup> -120

*Frequency, KHz*

**(a)**

*jitter / Ts, %*

<sup>10</sup>-3 <sup>10</sup>-2 <sup>10</sup>-1 <sup>10</sup><sup>0</sup> <sup>10</sup><sup>1</sup> -120

.ࢠૠ ൌ ,െ ൌ







*dBFS*




*IBJN Total IBN*




*FFT Magnitude dBFS*



0

**(c)**

**Figure 21.** Sensitivity plots of the ΔƩ modulator in Figure 18 to clock-jitter in the DAC. ൌ െ, ൌ Ǥ ૢࢠ.) a) RZ DAC. (b) NRZ DAC. (c) SCR DAC.

**Figure 22.** IBJN plots for the ΔƩ modulator in Figure 18 using different DAC types. .ࢠૢ Ǥ ൌ ,െ ൌ

#### **6. Conclusion**

In this chapter, the effects of clock-jitter in the sampling-clocks of ΔƩ modulators are analyzed and studied in details. The critical sources of jitter induced errors in a ΔƩ loop are discussed for ΔƩ modulators with DT and CT loop filters. The comparison between DT and CT modulators showed that CT architectures are more sensitive to clock-jitter than DT counterparts due to PWJ in the feedback signal caused by clock-jitter in the DAC samplingclock. In essence, PWJ in the feedback waveform entails random phase-modulation that folds back high-pass shaped noise components over the desired channel bandwidth. Thus, a detailed analysis for the sensitivities of various signal waveforms provided by different types of CT DACs to clock-jitter is given thereafter. Also, efficient Matlab/Simulink models for additive errors induced by clock-jitter in the feedback DACs are shown so that to help designers characterize the sensitivities of various types of CT ΔƩ architectures to clock-jitter and obtain the specification requirement on the rms jitter of the sampling-clock for a given target performance. Furthermore, modeling of jitter induced errors is beneficial for systemlevel simulations adopted in the process of developing efficient solutions and modulator or DAC architectures that can remedy the effects of clock-jitter on the ΔƩ modulator performance. The robustness of these models is verified by CT simulations in Matlab/Simulink and simulations results show good agreement with the theoretical expectations.
