**3. Sensitivity of ΔƩ modulators to clock-jitter**

The purpose of this section is to address the effects of clock-jitter in the two main classes of ΔƩ modulators, shown in Figure 12, and provide a comparison between them in terms of sensitivity to clock-jitter. In order to determine the performance sensitivity to clock-jitter in DT and CT modulators, the critical sources of jitter induced errors in the loop should be identified in each one. The most critical clock-jitter errors in a ΔƩ modulator are those generated at the modulator input and in the feedback path through the outermost DAC feeding the first stage in the loop filter (recall that errors generated at inner nodes in the loop are suppressed by the previous stages of the loop filter).

The feedback signal is carrying a digital data (coming from the loop quantizer) and hence it is robust to aperture jitter2. However, depending on the type of the adopted feedback DAC, the feedback signal in a ΔƩ loop can suffer one of the other two kinds of jitter induced errors (namely, charge transfer jitter and PWJ). The effect of feedback jitter can be further discussed in the frequency domain with the aid of Figure 13 as follows. Recall that the modulator feedback signal includes the in-band desired signal (input signal) and the high-pass shaped noise. Since the sampling process ideally is a multiplication in time, the spectra of the analog input signal and the clock signal convolve. Thus, the error generated by DAC clock PN has two main components, as illustrated by Figure 13. First, the clock PN components close to the clock frequency modulates the in-band desired signal resulting in signal side-bands in the same manner like the PN of an upfront sampler [5]. Second, the wideband clock PN, modulates the high-pass shaped noise components and the modulation products fall over the desired band and hence elevate the in-band noise level.

**<sup>2</sup>** Since the digital data coming in the feedback is usually sampled at the middle of the clock-cycle, sampled signal in the feedback can suffer aperture jitter only if the clock-jitter is ≥ ����.

due to PWJ problem for different values of the rms jitter ��.

obtained by reducing the discharging time-constant �.

**3. Sensitivity of ΔƩ modulators to clock-jitter** 

are suppressed by the previous stages of the loop filter).

the feedback can suffer aperture jitter only if the clock-jitter is ≥ ����.

level. 

Thus, the SNR degradation by PWJ is less than that of the aperture jitter by a factor of ���. The plots in Figure 10 show the limitation on the achievable SNR vs. the signal frequency

Figure 11 provides a comparative insight about the SNR limitation imposed by each one of the clock-jitter induced problems discussed above. It is worth noting that these plots are for Nyquist-rate sampling; however the foregoing analysis and results can be easily extended to include the effect of oversampling in oversampled circuits. As can be observed from the plots in Figure 11, for a given sampling frequency, the maximum limitation on the achievable SNR is caused by aperture jitter. However, the charge transfer jitter limits the SNR at very high frequencies; for example for an SNR of 80 dB, the charge transfer jitter starts to limit the achievable SNR at sampling frequency �� ≥ ����� for � � ������, and as mentioned before more robustness to charge transfer jitter at high frequencies can be

The purpose of this section is to address the effects of clock-jitter in the two main classes of ΔƩ modulators, shown in Figure 12, and provide a comparison between them in terms of sensitivity to clock-jitter. In order to determine the performance sensitivity to clock-jitter in DT and CT modulators, the critical sources of jitter induced errors in the loop should be identified in each one. The most critical clock-jitter errors in a ΔƩ modulator are those generated at the modulator input and in the feedback path through the outermost DAC feeding the first stage in the loop filter (recall that errors generated at inner nodes in the loop

The feedback signal is carrying a digital data (coming from the loop quantizer) and hence it is robust to aperture jitter2. However, depending on the type of the adopted feedback DAC, the feedback signal in a ΔƩ loop can suffer one of the other two kinds of jitter induced errors (namely, charge transfer jitter and PWJ). The effect of feedback jitter can be further discussed in the frequency domain with the aid of Figure 13 as follows. Recall that the modulator feedback signal includes the in-band desired signal (input signal) and the high-pass shaped noise. Since the sampling process ideally is a multiplication in time, the spectra of the analog input signal and the clock signal convolve. Thus, the error generated by DAC clock PN has two main components, as illustrated by Figure 13. First, the clock PN components close to the clock frequency modulates the in-band desired signal resulting in signal side-bands in the same manner like the PN of an upfront sampler [5]. Second, the wideband clock PN, modulates the high-pass shaped noise components and the modulation products fall over the desired band and hence elevate the in-band noise

**<sup>2</sup>** Since the digital data coming in the feedback is usually sampled at the middle of the clock-cycle, sampled signal in

**(a)**

**(b)**

**Figure 12.** ΔƩ Modulators. (a) Continuous-Time. (b) Discrete-Time.

**Figure 13.** Modulation of in-band desired signal and shaped quantization noise by phase-noise in the DAC sampling clock.

**Figure 14.** Non-inverting switched-capacitor discrete-time integrator.

#### **3.1. DT ΔƩ modulators**

In DT ΔƩ modulators, the sampling takes place at the modulator input. The SC integrator in Figure 14 is commonly used as an input stage for DT loop filters in ΔƩ modulators. The sampling aperture jitter errors due to the sampling switch (*S1*) will be added to the signal at the input and hence will directly appear at the modulator output without any suppression. As mentioned earlier, the feedback signal (*VDAC*) doesn't experience aperture jitter because the feedback signal is DT and also it has discrete amplitude levels. Thus, timing errors cannot result in a sampled value that is different from the original feedback one. Timing errors at switch *S2* cause charge transfer jitter errors being added at the input stage. However, the charge transfer jitter errors at *S2* are very small owing to the high robustness of the exponentially-decaying waveform to clock-jitter and moreover ܴைே of the switches are usually very small resulting in a small time-constant ߬ which gives more jitter robustness to the waveform (recall the analysis given in the previous section).

According to the above discussion, the jitter induced noise in DT ΔƩ modulators is mainly dominated by the aperture error at *S1*. At a given sampling speed, the only way to improve the performance of DT ΔƩ modulators is to improve the jitter performance of the clock generator which translates into significant increase in the total power consumption in case of ΔƩ ADCs targeting high resolution. On the other hand, for a given rms jitter, if the sampling frequency is reduced for the sake of improving tolerance to jitter errors, then to achieve high resolution at the resulting low OSR, the filter order and/or the quantizer levels need to be increased. This translates into significant power penalty too. Moreover, this approach wouldn't work for state-of-the-art wireless standards with continuously increasing channel bandwidths.
