**4. Architectures**

34 Introduction to PID Controllers – Theory, Tuning and Application to Frontier Areas

The optimal tracking problem (Kwakernaak & Sivan, 1972) is to find an admissible input *u(t)* such that the tracking objective (5) is minimized subject to the dynamic constraints (1-

In order to solve the Optimal Tracking Problem we augment the state variables (Kwakernaak & Sivan, 1972) and further assume that *A=Ar*, *B=Br* and *C=Cr*. This assumption states that the nominal values of the plant's parameters are known. The case *A≠Ar*, *B≠Br* and

00 0 0

00 0 0

then the problem is minimization of (5) subject to (1-4) is the problem of minimization of

1

*t*

*o*

*t*

<sup>2</sup> { ( ) ( ) [ ( ) ( ) ( ) ( )] }

1 2 <sup>0</sup>

<sup>1</sup> , () . *<sup>T</sup>*

*P PA A P Q PBR BP P t G*

 <sup>1</sup> 11 12 1 2 *<sup>T</sup> x x e e*

*u = R B P P K K*

Notice that the solution is independent of the reference trajectory generator input, *wr* .

*<sup>T</sup> G C GC G* 

*J E X t GX t X t QX t u t Ru t dt* (8)

, () , *X AX Bu Bw x t x r oo* (9)

1

*f*

(11)

0 1.

*T TT*

*C*

; 0 00 ; ; 00 0 0

00 0

*X A C B CC*

 

*e B A*

 

; () , *x x r x o ro o e Ae Bw Bu e t x x* (6)

(7)

(10)

(12)

All vectors and matrices are of the proper dimension.

**3. Solution of the optimal tracking problem** 

*C≠Cr* is beyond the scope of this chapter.

1 1 2 2

1

*e*

*C*

*m em*

*e*

*f f*

1 2 <sup>0</sup> 0 1, <sup>1</sup>

*<sup>T</sup> Q C QC Q* 

The solution is (Kwakernaak & Sivan, 1972) (Bryson & Ho, 1969)

1

*u R BP X*

If we appropriately partition *P*, then

We have the error system

*x*

subject to

where

4).

As stated in the introduction Architecture deals with the connections between the outputs/sensors and the inputs/actuators; Structure deals with the specific realization of the controllers' blocks; and Configuration is a specific combination of architecture and structure. These issues fall within the of control and feedback organization theory (Rusnak, 2006, 2008), and are beyond the scope of this chapter.

In this chapter we deal with three specific architectures. These are:


#### **4.1 Parallel controller architecture**

This control architecture is directly derived from the Solution of the Optimal Tracking Problem as derived in (Asseo, 1970) and in (12). The parallel controller can be written directly from (12) in Laplace domain as

$$\begin{aligned} \mu(\mathbf{s}) &= \sum\_{i=1}^{n} \mathbf{C}\_{i}(\mathbf{s}) \left( \mathbf{x}\_{ri}(\mathbf{s}) - \mathbf{x}\_{i}(\mathbf{s}) \right) = \sum\_{i=1}^{n} \mathbf{C}\_{i}(\mathbf{s}) e\_{i}(\mathbf{s}) \\ &= \mathbf{C}\_{1}(\mathbf{s}) \left( \mathbf{x}\_{r1}(\mathbf{s}) - \mathbf{x}\_{1}(\mathbf{s}) \right) + \dots + \mathbf{C}\_{n}(\mathbf{s}) \left( \mathbf{x}\_{rn}(\mathbf{s}) - \mathbf{x}\_{n}(\mathbf{s}) \right) \end{aligned} \tag{13}$$

For 2nd order system the parallel controller architecture takes the form.

$$\mu(\mathbf{s}) = \mathbb{C}\_1(\mathbf{s}) \left( \mathbf{x}\_{r1}(\mathbf{s}) - \mathbf{x}\_1(\mathbf{s}) \right) + \mathbb{C}\_2(\mathbf{s}) \left( \mathbf{x}\_{2r}(\mathbf{s}) - \mathbf{x}\_2(\mathbf{s}) \right) \tag{14}$$

Figure 1 presents the block diagram of the parallel controller architecture for a 2nd order system.

Fig. 1. Parallel controller architecture for 2nd order system.

#### **4.2 Cascade controller architecture**

By elementary block operation (13) can be written as

$$\begin{split} \mu(\mathbf{s}) = \mathsf{C}\_{n}(\mathbf{s}) \{ (\mathbf{x}\_{r\_{n}}(\mathbf{s}) - \mathbf{x}\_{n}(\mathbf{s})) + \frac{\mathsf{C}\_{n-1}(\mathbf{s})}{\mathsf{C}\_{n}(\mathbf{s})} [(\mathbf{x}\_{r\_{n-1}}(\mathbf{s}) - \mathbf{x}\_{n-1}(\mathbf{s})) \\ + \frac{\mathsf{C}\_{n-2}(\mathbf{s})}{\mathsf{C}\_{n-1}(\mathbf{s})} [(\mathbf{x}\_{r\_{n-2}}(\mathbf{s}) - \mathbf{x}\_{n-2}(\mathbf{s})) + \frac{\mathsf{C}\_{n-3}(\mathbf{s})}{\mathsf{C}\_{n-2}(\mathbf{s})} [(\mathbf{x}\_{r\_{n-3}}(\mathbf{s}) - \mathbf{x}\_{n-3}(\mathbf{s})) + \dots \\ + \frac{\mathsf{C}\_{1}(\mathbf{s})}{\mathsf{C}\_{2}(\mathbf{s})} (\mathbf{x}\_{r\_{1}}(\mathbf{s}) - \mathbf{x}\_{1}(\mathbf{s}))] \dots \} \end{split} \tag{15}$$

Family of the PID Controllers 37

As a first order system is considered, this leads to the one block controller architecture only.

1

 

*e*

This is the proportional + double integrator - PI2 controller.

*x*

*T x*

*or e*

  *T x x*

11 12 1 2 1 2

*e e u = R B P P k k k e k e dt*

<sup>1</sup> ( ) *k ks k C s = k*

 

1

 

212

*s s*

11 12 1 21 22 1 1 21 22

*u = R B P P k k k k e k e dt k e dt*

<sup>1</sup> 2 2 ( ) *k k ks k s k C s = k s s s*

21 2

*x*

*e*

1,

*mm m x*

  2

2 21 22 1 21 22

( )

*or e*

  *m*

*x*

, ,

*or e*

*x*

(22)

*e*

*u = k e k x x* 1 1 *x r* (18)

<sup>1</sup> *C s = k* ( ) (19)

*x x*

(21)

*xx x*

(23)

(20)

(24)

**5. Controllers for first order system** 

This is the proportional - P controller.

1

1

*x*

*e*

This is the proportional + Integral - PI controller.

**5.1 P controller**  Here we have

**5.2 PI controller**  Here we have

**5.3 PI<sup>2</sup>**

Here we have

 **controller** 

1

**5.4 PIm controller**  Here we have

21 2

, *x*

1

*e*

This is the cascade controller architecture. For 2nd order system the cascade controller architecture takes the form.

$$\mu(\mathbf{s}) = \mathbb{C}\_2 \left[ \left( \mathbf{x}\_{r2} - \mathbf{x}\_2 \right) + \frac{\mathbf{C}\_1}{\mathbf{C}\_2} (\mathbf{x}\_{r1} - \mathbf{x}\_1) \right] = \mathbb{C}\_v \{ (\mathbf{x}\_{r2} - \mathbf{x}\_2) + \mathbf{C}\_p (\mathbf{x}\_{r1} - \mathbf{x}\_1) \} \tag{16}$$

Figure 2 presents the block diagram of the cascade controller architecture for a 2nd order system. The rationale for the notation of *Cp* (position) and *Cv* (velocity) will be presented in the sequel.

Fig. 2. Cascade controller architecture for 2nd order system.

#### **4.3 One block controller architecture**

By elementary operation on (13), and exploiting the relations between the state space variables, the one block controller architecture can be written as

$$
\mu(\mathbf{s}) = \mathbf{C}(\mathbf{s}) \left( \mathbf{x}\_{1r}(\mathbf{s}) - \mathbf{x}\_{1}(\mathbf{s}) \right) \tag{17}
$$

Figure 3 presents the block diagram of the one block controller architecture.

Fig. 3. One block controller architecture.

#### **4.4 Discussion**

Although from input-output transfer function point-of-view, there is no formal difference between the different architectures, there is difference with respect to the response to initial conditions, effects of saturation and nonlinearities, robustness, and more.
