**3.2 P-Node + C-Node performance evaluation by XDD bench**

In this section we evaluate C-Node L4 cache management policy as L3<L4. The objective of this experiment is to carry out performance evaluation of P-Node + C-Node using L3/L4 cache (combined performance gain due to L3 and L4 caches). This evaluation shows that the high I/O cache node doesn't maintain the I/O performance gain stable. The I/O performance gain calculates by Amdahl's law as shown in equation (1).

$$\mathbf{G}\_{i} = \frac{\mathbf{1}}{\mathbf{1} - \mathbf{C}\_{i} + \frac{\mathbf{C}\_{i}}{X\_{i}}} \prod\_{j=1}^{m} L\_{i,j}. \tag{1}$$

Gi = cache gain, Ci = cache hit ratio

232 Emerging Informatics – Innovative Concepts and Applications

assurance purpose. One of C-Node is mounted one of L3 cache node and other one is mounted no L3 cache as standard drive access way. Therefore, two P-Node with two C-Node partitions are required to maintain high latency of I/O. Thus, two partitions are required physically to achieve low latency of time for the write event. But, in two node configuration, there is no assurance policy against one node failure. Seeing from online function sustainability, three nodes is minimum number for a group. Each P-Node is connecting C-Node for its representative. Therefore, the combinations between P-Node and C-Node require the same number of nodes. To consider the online availability, the number of nodes is determined by Scale-out for the system. The latency of time and its overhead and threshold value are evaluated. Then it is determined about the number of nodes which can be easily managed. About online availability, what is the best number of node on each Data Field is evaluated. Proposing architecture has trio node group and when the event of one of node failed, the node availability of system level is 7/8. If node number n is same as node number n, its redundancy is much higher than Trio node n=3. But there are so many data communication on Processing Data Field and Content Data Field. For example, Dual node is 3/4, Trio node is 7/8 and Quad node is 15/16. 3/4 < 7/8 < 15/16 Therefore, quad node is higher than others. But, IO transaction is n\*(n-1)/2 by Metcalfe's law. Therefore, its network

Moreover, management cost of cache coherency and cache size on each node is 1/n size from original cache size. Therefore, ½, 1/3 and ¼ cache size is utilized. It significantly reduces cache size. This matter generates very big impact of cache performance and less cache hit ratio. Therefore, Trio node plus two partitions is much better architecture in

overhead is

NP *(dual)* = 2\*1/2 = 1 NP *(Trio)* = 3\*2/2 = 3 NP *(Quad)* = 4\*3/2 = 6

Fig. 7. n-Node simulation

comparison with other number of nodes architecture.

Xi= cache device speed gain compare target device speed.

Lij = overhead for cache program.

Therefore, if the access doesn't hit the cache, performance drops more than original target drive speed because cache overhead exists. To manage this cache behavior, multi-layer cache system architecture with balanced cache ratio is key factor. This experiment carries out two scenarios under this hardware and XDD benchmark test was utilized as shown in Table 2.


Table 2. System specifications for system configuration

The evaluation of I/O performance of L3 cache on P-Node against OS UBC cache has been carried out on Linux Kernel 2.6.24 rt27 32bit by XDD65.013007 as shown in Figure 8 (a), (b) and (c). In this scenario sequential read and write data types are utilized. Interoperable (two way) I/O types read/write (50% 50%) are evaluated in this scenario. The test files are 4KB, 64KB and 128KB on each access type for L3 cache in comparison with OS based UBC cache.

Autonomous Decentralized Multi-Layer

node community expansion / reduction technology design.

IEEE Computer, 31(4):32-34, April 1998.

trends. In Proc. of ISADS, IEEE, pages 28-34, 1993

Computer Architecture pp. 114 - 121 (1989). [6] Moore's law www.intel.com/technology/mooreslaw/ index.htm

Sciences, Vol. E83-A, No.11 pp.2228-2235, November 2000

**4. Conclusion** 

**5. References** 

IEEE, May 2000

Cache System to Low Latency User Push Web Services 235

Web service is heterogeneously demand model in today. User push type web service is so popular such as twitter and SNS. The demand from them is web evolving target model behavior. Therefore, web service needs adaptability, online expandability and data availability. Increasing user push type web service demand has dynamic behavior. Therefore the management of the coherency of written data is also a big issue. Proxy server is read cache model and it is data duplication model but it doesn't support duplication write data event dynamically. It also doesn't support coherency of write data too. Maintaining the low latency of time, single Data Field model can't achieve these issues with limited size of write cache memory space. The proposed system architecture ensures 1) Adaptability for user push type web service demands and 2) online node sustainability and 3) low latency of write data without write cache size limit and 4) P-node /C-Node cache autonomous contribution. Utilize L3 cache and L4 cache benefits by P-Node/C-Node L3/L4 cache. The write data coherency issues, P-Node plus C-Node write eventually Consistency process is enabled it. The concept is always executed by L3 cache P-Node and it guarantees the write event latency minimum network hops. Therefore, it achieves the low latency of time write I/O event for real time web application. P-Node also performs read data performance by L3 cache. L3 cache on P-Node evaluation shows double performance in comparison with UBC cache at sequential read and write test. Other results in case of read/write 50%/50% shows 13706.78 IOPS compare 2745.08 for UBC. It is five times faster than UBC cache node system. This is the proof of performance effects by L3 dedicated cache for low latency web service in comparison with unified buffer on autonomous node.Thus, the layer cache node would be utilized under many massive I/O applications by its autonomous decentralized node. Corelated P-Node and C-Node show high I/O advantage with dynamic data availability. Therefore, Autonomous multi-layer cache system architecture is the solution for interoperable communication with low latency of time web service with dynamic data availability. Our next step is variable service application level evaluation and autonomous

[1] I.-L. Yen, R.Paul and K. Mori. Towards integrated methods for high-assurance systems.

[2] K. Mori. Autonomous decentralized systems: concept, data field architecture and future

[3] H.F. Ahmad and Mori. Autonomous Information Service System: Basic Concept for

[4] Leguizamo, C.P. Kato, S. Kirai, K. Mori, K. Autonomous Decentralized Database System

[5] S. Przybylski,M. Horowitz, J. Hennessy, Characteristics of performance-optimal multi-

Evaluation, IEICE Transactions on Fundamentals of Electronics and Computer

for Assurance in Heterogeneous e-Business. Proceeding of COMPSAC, p589-p595,

level cache hierarchies, Proc of the 16th Annual International Symposium on

The total memory size is 4GB in the computer and it is assigned 3GB OS area and 1GB L3 cache. UBC utilizes full size of 4GB memory without any limitation. L3 cache policy was designed write back policy with read through. The reason of read through cache on UBC is because it is read buffer cache when read event is on the buffer space. L3 cache dedicates the write event and holds write event data for the read event. The result shows that L3 cache gives double performance than UBC buffer at sequential read and write test. Other result at read/write 50%/50% shows 13706.78 IOPS with L3 cache in comparison to 2745.08 for UBC. It is five times gain at read/write 50%/50% compare UBC cache node system. L3 cache is dedicated storage partition block cache and it manages write back policy by L3 cache and read from L3 cache. Therefore, interoperable I/O performance is very effectiveness event. This result shows the proof of performance effects by L3 cache compare unified buffer space.

(a) Read sequential

(b) Write sequential

(c) Read/write 50% / 50%

Fig. 8. L3 cache VS OS UBC cache I/O performance.
