**4.1 Introduction**

18 Video Compression

main reason for the decoder complexity, as once a parity chunk arrives at the decoder, the turbo decoding algorithm (one of the most computationally-demanding tasks (Brites et al., 2008) is called. Taking this fact into account, there are several approaches which try to reduce the complexity of the decoder, which usually induces a rate distortion penalty. However, due to technological advances, new parallel hardware is beginning to be introduced into practical video coding solutions. These new features of computers offer a new challenge to the research community with regards to integrating their algorithms into a parallel framework; this opens a new door in multimedia research. It is true that, with regards to traditional standards, several approaches have been proposed since multicores appeared on the market, but this chapter focuses on parallel computing applied to the WZ

Having said this, in 2010 several different parallel solutions for WZ were proposed. In particular, in (Oh et al., 2010) Oh et al. proposed a WZ parallel execution carried out by Graphic Processing Units (GPUs). In this proposal, the authors focus on designing a parallel distribution for a Slepian-Wolf decoder based on rate Adaptative Low Density Check Code (LDPC) with Accumulator (LDPCA). LDPC codes are composed of many bit-nodes which do not have many dependencies between each node, so they propose a parallel execution in three kernels (steps): i) kernels for check node calculations, ii) kernels for bit node calculations, and iii) kernels for termination condition calculations. In a GPU they achieve a decoding 4~5 times faster for QCIF and 15~20 for CIF. On the other hand, in (Momcilovic et al., 2010) Momcilovic et al. proposed a WZ LDPC parallel decoding based on multicore processors. In this work, the authors parallelize several LDPC approaches. On a Quad-Core machine, they achieve a speedup of about 3.5. Both approaches propose low-level

This chapter presents a WZ to H.264/AVC transcoder which includes a higher-level parallel WZ video decoding algorithm implemented on a multicore system. The reference WZ decoding algorithm is adapted to a multicore architecture, which divides each frame into several slices and distributes the work among available cores. In addition, the proposed algorithm is scalable because it does not depend on the hardware architecture, the number of cores or even on the implementation of the internal Wyner-Ziv decoder. Therefore, the time reduction can be increased simply by increasing the number of cores, as technology advances. Furthermore, the proposed method can also be applied to WZ architectures with

Nowadays, mobile-to-mobile video communications are getting more and more common. Transcoding from a low cost encoder format to a low cost decoder provides a practical solution for these types of communications. Although H.264/AVC has been included in multiple transcoding architectures from other coding formats (such as MPEG-2 to H.264/AVC (Fernandez-Escribano et al., 2007, 2008) or even homogeneous H.264/AVC (De Cock et al., 2010), proposals in WZ to H.26x to support mobile communications are rather

In 2008, the first WZ transcoder architecture was introduced by Peixoto et al. in (Peixoto et al., 2010). In this work, they presented a WZ to H.263 transcoder for mobile video

parallelism for a particular LDPC/LDPCA implementation.

or without a feedback channel (Sheng et al., 2010).

recent and there are only a few approaches so far.

**3.2 WZ to H.26x transcoding** 

framework.

The main task of a transcoder is to convert a source coding format into another one. In the case of mobile video communications, the transcoding process should be done as fast as possible. In addition, a flexible transcoder should take into account the conversion between the input and the output patterns. In order to provide a flexible and fast transcoding architecture, it is proposed the architecture displayed in Figure 3.

This architecture is composed of a Wyner-Ziv decoder and a H.264/AVC encoder with several modifications or extra modules. In particular, the WZ decoder is redesigned to parallelize the decoding process and the black modules in Figure 3 have been included or modified to obtain a faster H.264/AVC encoding. Details will be given in the following subsections.
