**Sum-Product Decoding of Punctured Convolutional Code for Wireless LAN**

Toshiyuki Shohon *Kagawa National College of Technology Japan*

#### **1. Introduction**

The next generation wireless Local Area Network (LAN) standard (IEEE802.11n) aims for high rate data transmission such as 100Mbps to 600Mbps. In order to implement that rate, high speed decoder for the convolutional code for the wireless LAN standard is necessary. From the viewpoint of high speed decoder, sum-product algorithm is an attractive decoding method, since decoding rule of sum-product algorithm is simple and sum-product algorithm is suit for parallel implementation. Furthermore, sum-product decoding is a soft-in soft-out decoding. The combined use of sum-product algorithm and another soft-in soft-out processing may provide good performance such as turbo equalization (Douillard et al., 1995; Laot et al., 2001). However, sum-product decoding for the convolutional code of the wireless LAN can not provide good performance. To improve the performance, the sum-product decoding method for the non-punctured convolutional code of the wireless LAN has been proposed (Shohon et al., 2009b; 2010). In the wireless LAN, however, punctured convolutional codes are also used. Therefore, this paper proposes sum-product decoding methods for the punctured convolutional codes of the wireless LAN.

A sum-product decoding method for convolutional codes has been introduced in (Kschischang et al., 2001). The sum-product algorithm uses a Wiberg-type graph that represents a code trellis with hidden variables as code states and visible variables as code bits. In this case, the Wiberg-type graph is equivalent to the code trellis and the sum-product algorithm becomes precisely identical to BCJR algorithm (Berrou, C. et al.;C; Kschischang et al., 2001). This method only gives interpretation of BCJR algorithm as sum-product algorithm. To avoid confusion, the method of (Kschischang et al., 2001) is referred to as BCJR. This paper deals with sum-product algorithm that uses a Tanner graph that represents a parity check matrix of the code. This sum-product algorithm is the same as that for Low-Density Parity-Check code (Gallager, 1963; MacKay, 1999). The sum-product decoding method for recursive systematic convolutional codes has been proposed in (Shohon et al., 2009a). In the wireless LAN, the non-systematic convolutional code is used. For the non-punctured convolutional code of the wireless LAN, the sum-product decoding method has been proposed in (Shohon et al., 2009b; 2010). In this paper, for punctured codes of the wireless LAN, sum-product decoding methods are proposed.

This paper is constructed as follows. In section 2, the convolutional codes used in the wireless LAN are explained. In section 3, the sum-product algorithm for convolutional codes is explained. In section 4, the sum-product decoding method for non-punctured convolutional code of the wireless LAN is explained and decoding performance of that method for punctured codes are shown. In section 5 and section 6, the sum-product decoding methods for punctured codes of the wireless LAN are proposed. In section 7, the decoding complexity is discussed.

#### **2. Convolutional code for wireless LAN**

#### **2.1 Non-punctured code**

The convolutional code for the wireless LAN is a non-systematic code with rate 1/2 (IEEE Std 802.11, 2007). Let a sequence of information bits be denoted by *x*0, *x*1, ··· , *xN*−1, a sequence of parity bits 1 be denoted by *p*1,0, *p*1,1, ··· , *p*1,*N*−1, and a sequence of parity bits 2 be denoted by *p*2,0, *p*2,1, ··· , *p*2,*N*−1. Polynomial representation for each sequence is as follows.

$$X(D) = \mathbf{x}\_0 + \mathbf{x}\_1 D + \mathbf{x}\_2 D^2 + \dots + \mathbf{x}\_{N-1} D^{N-1} \tag{1}$$

$$P\_1(D) = p\_{1,0} + p\_{1,1}D + p\_{1,2}D^2 + \dots + p\_{1,N-1}D^{N-1} \tag{2}$$

$$P\_2(D) = p\_{2,0} + p\_{2,1}D + p\_{2,2}D^2 + \dots + p\_{2,N-1}D^{N-1} \tag{3}$$

Parity bit polynomials are given by

$$P\_1(D) = G\_1(D)X(D),\tag{4}$$

$$P\_2(D) = \mathcal{G}\_2(D)X(D). \tag{5}$$

For the wireless LAN standard, *G*1(*D*) and *G*2(*D*) are given by

$$G\_1(D) = 1 + D^2 + D^3 + D^5 + D^6 \,\,\,\,\,\tag{6}$$

$$G\_{\mathcal{Z}}(D) = 1 + D + D^2 + D^3 + D^6. \tag{7}$$

Polynomials *X*(*D*), *P*1(*D*), *P*2(*D*) are also represented by *X*, *P*1, *P*<sup>2</sup> in this paper.

#### **2.2 Punctured code**

In this section, puncturing method for wireless LAN will be explained. Puncturing is a procedure for omitting some of the encoded bits in the transmitter. The effect from puncturing will reducing the number of transmitted bits and increasing the coding rate. Figure 1(a) to Fig.1(b) shows the puncturing pattern for coding rate, *r* = 2/3, 3/4.

Fig. 1. Puncturing pattern

#### **3. Sum-product algorithm for convolutional codes**

Sum-product algorithm is a message exchanging algorithm along with edge of the Tanner graph of the code. Tanner graph is a bipartite graph that represents the parity check matrix of the code. For convolutional code, it is easy to obtain tanner graph from parity check polynomial. This section explains parity check polynomial for convolutional codes, tanner graph and sum-product algorithm.

#### **3.1 Parity check polynomial of convolutional code for wireless LAN**

From Equation 4 ∼ Equation 5, we can obtain following equations.

$$G\_1(D)X + P\_1 = 0\tag{8}$$

$$G\_2(D)X + P\_2 = 0\tag{9}$$

Let left parts of Equation 8 and Equation 9 be defined as parity check polynomial.

$$H\_{\text{org},1}(X, P\_1) = G\_1(D)X + P\_1 \tag{10}$$

$$H\_{\text{org},2}(X, P\_2) = G\_2(D)X + P\_2 \tag{11}$$

A tuple of polynomials (*X*, *P*1, *P*2) is a code word if following equations are satisfied.

$$H\_{\text{org},1}(X, P\_1) = 0 \tag{12}$$

$$H\_{\text{org},2}(X, P\_2) = 0 \tag{13}$$

The degree of a parity check polynomial is denoted by *ν*, that is the maximum degree of coefficients of the polynomial. For example, since coefficients of *Horg*,1(*X*, *P*1) are {*G*1(*D*), 1}, the maximum degree is *ν* = 6 that is the maximum degree of *G*1(*D*).

#### **3.2 Tanner graph of convolutional code**

From Equation 12, parity check equations at *k* and *k* + 1 time slots are given by

$$\mathbf{C}\_{k}: \ \mathbf{x}\_{k-6} + \mathbf{x}\_{k-5} + \mathbf{x}\_{k-3} + \mathbf{x}\_{k-2} + \mathbf{x}\_{k} + p\_{1,k} = \mathbf{0},\tag{14}$$

$$\mathbb{C}\_{k+1} \text{ : } \mathbf{x}\_{k-5} + \mathbf{x}\_{k-4} + \mathbf{x}\_{k-2} + \mathbf{x}\_{k-1} + \mathbf{x}\_{k+1} + p\_{1,k+1} = \mathbf{0}.\tag{15}$$

Those equations are corresponding to check nodes *Ck* and *Ck*+1, of the tanner graph. The part of tanner graph corresponding to those parity check equations is as shown in Fig.2.

#### **3.3 Algorithm**

2 Will-be-set-by-IN-TECH

method for punctured codes are shown. In section 5 and section 6, the sum-product decoding methods for punctured codes of the wireless LAN are proposed. In section 7, the decoding

The convolutional code for the wireless LAN is a non-systematic code with rate 1/2 (IEEE Std 802.11, 2007). Let a sequence of information bits be denoted by *x*0, *x*1, ··· , *xN*−1, a sequence of parity bits 1 be denoted by *p*1,0, *p*1,1, ··· , *p*1,*N*−1, and a sequence of parity bits 2 be denoted

> *<sup>X</sup>*(*D*) =*x*<sup>0</sup> <sup>+</sup> *<sup>x</sup>*1*<sup>D</sup>* <sup>+</sup> *<sup>x</sup>*2*D*<sup>2</sup> <sup>+</sup> ··· <sup>+</sup> *xN*−1*DN*−<sup>1</sup> (1) *<sup>P</sup>*1(*D*) =*p*1,0 <sup>+</sup> *<sup>p</sup>*1,1*<sup>D</sup>* <sup>+</sup> *<sup>p</sup>*1,2*D*<sup>2</sup> <sup>+</sup> ··· <sup>+</sup> *<sup>p</sup>*1,*N*−1*DN*−<sup>1</sup> (2) *<sup>P</sup>*2(*D*) =*p*2,0 <sup>+</sup> *<sup>p</sup>*2,1*<sup>D</sup>* <sup>+</sup> *<sup>p</sup>*2,2*D*<sup>2</sup> <sup>+</sup> ··· <sup>+</sup> *<sup>p</sup>*2,*N*−1*DN*−<sup>1</sup> (3)

> > *P*1(*D*) =*G*1(*D*)*X*(*D*), (4) *P*2(*D*) =*G*2(*D*)*X*(*D*). (5)

> > > punctured bit

*G*1(*D*) =1 + *D*<sup>2</sup> + *D*<sup>3</sup> + *D*<sup>5</sup> + *D*6, (6) *G*2(*D*) =1 + *D* + *D*<sup>2</sup> + *D*<sup>3</sup> + *D*6. (7)

info bit X0

Parity 1 Parity 2

encoded data

A1

B1

B2

B2

A2

X2

A0 B0 A1

(b) Puncturing pattern for code rate 3/4

X1

B0

A0

by *p*2,0, *p*2,1, ··· , *p*2,*N*−1. Polynomial representation for each sequence is as follows.

For the wireless LAN standard, *G*1(*D*) and *G*2(*D*) are given by

Fig.1(b) shows the puncturing pattern for coding rate, *r* = 2/3, 3/4.

Polynomials *X*(*D*), *P*1(*D*), *P*2(*D*) are also represented by *X*, *P*1, *P*<sup>2</sup> in this paper.

punctured bit

In this section, puncturing method for wireless LAN will be explained. Puncturing is a procedure for omitting some of the encoded bits in the transmitter. The effect from puncturing will reducing the number of transmitted bits and increasing the coding rate. Figure 1(a) to

complexity is discussed.

**2.1 Non-punctured code**

**2. Convolutional code for wireless LAN**

Parity bit polynomials are given by

**2.2 Punctured code**

info bit X0

Parity 1 Parity 2

Fig. 1. Puncturing pattern

encoded data

A1

B1

A0 B0 A1

(a) Puncturing pattern for code rate 2/3

X1

B0

A0

For convenience, bit node is denoted by *un* such that

$$\begin{cases} u\_{3n} = \chi\_n \\ u\_{3n+1} = p\_{1,n} \\ u\_{3n+2} = p\_{2,n} \end{cases} \tag{16}$$

where information bit is *xn* and parity bits are *p*1,*n*, *p*2,*n*. Message from bit node, *un*, to check node *Cm*, is denoted by *Vm*,*n*. Message from check node, *Cm*, to bit node *un*, is denoted by *Um*,*n*. Sum-Product algorithm is described as follows.

Fig. 2. Part of Tanner graph

Step1. Initialization

Each message *Vm*,*n* is set to the initial value as follows.

$$V\_{m,n} = \lambda\_n = \frac{2r\_n}{\sigma^2} \tag{17}$$

where, *rn* denotes received signal, *σ*<sup>2</sup> denotes variance of additive white Gaussian noise and *λn* is channel value.

Step2. Message from check node to bit node

Each check node *Cm* updates the message on bit node *un* by gathering all incoming messages from other bit nodes that connected to check node *Cm*. Message *Um*,*n* is calculated by following equation (Gallager, 1963; Hagenauer, 1996; Richardson et al., 2001).

$$\mathcal{U}\_{m,n} = 2f\_s \tanh^{-1} \left\{ \prod\_{n' \in \mathcal{N}(m) \backslash n} \tanh \left( \frac{V\_{m,n'}}{2} \right) \right\} \tag{18}$$

where, N (*m*) denotes the set of bit node numbers that connect to the check node *Cm* and *fs* is a scaling factor. This factor is used in the proposed method described later. When *fs* is not specified, *fs* = 1.

Step3. Message from bit node to check node

Each bit node *n* propagates its message to all check nodes that connect to it.

$$V\_{m,n} = \lambda\_n + \sum\_{m' \in \mathcal{M}(n) \backslash m} U\_{m',n} \tag{19}$$

where M(*n*) denotes the set of check node numbers that connect to the bit node, *un*.

Step4. Tentative estimated code word computation

By summing up all the messages from all check nodes connected to a bit node, the a posteriori value Λ*n* can be obtained by

$$
\Lambda\_{\mathcal{U}} = \lambda\_{\mathcal{U}} + \sum\_{m \in \mathcal{M}(n)} \mathcal{U}\_{m,n}. \tag{20}
$$

The extrinsic value, *Le*(*un*), of bit node *un* can be obtained by

$$L\_{\mathfrak{C}}(\boldsymbol{u}\_{\mathfrak{N}}) = \sum\_{\mathfrak{m} \in \mathcal{M}(\mathfrak{n})} \mathcal{U}\_{\mathfrak{m},\mathfrak{n}}.\tag{21}$$

The tentative estimated bit *u*� *<sup>n</sup>* can be obtained by

$$\mu\_n' = \begin{cases} 0 & \text{if } \operatorname{sign}(\Lambda\_n) = +1 \\ 1 & \text{if } \operatorname{sign}(\Lambda\_n) = -1 \end{cases} \tag{22}$$

Step5. Stop criterion

4 Will-be-set-by-IN-TECH *Ck Ck*<sup>+</sup><sup>1</sup>

*xk*−<sup>6</sup> *xk*−<sup>5</sup> *xk*−<sup>4</sup> *xk*−<sup>3</sup> *xk*−<sup>2</sup> *xk*−<sup>1</sup> *xk <sup>p</sup>*1,*<sup>k</sup> xk*<sup>+</sup><sup>1</sup> *<sup>p</sup>*1,*k*+<sup>1</sup>

*Vm*,*<sup>n</sup>* <sup>=</sup> *<sup>λ</sup><sup>n</sup>* <sup>=</sup> <sup>2</sup>*rn*

where, *rn* denotes received signal, *σ*<sup>2</sup> denotes variance of additive white Gaussian noise and

Each check node *Cm* updates the message on bit node *un* by gathering all incoming messages from other bit nodes that connected to check node *Cm*. Message *Um*,*n* is calculated by

> ∏ *n*�∈N (*m*)\*n*

*m*�∈M(*n*)\*m*

where, N (*m*) denotes the set of bit node numbers that connect to the check node *Cm* and *fs* is a scaling factor. This factor is used in the proposed method described later. When *fs* is not

tanh

*Um*�

�*Vm*,*n*� 2

�⎫ ⎬ ⎭

,*<sup>n</sup>* (19)

*Um*,*n*. (20)

(18)

following equation (Gallager, 1963; Hagenauer, 1996; Richardson et al., 2001).

Each bit node *n* propagates its message to all check nodes that connect to it.

*Vm*,*<sup>n</sup>* = *λ<sup>n</sup>* + ∑

where M(*n*) denotes the set of check node numbers that connect to the bit node, *un*.

Λ*<sup>n</sup>* = *λ<sup>n</sup>* + ∑

By summing up all the messages from all check nodes connected to a bit node, the a posteriori

*m*∈M(*n*)

⎧ ⎨ ⎩

*Um*,*<sup>n</sup>* = 2 *fs* tanh <sup>−</sup><sup>1</sup>

*<sup>σ</sup>*<sup>2</sup> (17)

Fig. 2. Part of Tanner graph

Each message *Vm*,*n* is set to the initial value as follows.

Step2. Message from check node to bit node

Step3. Message from bit node to check node

Step4. Tentative estimated code word computation

Step1. Initialization

*λn* is channel value.

specified, *fs* = 1.

value Λ*n* can be obtained by

Tentative estimated code word **u**� obtained in Step 4 is checked against the parity check matrix *H*. If *H* multiplied by Tentative estimated code word **u**�*<sup>T</sup>* equal to zero vector, the decoder stop and outputs **u**� , if not, it repeats Steps 2-5.

$$H\mathbf{u}^{\prime T} = \mathbf{0} \tag{23}$$

If maximum iteration number of decoding is set, the tentative estimated code word **u**� outputs after decoding procedure repeat the process until the maximum iteration is reached.

#### **4. Sum-product decoding for wireless LAN (conventional method)**

This section will give summary of (Shohon et al., 2009b; 2010). Sum-product decoding can be performed by using Equation 10 and Equation 11 as parity check polynomials. However, the decoding provides bad performance. Since the code under consideration is a non-systematic code, there are no received signals corresponding to information bits and channel values for information bits are zero. It can be seen from Equation 10, Equation 11 that each check node has more than one information bit connections. Therefore reliability increment at check node cannot be obtained. Consequently, conventional sum-product algorithm cannot realize good performance. To improve the sum-product decoding performance, I have proposed the 2-step decoding method (Shohon et al., 2009b; 2010).

#### **4.1 2-Step decoding**

The 2-step decoding method is as follows. (1) Only parity bits are decoded by sum-product algorithm. (2) With decoded parity bits, information bits are regenerated.

#### **4.1.1 Decoding parity bits**

The parity check equation is derived from Equation 4 ∼ Equation 5 as follows.

$$G\_2(D)P\_1(D) + G\_1(D)P\_2(D) = 0\tag{24}$$

The left part of the equation is defined as parity check polynomial *H*(*P*1, *P*2).

$$H(P\_1, P\_2) = G\_2(D)P\_1 + G\_1(D)P\_2 \tag{25}$$

Parity bits *P*<sup>1</sup> and *P*<sup>2</sup> can be decoded by sum-product algorithm based on parity check polynomial given by Equation 25. By using the decoded parity bits, information bits can be regenerated.

#### **4.1.2 Decoding information bits**

Decoded information bit *X*ˆ can be obtained by Equation 26 with decoded parity bits *P*ˆ 1, *P*ˆ 2.

$$
\dot{X} = G\_{\mathbf{x},1}(D)\mathcal{P}\_1 + G\_{\mathbf{x},2}(D)\mathcal{P}\_2 \tag{26}
$$

where,

$$G\_{\chi,1}(D) = D^4 + D^2 \tag{27}$$

$$G\_{\chi,2}(D) = D^4 + D^3 + D^2 + D + 1\tag{28}$$

From Equation 26, Equation 27, and Equation 28, it can be seen that information bit can be regenerated by using a non-recursive convolutional encoder with input *P*ˆ 1, *P*ˆ <sup>2</sup> and output *X*ˆ as shown in Fig.3.

Fig. 3. Information bits regenerator

#### **4.2 Higher degree parity check polynomial**

I have proposed to use higher degree parity check polynomial to obtain further performance improvement (Shohon et al., 2009b; 2010).

The method is a sum-product decoding with higher degree parity check polynomial than that of the original parity check polynomial. In this section, the method is applied to improve the sum-product decoding performance for parity bits. The higher degree parity check polynomial is denoted by *H*� (*P*1, *P*2), that is given by

$$H'(P\_1, P\_2) = M(D)H(P\_1, P\_2) \tag{29}$$

$$=M(D)G\_2(D)P\_1 + M(D)G\_1(D)P\_2\tag{30}$$

$$=G\_2'(D)P\_1 + G\_1'(D)P\_2\tag{31}$$

where *M*(*D*) is a non-zero polynomial. Among possible higher degree parity check polynomials, we aim to select the optimum higher degree parity check polynomial by experiments and to use it for sum-product decoding. However, the number of prospective objects becomes too much when we include all possible higher degree parity check polynomials in the experimental objects. Therefore, we limit the range of degree of higher degree parity check polynomials (*ν* ≤ 16). For those higher degree parity check polynomials, we further limit the prospective objects by using *n f c*, that is the number of four-cycles per one check node (Shohon et al., 2009a). For every degree of higher degree parity check polynomial, we select the higher degree parity check polynomial that has the minimum *n f c* among higher degree parity check polynomials of object degree and include it in the experimental objects. By this means, Table 1 was obtained.

6 Will-be-set-by-IN-TECH

From Equation 26, Equation 27, and Equation 28, it can be seen that information bit can be

D D D D

D D D D

I have proposed to use higher degree parity check polynomial to obtain further performance

The method is a sum-product decoding with higher degree parity check polynomial than that of the original parity check polynomial. In this section, the method is applied to improve the sum-product decoding performance for parity bits. The higher degree parity check

(*P*1, *P*2) =*M*(*D*)*H*(*P*1, *P*2) (29)

=*M*(*D*)*G*2(*D*)*P*<sup>1</sup> + *M*(*D*)*G*1(*D*)*P*<sup>2</sup> (30)

<sup>1</sup>(*D*)*P*<sup>2</sup> (31)

(*P*1, *P*2), that is given by

<sup>2</sup>(*D*)*P*<sup>1</sup> + *G*�

where *M*(*D*) is a non-zero polynomial. Among possible higher degree parity check polynomials, we aim to select the optimum higher degree parity check polynomial by experiments and to use it for sum-product decoding. However, the number of prospective objects becomes too much when we include all possible higher degree parity check polynomials in the experimental objects. Therefore, we limit the range of degree of higher degree parity check polynomials (*ν* ≤ 16). For those higher degree parity check polynomials, we further limit the prospective objects by using *n f c*, that is the number of four-cycles per one check node (Shohon et al., 2009a). For every degree of higher degree parity check polynomial, we select the higher degree parity check polynomial that has the minimum *n f c* among higher degree parity check polynomials of object degree and include it in the experimental objects.

=*G*�

<sup>1</sup> + *Gx*,2(*D*)*P*ˆ

*Gx*,1(*D*) =*D*<sup>4</sup> + *D*<sup>2</sup> (27) *Gx*,2(*D*) =*D*<sup>4</sup> + *D*<sup>3</sup> + *D*<sup>2</sup> + *D* + 1 (28)

*X*ˆ

1, *P*ˆ 2.

<sup>2</sup> and output *X*ˆ

<sup>2</sup> (26)

1, *P*ˆ

Decoded information bit *X*ˆ can be obtained by Equation 26 with decoded parity bits *P*ˆ

*X*ˆ = *Gx*,1(*D*)*P*ˆ

regenerated by using a non-recursive convolutional encoder with input *P*ˆ

P1

P2

Fig. 3. Information bits regenerator

polynomial is denoted by *H*�

By this means, Table 1 was obtained.

**4.2 Higher degree parity check polynomial**

improvement (Shohon et al., 2009b; 2010).

*H*�

**4.1.2 Decoding information bits**

where,

as shown in Fig.3.


Table 1. Examined higher degree parity check polynomials for code rate 1/2

Experimental result shows that higher degree parity check polynomial of degree *ν* = 13 provides the best performance. The higher degree parity check polynomial is given by

$$H'(P\_1, P\_2) = G\_2'(D)P\_1 + G\_1'(D)P\_2 \tag{32}$$

$$\mathcal{G}\_1'(D) = 1 + D^3 + D^\prime + D^8 + D^{12} + D^{13} \tag{33}$$

$$\mathcal{G}\_2'(D) = 1 + D + D^9 + D^{13} \tag{34}$$

#### **4.3 Simulation results for non-punctured code**

Simulation condition is shown in Table 2. Hereafter, this condition was used, if simulation condition is not specified. Figure 4 shows simulation results. The figure shows that the performance for information bits of 2-Step Decoding with higher degree parity check polynomial (denoted by conventional) is only 0.7[dB] inferior to that of BCJR at bit error rate 10−5.


Table 2. Simulation condition

#### **4.4 Simulation results for punctured codes**

For non-punctured code, higher degree parity check polynomial with degree *ν* = 13 provides the best performance. With that higher degree parity check polynomial, for punctured codes with code rates 2/3 and 3/4, the sum-product decoding simulation were executed. The simulation results are shown in Fig.5 and Fig.6.

From Fig.5 and Fig.6, it can be seen that the conventional method, that is sum-product decoding with higher degree parity check polynomial with *ν* = 13, can not provide good performance for punctured code with code rates 2/3 and 3/4.

Fig. 4. Bit error rate performance of conventional method for code rate 1/2

Fig. 5. Bit error rate performance of conventional method for code rate 2/3

8 Will-be-set-by-IN-TECH

0 1 2 3 4 5 6

0 1 2 3 4 5 6 7

*Eb*/*N*<sup>0</sup> [dB]

BCJR

*Eb*/*N*<sup>0</sup> [dB]

BCJR

Sum-Product : Info bit Sum-Product : Parity bit

Fig. 4. Bit error rate performance of conventional method for code rate 1/2

Sum-Product : Info bit Sum-Product : Parity bit

Fig. 5. Bit error rate performance of conventional method for code rate 2/3

10-7

10-8

10-7

10-6

10-5

Bit error rate

10-4

10-3

10-2

10-1

100

10-6

10-5

10-4

Bit error rate

10-3

10-2

10-1

100

Fig. 6. Bit error rate performance of conventional method for code rate 3/4

#### **5. Single punctured bit method (Proposed decoding method (1))**

I inferred that the bad sum-product decoding performance for punctured codes is caused by more than one punctured bits included in the parity check equation at time slot *k*. The reason is as follows. Since received signals are not available for punctured bits, the channel values for punctured bits are zero. This causes that every messages from punctured bit node to check node are zero. In this case, like stopping set (Di et al., 2002), messages from the check node to bit nodes are zero. Therefore, sum-product algorithm does not work.

In order to improve the sum-product decoding performance, this paper proposes to use parity check equation that includes single punctured bit. The condition to include single punctured bit in parity check equation is referred to as single punctured bit condition. If single punctured bit is included in a parity check equation at time slot *k*, the message to the corresponding bit node can be obtained from the corresponding check node *Ck*. In this case, sum-product algorithm can work. Therefore, we expect that using higher degree parity check polynomial such that parity check equation includes single punctured bit, brings performance improvement of sum-product decoding of punctured codes.

#### **5.1 Higher degree parity check polynomial satisfying single puncture bit condition**

In this section, single punctured bit condition is derived for higher degree parity check polynomial. A higher degree parity check equation is given by

$$H'(P\_1, P\_2) = G\_2'(D)P\_1 + G\_1'(D)P\_2 \tag{35}$$

Generally, polynomials *G*� <sup>1</sup>(*D*) and *G*� <sup>2</sup>(*D*) are given by

$$G\_1'(D) = \sum\_{i=1}^{d\_1} D^{a\_i} \tag{36}$$

$$G\_2'(D) = \sum\_{i=1}^{d\_2} D^{\beta\_i} \tag{37}$$

If (*P*1, *P*2) is code word, it satisfies

$$G\_2'(D)P\_1 + G\_1'(D)P\_2 = 0\tag{38}$$

From Equation 36, Equation 37 and Equation 38, parity check equation at time slot *k* is represented by

$$\sum\_{i=1}^{d\_1} p\_{1,k-\beta\_i} + \sum\_{i=1}^{d\_2} p\_{2,k-\alpha\_i} = 0 \tag{39}$$

#### **5.1.1 Code rate 2/3**

For code rate 2/3, punctured bits are

$$\left\{ \left. p\_{2,2n+1} \right| n = 0, 1, 2, \cdots \right\} \tag{40}$$

From Equation 39 and Equation 40, it can be seen that punctured bits included in parity check equation at time slot *k* satisfies

$$p\_{2,k-n\_l} = p\_{2,2n+1} \tag{41}$$

Therefore, we obtain

$$k - \alpha\_i = 2n + 1\tag{42}$$

$$
\mathfrak{a}\_{i} = k - (2n + 1). \tag{43}
$$

For time slot *k* = 2*l*, *l* = 0, 1, 2, ··· ,

$$
\alpha\_i = 2l - (2n + 1) \tag{44}
$$

$$l = 2(l - n) - 1\tag{45}$$

Therefore, the set {*α<sup>i</sup>* | (*α<sup>i</sup>* mod 2) = 1} in higher degree parity check polynomial corresponds to punctured bits in the parity check equation at time slot *k* = 2*l*, *l* = 0, 1, 2, ··· . If Equation 46 is satisfied, the higher degree parity check polynomial satisfies single punctured bit condition at time slot *k* = 2*l*, *l* = 0, 1, 2, ··· .

$$\#\{\alpha\_i \mid (\alpha\_i \bmod 2) = 1\} = 1\tag{46}$$

where #{*x*} denotes the number of elements in the set {*x*}.

Similarly, if Equation 47 is satisfied, the higher degree parity check polynomial satisfies single punctured bit condition at time slot *k* = 2*l* + 1, *l* = 0, 1, 2, ··· .

$$\#\{\mathfrak{a}\_i \mid (\mathfrak{a}\_i \bmod 2) = 0\} = 1 \tag{47}$$

Therefore, if either Equation 46 or Equation 47 is satisfied, the higher degree parity check polynomial satisfies single punctured bit condition.

#### **5.1.2 Code rate 3/4**

10 Will-be-set-by-IN-TECH

<sup>2</sup>(*D*) are given by

*d*1 ∑ *i*=1

*d*2 ∑ *i*=1 *Dα<sup>i</sup>* (36)

*Dβ<sup>i</sup>* (37)

<sup>1</sup>(*D*)*P*<sup>2</sup> = 0 (38)

*<sup>p</sup>*2,*k*−*α<sup>i</sup>* = <sup>0</sup> (39)

*<sup>p</sup>*2,2*n*+<sup>1</sup> <sup>|</sup> *<sup>n</sup>* <sup>=</sup> 0, 1, 2, ··· (40)

*<sup>p</sup>*2,*k*−*α<sup>i</sup>* = *<sup>p</sup>*2,2*n*+<sup>1</sup> (41)

*k* − *α<sup>i</sup>* = 2*n* + 1 (42) *α<sup>i</sup>* = *k* − (2*n* + 1). (43)

*α<sup>i</sup>* = 2*l* − (2*n* + 1) (44) = 2(*l* − *n*) − 1 (45)

#{*α<sup>i</sup>* | (*α<sup>i</sup>* mod 2) = 1} = 1 (46)

#{*α<sup>i</sup>* | (*α<sup>i</sup>* mod 2) = 0} = 1 (47)

*G*� <sup>1</sup>(*D*) =

*G*� <sup>2</sup>(*D*) =

<sup>2</sup>(*D*)*P*<sup>1</sup> + *G*�

*<sup>p</sup>*1,*k*−*β<sup>i</sup>* +

From Equation 36, Equation 37 and Equation 38, parity check equation at time slot *k* is

*d*2 ∑ *i*=1

From Equation 39 and Equation 40, it can be seen that punctured bits included in parity check

Therefore, the set {*α<sup>i</sup>* | (*α<sup>i</sup>* mod 2) = 1} in higher degree parity check polynomial corresponds to punctured bits in the parity check equation at time slot *k* = 2*l*, *l* = 0, 1, 2, ··· . If Equation 46 is satisfied, the higher degree parity check polynomial satisfies single punctured bit condition

Similarly, if Equation 47 is satisfied, the higher degree parity check polynomial satisfies single

*G*�

*d*1 ∑ *i*=1

<sup>1</sup>(*D*) and *G*�

Generally, polynomials *G*�

If (*P*1, *P*2) is code word, it satisfies

For code rate 2/3, punctured bits are

equation at time slot *k* satisfies

For time slot *k* = 2*l*, *l* = 0, 1, 2, ··· ,

at time slot *k* = 2*l*, *l* = 0, 1, 2, ··· .

where #{*x*} denotes the number of elements in the set {*x*}.

punctured bit condition at time slot *k* = 2*l* + 1, *l* = 0, 1, 2, ··· .

represented by

**5.1.1 Code rate 2/3**

Therefore, we obtain

For code rate 3/4, punctured bits are

$$\begin{cases} p\_{1,3n+2} \ n = 0, 1, 2, \cdots \\ p\_{2,3n+1} \ n = 0, 1, 2, \cdots \end{cases} \tag{48}$$

From Equation 39 and Equation 48, it can be seen that punctured bits included in parity check equation at time slot *k* satisfies

$$\begin{cases} p\_{1,k-\beta\_l} = p\_{1,3n+2} \ n = 0, 1, 2, \cdots\\ p\_{2,k-a\_l} = p\_{2,3n+1} \ n = 0, 1, 2, \cdots \end{cases} \tag{49}$$

Therefore, we obtain

$$\begin{cases} k - \beta\_l = 3n + 2\\ k - \alpha\_l = 3n + 1 \end{cases} \tag{50}$$

For time slot *k* = 3*l*, *l* = 0, 1, 2, ··· ,

$$
\mathfrak{J} \cdot \mathfrak{J} - \mathfrak{J}\_i = \mathfrak{J}n + 2 \tag{51}
$$

$$\mathcal{B}\_{l} = \mathfrak{Z}(l - n) - 2 \tag{52}$$

$$\mathfrak{J}l - \mathfrak{a}\_{l} = \mathfrak{J}n + 1\tag{53}$$

$$\mathfrak{a}\_{l} = \mathfrak{Z}(l - n) - 1 \tag{54}$$

From Equation 52, it can be seen that the set {*β<sup>i</sup>* | (*β<sup>i</sup>* mod 3) = 1} in higher degree parity check polynomial corresponds to punctured bits of parity bit *P*<sup>1</sup> in the parity check equation at time slot *k* = 3*l*, *l* = 0, 1, 2, ··· . From Equation 54, it can be seen that the set {*α<sup>i</sup>* | (*α<sup>i</sup>* mod 3) = 2} in higher degree parity check polynomial correspond to punctured bits of the parity bit *P*<sup>2</sup> in the parity check equation at time slot *k* = 3*l*, *l* = 0, 1, 2, ··· .

Therefore, if either Equation 55 or Equation 56 is satisfied, the higher degree parity check polynomial satisfies single punctured bit condition at time slot *k* = 3*l*, *l* = 0, 1, 2, ··· .

$$\begin{array}{c} \left(\#\{\beta\_{\bar{i}} \mid (\beta\_{\bar{i}} \bmod 3) = 1\} = 1\right) = 1\\ \land \left(\#\{\alpha\_{\bar{i}} \mid (\alpha\_{\bar{i}} \bmod 3) = 2\} = 0\right) \end{array} \tag{55}$$

$$\begin{array}{l} \left(\#\{\beta\_{\bar{l}} \mid (\beta\_{\bar{l}} \bmod 3) = 1\} = 0\right) \\ \land \left(\#\{\alpha\_{\bar{l}} \mid (\alpha\_{\bar{l}} \bmod 3) = 2\} = 1\right) \end{array} \tag{56}$$

Similarly, if either Equation 57 or Equation 58 is satisfied, the higher degree parity check polynomial satisfies single punctured bit condition at time slot *k* = 3*l* + 1, (*l* = 0, 1, 2, ···).

$$\begin{array}{c} \left(\#\{\beta\_{\bar{i}} \mid (\beta\_{\bar{i}} \bmod 3) = 2\} = 1\right) \\ \land \left(\#\{\alpha\_{\bar{i}} \mid (\alpha\_{\bar{i}} \bmod 3) = 0\} = 0\right) \end{array} \tag{57}$$

$$\begin{array}{c} \left(\#\{\beta\_{i} \mid (\beta\_{i} \bmod 3) = 2\} = 0\right) \\ \land \left(\#\{\alpha\_{i} \mid (\alpha\_{i} \bmod 3) = 0\} = 1\right) \end{array} \tag{58}$$

Similarly, if either Equation 59 or Equation 60 is satisfied, the higher degree parity check polynomial satisfies single punctured bit condition at time slot *k* = 3*l* + 2, (*l* = 0, 1, 2, ···).

$$\begin{array}{c} \left(\#\{\beta\_{i} \mid (\beta\_{i} \bmod 3) = 0\} = 1\right) \\ \land \left(\#\{\alpha\_{i} \mid (\alpha\_{i} \bmod 3) = 1\} = 0\right) \end{array} \tag{59}$$

$$\begin{array}{l} \left(\#\{\beta\_{i} \mid (\beta\_{i} \bmod 3) = 0\} = 0\right) \\ \land \left(\#\{\alpha\_{i} \mid (\alpha\_{i} \bmod 3) = 1\} = 1\right) \end{array} \tag{60}$$

#### **5.2 Search of higher degree parity check polynomial for decoding**

In this paper, basically, the higher degree parity check polynomials for decoding are searched as follows.


#### **5.2.1 Code rate 2/3**

In the Step.1, 208 higher degree parity check polynomials satisfy single punctured bit condition. Since many higher degree parity check polynomials are selected, they are limited by *n f c*. In this paper, among those higher degree parity check polynomials, 9 higher degree parity check polynomials with lower *n f c* are selected. They are shown in Table 3.


Table 3. Examined higher degree parity check polynomials for code rate 2/3

The simulation results of Step.2 with higher degree parity check polynomials in Table 3 are shown in Fig. 7. Simulation condition is shown in Table 2 and *Eb*/*N*<sup>0</sup> = 5.0 [dB]. From Fig. 7, it can be seen that higher degree parity check polynomial of No.5 with scaling factor *fs* = 0.9 provides the best performance.

Fig. 7. Simulation results of Step.2 for code rate 2/3 at *Eb*/*N*<sup>0</sup> =5[dB]

#### **5.2.2 Code rate 3/4**

5.2.2.1 Step.1

12 Will-be-set-by-IN-TECH

Similarly, if either Equation 59 or Equation 60 is satisfied, the higher degree parity check polynomial satisfies single punctured bit condition at time slot *k* = 3*l* + 2, (*l* = 0, 1, 2, ···).

∧(#{*α<sup>i</sup>* | (*α<sup>i</sup>* mod 3) = 0} = 1) (58)

∧(#{*α<sup>i</sup>* | (*α<sup>i</sup>* mod 3) = 1} = 0) (59)

∧(#{*α<sup>i</sup>* | (*α<sup>i</sup>* mod 3) = 1} = 1) (60)

(#{*β<sup>i</sup>* | (*β<sup>i</sup>* mod 3) = 2} = 0)

(#{*β<sup>i</sup>* | (*β<sup>i</sup>* mod 3) = 0} = 1)

(#{*β<sup>i</sup>* | (*β<sup>i</sup>* mod 3) = 0} = 0)

In this paper, basically, the higher degree parity check polynomials for decoding are searched

Step.1 Select higher degree parity check polynomials with degree *ν* ≤ 21 that satisfies single

Step.2 Among those higher degree parity check polynomials, select the higher degree parity check polynomial that provides the best sum-product decoding performance by using

In the Step.1, 208 higher degree parity check polynomials satisfy single punctured bit condition. Since many higher degree parity check polynomials are selected, they are limited by *n f c*. In this paper, among those higher degree parity check polynomials, 9 higher degree

The simulation results of Step.2 with higher degree parity check polynomials in Table 3 are shown in Fig. 7. Simulation condition is shown in Table 2 and *Eb*/*N*<sup>0</sup> = 5.0 [dB]. From Fig. 7, it can be seen that higher degree parity check polynomial of No.5 with scaling factor *fs* = 0.9

<sup>2</sup>(*oct*) *G*�

<sup>1</sup>(*oct*)

parity check polynomials with lower *n f c* are selected. They are shown in Table 3.

No. *ν n f c G*�

Table 3. Examined higher degree parity check polynomials for code rate 2/3

**5.2 Search of higher degree parity check polynomial for decoding**

as follows.

punctured bit condition.

computer simulation.

provides the best performance.

**5.2.1 Code rate 2/3**

For code rate 3/4, there are both puncture bits of parity *P*<sup>1</sup> and parity *P*2. Decodable punctured parity bit by sum-product algorithm with certain parity check equation is either parity *P*<sup>1</sup> or parity bit *P*2. From the viewpoint of decodable parity bit, single punctured bit condition can be arranged as follows.


Therefore, for code rate 3/4, both higher degree parity check polynomials for *P*<sup>1</sup> and *P*<sup>2</sup> are necessary to decode.

For code rate 3/4, there are 16 higher degree parity check polynomials for *P*<sup>1</sup> and 16 higher degree parity check polynomials for *P*2. The number of combination of higher degree parity check polynomial for *P*<sup>1</sup> and that for *P*<sup>2</sup> is many. Therefore, they are limited by *n f c*. Higher degree parity check polynomials that have lower *n f c* are selected as shown in Table 4 and Table 5.


Table 4. Examined higher degree parity check polynomials for *P*<sup>1</sup>


Table 5. Examined higher degree parity check polynomials for *P*<sup>2</sup>

#### 5.2.2.2 Step.2

A block diagram of the decoder for code rate 3/4 is shown in Fig. 8. It is similar to a turbo decoder. In Fig.8, DEC1 is sum-product algorithm decoder with higher degree parity check polynomial for *P*<sup>1</sup> and DEC2 is sum-product algorithm decoder with higher degree parity check polynomial for *P*2. Channel value is denoted by *λn*. Extrinsic values of DEC1 and DEC2 are denoted by *Le*1(*un*) and *Le*2(*un*), respectively. A posteriori value of DEC2 is denoted by Λ2,*n*.

In DEC1, *Le*2(*un*) is added to *λ<sup>n</sup>* as follows.

$$
\lambda\_n' = \lambda\_n + L\_{\text{e2}}(\mu\_n) \tag{61}
$$

The value *λ <sup>n</sup>* is used as initial value of *λ<sup>n</sup>* in Equation 17.

Similarly, in DEC2, *Le*1(*un*) is added to *λ<sup>n</sup>* and that value is used as initial value of *λn*. In computer simulation, the number of iteration of sum-product algorithm at each decoder was set to 1. The maximum number of iteration between two decoders was set to 200. Other simulation conditions are the same as shown in Table 2.

Fig. 8. Block diagram of decoder of single punctured bit method for code rate 3/4

Figure 9 shows the simulation results of Step.2 for code rate 3/4 at *Eb*/*N*<sup>0</sup> = 6[dB].

From Fig.9, it can be seen that the combination of higher degree parity check polynomials No.2 and No.3 with scaling factor *fs* = 0.5 provides the best decoding performance.

Fig. 9. Simulation results of Step.2 for code rate 3/4 at *Eb*/*N*<sup>0</sup> = 6[dB]

#### **5.3 Simulation results**

#### **5.3.1 Code rate 2/3**

14 Will-be-set-by-IN-TECH

1 12 30 14453 12121 2 21 64 17010055 10212103

3 7 24 321 267 4 12 29 11055 15103 5 21 38 10540055 14222103

A block diagram of the decoder for code rate 3/4 is shown in Fig. 8. It is similar to a turbo decoder. In Fig.8, DEC1 is sum-product algorithm decoder with higher degree parity check polynomial for *P*<sup>1</sup> and DEC2 is sum-product algorithm decoder with higher degree parity check polynomial for *P*2. Channel value is denoted by *λn*. Extrinsic values of DEC1 and DEC2 are denoted by *Le*1(*un*) and *Le*2(*un*), respectively. A posteriori value of DEC2 is denoted by

Similarly, in DEC2, *Le*1(*un*) is added to *λ<sup>n</sup>* and that value is used as initial value of *λn*. In computer simulation, the number of iteration of sum-product algorithm at each decoder was set to 1. The maximum number of iteration between two decoders was set to 200. Other

Λ2,*<sup>n</sup> λ<sup>n</sup>*

Fig. 8. Block diagram of decoder of single punctured bit method for code rate 3/4

Figure 9 shows the simulation results of Step.2 for code rate 3/4 at *Eb*/*N*<sup>0</sup> = 6[dB].

No.2 and No.3 with scaling factor *fs* = 0.5 provides the best decoding performance.

From Fig.9, it can be seen that the combination of higher degree parity check polynomials

DEC1 DEC2

<sup>2</sup>(*oct*) *G*

<sup>2</sup>(*oct*) *G*

<sup>1</sup>(*oct*)

<sup>1</sup>(*oct*)

*<sup>n</sup>* =*λ<sup>n</sup>* + *Le*2(*un*) (61)

*Le*1(*un*) *Le*2(*un*)

No. *ν n f c G*

No. *ν n f c G*

*λ*

*<sup>n</sup>* is used as initial value of *λ<sup>n</sup>* in Equation 17.

simulation conditions are the same as shown in Table 2.

Table 4. Examined higher degree parity check polynomials for *P*<sup>1</sup>

Table 5. Examined higher degree parity check polynomials for *P*<sup>2</sup>

In DEC1, *Le*2(*un*) is added to *λ<sup>n</sup>* as follows.

5.2.2.2 Step.2

Λ2,*n*.

The value *λ*

Figure 10 shows bit error rate performance of the single punctured bit method for code rate 2/3.

Fig. 10. BER performance of single punctured bit method for code rate 2/3

From Fig.10 it can be seen that the parity bit error rate performance of the single punctured bit method is 1.12[dB] superior to that of the conventional method (higher degree parity check polynomial of *ν* = 13) at bit error rate 10−5. The parity bit error rate performance of the single punctured bit method is only 0.83[dB] inferior to that of BCJR.

From Fig.10, information bit error performance of the single punctured bit method is 1.28[dB] superior to that of the conventional method at bit error rate 10−5. The information bit error rate performance of the single punctured bit method is only 0.98 [dB] inferior to that of BCJR.

#### **5.3.2 Code rate 3/4**

Fig. 11. Parity bit error rate performance of single punctured bit method for code rate 3/4

Figure 11 shows parity bit error rate performance of the single punctured bit method for code rate 3/4. From Fig.11 it can be seen that the parity bit error rate performance of the single punctured bit method is 0.82[dB] superior to that of the conventional method (higher degree parity check polynomial of *ν* = 13) at bit error rate 10−5. The parity bit error rate performance of the single punctured bit method is 3.24[dB] inferior to that of BCJR.

Figure 12 shows information bit error rate performance of the single punctured bit method. From Fig.12, it can be seen that the information bit error rate performance of the single punctured bit method is 1.11[dB] superior to the conventional method at bit error rate 10−5. The information bit error rate performance of the single punctured bit method is 4.11[dB] inferior to that of BCJR at bit error rate 10−5.

#### **6. Switching parity check method (proposed decoding method (2))**

For code rate 3/4, the proposed method (1) can not provide good performance. Therefore, this paper try to improve the sum-product decoding performance for code rate 3/4.

16 Will-be-set-by-IN-TECH

From Fig.10 it can be seen that the parity bit error rate performance of the single punctured bit method is 1.12[dB] superior to that of the conventional method (higher degree parity check polynomial of *ν* = 13) at bit error rate 10−5. The parity bit error rate performance of the single

From Fig.10, information bit error performance of the single punctured bit method is 1.28[dB] superior to that of the conventional method at bit error rate 10−5. The information bit error rate performance of the single punctured bit method is only 0.98 [dB] inferior to that of BCJR.

0 1 2 3 4 5 6 7 8 9 10 11

Fig. 11. Parity bit error rate performance of single punctured bit method for code rate 3/4 Figure 11 shows parity bit error rate performance of the single punctured bit method for code rate 3/4. From Fig.11 it can be seen that the parity bit error rate performance of the single punctured bit method is 0.82[dB] superior to that of the conventional method (higher degree parity check polynomial of *ν* = 13) at bit error rate 10−5. The parity bit error rate performance

Figure 12 shows information bit error rate performance of the single punctured bit method. From Fig.12, it can be seen that the information bit error rate performance of the single punctured bit method is 1.11[dB] superior to the conventional method at bit error rate 10−5. The information bit error rate performance of the single punctured bit method is 4.11[dB]

For code rate 3/4, the proposed method (1) can not provide good performance. Therefore,

this paper try to improve the sum-product decoding performance for code rate 3/4.

*Eb*/*N*0[dB]

punctured bit method is only 0.83[dB] inferior to that of BCJR.

Conventional

BCJR

of the single punctured bit method is 3.24[dB] inferior to that of BCJR.

**6. Switching parity check method (proposed decoding method (2))**

Single punctured bit

inferior to that of BCJR at bit error rate 10−5.

**5.3.2 Code rate 3/4**

10-6

10-5

10-4

Parity bit error rate

10-3

10-2

10-1

100

Fig. 12. Information bit error rate performance of single punctured bit method for code rate 3/4

I inferred that the bad decoding performance is caused by the four-cycles of higher degree parity check polynomial, since *n f c* of higher degree parity check polynomial satisfying single punctured bit condition tends to be larger than *n f c* of higher degree parity check polynomial that does not satisfy single punctured bit condition. Therefore, this paper proposes following method. Only at first iteration, the higher degree parity check polynomial satisfying single punctured bit condition is used to decode and after first iteration, another higher degree parity check polynomial without single punctured bit condition is used to decode. By decoding, only at first iteration, with higher degree parity check polynomial satisfying single punctured bit condition, the a posteriori values of punctured bits are obtained. After obtaining the a posteriori values of punctured bit, the higher degree parity check polynomial with lower *n f c* may provide good bit error rate performance.

Figure 13 shows a block diagram of decoder of the switching parity check method. In Fig. 13, DEC1 is a sum-product algorithm decoder with higher degree parity check polynomial for *P*1, DEC2 is a sum-product algorithm decoder with higher degree parity check polynomial for *P*<sup>2</sup> and DEC3 is a sum-product algorithm decoder with higher degree parity check polynomial with lower *n f c* for iteration. Chanel values for DEC1, DEC2 and DEC3 are *λ*1,*n*, *λ*2,*<sup>n</sup>* and *λ*3,*n*, respectively. A posteriori values of DEC1, DEC2 and DEC3 are Λ1,*n*, Λ2,*<sup>n</sup>* and Λ3,*n*, respectively. Decoders DEC2 and DEC3 use the a posteriori value of previous decoder as the channel value.

#### **6.1 Search of higher degree parity check polynomial for decoding**

This paper searches higher degree parity check polynomials for DEC1, DEC2 and DEC3 by computer simulation.

Fig. 13. Block diagram of decoder of switching parity check method for code rate 3/4

In this paper, the higher degree parity check polynomials for DEC1, DEC2 and DEC3 were selected from Table 4, Table 5 and Table 1, respectively. There are many number of combination of the higher degree parity check polynomials. Therefore, this paper searches the higher degree parity check polynomials as follows.


Figure 14 shows the simulation results of Step.1 at *Eb*/*N*<sup>0</sup> = 6[dB]. From Fig.14, it can be seen that the higher degree parity check polynomial with *ν* = 15 provides the best performance. Therefore, that higher degree parity check polynomial is used.

Figure 15 shows the simulation results of Step.2 at *Eb*/*N*0=7[dB]. From Fig.15, it can be seen that the combination of higher degree parity check polynomials No.2 and No.5 with scaling factor *fs* = 0.1 provides the best performance, where scaling factor *fs* = 0.1 is used for DEC1 and DEC2, and DEC3 uses fixed scaling factor *fs* = 1.

Fig. 14. Simulation results of step.1 in switching parity check method at *Eb*/*N*<sup>0</sup> = 6[dB]

Fig. 15. Simulation results of step.2 in switching parity check method at *Eb*/*N*<sup>0</sup> = 7[dB]

#### **6.2 Simulation results**

18 Will-be-set-by-IN-TECH

*<sup>λ</sup>*1,*<sup>n</sup>* DEC1 <sup>Λ</sup>1,*<sup>n</sup> <sup>λ</sup>*2,*<sup>n</sup>* DEC2 <sup>Λ</sup>2,*<sup>n</sup> <sup>λ</sup>*3,*<sup>n</sup>* DEC3 <sup>Λ</sup>3,*<sup>n</sup>*

In this paper, the higher degree parity check polynomials for DEC1, DEC2 and DEC3 were selected from Table 4, Table 5 and Table 1, respectively. There are many number of combination of the higher degree parity check polynomials. Therefore, this paper searches

Step.1 At first, the higher degree parity check polynomial for DEC3 is determined by

Step.2 With the determined higher degree parity check polynomial for DEC3, the higher degree parity check polynomials for DEC1 and DEC2 are determined by decoding

Figure 14 shows the simulation results of Step.1 at *Eb*/*N*<sup>0</sup> = 6[dB]. From Fig.14, it can be seen that the higher degree parity check polynomial with *ν* = 15 provides the best performance.

Figure 15 shows the simulation results of Step.2 at *Eb*/*N*0=7[dB]. From Fig.15, it can be seen that the combination of higher degree parity check polynomials No.2 and No.5 with scaling factor *fs* = 0.1 provides the best performance, where scaling factor *fs* = 0.1 is used for DEC1

6 7 8 9 10 11 12 13 14 15 16

Fig. 14. Simulation results of step.1 in switching parity check method at *Eb*/*N*<sup>0</sup> = 6[dB]

Degree of Higher Degree Parity Check Polynomial *ν*

Fig. 13. Block diagram of decoder of switching parity check method for code rate 3/4

the higher degree parity check polynomials as follows.

Therefore, that higher degree parity check polynomial is used.

and DEC2, and DEC3 uses fixed scaling factor *fs* = 1.

10-5

10-4

10-3

Parity Bit Error Rate

10-2

10-1

100

decoding simulation with only DEC3.

simulation with DEC1, DEC2 and DEC3.

1st Iteration After 1st iteration

Simulation results are shown in Fig.16 and 17. Figure 16 shows parity bit error rate performance. From Fig.16, it can be seen that parity bit error rate performance of the switching parity check method is 3.02[dB] superior to that of the conventional method and 2.2[dB] superior to that of the single punctured bit method. Parity bit error rate performance of the switching parity check method is only 1.04[dB] inferior to that of BCJR.

Figure 17 shows information bit error rate performance. From Fig.17, it can be seen that information bit error rate performance of the switching parity check method is 4.16[dB] superior to that of the conventional method and 3.05[dB] superior to that of the single punctured bit method. Information bit error rate performance of the switching parity check method is only 1.06 [dB] inferior to that of BCJR.

#### **7. Decoding complexity**

Table 6 and Table 7 show the numbers of operations per one bit decoding for sum-product algorithm and BCJR, respectively. In both tables, *Nadd* denotes the number of additions, *Nmult* denotes the number of multiplications and *Ntotal* denotes the total number of operations. For sum-product algorithm, *Nsp* denotes the number of operations for tanh(·), tanh−1(·). For BCJR, *Nsp* denotes the number of operations for exp(·), log(·). In Table 6, for information bits, *Nadd* shows the number of XOR's. In Table 6, *Nitr* denotes the average number of iterations, where the number was counted at *Eb*/*N*0=6[dB] by using computer simulation. For code rate 2/3, complexity of the single punctured bit method is shown. For code rate 3/4, complexity of the switching parity check method is shown. It is necessary to notice that iteration of sum-product algorithm is required for parity bits decoding only. For the switching parity

Fig. 16. Parity Bit Error Rate Performance of switching parity check method

Fig. 17. Information Bit Error Rate Performance of switching parity check method

check method, it is necessary to notice that higher degree parity check polynomials No.2 and No.5 are used at only first iteration and after first iteration, higher degree parity check polynomials with degree *ν* = 15 is used.

From those tables, for code rate 2/3, it can be seen that the number of operations of the single punctured bit method is 0.1 times of that of BCJR. For code rate 3/4, the number of operations of the switching parity check method is 0.2 times of that of BCJR.

For the both code rates, it can be seen that the number of operations of the proposed method is much less than that of BCJR.


Table 6. Complexity of sum-product algorithm


Table 7. Complexity of BCJR

#### **8. Conclusion**

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Switching parity check

Switching parity check

Conventional Single punctured bit

BCJR

Conventional Single punctured bit

BCJR

0 1 2 3 4 5 6 7 8 9 10 11

0 1 2 3 4 5 6 7 8 9 10 11

*Eb*/*N*0[dB]

Fig. 17. Information Bit Error Rate Performance of switching parity check method

*Eb*/*N*0[dB]

Fig. 16. Parity Bit Error Rate Performance of switching parity check method

10-6

10-6

10-5

10-4

Information

 Bit Error Rate

10-3

10-2

10-1

100

10-5

10-4

Parity Bit Error Rate

10-3

10-2

10-1

100

This paper proposes sum-product decoding methods for the punctured convolutional codes of wireless LAN. The wireless LAN standard include the punctured convolutional codes with code rate 2/3 and 3/4. This paper proposes to decode with the higher degree parity check polynomial that satisfies single punctured bit condition as the single punctured bit method. Single punctured bit condition is the condition to include single punctured bit in parity check equation. For code rate 2/3, the performance of the single punctured bit method is 1.28[dB] superior to that of the conventional method and only 0.98[dB] inferior to that of BCJR at bit error rate 10−5. For code rate 3/4, the single punctured bit method can not provide good performance. To improve the performance, this paper proposes following method as the switching parity check method. Only at first iteration, the higher degree parity check polynomial satisfying single punctured bit condition is used to decode and after first iteration, another higher degree parity check polynomial with lower *n f c* without single punctured bit condition is used to decode. For code rate 3/4, the performance of the switching parity check method is 4.16[dB] superior to that of the conventional method, 3.05[dB] superior to that of the single punctured bit method and only 1.06[dB] inferior to that of BCJR. Complexity of the single punctured bit method is 0.1 times of that of BCJR for code rate 2/3. For code rate 3/4, complexity of the switching parity check method is 0.2 times of that of BCJR. For the both code rates, complexity of the proposed method is much less than that of BCJR.

#### **9. Acknowledgment**

This work was supported by Japan Society for the Promotion of Science (JSPS) Grant-in-Aid for Scientific Research (C) 23560444.

#### **10. References**

