Fig. 10. Circuit schematic of DC/AC inverter

The PWM pulses which are generated by a microcontroller are fed into the gates of a full bridge inverter. Programming the microcontroller allows the transistors Q1 and Q4 to be on while Q2 and Q3 to be off and vice versa. Due to the limited response time and delay time of the transistors, two switches in one leg may be switched on at the same time then shoot through will occur and the switches may be damaged due to high short circuit current then the dead time is introduced in order to avoid the occurrence of the short circuit.

Figure 11 shows the ideal switching patterns and the drive signals containing the dead time for the inverter leg. The Sp and Sn are the ideal switching pattern of the positive device and the negative device of the full bridge DC/AC inverter, respectively. As mentioned before, the short time delay is used to avoid shoot-through, where the actual gate drive signals must be delayed by the dead time. The gate drive signals containing the dead time are denoted as Spd and Snd since the gate drive signals are shifted from the center of the sampling interval by the dead time. The generated phase voltage is also shifted as much as the delay time. It had been reported that the generated voltage pulses residing in the middle of the sampling interval contain the least amount of harmonics (Choi et al., 1999). Although the produced voltage pulses resulting from each of the gate drive signals during the sampling intervals are not much affected, the resultant voltage during an entire cycle is significantly reduced due to the dead time. In addition, those cumulated delays may distort the output waveform of the inverter.

In fact, the addition of the dead time can improve the performance of inverter power supply by preventing the short circuit current. However, the instability and harmonic distortion problem can be arising due to the incorrect selection of the sufficient dead time value.

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Motor Management Timer (MMT) can output 6-phase PWM waveforms with non-overlap times. Figure 13 shows a block diagram of the MMT. In the inverter power supply application, the MMT unit is used to control the switching devices in the DC/DC stage by

Fig. 12. Block diagram of SH microprocessor

**6.3.1 Motor Management Timer (MMT)** 

generating the PWM signal.

Fig. 11. Gate drive signals of the PWM inverters
