**6.3.1 Motor Management Timer (MMT)**

Motor Management Timer (MMT) can output 6-phase PWM waveforms with non-overlap times. Figure 13 shows a block diagram of the MMT. In the inverter power supply application, the MMT unit is used to control the switching devices in the DC/DC stage by generating the PWM signal.

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Figure 14 illustrates an example of the PWM pulse which is generated from the MMT unit. In this figure the PWM output waveform is generated by comparing the values in the Timer counter (TCNT) and the Timer general register (TGR) resulting in the compare output waveform. Then the dead time generation process is started using the TDCNT0 and TDCNT1 registers. The output generation wave form is generated by finally adding the compare output waveforms with the dead time signal. The PWM waveform is generated by converting the output generation waveform to the output PWM pins. In the operating modes, PWM waveforms with any duty cycle from 0% to 100% can be

PUOA Output PWMU phase output (positive phase) PUOB Output PWMU phase output (negative phase) PVOA Output PWMV phase output (positive phase) PVOB Output PWMV phase output (negative phase) PWOA Output PWMW phase output (positive phase) PWOB Output PWMW phase output (negative phase)

Fig. 14. Example of PWM waveform generation from MMT unit

Counter clear signal input when set as an input by PAIORL register: toggle output in synchronization with the PWM

cycle when set as output by PAIORL register.

Name I/O Function

Table 1. The pin configuration of the MMT

PCIO Input/Output

generated.

Fig. 13. Block diagram of MMT

Pin Configuration of the MMT unit is described in Table 1, as shown in Table 1, the PUOA, PUOB, PVOA, PVOB, PWOA, and PWOB pins are PWM output pins (Sh-2Sh7047 Group Hardware Manual).


Table 1. The pin configuration of the MMT

340 Grid Computing – Technology and Applications, Widespread Coverage and New Horizons

Pin Configuration of the MMT unit is described in Table 1, as shown in Table 1, the PUOA, PUOB, PVOA, PVOB, PWOA, and PWOB pins are PWM output pins (Sh-2Sh7047 Group

Fig. 13. Block diagram of MMT

Hardware Manual).

Figure 14 illustrates an example of the PWM pulse which is generated from the MMT unit. In this figure the PWM output waveform is generated by comparing the values in the Timer counter (TCNT) and the Timer general register (TGR) resulting in the compare output waveform. Then the dead time generation process is started using the TDCNT0 and TDCNT1 registers. The output generation wave form is generated by finally adding the compare output waveforms with the dead time signal. The PWM waveform is generated by converting the output generation waveform to the output PWM pins. In the operating modes, PWM waveforms with any duty cycle from 0% to 100% can be generated.

Fig. 14. Example of PWM waveform generation from MMT unit

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In PWM mode, PWM waveforms can be generated from the output pins. The output level can be selected and TGR registers settings can be used to output a PWM waveform in the range of 0% to 100% duty. All channels can be independently designated for PWM mode

There are two PWM modes: in PWM mode 1, PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and TGRC with TGRD. In PWM mode 2, PWM output is generated using one TGR as the cycle register and the others as duty registers. The output specified in TIOR is performed by means of compare matches. Upon counter clearing by a synchronization register compare match, the output value of each pin is the initial value set in TIOR. If the set values of the cycle and duty registers are identical,

This chapter proposes an entire virtual environment for the inverter power supply design to optimize and test the embedded software parameters. This environment is based on the Model Based Design method. The MATLAB and Simulink (MathWorks web site) environment is used for building such a virtual system which is divided in two main parts, the analog part (controlled part) and the digital (control) part which are described as follows. The analog part consists of electrical circuits of DC/DC converter and DC/AC inverter. The second part is the digital part (controller part) consisting of the microcontroller and the embedded software. The embedded software has two tasks which are the generation of the pulses to control the operations of the electrical circuits and to implement the control algorithm that is necessary for regulating the output voltage against any disturbance. The entire virtual environment of the

The topology of the inverter power supply is DC-DC-AC. MILS of the inverter process is done in two stages. The first stage is the DC/DC converter and in this stage, the input DC voltage is converted to higher level DC output. This new DC output acts as an input of the second stage which is the DC/AC inverter. SH 7047 was used as a digital controller to control the generation of the PWM pulses and control the inverter power supply operation. Both the DC/DC and DC/AC stages are controlled individually, as shown in Figure 16.

The hardware parts of the electric circuits are modelled using Simulink power block set. The power block set consists of the power electronic elements. Each element in this block set has its own block window which allows for the selection for the key parameters. At the bottom of the block parameter window is a pull down menu, which allows for the key voltage and current to be easily measured. In the first stage, the electrical circuit was modeled in an open loop system to determine the performance of each circuit separately. The PWM generation block was modeled for both DC/DC converter stage and DC/AC inverter stage. For example, the PWM model in the MTU microprocessor unit is illustrated in Figure 17. The PWM block compares both the sin wave signal with the required output frequency and the sawtooth signal with the carrier frequency equal to 10 kHz. Then the dead time is generated using the delay block and finally, the PWM pulse is generated and fed into the gates of the

(Sh-2Sh7047 Group Hardware Manual).

**7. Model in the Loop Simulation (MILS)** 

inverter power supply is described below.

**7.1 DC/DC and DC/AC circuit simulation** 

full bridge transistors.

the output value does not change when a compare match occurs.
