**3.3 Floor planning and design at layout level**

The main structural component in the sorting network which is exposed in section 3.1, is a three-data comparator. As shown in Fig. 14, this element can be constituted by a set of interconnected one-bit CS cells. Three 8-bit word-length inputs described as: A, B and C can be identified. Also, three 8-bit CS blocks make possible to collect the median datum in the middle bus denoted by MED(A,B,C), and the corresponding minimum and maximum data into the external buses described as MIN(A,B,C) and MAX(A,B,C). In order to minimize the layout area, the CS modules have been rotated and placed in the position as illustrates the floorplanning and layout of Fig. 16.

Fig. 16. Floorplanning (on left) and layout (on right) for the 8-bit three-data comparator included in the median filter

VLSI Design of Sorting Networks in CMOS Technology 105

Fig. 18. Layout for the nine-data sorting network in the median filter design

**3.4 Spice simulations for delay time estimation and electrical verification** 

D8=00001111(24010), and D9=00010101 (16810).

The netlist including parasitic capacitances from the layout of Fig.18 is simulated to verify the circuit operation. The voltage waveforms for the median datum are shown in Fig. 19. The signals S0, S1, ..., and S7, correspond to the 8-bits median datum of the set of inputs {D0, D1, ..., D9} given by: D1=00101011 (21210), D2=01000011(19410), D3=00100010 (6910), D4=00001101 (17610), D5=00011100 (5610), D6=00011110 (12010), D7=00010111 (23210),

In this simulation, the median for the input described in base-10 { 21210, 19410, 6910, 17610, 5610, 12010, 23210, 24010, 16810 } is the datum 17610 ,which in a binary base is represented as

A graphical description, about the size and placement of the three-data modules that constitutes the nine-data sorting network is presented in Fig. 17. This floorplanning shows the connectivity between every module without showing internal layout details. It can be observed that some modules should be flipped to improve the routing and also achieving an area minimization. In this layout, two blocks can be recognized: the nine-data serialin/parallel-out register and the nine-data sorting network. In accordance to the proposed median filter algorithm the unique signal of interest from the sorting network output is the median datum (D4) while the other data (D1,D2,D3,D5,D6,D7, and D8) are discarded.

Fig. 17. Floorplanning for the nine-data sorting network in the median filter design Figure 18 shows the translation to a layout level of the floorplanning design of fig. 17.

A graphical description, about the size and placement of the three-data modules that constitutes the nine-data sorting network is presented in Fig. 17. This floorplanning shows the connectivity between every module without showing internal layout details. It can be observed that some modules should be flipped to improve the routing and also achieving an area minimization. In this layout, two blocks can be recognized: the nine-data serialin/parallel-out register and the nine-data sorting network. In accordance to the proposed median filter algorithm the unique signal of interest from the sorting network output is the median datum (D4) while the other data (D1,D2,D3,D5,D6,D7, and D8) are discarded.

Fig. 17. Floorplanning for the nine-data sorting network in the median filter design

Figure 18 shows the translation to a layout level of the floorplanning design of fig. 17.

Fig. 18. Layout for the nine-data sorting network in the median filter design
