**1. Introduction**

16 VLSI Design

This research was sponsored in part by the 2007 Wertheim Fellowship, US Naval

De Zuane, Handbook of Drinking Water Quality, Standards and Control,Van Nostrand

Ellis, A. M., Electronic and Photoelectron Spectroscopy: Fundamentals and Case Studies,

Herwaarden, A. W. Van, P. M. Sarro, J. W. Gardner, and P. Bataillard, "Liquid and Gas

Hsu, T. R., MEMS and Microsystems: Design, manufacture, and Nanoscale Engineering,

Moskowitz, M., L. Sellami, R. Newcomb, and V. Rodellar, "Current Mode Realization of

Patterson, J. D., "Micro-Mechanical Voltage Tunable Fabry-Perot Filters Formed in (111)

Svanberg, S., Atomic and Molecular Spectroscopy: Basic Aspects and Practical Applications,

Turner, A. P. F., I. Karube, and G. S. Wilson, Editors, Biosensors, Fundamentals and

Tyree, V., J.-I. Pi, C. Pina, W. Hansford, J. Marshall, M. Gaitan, M. Zaghloul, and D.

Van der Schoot and P. Berveld, "Use of Immobilized Enzymes in FET-Detectors," in

Novotny, "Realizing Suspended Structures on Chips Manufactured by CMOS Foundry Processes through the MOSIS Service," MEMS Announcement, 41 pages,

Analytical Uses of Immobilized Biological Compounds for Detection, Medical and Industrial Uses, edited by G. G. Guilbault and M. Mascini, Reidel Publishing Co.,

Schmidt, W., Optical Spectroscopy in Chemistry and Life Sciences, Wiley-VCH, 2005. Sellami, L., and R. W. Newcomb, "A Mosfet Bridge Fluid Biosensor," IEEE International Symposium on Circuits and Systems, May 30-June 2, 1999, Vol. V, pp. 140-143. Singth, R. P., and D.R. Heldman, Introduction to Food Engineering,Academic Press, Inc.,

Micro-calorimeters for (Bio)chemical Measurements," Sensors and Actuators, Vol.

Ear-Type Multisensors," International Symposium on Circuits and Systems, ISCAS

Silicon," National Aeronautics and Space Administration, Langley Research

Eggins, B. R., Biosensors: an Introduction, Wiley-Teubner, New York, 1996.

**11. Acknowledgments** 

Reinhold, New York, 1990.

43, 1994, pp. 24-30.

John Wiley, 2008.

Center, 1997.

Springer, 2001.

Ultrecht, 1988, pp. 195-206.

1984.

Cambridge University Press, 2005.

2001, Sydney, Australia, volume 2, pp. 285-289.

Scheller, F., and F. Schubert, Biosensors, Elsevier, Amsterdam, 1992.

Applications, Oxford University Press, Oxford, 1987.

available fromXMOSIS@mosis-chip.isi.edu, 1994.

Academy.

**12. References** 

As the performance of a processing system is to be significantly enhanced, on-chip manycore architecture plays an indispensable role. Since there are fast growing numbers of transistors on the chips, two-dimensional topologies face challenges of significant increases in interconnection delay and power consumption (Hennessy & Patterson, 2007; Kurd et al., 2001). Explorations of a suitable three-dimensional integrated circuit (3D IC) with throughsilicon via (TSV) to realize a large number of processing units and highly dense interconnects certainly attracts a lot of attention. However, the combination of processors, memories, and/or sensors in a stacked die leads to the cooling problem in a tottering situation (Tiwari et al., 1998). One solution to overcome the obstacles and continue the performance scaling while still is to integrate on chip many cores and their communication network (Beigne, 2008; Yu & Baas, 2006). Through concerted processors, routers, and links, the network-on-chip (NoC) provides the advantages of low power dissipation and abundance of connectivity. Moreover, because of the widespread uses of radio frequency (RF), micro-electro-mechanical systems (MEMS) (Lu, 2009), and various sensors in mobile applications, proposals of three-dimensional integrated circuit (3D IC) with through silicon via (TSV) implementations in a layered architecture have been reported (Lee, 1992; Tsai & Kang, 2000). For interconnection scalability from layer to layer, 3D fabrics are a necessity. Consequently, a thermal solution which has a high heat removing rate seems unavoidable. Since there are fast growing numbers of transistors on the chips, two-dimensional topologies face challenges of significant increases in wire delay and power consumption. The two factors are often regarded as the primary limitations for current processor architectures (Hennessy & Patterson, 2007; Kurd et al., 2001; Tiwari et al., 1998).

On the other hand, the high packing density of the stacked dies also hampers the heat dissipation of the NoC system. Thermal issues arise from increasing dynamic power losses which in turn raise the temperature. Thermal and power constraints are of great concern with 3D IC since die stacking can dramatically increase power density, if hotspots overlap each other, and additional dies are farther away from the heat sink.

Three-Dimensional Integrated Circuits Design

**2.1.1 Analytical model of the thermal ridge** 

of the surrounding surfaces are *convective*.

taking the transient into consideration is utilized.

(3), we have

needs to be larger.

following equation:

for Thousand-Core Processors: From Aspect of Thermal Management 19

*T TT T k k k gC*

 

conductivity of the material. This fundamental thermal conduction equation describes that the temperature transmitting through the thermal volume depends on time *θ* and directional thermal conductivities *xx k* , *yy k* , and *zz k* (Chieh et al., 2010; Lung et al., 2010). The boundary conditions of the top and bottom surfaces of the chip are *adiabatic* and those

For dissipating the heat into the substrate homogeneously, the inter-core-group thermal ridges are aligned orthogonally in column and in row. The temperature prediction of the many-core system is performed by utilizing CFD-RC which is commercial thermal and fluidic temperature simulation software. However, in order to illustrate the physical phenomenon more intuitively, a simplified one-dimensional conduction equation without

> *xx <sup>T</sup> k g x x*

<sup>1</sup> <sup>2</sup> *<sup>s</sup> T T <sup>q</sup> T T x w xx w k*

where *T*1 and *T*2 are the temperatures of CG1 and CG2, respectively, *q* is the heat conducted to the ambient environment by the thermal ridge, *ks* is the equivalent thermal conductivity of the thermal ridge, and *w* is the width of the thermal ridge. Since *T* denotes the temperature at the location *x*, examining the mid-point *T*1/2 by substituting *x* with *w*/2 into

The temperature distribution between CG1 and CG2 can be expressed by

8

**2.1.2 Effective thermal conductivity of the thermal ridge** 

*q*

The heat removing rate of the thermal ridge is assumed to be *q*. Let us consider two CGs.

2 1

1/2 1/2 1 2

2

From (4), it is easy to see that if the mid-point temperature *T*1/2 is targeted to be lower, *w*

The equivalent thermal conductivity *kszz* of a thermal ridge is decided by the density of the thermal TSVs in the thermal ridge (Chieh et al., 2010; Lung et al., 2010). To determine *kszz*, the effective thermal conductivity should be taken into account and described as the

*<sup>s</sup> <sup>k</sup> T T w T*

1/2

(1)

(2)

(3)

is time, and *k* is the thermal

(4)

is the density of the

At the transient state, the heat conduction can be described by the following equation

*xx yy zz*

*x xy yz z*

where *T* is the temperature, *g* is the heat generation rate in W/cm2,

material, *C* is the thermal capacity of the material,

Thermal-aware floorplanning is the key in which the inter-layer interconnection plays a role more than just signal transmission or power delivery. Figure 1 depicts the usage of thermal TSV to alleviate the heat accumulation, which is brought from that used in printed circuit boards (PCBs) (Lee et al., 1992). For 3D ICs, the problems of high power/thermal density can be more serious than that in the planar form. Thus, the thermal TSVs become essential for heat dissipation. Of particular interest is the design of an efficient heat transferring path. Some recent works discussed the placement of thermal TSVs. However, not only the routing but also the floorplan may need to be changed substantially after the thermal TSVs are inserted (Tsai & Kang, 2000). This leads to long iterations. Further, as the circuit complexity is increased, to insert the thermal TSVs without largely changing the floorplan is an important technology to be developed (Tsui et al., 2003). In order to keep the original routing and floorplan as much as possible, the temperature-driven design should be brought in early phases of the design procedure.

Fig. 1. 3D IC implementations of a multiprocessor system-on-chip (MP-SoC) with (a) a traditional structure and (b) with the insertion of thermal ridges.
