**Library-Based Gate-Level Current Waveform Modeling for Dynamic Supply Noise Analysis**

Mu-Shun Matt Lee and Chien-Nan Jimmy Liu *National Central University Taiwan (ROC)* 

### **1. Introduction**

16 VLSI Design

182 VLSI Design

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As the VLSI technology goes into the nanometer era, the device sizes and supply voltages are continually decreased. The smaller supply voltage reduces the power dissipation but also decreases the noise margin of devices. Therefore, the power integrity problem has become one of the critical issues that limit the design performance (Blakiewicz & Chrzaniwska-Jeske, 2007; kawa, 2008 & Michael et al., 2008). Most of the power supply noises (PSNs) come from two primary sources. One is the IR-drop and the other is the simultaneous switching noise (SSN). Figure 1(a) illustrates a typical RLC model for power supply networks, which is the combination of on-chip power grids and off-chip power pins. The IR-drop is a power supply noise when the supply current goes through those non-zero resistors and results in a I·R voltage drop. The simultaneous switching noise (SSN) is the supply noise which happens when large instantaneous current goes through those non-zero inductors on power networks and generates a L·(di/dt) voltage drop. When the supply voltage is reduced , the noise margin of devices also decreases as shown in Fig.1(b). It may induce worse performance because the driving capability of devices becomes week due to smaller supply voltage. If serious power supply noise occurs, the logic level may be changed, which causes function error in the circuit. The worst situation is the electronmigration (EM) effects. Supply wires are shorten or broken because a large current travels through the small supply wires. Therefore, the power supply noise analysis is reguired at design stages to evaluate the effects caused by power supply noise.

Fig. 1. (a)RLC model for power supply (b) Supply Voltage over Time at Silicon Device.

Library-Based Gate-Level Current Waveform Modeling for Dynamic Supply Noise Analysis 185

In the literature, the authors in (Boliolo et al., 1997) propose an approach to estimate power supply noise at gate level. In their approach, the capacitance of each internal node in a cell, the energy consumption of each transition, and several regression equations representing the timing behavior, are required to estimate the supply current waveforms. Given an input pattern to a cell, its supply current will be approximated as a simple triangle, whose area is the total energy. The base and the height of this triangle are obtained from the regression equations. Then, combining all triangles of every changed cell in time obtains the overall supply current waveform. This approach is a practical solution that can be combined with logic simulation tools. The results shown in the paper are also accurate. However, the required timing behaviors of supply current waveforms are not available in standard library files. Extra characterization efforts for different cell libraries are still required before using

In anthor work (Shimazaki et al., 2000), the authors propose an EMI-noise analysis approach based on a rough supply current waveform. Although their approach also uses standard library infotmation, their current waveform estimaiton approach is too simple to provide accurate supply current waveforms. Most importantly, their approach can be used in combination caircuits only, which is not feasibal for modern complex designs. Therefore, an accurate gate-level supply current model using standard library information, even for sequential circuits, is propsed to avoid addtional charcterization process (Lee et al., 2008). The proposed current model has provided the solutions to estimate the ideal supply current waveforms without noise effects. However, the estimated waveforms cannot be directly used to analyze IR-drop effects because the supply currents will have significant difference with non-zero resistance on the supply lines. Figure 2(b) shows an example obtained from the c432 circuit suffering from different supply noises. In typical cases, the current with supply noise is less than the ideal current. If the ideal supply current waveforms are used to calculate the IR-drop, the results are often overestimated. The direct solution to consider the effects of IR-drop is to extend the libraries with different supply resistors. However, this approach will greatly increase the storage space and characterization efforts for library information, which may be not a good solution. Therefore, a library adjustment method is also proposed to consider the IR-drop effect on supply current modeling with standard

this approach, which is a very time-consuming process.

library information (Lee et al., 2010).

Fig. 3. The proposed gate-level IR-drop analysis flow

While esimating the power supply noise, both the magnitude and slope of supply currents are required. Traditionally, accurate supply current waveforms can only be obtained from the transistor-level simulation. Therefore, in the present design flow, the power supply noise (PSN) check is mostly performed at very late design stage. Although the analysis results are accurate at transistor level, this approach may be impractical for large designs because simulating the entire design at transistor level requires great computation resources. If any problem is found, the designers often tune the width of the supply lines or add another current path to fit the specification. However, if the supply current waveforms are obtained at early stage, more efficient low-power technologies, like multiple supply voltages and powergating, can be used to reduce the supply power and noise (Chen et al., 2005; Juan et al., 2010; Kawa, 2008; Michael et al., 2008; Popovich et al., 2008; Xu et at., 2011 & Zhao et al. 2002). The primary reason of lacking tools for checking the power integrity problems at gate level or higher levels is the limited design information, that current cannot provide waveforms directly. In this research, we propose the gate-level IR-drop analysis method with limited design information to build the missing link of the traditional design flow.

The most popular format to store the gate-level information is the liberty format (LIB) (Synopsys, 2003). The LIB file of a cell library keeps the information of all cells and is widely used in the synthesis and timing analysis at gate level and RT level. However, due to the format limitation, only timing information and average energy consumption are kept in LIB files. They cannot provide instantaneous supply current information directly. One straightforward approach is to approximate the instantaneous supply current using the average power divided by the user-given time interval as illustrated in Fig. 2(a). However, even if the average power is the same, the waveforms can be quite different with different time intervals. It may not be accurate enough to estimate real instantaneous supply current.

Several advanced library formats have been proposed for recording voltage waveforms (ECSM) (Candence, 2006) or current waveforms (CCSM) (Synopsys, 2008) to provide the more accurate timing and power information. These formats need large storage space to record these piece-wise-linear waveforms. Therefore, those new formats are only used in very advanced process, like 65 nm technology. Typically, the libraries with new formats are used to support the static timing analysis to obtain more accurate estimation. It may also support the gate-level power estimation to obtain more accurate peak power. However, because the peak power is often evaluated in the cycle-accurate basis at gate level, it will suffer the same time-interval issue.

Fig. 2. (a) The power waveforms with different time intervals (b) The current waveforms with different supply noises

While esimating the power supply noise, both the magnitude and slope of supply currents are required. Traditionally, accurate supply current waveforms can only be obtained from the transistor-level simulation. Therefore, in the present design flow, the power supply noise (PSN) check is mostly performed at very late design stage. Although the analysis results are accurate at transistor level, this approach may be impractical for large designs because simulating the entire design at transistor level requires great computation resources. If any problem is found, the designers often tune the width of the supply lines or add another current path to fit the specification. However, if the supply current waveforms are obtained at early stage, more efficient low-power technologies, like multiple supply voltages and powergating, can be used to reduce the supply power and noise (Chen et al., 2005; Juan et al., 2010; Kawa, 2008; Michael et al., 2008; Popovich et al., 2008; Xu et at., 2011 & Zhao et al. 2002). The primary reason of lacking tools for checking the power integrity problems at gate level or higher levels is the limited design information, that current cannot provide waveforms directly. In this research, we propose the gate-level IR-drop analysis method with limited

The most popular format to store the gate-level information is the liberty format (LIB) (Synopsys, 2003). The LIB file of a cell library keeps the information of all cells and is widely used in the synthesis and timing analysis at gate level and RT level. However, due to the format limitation, only timing information and average energy consumption are kept in LIB files. They cannot provide instantaneous supply current information directly. One straightforward approach is to approximate the instantaneous supply current using the average power divided by the user-given time interval as illustrated in Fig. 2(a). However, even if the average power is the same, the waveforms can be quite different with different time intervals. It may not be accurate enough to estimate real instantaneous supply current. Several advanced library formats have been proposed for recording voltage waveforms (ECSM) (Candence, 2006) or current waveforms (CCSM) (Synopsys, 2008) to provide the more accurate timing and power information. These formats need large storage space to record these piece-wise-linear waveforms. Therefore, those new formats are only used in very advanced process, like 65 nm technology. Typically, the libraries with new formats are used to support the static timing analysis to obtain more accurate estimation. It may also support the gate-level power estimation to obtain more accurate peak power. However, because the peak power is often evaluated in the cycle-accurate basis at gate level, it will

(a) (b) Fig. 2. (a) The power waveforms with different time intervals (b) The current waveforms

design information to build the missing link of the traditional design flow.

suffer the same time-interval issue.

with different supply noises

In the literature, the authors in (Boliolo et al., 1997) propose an approach to estimate power supply noise at gate level. In their approach, the capacitance of each internal node in a cell, the energy consumption of each transition, and several regression equations representing the timing behavior, are required to estimate the supply current waveforms. Given an input pattern to a cell, its supply current will be approximated as a simple triangle, whose area is the total energy. The base and the height of this triangle are obtained from the regression equations. Then, combining all triangles of every changed cell in time obtains the overall supply current waveform. This approach is a practical solution that can be combined with logic simulation tools. The results shown in the paper are also accurate. However, the required timing behaviors of supply current waveforms are not available in standard library files. Extra characterization efforts for different cell libraries are still required before using this approach, which is a very time-consuming process.

In anthor work (Shimazaki et al., 2000), the authors propose an EMI-noise analysis approach based on a rough supply current waveform. Although their approach also uses standard library infotmation, their current waveform estimaiton approach is too simple to provide accurate supply current waveforms. Most importantly, their approach can be used in combination caircuits only, which is not feasibal for modern complex designs. Therefore, an accurate gate-level supply current model using standard library information, even for sequential circuits, is propsed to avoid addtional charcterization process (Lee et al., 2008).

The proposed current model has provided the solutions to estimate the ideal supply current waveforms without noise effects. However, the estimated waveforms cannot be directly used to analyze IR-drop effects because the supply currents will have significant difference with non-zero resistance on the supply lines. Figure 2(b) shows an example obtained from the c432 circuit suffering from different supply noises. In typical cases, the current with supply noise is less than the ideal current. If the ideal supply current waveforms are used to calculate the IR-drop, the results are often overestimated. The direct solution to consider the effects of IR-drop is to extend the libraries with different supply resistors. However, this approach will greatly increase the storage space and characterization efforts for library information, which may be not a good solution. Therefore, a library adjustment method is also proposed to consider the IR-drop effect on supply current modeling with standard library information (Lee et al., 2010).

Fig. 3. The proposed gate-level IR-drop analysis flow

Library-Based Gate-Level Current Waveform Modeling for Dynamic Supply Noise Analysis 187

**Changing Time**: T(X) is defined as the time that the signal X is crossing 50% VDD, which is the signal transition point in logic simulators recorded in VCD (Value Changed Dump) files. **Voltage Definitions**: VDD is defined as the supply voltage. VT is defined as the threshold

In order to avoid extra characterization efforts while migrating to new cell libraries, a supply current model is proposed based on standard library information. The key idea is using a triangular waveform to approximate the real supply current waveform generated by a cell switching as shown in Fig. 4. Then, the parameters of the triangle are calculated by standard library information only. Finally, the overall supply current waveform can be obtained by combining all triangles of every changed cells in time. Before presenting the proposed approach, some variables must be defined first. For each triangle shown in Fig. 4, four variables, TSTART, TEND, TPEAK and IPEAK, are defined to represent the triangular waveform. TSTART and TEND are the start/end time of the supply current waveform. These two variables define the duration of the waveform. TPEAK and IPEAK are the location and

Although there are a lot of cells in a cell library, most of them can be classified into three categories in our approach. In the following sections, the formulas to construct the current waveform model in each category will be presented. During the formula construction, this work assumes that only the LIB file is available. Therefore, the transistor-level netlist and detailed device sizes are avoided. If some general structures are required to build the formulas, only the information provided in the library data sheet will be used. While applying the proposed methodology to different libraries, users can make necessary

If the CMOS implementation of a cell is a single layer structure, it is called a simple logic cell in this work, such as **INVERTER**, **NAND**, **NOR** as shown in Fig. 5. Those cells can be modeled as an equivalent inverter with two parts, the equivalent PMOS and NMOS. Therefore, in the following discussion, an inverter is used as an example to discuss its supply current model in the charging period (the output signal is rising) and the

**3. Current waveform estimation using library information** 

current value when the maximum supply current occurs.

Fig. 4. The definition of the triangular current waveform

adjustment easily from that public information.

discharging period (the output signal is falling).

**3.1 Simple logic cells** 

voltage of the transistor.

The proposed gate-level IR-drop analysis flow is illustrated in Fig.3. According to the cell switching from gate-level activity files, the corresponding supply current waveform of each cell can be constructed by using standard library information. The supply current waveforms obtained from the original standard libraries are then modified to consider IR-drop effects. Second, the estimated supply current waveforms of all switching cells are summarized in time to obtain the supply current waveforms of the whole circuit. Finally, the IR-drop voltage caused from the supply resistor can be derived from the current waveform.

The rest of this article is organized as follow. In Section 2, the most popular library format, the liberty format, is presented. A gate-level supply current waveform estimation method using standard library information is proposed in Section 3. A correction method of the library information is also proposed to modify the IR-drop effect in Section 4. The experimental results of this work are demonstrated in Section 5 and a simple conclusion is presented in Section 6.
