**3. Current waveform estimation using library information**

In order to avoid extra characterization efforts while migrating to new cell libraries, a supply current model is proposed based on standard library information. The key idea is using a triangular waveform to approximate the real supply current waveform generated by a cell switching as shown in Fig. 4. Then, the parameters of the triangle are calculated by standard library information only. Finally, the overall supply current waveform can be obtained by combining all triangles of every changed cells in time. Before presenting the proposed approach, some variables must be defined first. For each triangle shown in Fig. 4, four variables, TSTART, TEND, TPEAK and IPEAK, are defined to represent the triangular waveform. TSTART and TEND are the start/end time of the supply current waveform. These two variables define the duration of the waveform. TPEAK and IPEAK are the location and current value when the maximum supply current occurs.

Fig. 4. The definition of the triangular current waveform

Although there are a lot of cells in a cell library, most of them can be classified into three categories in our approach. In the following sections, the formulas to construct the current waveform model in each category will be presented. During the formula construction, this work assumes that only the LIB file is available. Therefore, the transistor-level netlist and detailed device sizes are avoided. If some general structures are required to build the formulas, only the information provided in the library data sheet will be used. While applying the proposed methodology to different libraries, users can make necessary adjustment easily from that public information.

#### **3.1 Simple logic cells**

186 VLSI Design

The proposed gate-level IR-drop analysis flow is illustrated in Fig.3. According to the cell switching from gate-level activity files, the corresponding supply current waveform of each cell can be constructed by using standard library information. The supply current waveforms obtained from the original standard libraries are then modified to consider IR-drop effects. Second, the estimated supply current waveforms of all switching cells are summarized in time to obtain the supply current waveforms of the whole circuit. Finally, the IR-drop voltage

The rest of this article is organized as follow. In Section 2, the most popular library format, the liberty format, is presented. A gate-level supply current waveform estimation method using standard library information is proposed in Section 3. A correction method of the library information is also proposed to modify the IR-drop effect in Section 4. The experimental results of this work are demonstrated in Section 5 and a simple conclusion is

Liberty format (LIB) (Synosys, 2003) is the most popular library format at gate level to store the timing information and the average energy consumption of each cell in the standard library. Those data are stored using some look-up tables. The definitions of some commonly used variables are listed as follows. They will be used later to derive the proposed current

**Transition Time**: This is defined as the duration time of a signal from 10% to 90% VDD in the rising case and from 90% to 10% VDD in the falling case. TR(X) is defined as the transition time of the node X in the rising case. TF(X) is defined as the transition time of the

**Propagation Time**: This is defined as the duration time from the input signal crossing 50% VDD to the output signal crossing 50% VDD. TDR(XÆY) is defined as the propagation delay from the related pin X to the output Y when the output Y is rising. D represents the propagation delay and R represents the rising case. TDF(XÆY) is defined as the propagation delay from the related pin X to the output Y when the output Y is falling. F represents the

**Setup Time**: This is a timing constraint of the sequential cell, which is defined as the minimum time that the data input D must remain stable before the active edge of the clock CK to ensure correct functioning of the cell. In other words, it is the duration from D crossing 50% VDD to CK crossing 50% VDD if the output value can be evaluated successfully. TSR(D) is defined as the setup time when the data input D is rising. S represents the setup time and R represents the rising case. TSF(D) is the setup time when the

**Load**: This is the total capacitance at a node. Load(Y) is defined as the capacitance at the

**Internal Powe**r: This is the internal energy consumption of a cell without the energy consumed on its output loading. EINT is defined as the internal energy consumption of the

caused from the supply resistor can be derived from the current waveform.

presented in Section 6.

waveform model.

falling case.

node Y.

cell.

node X in the falling case.

**2. Standard library: Liberty format (LIB)** 

data input D is falling. F represents the falling case.

If the CMOS implementation of a cell is a single layer structure, it is called a simple logic cell in this work, such as **INVERTER**, **NAND**, **NOR** as shown in Fig. 5. Those cells can be modeled as an equivalent inverter with two parts, the equivalent PMOS and NMOS. Therefore, in the following discussion, an inverter is used as an example to discuss its supply current model in the charging period (the output signal is rising) and the discharging period (the output signal is falling).

Library-Based Gate-Level Current Waveform Modeling for Dynamic Supply Noise Analysis 189

τ

[ ( 0% ) ( 50% )] ln(0.5)

( ) [ ( 0% ) ( 50% )] [ ( 0% ) ( 95% )]

*T Y TD V Y VDD V Y VDD TD V Y VDD V Y VDD*

In this paper, two points (X1, Y1) and (X2, Y2) on a plane are used to define a line. Then, the

11 2 2

Under this definition, the time t that the equation Y(t) is larger than the equation X(t) with

*Xt X Y X Y a t b*

= = ×+

( ) {( , ),( , )}

*Intercept b b Y a X*

*X Y X Y*

*a a*

*VT b b Then t T Y t X t VT*

In the charging period, TPEAK is defined as the time that the operation mode of NMOS is in the saturation mode and the operation mode of PMOS is changing from the saturation mode to the linear mode, which is the point that allows most current to flow through PMOS. In other words, TPEAK happens at the time when the voltage difference between the output Y and the input X is equal to VT (VSG=VT). Therefore, TPEAK can be obtained when Y(t) − X(t) = VT. Because the definitions of TF(X) and TR(Y) are the signal duration from 10% to 90% VDD, using them to calculate the signal duration from 0% to 50% VDD should be multiplied by 0.625(=0.5/(90% − 10%)) instead of 0.5. Finally, the corollary of TPEAK is shown as follows.

> ( ) {( ( ),0.5 ),( ( ) 0.625 ( ), )} ( ) {( ( ),0.5 ),( ( ) 0.625 ( ),0)}

*X t T X VDD T X TF X VDD Y t T Y VDD T Y TR Y*

If the total consumed energy is used as the area of this triangle and the base of this triangle is (TEND-TSTART), IPEAK can be obtained from the formula of the triangle area. Please note that the energy stored in the LIB file is the internal energy consumption (EINT) of the cell only.

− − = = −= <sup>−</sup>

<sup>−</sup> ⇒ = <sup>−</sup>

2 1 2 1

⇒ = −×

1 1

( ) ( () () )

⇒ = →= = ×

τ

 τ τ

(2)

(3)

ln( )

*VDD*

*VDD VDD VDD*

0.5 ln( )

( ) ln(0.5) ln(1 0.95)

= − ×+ − ×

( )

( () () )

( ( ) ( )) ) *PEAK*

<sup>⎧</sup> = × −× <sup>⎨</sup> ⎩ = × −×

*T T Y t X t VT*

⇒= −=

− =

*X X Y Y*

( )

*Y Y Slope a a X X*

τ

= − = →= + = →=

<sup>⎨</sup> − × <sup>⎪</sup> <sup>=</sup> <sup>×</sup> ⎪⎩

*VDD TD V Y VDD V Y VDD*

0%

*t*

*VDD*

<sup>⎧</sup> = × ⎪⎪

50%

*TEND*

*T Y*

VT can be calculated as follows.

slope (a) and intercept (b) can be calculated as follows.

( ) ( )

*Xt a t b Yt a t b If Y t X t VT*

<sup>⎧</sup> = ×+ <sup>⎨</sup> ⎩ = ×+

*t*

*VDD*

Fig. 5. The structures of simple logic cells (a) INVERTER (b) NAND (c) NOR

#### **3.1.1 Charging period**

In the charging period, the relationship between the input signal X, the output signal Y and the timing parameters of the triangular waveform can be illustrated in Fig. 6. TSTART is defined as the time that the input voltage achieves (VDD-VT) because the equivalent PMOS turns on at this time. The corollary of TSTART is shown as follows.

$$\begin{aligned} \frac{T\_{\text{STAR}} - [T(X) - 0.625 \times TF(X)]}{VT} &= \frac{1.25 \times TF(X)}{VDD} \\ \Rightarrow T\_{\text{STAR}} &= T(X) - 1.2 \times TF(X) \times \frac{0.5 \times VDD - VT}{VDD} \\ \text{@WORK} &= \left[ \frac{\text{Total}}{\text{Total}} \right] \times \text{Time} \\ \text{@NOVOD} &= \left[ \frac{\text{Total}}{\text{Total}} \right] \times \left[ \frac{\text{Total}}{\text{Total}} \right] \times \left[ \frac{\text{Total}}{\text{Total}} \right] \\ \text{@NOVOD} &= \left[ \frac{\text{Total}}{\text{Total}} \right] \times \left[ \frac{\text{Total}}{\text{Total}} \right] \times \left[ \frac{\text{Total}}{\text{Total}} \right] \\ \text{@NOVOD} &= \left[ \frac{\text{Total}}{\text{Total}} \right] \times \left[ \frac{\text{Total}}{\text{Total}} \right] \times \left[ \frac{\text{Total}}{\text{Total}} \right] \end{aligned}$$

Fig. 6. The parameters of a simple cell in the charging period

In typical cases, the shape of the charging current for a simple logic cell is similar to a RC charging behavior. Therefore, the exponential RC charging function is used to approximate this behavior. Theoretically, TEND is defined as the time when the output loading is charged to VDD. However, due to the long tail of the RC charging curve, TEND is defined as the time that the output loading is charged to 95% VDD in this work to reduce the error while the waveform is simplified to a triangle. The corollary of TEND is shown as follows, where τ is the RC time constant.

$$V'(t) = V\_0 \times (1 - e^{\frac{(\cdots t)}{\tau}}) \implies t = \ln(\frac{V\_0 - V(t)}{V\_0}) \times \tau$$

$$\begin{cases} t\_{10\%VDD} = \ln(\frac{VDD - 0.1 \times VDD}{VDD}) \times \tau \\ t\_{90\%VDD} = \ln(\frac{VDD - 0.9 \times VDD}{VDD}) \times \tau \end{cases} \Rightarrow TR(Y) = [\ln(0.9) - \ln(0.1)] \times \tau \Longrightarrow \tau = \frac{TR(Y)}{\ln(9)}$$

In the charging period, the relationship between the input signal X, the output signal Y and the timing parameters of the triangular waveform can be illustrated in Fig. 6. TSTART is defined as the time that the input voltage achieves (VDD-VT) because the equivalent PMOS

0.5 ( ) 1.2 ( )

In typical cases, the shape of the charging current for a simple logic cell is similar to a RC charging behavior. Therefore, the exponential RC charging function is used to approximate this behavior. Theoretically, TEND is defined as the time when the output loading is charged to VDD. However, due to the long tail of the RC charging curve, TEND is defined as the time that the output loading is charged to 95% VDD in this work to reduce the error while the waveform is simplified to a triangle. The corollary of TEND is shown as follows, where τ is

( ) <sup>0</sup>

0.1 ln( ) ( ) ( ) [ln(0.9) ln(0.1)] 0.9 ln(9) ln( )

*VDD TR Y TR Y*

<sup>−</sup> <sup>−</sup> <sup>=</sup> × − ⇒= ×

( ) ( ) (1 ) ln( ) *<sup>t</sup> V Vt Vt V e t*

τ

τ

τ

<sup>⎨</sup> ⇒ = − ×⇒ = − × <sup>⎪</sup> <sup>=</sup> <sup>×</sup> ⎪⎩

0

τ

τ τ

*V*

× − ⇒ = −× ×

*T T X TF X TF X*

<sup>−</sup> − × <sup>×</sup> <sup>=</sup>

[ ( ) 0.625 ( )] 1.25 ( )

*VT VDD VDD VT T T X TF X*

*VDD*

(1)

Fig. 5. The structures of simple logic cells (a) INVERTER (b) NAND (c) NOR

turns on at this time. The corollary of TSTART is shown as follows.

*START*

*START*

Fig. 6. The parameters of a simple cell in the charging period

0

*VDD VDD*

<sup>⎧</sup> − × <sup>=</sup> <sup>×</sup> ⎪⎪

*VDD VDD*

*VDD*

**3.1.1 Charging period** 

the RC time constant.

10%

*t*

*t*

*VDD*

*VDD*

90%

$$\begin{cases} & t\_{\text{@}\%DID} = \ln(\frac{VDD}{VDD}) \times \tau \\\\ & t\_{\text{@}\%DID} = \ln(\frac{VDD - 0.5 \times VDD}{VDD}) \times \tau \end{cases}$$

$$\implies TD[V(Y = 0 \%VDD) \to V(Y = 50 \%VDD)] = \ln(0.5) \times \tau$$

$$\begin{aligned} T\_{EUD} \\ &= T(Y) - TD[V(Y = 0 \%VDD) \to V(Y = 50 \%VDD)] \\ &+ T D[V(Y = 0 \%VDD) \to V(Y = 9 \\$\%VDD)] \\ &= T(Y) - \ln(0.5) \times \tau + \ln(1 - 0.95) \times \tau \end{aligned} \tag{2}$$

In this paper, two points (X1, Y1) and (X2, Y2) on a plane are used to define a line. Then, the slope (a) and intercept (b) can be calculated as follows.

$$\begin{aligned} X(t) &= \{ (X\_1, Y\_1), (X\_2, Y\_2) \} = a \times t + b \\ Slope(a) &\Longrightarrow a = \frac{Y\_2 - Y\_1}{X\_2 - X\_1} \\ Interval(b) &\Longrightarrow b = Y\_1 - a \times X\_1 \end{aligned}$$

Under this definition, the time t that the equation Y(t) is larger than the equation X(t) with VT can be calculated as follows.

$$\begin{cases} X(t) = a\_X \times t + b\_X \\ Y(t) = a\_Y \times t + b\_Y \end{cases}$$

$$\begin{aligned} If \quad (Y(t) - X(t) = VT) \\ Then \quad t = \frac{VT - (b\_X - b\_Y)}{a\_X - a\_Y} = T(Y(t) - X(t) = VT) \end{aligned}$$

In the charging period, TPEAK is defined as the time that the operation mode of NMOS is in the saturation mode and the operation mode of PMOS is changing from the saturation mode to the linear mode, which is the point that allows most current to flow through PMOS. In other words, TPEAK happens at the time when the voltage difference between the output Y and the input X is equal to VT (VSG=VT). Therefore, TPEAK can be obtained when Y(t) − X(t) = VT. Because the definitions of TF(X) and TR(Y) are the signal duration from 10% to 90% VDD, using them to calculate the signal duration from 0% to 50% VDD should be multiplied by 0.625(=0.5/(90% − 10%)) instead of 0.5. Finally, the corollary of TPEAK is shown as follows.

$$\begin{cases} X(t) = \{ (T(X), 0.5 \times VDD), (T(X) - 0.625 \times TF(X), VDD) \} \\ Y(t) = \{ (T(Y), 0.5 \times VDD), (T(Y) - 0.625 \times TR(Y), 0) \} \\ \implies T\_{PEK} = T(Y(t) - X(t)) = VT \end{cases} \tag{3}$$

If the total consumed energy is used as the area of this triangle and the base of this triangle is (TEND-TSTART), IPEAK can be obtained from the formula of the triangle area. Please note that the energy stored in the LIB file is the internal energy consumption (EINT) of the cell only.

Library-Based Gate-Level Current Waveform Modeling for Dynamic Supply Noise Analysis 191

= × − × ⇒ =× <sup>−</sup>

As shown in Fig. 8, some cells are composed of two or more simple logic cells, such as **BUFFER**, **AND**, and **OR** cells. Those cells are called "composite logic cells" in this work. In the following descriptions, a **BUFFER** is used as an example to explain the proposed approach for those cells. Because the information of the internal signal I in Fig. 8(a) cannot be obtained in the LIB file, an assumption is made in this work that the input signal of the second stage in a composite cell will start rising/falling when the output voltage of its first stage achieves 50% VDD. With this assumption, the internal signal I can be rebuilt using existing library information as shown in Fig. 9. Since the timing information of the internal node can be estimated, the methods proposed in Sect. 3.1 can be used to handle the two simple cells

*INT*

(8)

*END START*

*T T*

<sup>1</sup> () 2 <sup>2</sup>

*<sup>E</sup> E TT I I*

*INT END START PEAK PEAK*

respectively and the total current waveform of this composite cell can be estimated.

Fig. 8. The structure of the composite logic cell (a) BUFFER (b) AND (c) OR

If the output of the composite cell is rising, the internal node I will be in the falling case as shown in Fig. 10. Therefore, the simple-cell methods in the discharging period are used to calculate TSTART\_1stF, TEND\_1stF and TPEAK\_1stF of the first stage. Then, the simple-cell methods in the charging period are used to calculate TSTART\_2ndR, TEND\_2ndR and TPEAK\_2ndR of the second stage. Because there is only one energy value in the library and no proper method to split it into two parts, an assumption is made that the transition of the two stages are very close such that the composition of the two triangles still approximates to a triangle. While combining the triangles of the two stages, the TSTART, TPEAK and TEND of the composed triangle are defined as the average values of the two triangles in this work for easier calculation. Then, IPEAK can be obtained in the same way from those timing information and

Fig. 9. The internal voltage waveform in a composite cell

**3.2.1 Charging period** 

**3.2 Composite logic cells** 

The energy consumed on the output loading (ELOAD) should be added to obtain the correct area of the triangle. The corollary of IPEAK is shown as follows.

$$E\_{INT} + E\_{LOAD} = \frac{1}{2} \times (T\_{END} - T\_{START}) \times I\_{PEAK} \tag{4}$$

$$\implies I\_{PEAK} = 2 \times \frac{E\_{INT} + E\_{LOAD}}{T\_{END} - T\_{START}}$$

#### **3.1.2 Discharging period**

Because the supply current does not charge the output loading in the discharging period, most of the supply current can appear only when NMOS is turned on but PMOS is not completely turned off yet. Therefore, in this case, TSTART is defined as the time that input voltage achieves VT because NMOS is turned on at this time. TEND is defined as the time that the input voltage achieves (VDD-VT) when PMOS is turned off. Using these definitions, the duration of the supply current waveform in the discharging period can be decided. Following the same assumption in Section 3.1.1, TPEAK is still defined as the time that the operation mode of PMOS is changed from linear to saturation. Figure 7 shows their relationship to the input/output waveforms. Because there is no current charging the output loading, the EINT obtained in the LIB file can be used as the triangle area in the discharging period to obtain the TPEAK value. The corollary of TEND is shown as follows.

Fig. 7. The parameters of a simple cell in the discharging period

*END*

$$\frac{T\_{S\text{LMT}} - [T(X) - 0.625 \times TR(X)]}{VT} = \frac{1.25 \times TR(X)}{VDD} \tag{5}$$

$$\Rightarrow T\_{S\text{LMT}} = T(X) - 1.25 \times TR(X) \times \frac{0.5 \times VDD - VT}{VDD}$$

$$\frac{[T(X) + 0.625 \times TR(X)] - T\_{ED}}{VT} = \frac{1.25 \times TR(X)}{VDD} \tag{6}$$

$$\implies T\_{ED} = T(X) + 1.25 \times TR(X) \times \frac{0.5 \times VDD - VT}{VDD}$$

*VDD*

$$\begin{cases} X(t) = \{ (T(X), 0.5 \times VDD), (T(X) - 0.625 \times TR(X), 0) \} \\ Y(t) = \{ (T(Y), 0.5 \times VDD), (T(Y) - 0.625 \times TF(Y), VDD) \} \\ \implies T\_{PEAK} = T(Y(t) - X(t)) = VT \end{cases} \tag{7}$$

$$E\_{\rm INT} = \frac{1}{2} \times (T\_{\rm END} - T\_{\rm START}) \times I\_{\rm PEAK} \implies I\_{\rm PEAK} = 2 \times \frac{E\_{\rm MT}}{T\_{\rm END} - T\_{\rm START}} \tag{8}$$

#### **3.2 Composite logic cells**

190 VLSI Design

The energy consumed on the output loading (ELOAD) should be added to obtain the correct

*INT LOAD END START PEAK INT LOAD*

+ =× − × +

*EE TT I*

*T T*

*END START*

Because the supply current does not charge the output loading in the discharging period, most of the supply current can appear only when NMOS is turned on but PMOS is not completely turned off yet. Therefore, in this case, TSTART is defined as the time that input voltage achieves VT because NMOS is turned on at this time. TEND is defined as the time that the input voltage achieves (VDD-VT) when PMOS is turned off. Using these definitions, the duration of the supply current waveform in the discharging period can be decided. Following the same assumption in Section 3.1.1, TPEAK is still defined as the time that the operation mode of PMOS is changed from linear to saturation. Figure 7 shows their relationship to the input/output waveforms. Because there is no current charging the output loading, the EINT obtained in the LIB file can be used as the triangle area in the discharging period to obtain the TPEAK value. The corollary of TEND is shown as follows.

[ ( ) 0.625 ( )] 1.25 ( )

*VT VDD VDD VT T T X TR X*

*END*

*VT VDD VDD VT T T X TR X*

*VDD*

*VDD*

0.5 ( ) 1.25 ( )

*T T X TR X TR X*

× − ⇒ = −× ×

[ ( ) 0.625 ( )] 1.25 ( )

*T X TR X T TR X*

<sup>+</sup> × − <sup>×</sup> <sup>=</sup>

0.5 ( ) 1.25 ( )

( ) {( ( ),0.5 ),( ( ) 0.625 ( ),0)} ( ) {( ( ),0.5 ),( ( ) 0.625 ( ), )}

× − ⇒ = +× ×

*X t T X VDD T X TR X Y t T Y VDD T Y TF Y VDD*

<sup>⎧</sup> = × −× <sup>⎨</sup> ⎩ = × −×

<sup>−</sup> − × <sup>×</sup> <sup>=</sup>

<sup>1</sup> ( ) <sup>2</sup>

(4)

(5)

(6)

(7)

area of the triangle. The corollary of IPEAK is shown as follows.

**3.1.2 Discharging period** 

2

⇒ =× <sup>−</sup>

*E E <sup>I</sup>*

*PEAK*

Fig. 7. The parameters of a simple cell in the discharging period

*START*

*START*

*END*

( ( ) ( )) ) *PEAK*

*T T Y t X t VT*

⇒= −=

As shown in Fig. 8, some cells are composed of two or more simple logic cells, such as **BUFFER**, **AND**, and **OR** cells. Those cells are called "composite logic cells" in this work. In the following descriptions, a **BUFFER** is used as an example to explain the proposed approach for those cells. Because the information of the internal signal I in Fig. 8(a) cannot be obtained in the LIB file, an assumption is made in this work that the input signal of the second stage in a composite cell will start rising/falling when the output voltage of its first stage achieves 50% VDD. With this assumption, the internal signal I can be rebuilt using existing library information as shown in Fig. 9. Since the timing information of the internal node can be estimated, the methods proposed in Sect. 3.1 can be used to handle the two simple cells respectively and the total current waveform of this composite cell can be estimated.

Fig. 8. The structure of the composite logic cell (a) BUFFER (b) AND (c) OR

Fig. 9. The internal voltage waveform in a composite cell

#### **3.2.1 Charging period**

If the output of the composite cell is rising, the internal node I will be in the falling case as shown in Fig. 10. Therefore, the simple-cell methods in the discharging period are used to calculate TSTART\_1stF, TEND\_1stF and TPEAK\_1stF of the first stage. Then, the simple-cell methods in the charging period are used to calculate TSTART\_2ndR, TEND\_2ndR and TPEAK\_2ndR of the second stage. Because there is only one energy value in the library and no proper method to split it into two parts, an assumption is made that the transition of the two stages are very close such that the composition of the two triangles still approximates to a triangle. While combining the triangles of the two stages, the TSTART, TPEAK and TEND of the composed triangle are defined as the average values of the two triangles in this work for easier calculation. Then, IPEAK can be obtained in the same way from those timing information and

Library-Based Gate-Level Current Waveform Modeling for Dynamic Supply Noise Analysis 193

*VDD I T T* ×

Fig. 11. The rebuilding voltage waveform of a composite logic cell in the discharging period

In real applications, most circuits contain sequential cells. For a feasible solution, it is important to develop proper approaches to handle sequential cells. Like composite cells, sequential cells are often composed of several simple cells. In a standard library, the information of the internal nodes in a sequential cell is not stored, either. In order not to use extra information, some assumptions are made to rebuild the internal signals of a sequential cell. In the following descriptions, a positive-edge-triggered D-flip-flop (**DFF**) is used as an example to explain the proposed approach on sequential cells. Other flip-flops in the standard cell library, such as the flip-flops with set/reset, can be handled by using similar methods for their normal operations. The special set/reset behaviors can be characterized as

Figure 12 shows the typical architecture of a DFF. It can be divided into three blocks, which are clock generator, setup block and evaluation block. The total supply current waveform of the DFF is the summation of the waveforms from the three blocks. Since the operation modes of a DFF are more complex, its current waveform model is discussed in three cases.

**3.3 Sequential elements** 

a special case since they do not appear very often.

Fig. 12. The architecture of a typical DFF

*PEAK*

⇒ = <sup>−</sup>

2 *INT*

*E*

*END START*

\_1 \_ 2 {, } ⇒ = *T avg T T END END stR END ndF* (15)

(16)

the stored energy information. The detailed formulas to construct the current waveforms in this case are summarized as follows.

$$\begin{aligned} X(t) &= \{ (T(X), 0.5 \times VDD), (T(X) - 0.625 \times TR(X), 0) \} \\ Y(t) &= \{ (T(X), VDD), (T(X) - 0.625 \times TR(Y), 0.5 \times VDD) \} \\ Y(t) &= \{ (T(Y), 0.5 \times VDD), (T(Y) - 0.625 \times TR(Y), 0) \} \end{aligned} \tag{9}$$

$$\implies T\_{\text{START}} = a \text{avg} \left( T\_{\text{START\\_1MF}}, T\_{\text{START\\_2nR}} \right) \tag{10}$$

$$\implies T\_{PE4K} = a \text{vg} \left\{ T\_{PE4K\_{\\_1M^F}}, T\_{PE4K\_{\\_2ndR}} \right\}$$

$$T\_{\rm{END}} = \arg \left\{ T\_{\rm{ED\_{-1}inF}}, T\_{\rm{END\_{-2}inR}} \right\} \tag{11}$$

$$\implies I\_{PEK} = \frac{2 \times (\frac{E\_{INT}}{VDD} + Loading(Y) \times VDD}{T\_{END} - T\_{START}} \tag{12}$$

Fig. 10. The rebuilding voltage waveform of a composite logic cell in the charging period

#### **3.2.2 Discharging period**

If the output of a buffer is falling, the internal node I will be in the rising case. Therefore, the simple-cell formulas in the charging period are used to handle the first stage. The simplecell formulas in the discharging period are used to handle the second stage. Then, using the similar approach for the case in charging period, TSTART, TPEAK and TEND can be obtained from the average values of the two triangles. The rebuilt voltage waveforms and timing parameters are shown in Fig. 11. Because the energy of the reversed supply current at the second stage can be eliminated by the energy of the first stage, the internal power in the discharging period can be used directly to estimate the IPEAK of this cell. The detailed formulas to construct the current waveform in this case are listed as follows.

$$X(t) = \langle (T(X), 0.5 \times VDD), (T(X) - 0.625 \times TF(X), VDD) \rangle$$

$$I(t) = \langle (T(X), VDD), (T(X) - 0.625 \times TF(Y), 0.5 \times VDD) \rangle$$

$$Y(t) = \langle (T(Y), 0.5 \times VDD), (T(Y) - 0.625 \times TF(Y), VDD) \rangle$$

$$\implies T\_{STAT} = \text{avg}\left\{ T\_{STAT\\_1\\_{\text{all}}}, T\_{STAT\\_2\\_{\text{all}}} \right\}$$

$$\implies T\_{PEK} = \text{avg}\left\{ T\_{PEK\\_1\\_{\text{all}}}, T\_{PEK\\_2\\_{\text{all}}} \right\} \tag{14}$$

$$T\_{\rm{END}} = \arg \left\{ T\_{\rm{END\\_1uR\\_2}}, T\_{\rm{END\\_2udF}} \right\} \tag{15}$$

$$\implies I\_{PE,K} = \frac{2 \times \frac{E\_{INT}}{VDD}}{T\_{END} - T\_{START}} \tag{16}$$

Fig. 11. The rebuilding voltage waveform of a composite logic cell in the discharging period

#### **3.3 Sequential elements**

192 VLSI Design

the stored energy information. The detailed formulas to construct the current waveforms in

( ) {( ( ),0.5 ),( ( ) 0.625 ( ),0)} ( ) {( ( ), ),( ( ) 0.625 ( ),0.5 )} ( ) {( ( ),0.5 ),( ( ) 0.625 ( ),0)}

\_1 \_ 2 {, } ⇒ = *T avg T T PEAK PEAK stF PEAK ndR*

2( () ) *INT*

*<sup>E</sup> Load Y VDD*

*END START*

*T T* ×+ ×

Fig. 10. The rebuilding voltage waveform of a composite logic cell in the charging period

If the output of a buffer is falling, the internal node I will be in the rising case. Therefore, the simple-cell formulas in the charging period are used to handle the first stage. The simplecell formulas in the discharging period are used to handle the second stage. Then, using the similar approach for the case in charging period, TSTART, TPEAK and TEND can be obtained from the average values of the two triangles. The rebuilt voltage waveforms and timing parameters are shown in Fig. 11. Because the energy of the reversed supply current at the second stage can be eliminated by the energy of the first stage, the internal power in the discharging period can be used directly to estimate the IPEAK of this cell. The detailed

> ( ) {( ( ),0.5 ),( ( ) 0.625 ( ), )} ( ) {( ( ), ),( ( ) 0.625 ( ),0.5 )} ( ) {( ( ),0.5 ),( ( ) 0.625 ( ), )}

*X t T X VDD T X TF X VDD I t T X VDD T X TF Y VDD Y t T Y VDD T Y TF Y VDD*

\_1 \_ 2 {, } ⇒ = *T avg T T START START stR START ndF*

\_1 \_ 2 {, } ⇒ = *T avg T T PEAK PEAK stR PEAK ndF* (14)

= × −× = −× × = × −×

formulas to construct the current waveform in this case are listed as follows.

\_1 \_ 2 {, } ⇒ = *T avg T T START START stF START ndR* (10)

\_1 \_ 2 {, } ⇒ = *T avg T T END END stF END ndR* (11)

(9)

(12)

(13)

*X t T X VDD T X TR X I t T X VDD T X TR Y VDD*

= × −× = −× × = × −×

*Y t T Y VDD T Y TR Y*

*PEAK*

*VDD I*

⇒ = <sup>−</sup>

this case are summarized as follows.

**3.2.2 Discharging period** 

In real applications, most circuits contain sequential cells. For a feasible solution, it is important to develop proper approaches to handle sequential cells. Like composite cells, sequential cells are often composed of several simple cells. In a standard library, the information of the internal nodes in a sequential cell is not stored, either. In order not to use extra information, some assumptions are made to rebuild the internal signals of a sequential cell. In the following descriptions, a positive-edge-triggered D-flip-flop (**DFF**) is used as an example to explain the proposed approach on sequential cells. Other flip-flops in the standard cell library, such as the flip-flops with set/reset, can be handled by using similar methods for their normal operations. The special set/reset behaviors can be characterized as a special case since they do not appear very often.

Figure 12 shows the typical architecture of a DFF. It can be divided into three blocks, which are clock generator, setup block and evaluation block. The total supply current waveform of the DFF is the summation of the waveforms from the three blocks. Since the operation modes of a DFF are more complex, its current waveform model is discussed in three cases.

Fig. 12. The architecture of a typical DFF

Library-Based Gate-Level Current Waveform Modeling for Dynamic Supply Noise Analysis 195

The second assumption is that the rising and falling times of the nodes cn and c are very similar because most clock buffers are designed to have similar rising and falling time. From the first assumption, the time when V(c)=0.5 × VDD + VT can be obtained. Following the same assumption for composite cells, the input signal of the second stage will start rising/falling when the output voltage of the previous stage achieves 50% VDD. In order to simplify the explanation, a time interval (PT) is defined in Fig. 14. Since PT can be obtained with these two assumptions, the times that c and cn reach 0.5×VDD can be expressed with PT. Then, the internal voltage waveforms can be rebuilt as shown in Fig. 14. The detailed

[ ( ( ) 0.5 ]-[ ( ) ]

= =× + +

<sup>2</sup> [ ( ) 0.625 ( )] 0.5 2( )

( ) {( ( ),0.5 ),( ( ) 0.625 ( ),0)}

\_1 \_ 2 {, } ⇒ = *T avg T T START START stF START ndR*

2 *INT*

*VDD I T T* ×

As to the CK falling case, no outputs change and no timing information is stored in the library because it is not the active edge. Although the internal nodes might change in this case, there is no information to make any reasoning. Therefore, the same timing information in the CK rising case is used to be the TSTART, TPEAK and TEND when only CK is falling. The internal energy consumption when only CK is falling is available in the library. It can be

In this case, the clock pin CK is stable and only the data pin D is changed. The supply current is generated by the setup block only. If CK is logic-1, the gate G3 is turned off such that the whole cell has no switching current. When CK is logic-0, the current waveform is determined by whether the data pin D is rising or falling. Because the timing information of the internal nodes N1\_1 and N1\_2 are not stored in the library, two assumptions are made

in this case to rebuild the approximate voltage waveforms of N1\_1 and N1\_2.

*E*

*END START*

\_1 \_ 2 {, } ⇒ = *T avg T T PEAK PEAK stF PEAK ndR* (18)

\_1 \_2 {, } ⇒ = *T avg T T END END stF END ndR* (19)

( ) {( ( ), ),( ( ) ,0.5 )} ( ) {( ( ) ,0),( ( ) 3 ), )}

*PEAK*

⇒ = <sup>−</sup>

*CK t T CK VDD T CK TR CK cn t T CK VDD T CK PT VDD c t T CK PT T CK PT VDD*

= × −× = + × = + + ×

*<sup>X</sup> PT VDD PT TDR CK Q TR Q VDD VT VDD VDD VT*

<sup>×</sup> = ⇒= × →− ×

(17)

(20)

corollary is listed as follows.

( ( ) 0.5 )

=× + = + →− ×

*T V c VDD VT*

( ) ( ) 0.625 ( )

× + × +

*T CK TDR CK Q TR Q*

used to calculate a different IPEAK for CK falling case.

**3.3.2 Only data pin is changed** 

*Assume X T V c VDD VT T CK PT*

#### **3.3.1 Only clock pin is changed**

In this case, the data pin D is stable and its value is the same as the output Q. In most cases, the internal signals, N1\_1, N1\_2, N2\_1 and N2\_2, are stable, too. Therefore, a supply current only occurs in the clock generator when only the clock pin is changing. The clock generator is often composed of two inverters to generate two inverse signals, c and cn, as shown in Fig. 13.

First, the case of CK rising (active edge) is discussed. Using the same idea for composite logic cells, the voltage waveforms of CK, cn and c will be rebuilt first. Then, the formulas of composite logic cells in the charging period can be used directly to decide TSTART, TPEAK, TEND and IPEAK. However, there is still no timing information for the internal nodes of flipflops in the LIB file. In order to solve this problem, two assumptions are made to rebuild the internal signals (cn and c) with approximate timing information.

The first assumption is that the maximum current of the tri-state inverter (G6) occurs when its output voltage (N2\_1) reaches 50% VDD, as illustrated in Fig. 13. Then, following the TPEAK definition of simple cells, the maximum current happens when the difference between the gate voltage of c and the drain voltage of N2\_1 is equal to VT. The time that the voltage of c reaches [0.5×VDD+VT] can be implied with [T(CK) + TDR(CKÆQ) − 0.625×TR(Q) ].

Fig. 13. The illustration of the first assumption to imply the timing information of internal node (c).

Fig. 14. The illustration of the second assumption to imply the timing information of internal nodes (cn) and (c).

The second assumption is that the rising and falling times of the nodes cn and c are very similar because most clock buffers are designed to have similar rising and falling time. From the first assumption, the time when V(c)=0.5 × VDD + VT can be obtained. Following the same assumption for composite cells, the input signal of the second stage will start rising/falling when the output voltage of the previous stage achieves 50% VDD. In order to simplify the explanation, a time interval (PT) is defined in Fig. 14. Since PT can be obtained with these two assumptions, the times that c and cn reach 0.5×VDD can be expressed with PT. Then, the internal voltage waveforms can be rebuilt as shown in Fig. 14. The detailed corollary is listed as follows.

$$\begin{aligned} \text{Assume} \quad & X = \left[ T(V(c) = 0.5 \times VDD + VT) \cdot \left[ T(CK) + PT \right] \right] \\ & T(V(c) = 0.5 \times VDD + VT) \\ & T = T(CK) + TDR(CK \to Q) - 0.625 \times TR(Q) \\ & \frac{X}{0.5 \times VDD + VT} = \frac{2 \times PT}{VDD} \Rightarrow PT = \frac{VDD}{2 \times (VDD + VT)} \times \left[ TDR(CK \to Q) - 0.625 \times TR(Q) \right] \\ & CK(t) = \left\{ (T(CK), 0.5 \times VDD), (T(CK) - 0.625 \times TR(CK), 0) \right\} \\ & cn(t) = \left\{ (T(CK), VDD), (T(CK) + PT, 0.5 \times VDD) \right\} \\ & c(t) = \left\{ (T(CK) + PT, 0), (T(CK) + 3 \times PT, VDD) \right\} \end{aligned} \tag{17}$$

$$\implies T\_{STAT} = \arg\left\{ T\_{STAR\\_1\,1gF}, T\_{STAR\\_2adR} \right\}$$

$$\implies T\_{PEAK} = \arg\left\{ T\_{PEAK\\_1\,1gF}, T\_{PEAK\\_2adR} \right\} \tag{18}$$

$$T\_{\rm{END}} = \arg \left\{ T\_{\rm{END\\_1uF}}, T\_{\rm{END\\_2ndR}} \right\} \tag{19}$$

$$\implies I\_{PEAK} = \frac{2 \times \frac{E\_{INT}}{VDD}}{T\_{END} - T\_{START}} \tag{20}$$

As to the CK falling case, no outputs change and no timing information is stored in the library because it is not the active edge. Although the internal nodes might change in this case, there is no information to make any reasoning. Therefore, the same timing information in the CK rising case is used to be the TSTART, TPEAK and TEND when only CK is falling. The internal energy consumption when only CK is falling is available in the library. It can be used to calculate a different IPEAK for CK falling case.

#### **3.3.2 Only data pin is changed**

194 VLSI Design

In this case, the data pin D is stable and its value is the same as the output Q. In most cases, the internal signals, N1\_1, N1\_2, N2\_1 and N2\_2, are stable, too. Therefore, a supply current only occurs in the clock generator when only the clock pin is changing. The clock generator is often composed of two inverters to generate two inverse signals, c and cn, as shown in

First, the case of CK rising (active edge) is discussed. Using the same idea for composite logic cells, the voltage waveforms of CK, cn and c will be rebuilt first. Then, the formulas of composite logic cells in the charging period can be used directly to decide TSTART, TPEAK, TEND and IPEAK. However, there is still no timing information for the internal nodes of flipflops in the LIB file. In order to solve this problem, two assumptions are made to rebuild the

The first assumption is that the maximum current of the tri-state inverter (G6) occurs when its output voltage (N2\_1) reaches 50% VDD, as illustrated in Fig. 13. Then, following the TPEAK definition of simple cells, the maximum current happens when the difference between the gate voltage of c and the drain voltage of N2\_1 is equal to VT. The time that the voltage of c reaches [0.5×VDD+VT] can be implied with [T(CK) + TDR(CKÆQ) − 0.625×TR(Q) ].

Fig. 13. The illustration of the first assumption to imply the timing information of internal

Fig. 14. The illustration of the second assumption to imply the timing information of internal

internal signals (cn and c) with approximate timing information.

**3.3.1 Only clock pin is changed** 

Fig. 13.

node (c).

nodes (cn) and (c).

In this case, the clock pin CK is stable and only the data pin D is changed. The supply current is generated by the setup block only. If CK is logic-1, the gate G3 is turned off such that the whole cell has no switching current. When CK is logic-0, the current waveform is determined by whether the data pin D is rising or falling. Because the timing information of the internal nodes N1\_1 and N1\_2 are not stored in the library, two assumptions are made in this case to rebuild the approximate voltage waveforms of N1\_1 and N1\_2.

Library-Based Gate-Level Current Waveform Modeling for Dynamic Supply Noise Analysis 197

*VDD I T T* ×

In this case, the clock pin has an active edge, the data pin is stable, and the output Q is evaluated. Both the clock generator and the evaluation block generate supply currents. Therefore, the current waveform is composed of two triangular waveforms in this case. The first current waveform of the clock generator is discussed in Sect. 3.3.1. It is focus on how to

Figure 16 illustrates the rebuilt signals of the evaluation block when output Q is rising. First, using the rebuilt internal signal c in Sect. 3.1.1, the time that N2\_1 starts to discharge can be obtained when the voltage of node c reaches VT. Second, T(Q) - 0.625 × TR(Q) implies the time that N2\_1 reaches 0.5×VDD by the assumption of composite logic cells. Then, the internal waveform of N2\_1 can be rebuilt. Third, T(QN) - 0.625 × TF(QN) implies the time that N2\_2 reaches 0.5×VDD by the assumption of composite logic cells, which helps to rebuild the internal waveform of N2\_2. After rebuilding the internal signals of the evaluation block, the similar approach for composite logic cells can be used to generate the

When the output Q is falling, the time when c reaches VT is defined as the start time of N2\_1 because the gate G6 starts to transition when c reaches VT. Then, changing TR(Q) and TF(QN) to TF(Q) and TR(QN) respectively, the same approach for the Q rising case can be

With the two internal waveforms of N2\_1 and N2\_2, TSTART of the evaluation block is defined as the earliest start time of N2\_1 and N2\_2. TEND of the evaluation block is defined as the time that both Q and QN complete their transitions. TPEAK can be calculated by the waveforms of internal nodes. The consumed internal energy of the evaluation block is the internal energy of total DFF minus the internal energy of the clock generator obtained in Sect. 3.3.1. After adding the energy of the output loading, the total triangle area of the evaluation block and the IPEAK of this block can be obtained. Finally, combining the waveform of the evaluation block with the waveform of the clock generator calculated in

*PEAK*

estimate the second triangular waveform of the evaluation block in this section.

Fig. 16. The signals in a DFF when Q is rising with active clock edge.

used to rebuild the internal signals when the output Q is falling.

**3.3.3 Output changed with clock active edge** 

composite triangular waveform of this DFF.

⇒ = <sup>−</sup>

2 *INT*

*E*

*END START*

\_1 \_2 {, } ⇒ = *T avg T T END END st END nd* (23)

(24)

The first assumption is that the data propagation time from the input D to the internal node N1\_1 equals to the setup time of this DFF. Because the definition of setup time is the minimum time that input data must be stable before clock arriving, it can be viewed as the time that the data has been propagated to N1\_1 to enter the first latch.

The second assumption is that the node N1\_2 will become stable before the gate G6 is turned on to allow the data to enter the second latch successfully. Because N2\_1 is discharging in the D rising case, N1\_2 must reach VDD when the voltage of the node c achieves VT. TC(VT) is defined to express the duration time between V(CK)=0.5×VDD and V(c)=VT. Following these assumptions, the time that N1\_1 reaches 50% VDD and the time that N1\_2 reaches VDD can be obtained. Then, following the same assumption of composite cells, the time that N1\_1 reaches 50% VDD is the time that N1\_2 reaches 0. The voltage waveforms of N1\_1 andN1\_2 can be rebuilt as shown in Fig. 15.

Fig. 15. The parameters of a DFF when only D is rising.

In the D falling case, TR(D) and TSR(D) are changed to TF(D) and TSF(D), respectively. EINT is changed from the rising energy to the falling one. With the two internal waveforms of N1\_1 and N1\_2, the triangle parameters can be determined by the same approach for composite cells. Finally, the detailed corollary is shown as follows.

$$TC(VT) \colon TD(\{V(CK) = 0.5 \times VDD\} \to \{V(\mathcal{c}) = VT\})$$

**D Rising Case** 

$$\begin{aligned} D(t) &= \{ (T(D), 0.5 \times VDD), (T(D) - 0.625 \times TR(D), 0) \} \\ N1\\_1(t) &= \{ (T(D), VDD), (T(D) + TSR(D), 0.5 \times VDD) \} \\ N1\\_2(t) &= \{ (T(D) + TSR(D), 0), (T(D) + TSR(D) + TC(VT), VDD) \} \end{aligned}$$

**D Falling Case** 

$$\begin{aligned} D(t) &= \{ (T(D), 0.5 \times VDD), (T(D) - 0.625 \times TF(D), VDD) \} \\ N1\\_1(t) &= \{ (T(D), 0), (T(D) + TSF(D), 0.5 \times VDD) \} \\ N1\\_2(t) &= \{ (T(D) + TSF(D), VDD), (T(D) + TSF(D) + TC(VT), 0) \} \end{aligned}$$

$$t \Longrightarrow T\_{\text{STAR}T} = \text{avg}\left\{ T\_{\text{STAR}T\\_1\omega}, T\_{\text{STAR}T\\_2\omega} \right\} \tag{21}$$

$$T\_1 \Longrightarrow T\_{PEAK} = a \text{vg} \left\{ T\_{PEAK\\_1sr}, T\_{PEAK\\_2nd} \right\} \tag{22}$$

$$T\_{\rm{END}} = \text{avg}\left\{ T\_{\rm{ED}\_{\\_1\text{M}}}, T\_{\rm{END\\_2ad}} \right\} \tag{23}$$

$$\implies I\_{PEAK} = \frac{2 \times \frac{E\_{INT}}{VDD}}{T\_{END} - T\_{START}} \tag{24}$$

#### **3.3.3 Output changed with clock active edge**

196 VLSI Design

The first assumption is that the data propagation time from the input D to the internal node N1\_1 equals to the setup time of this DFF. Because the definition of setup time is the minimum time that input data must be stable before clock arriving, it can be viewed as the

The second assumption is that the node N1\_2 will become stable before the gate G6 is turned on to allow the data to enter the second latch successfully. Because N2\_1 is discharging in the D rising case, N1\_2 must reach VDD when the voltage of the node c achieves VT. TC(VT) is defined to express the duration time between V(CK)=0.5×VDD and V(c)=VT. Following these assumptions, the time that N1\_1 reaches 50% VDD and the time that N1\_2 reaches VDD can be obtained. Then, following the same assumption of composite cells, the time that N1\_1 reaches 50% VDD is the time that N1\_2 reaches 0. The voltage

In the D falling case, TR(D) and TSR(D) are changed to TF(D) and TSF(D), respectively. EINT is changed from the rising energy to the falling one. With the two internal waveforms of N1\_1 and N1\_2, the triangle parameters can be determined by the same approach for

*TC VT TD V CK VDD V c VT* ( ) : ([ ( ) 0.5 ] [ ( ) ]) = ×→=

1\_ 2( ) {( ( ) ( ),0),( ( ) ( ) ( ), )}

1\_ 2( ) {( ( ) ( ), ),( ( ) ( ) ( ),0)}

\_1 \_ 2 {, } ⇒ = *T avg T T START START st START nd* (21)

\_1 \_2 {, } ⇒ = *T avg T T PEAK PEAK st PEAK nd* (22)

*N t T D TSR D T D TSR D TC VT VDD*

( ) {( ( ),0.5 ),( ( ) 0.625 ( ),0)} 1\_1( ) {( ( ), ),( ( ) ( ),0.5 )}

= +× =+ + +

( ) {( ( ),0.5 ),( ( ) 0.625 ( ), )} 1\_1( ) {( ( ),0),( ( ) ( ),0.5 )}

*N t T D TSF D VDD T D TSF D TC VT*

= + + +

*D t T D VDD T D TF D VDD N t T D T D TSF D VDD*

*D t T D VDD T D TR D N t T D VDD T D TSR D VDD*

= × −×

= × −× = +×

time that the data has been propagated to N1\_1 to enter the first latch.

waveforms of N1\_1 andN1\_2 can be rebuilt as shown in Fig. 15.

Fig. 15. The parameters of a DFF when only D is rising.

**D Rising Case** 

**D Falling Case** 

composite cells. Finally, the detailed corollary is shown as follows.

In this case, the clock pin has an active edge, the data pin is stable, and the output Q is evaluated. Both the clock generator and the evaluation block generate supply currents. Therefore, the current waveform is composed of two triangular waveforms in this case. The first current waveform of the clock generator is discussed in Sect. 3.3.1. It is focus on how to estimate the second triangular waveform of the evaluation block in this section.

Figure 16 illustrates the rebuilt signals of the evaluation block when output Q is rising. First, using the rebuilt internal signal c in Sect. 3.1.1, the time that N2\_1 starts to discharge can be obtained when the voltage of node c reaches VT. Second, T(Q) - 0.625 × TR(Q) implies the time that N2\_1 reaches 0.5×VDD by the assumption of composite logic cells. Then, the internal waveform of N2\_1 can be rebuilt. Third, T(QN) - 0.625 × TF(QN) implies the time that N2\_2 reaches 0.5×VDD by the assumption of composite logic cells, which helps to rebuild the internal waveform of N2\_2. After rebuilding the internal signals of the evaluation block, the similar approach for composite logic cells can be used to generate the composite triangular waveform of this DFF.

Fig. 16. The signals in a DFF when Q is rising with active clock edge.

When the output Q is falling, the time when c reaches VT is defined as the start time of N2\_1 because the gate G6 starts to transition when c reaches VT. Then, changing TR(Q) and TF(QN) to TF(Q) and TR(QN) respectively, the same approach for the Q rising case can be used to rebuild the internal signals when the output Q is falling.

With the two internal waveforms of N2\_1 and N2\_2, TSTART of the evaluation block is defined as the earliest start time of N2\_1 and N2\_2. TEND of the evaluation block is defined as the time that both Q and QN complete their transitions. TPEAK can be calculated by the waveforms of internal nodes. The consumed internal energy of the evaluation block is the internal energy of total DFF minus the internal energy of the clock generator obtained in Sect. 3.3.1. After adding the energy of the output loading, the total triangle area of the evaluation block and the IPEAK of this block can be obtained. Finally, combining the waveform of the evaluation block with the waveform of the clock generator calculated in

Library-Based Gate-Level Current Waveform Modeling for Dynamic Supply Noise Analysis 199

increased total resistance. Therefore, the RC charging model is used to calculate the

REFF represents the effective resistance of the cell. CEFF represents the effective capacitance of the cell. EINT and ELOAD represent the energy consumption caused by the cell and its output loading. In the output rising case, the CEFF is approximated by the total energy divided by supply voltage. Assume TR(Y)ORG represents the original transition time in LIB files. TR(Y)ADJ represents the adjusted transition time in the output rising case. The detailed corollary and the adjustment formula can be derived as follows, in which the increased term is related to the known variables (RWIRE, CEFF) only. In the output falling case, the transition time is not changed because the current does not flow through the supply resistor. If there is

a resistor in current path to ground, similar approach can be used to adjust TF(Y).

Fig. 17. The circuit structure of a simple cell (**INVETER**) with a supply resistor in (a) the

*E E <sup>C</sup>*

*TR Y R C*

<sup>⎪</sup> =× × <sup>⎩</sup>

= × × +× × = +× ×

Fig. 18. The circuit structure of a composite cell (**BUFFER**) with a supply resistor in (a) the

*INT LOAD*

*VDD*

*ORG EFF EFF*

*EFF EFF WIRE EFF ORG WIRE EFF*

(29)

*R C R C TR Y R C*

( ) ln 9

*EFF*

ln9 ln 9 ( ) ln 9

<sup>⎧</sup> <sup>+</sup> <sup>⎪</sup> <sup>=</sup> <sup>⎨</sup>

increased transition time caused by the supply resistor.

output rising case (b) the output falling case

output rising case (b) the output falling case

( ) ln 9 ( )

*TR T RR C*

*ADJ EFF WIRE EFF*

= ×+ ×

Sect. 3.3.1, the supply current waveform of the DFF in this case is obtained. The detailed formulas to construct the current waveform in this case are summarized as follows.

$$TC(VT) \colon TD(\{V(CK) = 0.5 \times VDD\} \to \{V(\mathcal{c}) = VT\})$$

#### **Q Rising Case**

$$\begin{aligned} N2\\_1(t) &= \langle (T(CK) + TC(VT), VDD), (T(Q) - 0.625 \times TR(Q), 0.5 \times VDD) \rangle \\ N2\\_2(t) &= \langle (T(Q) - 0.625 \times TR(Q), 0), (T(QN) - 0.625 \times TF(QN), 0.5 \times VDD) \rangle \\ Q(t) &= \langle (T(Q), 0.5 \times VDD), (T(Q) - 0.625 \times TR(Q), 0) \rangle \\ QN(t) &= \langle (T(QN), 0.5 \times VDD), (T(QN) - 0.625 \times TF(QN), VDD) \rangle \end{aligned}$$

#### **Q Falling Case**

$$\begin{aligned} N2\_{-1}(t) &= \{ (TCN(VDD-VT), 0), (T(Q)-0.625 \times TF(Q), 0.5 \times VDD) \} \\ N2\_{-2}(t) &= \{ (T(Q)-0.625 \times TF(Q), VDD), (T(QN)-0.625 \times TR(QN), 0.5 \times VDD) \} \\ Q(t) &= \{ (T(Q), 0.5 \times VDD), (T(Q)+0.625 \times TF(Q), 0) \} \\ QN(t) &= \{ (T(QN), 0.5 \times VDD), (T(QN)+0.625 \times TR(QN), VDD) \} \end{aligned}$$

$$\implies T\_{\text{START}} = TC(VT) \tag{25}$$

$$T\_{PEAK} = \arg \left\{ T\_{PEAK\_{\\_ {\{G\\_1\\_1\}}}}, T\_{PEAK\_{\\_ {\{G\\_2\}}}}, T\_{PEAK\_{\\_ {\{G\\_2\}}}} \right\} \tag{26}$$

$$T\_{\rm{END}} = \arg \left\{ T\_{\rm{ED\_{\\_{-}}(G\mathbb{2}\_{-}4)}, T\_{\rm{ED\_{-}}(G\mathbb{2}\_{-}9)}} \right\} \tag{27}$$

$$\implies I\_{PEAK} = \frac{2 \times (\frac{E\_{INT} - E\_{CrackGionwater}}{VDD} + Load(Q) \times VDD)}{T\_{END} - T\_{STRF}} \tag{28}$$

#### **4. IR-Drop aware library adjustment methods**

In this section, an analytical library adjustment approach is proposed to consider the effects of the supply resistors without extra characterization. The timing and power information stored in LIB file can be modified to reflect the effect of the supply resistor by the proposed equations. Therefore, the proposed gate-level supply current estimation method can obtain the accurate waveforms with IR-drop effects. Most importantly, this method can be easily embedded into present design flow to improve the accuracy of gate-level IR-drop analysis and provide designers a fast solution to consider IR-drop effect at early design stages. In this section, the adjustment methods of combination cells, simple logic and composite logic cells are discussed first in Section 4.1. Then, in Section 4.2, the methods of sequential cell are presented. Finally, the adjustment methods of activity files (VCD) are explained in Section 4.3.

#### **4.1 Timing and power adjustment of combination cells**

#### **4.1.1 Output transition time**

Figure 17 illustrates a simple cell with a supply resistor. In the output rising case, the supply current flows through the supply resistor, which increases the transition time due to the

Sect. 3.3.1, the supply current waveform of the DFF in this case is obtained. The detailed

*TC VT TD V CK VDD V c VT* ( ) : ([ ( ) 0.5 ] [ ( ) ]) = ×→=

2 \_1( ) {( ( ) ( ), ),( ( ) 0.625 ( ),0.5 )} 2 \_ 2( ) {( ( ) 0.625 ( ),0),( ( ) 0.625 ( ),0.5 )}

= + − × × = −× −× ×

*N t T CK TC VT VDD T Q TR Q VDD N t T Q TR Q T QN TF QN VDD*

= × −× *DD*)}

2 \_1( ) {( ( ),0),( ( ) 0.625 ( ),0.5 )}

= − −× ×

= × +× *D*)}

*N t TCN VDD VT T Q TF Q VDD*

2 \_ 2( ) {( ( ) 0.625 ( ), ),( ( ) 0.625 ( ),0.5 )}

= −× −× ×

2 ( () ) *INT ClockGenerator*

*E E Load Q VDD VDD <sup>I</sup> T T*

In this section, an analytical library adjustment approach is proposed to consider the effects of the supply resistors without extra characterization. The timing and power information stored in LIB file can be modified to reflect the effect of the supply resistor by the proposed equations. Therefore, the proposed gate-level supply current estimation method can obtain the accurate waveforms with IR-drop effects. Most importantly, this method can be easily embedded into present design flow to improve the accuracy of gate-level IR-drop analysis and provide designers a fast solution to consider IR-drop effect at early design stages. In this section, the adjustment methods of combination cells, simple logic and composite logic cells are discussed first in Section 4.1. Then, in Section 4.2, the methods of sequential cell are presented. Finally,

Figure 17 illustrates a simple cell with a supply resistor. In the output rising case, the supply current flows through the supply resistor, which increases the transition time due to the

<sup>−</sup> × +×

*END START*

( ) ⇒ = *T TC VT START* (25)

(28)

\_( 2 \_1) \_( 2\_ 2) \_( 2 \_ 5) {, , } ⇒ = *T avg T T T PEAK PEAK G PEAK G PEAK G* (26)

\_( 2 \_ 4) \_( 2 \_ 5) {,} ⇒ = *T avg T T END END G END G* (27)

*N t T Q TF Q VDD T QN TR QN VDD*

formulas to construct the current waveform in this case are summarized as follows.

( ) {( ( ),0.5 ),( ( ) 0.625 ( ),0)} ( ) {( ( ),0.5 ),( ( ) 0.625 ( ),

*QN t T QN VDD T QN TF QN V*

*Q t T Q VDD T Q TR Q*

( ) {( ( ),0.5 ),( ( ) 0.625 ( ),0)} ( ) {( ( ),0.5 ),( ( ) 0.625 ( ),

*QN t T QN VDD T QN TR QN VD*

⇒ = <sup>−</sup>

the adjustment methods of activity files (VCD) are explained in Section 4.3.

**4.1 Timing and power adjustment of combination cells** 

**4.1.1 Output transition time** 

*Q t T Q VDD T Q TF Q*

= × +×

*PEAK*

**4. IR-Drop aware library adjustment methods** 

= × −×

**Q Rising Case** 

**Q Falling Case** 

increased total resistance. Therefore, the RC charging model is used to calculate the increased transition time caused by the supply resistor.

REFF represents the effective resistance of the cell. CEFF represents the effective capacitance of the cell. EINT and ELOAD represent the energy consumption caused by the cell and its output loading. In the output rising case, the CEFF is approximated by the total energy divided by supply voltage. Assume TR(Y)ORG represents the original transition time in LIB files. TR(Y)ADJ represents the adjusted transition time in the output rising case. The detailed corollary and the adjustment formula can be derived as follows, in which the increased term is related to the known variables (RWIRE, CEFF) only. In the output falling case, the transition time is not changed because the current does not flow through the supply resistor. If there is a resistor in current path to ground, similar approach can be used to adjust TF(Y).

Fig. 17. The circuit structure of a simple cell (**INVETER**) with a supply resistor in (a) the output rising case (b) the output falling case

$$\begin{cases} \begin{aligned} C\_{EFF} &= \frac{E\_{INT} + E\_{LOAD}}{VDD} \\ \end{aligned} \end{cases}$$

$$\begin{aligned} \begin{aligned} TR(Y)\_{\alpha \& G} &= \frac{\ln 9 \times R\_{EFF} \times C\_{EFF}}{} \end{aligned}$$

$$\begin{aligned} \text{TR}(T)\_{\text{ADU}} &= \ln 9 \times (R\_{\text{EFF}} + R\_{\text{WRE}}) \times C\_{\text{EFF}} \\ &= \ln 9 \times R\_{\text{EFF}} \times C\_{\text{EFF}} + \ln 9 \times R\_{\text{WRE}} \times C\_{\text{EFF}} = \text{TR}(Y)\_{\text{ORG}} + \ln 9 \times R\_{\text{WRE}} \times C\_{\text{EFF}} \end{aligned} \tag{29}$$

Fig. 18. The circuit structure of a composite cell (**BUFFER**) with a supply resistor in (a) the output rising case (b) the output falling case

Library-Based Gate-Level Current Waveform Modeling for Dynamic Supply Noise Analysis 201

*EFF*

*R VDD <sup>R</sup> E TE RR RR*

formulas in the timing and internal energy are discussed in the following subsections.

( ) ( ) ( )

*INT ADJ SC INT ORG EFF WIRE EFF WIRE*

Only the output Q rising case is to explain the adjusted formulas because the formulas fir other cases can be derived by similar ways. One difficulty of the adjustment of DFF cases is to estimate the effective capacitance of the gate because the internal capacitance is unavailable. In this work, the internal energy is used to approximate the effective capacitance. The other difficulty is the adjustment of effective supply resistance because more than one gates switch in the DFF. Therefore, the simple parallel connection formula is applied first to approximate the effective supply resistance seen by each switching gate. The details of the adjusted

Only the increased transition time caused by the output stage (G9) should be added to adjust the output transition time of output Q. The EINT (CKRISEÆQRISE) represents the internal energy consumption stored in the library for the output Q rising case when CK actives, which is composed of the energy of G1, G2, G6, G7, G9 and G10. The EINT(CKRISE) represents the internal energy consumption of G1 and G2 when only CK actives. It implies that the energy consumption of G6, G7, G10 and G9 in Fig.19 can be calculated by EINT (CKRISEÆQRISE)-EINT(CKRISE). Therefore, the CEFF of the path through G9 can be approximated as a half of EINT (CKRISEÆQRISE)- EINT(CKRISE) divided by VDD because the

When measuring the output transition time, three current paths travel through the RWIRE. Assume the three inverters G2, G7 and G9 have similar sizes, the equivalent supply resistor of each cell must be three times the lumped supply resistor (RWIRE) according to the parallel connection formula. Therefore, the adjusted formula is modified a little bit as follows. The falling time of QN (TF(QN)) is not necessary to be adjusted because it is a falling gate. The adjustment formulas for the output transition time in output Q falling case are also listed as

( )()

( )()

*INT RISE FALL INT RISE EFF LOAD EFF WIRE*

*E CK Q E CK C C VDD R R*

*ADJ ORG WIRE EFF*

= +× ×

*INT RISE RISE INT RISE EFF LOAD EFF WIRE*

*E CK Q E CK C C VDD R R*

2 3

<sup>⎧</sup> → − <sup>⎪</sup> <sup>=</sup> <sup>+</sup> <sup>⎨</sup> <sup>×</sup>

*ADJ ORG WIRE EFF*

2 3

<sup>⎧</sup> → − <sup>⎪</sup> <sup>=</sup> <sup>+</sup> <sup>⎨</sup> <sup>×</sup>

= +× ×

follows, which can be derived by similar way as in the output Q rising case.

( ) ( ) ln 9 () ()

⎩ = ×

*TF QN TF QN*

() ()

*TF Q TF Q*

=

⎪

⎪

*ADJ ORG*

( ) ( ) ln 9

*TR QN TR QN R C*

*ADJ ORG*

⎩ = × =

*TR Q TR Q R C*

= ×= × + +

*EFF*

(33)

(34)

(35)

( )

**4.2.1 Output transition time** 

**4.2 Timing and power adjustment of sequential elements** 

energy are separated into two rising gates (G7 and G9).

*INT ORG SC SC SC*

=×= ×

*VDD E IT T*

Figure 18 illustrates a composite cell with a supply resistor. Typically, this kind of cells is composed of multiple stages of simple cells. In Fig.18(a), the supply current flows through the second stage in the output rising case. The first stage is in the output falling case. Therefore, only the increased transition time of the second stage should be considered in the output rising case. Applying the same method for the simple logic cells on the second stage can obtain the increased transition time. In the output falling case, the output transition time is still not changed because the current does not flow through the second stage. Only the propagation delay may be changed in such case, which is discussed in the next section.

#### **4.1.2 Propagation delay time**

According to the same model shown in Fig.18, the adjustment method of the propagation time for simple logic cells can be derived. Similarly, only the increased propagation time in the output rising case should be considered to adjust the original timing information. The adjustment formulas are listed as follows, in which the increased term is related to the known variables (RWIRE, CEFF) only.

$$\begin{cases} \begin{aligned} C\_{EFF} &= \frac{E\_{INT} + E\_{LOAD}}{VDD} \\ TDR(Y)\_{ORG} &= \underline{-\ln 0.S} \times R\_{EFF} \times C\_{EFF} \end{aligned} \end{cases}$$

$$\begin{aligned} \text{TDR}(T)\_{\text{ADU}} &= (-\ln 0.\text{S}) \times (R\_{\text{EFF}} + R\_{\text{WRE}}) \times C\_{\text{EFF}} \\ &= (-0.\text{S}) \times R\_{\text{EFF}} \times C\_{\text{EFF}} + (-\ln 0.\text{S}) \times R\_{\text{WRE}} \times C\_{\text{EFF}} = \text{TDR}(Y)\_{\text{ORG}} + (-\ln 0.\text{S}) \times R\_{\text{WRE}} \times C\_{\text{EFF}} \end{aligned} \tag{30}$$

For composite logic cells, the adjustment of the propagation time in the output rising case is the same with the simple logic cell as shown in Fig.18 (a). In the output falling case shown in Fig.18(b), CEFF is the internal capacitance CINT. This internal capacitance can be approximated as the EINT divided by the supply voltage because the operation current flows through the cell only. The adjustment formulas are listed as follows, in which the increased term is related the known variables only.

$$C\_{\rm EFF} = \frac{E\_{\rm NT} + E\_{\rm LOAD}}{VDD} \Rightarrow TDR(X \rightarrow Y)\_{\rm nLV} = TDR(X \rightarrow Y)\_{\rm nGC} + (-\ln 0.5) \times R\_{\rm wRE} \times C\_{\rm EFF} \tag{31}$$

$$C\_{\rm EFF} = \frac{E\_{\rm NT}}{VDD} \Longrightarrow TDR(X \to Y)\_{\rm nLV} = TDR(X \to Y)\_{\rm nRV} + (-\ln 0.5) \times R\_{\rm WRE} \times C\_{\rm EFF} \tag{32}$$

#### **4.1.3 Internal energy**

Assume EINT(ORG) represents the internal energy stored in standard libraries, and EINT(ADJ) represents the modified internal energy. This internal energy can be viewed as the shortcircuit energy by ignoring the effect of internal capacitances. Therefore, EINT(OLD) can be expressed as the short-circuit current (ISC) times the duration of the short-circuit current (TSC). Since ISC can be rewritten as VDD/ RINT, the EINT(ADJ) can be derived by the ratio of REFF and RADJ, as shown in the following equations. Please be noted that the REFF can be calculated from the original propagation time because the short-circuit current happens at the logic transition period.

$$E\_{INT(ORG)} = I\_{sc} \times T\_{sc} = \frac{VDD}{R\_{EF}} \times T\_{sc} \tag{33}$$

$$E\_{INT(ADJ)} = \frac{VDD}{(R\_{EF} + R\_{WRE})} \times T\_{sc} = \frac{R\_{EF}}{R\_{EF} + R\_{WRE}} \times E\_{INT(ORG)}$$

#### **4.2 Timing and power adjustment of sequential elements**

Only the output Q rising case is to explain the adjusted formulas because the formulas fir other cases can be derived by similar ways. One difficulty of the adjustment of DFF cases is to estimate the effective capacitance of the gate because the internal capacitance is unavailable. In this work, the internal energy is used to approximate the effective capacitance. The other difficulty is the adjustment of effective supply resistance because more than one gates switch in the DFF. Therefore, the simple parallel connection formula is applied first to approximate the effective supply resistance seen by each switching gate. The details of the adjusted formulas in the timing and internal energy are discussed in the following subsections.

#### **4.2.1 Output transition time**

200 VLSI Design

Figure 18 illustrates a composite cell with a supply resistor. Typically, this kind of cells is composed of multiple stages of simple cells. In Fig.18(a), the supply current flows through the second stage in the output rising case. The first stage is in the output falling case. Therefore, only the increased transition time of the second stage should be considered in the output rising case. Applying the same method for the simple logic cells on the second stage can obtain the increased transition time. In the output falling case, the output transition time is still not changed because the current does not flow through the second stage. Only the propagation delay may be changed in such case, which is discussed in the next section.

According to the same model shown in Fig.18, the adjustment method of the propagation time for simple logic cells can be derived. Similarly, only the increased propagation time in the output rising case should be considered to adjust the original timing information. The adjustment formulas are listed as follows, in which the increased term is related to the

*INT LOAD*

*ORG EFF EFF*

*EFF EFF WIRE EFF ORG WIRE EFF*

(30)

(31)

(32)

*R C R C TDR Y R C*

*VDD*

( ) ln 0.5

=− × × +− × × = +− × ×

( ) ( ) ( ln 0.5) *INT LOAD EFF ADJ ORG WIRE EFF E E <sup>C</sup> TDR X Y TDR X Y R C*

( ) ( ) ( ln 0.5) *INT EFF ADJ ORG WIRE EFF <sup>E</sup> <sup>C</sup> TDR X Y TDR X Y R C*

= ⇒ → = → +− × ×

= ⇒ → = → +− × ×

Assume EINT(ORG) represents the internal energy stored in standard libraries, and EINT(ADJ) represents the modified internal energy. This internal energy can be viewed as the shortcircuit energy by ignoring the effect of internal capacitances. Therefore, EINT(OLD) can be expressed as the short-circuit current (ISC) times the duration of the short-circuit current (TSC). Since ISC can be rewritten as VDD/ RINT, the EINT(ADJ) can be derived by the ratio of REFF and RADJ, as shown in the following equations. Please be noted that the REFF can be calculated from the original propagation time because the short-circuit current happens at

<sup>⎪</sup> =− × × <sup>⎩</sup>

*E E <sup>C</sup>*

*TDR Y R C*

For composite logic cells, the adjustment of the propagation time in the output rising case is the same with the simple logic cell as shown in Fig.18 (a). In the output falling case shown in Fig.18(b), CEFF is the internal capacitance CINT. This internal capacitance can be approximated as the EINT divided by the supply voltage because the operation current flows through the cell only. The adjustment formulas are listed as follows, in which the increased

*EFF*

<sup>⎧</sup> <sup>+</sup> <sup>⎪</sup> <sup>=</sup> <sup>⎨</sup>

( 0.5) ( ln 0.5) ( ) ( ln 0.5)

**4.1.2 Propagation delay time** 

known variables (RWIRE, CEFF) only.

term is related the known variables only.

*VDD* +

*VDD*

**4.1.3 Internal energy** 

the logic transition period.

( ) ( ln 0.5) ( )

*TDR T RR C*

*ADJ EFF WIRE EFF*

= − ×+ ×

Only the increased transition time caused by the output stage (G9) should be added to adjust the output transition time of output Q. The EINT (CKRISEÆQRISE) represents the internal energy consumption stored in the library for the output Q rising case when CK actives, which is composed of the energy of G1, G2, G6, G7, G9 and G10. The EINT(CKRISE) represents the internal energy consumption of G1 and G2 when only CK actives. It implies that the energy consumption of G6, G7, G10 and G9 in Fig.19 can be calculated by EINT (CKRISEÆQRISE)-EINT(CKRISE). Therefore, the CEFF of the path through G9 can be approximated as a half of EINT (CKRISEÆQRISE)- EINT(CKRISE) divided by VDD because the energy are separated into two rising gates (G7 and G9).

When measuring the output transition time, three current paths travel through the RWIRE. Assume the three inverters G2, G7 and G9 have similar sizes, the equivalent supply resistor of each cell must be three times the lumped supply resistor (RWIRE) according to the parallel connection formula. Therefore, the adjusted formula is modified a little bit as follows. The falling time of QN (TF(QN)) is not necessary to be adjusted because it is a falling gate. The adjustment formulas for the output transition time in output Q falling case are also listed as follows, which can be derived by similar way as in the output Q rising case.

$$\begin{cases} C\_{EF} = \frac{E\_{NT}(CK\_{R\&E} \rightarrow Q\_{R\&E}) - E\_{NT}(CK\_{R\&E})}{2 \times VDD} + C\_{LOAD} \\ \text{ } & R\_{EF} = 3 \times R\_{W\&E} \end{cases} \tag{34}$$

$$\begin{aligned} TR(Q)\_{AD} &= TR(Q)\_{OR} + \ln 9 \times R\_{W\&E} \times C\_{EF} \\ TF(QN)\_{AD} &= TF(QN)\_{OR} \end{aligned} \tag{35}$$

$$\begin{cases} C\_{EF} = \frac{E\_{NT}(CK\_{R\&E} \rightarrow Q\_{EIL}) - E\_{NT}(CK\_{R\&E})}{2 \times VDD} + C\_{LOAD} \\ R\_{EF} &= 3 \times R\_{W\&E} \end{cases} \tag{35}$$

$$\begin{aligned} \left( \operatorname{TR}(\operatorname{\mathcal{Q}N}) \right)\_{\operatorname{ADU}} &= \operatorname{TR}(\operatorname{\mathcal{Q}N})\_{\operatorname{\mathcal{O}\mathcal{B}G}} + \underbrace{\ln \operatorname{9} \times R\_{\operatorname{WRE}} \times C\_{\operatorname{EFF}}}\_{\operatorname{EFF}} \end{aligned}$$

Library-Based Gate-Level Current Waveform Modeling for Dynamic Supply Noise Analysis 203

The propagation delay time TDF(DÆN1\_2)ADJ and TDR(CKÆc)ADJ can be calculated with the similar method for the propagation delay time. Because there are two current paths in this case as shown in Fig.20, the equivalent supply resistor of each cell is two times RWIRE.

( 1\_ 2) ( 1\_ 2) ( ln 0.5) ( 3))

*ADJ ORG EFF EFF*

(39)

(40)

( ) ( ) ( ln 0.5) ( 2))

*TDR CK c TDR CK c R CG*

*TDF D N TDF D N R CG*

→ = → +− × × → = → +− × ×

*ADJ ORG EFF EFF*

Therefore, the formula of the adjusted setup time TSR(D)ADJ can be obtained as follows. The setup time in the D falling case can be obtained by the similar way. The formula is also listed

> ( ) ( 1\_ 2) ( ) ( ) ( ln 0.5) [ ( 3) ( 2)] ( ) ( 1\_ 2) ( ) ( ) ( ln 0.5) [ ( 4) ( 2)]

The internal energy of DFF cannot be separated to each cell. Therefore, the entire DFF is viewed as a super-gate to adjust its internal energy. The same formulas of the composite

During gate-level simulation, the signal events are recorded in activity files (.vcd). Figure 21(a) shows the ideal timing diagram of four events, T(A), T(B), T(C), T(Y). With non-ideal

*TSR D TDF D N TDR CK c TSR D R CGCG TSF D TDR D N TDR CK c TSF D R CG CG*

= +− × × −

= +− × × −

*ADJ ADJ ADJ*

= → −→

=→ − →

*EFF EFF EFF ADJ ADJ ADJ*

*EFF EFF EFF*

Fig. 20. The internal status of a DFF when D is setting up.

( ) ( 3)

*E D C G*

*E CK C G*

*INT RISE*

*VDD*

*INT RISE*

*VDD*

logic cells are used directly to adjust the internal energy of DFF.

**4.3 Timing correction of cell switching activities** 

( ) ( 2)

2

*R R*

*EFF WIRE*

The formulas are listed as follows.

*EFF*

<sup>⎧</sup> <sup>=</sup> <sup>⎪</sup>

⎨ ==

<sup>⎪</sup> = × <sup>⎪</sup>

*EFF*

⎪ ⎪

⎪

⎩

as follows.

**4.2.4 Internal energy** 

( ) ( 1\_ 2) ( ) *TSR D TDF D N TDR CK c ORG* = → −→ *ORG ORG* (38)

Fig. 19. The current flows of the DFF in the output rising case

#### **4.2.2 Propagation delay time**

In the signal propagation path from CK to Q, only G2 and G9 are rising in the output Q rising case. Therefore, the increased delay time of the two gates are added by the similar method shown in Section 4.1.2 to adjust the CK to Q delay of DFF circuits. The effective capacitance of G2, CEFF(G2), can be approximated as the EINT(CKRISE) divided by VDD. The effective capacitance of G9, CEFF(G9), and the REFF of G2 and G9 are obtained by the same approach for the output transition time. The adjusted propagation delay time TDR(CKÆQ)ADJ can be calculated by the following formulas, in which the increased term is related to known variables only.

$$\begin{cases} \begin{aligned} C\_{\rm{EF}} \left( G2 \right) &= \frac{E\_{\rm{RT}} \left( C K\_{\rm{RE}} \right)}{VDD} \\ C\_{\rm{EFF}} \left( G9 \right) &= \frac{E\_{\rm{RT}} \left( C K\_{\rm{REE}} \to Q\_{\rm{REE}} \right) - E\_{\rm{RT}} \left( C K\_{\rm{REE}} \right)}{2 \times VDD} + C\_{\rm{LOAD}} \\ R\_{\rm{EFF}} &= 3 \times R\_{\rm{minE}} \end{aligned} \tag{36}$$
  $TDR(CK \to Q)\_{\rm{ADU}} = TDR(CK \to Q)\_{\rm{DDG}} + \left( - \ln 0.5 \right) \times R\_{\rm{EFF}} \times \left( C\_{\rm{EFF}} \left( G2 \right) + C\_{\rm{EFF}} \left( G9 \right) \end{aligned}$ 

The propagation delay time of the output QN TDF(CKÆQN)ADJ can be calculated by the similar approach of TDR(CKÆQ)ADJ. The adjustment formula is listed as follows, except that G7 is used instead of G9 for different output.

$$\begin{cases} & C\_{\rm{FFF}}(G2) = \frac{E\_{\rm{nTr}}(CK\_{\rm{nEx}})}{VDD} \\\\ & C\_{\rm{EFF}}(G7) = \frac{E\_{\rm{nTr}}(CK\_{\rm{nEx}} \to Q\_{\rm{EXE}}) - E\_{\rm{nTr}}(CK\_{\rm{nEx}})}{2 \times VDD} + C\_{\rm{Lo0}} \\ & R\_{\rm{EFF}} = 3 \times R\_{\rm{wRE}} \end{cases} \tag{37}$$
 
$$\begin{bmatrix} TDF(CK \to Q)\_{\rm{ADU}} = TDF(CK \to Q)\_{\rm{nGG}} + (-\ln 0.5) \times R\_{\rm{EFF}} \times (C\_{\rm{EFF}}(G2) + C\_{\rm{EFF}}(G7)) \end{bmatrix}$$

#### **4.2.3 Setup time**

Figure 20 illustrates the internal status of a DFF when data is setting up. Following the same assumption of the setup time in Section 3, the data must reach N1\_2 before the internal node c rises to ensure that the data can enter the next stage successfully. Therefore, the setup time of the D rising case TSR(D) can be expressed as the following formula.

$$TSR(D)\_{\text{ORG}} = TDF(D \to N1\\_2)\_{\text{ORG}} - TDR(CK \to \mathfrak{c})\_{\text{ORG}} \tag{38}$$

Fig. 20. The internal status of a DFF when D is setting up.

The propagation delay time TDF(DÆN1\_2)ADJ and TDR(CKÆc)ADJ can be calculated with the similar method for the propagation delay time. Because there are two current paths in this case as shown in Fig.20, the equivalent supply resistor of each cell is two times RWIRE. The formulas are listed as follows.

$$\begin{cases} C\_{EF}(G3) = \frac{E\_{NT}(D\_{RE})}{VDD} \\ C\_{EF}(G2) = \frac{E\_{NT}(CK\_{RE5})}{VDD} \\ R\_{EF} = 2 \times R\_{\text{wRE}} \\ \end{cases}$$

$$\begin{aligned} \text{TDF}(D \to N1\\_2)\_{AD} &= \text{TDF}(D \to N1\\_2)\_{GR} + (\underline{-\ln 0.5}) \times R\_{EF} \times C\_{EF}(G3) \\ \text{TDR}(CK \to c)\_{AD} &= \text{TDR}(CK \to c)\_{BD} + (\underline{-\ln 0.5}) \times R\_{EF} \times C\_{EF}(G2) \end{aligned} \tag{39}$$

Therefore, the formula of the adjusted setup time TSR(D)ADJ can be obtained as follows. The setup time in the D falling case can be obtained by the similar way. The formula is also listed as follows.

$$\begin{aligned} &TSR(D)\_{\mathit{ADU}} = TDF(D \to N1\\_2)\_{\mathit{ADU}} - TDR(CK \to c)\_{\mathit{ADU}}\\ &= TSR(D) + (-\ln 0.5) \times R\_{EF} \times [C\_{EF}(G3) - C\_{EF}(G2)] \\ &TSF(D)\_{\mathit{ADU}} = TDR(D \to N1\\_2)\_{\mathit{ADU}} - TDR(CK \to c)\_{\mathit{ADU}} \\ &= TSF(D) + (-\ln 0.5) \times R\_{EF} \times [C\_{EF}(G4) - C\_{EF}(G2)] \end{aligned} \tag{40}$$

#### **4.2.4 Internal energy**

202 VLSI Design

In the signal propagation path from CK to Q, only G2 and G9 are rising in the output Q rising case. Therefore, the increased delay time of the two gates are added by the similar method shown in Section 4.1.2 to adjust the CK to Q delay of DFF circuits. The effective capacitance of G2, CEFF(G2), can be approximated as the EINT(CKRISE) divided by VDD. The effective capacitance of G9, CEFF(G9), and the REFF of G2 and G9 are obtained by the same approach for the output transition time. The adjusted propagation delay time TDR(CKÆQ)ADJ can be calculated by the following formulas, in which the increased term is

( ) ( ) ( ln 0.5) ( ( 2) ( 9))

( ) ( ) ( ln 0.5) ( ( 2) ( 7))

*TDF CK Q TDF CK Q R CG CG*

→ = → +− × × +

Figure 20 illustrates the internal status of a DFF when data is setting up. Following the same assumption of the setup time in Section 3, the data must reach N1\_2 before the internal node c rises to ensure that the data can enter the next stage successfully. Therefore, the setup time

*ADJ ORG EFF EFF EFF*

*TDR CK Q TDR CK Q R CG CG*

→ = → +− × × +

The propagation delay time of the output QN TDF(CKÆQN)ADJ can be calculated by the similar approach of TDR(CKÆQ)ADJ. The adjustment formula is listed as follows, except that

*ADJ ORG EFF EFF EFF*

(36)

(37)

( ) ( 2)

*INT RISE RISE INT RISE EFF LOAD EFF WIRE*

( ) ( 2)

*INT RISE RISE INT RISE EFF LOAD EFF WIRE*

*VDD*

*INT RISE*

*VDD*

( )() ( 7) <sup>2</sup> 3

*R R*

of the D rising case TSR(D) can be expressed as the following formula.

*E CK Q E CK C G <sup>C</sup>*

<sup>⎪</sup> → − <sup>⎨</sup> <sup>=</sup> <sup>+</sup> <sup>×</sup> <sup>⎪</sup>

*E CK C G*

*VDD*

*INT RISE*

*VDD*

( )() ( 9) <sup>2</sup> 3

*R R*

*E CK Q E CK C G <sup>C</sup>*

<sup>⎪</sup> → − <sup>⎨</sup> <sup>=</sup> <sup>+</sup> <sup>×</sup> <sup>⎪</sup>

*E CK C G*

*EFF*

<sup>⎧</sup> <sup>=</sup> <sup>⎪</sup>

<sup>⎪</sup> = × <sup>⎪</sup>

G7 is used instead of G9 for different output.

<sup>⎧</sup> <sup>=</sup> <sup>⎪</sup>

<sup>⎪</sup> = × <sup>⎪</sup>

*EFF*

Fig. 19. The current flows of the DFF in the output rising case

**4.2.2 Propagation delay time** 

related to known variables only.

⎪

⎩

⎪

⎩

**4.2.3 Setup time** 

The internal energy of DFF cannot be separated to each cell. Therefore, the entire DFF is viewed as a super-gate to adjust its internal energy. The same formulas of the composite logic cells are used directly to adjust the internal energy of DFF.

#### **4.3 Timing correction of cell switching activities**

During gate-level simulation, the signal events are recorded in activity files (.vcd). Figure 21(a) shows the ideal timing diagram of four events, T(A), T(B), T(C), T(Y). With non-ideal

Library-Based Gate-Level Current Waveform Modeling for Dynamic Supply Noise Analysis 205

cells are characterized in our preliminary experiments. The previous approach (Shimazaki et al., 2000) is also rebuilt in our environment and tested in the same experiments to show our improvements on accuracy. Because they did not mention how to apply their approach on

In the experiments, ISCAS'85 and ISCAS'89 benchmark circuits, which are implemented with TSMC 0.13um process, are used to test the accuracy. For each benchmark circuit, 200 random patterns are generated to trigger the circuit. After all, the average errors of the peak current and position with 200 pattern-pairs are shown in the row "eIp" of Tables 1 and 2. The standard deviation of the peak current and position with the 200 results is shown in the row "sIp" of Tables 1 and 2. The last column "AVG" in Tables 1 and 2 shows the average values of all cases. Figure 22 shows the estimated current waveforms of c7552 and

According to the results estimated by PrimeTime-PX, the CCSM libraries significantly improve the accuracy of peak current estimation. However, the cycle-accurate results are still not accurate enough for analyzing the peak power or the IR-drop noise. The estimation results of the proposed methods, which are listed in the row "GCM" of Tables 2 and 3, demonstrates that the proposed approach can provide accurate estimations on the supply current waveforms by using the same information provided in traditional LIB libraries. The average estimation errors on eIPEAK and eTPEAK are about 10% with small standard deviation. The correlation between the estimated waveforms and HSPICE waveforms is higher than 0.97, which shows the similarity between the two waveforms. Compared to the rough estimation in (Shimazaki et al., 2000), the proposed approach does have a significant improvement on the estimation accuracy. Most importantly, the proposed approach can deal with sequential circuits, which enables this approach to be applied to modern designs. The run time of the current waveform estimation for each benchmark circuit is provided in Table 3, which is measured on a XEON 3G machine with 2G RAM. The row"GCM" shows the run time of the proposed approach in seconds. The row "HSPICE" shows the run time of HSPICE simulation with the same patterns in hours. The row "Ratio"shows the ratio of the run time between HSPICE and GCM, which demonstrates a significant speed

sequential cells, only combinational circuits are compared.

s9234 as examples, which are very similar to HSPICE results.

Fig. 22. The estimation supply current waveforms of (a)c7552 (b)s9234.

improvement.

supply lines, these events will occur at different time thus incurring different current waveforms. Therefore, the modification of activity files is also proposed in this paper, as illustrated in Fig.21(b). First, the modified propagation delay time TD(G1)ADJ can be obtained by the modification method of the signal cell. Then, Diff(G1) can be implied by TD(G1)ADJ-TD(G1)ORG and be propagated to next event T(B). T(B)ADJ is derived by the summation of T(B) and Diff(G1). The other events can be modified in the similar way. After the timing errors are corrected, the accuracy of the constructed waveforms based on those events can be further improved.

Fig. 21. Illustration of VCD events with (a) ideal (b) non-ideal supply lines
