**3.1.6 Cross coupling of through-silicon-vias (TSVs)**

The results in (Liu et al., 2011) show that TSVs cause a significant coupling noise and timing problems even if TSV count is significantly less compared to the gate count. The core switching noise through power distribution TSVs may directly or through substrate couple to I/O drivers power supply network, signal links, clock lines, and analog components of the chip. In addition to that the core switching noise may couple to neighboring dies through TSVs for a three-dimensional (3D) stack of dies interconnected through TSVs as the substrates of different planes may essentially be biased through a common ground (Salman, 2011). Various inter-plane noise coupling paths have been identified in (Salman et al., 2010). The results in (Radhakrishna et al., 2007) show that I/O voltage is more sensitive to transient currents produced by switching of the core logic. Power distribution TSVs have significant capacitance due to larger in size as compared to signal TSVs and therefore, may produce significant noise coupling to substrate. The coupling noise from a power distribution TSV may cause path delay in signal line due to Miller effect. The coupling noise through power distribution TSVs may cause charge sharing to dynamic logic, thereby flipping the signal unintentionally or may change the state of a sequential element in static logic.

Fig. 3. Cross coupling of a TSV to nearby TSVs where M indicates the middle TSV and E, W, N, S, SE, SW, NW, and NE indicate the locations of closer TSVs to the middle TSV. The diagram is taken from (Roshan, 2008).

With the scaling of power supply voltage the thickness of the gate oxide in modern CMOS VLSI circuits is very thin in order to reduce the nominal supply voltage (Ming-Dou & Jung-Sheng, 2008). The excessive surge in power voltage or drop in ground voltage, therefore,

The channels of CMOS devices are already very short in length due to scaling with the technology nodes. Therefore, excessive surge in supply voltage or drop in ground voltage may cause the carriers to inject into the substrate or the gate oxide due to over voltage thereby depleting the drain-channel junction. It is called hot carrier injection and occurs when the transistor is in saturation (or switched). Consequently, it increases the switching

The results in (Liu et al., 2011) show that TSVs cause a significant coupling noise and timing problems even if TSV count is significantly less compared to the gate count. The core switching noise through power distribution TSVs may directly or through substrate couple to I/O drivers power supply network, signal links, clock lines, and analog components of the chip. In addition to that the core switching noise may couple to neighboring dies through TSVs for a three-dimensional (3D) stack of dies interconnected through TSVs as the substrates of different planes may essentially be biased through a common ground (Salman, 2011). Various inter-plane noise coupling paths have been identified in (Salman et al., 2010). The results in (Radhakrishna et al., 2007) show that I/O voltage is more sensitive to transient currents produced by switching of the core logic. Power distribution TSVs have significant capacitance due to larger in size as compared to signal TSVs and therefore, may produce significant noise coupling to substrate. The coupling noise from a power distribution TSV may cause path delay in signal line due to Miller effect. The coupling noise through power distribution TSVs may cause charge sharing to dynamic logic, thereby flipping the signal unintentionally or may change the state of a sequential element in static

Fig. 3. Cross coupling of a TSV to nearby TSVs where M indicates the middle TSV and E, W, N, S, SE, SW, NW, and NE indicate the locations of closer TSVs to the middle TSV. The

may cause the transistor gate oxide reliability issue due to the electrical over-stress.

time of an NMOS device and decreases the switching time of a PMOS device.

**3.1.6 Cross coupling of through-silicon-vias (TSVs)** 

**3.1.4 Gate oxide reliability issue** 

**3.1.5 Hot carrier injection (HCI)** 

logic.

diagram is taken from (Roshan, 2008).

Figure 3 shows the capacitive coupling of a given TSV to all the six TSVs arount it. This coupling depends on the distance of a TSV from other TSVs as well as the size of the TSVs. The capacitive coupling can be much stronger in bulky TSVs having significant hight. The coupling also, increases by increasing the density of TSVs. In addition to that, the coupling is inversly proportional to the thickness of the barrier layer around a TSV.
