**10. Summary**

In this chapter we developed a general framework for the design and fabrication of a multi-sensor system on a chip, which includes intelligent signal processing, as well as a built-in self test and parameter adjustment units. Further, we outlined its architecture, and examined various types of sensors (fluid biosensors for measuring resistivity and dielectric constant, spectral sensors, MEMS based photo-sensors, and optical microchemical and biochemical sensors), and fabrication techniques, as well as develop a transistorized bridge fluid biosensor for monitoring changes in the dielectric constant of a fluid, which could be of use for in-home monitoring of kidney function of patients with renal failure.

**2** 

*Taiwan* 

**Three-Dimensional Integrated Circuits** 

**From Aspect of Thermal Management** 

Chiao-Ling Lung1,2, Jui-Hung Chien2, Yung-Fa Chou2,

*1Department of Computer Science, National Tsing Hua University* 

As the performance of a processing system is to be significantly enhanced, on-chip manycore architecture plays an indispensable role. Since there are fast growing numbers of transistors on the chips, two-dimensional topologies face challenges of significant increases in interconnection delay and power consumption (Hennessy & Patterson, 2007; Kurd et al., 2001). Explorations of a suitable three-dimensional integrated circuit (3D IC) with throughsilicon via (TSV) to realize a large number of processing units and highly dense interconnects certainly attracts a lot of attention. However, the combination of processors, memories, and/or sensors in a stacked die leads to the cooling problem in a tottering situation (Tiwari et al., 1998). One solution to overcome the obstacles and continue the performance scaling while still is to integrate on chip many cores and their communication network (Beigne, 2008; Yu & Baas, 2006). Through concerted processors, routers, and links, the network-on-chip (NoC) provides the advantages of low power dissipation and abundance of connectivity. Moreover, because of the widespread uses of radio frequency (RF), micro-electro-mechanical systems (MEMS) (Lu, 2009), and various sensors in mobile applications, proposals of three-dimensional integrated circuit (3D IC) with through silicon via (TSV) implementations in a layered architecture have been reported (Lee, 1992; Tsai & Kang, 2000). For interconnection scalability from layer to layer, 3D fabrics are a necessity. Consequently, a thermal solution which has a high heat removing rate seems unavoidable. Since there are fast growing numbers of transistors on the chips, two-dimensional topologies face challenges of significant increases in wire delay and power consumption. The two factors are often regarded as the primary limitations for current processor

architectures (Hennessy & Patterson, 2007; Kurd et al., 2001; Tiwari et al., 1998).

each other, and additional dies are farther away from the heat sink.

On the other hand, the high packing density of the stacked dies also hampers the heat dissipation of the NoC system. Thermal issues arise from increasing dynamic power losses which in turn raise the temperature. Thermal and power constraints are of great concern with 3D IC since die stacking can dramatically increase power density, if hotspots overlap

**1. Introduction** 

Ding-Ming Kwai2 and Shih-Chieh Chang1

*Industrial Technology Research Institute*

*2Information and Communications Research Laboratories,* 

**Design for Thousand-Core Processors:** 

### **11. Acknowledgments**

This research was sponsored in part by the 2007 Wertheim Fellowship, US Naval Academy.

### **12. References**

