**3.3 Experimental setup**

The die photo of the proposed test chip in this chapter is shown in Figure 20. This chip is fabricated by TSMC in 0.18 μm 1P4M mixed-mode process technology. The package uses 256-pin IST Universal PGA. The front of the chip is covered by the package glue. In order to observe the thermal behavior of the test chip, the back of the chip is exposed to air with a transparent PYREX® glass of 120 μm. There is a 6 cm x 6cm open window in the central area of the evaluation board to facilitate the observation on the temperature measurement.

Fig. 20. The die photo of the proposed test chip in this chapter, the dimension of the chip is 5,040 µm × 5,040 µm, including the seal ring.

The principle measurement environment setup includes DC power supplier (MOTECH PPS 3210), current meter (FLUKE 189), function generator (HP 8166A), temperature-humidity chamber (HOLINK EZ040-72001), logic analyzer (Agilent N6705A), infrared camera (FLIR SC5700), and thermal management total analysis platform. As shown in Figure 21(a), the FLIR SC5700 with a microscope of three μm resolution is responsible for infrared radiation (IR) inspection. The temperature responses are measured by the thermal management total analysis platform designed by ICL, ITRI as shown in Figure 21(b). It is clear in Figure 21(c), the test environment is controlled at a constant ambient temperature, in which the temperature error varies within ± 0.5 oC. The programmable temperature-humidity chamber HOLINK EZ040-72001 is used to control the operation temperature from 0 oC to 100 oC. MOTECH PPS 3210 is the power supply which provides the three voltage levels. The control signals (*TS\_EN* and *CLK*) are generated from HP 8166A. The current meter FLUKE 189 is utilized for measuring the current consumption. Last, the output signals are collected and analyzed by Agilent N6705A.

The die photo of the proposed test chip in this chapter is shown in Figure 20. This chip is fabricated by TSMC in 0.18 μm 1P4M mixed-mode process technology. The package uses 256-pin IST Universal PGA. The front of the chip is covered by the package glue. In order to observe the thermal behavior of the test chip, the back of the chip is exposed to air with a transparent PYREX® glass of 120 μm. There is a 6 cm x 6cm open window in the central area of the evaluation board to facilitate the observation on the temperature measurement.

Fig. 20. The die photo of the proposed test chip in this chapter, the dimension of the chip is

The principle measurement environment setup includes DC power supplier (MOTECH PPS 3210), current meter (FLUKE 189), function generator (HP 8166A), temperature-humidity chamber (HOLINK EZ040-72001), logic analyzer (Agilent N6705A), infrared camera (FLIR SC5700), and thermal management total analysis platform. As shown in Figure 21(a), the FLIR SC5700 with a microscope of three μm resolution is responsible for infrared radiation (IR) inspection. The temperature responses are measured by the thermal management total analysis platform designed by ICL, ITRI as shown in Figure 21(b). It is clear in Figure 21(c), the test environment is controlled at a constant ambient temperature, in which the temperature error varies within ± 0.5 oC. The programmable temperature-humidity chamber HOLINK EZ040-72001 is used to control the operation temperature from 0 oC to 100 oC. MOTECH PPS 3210 is the power supply which provides the three voltage levels. The control signals (*TS\_EN* and *CLK*) are generated from HP 8166A. The current meter FLUKE 189 is utilized for measuring the current consumption. Last, the output signals are collected and

5,040 µm × 5,040 µm, including the seal ring.

analyzed by Agilent N6705A.

**3.3 Experimental setup** 

(c)

Fig. 21. The testing environment and setup. (a) The test chip is under the measurement environment with the infrared radiation inspection. (b) The naked die with the evaluation board and thermal management total analysis platform. (c) The test chip is placed in the chamber at a nearly constant ambient temperature.

Three-Dimensional Integrated Circuits Design

is clear that the temperature of 1

thermal conductive capability of 1

**Type of metallic** 

**thermal skeleton** 

**Tavg (on the metallic** 

Table 1. The temperature distribution of the test chip.

**thermal skeleton)** 

the <sup>2</sup> -A5- <sup>1</sup> 

sink.

**4. Conclusion** 

for Thousand-Core Processors: From Aspect of Thermal Management 37

On the other hand, transient temperature response is recorded by the high speed infrared radiation dynamic photos as shown in Figure 22. Take the region in the photo for example;

is higher than that of

metal density constraint in the design rule released from the foundry, therefore no more metal are allowed to be placed. However, the region may be reserved for the placement of thermal TSVs or front metal stripes during the post CMOS process to be the on-chip heat

is better than that of

**Tmax (at virtual core) 71.00 71.36 70.12** 

**Tmin (in the region) 57.48 56.38 57.82** 

**Tmax - Tmin 13.52 14.98 12.30** 

The cost of thermal ridges and metallic thermal skeletons may be compared with the advanced techniques, such as micro-channel liquid cooling or the thermo-electric cooling (TEC). Since by ITRS, the number of stacked dies is expected to increase in the future, the cooling problem of the inter-layer dies will become more challenging. If the heat should be removed by pumping liquid or external energy into the stacked dies, the cooling cost will grow exponentially. The thermal ridges and metallic thermal skeletons proposed in this chapter will be relatively cost-effective and energy-saving. Moreover, this proposed method locally improves the temperature non-uniformity, and the thermal gradient of the most part of the chip also decreases. Nevertheless, the global temperature non-uniformity which affects the chip operations from the electrical perspective deserves more efforts to pursue. Since the 3D IC with TSV now appears as an emerging technology, the early floorplan for the insertion of thermal ridges and metallic thermal skeletons for thermal management will be discussed more and more widespread. The temperature distributions measured by the

region (referred to Figure 12) includes 2 types of metallic thermal skeletons. It

**α β γ**

**63.13 62.92 63.45** 

**Temperature in oC** 

<sup>2</sup> . This results show that the

<sup>2</sup> . The area of is limited by the

#### **3.4 Results and discussions**

The experimental results are shown in Table 1. When the power density of 7.38 W/cm2 is applied to the virtual core, each core is operated at the power of 20 mW. To evaluate the thermal conduction capability of the metallic thermal skeleton, the average temperature of the metallic thermal skeleton is an important index. Since the metallic thermal skeletons are employed to conduct the heat flux generated by the virtual cores, the temperature at *w*/2 (referred to Figure 18) especially represents the results of the lateral thermal diffusion. To compare with the experimental steady state data shown in Table 1, it is clear that the virtual cores with the metallic thermal skeleton type have better thermal conductive performance. Moreover, Tmax-Tmin denotes the temperature uniformity in the region. The results show that the metallic thermal skeleton has the best performance among these three combinations.

Fig. 22. The transient response of the test chip is taken by the infrared radiation camera when the virtual cores are activated. These are the back views of the test chip.

On the other hand, transient temperature response is recorded by the high speed infrared radiation dynamic photos as shown in Figure 22. Take the region in the photo for example; the <sup>2</sup> -A5- <sup>1</sup> region (referred to Figure 12) includes 2 types of metallic thermal skeletons. It is clear that the temperature of 1 is higher than that of <sup>2</sup> . This results show that the thermal conductive capability of 1 is better than that of <sup>2</sup> . The area of is limited by the metal density constraint in the design rule released from the foundry, therefore no more metal are allowed to be placed. However, the region may be reserved for the placement of thermal TSVs or front metal stripes during the post CMOS process to be the on-chip heat sink.


**Temperature in oC** 

Table 1. The temperature distribution of the test chip.
