**5. Experimental result**

#### **5.1 Experimental result of supply current waveform estimation method**

We have implemented a supply current waveform estimation tool in C/C++. Given an input pattern, this tool can calculate the triangle that simulates the supply current waveform of each cell. The overall supply current waveform is then obtained by combining all triangles of every changed cell in time. All the input files of this tool follow standard formats, which are Verilog netlist file of the gate-level design, value changed dump (VCD) file of the design under given input patterns, and the LIB file of the standard cell library. The output format is a (time, voltage) pair that can be used to plot the dynamic supply current waveform. Those input/output files are compatible with current EDA tools. It allows our solution to be plugged into the existing EDA flow smoothly.

Very few commercial tools can provide the current waveform information at gate level. We choose PrimeTime- PX (Synopsys, 2009) for comparison, which can be used to estimate cycle-accurate peak power at gate level. Divided by the supply voltage, the peak power can be transformed to the peak current. Besides traditional LIB format, this tool also supports CCSM library format, which can be used to demonstrate the help from new library format. The results with and without CCSM data are shown in the rows "CCSM"and "LIB" of Table 1 respectively. Because 0.13 μm library does not have CCSM data yet, those CCSM data are characterized from HSPICE simulation by ourselves. Therefore, only combinational

supply lines, these events will occur at different time thus incurring different current waveforms. Therefore, the modification of activity files is also proposed in this paper, as illustrated in Fig.21(b). First, the modified propagation delay time TD(G1)ADJ can be obtained by the modification method of the signal cell. Then, Diff(G1) can be implied by TD(G1)ADJ-TD(G1)ORG and be propagated to next event T(B). T(B)ADJ is derived by the summation of T(B) and Diff(G1). The other events can be modified in the similar way. After the timing errors are corrected, the accuracy of the constructed waveforms based on those

Fig. 21. Illustration of VCD events with (a) ideal (b) non-ideal supply lines

**5.1 Experimental result of supply current waveform estimation method** 

solution to be plugged into the existing EDA flow smoothly.

We have implemented a supply current waveform estimation tool in C/C++. Given an input pattern, this tool can calculate the triangle that simulates the supply current waveform of each cell. The overall supply current waveform is then obtained by combining all triangles of every changed cell in time. All the input files of this tool follow standard formats, which are Verilog netlist file of the gate-level design, value changed dump (VCD) file of the design under given input patterns, and the LIB file of the standard cell library. The output format is a (time, voltage) pair that can be used to plot the dynamic supply current waveform. Those input/output files are compatible with current EDA tools. It allows our

Very few commercial tools can provide the current waveform information at gate level. We choose PrimeTime- PX (Synopsys, 2009) for comparison, which can be used to estimate cycle-accurate peak power at gate level. Divided by the supply voltage, the peak power can be transformed to the peak current. Besides traditional LIB format, this tool also supports CCSM library format, which can be used to demonstrate the help from new library format. The results with and without CCSM data are shown in the rows "CCSM"and "LIB" of Table 1 respectively. Because 0.13 μm library does not have CCSM data yet, those CCSM data are characterized from HSPICE simulation by ourselves. Therefore, only combinational

events can be further improved.

**5. Experimental result** 

cells are characterized in our preliminary experiments. The previous approach (Shimazaki et al., 2000) is also rebuilt in our environment and tested in the same experiments to show our improvements on accuracy. Because they did not mention how to apply their approach on sequential cells, only combinational circuits are compared.

In the experiments, ISCAS'85 and ISCAS'89 benchmark circuits, which are implemented with TSMC 0.13um process, are used to test the accuracy. For each benchmark circuit, 200 random patterns are generated to trigger the circuit. After all, the average errors of the peak current and position with 200 pattern-pairs are shown in the row "eIp" of Tables 1 and 2. The standard deviation of the peak current and position with the 200 results is shown in the row "sIp" of Tables 1 and 2. The last column "AVG" in Tables 1 and 2 shows the average values of all cases. Figure 22 shows the estimated current waveforms of c7552 and s9234 as examples, which are very similar to HSPICE results.

According to the results estimated by PrimeTime-PX, the CCSM libraries significantly improve the accuracy of peak current estimation. However, the cycle-accurate results are still not accurate enough for analyzing the peak power or the IR-drop noise. The estimation results of the proposed methods, which are listed in the row "GCM" of Tables 2 and 3, demonstrates that the proposed approach can provide accurate estimations on the supply current waveforms by using the same information provided in traditional LIB libraries. The average estimation errors on eIPEAK and eTPEAK are about 10% with small standard deviation. The correlation between the estimated waveforms and HSPICE waveforms is higher than 0.97, which shows the similarity between the two waveforms. Compared to the rough estimation in (Shimazaki et al., 2000), the proposed approach does have a significant improvement on the estimation accuracy. Most importantly, the proposed approach can deal with sequential circuits, which enables this approach to be applied to modern designs.

The run time of the current waveform estimation for each benchmark circuit is provided in Table 3, which is measured on a XEON 3G machine with 2G RAM. The row"GCM" shows the run time of the proposed approach in seconds. The row "HSPICE" shows the run time of HSPICE simulation with the same patterns in hours. The row "Ratio"shows the ratio of the run time between HSPICE and GCM, which demonstrates a significant speed improvement.

Fig. 22. The estimation supply current waveforms of (a)c7552 (b)s9234.

Library-Based Gate-Level Current Waveform Modeling for Dynamic Supply Noise Analysis 207

method can reduce the estimation errors successfully. Figure 24 shows the estimated supply current waveforms of c7552 circuit as example, which also confirm the accuracy of the proposed approach (GCM(ADJ)). The waveforms obtained without IR-drop consideration (GCM) are also used to estimate the IR-drop directly with the same input pattern. The results show that estimation without considering Rwire effects suffers large errors when the resistance on supply lines is getting larger. The proposed adjustment can consider the Rwire

Fig. 23. The experimental results of library-adjustment methods on (a) ISCAS'85 (b)

Fig. 24. The estimation supply current waveforms of c7552 with RWIRE=10ohm

In this article, a library-based IR-drop estimation method is presented. This method concludes two parts, one is a gate-level supply current waveform estimation method using standard library information and the other is an analytical library adjustment method with IR-drop effect consideration. Extra characterization efforts and regression cost can be avoided to obtain accurate IR-drop estimation with less overhead. As shown in the experimental results, such an efficient modification method can provided good accuracy on IR-drop estimation with limited information. The estimation errors of our approach are

effects and have a significant improvement on accuracy.

ISCAS'89.

**6. Conclusion** 

about 5% compared with HSPICE results.


Table 1. Experimental results of ISCAS85 benchmark circuits


Table 2. Experimental results of ISCAS89 benchmark circuits


Table 3. Experimental results of run time

#### **5.2 Experimental result of library adjustment method**

In order to demonstrate the accuracy of the IR-drop-aware adjustment approach, the same ISCAS85 and ISCAS89 benchmark circuits are used to perform some experiments. For each benchmark circuit, 200 random pattern pairs are generated to trigger the circuit. The average results of all circuits are illustrated in Fig.23. The average peak current errors using the method without adjustment the library information is draw with dash lines (w/o). The proposed library method is draw with bold line(w). According to the results, the proposed method can reduce the estimation errors successfully. Figure 24 shows the estimated supply current waveforms of c7552 circuit as example, which also confirm the accuracy of the proposed approach (GCM(ADJ)). The waveforms obtained without IR-drop consideration (GCM) are also used to estimate the IR-drop directly with the same input pattern. The results show that estimation without considering Rwire effects suffers large errors when the resistance on supply lines is getting larger. The proposed adjustment can consider the Rwire effects and have a significant improvement on accuracy.

Fig. 23. The experimental results of library-adjustment methods on (a) ISCAS'85 (b) ISCAS'89.

Fig. 24. The estimation supply current waveforms of c7552 with RWIRE=10ohm

#### **6. Conclusion**

206 VLSI Design

Circuit c432 c499 c880 c1355 c1908 c2670 c3540 c5315 c6288 c7552 AVG LIB eIP(%) 60.63 203.96 44.51 111.75 64.72 812.42 69.66 1396.90 46.67 537.70 281.12

CCS eIP(%) 25.25 38.41 33.49 42.43 52.22 255.50 50.68 299.00 51.94 73.05 92.29

GCM eIP(%) 12.87 7.42 6.24 9.95 8.80 9.47 6.17 5.20 6.06 3.97 7.61

Circuit s298 s444 s526 s820 s1196 s1238 s1494 s5378 s9234 s15850 AVG GCM eIP(%) 8.96 12.52 10.96 12.96 8.92 9.32 2.84 10.81 13.77 13.04 10.40 sIp(%) 6.11 1.51 8.56 10.60 5.23 6.63 3.57 2.01 1.14 0.97 4.63 eTP(%) 10.99 4.12 7.25 6.97 5.87 5.12 8.25 2.12 1.52 3.29 5.55 sTp(%) 12.38 1.78 7.53 5.98 6.79 5.54 6.96 0.39 0.26 1.36 4.89 Corr 0.967 0.976 0.966 0.968 0.977 0.977 0.975 0.973 0.982 0.979 0.974

Circuit c432 c499 c880 c1355 c1908 c2670 c3540 c5315 c6288 c7552 AVG GCM (sec) 13.17 23.05 20.05 43.79 55.39 46.43 90.60 179.77 1083.94 414.68 - HSPICE(hr) 9.73 17.58 16.44 27.45 26.54 40.61 54.82 86.76 69.16 128.38 - Ratio 2661 2746 2951 2256 1725 3419 2178 1737 230 1115 2074 Circuit s298 s444 s526 s820 s1196 s1238 s1494 s5378 s9234 s15850 AVG GCM(sec) 4.38 1.78 3.15 2.76 6.89 6.12 4.88 28.55 35.35 71.75 - HSPICE(hr) 13.49 10.33 12.05 14.50 23.03 23.88 28.68 107.83 183.15 495.78 - Ratio 11089 20883 13770 18914 12034 14048 21161 13596 18652 24876 16902

In order to demonstrate the accuracy of the IR-drop-aware adjustment approach, the same ISCAS85 and ISCAS89 benchmark circuits are used to perform some experiments. For each benchmark circuit, 200 random pattern pairs are generated to trigger the circuit. The average results of all circuits are illustrated in Fig.23. The average peak current errors using the method without adjustment the library information is draw with dash lines (w/o). The proposed library method is draw with bold line(w). According to the results, the proposed

Table 1. Experimental results of ISCAS85 benchmark circuits

Table 2. Experimental results of ISCAS89 benchmark circuits

Table 3. Experimental results of run time

**5.2 Experimental result of library adjustment method** 

(Shimaza ki et al., 2000)

sIp(%) 0.62 0.46 0.22 0.18 0.34 2.09 0.25 4.04 0.06 1.75 1.00

sIp(%) 0.16 0.11 0.10 0.07 0.13 0.91 0.14 0.94 0.08 0.26 0.29

eIP(%) 42.16 35.81 59.85 81.11 64.88 41.01 51.61 38.48 27.73 31.67 47.43 sIp(%) 15.92 14.58 19.68 16.47 16.99 10.21 15.70 9.96 18.56 10.02 14.80 eTP(%) 2.80 1.04 4.48 1.58 5.25 1.48 6.00 4.88 11.02 7.11 4.56 sTp(%) 7.50 1.18 4.98 1.19 4.50 2.42 7.72 5.82 8.13 10.14 5.36 Corr 0.959 0.977 0.961 0.928 0.973 0.981 0.971 0.988 0.993 0.980 0.971

sIp(%) 8.18 4.99 4.96 4.69 5.21 5.82 4.77 3.98 2.55 2.99 4.81 eTP(%) 6.52 1.79 5.09 4.21 4.52 5.34 5.51 5.64 2.31 3.04 4.39 sTp(%) 13.16 1.14 7.02 2.45 2.45 6.67 7.80 6.29 3.16 5.31 5.64 Corr 0.964 0.985 0.985 0.976 0.987 0.977 0.982 0.989 0.992 0.988 0.983

> In this article, a library-based IR-drop estimation method is presented. This method concludes two parts, one is a gate-level supply current waveform estimation method using standard library information and the other is an analytical library adjustment method with IR-drop effect consideration. Extra characterization efforts and regression cost can be avoided to obtain accurate IR-drop estimation with less overhead. As shown in the experimental results, such an efficient modification method can provided good accuracy on IR-drop estimation with limited information. The estimation errors of our approach are about 5% compared with HSPICE results.

**10** 

*Sweden* 

**Switching Noise in 3D Power Distribution** 

The design and analysis of a power distribution network is one of the most important areas in high-speed digital systems. The main function of a power distribution network is to supply power to core logic and I/O circuits in any digital system. With increasing clock speeds accompanied by decreasing signal rise times and supply voltages, the transient currents injected into the power distribution planes can induce voltage fluctuations on the power distribution network (Tummala et al., 1997). This undesired voltage fluctuation on the power/ground planes is commonly known as switching noise or delta-I noise. Power supply noise leads to unwanted effects on the power distribution network (PDN) such as ground bounce, power supply compression, and electromagnetic interference. The digital switching noise propagates through the substrate and power distribution networks to analog circuits, degrading their performance in system-on-chip (SoC) applications (Iogra, 2007). The modern advances in process technology along with tremendous increase in number of on-chip devices make the design of on-chip power distribution network a major design challenge. Increased switching activity of high speed devices therefore causes large current derivatives or current transients. These current transients may cause unwanted potential drops in supply voltage due to parasitic resistance and inductance of power distribution network. Over and above, scaling of the supply voltage may cause a large degradation in the signal-to-noise ratio of high speed CMOS circuits (Bai & Hajj, 2002). When on-chip logic cells switch, either they draw current from supply network or inject current into the ground network. If a lot of logic cells switch simultaneously, then they may cause voltage variations within the supply network due to parasitic associated with the power distribution network. This voltage variation is nothing but core switching noise. It is called the voltage surge if variation is above the nominal voltage and is called the sag if variation is below the nominal supply voltage (Bobba & Hajj, 2002). This variation in supply voltage may cause logic errors thereby adversely affecting the circuit performance (Bai & Hajj, 2002). Excessive drop in power bus voltage or surge in ground bus voltage can cause following problems: decrease in the device drive capability, increase in the logic gate delay, and reduction of the noise margin. Hence, it is important to estimate these voltage variations in the power distribution network (Bai & Hajj, 2002). Simultaneous switching noise is mainly caused by the parasitic inductance associated with the power distribution network at high frequency. The power supply level goes down at different nodes in a PDN because of

**1. Introduction** 

*KTH Royal Institute of Technology KTH/ICT/ECS/ESD, Stockholm* 

**Networks: An Overview** 

Waqar Ahmad and Hannu Tenhunen
