**1. Introduction**

208 VLSI Design

This work was partially supported by R.O.C National Science Council under Grant NSC99-

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**7. Acknowledgment** 

1063-8210

59593-999-9

Synopsys

**8. References** 

2221-E-008-104. Their support are greatly appreciated.

233-240, ISSN: 1751-858X

The design and analysis of a power distribution network is one of the most important areas in high-speed digital systems. The main function of a power distribution network is to supply power to core logic and I/O circuits in any digital system. With increasing clock speeds accompanied by decreasing signal rise times and supply voltages, the transient currents injected into the power distribution planes can induce voltage fluctuations on the power distribution network (Tummala et al., 1997). This undesired voltage fluctuation on the power/ground planes is commonly known as switching noise or delta-I noise. Power supply noise leads to unwanted effects on the power distribution network (PDN) such as ground bounce, power supply compression, and electromagnetic interference. The digital switching noise propagates through the substrate and power distribution networks to analog circuits, degrading their performance in system-on-chip (SoC) applications (Iogra, 2007). The modern advances in process technology along with tremendous increase in number of on-chip devices make the design of on-chip power distribution network a major design challenge. Increased switching activity of high speed devices therefore causes large current derivatives or current transients. These current transients may cause unwanted potential drops in supply voltage due to parasitic resistance and inductance of power distribution network. Over and above, scaling of the supply voltage may cause a large degradation in the signal-to-noise ratio of high speed CMOS circuits (Bai & Hajj, 2002). When on-chip logic cells switch, either they draw current from supply network or inject current into the ground network. If a lot of logic cells switch simultaneously, then they may cause voltage variations within the supply network due to parasitic associated with the power distribution network. This voltage variation is nothing but core switching noise. It is called the voltage surge if variation is above the nominal voltage and is called the sag if variation is below the nominal supply voltage (Bobba & Hajj, 2002). This variation in supply voltage may cause logic errors thereby adversely affecting the circuit performance (Bai & Hajj, 2002). Excessive drop in power bus voltage or surge in ground bus voltage can cause following problems: decrease in the device drive capability, increase in the logic gate delay, and reduction of the noise margin. Hence, it is important to estimate these voltage variations in the power distribution network (Bai & Hajj, 2002). Simultaneous switching noise is mainly caused by the parasitic inductance associated with the power distribution network at high frequency. The power supply level goes down at different nodes in a PDN because of

devices.

(Sapatnekar, 2009).

nodes:

Switching Noise in 3D Power Distribution Networks: An Overview 211

switching noise is substrate noise which may modulate the threshold voltage of MOS

Three-Dimensional (3D) integration is a key enabling technology in today's high speed digital design. The purpose of 3D integration is either to partition a single chip into multiple strata to reduce on-chip global interconnects length (Joyner, 2004) or stacking of chips together through TSVs. By increasing the number of strata from one to four reduces the length of the longest interconnect by 50% with 75% improvement in latency and 50% improvement in interconnect energy dissipation (Meindl, 2002). Using 3D integration the wire-limited clock frequency can be increased by 3.9x and wire-limited area and power can be reduced by 84% (Miendl, 2003) and 51% (Khan et al., 2011) respectively. The power delivery to a 3D stack of high power chips also presents many challenges and requires careful and appropriate resource allocation at the package level, die level, and interstratal interconnect level (Huang et al., 2007). Three-Dimensional (3D) integration provides the potential for tremendously increased level of integration per unit footprint as compared to its 2D counterpart (Xie et al., 2010). While the third dimension introduced this way is attractive for many applications but puts some stringent requirements and bottlenecks on 3D power delivery. The huge current requirements per package pin for 3D integration lead to significant complications in reliable power delivery. A k-tier 3D chip could use k times as much current as a single 2D chip of the same footprint under similar packaging technology (Xie et al., 2010). Through silicon vias used in 3D integration introduce extra resistance and inductance in the power distribution path. The power distribution network impedance has not been kept up with the scaling of technology node due limited wire resources, increased device density and current demands (Xie et al., 2010) and situation is further worsened by 3D integration. The increased IR and Ldi/dt supply noise in 3D chips may cause a larger variation in operating speed leading to more timing violations (Xie et al., 2010). The supply noise overshoot due to inductive parasitic may aggravate reliability issues such as oxide breakdown, hot carrier injection (HCI), and negative bias temperature instability (NBTI)

Three-Dimensional (3D) integration increases integration density by increasing number of on-chip devices per unit footprint which has following effects with the scaling of technology

Each power distribution TSV pair has to supply a logic load with decoupling capacitance. In order to increase the switching speed, the time constant RC needs to be reduced which means to reduce TSV resistance which is difficult with the scaling of technology node. Even if the instantaneous voltage fluctuation is very small, the periodic nature of digital circuits can cause resonance (Larsson, 1998). The resonance frequency due to effective TSV

1

*TSV dec*

<sup>2</sup> *<sup>r</sup> eff*

π*L C*

*f*

=

• Increase in inductance per unit foot print at high frequency of the order of GHz. • Consequent rise in switching noise imposed on 3D power distribution network.

• Tremendous increase in current per unit foot print.

inductance and decoupling capacitance is given as follows

• Increase in power per unit foot print.

the inductive voltage drop at high frequency. This is because of the simultaneous switching of on-chip logic load as well as drivers connected to the output pins of a chip. The glitch in voltage caused this way is proportional to the number of circuit components switching at a clock edge, the steepness of the clock edge and effective inductance of the power distribution network at this moment. On-chip core switching noise as well as the noise caused by switching of the external drivers is equally important at high operating frequencies of the order of GHz. Scaling down of the technology node shrinks the minimum feature size which in turn increases average capacitive load offered by on-chip core logic. Therefore average charging and discharging currents for on-chip logic load increase. The increased circuit speed also raises di/dt. Therefore, on-chip currents may fluctuate by large amounts within short interval of times. Hence voltage fluctuations caused by switching of on-chip logic load known as core switching noise is very significant and important under these circumstance.

On-chip power distribution noise has become a determining factor in performance and reliability where the core voltage has dramatically dropped to 0.9V for 40nm technology node (Shishuang et al., 2010) and the trend continuous. At the same time jitter tolerance and timing margins are shrinking due to ever increasing clock frequency (Shishuang et al., 2010). The chip-package PDN should therefore be optimized at early design stages to meet I/O jitter specifications and core logic timing closure (Bai & Hajj, 2002). For the IC designers and the signal integrity engineers, the most important issue is to understand how the on-chip transient current load interacts with the entire PDN system, and how the on-chip PDN noise affects the circuit performance (Shishuang et al., 2010). The experimental results in (Shishuang et al., 2010) show that on-chip PDN noise may be much higher even if PCB level PDN noise is well under control.

On-chip noise margins decrease proportionally with the power supply with the scaling of the technology nodes (Coenen & Roermund, 2010). Generally the voltage fluctuation should be kept within 5-10% of the supply voltage in VLSI design (Dennis et al., 2008). When supply voltage is less than the nominal value in synchronous digital circuits, it causes timing violations in a register during a clock period (Dennis et al., 2008). This timing error caused by power supply noise may become permanent when stored in a register (Dennis et al., 2008). Core switching noise has been neglected in past due to higher package inductance as compared to on-chip inductance of the power distribution network. Therefore, switching noise was considered to be inductive voltage noise caused by fast switching I/O drivers (Bathy, 1996; Kabbani & Al-Khalili, 1999; Senthinathan & Prince, 1991; Vaidyanath, 1994;Yang & Brews, 1996). On the other hand today several folds increase in clock frequency as compared to I/O speed accompanied with higher integration densities and scaling of onchip interconnects has made the core switching noise more critical than ever (Zheng & Tenhunnen, 2001). The supply-noise becomes more problematic when microprocessors share the same substrate as the analogue circuits like PLL (Stark et al., 2008) (Vonkaenel, 2002). Therefore core switching noise may cause jitter in clock frequency thereby reducing the usable cycle time and consequently causing critical path failure in the processor. If core switching noise is extended over several clock cycles, then jitter accumulation will take place thereby causing deviation of each subsequent clock edge more and more from the ideal location (Larsson, 2002). The noise accumulation therefore causes synchronization failure between different clock domains more than the critical path failure. The other side effect of

the inductive voltage drop at high frequency. This is because of the simultaneous switching of on-chip logic load as well as drivers connected to the output pins of a chip. The glitch in voltage caused this way is proportional to the number of circuit components switching at a clock edge, the steepness of the clock edge and effective inductance of the power distribution network at this moment. On-chip core switching noise as well as the noise caused by switching of the external drivers is equally important at high operating frequencies of the order of GHz. Scaling down of the technology node shrinks the minimum feature size which in turn increases average capacitive load offered by on-chip core logic. Therefore average charging and discharging currents for on-chip logic load increase. The increased circuit speed also raises di/dt. Therefore, on-chip currents may fluctuate by large amounts within short interval of times. Hence voltage fluctuations caused by switching of on-chip logic load known as core switching noise is very significant and important under

On-chip power distribution noise has become a determining factor in performance and reliability where the core voltage has dramatically dropped to 0.9V for 40nm technology node (Shishuang et al., 2010) and the trend continuous. At the same time jitter tolerance and timing margins are shrinking due to ever increasing clock frequency (Shishuang et al., 2010). The chip-package PDN should therefore be optimized at early design stages to meet I/O jitter specifications and core logic timing closure (Bai & Hajj, 2002). For the IC designers and the signal integrity engineers, the most important issue is to understand how the on-chip transient current load interacts with the entire PDN system, and how the on-chip PDN noise affects the circuit performance (Shishuang et al., 2010). The experimental results in (Shishuang et al., 2010) show that on-chip PDN noise may be much higher even if PCB level

On-chip noise margins decrease proportionally with the power supply with the scaling of the technology nodes (Coenen & Roermund, 2010). Generally the voltage fluctuation should be kept within 5-10% of the supply voltage in VLSI design (Dennis et al., 2008). When supply voltage is less than the nominal value in synchronous digital circuits, it causes timing violations in a register during a clock period (Dennis et al., 2008). This timing error caused by power supply noise may become permanent when stored in a register (Dennis et al., 2008). Core switching noise has been neglected in past due to higher package inductance as compared to on-chip inductance of the power distribution network. Therefore, switching noise was considered to be inductive voltage noise caused by fast switching I/O drivers (Bathy, 1996; Kabbani & Al-Khalili, 1999; Senthinathan & Prince, 1991; Vaidyanath, 1994;Yang & Brews, 1996). On the other hand today several folds increase in clock frequency as compared to I/O speed accompanied with higher integration densities and scaling of onchip interconnects has made the core switching noise more critical than ever (Zheng & Tenhunnen, 2001). The supply-noise becomes more problematic when microprocessors share the same substrate as the analogue circuits like PLL (Stark et al., 2008) (Vonkaenel, 2002). Therefore core switching noise may cause jitter in clock frequency thereby reducing the usable cycle time and consequently causing critical path failure in the processor. If core switching noise is extended over several clock cycles, then jitter accumulation will take place thereby causing deviation of each subsequent clock edge more and more from the ideal location (Larsson, 2002). The noise accumulation therefore causes synchronization failure between different clock domains more than the critical path failure. The other side effect of

these circumstance.

PDN noise is well under control.

switching noise is substrate noise which may modulate the threshold voltage of MOS devices.

Three-Dimensional (3D) integration is a key enabling technology in today's high speed digital design. The purpose of 3D integration is either to partition a single chip into multiple strata to reduce on-chip global interconnects length (Joyner, 2004) or stacking of chips together through TSVs. By increasing the number of strata from one to four reduces the length of the longest interconnect by 50% with 75% improvement in latency and 50% improvement in interconnect energy dissipation (Meindl, 2002). Using 3D integration the wire-limited clock frequency can be increased by 3.9x and wire-limited area and power can be reduced by 84% (Miendl, 2003) and 51% (Khan et al., 2011) respectively. The power delivery to a 3D stack of high power chips also presents many challenges and requires careful and appropriate resource allocation at the package level, die level, and interstratal interconnect level (Huang et al., 2007). Three-Dimensional (3D) integration provides the potential for tremendously increased level of integration per unit footprint as compared to its 2D counterpart (Xie et al., 2010). While the third dimension introduced this way is attractive for many applications but puts some stringent requirements and bottlenecks on 3D power delivery. The huge current requirements per package pin for 3D integration lead to significant complications in reliable power delivery. A k-tier 3D chip could use k times as much current as a single 2D chip of the same footprint under similar packaging technology (Xie et al., 2010). Through silicon vias used in 3D integration introduce extra resistance and inductance in the power distribution path. The power distribution network impedance has not been kept up with the scaling of technology node due limited wire resources, increased device density and current demands (Xie et al., 2010) and situation is further worsened by 3D integration. The increased IR and Ldi/dt supply noise in 3D chips may cause a larger variation in operating speed leading to more timing violations (Xie et al., 2010). The supply noise overshoot due to inductive parasitic may aggravate reliability issues such as oxide breakdown, hot carrier injection (HCI), and negative bias temperature instability (NBTI) (Sapatnekar, 2009).

Three-Dimensional (3D) integration increases integration density by increasing number of on-chip devices per unit footprint which has following effects with the scaling of technology nodes:


Each power distribution TSV pair has to supply a logic load with decoupling capacitance. In order to increase the switching speed, the time constant RC needs to be reduced which means to reduce TSV resistance which is difficult with the scaling of technology node. Even if the instantaneous voltage fluctuation is very small, the periodic nature of digital circuits can cause resonance (Larsson, 1998). The resonance frequency due to effective TSV inductance and decoupling capacitance is given as follows

$$f\_r = \frac{1}{2\pi\sqrt{L\_{ISV}^{eff}C\_{dec}}}$$

Switching Noise in 3D Power Distribution Networks: An Overview 213

power distribution network depends on the parasitic inductance of the current path between the driver and the output load, the maximum current demand of the load, and the

Fig. 2. (a) Configuration of three stacked chip-PDN connected by a multi-P/G TSV. (b) Simulated PDN impedances of a single chip-PDN (dotted line) and three stacked chip-PDN (solid and dashed lines) by the proposed separated P/G TSVand chip-PDN models. The

The impedance peaks for the power distribution network of a three-dimensional (3D) stack of chips as compared to a two-dimensional (2D) chip is shown by Figure 2 (Pak et al., 2011). The impedance peaks are in GHz range and are created due to faster switching on the power distribution network. A huge amount of decoupling capacitance is required to suppress these peaks for a three-dimensional (3D) power distribution network (Pak et al., 2011). The impedance peaks are mainly generated due to TSV inductance at high frequency.

• Circuit reliability degradation like decrease in the signal to noise ratio or increase in the

Figure is taken from (Pak et al., 2011).

• Reduction of the voltage margins.

• Failure of the logic.

noise sensitivity.

Simultaneous switching noise causes the following problems:

• Noise coupling to sensitive circuits like RF and analogue circuits.

clock frequency.

In order to prevent oscillations through a TSV pair the resonance frequency should be higher or lower than the system clock frequency. The effective resistance of TSV produces IR-drop, whereas reduces the resonance oscillations by providing damping. If simultaneous switching noise is dominant, the decrease in TSV effective resistance may increase the total noise in a 3D power distribution network.

A three-dimensional (3D) stack of logic dies interconnected through TSVs has to connect the core logic circuits, IO circuits, and rest of the circuits from three-dimensional (3D) stack to the printed circuit board. Therefore, both the simultaneous switching noise and the core switching noise depend on high-speed switching currents through power distribution network in three-dimensional (3D) stack of dies, location and number of power distribution TSV pairs, vias and routing of various serial and parallel signal interfaces on signal layers of the package. The signal distribution TSV pairs share the IO power distribution environment. Three-dimensional (3D) power distribution network parasitic significantly account for core noise, significantly influence the simultaneous switching noise, crosstalk, signal propagation delay and skew between signal distribution TSVs. The transient currents drawn by core logic produce voltage droops across outputs of the core power distribution network thereby degrading the operating frequency performance of the microprocessor. Similar voltage droops are produced across IO power distribution network as a result of total transient current pulled through IO drivers and buffers. These droops weaken the signal driving capability of IO drivers thereby causing signal integrity issues.

#### **2. Simultaneous switching in 3D power distribution network**

On-chip simultaneous switching noise is caused by switching of the output buffers or drivers as shown by Figure 1. These drivers have to drive the off chip load. The noise on

Fig. 1. Simultaneous Switching of Output Drivers

In order to prevent oscillations through a TSV pair the resonance frequency should be higher or lower than the system clock frequency. The effective resistance of TSV produces IR-drop, whereas reduces the resonance oscillations by providing damping. If simultaneous switching noise is dominant, the decrease in TSV effective resistance may increase the total

A three-dimensional (3D) stack of logic dies interconnected through TSVs has to connect the core logic circuits, IO circuits, and rest of the circuits from three-dimensional (3D) stack to the printed circuit board. Therefore, both the simultaneous switching noise and the core switching noise depend on high-speed switching currents through power distribution network in three-dimensional (3D) stack of dies, location and number of power distribution TSV pairs, vias and routing of various serial and parallel signal interfaces on signal layers of the package. The signal distribution TSV pairs share the IO power distribution environment. Three-dimensional (3D) power distribution network parasitic significantly account for core noise, significantly influence the simultaneous switching noise, crosstalk, signal propagation delay and skew between signal distribution TSVs. The transient currents drawn by core logic produce voltage droops across outputs of the core power distribution network thereby degrading the operating frequency performance of the microprocessor. Similar voltage droops are produced across IO power distribution network as a result of total transient current pulled through IO drivers and buffers. These droops weaken the signal driving

On-chip simultaneous switching noise is caused by switching of the output buffers or drivers as shown by Figure 1. These drivers have to drive the off chip load. The noise on

I1 I2 In

Increase of maximum power (current)

Simultaneous Switching of Output Buffers Parasitic Inductance

**1 2 n** 

H

L

L

L

V=Vdd + V

I= I1+ I2+....+ In

noise in a 3D power distribution network.

capability of IO drivers thereby causing signal integrity issues.

Fig. 1. Simultaneous Switching of Output Drivers

H

L

Common Power Supply

t

<sup>I</sup>**V=L** 

Common Ground

H

L

**2. Simultaneous switching in 3D power distribution network** 

Increase of clock frequency

power distribution network depends on the parasitic inductance of the current path between the driver and the output load, the maximum current demand of the load, and the clock frequency.

Fig. 2. (a) Configuration of three stacked chip-PDN connected by a multi-P/G TSV. (b) Simulated PDN impedances of a single chip-PDN (dotted line) and three stacked chip-PDN (solid and dashed lines) by the proposed separated P/G TSVand chip-PDN models. The Figure is taken from (Pak et al., 2011).

The impedance peaks for the power distribution network of a three-dimensional (3D) stack of chips as compared to a two-dimensional (2D) chip is shown by Figure 2 (Pak et al., 2011). The impedance peaks are in GHz range and are created due to faster switching on the power distribution network. A huge amount of decoupling capacitance is required to suppress these peaks for a three-dimensional (3D) power distribution network (Pak et al., 2011). The impedance peaks are mainly generated due to TSV inductance at high frequency.

Simultaneous switching noise causes the following problems:


Switching Noise in 3D Power Distribution Networks: An Overview 215

noise overshoot due to inductive parasitic may aggravate reliability issues such as oxide breakdown, hot carrier injection (HCI), and negative bias temperature instability (NBTI) (Sapatnekar, 2009). The power delivery to a three-dimensional (3D) stack of high power chips also presents many challenges and requires careful and appropriate resource allocation at the package level, die level, and interstratal interconnect level (Huang et al., 2007). Any drop in the core supply voltage directly impacts the maximum operating frequency of the processor (Huang et al., 2007). Simultaneous switching noise originated from the internal logic circuitry has become a serious issue with the increase in speed and

The voltage variations due to core switching noise are spread out to the diverse nodes of the power distribution network, thereby causing severe performance degradations in the form of propagation delays (Andarde et al., 2007). The timing violation in a register is produced when value of the supply voltage is less than the nominal value in a synchronous digital circuit. Due to slow variation of the supply voltage as compared to the clock period the value of the supply voltage may remain same for all the gates in a combinational path. Therefore, the value of supply voltage may vary period to period causing severe reliability issues is the logic. The logic cells are prone to more delays with the voltage scaling whereas keeping the threshold voltage relatively constant (Ajami et al., 2003). The propagation delay of the gates increases by 10% with 10% drop in the supply voltage for 180nm (Saleh et al., 2002), by 30% with 10% variation in the supply voltage for 130nm (Pant et al., 2004), and by 4% with 1% change in the supply voltage for 90nm technology node (Tirumuri et al., 2004).

The scaling of the threshold voltage with the scaling of the power supply voltage has reduced the noise margins, thereby making the CMOS circuits more vulnerable to the noise (Bobba & Hajj, 2002). The excessive drop in the power voltage or surge in the ground voltage may drop the noise margins of the circuits. Consequently, a circuit may erroneously latch up to a wrong value or switch at a wrong time if magnitude of the voltage surge/droop is greater than the noise margin of the circuit for a given clock edge (Pant et al., 2000). The problem is expected to grow for a three-dimensional (3D) stack of logic dies

The gates are becoming increasingly sensitive to the switching noise due to limited scaling of the threshold voltage as compared to the supply voltage scaling with each technology node (Junxia et al., 2009). The reduction in supply voltage not only reduces the noise immunity but also produces signal integrity as well as the performance and the reliability issues. The voltage spikes are droops produced in the power distribution network due to core switching because of the parasitic inductance and resistance associated with the power supply network. The excessive drop in power voltage or surge in the ground voltage, therefore, slows down the cell transition capability, thereby seriously compromising the cell driving capabilities. Consequently clock skews are produced as a result of violations in the

interconnected through TSVs, with the addition of each die in the vertical stack.

**3.1.3 Impairing driving capabilities of a gate** 

density of the internal circuitry.

**3.1.1 Propagation delay** 

**3.1.2 Logic errors** 

setup and the hold times.

### **3. Core switching noise in 3D power distribution network**

Logic cells are connected between supply and ground TSVs for a three-dimensional (3D) power distribution network. Each logic cell has an equivalent capacitance as a load to the power distribution TSV pair. On-chip logic cells switch either low to high or high to low at different clock edges in a synchronous logic system. When on-chip logic cells switch, either they draw current from supply network or inject current into the ground network. If a lot of logic cells switch simultaneously, they may produce voltage variations within the supply network due to the parasitic associated with the power distribution network. This voltage variation is nothing but core switching noise. It is called voltage surge if variation is above the nominal voltage and is called the sag if variation is below the nominal supply voltage (Bobba & Hajj, 2002). The core switching noise depends on the on-chip power distribution network parasitic rather than the package parasitic because of the scaling of the interconnect in modern high speed ULSI design. In addition to that the core switching noise has become more on-chip centric as the package inductance is significantly less as compared to the onchip inductance at high frequency because of the introduction of BGAs and TSVs in modern packaging. The core switching noise is a major part of the total simultaneous switching noise as the current drawn by the core logic load is generally much higher than the I/O driver's current (Radhakrishnan et al., 2007). The core switching noise in a threedimensional (3D) stack of logic dies interconnected through TSVs is more significant as compared to 2D ICs due to extra parasitic introduced through vertical TSVs. A large switching noise is introduced in a three-dimensional (3D) power distribution network if various stacked dies switch simultaneously (Huang et al., 2007). The number of power distributions TSVs for a three-dimensional (3D) stack of dies is basically limited by the footprint of the die (Jain et al., 2008) and on top of that the power supply noise is further worsened with the addition of dies in vertical stack due to additional parasitic involved in the power distribution paths through TSVs. The core switching noise can be a critical issue in a system like three-dimensional (3D) multi-processor system-on-chip (3D MOPSoC) (Tao et al., 2010). The core switching noise may introduce common mode noise in mixed analog and digital design as well as increase radiation at resonant frequencies. Overall power consumption in a three-dimensional (3D) stack reduces due to less interconnect, however, power density is increased in parts of three-dimensional (3D) stack due to increase in the number of transistors per unit volume as compared to two-dimensional (2D) counterpart.

#### **3.1 Effects of core switching noise**

While the third dimension is attractive for many applications but puts some stringent requirements and bottlenecks on three-dimensional (3D) power delivery. Huge current requirements per package pin for three-dimensional (3D) integration lead to significant complications in reliable power delivery. A k-tier three-dimensional (3D) chip could use k times as much current as a single two-dimensional (2D) chip of the same footprint under similar packaging technology (Xie et al., 2010). Through-silicon-vias used in threedimensional (3D) integration introduce extra resistance and inductance in the power distribution path. The power distribution network impedance has not been kept up with the scaling of the technology node due to limited wire resources, increased device density and current demands (Xie et al., 2010) and situation is further worsened by 3D integration. The increased IR and Ldi/dt supply noise in three-dimensional (3D) chips may cause a larger variation in operating speed leading to more timing violations (Xie et al., 2010). The supply noise overshoot due to inductive parasitic may aggravate reliability issues such as oxide breakdown, hot carrier injection (HCI), and negative bias temperature instability (NBTI) (Sapatnekar, 2009). The power delivery to a three-dimensional (3D) stack of high power chips also presents many challenges and requires careful and appropriate resource allocation at the package level, die level, and interstratal interconnect level (Huang et al., 2007). Any drop in the core supply voltage directly impacts the maximum operating frequency of the processor (Huang et al., 2007). Simultaneous switching noise originated from the internal logic circuitry has become a serious issue with the increase in speed and density of the internal circuitry.
