**4. How to overcome core switching noise**

The core switching noise depends on the amount of logic load driven on rising/falling edge of the clock, sharpness of the clock edge (i.e. rise time), and nature of the network between power supply and logic load. The core switching noise can be reduced through different ways like placing on-chip decoupling capacitance close to the load, placing integrated decoupling capacitance with lower values of ESL and ESR into the substrate, keeping the output impedance across load as close to the target impedance as possible, and determining the optimum value of the damping factor for the power distribution network between supply and load. The rise time increases with the speed of the circuit and logic load increases with the integration density of transistors with each technology node and the problem is exacerbated for three-dimensional (3D) power distribution network.

#### **4.1 Using on-chip decoupling capacitance**

Decoupling capacitors are used as charge reservoirs to reduce the power supply noise during switching of the on-chip logic load. The decoupling capacitor is placed across the power and ground conductors to satisfy the target impedance that should be met at all the specified frequencies (Yamamoto & Davis, 2007). Practically, the decoupling capacitance is not a pure capacitance at high frequency because of the intrinsic effective series inductance and effective series resistance. Above the resonance frequency, the impedance of the decoupling capacitance appears inductive and the decoupling capacitance is therefore, not effective as desired above the self resonance frequency. Figure 4 (a) (Jakushokas et al., 2011) shows that the impedance of a power distribution network is resistive at low frequency, whereas it increases linearly with the frequency for higher frequencies due to the dominance of the inductive reactance of the network. There is a maximum frequency ωmax at which the network impedance exceeds the target impedance. Figure 4 (b) (Jakushokas et al., 2011) shows that the impedance of the network shoots up at the resonance frequency by using decoupling capacitance as compared to the no decoupling capacitance case. It is because of the parallel resonance produced by the LC tank circuit which produces the maximum impedance. However, above this frequency, the impedance starts increasing linearly with the frequency because of the dominance of the inductive reactance of the network at high frequency.

Figure 4 (Jakushokas et al., 2011) shows that the target impedance is reached at a higher frequency when using decoupling capacitance as compared to without the use of decoupling capacitance. Therefore, decoupling capacitance is used to increase the frequency at which the impedance of the power distribution network exceeds the target impedance. The impedance of a decoupling capacitance is equal to the effective series resistance of a capacitor at the resonance frequency. A logic gate that is not switching connects its output

Switching Noise in 3D Power Distribution Networks: An Overview 219

series resistance and inductance can be further brought down by inserting banks of small parallel decoupling capacitors in the substrate. The integrated decoupling capacitors provide noise immunity and improved power distribution for a monolithic threedimensional (3D) chips stack (Dang et al., 2009). Therefore, the integrated decoupling capacitors are more attractive for high frequency three-dimensional (3D) integrated systems.

There may be resonance oscillations in the power distribution network by adding on-chip decoupling capacitance (Bakoglu et al., 1990). A three-dimensional (3D) power distribution network has lower resonance frequency as compared to its two-dimensional (2D) counterpart (Jain et al., 2008). The resonance oscillations produced this way may cause worst case noise accumulation during subsequent clock cycles if not damped in a proper way. The on-chip decoupling capacitance should therefore be selected with a significant ESR (effective series resistance) in order to damp the resonance oscillations. The logic load on each die may have a resonance frequency as a result of the interaction between inductance of the power distribution TSV pairs and decoupling capacitance across the logic load. The damping is only required in the frequency domain around the resonance frequency, rather than at all the frequencies, therefore decoupling capacitance should be selected to have maximum ESR (effective series resistance) around the resonance frequency. The peak-to-peak ground noise on a power distribution TSV pair is given by (Larsson, 1998) through the following equation, assuming that TSV pair forms an under-damped system with damping factor less than one:

<sup>2</sup> -

⎝ ⎠

πζ

ζ

1- 1 e *pp v v*

Where

ζ

*eff*

eff RTSV 2

*pp* Δ*v* = Peak-to-peak ground noise on TSV pair.

in order to increase the value of the damping factor.

= = Damping factor for the power distribution TSV pair.

eff RTSV = Effective series resistance associated with a power distribution TSV pair.

*TSV L* = Effective series inductance associated with a power distribution TSV pair. *Cdec* = On-Chip decoupling capacitance associated with a decoupling capacitance.

The performance and reliability of a three-dimensional (3D) power distribution network also depends on the magnitude and duration of the resonance oscillations. These oscillations must be controlled or significantly damped, otherwise noise accumulation will take place at subsequent clock cycles. The damping factor should have significant value in order to suppress the resonance oscillations. The effective resistance of a power distribution TSV pair should be kept much higher than the effective inductance of the power distribution TSV pair

Δ*v* = Peak ground noise on TSV pair.

*dec eff TSV C L*

⎛ ⎞ ⎜ ⎟ Δ =Δ + ⎜ ⎟

**5. Resonance and damping in 3D power distribution network** 

load capacitance to either the positive supply or ground (Dally & Poulton, 1998). Thus, most of the time these output loads serve as symbiotic bypass capacitors that help maintain the supply voltage during current transients (Dally & Poulton, 1998). The method of calculating the symbiotic bypass capacitance is also given by (Dally & Poulton, 1998). The symbiotic bypass capacitance, therefore, enhances the strength of the intentional on-chip decoupling capacitance. However, too large decoupling capacitance reduces the resonance frequency of the power distribution network. Therefore, there is always a tradeoff between the resonance frequency and the amount of decoupling capacitance.

Fig. 4. (a) Frequency response of the impedance of a power distribution network without decoupling capacitance. (b) Frequency response of the impedance of a power distribution network with decoupling capacitance (Jakushokas et al., 2011).

#### **4.2 Using integrated decoupling capacitance for 3D chip stack**

The decoupling capacitors integrated into the Si substrate can provide high capacitance at low cost (Sharma et al., 2008). The integrated decoupling capacitors are famous for comparatively low effective series resistance and inductance at high frequency. The effective series resistance and inductance can be further brought down by inserting banks of small parallel decoupling capacitors in the substrate. The integrated decoupling capacitors provide noise immunity and improved power distribution for a monolithic threedimensional (3D) chips stack (Dang et al., 2009). Therefore, the integrated decoupling capacitors are more attractive for high frequency three-dimensional (3D) integrated systems.

#### **5. Resonance and damping in 3D power distribution network**

There may be resonance oscillations in the power distribution network by adding on-chip decoupling capacitance (Bakoglu et al., 1990). A three-dimensional (3D) power distribution network has lower resonance frequency as compared to its two-dimensional (2D) counterpart (Jain et al., 2008). The resonance oscillations produced this way may cause worst case noise accumulation during subsequent clock cycles if not damped in a proper way. The on-chip decoupling capacitance should therefore be selected with a significant ESR (effective series resistance) in order to damp the resonance oscillations. The logic load on each die may have a resonance frequency as a result of the interaction between inductance of the power distribution TSV pairs and decoupling capacitance across the logic load. The damping is only required in the frequency domain around the resonance frequency, rather than at all the frequencies, therefore decoupling capacitance should be selected to have maximum ESR (effective series resistance) around the resonance frequency. The peak-to-peak ground noise on a power distribution TSV pair is given by (Larsson, 1998) through the following equation, assuming that TSV pair forms an under-damped system with damping factor less than one:

$$
\Delta \upsilon\_{pp} = \Delta \upsilon \left( 1 + \mathbf{e} \stackrel{\overline{\kappa}^{\zeta}}{\sqrt{1 \cdot \zeta^2}} \right)
$$

Where

218 VLSI Design

load capacitance to either the positive supply or ground (Dally & Poulton, 1998). Thus, most of the time these output loads serve as symbiotic bypass capacitors that help maintain the supply voltage during current transients (Dally & Poulton, 1998). The method of calculating the symbiotic bypass capacitance is also given by (Dally & Poulton, 1998). The symbiotic bypass capacitance, therefore, enhances the strength of the intentional on-chip decoupling capacitance. However, too large decoupling capacitance reduces the resonance frequency of the power distribution network. Therefore, there is always a tradeoff between the resonance

> Angular frequency (log) (a)

*total L*

max

With decoupling capacitance

ω= total R

Without decoupling capacitance

> *t et* arg *total Z L*

> > ωmax

Fig. 4. (a) Frequency response of the impedance of a power distribution network without decoupling capacitance. (b) Frequency response of the impedance of a power distribution

r

ω=

(b)

Angular frequency (log)

1 *LC*

The decoupling capacitors integrated into the Si substrate can provide high capacitance at low cost (Sharma et al., 2008). The integrated decoupling capacitors are famous for comparatively low effective series resistance and inductance at high frequency. The effective

network with decoupling capacitance (Jakushokas et al., 2011).

**4.2 Using integrated decoupling capacitance for 3D chip stack** 

frequency and the amount of decoupling capacitance.

Impedance (log)

Ztarget

total R

Ztarget

total R

Impedance (log)

*pp* Δ*v* = Peak-to-peak ground noise on TSV pair.

Δ*v* = Peak ground noise on TSV pair.

$$\mathcal{L} = \frac{\mathbf{R}\_{\text{TSV}}^{\text{eff}}}{2} \sqrt{\frac{\mathbf{C}\_{\text{dec}}}{L\_{\text{TSV}}^{\text{eff}}}} = \text{Damping factor for the power distribution TSV pair.} $$

eff RTSV = Effective series resistance associated with a power distribution TSV pair.

*eff TSV L* = Effective series inductance associated with a power distribution TSV pair.

*Cdec* = On-Chip decoupling capacitance associated with a decoupling capacitance.

The performance and reliability of a three-dimensional (3D) power distribution network also depends on the magnitude and duration of the resonance oscillations. These oscillations must be controlled or significantly damped, otherwise noise accumulation will take place at subsequent clock cycles. The damping factor should have significant value in order to suppress the resonance oscillations. The effective resistance of a power distribution TSV pair should be kept much higher than the effective inductance of the power distribution TSV pair in order to increase the value of the damping factor.

Switching Noise in 3D Power Distribution Networks: An Overview 221

On-chip switching noise for a three-dimensional (3D) power distribution network has deleterious effects on power distribution network itself as well the active devices. The extent of switching noise is related to the TSV density on one hand, whereas the integration density of on-chip devices on the other hand. Peaks of the switching noise largely depend on effective inductance of the power distribution network at high frequencies of the order of GHz. Therefore, efficient implementation of on-chip decoupling capacitance along with other on-chip inductance reduction techniques at high frequency is necessary to overcome the switching noise. In addition to that some accurate and efficient modeling techniques are also necessary for early estimation of the switching noise in order to lay down the rest of the

The author would like to acknowledge European Union research funding under grant FP7- ICT-215030 (ELITE) of the 7th framework program and Higher Education Commission

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**7. Summary and future work** 

**8. Acknowledgment** 

**9. References** 

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