**2. Signaling schemes**

Electrical signaling schemes, which have become one of the most important topics in digital design and a hot topic in research, are the techniques used in the transmission of digital signals from one place to another through an interconnection (Dally & Poulton, 1998). Typical medias for the transmitted signals are on-chip, PCB and backplane interconnections as well as cable lines.

Electrical signaling schemes are classified into voltage mode and current mode signaling schemes depending on the signal carriers of the data through the interconnection. Besides, signaling schemes are also grouped into single ended, fully differential, pseudo differential and incremental signaling (Juan, 2007). In this section electrical signaling schemes are presented and the advantages of current mode over voltage mode are enlisted.

### **2.1 Voltage mode signaling**

In Fig. 1 the model for a voltage mode signaling scheme is shown where the line driver is represented by a voltage source *VDD* that corresponds to the value of the voltage swing. The resistance *RS* represents the output impedance of the driver and the transitions between logic states is achieved by changing the position of the switch. Thus, these logic states, namely 1 and 0, are represented by two supply voltage levels. The circuit drives the output signal through the transmission line with characteristic impedance *ZO* to the far end of it where a CMOS inverter compares the received voltage against a voltage reference derived from the power supply. Finally the voltage source *VN* represents the power supply noise generated between the transmitter and the receiver at both ends of the line which, in fact, deteriorates the signal integrity at the far end.

An important property in voltage mode signaling is that due to the large swing of the signal the noise margins are also large. Even so, special care must be taken in the design of such circuits because of the swing dependent noise sources that are added to the data signals.

Fig. 1. Voltage mode signaling modeling.

Some realizations of circuits for voltage mode signaling are presented in (Ramachandran N. et. al., 2003),(Dehon et. al., 1993),(Deutschmann B. & Ostermann T., 2003), (Svensson C. & Yuan J., 1991), (Choy C. S. et. al., 1997), (Shin S. K. et. al., 2005) and (Balatsos A., 1998). The simplest voltage mode signaling circuit is shown in Fig. 2. It consists of an inverter stage at the near end of the channel where each transistor acts as a switch that directs the output node to the respective rail voltage (*VDD* through *M*<sup>1</sup> and *VSS* through *M*2). Also, it is important to say that at any time one transistor of the circuit is inactive while the other is active. As a consequence the signal transmitted through the channel is the voltage at the output *VO* of the 2 Will-be-set-by-IN-TECH

Electrical signaling schemes, which have become one of the most important topics in digital design and a hot topic in research, are the techniques used in the transmission of digital signals from one place to another through an interconnection (Dally & Poulton, 1998). Typical medias for the transmitted signals are on-chip, PCB and backplane interconnections as well as cable

Electrical signaling schemes are classified into voltage mode and current mode signaling schemes depending on the signal carriers of the data through the interconnection. Besides, signaling schemes are also grouped into single ended, fully differential, pseudo differential and incremental signaling (Juan, 2007). In this section electrical signaling schemes are

In Fig. 1 the model for a voltage mode signaling scheme is shown where the line driver is represented by a voltage source *VDD* that corresponds to the value of the voltage swing. The resistance *RS* represents the output impedance of the driver and the transitions between logic states is achieved by changing the position of the switch. Thus, these logic states, namely 1 and 0, are represented by two supply voltage levels. The circuit drives the output signal through the transmission line with characteristic impedance *ZO* to the far end of it where a CMOS inverter compares the received voltage against a voltage reference derived from the power supply. Finally the voltage source *VN* represents the power supply noise generated between the transmitter and the receiver at both ends of the line which, in fact, deteriorates

An important property in voltage mode signaling is that due to the large swing of the signal the noise margins are also large. Even so, special care must be taken in the design of such circuits because of the swing dependent noise sources that are added to the data signals.

Some realizations of circuits for voltage mode signaling are presented in (Ramachandran N. et. al., 2003),(Dehon et. al., 1993),(Deutschmann B. & Ostermann T., 2003), (Svensson C. & Yuan J., 1991), (Choy C. S. et. al., 1997), (Shin S. K. et. al., 2005) and (Balatsos A., 1998). The simplest voltage mode signaling circuit is shown in Fig. 2. It consists of an inverter stage at the near end of the channel where each transistor acts as a switch that directs the output node to the respective rail voltage (*VDD* through *M*<sup>1</sup> and *VSS* through *M*2). Also, it is important to say that at any time one transistor of the circuit is inactive while the other is active. As a consequence the signal transmitted through the channel is the voltage at the output *VO* of the

**S R**

**channel**

**OZ**

**NV**

presented and the advantages of current mode over voltage mode are enlisted.

**2. Signaling schemes**

**2.1 Voltage mode signaling**

the signal integrity at the far end.

**DD V**

Fig. 1. Voltage mode signaling modeling.

lines.

inverter and can be computed with equation (1)for rising edge signal and (2) for falling edge, (Juan, 2007).

Fig. 2. Voltage mode signaling typical circuit.

$$\mathbf{C}\_{L}\frac{dv\_{o}(t)}{dt} + \frac{v\_{o}(t) - V\_{DD}}{R\_{p}} - \mathbf{C}\_{L}V\_{OL}\delta(t) = 0\tag{1}$$

$$\mathbf{C}\_{L}\frac{dv\_{o}(t)}{dt} + \frac{v\_{o}(t)}{R\_{\text{fl}}} - \mathbf{C}\_{L}V\_{OH}\delta(t) = 0\tag{2}$$

In equations (1) and (2) the constants *Rn* and *Rp* are the resistances of the NMOS and PMOS transistor channels when they are biased in the triode region. *CL* is the load capacitance of the driver, *VOL* and *VOH* are the voltages that represent the logic states 0 and 1. Finally, the products *CLVOLδ*(*t*) and *CLVOHδ*(*t*) are the contribution of the initial voltage for the processes of charging and discharging respectively.

The power consumption for voltage mode signaling systems is shown in equation (3), where *κ* is the switching activity coefficient. It is clear that the dependence with the frequency represents a disadvantage for high frequency applications.

$$P \approx \kappa \mathbb{C}\_{\mathbb{C}} V\_{\text{DD}}^2 f \tag{3}$$

In the following subsections advantages and limitations of various voltage mode signalling schemes, such as single ended, fully differential, pseudo differential and incremental, are presented. This classification is obtained from (Juan, 2007).

#### **2.1.1 Single ended signaling**

In single ended signaling, only one conductor per channel is needed to carry the signal to the receiver side of the system. As shown in Fig. 3(a), the signal arriving to the far end of the line contains both the transmitted one and a noise component that is generated by the devices

**Vcm**


Fig. 4. Fully differential voltage mode signaling

**S V**

considered as receivers then noise components can be eliminated.

**S1 V**

**S4 V**

**R1 V**

**channel**

Impedance Matching in VLSI Systems 71

**channel**

form the closed loop shown with the dashed line in the Fig. 4. Compared with the one in single ended, the area occupied by this loop is small due to the proximity of the conductors. As a consequence, the electromagnetic coupling with other channels is small. Finally, the most important shortcoming of the differential signaling systems is the occupied area by the two

The pseudo differential signaling for voltage mode links is shown in Fig. 5, it is, in essence, a combination of the single ended and the differential signaling systems. In the pseudo differential scheme a single conductor is used as a reference for a group of signal paths. A common number for this group is four. As in fully differential signaling, the physical lines running from the transmitter to the receiver are so close between them that the induced noise *Vni* is considered the same in all of them. In consequence, if differential comparators are

**channel S1 n1 V V+**

**Tx Rx**

**channel S4 n4 V V+**

**channel R1 nR1 V V+**

It is clear that the main advantage of pseudo differential links is the reduced number of conductors that it needs. Unfortunately, the use of a single conductor as a reference signal also represents a drawback, because the area for the signal loops is increased. As a consequence, the channel inductance is larger compared to that in the fully differential approach. A solution for this drawback is presented in (Carusone A. et. al., 2001), where an incremental signaling

**<sup>S</sup> <sup>V</sup>** -

**Cin+**

**Cin-**

**<sup>S</sup> <sup>n</sup> V V+**

+ **<sup>S</sup> <sup>n</sup> V V+**

**S V+**

**2.1.3 Pseudo differential signaling**

**<sup>1</sup> IN**

**<sup>2</sup> IN**

**R1 IN**

Fig. 5. Pseudo differential voltage mode signaling

approach with high signal integrity is presented.

lines.

that are near to the conductor. This signal is compared against a reference signal *VREF* that is generated locally in the receiver.

Fig. 3. (a) Single ended signaling in voltage mode; (b) input output voltage examples

In Fig. 3(b) the input and output voltage examples for a single ended voltage mode link are shown. Due to the single ended characteristic of the system the noise can not be rejected by the comparator and, in consequence, the output presents unwanted error symbols. That is why such systems are susceptible to coupled noise. In addition, in Fig. 3(a) the dotted line shows the path of the signal in the interconnection which goes from the driver to the receiver through the line and returns usually through the ground planes. The capacitor *Cin* is the input impedance of the comparator. This path represents a large area loop that results in high level electromagnetic emissions that affect devices located close to the channel.

#### **2.1.2 Fully differential signaling**

The fully differential signaling for voltage mode links is shown in Fig. 4. The main difference compared with the single ended scheme is that it uses two interconnections to carry the signal to the far end of the line. Another important characteristic is that conductors are so close to each other that the induced noise tends to be the same in each one. As a consequence the signals that are present at the line far ends are the transmitted positive voltage *V*<sup>+</sup> *<sup>S</sup>* plus the induced potential *Vn*, i.e. *V*<sup>+</sup> *<sup>S</sup>* + *Vn* and, in the same way, the signal in the other polarity is *V*− *<sup>S</sup>* + *Vn*. At the receiver side the determination of the symbol is done by means of the voltage comparator configured in a differential way, because of this, the noise component is cancelled. As a conclusion, it can be said that fully differential configuration for signaling provides excellent common mode noise immunity.

By analyzing Fig. 4 the signals that charge the input capacitors *Cin*<sup>+</sup> and *Cin*<sup>−</sup> are the time varying differential currents that flow in opposite ways in each conductor. These currents 4 Will-be-set-by-IN-TECH

that are near to the conductor. This signal is compared against a reference signal *VREF* that is

**channel OZ**

**(a)**

**(B)**

In Fig. 3(b) the input and output voltage examples for a single ended voltage mode link are shown. Due to the single ended characteristic of the system the noise can not be rejected by the comparator and, in consequence, the output presents unwanted error symbols. That is why such systems are susceptible to coupled noise. In addition, in Fig. 3(a) the dotted line shows the path of the signal in the interconnection which goes from the driver to the receiver through the line and returns usually through the ground planes. The capacitor *Cin* is the input impedance of the comparator. This path represents a large area loop that results in high level

The fully differential signaling for voltage mode links is shown in Fig. 4. The main difference compared with the single ended scheme is that it uses two interconnections to carry the signal to the far end of the line. Another important characteristic is that conductors are so close to each other that the induced noise tends to be the same in each one. As a consequence the signals that are present at the line far ends are the transmitted positive voltage *V*<sup>+</sup>

*<sup>S</sup>* + *Vn*. At the receiver side the determination of the symbol is done by means of the voltage comparator configured in a differential way, because of this, the noise component is cancelled. As a conclusion, it can be said that fully differential configuration for signaling

By analyzing Fig. 4 the signals that charge the input capacitors *Cin*<sup>+</sup> and *Cin*<sup>−</sup> are the time varying differential currents that flow in opposite ways in each conductor. These currents

*<sup>S</sup>* + *Vn* and, in the same way, the signal in the other polarity

Fig. 3. (a) Single ended signaling in voltage mode; (b) input output voltage examples

electromagnetic emissions that affect devices located close to the channel.

**REF V**

*<sup>S</sup>* plus

**Cin**

**<sup>S</sup> <sup>n</sup> V V+**

**S V**

**VS+Vn**

generated locally in the receiver.

**V REF**

**2.1.2 Fully differential signaling**

the induced potential *Vn*, i.e. *V*<sup>+</sup>

provides excellent common mode noise immunity.

is *V*−

Fig. 4. Fully differential voltage mode signaling

form the closed loop shown with the dashed line in the Fig. 4. Compared with the one in single ended, the area occupied by this loop is small due to the proximity of the conductors. As a consequence, the electromagnetic coupling with other channels is small. Finally, the most important shortcoming of the differential signaling systems is the occupied area by the two lines.

#### **2.1.3 Pseudo differential signaling**

The pseudo differential signaling for voltage mode links is shown in Fig. 5, it is, in essence, a combination of the single ended and the differential signaling systems. In the pseudo differential scheme a single conductor is used as a reference for a group of signal paths. A common number for this group is four. As in fully differential signaling, the physical lines running from the transmitter to the receiver are so close between them that the induced noise *Vni* is considered the same in all of them. In consequence, if differential comparators are considered as receivers then noise components can be eliminated.

Fig. 5. Pseudo differential voltage mode signaling

It is clear that the main advantage of pseudo differential links is the reduced number of conductors that it needs. Unfortunately, the use of a single conductor as a reference signal also represents a drawback, because the area for the signal loops is increased. As a consequence, the channel inductance is larger compared to that in the fully differential approach. A solution for this drawback is presented in (Carusone A. et. al., 2001), where an incremental signaling approach with high signal integrity is presented.

**VBIAS**

which make them suitable for high speed environments.

consumption which represents a benefit in high frequency applications.

are presented. They are called unipolar and bipolar current mode signalling.

**M1**

**Dat**

Fig. 7. Current mode signaling circuit.

**2.2.1 Unipolar current mode signaling**

*IR*.

**SI**

(4),it can be concluded that current mode signalling systems have small propagation delay

An important topic regarding electronic systems is power consumption. In particular, it is essential for signaling systems because they tend to consume big quantities of power. The power consumption in current mode circuits can be calculated by using equation (5), where it can be seen that there is not a dependence with frequency. Moreover, has only static power

In the following subsections two of the most important realizations for current mode signaling

The symbol codification in unipolar current mode signaling (UCMS) is shown in Fig. 8, where a logical 1 is represented by the current *I*<sup>1</sup> and the logical 0 is represented by the absence of current. In this system the transmitter offset current is represented by *IX*<sup>0</sup> and the possible values for the symbol are represented by the black area (it is clear that a zero current is easy to implement, that is why the black area corresponding to the symbol 0 is small). The receiver offset *Ir*<sup>0</sup> and sensitivity *Irs* are also sketched in the scheme, they are near the reference current

In Fig. 9 the unipolar current mode signaling system is depicted. The UCMS block represents the driver which is, in this case, the one shown in Fig. 7. As stated before, the driver sinks a current *I* from one line each time, i. e. there is no signal flowing in both conductors at the

**Dat VOutB**

**R R**

**VDDO VDDO**

Impedance Matching in VLSI Systems 73

**Z0**

**VOut**

**M2**

**Z0**

*P* ≈ *I* ∗ *VDD* (5)

#### **2.2 Current mode signaling**

A model for a current mode signaling system is shown in Fig. 6. In this case the line driver is represented by a current source *IS* and the couple of switches that direct the current trough the line. At the far end of the link a resistor *RL* is connected between the reference and signal lines and its purpose is not only to match the transmission line impedance but also to convert the current into voltage. This voltage is then changed to digital by the differential-mode comparator at the receiver side.

Fig. 6. Current mode signaling modeling.

In current mode signaling systems the symbols are represented by branch current signals. For the case of Fig. 6 when switches are in the upper side a current *IS* flows through the line from transmitter to receiver and, in the ideal case, through the load resistor. In this case a voltage *VL* = *IS* ∗ *RL* is present at the input of the comparator. In the opposite case, when switches are in the lower side, the current flows from receiver to driver, then the voltage drop is *VL* = −*IS* ∗ *RL*. In consequence, the total voltage swing at the far end of the link is *Vsw* = 2 ∗ *IS* ∗ *RL*.

One of the most basic drivers for current mode signaling systems is shown in Fig. 7 where the current *IS* is directed to one branch or to the other just by switching the transistors *M*<sup>1</sup> and *M*2. The control of this action is achieved by the digital data to be transmitted *Dat* and *Dat* ¯ . The resistances *R* are implemented to match the characteristic impedance *Z*<sup>0</sup> of the channel.

One of the most important advantages of current mode signaling is that the information is represented by branch currents and, due to the low impedance characteristic of the transmission media, the voltage swing for these systems is small even though the current signals are big. As a consequence, circuits can operate with a low voltage supply and current swings are not affected by the variations on the supply voltages (as opposed to voltage mode signaling). From the argument of swing invariance to supply changes, it can be concluded that current mode signaling has superior signal integrity compared with the voltage mode one.

An important issue in signaling systems is the propagation delay and is directly related to the rising and falling time of the signal. For a capacitive node, the rising(falling) time is shown in (4), (Juan, 2007), where *I* is the average current charging and discharging the node, *Cn* is the node capacitance and Δ*Vn* is the node voltage swing.

$$
\Delta t = \frac{C\_n \Delta V\_n}{I} \tag{4}
$$

From equation (4) it can be inferred that if a small Δ*t* is needed then the voltage swing Δ*Vn* must be minimized or the charging/discharging current must be big. Then, from equation 6 Will-be-set-by-IN-TECH

A model for a current mode signaling system is shown in Fig. 6. In this case the line driver is represented by a current source *IS* and the couple of switches that direct the current trough the line. At the far end of the link a resistor *RL* is connected between the reference and signal lines and its purpose is not only to match the transmission line impedance but also to convert the current into voltage. This voltage is then changed to digital by the differential-mode

**channel**

In current mode signaling systems the symbols are represented by branch current signals. For the case of Fig. 6 when switches are in the upper side a current *IS* flows through the line from transmitter to receiver and, in the ideal case, through the load resistor. In this case a voltage *VL* = *IS* ∗ *RL* is present at the input of the comparator. In the opposite case, when switches are in the lower side, the current flows from receiver to driver, then the voltage drop is *VL* = −*IS* ∗ *RL*. In consequence, the total voltage swing at the far end of the link is

One of the most basic drivers for current mode signaling systems is shown in Fig. 7 where the current *IS* is directed to one branch or to the other just by switching the transistors *M*<sup>1</sup> and *M*2. The control of this action is achieved by the digital data to be transmitted *Dat* and *Dat* ¯ . The resistances *R* are implemented to match the characteristic impedance *Z*<sup>0</sup> of the channel. One of the most important advantages of current mode signaling is that the information is represented by branch currents and, due to the low impedance characteristic of the transmission media, the voltage swing for these systems is small even though the current signals are big. As a consequence, circuits can operate with a low voltage supply and current swings are not affected by the variations on the supply voltages (as opposed to voltage mode signaling). From the argument of swing invariance to supply changes, it can be concluded that current mode signaling has superior signal integrity compared with the voltage mode

An important issue in signaling systems is the propagation delay and is directly related to the rising and falling time of the signal. For a capacitive node, the rising(falling) time is shown in (4), (Juan, 2007), where *I* is the average current charging and discharging the node, *Cn* is the

<sup>Δ</sup>*<sup>t</sup>* <sup>=</sup> *Cn*Δ*Vn*

From equation (4) it can be inferred that if a small Δ*t* is needed then the voltage swing Δ*Vn* must be minimized or the charging/discharging current must be big. Then, from equation

*<sup>I</sup>* (4)

**<sup>L</sup> <sup>O</sup> <sup>R</sup> <sup>Z</sup>**

**2.2 Current mode signaling**

comparator at the receiver side.

**SI**

Fig. 6. Current mode signaling modeling.

node capacitance and Δ*Vn* is the node voltage swing.

*Vsw* = 2 ∗ *IS* ∗ *RL*.

one.

Fig. 7. Current mode signaling circuit.

(4),it can be concluded that current mode signalling systems have small propagation delay which make them suitable for high speed environments.

An important topic regarding electronic systems is power consumption. In particular, it is essential for signaling systems because they tend to consume big quantities of power. The power consumption in current mode circuits can be calculated by using equation (5), where it can be seen that there is not a dependence with frequency. Moreover, has only static power consumption which represents a benefit in high frequency applications.

$$P \approx I \ast V\_{\rm DD} \tag{5}$$

In the following subsections two of the most important realizations for current mode signaling are presented. They are called unipolar and bipolar current mode signalling.

#### **2.2.1 Unipolar current mode signaling**

The symbol codification in unipolar current mode signaling (UCMS) is shown in Fig. 8, where a logical 1 is represented by the current *I*<sup>1</sup> and the logical 0 is represented by the absence of current. In this system the transmitter offset current is represented by *IX*<sup>0</sup> and the possible values for the symbol are represented by the black area (it is clear that a zero current is easy to implement, that is why the black area corresponding to the symbol 0 is small). The receiver offset *Ir*<sup>0</sup> and sensitivity *Irs* are also sketched in the scheme, they are near the reference current *IR*.

In Fig. 9 the unipolar current mode signaling system is depicted. The UCMS block represents the driver which is, in this case, the one shown in Fig. 7. As stated before, the driver sinks a current *I* from one line each time, i. e. there is no signal flowing in both conductors at the

0 1

**1 -I**

Fig. 10. Symbols in bipolar current mode signaling.

the differential mode comparator at the receiver.

**<sup>1</sup> IN**

**<sup>1</sup> IN**

driver size in a considerably amount.

**2.3 Specifications for signaling standards**

conditions.

Fig. 11. Bipolar current mode signaling system.

**R I**

Impedance Matching in VLSI Systems 75

**<sup>1</sup> <sup>0</sup> <sup>I</sup>**

**in ÄV**

**X0 I**

<sup>+</sup> **r0 rs I I <sup>2</sup>**

stated before in this section. This property allows these systems to have a low electromagnetic emission because field components are cancelled due to the opposite directions of the current. Another characteristic of bipolar signaling is that the load resistance *RT* is placed between the interconnections in such a way that current signals generate a voltage which is compared by

**Tx Rx**

**I**

**channel**

**BCMS RT**

**0 I**

**0 I**

details on this approach are presented in (Wang T. & Yuan F., 2007).

similar way, the noise margin for a logic low is *NML* = *VIL* − *VOL*.

**channel**

Bipolar current mode signalling systems are also called low voltage differential signalling (LVDS) and a typical driver is shown in Fig. 12 where the both switches direct the signal to the corresponding conductor according to the data input *IN*1. A disadvantage of LVDS links is that both switches current mode sources are implemented with transistors. Then, there are four transistors between the supply voltage and the ground, which is not so desirable in low supply voltage applications. Also common mode feedback circuits are needed increasing the

When a N-bit parallel link is needed, a group of N bipolar current mode drivers are put together in a special array. This array is called current mode incremental signaling and specific

The specifications for the signaling standards are essential in communication because they establish the voltage levels so that the driver and receiver agree with the logic high and low

An illustration of the specifications for digital signaling is shown in Fig. 13. The voltages *VH* and *VL* are the expected voltage levels for the logic values 1 and 0 respectively. In the transmitter side, the driver's goal is to have a high logic level that goes above a minimum voltage level, i.e. *V*0*<sup>H</sup>* ≤ *VH* and at the receiver side the accepted voltages must go above *VIH*. Then the noise margin for the high logic level can be written as *NMH* = *V*0*<sup>H</sup>* − *VIH*. In a

Fig. 8. Symbols in unipolar current mode signaling.

same time. At the far end of the lines, termination resistors *RT* are placed in order to generate a differential voltage at the input of the receiver. This voltage is given by the difference between the positive and the negative inputs of the comparator as shown in equation (6).

$$
\Delta V\_{in} = |V\_{in}^{+} - V\_{in}^{-}| = |V\_{DD} - R\_T I - V\_{DD}| = R\_T I \tag{6}
$$

Fig. 9. Unipolar current mode signaling system.

As stated before, the variations in the voltage supply and in the ground sources do not have effect in the current flowing through the channel. Furthermore, due to the differential configuration at the receiver side, the common mode noise is eliminated. The disadvantage in unipolar signalling is that electromagnetic emission exists because only one conductor is carrying the current each time.

#### **2.2.2 Bipolar current mode signaling**

The symbol codification in bipolar current mode signaling is presented in Fig. 10. In this case the logical 1 is represented, as in unipolar signaling, by the current *I*1. The difference is that the logical 0 is represented by the current −*I*1.

By comparing Fig. 10 with Fig. 8 it can be appreciated that the allowed area for the logical 1 offset at the receiver has decreased. The reason for this is that the area of the offset for the logical 0 has to be increased because the current that represents it is now different from zero. The receiver offset *Ir*<sup>0</sup> and sensitivity *Irs* are also sketched in the scheme, they are near the reference current *IR* which is centered in zero amperes in bipolar signaling.

An example of bipolar current mode signaling systems is depicted in Fig. 11. It can be seen in the figure that current flows always in both interconnections but in opposite directions, as 8 Will-be-set-by-IN-TECH

**R I**

same time. At the far end of the lines, termination resistors *RT* are placed in order to generate a differential voltage at the input of the receiver. This voltage is given by the difference between

**Tx Rx**

**channel**

**channel**

As stated before, the variations in the voltage supply and in the ground sources do not have effect in the current flowing through the channel. Furthermore, due to the differential configuration at the receiver side, the common mode noise is eliminated. The disadvantage in unipolar signalling is that electromagnetic emission exists because only one conductor is

The symbol codification in bipolar current mode signaling is presented in Fig. 10. In this case the logical 1 is represented, as in unipolar signaling, by the current *I*1. The difference is that

By comparing Fig. 10 with Fig. 8 it can be appreciated that the allowed area for the logical 1 offset at the receiver has decreased. The reason for this is that the area of the offset for the logical 0 has to be increased because the current that represents it is now different from zero. The receiver offset *Ir*<sup>0</sup> and sensitivity *Irs* are also sketched in the scheme, they are near the

An example of bipolar current mode signaling systems is depicted in Fig. 11. It can be seen in the figure that current flows always in both interconnections but in opposite directions, as

reference current *IR* which is centered in zero amperes in bipolar signaling.

**<sup>1</sup> <sup>1</sup> <sup>I</sup> <sup>I</sup>**

**X0 I**

*in* | = |*VDD* − *RT I* − *VDD*| = *RT I* (6)

**in ÄV**

**RT RT**

0 1

<sup>+</sup> **r0 rs I I <sup>2</sup>**

the positive and the negative inputs of the comparator as shown in equation (6).

*in* − *V*<sup>−</sup>

**0 I**

**<sup>2</sup> <sup>0</sup>**

Fig. 8. Symbols in unipolar current mode signaling.

<sup>Δ</sup>*Vin* <sup>=</sup> <sup>|</sup>*V*<sup>+</sup>

**UCMS**

**<sup>1</sup> IN**

**<sup>1</sup> IN**

carrying the current each time.

**2.2.2 Bipolar current mode signaling**

the logical 0 is represented by the current −*I*1.

Fig. 9. Unipolar current mode signaling system.

Fig. 10. Symbols in bipolar current mode signaling.

stated before in this section. This property allows these systems to have a low electromagnetic emission because field components are cancelled due to the opposite directions of the current. Another characteristic of bipolar signaling is that the load resistance *RT* is placed between the interconnections in such a way that current signals generate a voltage which is compared by the differential mode comparator at the receiver.

Fig. 11. Bipolar current mode signaling system.

Bipolar current mode signalling systems are also called low voltage differential signalling (LVDS) and a typical driver is shown in Fig. 12 where the both switches direct the signal to the corresponding conductor according to the data input *IN*1. A disadvantage of LVDS links is that both switches current mode sources are implemented with transistors. Then, there are four transistors between the supply voltage and the ground, which is not so desirable in low supply voltage applications. Also common mode feedback circuits are needed increasing the driver size in a considerably amount.

When a N-bit parallel link is needed, a group of N bipolar current mode drivers are put together in a special array. This array is called current mode incremental signaling and specific details on this approach are presented in (Wang T. & Yuan F., 2007).

#### **2.3 Specifications for signaling standards**

The specifications for the signaling standards are essential in communication because they establish the voltage levels so that the driver and receiver agree with the logic high and low conditions.

An illustration of the specifications for digital signaling is shown in Fig. 13. The voltages *VH* and *VL* are the expected voltage levels for the logic values 1 and 0 respectively. In the transmitter side, the driver's goal is to have a high logic level that goes above a minimum voltage level, i.e. *V*0*<sup>H</sup>* ≤ *VH* and at the receiver side the accepted voltages must go above *VIH*. Then the noise margin for the high logic level can be written as *NMH* = *V*0*<sup>H</sup>* − *VIH*. In a similar way, the noise margin for a logic low is *NML* = *VIL* − *VOL*.

Stan *VDDQ V*0*<sup>L</sup> V*0*<sup>H</sup>* Termi Driver

Impedance Matching in VLSI Systems 77

TTL 5 ± 10% 0.4 2.4 None PP LVTTL 3.3 ± 10% 0.4 2.4 None PP GTL 0.4 *Rsystem* OD HSTL 1.5 <sup>±</sup> 0.1 0.4 *VDDQ* <sup>−</sup> 0.4 <sup>1</sup> PP ECL −5.2 ∓ 5% -1.810 -1.620 -1.025 -0.880 50Ω(−2*V*) CM PECL 5 ± 5% 3.190 3.380 3.975 4.120 50Ω CM LVPECL 3.3 ± 5% 1.490 1.680 2.275 2.420 50Ω CM LVDS 0.925 1.474 50Ω CM

accomplished by systems with terminations, reduced voltage swings and with differential

As stated in previous sections, impedance matching techniques must be implemented in order to reduce return losses. It has been also shown that the fastest signaling standards implement termination resistors in order to match the interconnection impedance. Four of the most common termination techniques are shown in Fig. 14, (Brooks D., 2003). The first technique is the parallel termination (Fig. 14(a)) where a single resistor is connected either to ground or to *VDD* and its value is equal to the characteristic impedance of the line. Although this is one of the most used methods, its disadvantage is that the current is always flowing through it, thus

The second termination technique is shown in Fig. 14(b), it is called Thevenin termination and consists of a couple of resistors, one connected to ground and the other to *VDD*. The advantage of this scheme is that it provides pull up and pull down functions improving noise margins in some cases. The drawback of this system is that it is not easy to find the optimum values of the resistors in order to match the characteristic impedance of the line. The third technique is the AC termination and is depicted in Fig. 14(c). It is composed by a series connection of a resistor and a capacitor. Here the capacitance blocks the DC signals in order to reduce the power consumption but distortion can appear when high speed links are considered. Finally the series termination scheme is presented in Fig. 14(d). This is one of the most often used

Unfortunately the techniques presented in Fig. 14 are implemented with fixed devices and process, temperature and voltage supply variations are not taken into account for the design of such systems. In the following subsections some techniques are presented in which variable terminators are implemented to automatically adapt the impedance of the transmission line.

An important issue in automatic impedance matching is the control technique used in the adaptation process. It takes the reference signal which indicates the desired value of the impedance and the signal that represents the actual value of the impedance and process them in order to have the same value. The output of the circuit sets the value of the impedance that

dard Min Max Min Max nation

Table 1. Driver specifications for signaling standards

increasing the power consumption of the system.

techniques, specially in voltage mode drivers.

matches the interconnection.

**3.1 Automatic impedance matching control techniques**

**3. Impedance matching techniques**

configuration.

Fig. 12. Low voltage differential signaling driver.

Fig. 13. Specifications for digital signaling.

In table 1 voltage specifications for some common standards are enlisted (Young B., 2001). Although some of them are current mode, the values are presented in voltage which represent the drop on the termination resistors. Another important issue is that the standards are in order from the lowest to the highest speed that can be achieved, then higher speeds are 10 Will-be-set-by-IN-TECH

**0 I**

**<sup>1</sup> IN**

**<sup>1</sup> IN**

**0 I**

**Time**

In table 1 voltage specifications for some common standards are enlisted (Young B., 2001). Although some of them are current mode, the values are presented in voltage which represent the drop on the termination resistors. Another important issue is that the standards are in order from the lowest to the highest speed that can be achieved, then higher speeds are

**<sup>1</sup> IN**

Fig. 12. Low voltage differential signaling driver.

**HV 0H V IH V**

**IL V 0L V LV**

Fig. 13. Specifications for digital signaling.

**Voltage**

**<sup>1</sup> IN**

**channel**

**channel**


Table 1. Driver specifications for signaling standards

accomplished by systems with terminations, reduced voltage swings and with differential configuration.
