**5. Knowledge-based impedace matching control design**

Formulation of a complete mathematical model for impedance mismatch is a very complex process, since the parameters involved depend on many factors like process variations, length variations of the interconnection lines, temperature, etc. In this sense, knowledge based algorithms represent interesting alternatives which can be explored when looking for solutions to the impedance mismatch problem using adaptive schemes.

Fuzzy logic formalizes the treatment of vague knowledge, and approximates reasoning through inference rules (Zadeh, L. 1999). It establishes the mechanisms to generate practical solutions to problems where traditional methods, which may require precise mathematical models, may not be suitable. Because of this, fuzzy control represents a good alternative to solve the impedance mismatch problem through on-chip adaptive mechanisms (Arroyo et al., 2009).

Fig. 31 shows the general structure of the fuzzy controller used to adapt the system. The structure is simple and was designed in UMC 90nm CMOS technology. The membership functions are implemeted using differential pairs, while the multipliers are four-quadrant multipliers. The controller was designed to work in current-mode, therefore the sum operation is simply the sum of the currents in a node. Since the implementation of the divisor circuit is not trivial, a normalizer circuit can be used as an alternative.

fuzzy controller adapts the impedance matching network, leading the system in every case to

Impedance Matching in VLSI Systems 91

In this chapter systems for on-die automatic impedance matching for off-chip signaling were described. A review of different techniques for impedance matching was presented. Based on that, two algorithms were proposed and implemented in order to perform the automatic impedance matching control: the first one is based on the integration of the sign of the impedance matching error and the sign of the coupling branch current, the second one uses a fuzzy controller in the feedback path in order to adapt the impedance of the matching network. Advantages and performance of these algorithms were discussed and proved by

Dally W. J. & Poulton J. W. (1998). *Digital Systems Engineering*, Cambridge University Press.

DeHon A. et. al (1993). Automatic impedance control, *IEEE International Conference on Solid*

Ramachandran N. et. al. (2003), A 3.3-v cmos adaptive analog video line driver with low

distortion performance, *IEEE Journal of Solid-State Circuits*, vol. 38, no. 6, pp. 1051 -

Juan F. (2007). *CMOS Current-Mode Circuits for Data Communications*, Springer.

match the value of the load impedance.

Fig. 34. Normalized mean square error

presenting computer simulations of layout extractions.

*State Circuits*, pp. 164 - 165, Feb. 1993.

**6. Conclusion**

**7. References**

1058.

Fig. 33. Adaptation process of the impedance matching system

Fig. 31. General structure of the fuzzy controller

Fig. 32. Impedance matching system

Fig. 32 depicts a block diagram of the fuzzy control-based scheme for the impedance matching system. In order to allow the impedance matching process, a two port network with a standard *π* configuration is inserted between the source and the load. It is considered that both, the source impedance *ZS* and the load impedance *ZL*, allow complex values in the general case. The reference model is used to generate the reference signal *y*(*t*), which is necessary to obtain the error. The error signal is used as the input to the fuzzy controller and is given by

$$e(t) = v(t)1 - y(t)\tag{25}$$

where *e*(*t*) is the error, *v*(*t*) is the current output of the system and *y*(*t*) is the desired output. The output of the fuzzy controller is used to adaptively change the value of one of the capacitors of the *π* network. The system iterates until the impedance matching condition given by (2) is fulfilled, i.e.

$$\mathbf{Z}\_{\rm L} = \mathbf{Z}\_{\rm out}^\* \tag{26}$$

where (∗) denotes the complex conjugate. It is clear that the fulfillment of this condition implies: *e*(*t*) = 0. Fig. 33 and Fig. 34 show the evolution in time of the absolute value of the adapted impedance and the normalized mean square error, respectively. As can be seen, the 24 Will-be-set-by-IN-TECH

Fig. 32 depicts a block diagram of the fuzzy control-based scheme for the impedance matching system. In order to allow the impedance matching process, a two port network with a standard *π* configuration is inserted between the source and the load. It is considered that both, the source impedance *ZS* and the load impedance *ZL*, allow complex values in the general case. The reference model is used to generate the reference signal *y*(*t*), which is necessary to obtain the error. The error signal is used as the input to the fuzzy controller

where *e*(*t*) is the error, *v*(*t*) is the current output of the system and *y*(*t*) is the desired output. The output of the fuzzy controller is used to adaptively change the value of one of the capacitors of the *π* network. The system iterates until the impedance matching condition

*ZL* = *Z*<sup>∗</sup>

where (∗) denotes the complex conjugate. It is clear that the fulfillment of this condition implies: *e*(*t*) = 0. Fig. 33 and Fig. 34 show the evolution in time of the absolute value of the adapted impedance and the normalized mean square error, respectively. As can be seen, the

*e*(*t*) = *v*(*t*)1 − *y*(*t*) (25)

*out* (26)

Fig. 31. General structure of the fuzzy controller

Fig. 32. Impedance matching system

and is given by

given by (2) is fulfilled, i.e.

fuzzy controller adapts the impedance matching network, leading the system in every case to match the value of the load impedance.

Fig. 33. Adaptation process of the impedance matching system

Fig. 34. Normalized mean square error

### **6. Conclusion**

In this chapter systems for on-die automatic impedance matching for off-chip signaling were described. A review of different techniques for impedance matching was presented. Based on that, two algorithms were proposed and implemented in order to perform the automatic impedance matching control: the first one is based on the integration of the sign of the impedance matching error and the sign of the coupling branch current, the second one uses a fuzzy controller in the feedback path in order to adapt the impedance of the matching network. Advantages and performance of these algorithms were discussed and proved by presenting computer simulations of layout extractions.

#### **7. References**

Dally W. J. & Poulton J. W. (1998). *Digital Systems Engineering*, Cambridge University Press. Juan F. (2007). *CMOS Current-Mode Circuits for Data Communications*, Springer.


**1. Introduction** 

 \*

**5** 

*México* 

**VLSI Design of Sorting Networks** 

*Universidad Veracruzana/Facultad de Instrumentación Electrónica,* 

Although sorting networks have extensively been reported in literature (Batcher, 1962), there are a few references that cover a detailed explanation about their VLSI (Very Large Scale of Integration) realization in CMOS (Complementary Metal-Oxide-Semiconductor) technology (Turan et al., 2003). From an algorithmic point of view, a sorting network is defined as a sequence of compare and interchange operations depending only on the number of elements to be sorted. From a hardware perspective, sorting networks can be visualized as combinatorial circuits where a set of denoted compare-swap (CS) circuits can be connected in accordance to a specific network topology (Knuth, 1997). In this chapter, the design of sorting networks in CMOS technology with applicability to VLSI design is approached at block, transistor, and layout levels. Special attention has been placed to show the hierarchical structure observed in sorting schemes where the so called CS circuit constitutes the fundamental standard cell. The CS circuit is characterized through SPICE simulation making a particular emphasis in the silicon area and delay time parameters. In order to illustrate the inclusion of sorting networks into specific applications, like signal processing and nonlinear function evaluation, two already reported examples of integrated

In an algorithmic context, the CS element is conceived as an ideal operator which is free of the inherent delay time presented when a signal propagates through it. It can be seen as a trivial two-input/two-output component with a general two number sorting capability. Also, it is considered that the CS element works taking in two numbers and, simultaneously, placing the minimum of them at the bottom output, and the maximum at the top output by performing a swap, if necessary (Pursley, 2008). Figure 1 shows the typical Knuth diagram for a CS operator. In this pictorial representation, at the input, the horizontal lines describe

Ana D. Martínez*1*, Joel Ramírez*1*, Jesús S. Orea*1*, Omar Alba*2*, Pedro Julián3, Juan A. Rodríguez3,

*3Universidad Nacional del Sur/ Departamento de Ingeniería Eléctrica y de Computadoras, Argentina* 

circuit designs are provided (Agustin et al., 2011; Jimenez et al., 2011).

**2. Compare-swap block design in CMOS technology** 

*1Universidad Veracruzana/Facultad de Instrumentación Electrónica, México 2Instituto Tecnológico Superior de Xalapa/ Departamento de Electrónica, México* 

Osvaldo Agamennoni3 and Omar D. Lifschitz3

**in CMOS Technology** 

Víctor M. Jiménez-Fernández et al.\*

