**Impedance Matching in VLSI Systems**

Díaz Méndez J. Alejandro1, López Delgadillo Edgar2 and Arroyo Huerta J. Erasmo1 <sup>1</sup>*National Institute for Astrophysics, Optics and Electronics* <sup>2</sup>*Universidad Autónoma de Aguascalientes Mexico*

### **1. Introduction**

66 VLSI Design

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The continuous scaling process into submicrometric dimensions of silicon based devices has allowed the integration of a large number of systems in a single chip. Besides, the operating frequencies of such systems are higher and a large amount of information can be processed in a short period of time. On the other hand, while the core frequencies are increasing, higher data rates for off-chip interconnections become necessary, for example a processor that communicates with the memory in order to process information. Unfortunately, at high rates the signal wave length is comparable with the physical length of the interconnections, because of this, parasitic and transmission line effects have to be taken into account. As a consequence, the transmitted signal integrity is degraded resulting in communication errors (Thierauf S., 2004), (Brooks D., 2003).

It has been shown that, for modern off-chip communication systems, current mode signaling offers several advantages over voltage-mode at high data rates (Juan, 2007), but they need to be matched in impedance to the interconnection line. However, impedance matching requires termination resistors. Moreover, due to the large number of input/output circuits in a single chip, terminations have to be placed on-chip (Fan Y. & Smith J., 2003) so that the PCB area is not increased. One of the most important transmission line effects that degrades signal integrity in these signaling schemes is reflection loss. In this case, signal reflections traveling trough the line are present in either driver to receiver or receiver to driver directions. Unfortunately, it is difficult to achieve perfect matching of impedances due to the large process variations in the fabrication of interconnection lines and the different traces between them (Ramachandran N. et. al., 2003). Also, temperature variations and external effects are present inside and outside the chip. As a conclusion, impedance matching techniques must be developed in order to automatically adapt the impedance variations of the line.

In this chapter systems for on-die automatic impedance matching for off-chip signaling are described. In order to perform the automatic matching operation an algorithm that integrates the sign of the impedance matching error and the sign of the coupling branch current is implemented. The advantage of this algorithm is that it works without interfering with the driver operation. Computer simulations of layout extractions are presented. Also, a system of knowlegde- based impedance matching which avoids the calculation of a complex mathematical model is presented.

inverter and can be computed with equation (1)for rising edge signal and (2) for falling edge,

Impedance Matching in VLSI Systems 69

**M1**

**OV**

**channel**

− *CLVOLδ*(*t*) = 0 (1)

− *CLVOHδ*(*t*) = 0 (2)

*DD f* (3)

**CL**

**M2**

*vo*(*t*) − *VDD Rp*

> *vo*(*t*) *Rn*

In equations (1) and (2) the constants *Rn* and *Rp* are the resistances of the NMOS and PMOS transistor channels when they are biased in the triode region. *CL* is the load capacitance of the driver, *VOL* and *VOH* are the voltages that represent the logic states 0 and 1. Finally, the products *CLVOLδ*(*t*) and *CLVOHδ*(*t*) are the contribution of the initial voltage for the processes

The power consumption for voltage mode signaling systems is shown in equation (3), where *κ* is the switching activity coefficient. It is clear that the dependence with the frequency

*<sup>P</sup>* <sup>≈</sup> *<sup>κ</sup>CCV*<sup>2</sup>

In the following subsections advantages and limitations of various voltage mode signalling schemes, such as single ended, fully differential, pseudo differential and incremental, are

In single ended signaling, only one conductor per channel is needed to carry the signal to the receiver side of the system. As shown in Fig. 3(a), the signal arriving to the far end of the line contains both the transmitted one and a noise component that is generated by the devices

(Juan, 2007).

**IN V**

Fig. 2. Voltage mode signaling typical circuit.

of charging and discharging respectively.

**2.1.1 Single ended signaling**

*CL*

*dvo*(*t*) *dt* <sup>+</sup>

*CL*

represents a disadvantage for high frequency applications.

presented. This classification is obtained from (Juan, 2007).

*dvo*(*t*) *dt* <sup>+</sup>
