K.A. Sumithra Devi

*R.V. College of Engineering, Bangalore Vishweshvaraya Technological University, Karnataka India* 

#### **1. Introduction**

16 VLSI Design

128 VLSI Design

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Due to advent of Very Large Scale Integration (VLSI), mainly due to rapid advances in integration technologies the electronics industry has achieved a phenomenal growth over the last two decades. Various applications of VLSI circuits in high-performance computing, telecommunications, and consumer electronics has been expanding progressively, and at a very hasty pace. Steady advances in semi-conductor technology and in the integration level of Integrated circuits (ICs) have enhanced many features, increased the performance, improved reliability of electronic equipment, and at the same time reduce the cost, power consumption and the system size. With the increase in the size and the complexity of the digital system, Computer Aided Design (CAD) tools are introduced into the hardware design process. The early paper and pencil design methods have given way to sophisticated design entry, verification and automatic hardware generation tools. The use of interactive and automatic design tools significantly increased the designer productivity with an efficient management of the design project and by automatically performing a huge amount of time extensive tasks. The designer heavily relies on software tools for every aspect of development cycle starting from circuit specification and design entry to the performance analysis, layout generation and verification. Partitioning is a method which is widely used for solving large complex problems. The partitioning methodology proved to be very useful in solving the VLSI design automation problems occurring in every stage of the IC design process. But the size and the complexity of the VLSI design has increased over time, hence some of the problems can be solved using partitioning techniques. Graphs and hypergraphs are the natural representation of the circuits, so many problems in VLSI design can be solved effectively either by graph or hyper-graph partitioning. VLSI circuit partitioning is a vital part of the physical design stage. The essence of the circuit partitioning is to divide a circuit into number of sub-circuits with minimum interconnection between them. Which can be accomplished recursively partitioning the circuits into two parts until the desired level of complexity is reached. Partitioning is a critical area of VLSI CAD. In order to build complex digital logic circuits it is often essential to sub-divide multi –million transistor design into manageable pieces. The presence of hierarchy gives rise to natural clusters of cells. Most of the widely used algorithms tend to ignore this clustering and divide the net list in a balanced partitioning and frequently the resulting partitions are not optimal.

The demand for high-speed field-programmable gate array (FPGA) compilation tools has escalated in the deep-sub micron era. Tree partitioning problem is a special case of graph

Algorithms for CAD Tools VLSI Design 131

interconnections between them. This can be accomplished by recursively partitioning a circuit into two parts until we reach desired level of complexity. Thus two way partitioning is basic problem in circuit partitioning, which can be described as (Dutt& Deng, 1996).

 Various weights representing different attributes are attached to all nodes and edges of the hypergraph H, these are: On nodes: area estimates, On edges: length (after global

 To partition the set V of all nodes vV into a set of disjoint subsets, of V, such that each node v is present in exactly one of these subsets. These subsets are referred to as blocks

 The partition on V induces a cut of the set of all hyper edges, that is, Eh. A cut is subset of Eh, such that for every hyper edge h present in the cut there are at least two nodes

 It should attempt to balance the area attribute of all the blocks of the partition with the additional constraint that there is an area penalty associated with every hyperedge that

It should try to minimize interconnections between different clusters so as to satisfy the

A new approach Memetic Algorithm is described in this section to solve problem of circuit

The circuit partitioning problem can be formally represented in graph theoretic notation as a weighted graph, with the components represented as nodes, and the wires connecting them as edges, the weights of the node represent the sizes of the corresponding components, and the weights of the edges represent the number of wires connecting the components. In its general form, the partitioning problem consists of dividing the nodes of the graph into two or more disjoint subsets such that the sum of weights of the nodes in each subset does not exceed a given capacity, and the sum of weights of edges connecting nodes in different subsets is minimized. But generally the circuits are represented as bipartite graphs consisting of two sets of nodes, the cells and the nets/ Edges connect each cell to several nets, and each net to several cells as shown in Fig1.Let G= (M, N, E), mi is a cell, niN is a net, and eij=(mi,nj) E is an edge which represents that mi and nj are connected electrically. For any nj for all I for which eij exists, we say that the cells mi are connected by net nj.

technological limit on the maximum number of interconnects allowed.

**3. Memetic approach in VLSI circuit partitioning** 

 The objective function of partitioning approach has to address the following issues: It should be able to handle multi-million node graphs in a reasonable amount of

Logic netlist can be represented as a hypergraph H (V,Eh) where

placement)

of the partition.

computation time

partitioning pertaining to VLSI.

**3.1 A model to solve circuit partitioning** 

get cut.

The problem is:

 Each node vV in hypergraph represents a logic cell of the netlist, and Each hyperedge e Eh represents a net connecting various logic cells

adjacent to h, which belong to separate blocks of the partition.

partitioning. A general graph partitioning though fast, is inefficient while partitioning a tree structure. An algorithm for tree partitioning that can handle large trees with less memory/run time requirement will be a modification of Luke's algorithm. Dynamic program mining based tree partition, which works well for small trees, but because of its high memory and run time complexity, it cannot be used for large trees. In order to optimize above mentioned issues this chapter concentrates on different methodologies starting with Memetic Approach in comparison with genetic concept, Neuro-Memetic approach in comparison with Memetic approach, then deviated the chapter to Neuro EM model with clustering concept. After that the topic concentration is on Fuzzy ARTMAP DBSCAN technique and finally there is a section on Data mining concept using two novel Clustering algorithms achieving the optimality of the partition algorithm in minimizing the number of inter-connections between the cells, which is the required criteria of the partitioning technique in VLSI circuit design. Memetic algorithm (MA) is population based heuristic search approach for combinatorial optimization problems based on cultural evolution. They are designed to search in the space of locally optimal solutions instead of searching in the space of all candidate solutions. This is achieved by applying local search after each of the genetic operators. Crossover and mutation operators are applied to randomly chosen individuals for a predefined number of times. To maintain local optimality, the local search procedure is applied to the newly created individuals.

Neuro-memetic model makes it possible to predict the sub-circuit from circuit with minimum interconnections between them. The system consists of three parts, each dealing with data extraction, learning stage and result stage. In data extraction, a circuit is bipartite and chromosomes are represented for each sub circuit. Extracted sequences are fed to Neuro-memetic model that would recognize sub-circuits with lowest amount of interconnections between them.

Next method focuses on the use of clustering k-means (J. B. MacQueen, 1967) and Expectation-Maximization (EM) methodology (Kaban & Girolami, 2000), which divides the circuit into a number of sub-circuits with minimum interconnections between them, and partition it into 10 clusters, by using k-means and EM methodology. In recognition stage the parameters, centroid and probability are fed into generalized delta rule algorithm separately.

Further, a new model for partitioning a circuit is explored using DBSCAN and fuzzy ARTMAP neural network. The first step is concerned with feature extraction, where it uses DBSCAN algorithm. The second step is classification and is composed of a fuzzy ARTMAP neural network.

Finally, two clustering algorithms Nearest Neighbor (NNA) and Partitioning Around Medoids (PAM) clustering algorithms are considered for dividing the circuits into sub circuits. Clustering is alternatively referred to as unsupervised learning segmentation. The clusters are formed by finding the similarities between data according to characteristics found in the actual data. NNA is a serial algorithm in which the items are iteratively merged into the existing clusters that are closest. PAM represents a cluster by a medoid.
