**2.2.1 Rotation of the hotspots**

22 VLSI Design

conductivity *ks*. The availability of the thermal ridge can be modelled by the equivalent

(a)

(b)

(c) Fig. 4. Resistive thermal models of two adjacent CGs inserted with (a) no thermal ridge, (b) a

Figure 4(a) shows the case when there is no thermal ridge between CG1 and CG2. It is clear in the schematic that no extra conduction path has been added to the ground. Since the

type-I thermal ridge, and (c) a type-II thermal ridge.

circuits as follows.

To verify the feasibility of the proposed scheme for thermal-aware floorplanning, we obtain the temperature distribution of the basic CG first. There are 4 × 4 cores within a CG as shown in Figure 5. The cores are homogenous, with the hotspot near the lower right corner. It is clear that since the hotspot is not located at the center of the core, when assembled into the CG, the temperature distribution is asymmetric.

Fig. 5. Temperature distribution of the 16-core CG.

Fig. 6. Temperature distribution of the 1,024-core NoC with the same orientation of each core.

Three-Dimensional Integrated Circuits Design

for Thousand-Core Processors: From Aspect of Thermal Management 25

(a)

(b)

The primary objective of the thermal ridges is to reduce the maximum temperature and the temperature non-uniformity at the same time. The thermal ridges are introduced into the design, with the required extra space under the constraint of manufacturing cost. In our case, at most 20% of the chip area is allowed for the thermal ridges and their locations are depicted in the Figure 8. Straits with widths of 400 μm and 200 μm are created by expanding

Fig. 8. The insertion places of thermal ridges. (a) Type I only. (b) Type I and Type II.

**2.2.2 Insertion of the thermal ridges** 

the routing distances between CGs.

However, the situation becomes worse, when 64 such CGs are put together to construct the 1,024-core NoC. Figure 6 shows a typical layout in which the orientation of each core is kept the same as in the Figure 5, with the hotspot near the lower right corner. Apparently, the design maintains regularity in connectivity with the same routing distance between cores, but unfortunately, it is not thermal-aware. The temperature distribution is still asymmetric and the maximum temperature of the whole chip now rises up to 408.9 K which requires a heat sink. The lack of symmetry leads to that the heat sink cannot be placed at a simple orientation with equal heat dissipation ability.

Let us define the temperature non-uniformity as follows:

$$
\Delta U = \frac{\Delta T}{\Delta \mathbf{x}} \tag{7}
$$

where *T* is temperature difference and *x* is distance between any two points on the single core. Hence, it represents the slope of the temperature gradient per unit length. Clearly, the bigger the value of *U* , the more severe the temperature difference between neighboring cores. In the case of Figure 6 the maximum *U* is around 4.1 K/cm the averaged *U* is around 3.1 K/cm.

Fig. 7. Temperature distribution of the 1,024-core NoC with the orientation of every quarter of CGs rotated 90 degree.

To mitigate the non-uniformity, we may try to rotate either the cores in the CG or the CGs so as to align the temperature profile symmetrically (Xu et al., 2006). Figure 7 shows the latter approach by dividing the CGs into four quadrants, keeping the orientation of the second quadrant, and rotating the other three quadrants of the CGs to the upper left, upper right, and lower left corners, respectively.

To compare with those attained in Figure 6, the maximum temperature decreases 1 K, but the averaged temperature non-uniformity increases to 3.8 K/cm. If we rotate the cores in the CG in a similar fashion and then assemble such CGs, the result is not much different and hence is not shown here. This illustrates the fact that the rotation of the hotspots cannot reduce the maximum temperature effectively.

However, the situation becomes worse, when 64 such CGs are put together to construct the 1,024-core NoC. Figure 6 shows a typical layout in which the orientation of each core is kept the same as in the Figure 5, with the hotspot near the lower right corner. Apparently, the design maintains regularity in connectivity with the same routing distance between cores, but unfortunately, it is not thermal-aware. The temperature distribution is still asymmetric and the maximum temperature of the whole chip now rises up to 408.9 K which requires a heat sink. The lack of symmetry leads to that the heat sink cannot be placed at a simple

> *<sup>T</sup> <sup>U</sup> x*

where *T* is temperature difference and *x* is distance between any two points on the single core. Hence, it represents the slope of the temperature gradient per unit length. Clearly, the bigger the value of *U* , the more severe the temperature difference between neighboring cores. In the case of Figure 6 the maximum *U* is around 4.1 K/cm the averaged

Fig. 7. Temperature distribution of the 1,024-core NoC with the orientation of every quarter

To mitigate the non-uniformity, we may try to rotate either the cores in the CG or the CGs so as to align the temperature profile symmetrically (Xu et al., 2006). Figure 7 shows the latter approach by dividing the CGs into four quadrants, keeping the orientation of the second quadrant, and rotating the other three quadrants of the CGs to the upper left, upper right,

To compare with those attained in Figure 6, the maximum temperature decreases 1 K, but the averaged temperature non-uniformity increases to 3.8 K/cm. If we rotate the cores in the CG in a similar fashion and then assemble such CGs, the result is not much different and hence is not shown here. This illustrates the fact that the rotation of the hotspots cannot

(7)

orientation with equal heat dissipation ability.

*U* is around 3.1 K/cm.

of CGs rotated 90 degree.

and lower left corners, respectively.

reduce the maximum temperature effectively.

Let us define the temperature non-uniformity as follows:

Fig. 8. The insertion places of thermal ridges. (a) Type I only. (b) Type I and Type II.
