**3. Impedance matching techniques**

As stated in previous sections, impedance matching techniques must be implemented in order to reduce return losses. It has been also shown that the fastest signaling standards implement termination resistors in order to match the interconnection impedance. Four of the most common termination techniques are shown in Fig. 14, (Brooks D., 2003). The first technique is the parallel termination (Fig. 14(a)) where a single resistor is connected either to ground or to *VDD* and its value is equal to the characteristic impedance of the line. Although this is one of the most used methods, its disadvantage is that the current is always flowing through it, thus increasing the power consumption of the system.

The second termination technique is shown in Fig. 14(b), it is called Thevenin termination and consists of a couple of resistors, one connected to ground and the other to *VDD*. The advantage of this scheme is that it provides pull up and pull down functions improving noise margins in some cases. The drawback of this system is that it is not easy to find the optimum values of the resistors in order to match the characteristic impedance of the line. The third technique is the AC termination and is depicted in Fig. 14(c). It is composed by a series connection of a resistor and a capacitor. Here the capacitance blocks the DC signals in order to reduce the power consumption but distortion can appear when high speed links are considered. Finally the series termination scheme is presented in Fig. 14(d). This is one of the most often used techniques, specially in voltage mode drivers.

Unfortunately the techniques presented in Fig. 14 are implemented with fixed devices and process, temperature and voltage supply variations are not taken into account for the design of such systems. In the following subsections some techniques are presented in which variable terminators are implemented to automatically adapt the impedance of the transmission line.

#### **3.1 Automatic impedance matching control techniques**

An important issue in automatic impedance matching is the control technique used in the adaptation process. It takes the reference signal which indicates the desired value of the impedance and the signal that represents the actual value of the impedance and process them in order to have the same value. The output of the circuit sets the value of the impedance that matches the interconnection.

input signals to this control circuit are the input and the output of the line driver, they are processed by the first stage which is a peak to peak detector. The second stage is a differential difference amplifier (DDA) and its output is the analog control voltage. The drawback of this analog technique is that the driver speed is limited by the frequency response of the control

Impedance Matching in VLSI Systems 79

A second analog approach for the control of an impedance matching system is shown in Fig. 17 which consists of a feedback amplifier. In this circuit the drawback of limited speed of the driver is eliminated by implementing an off-line matching of the impedance, i. e. a replica of the matching impedance is implemented in order to generate the reference signal and no measurements are made from the ports of the driver. The problem with this system is that variations in the interconnection impedance are not taken into account in the process of

**BIAS <sup>V</sup>**

**CC ctrl <sup>V</sup>**

**RC**

Fig. 17. Feedback amplifier based analog control for automatic impedance matching.

In this section some of the most popular reference signal generating circuits are presented. Reference signals are an important subject in automatic impedance matching because they establish the value that the variable impedance must reach in order to fulfill the matching

One of the most used circuits for reference signal generating is shown in Fig. 18, (Fan Y. & Smith J., 2003), (Koo K. et. al., 2006) and (Tae-Hyoung K. et. al., 2005). It consists of an off-chip precision resistor *RREF* connected in series with a replica of the on-chip variable impedance used to match the interconnection *Rv*. The reference voltage *VREF* is obtained from the node located between the resistors and its optimal value is the half rail voltage *VDD*/2. An

**DDA**

**ctrl <sup>V</sup>**

circuits due to the direct signal measurement in the input and output ports.

**Peak to peak**

Fig. 16. DDA based analog control for automatic impedance matching.

**<sup>0</sup> <sup>V</sup> Peak to peak detector**

**detector**

**VREF**

**3.2 Reference signal generating circuits**

**i V**

matching.

condition.

Fig. 14. Termination techniques. (a) Parallel, (b) thevenin, (c) AC and (d) Series.

One of the most common technique used to control the impedance in signaling systems is the one shown in Fig. 15. This technique represents the concept for the circuits presented in (Dehon et. al., 1993), (Koo K. et. al., 2001), (Koo K. et. al., 2006) and (Muljono H. et. al., 2003). It has in essence three stages, the first is a clocked comparator that decides if the impedance value is higher or lower than the reference one. The second stage is a counter which can be either binary or thermometer coded and its input is an *U p*/*Dn* signal that comes from the comparator. The last stage is a digital register that is used to hold the value of the counter when the matching condition of the impedance is fulfilled. The digital outputs of the register are used to control arrays of transistors in a pull up or pull down connection. The drawback of this technique is that switching noise in the supply lines can be generated due to the turning on and the turning off of the transistor array.

Fig. 15. Digital control for automatic impedance matching.

Another approach used in the control of automatic impedance matching is shown in Fig. 16 which is a simplified version of the one presented in (Ramachandran N. et. al., 2003). This circuit is designed to adapt directly the output impedance of an analog driver to the interconnection line by controlling a variable resistor at the output stage of the driver. The 12 Will-be-set-by-IN-TECH

**RL**

**(a) (b)**

**(c) (d)**

One of the most common technique used to control the impedance in signaling systems is the one shown in Fig. 15. This technique represents the concept for the circuits presented in (Dehon et. al., 1993), (Koo K. et. al., 2001), (Koo K. et. al., 2006) and (Muljono H. et. al., 2003). It has in essence three stages, the first is a clocked comparator that decides if the impedance value is higher or lower than the reference one. The second stage is a counter which can be either binary or thermometer coded and its input is an *U p*/*Dn* signal that comes from the comparator. The last stage is a digital register that is used to hold the value of the counter when the matching condition of the impedance is fulfilled. The digital outputs of the register are used to control arrays of transistors in a pull up or pull down connection. The drawback of this technique is that switching noise in the supply lines can be generated due to the turning

**Counter Register**

Another approach used in the control of automatic impedance matching is shown in Fig. 16 which is a simplified version of the one presented in (Ramachandran N. et. al., 2003). This circuit is designed to adapt directly the output impedance of an analog driver to the interconnection line by controlling a variable resistor at the output stage of the driver. The

**RL**

**C**

Fig. 14. Termination techniques. (a) Parallel, (b) thevenin, (c) AC and (d) Series.

**channel**

**channel**

on and the turning off of the transistor array.

**VREF**

**VCLK**

**VIN**

**Cmp**

**up dn**

**Ref In**

Fig. 15. Digital control for automatic impedance matching.

**channel**

**RS**

**RL2**

**channel**

**to controlled terminators**

**RL1**

input signals to this control circuit are the input and the output of the line driver, they are processed by the first stage which is a peak to peak detector. The second stage is a differential difference amplifier (DDA) and its output is the analog control voltage. The drawback of this analog technique is that the driver speed is limited by the frequency response of the control circuits due to the direct signal measurement in the input and output ports.

Fig. 16. DDA based analog control for automatic impedance matching.

A second analog approach for the control of an impedance matching system is shown in Fig. 17 which consists of a feedback amplifier. In this circuit the drawback of limited speed of the driver is eliminated by implementing an off-line matching of the impedance, i. e. a replica of the matching impedance is implemented in order to generate the reference signal and no measurements are made from the ports of the driver. The problem with this system is that variations in the interconnection impedance are not taken into account in the process of matching.

Fig. 17. Feedback amplifier based analog control for automatic impedance matching.

#### **3.2 Reference signal generating circuits**

In this section some of the most popular reference signal generating circuits are presented. Reference signals are an important subject in automatic impedance matching because they establish the value that the variable impedance must reach in order to fulfill the matching condition.

One of the most used circuits for reference signal generating is shown in Fig. 18, (Fan Y. & Smith J., 2003), (Koo K. et. al., 2006) and (Tae-Hyoung K. et. al., 2005). It consists of an off-chip precision resistor *RREF* connected in series with a replica of the on-chip variable impedance used to match the interconnection *Rv*. The reference voltage *VREF* is obtained from the node located between the resistors and its optimal value is the half rail voltage *VDD*/2. An

**REF V**

**CHIP**

Fig. 19. Voltage drop reference generation.

time.

variations in the interconnection impedance are not considered.

**REF R**

Impedance Matching in VLSI Systems 81

**0**

value generating impedance errors. As in the case of the techniques presented before, the

In order to overcome the drawbacks related with the variations in the interconnection impedance, the technique shown in Fig. 21 has been implemented in (Dehon et. al., 1993) and (Dally & Poulton, 1998). In this case a voltage mode driver is implemented in order to drive an interconnection that is terminated with an open at the far end. The reference signal is taken from the node between the matching resistance and the interconnection channel and its shape is as shown at the bottom of the figure. This shape is composed by the signal arriving to the channel from the driver and the one reflected from the far end. In this case the matching condition is fulfilled when the middle part of the reference signal is the same as *Vsw*/2, where *Vsw* is the total swing of the transmitted signal. The drawback of this system is the difficulty in generating the correct timing signals in order to make the voltage comparisons in the correct

**REF2 V**

**Rv**

**<sup>I</sup> <sup>0</sup>**

**I**

advantage of this technique is that the matching operation is independent from the driver data rate because measurements are not taken from the signal lines. The drawback is that an external resistor is needed which increases the area of the PCB. Furthermore, impedance variations of the off-chip interconnection are not taken into account since the reference is generated off line.

Fig. 18. Generation by dividing voltage.

An approach where current sources are implemented in order to generate voltage drops in a replica of the on chip variable impedance *Rv* and in an off-chip precision resistor *RREF* is depicted in Fig. 19 (Dally & Poulton, 1998). Here, the two voltage references *VREF* and *VREF*<sup>2</sup> must have the same value in order to fulfill the matching condition of the impedance. As in the case of the circuit in Fig. 18, the off-chip resistor increases the area of the PCB which represents a disadvantage when high performance systems are needed. Also, variations in the interconnection impedance are not considered because references are generated in a circuit which is separated from the driver.

A modification of the circuit of Fig. 19 is shown in Fig. 20, (Koo K. et. al., 2001). In this case only the voltage drop from the on chip variable impedance *Rv* is considered as a voltage reference, avoiding the need of an off-chip resistor. In order to accomplish the automatic impedance matching operation, the reference voltage *VREF* is compared against an internally generated voltage reference. The disadvantage of this technique is that the on-die process, voltage and temperature variations can move the internal reference away from its optimal 14 Will-be-set-by-IN-TECH

advantage of this technique is that the matching operation is independent from the driver data rate because measurements are not taken from the signal lines. The drawback is that an external resistor is needed which increases the area of the PCB. Furthermore, impedance variations of the off-chip interconnection are not taken into account since the reference is

**Rv**

An approach where current sources are implemented in order to generate voltage drops in a replica of the on chip variable impedance *Rv* and in an off-chip precision resistor *RREF* is depicted in Fig. 19 (Dally & Poulton, 1998). Here, the two voltage references *VREF* and *VREF*<sup>2</sup> must have the same value in order to fulfill the matching condition of the impedance. As in the case of the circuit in Fig. 18, the off-chip resistor increases the area of the PCB which represents a disadvantage when high performance systems are needed. Also, variations in the interconnection impedance are not considered because references are generated in a circuit

A modification of the circuit of Fig. 19 is shown in Fig. 20, (Koo K. et. al., 2001). In this case only the voltage drop from the on chip variable impedance *Rv* is considered as a voltage reference, avoiding the need of an off-chip resistor. In order to accomplish the automatic impedance matching operation, the reference voltage *VREF* is compared against an internally generated voltage reference. The disadvantage of this technique is that the on-die process, voltage and temperature variations can move the internal reference away from its optimal

**REF R**

**REF V**

Fig. 18. Generation by dividing voltage.

which is separated from the driver.

**CHIP**

generated off line.

Fig. 19. Voltage drop reference generation.

value generating impedance errors. As in the case of the techniques presented before, the variations in the interconnection impedance are not considered.

In order to overcome the drawbacks related with the variations in the interconnection impedance, the technique shown in Fig. 21 has been implemented in (Dehon et. al., 1993) and (Dally & Poulton, 1998). In this case a voltage mode driver is implemented in order to drive an interconnection that is terminated with an open at the far end. The reference signal is taken from the node between the matching resistance and the interconnection channel and its shape is as shown at the bottom of the figure. This shape is composed by the signal arriving to the channel from the driver and the one reflected from the far end. In this case the matching condition is fulfilled when the middle part of the reference signal is the same as *Vsw*/2, where *Vsw* is the total swing of the transmitted signal. The drawback of this system is the difficulty in generating the correct timing signals in order to make the voltage comparisons in the correct time.

**channel**

**CHIP**

Fig. 22. Reference generation by current division.

**4.1 Mathematical approach**

by its voltage characteristics.

coupling branch current *Ig*.

can be expressed as in the equation (8).

**Rv**

**I**

Impedance Matching in VLSI Systems 83

**O I**

An automatic impedance matching based on an optimization algorithm that uses the sign of the error and the sign of the coupling branch current is proposed. A possible implementation

The mathematical formulation of the proposed method for impedance matching is based on Fig. 23, which is a modification of the system proposed in (Munshi A. et. al., 1994). In this system the output driver is modeled with a simple time variant current source and its output impedance is set to infinity. The current is divided between two branches, one is the transmission line with characteristic impedance *Z*<sup>0</sup> and the other is the matching branch *Zg* which is used to avoid reflections in the line. This matching impedance is mainly composed by two elements, a current dependent voltage source *Vg* and a fixed impedance *ZP*. The output voltage *VS* is the voltage drop that results when the output current *IS* flows through the parallel configuration of *Zg* and *Z*0. Then the system can be seen either by its current or

As shown in equation (7), the voltage dependent source *Vg* has a linear relationship with the

By analyzing the Fig 23 it can be deduced that the current *Ig*, flowing in the coupling branch,

From equation (8), and making some mathematical manipulation, it is posible to prove that the matching impedance is given in terms of the fixed impedance *ZP* and the transimpedance

where, the transimpedance *Hg* is a variable parameter with units of Ohms (Ω).

*Ig* <sup>=</sup> <sup>1</sup> *ZP*

**I <sup>V</sup>**

**4. Automatic impedance matching design based on the sign of the error**

**S**

of the system, simulation and experimental results are presented.

**OZ**

*Vg* = *Hg Ig* (7)

(*VS* − *Vg*) (8)

Fig. 20. On chip reference generation.

Fig. 21. Reference generation by signal reflection.

Finally, an approach for reference signal generation in current mode drivers is depicted in Fig. 22 which is an idea presented in (Munshi A. et. al., 1994). In this technique the current mode driver sinks or sources a current *IS* from or to the interconnection which is in a parallel array with the matching impedance *Rv*. Then the matching condition in this scheme is fulfilled when the current *Iv* flowing though *Rv* is *Iv* = *I*0, in other words, when *Iv* = *IS*/2. The advantage of this method is that variations in the impedance of the interconnection are taken into account since reference signals are measured directly from the data link. The drawback is that measuring currents may modify the impedance branch.

In a similar way, reference signals for voltage mode interconnections can be obtained by considering the variable impedance and the interconnection line as a voltage divider. In this case, the reference voltage must be equal to *VS*/2.

16 Will-be-set-by-IN-TECH

**Rv**

**REF V**

**Rv**

Finally, an approach for reference signal generation in current mode drivers is depicted in Fig. 22 which is an idea presented in (Munshi A. et. al., 1994). In this technique the current mode driver sinks or sources a current *IS* from or to the interconnection which is in a parallel array with the matching impedance *Rv*. Then the matching condition in this scheme is fulfilled when the current *Iv* flowing though *Rv* is *Iv* = *I*0, in other words, when *Iv* = *IS*/2. The advantage of this method is that variations in the impedance of the interconnection are taken into account since reference signals are measured directly from the data link. The drawback

In a similar way, reference signals for voltage mode interconnections can be obtained by considering the variable impedance and the interconnection line as a voltage divider. In this

**CHIP**

Fig. 20. On chip reference generation.

**CHIP**

**SW V 2**

Fig. 21. Reference generation by signal reflection.

case, the reference voltage must be equal to *VS*/2.

is that measuring currents may modify the impedance branch.

**0 I**

**channel**

**OZ**

**OPEN**

Fig. 22. Reference generation by current division.

#### **4. Automatic impedance matching design based on the sign of the error**

An automatic impedance matching based on an optimization algorithm that uses the sign of the error and the sign of the coupling branch current is proposed. A possible implementation of the system, simulation and experimental results are presented.

#### **4.1 Mathematical approach**

The mathematical formulation of the proposed method for impedance matching is based on Fig. 23, which is a modification of the system proposed in (Munshi A. et. al., 1994). In this system the output driver is modeled with a simple time variant current source and its output impedance is set to infinity. The current is divided between two branches, one is the transmission line with characteristic impedance *Z*<sup>0</sup> and the other is the matching branch *Zg* which is used to avoid reflections in the line. This matching impedance is mainly composed by two elements, a current dependent voltage source *Vg* and a fixed impedance *ZP*. The output voltage *VS* is the voltage drop that results when the output current *IS* flows through the parallel configuration of *Zg* and *Z*0. Then the system can be seen either by its current or by its voltage characteristics.

As shown in equation (7), the voltage dependent source *Vg* has a linear relationship with the coupling branch current *Ig*.

$$V\_{\mathcal{S}} = H\_{\mathcal{S}} I\_{\mathcal{S}} \tag{7}$$

where, the transimpedance *Hg* is a variable parameter with units of Ohms (Ω).

By analyzing the Fig 23 it can be deduced that the current *Ig*, flowing in the coupling branch, can be expressed as in the equation (8).

$$I\_{\mathcal{S}} = \frac{1}{Z\_P} (V\_{\mathcal{S}} - V\_{\mathcal{S}}) \tag{8}$$

From equation (8), and making some mathematical manipulation, it is posible to prove that the matching impedance is given in terms of the fixed impedance *ZP* and the transimpedance

From equations (7),(10) and (13), it is possible to find the gradient of the error as shown in

Impedance Matching in VLSI Systems 85

Finally, from equations (14) and (12) the coefficient *ρ* as a function of the system parameters is

 *t* −∞

It can be seen from (15) that for practical implementation the silicon area can be large due to the multiplication operation. In order to simplify the system, the SS-LMS (Sign-Sign LMS) algorithm, (Carusone A. & Johns D., 2000), is considered, where the sign function is applied to the error and to the matching branch signals. Thus, the multiplication results in a trivial

Based on equation (16), the block diagram of the proposed system for automatic impedance matching is depicted in Fig. 24. The system input is the driver voltage *VS* and the reference

impedance and the transimpedance block *H*(*α*) performs the dependent source *Vg*. The impedance optimization is made by the sign blocks together with the multiplication and integration blocks. The coefficient *α* specifies the speed of matching and the error level around

**Sign**

**e ñ**

**Sign**

<sup>2</sup> *IS* <sup>−</sup> *Ig*

*ZP IS* − *ZP Ig*

*ZP*

*ZH Ig* (14)

*e*(*u*)*Ig*(*u*)*du* (15)

*Sgn*(*e*(*u*))*Sgn*(*Ig*(*u*))*du* (16)

**á**

(17)

*Zp* represents the fixed

<sup>∇</sup>*ρ<sup>e</sup>* <sup>=</sup> <sup>−</sup> <sup>1</sup>

*<sup>ρ</sup>*(*t*) = <sup>2</sup>*μZH ZP*

operation. Consequently, the impedance matching coefficient become:

for the error signal is the driver current divided by two. The block <sup>1</sup>

**g I**

**P 1 Z**

**H (ñ) <sup>g</sup>**

+ -

**S 1 I 2**

One condition that must be established for the circuit implementation of the system of Fig. 24 is that the impedance *ZP* is real and that its value is smaller than the load impedance *Z*0. It means that *ZP* must accomplish the following conditions: 0 < *ZP* < *Z*<sup>0</sup> and *ZP* = *Re*(*ZP*).

*Sgn*(*e*) = *Sgn* <sup>1</sup>

2

<sup>=</sup> *Sgn* <sup>1</sup>

 *t* −∞

*ρ*(*t*) = *α*

equation (14).

presented in (15).

where, *α* = <sup>2</sup>*μZi*

the optimal impedance.

*ZP* is constant.

**VS**

**4.2 Proposed implementation**

+ -

Fig. 24. Block Diagram for Impedance Matching.

**Vg**

Also, the sign operation for the error can be expressed as:

Fig. 23. Impedance Matching Synthesis Circuit

*Hg*. This is shown in the equation (9).

$$\frac{V\_{\text{S}}}{I\_{\text{g}}} = Z\_{\text{g}} = Z\_{\text{P}} + H\_{\text{g}} \tag{9}$$

From equation (9) it can be inferred that *Hg* should be modified in order to achieve an impedance value *Zg* = *Z*0, which is the coupling condition. In consequence, *Hg* is defined as:

$$H\_{\mathcal{S}}(t) = \rho(t)Z\_H \tag{10}$$

where, *ZH* is constant and has units of Ohms(Ω) and *ρ*(*t*) is an impedance matching coefficient and its optimal value is achieved when the impedance matching condition *Zg* = *ZL* is fulfilled. It is clear that the fulfillment of the condition implies: *Ig* = *IL* = 1/2*IS*. From this expression, the impedance matching error *e* is defined as in equation (11).

$$e = \frac{1}{2}I\_{\mathbb{S}} - I\_{\mathbb{S}} \tag{11}$$

From equations (7), (10) and (11), the goal of the system is to dynamically adapt the coefficient *ρ*(*t*) in such a way that the error *e* is minimized. A suitable technique to accomplish this goal is the LMS (Least Mean Square) (Carusone A. & Johns D., 2000), in which the criteria is to optimize temporal estimations of *E*[*e*2]. Then, it is possible to express *ρ* as follows:

$$\rho(t) = -2\mu \int\_{-\infty}^{t} \varepsilon(u) \nabla\_{\rho} \varepsilon(u) du \tag{12}$$

where, *μ* is constant and establishes the speed of adaptation of the system, ∇*ρe*(*u*) represents the gradient of the error related with the parameter *ρ* . Also, for the equation 12 is considered that *e*<sup>2</sup> is a noisy estimation of *E*[*e*2].

Once established the conditions and the optimization method, it is necessary to find *ρ* as a function of the system parameters. Then, by substituting equation (8) in (11), the impedance matching error is given by:

$$e = \frac{1}{2}I\_S - \frac{1}{Z\_P}(V\_S - V\_{\mathcal{S}}) \tag{13}$$

18 Will-be-set-by-IN-TECH

**Zg <sup>I</sup>**

*VS Ig*

the impedance matching error *e* is defined as in equation (11).

**ZP**

From equation (9) it can be inferred that *Hg* should be modified in order to achieve an impedance value *Zg* = *Z*0, which is the coupling condition. In consequence, *Hg* is defined

where, *ZH* is constant and has units of Ohms(Ω) and *ρ*(*t*) is an impedance matching coefficient and its optimal value is achieved when the impedance matching condition *Zg* = *ZL* is fulfilled. It is clear that the fulfillment of the condition implies: *Ig* = *IL* = 1/2*IS*. From this expression,

From equations (7), (10) and (11), the goal of the system is to dynamically adapt the coefficient *ρ*(*t*) in such a way that the error *e* is minimized. A suitable technique to accomplish this goal is the LMS (Least Mean Square) (Carusone A. & Johns D., 2000), in which the criteria is to

*<sup>e</sup>* <sup>=</sup> <sup>1</sup>

optimize temporal estimations of *E*[*e*2]. Then, it is possible to express *ρ* as follows:

 *t* −∞

where, *μ* is constant and establishes the speed of adaptation of the system, ∇*ρe*(*u*) represents the gradient of the error related with the parameter *ρ* . Also, for the equation 12 is considered

Once established the conditions and the optimization method, it is necessary to find *ρ* as a function of the system parameters. Then, by substituting equation (8) in (11), the impedance

> <sup>2</sup> *IS* <sup>−</sup> <sup>1</sup> *ZP*

*ρ*(*t*) = −2*μ*

*<sup>e</sup>* <sup>=</sup> <sup>1</sup>

**Vg**

**S I**

Fig. 23. Impedance Matching Synthesis Circuit

*Hg*. This is shown in the equation (9).

that *e*<sup>2</sup> is a noisy estimation of *E*[*e*2].

matching error is given by:

as:

**LI <sup>S</sup> <sup>I</sup> VS**

**g**

**ñ(t)ZH**

**Z0**

= *Zg* = *ZP* + *Hg* (9)

*Hg*(*t*) = *ρ*(*t*)*ZH* (10)

<sup>2</sup> *IS* <sup>−</sup> *Ig* (11)

*e*(*u*)∇*ρe*(*u*)*du* (12)

(*VS* − *Vg*) (13)

From equations (7),(10) and (13), it is possible to find the gradient of the error as shown in equation (14).

$$\nabla\_{\theta}e = -\frac{1}{Z\_P} Z\_H I\_{\mathbb{S}} \tag{14}$$

Finally, from equations (14) and (12) the coefficient *ρ* as a function of the system parameters is presented in (15).

$$\rho(t) = \frac{2\mu Z\_H}{Z\_P} \int\_{-\infty}^{t} e(u) I\_\mathcal{S}(u) du \tag{15}$$

It can be seen from (15) that for practical implementation the silicon area can be large due to the multiplication operation. In order to simplify the system, the SS-LMS (Sign-Sign LMS) algorithm, (Carusone A. & Johns D., 2000), is considered, where the sign function is applied to the error and to the matching branch signals. Thus, the multiplication results in a trivial operation. Consequently, the impedance matching coefficient become:

$$\rho(t) = \alpha \int\_{-\infty}^{t} \text{Sgn}(e(u)) \text{Sgn}(I\_{\mathcal{S}}(u)) du \tag{16}$$

where, *α* = <sup>2</sup>*μZi ZP* is constant.

Based on equation (16), the block diagram of the proposed system for automatic impedance matching is depicted in Fig. 24. The system input is the driver voltage *VS* and the reference for the error signal is the driver current divided by two. The block <sup>1</sup> *Zp* represents the fixed impedance and the transimpedance block *H*(*α*) performs the dependent source *Vg*. The impedance optimization is made by the sign blocks together with the multiplication and integration blocks. The coefficient *α* specifies the speed of matching and the error level around the optimal impedance.

Fig. 24. Block Diagram for Impedance Matching.

#### **4.2 Proposed implementation**

One condition that must be established for the circuit implementation of the system of Fig. 24 is that the impedance *ZP* is real and that its value is smaller than the load impedance *Z*0. It means that *ZP* must accomplish the following conditions: 0 < *ZP* < *Z*<sup>0</sup> and *ZP* = *Re*(*ZP*). Also, the sign operation for the error can be expressed as:

$$\begin{split} \mathcal{S}gn(e) &= \mathcal{S}gn\left(\frac{1}{2}I\_{\mathcal{S}} - I\_{\mathcal{S}}\right) \\ &= \mathcal{S}gn\left(\frac{1}{2}Z\_{P}I\_{\mathcal{S}} - Z\_{P}I\_{\mathcal{S}}\right) \end{split} \tag{17}$$

a current *IS*

voltage *VCTRL* by implementing equation (20).

**Pre Driver**

**Dat Dat**

Fig. 26. Proposed Implementation.

affecting the operation of the driver.

outside the dashed line.

<sup>2</sup> from a replica of the programmable resistance *Zg*. The voltages *VOut* of the driver

**VDDO**

**VOut VOutB**

**VREF**

**S 1 I 2**

 *IS* <sup>2</sup> <sup>−</sup> *Ig* **Z0 Z0**

**Impedance Calibration VCTRL**

*VOut* = *VDD*<sup>0</sup> − *IgZg*. (21)

<sup>2</sup> *Zg*. (22)

. (23)

(24)

and *VREF* are the inputs for the impedance calibration circuit. This circuit generates the control

Impedance Matching in VLSI Systems 87

**VCTRL Zg**

By analyzing Fig. 26 one can find that the output voltage *VOut* and the reference voltage *VREF*

*VREF* <sup>=</sup> *VDD*<sup>0</sup> <sup>−</sup> *Is*

Also, by assuming that *Zg* > 0, it is inferred that the sign of the errors in voltage and in current mode are the same, this can be verified by equation (24), moreover, the function *Sgn*(*Ig*) can be calculated directly from the input to the driver *Dat*. Consequently this shows that measuring voltages instead of currents is a good option to implement the SS-LMS technique without

<sup>=</sup> *Sgn*

A print of the Mentor Graphics screen of the layout of the system is shown in Fig. 27 and it was designed in the 0.35*μm* C35B4C3 AMS technology. The circuit enclosed by the dashed line corresponds to the current mode driver, the pre-driver, the programmable resistors and the voltage reference circuit. The SS-LMS based impedance matching algorithm is shown

In order to verify the performance of the impedance calibration circuit, the system was simulated with post layout extractions using Mentor Graphics tools. To test the circuit, different resistive loads (45Ω, 50Ω and 55Ω) were attached to the circuit. The signal rate

*Zg IS* <sup>2</sup> <sup>−</sup> *Ig*

Using equations (21) and (22) we can define the voltage mode error as follows:

*eV* = *VOut* − *VREF* = *Zg*

**VCTRL**

**I 0**

**VDD**

**Zg Zg**

**S I**

**VBIAS**

are those described by equations (21) and (22), respectively.

*Sgn IS*

<sup>2</sup> <sup>−</sup> *Ig*

**VDDO**

**Ig**

In the same way, the sign operation for *Ig* is:

$$\operatorname{Sym}(I\_{\mathfrak{F}}) = \operatorname{Sym}(Z\_P I\_{\mathfrak{F}}) \tag{18}$$

As shown in (17) and (18), the sign operation can be implemented as a voltage level comparator. In this way, the inputs for (17) are the voltage across the fixed impedance *ZP* and the reference voltage across the impedance with the same value as *ZP*.

Fig. 25. Automatic Impedance Matching System Implementation.

The proposed circuit implementation for the automatic impedance matching system is shown in Fig. 25, where it can be seen that the error signal sign and the sign of the current in the coupling branch give as a result logic levels, then the multiplication is trivial and is implemented with a Xor logic gate, as shown in (19).

$$\mathcal{S}gn(e)\mathcal{S}gn(I\_{\mathcal{S}}) \Rightarrow \mathcal{S}gn(e) \oplus \mathcal{S}gn(I\_{\mathcal{S}}) \tag{19}$$

Another important operation for the system is the integration, which is implemented by means of a charge pump and a filter (Lopez et al., 2009). The current *ICH* of the pump is directly related with the parameter *α*, as a consequence, the matching speed is established by this current. Finally, the current dependent voltage source *Vg* = *Hg Ig* is implemented with a variable resistance, and its value is controlled by the voltage in the charge pump filter.

#### **4.3 Proposed test vehicle**

As stated before the mathematical representation of the system to be implemented is that shown in equation (20).

$$\rho(t) = \beta \int\_{-\infty}^{t} \operatorname{sgn}\left(\frac{1}{2}I\_{\mathcal{S}}(u) - I\_{\mathcal{S}}(u)\right) \operatorname{sgn}(I\_{\mathcal{S}}(u)) du \tag{20}$$

Even though equation (20) is expressed in terms of branch currents, it is difficult to achieve a practical implementation for it. This is due to the fact that sensing a branch current is more complicated than sensing a node voltage. Therefore in the proposed implementation shown in Fig. 26, the inputs to the calibration circuit are voltages. The core of the scheme is the unipolar current mode differential driver (Dally & Poulton, 1998). This driver sinks the current *IS* from its outputs depending on the logic state of its inputs *Dat* and *Dat*. The terminators *Zg* are programmable resistors that can be analog programmed via *VCTRL* to match the interconnection impedance *Z*0. The voltage reference *VREF* is generated by sinking 20 Will-be-set-by-IN-TECH

As shown in (17) and (18), the sign operation can be implemented as a voltage level comparator. In this way, the inputs for (17) are the voltage across the fixed impedance *ZP*

**Z0**

**Ref In**

**Ref In**

The proposed circuit implementation for the automatic impedance matching system is shown in Fig. 25, where it can be seen that the error signal sign and the sign of the current in the coupling branch give as a result logic levels, then the multiplication is trivial and is

Another important operation for the system is the integration, which is implemented by means of a charge pump and a filter (Lopez et al., 2009). The current *ICH* of the pump is directly related with the parameter *α*, as a consequence, the matching speed is established by this current. Finally, the current dependent voltage source *Vg* = *Hg Ig* is implemented with a variable resistance, and its value is controlled by the voltage in the charge pump filter.

As stated before the mathematical representation of the system to be implemented is that

Even though equation (20) is expressed in terms of branch currents, it is difficult to achieve a practical implementation for it. This is due to the fact that sensing a branch current is more complicated than sensing a node voltage. Therefore in the proposed implementation shown in Fig. 26, the inputs to the calibration circuit are voltages. The core of the scheme is the unipolar current mode differential driver (Dally & Poulton, 1998). This driver sinks the current *IS* from its outputs depending on the logic state of its inputs *Dat* and *Dat*. The terminators *Zg* are programmable resistors that can be analog programmed via *VCTRL* to match the interconnection impedance *Z*0. The voltage reference *VREF* is generated by sinking

<sup>2</sup> *IS*(*u*) <sup>−</sup> *Ig*(*u*)

**Cmp1**

**Cmp2**

and the reference voltage across the impedance with the same value as *ZP*.

**S 1 I 2**

**ZP ZP**

Fig. 25. Automatic Impedance Matching System Implementation.

**g I**

implemented with a Xor logic gate, as shown in (19).

*ρ*(*t*) = *β*

 *t* −∞ *Sgn* 1

**4.3 Proposed test vehicle**

shown in equation (20).

**Hg**

+ -

**LI <sup>S</sup> I**

*Sgn*(*Ig*) = *Sgn*(*ZP Ig*) (18)

*Sgn*(*e*)*Sgn*(*IS*) ⇒ *Sgn*(*e*) ⊕ *Sgn*(*IS*) (19)

**CH I**

**CH <sup>I</sup> <sup>C</sup>**

*Sgn*(*Ig*(*u*))*du* (20)

In the same way, the sign operation for *Ig* is:

Tx

a current *IS* <sup>2</sup> from a replica of the programmable resistance *Zg*. The voltages *VOut* of the driver and *VREF* are the inputs for the impedance calibration circuit. This circuit generates the control voltage *VCTRL* by implementing equation (20).

Fig. 26. Proposed Implementation.

By analyzing Fig. 26 one can find that the output voltage *VOut* and the reference voltage *VREF* are those described by equations (21) and (22), respectively.

$$V\_{\rm Out} = V\_{\rm DD0} - I\_{\rm g} Z\_{\rm g}.\tag{21}$$

$$V\_{\rm REF} = V\_{\rm DD0} - \frac{I\_{\rm s}}{2} Z\_{\rm \S}. \tag{22}$$

Using equations (21) and (22) we can define the voltage mode error as follows:

$$\mathcal{e}\_V = V\_{\text{Out}} - V\_{\text{REF}} = Z\_{\text{\S}} \left( \frac{I\_{\text{S}}}{2} - I\_{\text{\S}} \right). \tag{23}$$

Also, by assuming that *Zg* > 0, it is inferred that the sign of the errors in voltage and in current mode are the same, this can be verified by equation (24), moreover, the function *Sgn*(*Ig*) can be calculated directly from the input to the driver *Dat*. Consequently this shows that measuring voltages instead of currents is a good option to implement the SS-LMS technique without affecting the operation of the driver.

$$\text{Sgn}\left(\frac{I\_{\text{S}}}{2} - I\_{\text{S}}\right) = \text{Sgn}\left(Z\_{\text{S}}\left(\frac{I\_{\text{S}}}{2} - I\_{\text{S}}\right)\right) \tag{24}$$

A print of the Mentor Graphics screen of the layout of the system is shown in Fig. 27 and it was designed in the 0.35*μm* C35B4C3 AMS technology. The circuit enclosed by the dashed line corresponds to the current mode driver, the pre-driver, the programmable resistors and the voltage reference circuit. The SS-LMS based impedance matching algorithm is shown outside the dashed line.

In order to verify the performance of the impedance calibration circuit, the system was simulated with post layout extractions using Mentor Graphics tools. To test the circuit, different resistive loads (45Ω, 50Ω and 55Ω) were attached to the circuit. The signal rate

**0 200 400 600 800 1000 1200**

**0 200 400 600 800 1000 1200**

**Time (ns)**

**Time (ns)**

**Zo=55 Ohms Zo=45 Ohms**

**-70 -60 -50 -40 -30 -20 -10**

**(a) (b)**

**-80 -60 -40 -20**

**Error (dB)**

**(a) (b)**

**0 200 400 600 800 1000 1200**

**Time (ns)**

**(c)** Fig. 30. Error in the (a) worst power, (b) worst speed and (c) temperature variation cases.

Formulation of a complete mathematical model for impedance mismatch is a very complex process, since the parameters involved depend on many factors like process variations, length variations of the interconnection lines, temperature, etc. In this sense, knowledge based algorithms represent interesting alternatives which can be explored when looking for

Fuzzy logic formalizes the treatment of vague knowledge, and approximates reasoning through inference rules (Zadeh, L. 1999). It establishes the mechanisms to generate practical solutions to problems where traditional methods, which may require precise mathematical models, may not be suitable. Because of this, fuzzy control represents a good alternative to solve the impedance mismatch problem through on-chip adaptive mechanisms (Arroyo et al.,

Fig. 31 shows the general structure of the fuzzy controller used to adapt the system. The structure is simple and was designed in UMC 90nm CMOS technology. The membership functions are implemeted using differential pairs, while the multipliers are four-quadrant multipliers. The controller was designed to work in current-mode, therefore the sum operation is simply the sum of the currents in a node. Since the implementation of the divisor

**Error (dB)**

Impedance Matching in VLSI Systems 89

**0 200 400 600 800 1000 1200**

**Time (ns)**

**0 200 400 600 800 1000 1200**

**Time (ns)**

**-30 -25 -20 -15**

**Error (dB)**

**5. Knowledge-based impedace matching control design**

solutions to the impedance mismatch problem using adaptive schemes.

circuit is not trivial, a normalizer circuit can be used as an alternative.

Fig. 29. Error for (a) 50 Ohms and (b) 45 and 55 Ohms loads.

**-80 -60 -40 -20**

**-70 -60 -50 -40 -30 -20**

**Error (dB)**

2009).

**Error (dB)**

Fig. 27. System Layout.

of the data inputs to the system *Dat* and *Dat* is 1*Gb*/*s* and clock frequency for the impedance calibration circuit is established at 300*MHz*.

In Fig. 28 the time domain signals for the output and the reference signal are shown. In this case, the load impedance for the system is set to 50Ω. As can be seen, the system adapts after some time.

Fig. 28. Time domain analysis, (a) before and (b) after adaptation.

In Fig. 29, learning curves are shown for the 50Ω load impedance case (Fig. 29a) and for 45Ω and 55Ω (Fig. 29b). Those curves are normalized error signals in dB as a function of time and the adaptation time can be seen on them.

The last post layout simulations deal with worst case power and speed scenarios as well as temperature. The Mentor Graphics kit is used to perform this task. Only worst power and speed cases are presented because they result in the poorest performance compared with the others. Figs. 30a, Fig. 30b and Fig. 30c show the simulation results for worst power, worst speed and temperature variations (100 degree Celsius) respectively. As can be observed in the figure, the error always converges to a level bellow the −30*dB*.

22 Will-be-set-by-IN-TECH

200um 270um

of the data inputs to the system *Dat* and *Dat* is 1*Gb*/*s* and clock frequency for the impedance

In Fig. 28 the time domain signals for the output and the reference signal are shown. In this case, the load impedance for the system is set to 50Ω. As can be seen, the system adapts after

**(a) (b)**

In Fig. 29, learning curves are shown for the 50Ω load impedance case (Fig. 29a) and for 45Ω and 55Ω (Fig. 29b). Those curves are normalized error signals in dB as a function of time and

The last post layout simulations deal with worst case power and speed scenarios as well as temperature. The Mentor Graphics kit is used to perform this task. Only worst power and speed cases are presented because they result in the poorest performance compared with the others. Figs. 30a, Fig. 30b and Fig. 30c show the simulation results for worst power, worst speed and temperature variations (100 degree Celsius) respectively. As can be observed in the

Fig. 28. Time domain analysis, (a) before and (b) after adaptation.

figure, the error always converges to a level bellow the −30*dB*.

the adaptation time can be seen on them.

235um

calibration circuit is established at 300*MHz*.

Fig. 27. System Layout.

some time.

Fig. 29. Error for (a) 50 Ohms and (b) 45 and 55 Ohms loads.

Fig. 30. Error in the (a) worst power, (b) worst speed and (c) temperature variation cases.
