**4. Conclusion**

36 VLSI Design

The experimental results are shown in Table 1. When the power density of 7.38 W/cm2 is applied to the virtual core, each core is operated at the power of 20 mW. To evaluate the thermal conduction capability of the metallic thermal skeleton, the average temperature of the metallic thermal skeleton is an important index. Since the metallic thermal skeletons are employed to conduct the heat flux generated by the virtual cores, the temperature at *w*/2 (referred to Figure 18) especially represents the results of the lateral thermal diffusion. To compare with the experimental steady state data shown in Table 1, it is clear that the virtual

performance. Moreover, Tmax-Tmin denotes the temperature uniformity in the region. The

t = 16sec

**β<sup>2</sup> A5 γ<sup>1</sup>**

**β<sup>2</sup> A5 γ<sup>1</sup>**

t = 32sec

**β<sup>2</sup> A5 γ<sup>1</sup>**

t = 64sec

**β<sup>2</sup> A5 γ<sup>1</sup> β<sup>2</sup> A5 γ<sup>1</sup>**

Fig. 22. The transient response of the test chip is taken by the infrared radiation camera

when the virtual cores are activated. These are the back views of the test chip.

t = 128sec

have better thermal conductive

has the best performance among these

**3.4 Results and discussions** 

three combinations.

cores with the metallic thermal skeleton type

t = 1sec

**β<sup>2</sup> A5 γ<sup>1</sup>**

**β<sup>2</sup> A5 γ<sup>1</sup>**

t = 2sec

**β<sup>2</sup> A5 γ<sup>1</sup>**

t = 4sec

t = 8sec

results show that the metallic thermal skeleton

The cost of thermal ridges and metallic thermal skeletons may be compared with the advanced techniques, such as micro-channel liquid cooling or the thermo-electric cooling (TEC). Since by ITRS, the number of stacked dies is expected to increase in the future, the cooling problem of the inter-layer dies will become more challenging. If the heat should be removed by pumping liquid or external energy into the stacked dies, the cooling cost will grow exponentially. The thermal ridges and metallic thermal skeletons proposed in this chapter will be relatively cost-effective and energy-saving. Moreover, this proposed method locally improves the temperature non-uniformity, and the thermal gradient of the most part of the chip also decreases. Nevertheless, the global temperature non-uniformity which affects the chip operations from the electrical perspective deserves more efforts to pursue. Since the 3D IC with TSV now appears as an emerging technology, the early floorplan for the insertion of thermal ridges and metallic thermal skeletons for thermal management will be discussed more and more widespread. The temperature distributions measured by the

Three-Dimensional Integrated Circuits Design

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