**5. Characteristics of the proposed algorithm operation with high imbalances**

The main feature of the algorithm is that it keeps the voltage in the NP controlled, even when there are big current imbalances during capacitor charge. This means that PV2 injects a different current than PV1.

Figure 10 shows the system simulation results with the proposed algorithm under the DCbus specifications listed in Table 4, for a ±2V band.


Table 4. Simulations conditions.

It can be seen that both capacitor voltages remain within the fixed band, and that line voltage matches with the one simulated in the Figure 3. This, however, is not true for phase voltage since it can be clearly seen that it tends to be connected to +Udc for positive values, and to 0V for negative values. This does not happen when injected current into the bus is symmetric.

In this case the number of switches is 914, which means an increase rate of 50.82 % over the simulation without the algorithm. However, in this case there is no choice, as there is no way to keep bus balanced when such imbalances are applied.

As shown in Section II, the algorithm induces the vector shift at the moment that each phase is connected to the same capacitor, meaning that an adequate state combination happens. If we consider that both capacitors have the same reference voltage, the maximum allowed imbalance can be calculated. If given:

$$D\_V > 1 - m = 1 - \frac{\mathcal{U}\_{DC}}{\sqrt{2}V\_L} \tag{11}$$

where *DV* is the duty cycle when vector shift can be done, and m is the modulation index.

Fig. 10. Simulation results for a ±2V ripple with IPV2=0.6IPV1.

Now, consider the following equations in terms of D*V:* 

$$P\_{PV\_{\text{max}}} = \frac{P\_G}{2} (1 + D\_V) \tag{12}$$

And, also:

334 Solar Radiation

Table 3 shows both the amount and the rate of increase of switches for the applied algorithm

±2V band 761 25,58% ±1V band 1027 69,47% ±0,5V band 1749 188,61%

Therefore, it can be affirmed that reducing the ripple to NP ripple values causes an increase in switches and, therfore, losses, but does not reduce ripple in the DC-Bus. Because of this, it

So, when the power injected into grid is lower, the NP ripple is also lower and the number of times that the algorithm has to shift, is lower, making the number of swiches lower as

**5. Characteristics of the proposed algorithm operation with high imbalances**  The main feature of the algorithm is that it keeps the voltage in the NP controlled, even when there are big current imbalances during capacitor charge. This means that PV2 injects

Figure 10 shows the system simulation results with the proposed algorithm under the DC-

IPV1 IPV2 UrefVc1 UrefVc2 125 A 75 A 375 V 375 V

It can be seen that both capacitor voltages remain within the fixed band, and that line voltage matches with the one simulated in the Figure 3. This, however, is not true for phase voltage since it can be clearly seen that it tends to be connected to +Udc for positive values, and to 0V for negative values. This does not happen when injected current into the bus is

In this case the number of switches is 914, which means an increase rate of 50.82 % over the simulation without the algorithm. However, in this case there is no choice, as there is no

As shown in Section II, the algorithm induces the vector shift at the moment that each phase is connected to the same capacitor, meaning that an adequate state combination happens. If

Without Algorithm 606 0% Proposed in (Pou et al., 2007) 845 39,44%

Table 3. Amount and rate of increase of switches in different simulations.

is not effective to use NP ripple values lower than DC-Bus ripple values.

Amount Increase Rate %

with different voltage spans.

a different current than PV1.

Table 4. Simulations conditions.

symmetric.

bus specifications listed in Table 4, for a ±2V band.

way to keep bus balanced when such imbalances are applied.

well.

$$P\_{PV\_{\min}} = \frac{P\_G}{2} (1 - D\_V) \tag{13}$$

The UmbMax is:

$$
\Delta Imb\_{\text{Max}} = \frac{P\_{PV\_{\text{min}}}}{P\_{PV\_{\text{max}}}} \tag{14}
$$

From (12), (13) and (14):

$$\frac{P\_{PV\_{\min}}}{P\_{PV\_{\max}}} = \frac{\{1 - D\_V\}}{\{1 + D\_V\}} \tag{15}$$

Now, the maximum imbalance condition can be given, guaranteeing functionality of the algorithm. From (11), (12), (13), (14) and (15):

$$\text{Lbm}\_{\text{Max}} = \frac{\left(\mathbf{1} - D\_V\right)}{\left(\mathbf{1} + D\_V\right)} > \frac{\mathbf{U}\_{\text{DC}}}{\sqrt{8}V\_L - \mathbf{U}\_{\text{DC}}} \tag{16}$$

Taking into account that VL is considered constant, maximum asymmetry is fixed by DCbus voltage, which is typically variable when coming from photovoltaic panels. Therefore, the system will work at its maximum performance as long as maximum asymmetry is met.

As a solution for higher asymmetries than the maximum asymmetry, the DC-bus voltage can be increased, although when this happens, it moves output away from the maximum power point of the panels.
