**3.1.2 Hardware design**

244 Wireless Communications and Networks – Recent Advances

Here we only focus on the indoor wireless MIMO channel for WLAN like devices. The measurement system supports 20/40MHz bandwidth by suitable RFIC [16][17]. The system

Sampling frequency s*f* 60MHz Symbol rate of PN sequence *R*symb 20M Symbol/s

Period of PN sequence, express in units of *T*symb *N*PN 127 Length of CIR, express in units of *T*symb *N*CIR 127 Sampling interval *T*<sup>s</sup> <sup>s</sup> 1 *f* Interpolated sample interval *T*<sup>i</sup> symb *T* 2 Symbol interval of PN sequence *T*symb symb 1 *R*

Symbol timing synchronizer is a critical module of the digital receiver design of the channel sounder based on sliding correlation channel measurement. Gardner's symbol timing recovery method is used in this system [18][19]. The structure of the symbol timing synchronizer is shown in Fig. 4. All the processing of this synchronizer is done in digital domain. No interaction between analog and digital part of the system is needed. This synchronizer is capable of compensating sampling phase and frequency offset and is

Interpolator Timing error

*yk*  (*T*i)

detector

*un*

(*T*symb)

*yk*  (*T*symb)

Loop filter

The sampled data *ym* , which is filtered by matching filter, is then feed into the interpolator to compute the desired sampled strobe *<sup>k</sup> y* . This is done by digital interpolation, controlled

*wk*  (T*symb*)

the NCO is / *TT K i symb* , where *K* is an integer. The loop consisting of timing error

detector, loop filter and NCO function just like a DPLL, where *un* , *wk* and

timing error signal, NCO control word and NCO register content respectively.

*<sup>k</sup>* . Ideally, the period of

*<sup>k</sup>* represents

by NCO (Numerical Controlled Oscillator) and fraction interval

NCO

*ηk* 

*μk* 

Compute *μ*

(*T*i)

(*T*i)

**Name Symbol Value** 

parameters of baseband are listed in Table 1.

**3.1.1.2 Symbol timing synchronizing algorithm** 

Table 1. System Parameters.

independent of carrier phase [20].

*ym*  (*T*s)

underflo

Fig. 4. Symbol timing synchronizer.

The whole measurement system hardware consists of several modules: antennas module, multi-channel AD/DA module, baseband processing FPGA board, USB access module and a computer Graphical User Interface (GUI) module. The architecture of hardware is showed in Fig. 5. The RF board is based on MAX2829, which can support MIMO operation. We choose the FFP board (IAF GmbH) as FPGA prototyping platform for baseband signal processing, RF control and interface to PC. The interface between the FFP board and the PC is an USB2.0 port. The GUI program runs on the computer for user to control the channel measurement functions and demonstrate the real time test results. Because the most effort is on the development of FPGA, here we focus on the design of baseband transceiver.

Fig. 5. Hardware architecture of the channel measurement system.

The baseband transceiver module performs the baseband signal processing of a 2x2 MIMO channel sounder. This module generates the baseband probing signal, i.e. a BPSK modulated PN sequence, and delivers the CIR extracted from the received signal to the upper-level module.

The block diagram of this module is shown in Fig. 6. The module can be divided into three parts. The first part is the transmitter, which includes signal generator and transmit multiplexer. The second part is the receiver, which includes receive buffers, signal processor, and data buffer. The last part is the control logic of the module.

The functions of the sub-modules are as follows:


 Signal processor performs the signal processing, i.e. filtering, symbol timing, and sliding correlation, to extract the CIR from received signal.

Fig. 6. Baseband transceivers.
