**4.1 Programmable voltage standards**

Programmable voltage standards (PJAVS) are made with series-connected subarrays, whose size follows a power of two sequence. Through control of the bias current of each section, the series voltage is set by the code represented by on/off status of array bias lines. To switch subarrays, junctions that can generate a current-controlled, univocally defined voltage, i.e. junctions with a single valued (non-hysteretic) IV curve must be used. To provide signal to noise ratios adequate to metrological applications, critical currents at the mA level are at least required. On the other side, due to the fact that only the first Shapiro step of junctions is used, to achieve voltages of 1 and 10 V, *Vc* even in excess of 100 µV are sought to reduce number of junctions.

As known, the amplitude of the n = 1 quantized Shapiro step normalized to the critical current attains its maximum when the microwave drive frequency and the junction characteristic frequency are nearly equal. This corresponds also to a condition of minimal power dissipation [26]. This leads to optimal *Vc* of 100-200 V.

SINIS junctions achieve the shunting of the capacitance of a SIS junction, by using two, very thin oxide layers, separated by a metallic barrier. They are typically made of Nb/Al/AlOx/Al/AlOx/Al/Nb and have been extensively studied both theoretically and experimentally [29-34]. The best results on these junctions for superconductive electronics applications and especially for programmable voltage standard have been obtained by the PTB group, who realized complete successful circuits for programmable potentiometer at 1 and 10 V level with 7000 and 70.000 junctions respectively. These SINIS junctions feature *Jc* ≤ 1kA/cm, *Vc* as high as more than 250 V at 4.2 K with junction size 100-1000 µm2. SINIS junctions with various values of Al thickness and AlOx barrier transparency have been reported, but, even if they feature *Jc* and *Vc* higher than those given above, their IV characteristic was rather anomalous showing an high residual hysteresis at 4.2 K, and were hardly reproducible.

In general a problem for the SINIS junctions is due to the high transparency of the two insulating barriers, with the necessity to realize very smooth planarization of the underlying films, since the probability of defects such as pinholes is increased. The fabrication process, requiring that the two barriers and the three thin aluminum layers been highly homogenous, has set a limitation to the fabrication of really high number of junctions, as in arrays for programmable voltages at 10 V and more [35].

In SNS junctions the damping of the IV characteristic for non-hysteretic behavior is obtained by using a normal metal as barrier. SNS have high values of *Jc,* but typically the metals used have very low resistivities. Nb/PdAu/Nb junctions have been the first developed type of SNS junctions for this application by NIST group, and have produced stable voltage outputs at 1 V as binary arrays for programmable potentiometers, being also used in circuits for pulse driven AC synthesis [14],[15]. They feature values in the range of 100 kA/cm2 and *Vc*  between 5 and 30 V with typical size of few µm2, even if *Jc* values would support also submicron dimensions. The values of *Vc* limit their use to drive frequencies of few GHz and circuits have about 30.000 junctions for 1 V.

Impressive results have been obtained with NbN/TiN/NbN junctions, developed by the Tsukuba group, since very large arrays, with more than 300.000 series connected junctions have been succesfully tested in a 8 and 11 bit DAC circuits with quantized steps at 10 V at 10 K [36],[37]. Features of these junctions are Jc about 10 to 10 A/cm and Vc 10-20 V at 10 K with areas of few square micrometer. 20 V output has been also achieved, by series connecting two arrays of different chips, minimizing interconnecting dissipation [9].

Materials have been also proposed as normal metal barrier which are at the metallic insulator transition. In such a way it was possible to tune the barrier resistivity and the characteristic voltage of the junctions [38],[39]. Among the experimental results we mention Nb/TaOx/Nb, NbN/TaN/NbN and Nb/NbxSi/Nb junctions. Nb/TaOx/Nb junctions fabricated at IEN-INRiM, showed resistivities varying different order of magnitudes depending on the bias voltage of the cathode during the sputtering deposition of the TaOx film [40]. The junctions have however a marked aging, featuring a reduction of at values less than 10 A/cm. Also NbN/TaN/NbN junctions studied in [41] have not yet been suitable for large circuits production. These junctions featured very high *Vc*, up to more than 0.5 mV at 4.2 K with *Jc* 104-105 A/cm2, but required a difficult tuning of fabrication parameters and also the temperature dependence of these parameters was critical.

In this category, Nb/NbxSi1-x/Nb junctions represent the most successful attempt so far. Although previously studied by Barrera and Beasley in the '80 [42], the most promising results have been achieved in the last years by the NIST researchers, which experimented these junctions in arrays at 1 V level [43]. These authors achieved a transition from a conductive to an highly resistive phase by varying the sputter deposition power of the two elements. Jc varying from 10 to 10 kA/cm2 and Vc from few V to 150 V and more at 4.2 K have been obtained. The stabilization of the barrier stoichiometry, critical aspect of this type of junctions, can be achieved by a thermal annealing after the deposition of the trilayer. Depending on the Nb content and the barrier thickness, also the temperature stability of these junctions can be optimized, see in a next section [44].
