**3.1 Structure and optimum values of the proposed logic gates**

The proposed logic gate is a square lattice two dimensional PhC that consists of silicon dielectric rods in air background. The structure has a width of 23 2*a* in x-direction and a length of 25 2*a* in z-direction. The dielectric constant and the refractive index of the dielectric rods are 12.0 and 3.46 respectively. In this structure the square lattice is oriented at 45° with the interface parallel to the Γ-M direction with period *a*' = 2*a* where '*a*' is a lattice constant. Successive cells are shifted by δx along the x axis and δz along the z axis. The amount of shifting is x= z= /2= 2 /2 *a*' *a* . The Figure 4a, 4b and 4c illustrate the 2D PhC lattice used for designing logic gates. The circles represent the silicon rods whose radii are r=0.35*a* =105 nm, where *a*=302 nm is the lattice constant.

The schematic circuital layout of the proposed logic gates is shown in Figure 4d. Electrical input signals 1 and 2 activate synchronized laser light sources 1 and 2 respectively to generate optical input signals I1 and I2. The reference signal Iref is obtained from reference laser phase locked with lasers 1 and 2. All the input signals including reference have same frequency, polarization, phase, and optical path, with only the reference signal having different amplitude for different gate types. Two input optical signals are coupled using Y coupler and applied to one of the input port of the crystal device and the reference signal

wave is totally reflected back into the high refractive index medium at the interface, provided the incident angle is larger than the critical angle given by θc = sin-1(nl/nh) (Chul-Sik Kee et al., 2007) . Self-collimated beams can be totally reflected at the interface of a PhC and air because PhC and air correspond to high refractive and low refractive mediums respectively. When it undergoes total internal reflection, the field amplitude decays very rapidly into air and becomes negligible at a distance within one lattice constant. An air layer created by introducing a line defect by removing a few rods in a row is expected to give rise to total internal reflection. Reflection provides a mechanism for bending and splitting of

All-optical logic gates will be the key elements used in next generation optical computer and optical network. All-optical signal processing can handle large bandwidth signals, large information flows and no need of electrical to optical conversion. All-optical logic gates are capable of performing many logic functions. These are expected to find many applications in optical communication, photonic microprocessors, optical signal processors, optical instrumentation, etc. AND logic gate is used to perform address recognition, packet-header modification, and data-integrity verification. All-optical AND-gates have served as sampling gates in optical sampling oscilloscopes (Westlund, et al., 2005) owing to their ultrafast operation compared to traditional electrical methods. XOR gates can perform a diverse set of processing functions, including comparison of data patterns for address recognition and subsequent packet switching, optical generation of pseudorandom patterns, data encryption/decryption, and parity checking. Threshold detector functionality can be realized by XNOR logic gate. All-optical NOT-gates can be used as inverter and switches. Combination of logic gates may be employed to perform basic or complex computing and arithmetic functions such as binary addition, subtraction, comparison, decoding, encoding

The proposed logic gate is a square lattice two dimensional PhC that consists of silicon dielectric rods in air background. The structure has a width of 23 2*a* in x-direction and a length of 25 2*a* in z-direction. The dielectric constant and the refractive index of the dielectric rods are 12.0 and 3.46 respectively. In this structure the square lattice is oriented at 45° with the interface parallel to the Γ-M direction with period *a*' = 2*a* where '*a*' is a lattice constant. Successive cells are shifted by δx along the x axis and δz along the z axis. The

PhC lattice used for designing logic gates. The circles represent the silicon rods whose radii

The schematic circuital layout of the proposed logic gates is shown in Figure 4d. Electrical input signals 1 and 2 activate synchronized laser light sources 1 and 2 respectively to generate optical input signals I1 and I2. The reference signal Iref is obtained from reference laser phase locked with lasers 1 and 2. All the input signals including reference have same frequency, polarization, phase, and optical path, with only the reference signal having different amplitude for different gate types. Two input optical signals are coupled using Y coupler and applied to one of the input port of the crystal device and the reference signal

x= z= /2= 2 /2 *a*' *a* . The Figure 4a, 4b and 4c illustrate the 2D

**3.1 Structure and optimum values of the proposed logic gates** 

self-collimated beams.

and flipflops.

amount of shifting is

 

are r=0.35*a* =105 nm, where *a*=302 nm is the lattice constant.

**3. All optical logic gates** 

Iref is launched at the second input port. The photonic crystal structure with mirror and splitter performs a specific logic gate function by combining the reflected signal and the partially transmitted reference signal. The optical output is detected and converted into electrical signal by photo detector. This structure can be used for stand alone logic gates. In an integrated circuit the output value will be standardized using a PhC amplifier and given to the input port of the next in sequence logic gate and so on.

Fig. 4. a Proposed structure of AND, NAND, NOR & XNOR logic gates

Fig. 4. b Proposed structure of XOR logic gate

Fig. 4. c Proposed structure of OR logic gate

Optical Logic Devices Based on Photonic Crystal 73

difference between the transmitted and the reflected signal is –π/2 and if it is less than host

PhC logic gate structure consists of four ports. Inputs and reference inputs are applied to port 1 and port 2 and the outputs are taken from the output ports 1 and 2. All incident signals including reference signal having the same wavelength of 1.55 μm, phase, and polarization. At the interfering point the path lengths of input signals are equal that is the path length from the AMS is equal to the path length BS which is set as 16 2*a* . The reflected input signal from the mirror interferes with another signal at the splitter. This interference is either constructive or destructive depending on their phase difference. The output taken

Based on the relation between the transmitting and the reflecting signal t2+ r2=1, the

*u i R e*

 <sup>E</sup> <sup>1</sup> <sup>2</sup> 12

<sup>2</sup> 22 *<sup>u</sup> <sup>T</sup> <sup>i</sup> <sup>e</sup>* 

12 22 2 *<sup>u</sup> <sup>i</sup> <sup>i</sup> OR T e e*

where R12 is reflected input signal 1 at splitter and T22 is the transmitted input signal 2 and 1 and 2 are the phase shifts of reflected and transmitted signals respectively. The resultant signal at the output port is a linear combination of reflected and transmitted beam,

2 *<sup>u</sup> i i IO e e*

Intensity of the reference signal is set at different levels according to the desired logic gates. In our simulations the mesh sizes in the *x*- and *z*- directions are set to be *a* /16. The time step

2 2

*x y*

 

 1 1 1

periodicity of the PhC. The transmitted and reflected signals are expressed as

.The propagation of a wave in a periodic medium is governed by the Floquet-

E 1 2

 

(25)

 

and the reflection amplitude is

, where E is a plane wave and *u(r)* has the

(22)

(23)

(24)

(26)

rods radii the phase difference is π/2 (Deyin Zhao et al., 2007).

from the output port 1 is destructive and port 2 is constructive.

transmission amplitude of the beam is e / 2 *<sup>i</sup>*

<sup>E</sup> <sup>2</sup>

<sup>2</sup> <sup>2</sup> <sup>E</sup> 1 2

*t*

*c*

for this mesh size is calculated from the Eq. 26

Bloch theorem which is given by ( ) ( )E *<sup>i</sup> Er ur e*

( ) <sup>2</sup> e / 2

expressed as

and its corresponding intensity

*i* 

Fig. 4. d Schematic circuital layout of the proposed logic gates

The proposed photonic crystal based logic gate utilizes both bending and splitting mechanisms of self collimating beam. In this structure two line defects are created by reducing the radius of 15 rods in the Γ**-X** direction. First line defect, in which 15 rods are completely removed act as mirror (M) and second one, in which the radius of the defect rods are reduced act as a splitter (S). When the self collimated beam is incident at rod-air interface, it is partially reflected and partially transmitted and there is a phase change 'ø' occurs in the reflected wave. The power splitting ratio at the line defect and phase difference between the transmitted and reflected signals are dependent on the radius of the rod. From the Figure 5 it is evident that at the defect rod radius rd=83nm=0.274*a* the transmitted and the reflected powers are divided equally and at rd=0 the mirror completely reflects the incident beam. Thus mirror completely reflects the incident beam and the splitter splits the beam with the power ratio 50:50.

Fig. 5. Normalized transmitted and reflected power with respect to defect rod radius

The phase difference between the transmitted and reflected beam depends on the defect rod radius. If the defect rods radii rd varied and greater than host rods radii the phase

The proposed photonic crystal based logic gate utilizes both bending and splitting mechanisms of self collimating beam. In this structure two line defects are created by reducing the radius of 15 rods in the Γ**-X** direction. First line defect, in which 15 rods are completely removed act as mirror (M) and second one, in which the radius of the defect rods are reduced act as a splitter (S). When the self collimated beam is incident at rod-air interface, it is partially reflected and partially transmitted and there is a phase change 'ø' occurs in the reflected wave. The power splitting ratio at the line defect and phase difference between the transmitted and reflected signals are dependent on the radius of the rod. From the Figure 5 it is evident that at the defect rod radius rd=83nm=0.274*a* the transmitted and the reflected powers are divided equally and at rd=0 the mirror completely reflects the incident beam. Thus mirror completely reflects the incident beam and the splitter splits the

Fig. 5. Normalized transmitted and reflected power with respect to defect rod radius

The phase difference between the transmitted and reflected beam depends on the defect rod radius. If the defect rods radii rd varied and greater than host rods radii the phase

Fig. 4. d Schematic circuital layout of the proposed logic gates

beam with the power ratio 50:50.

difference between the transmitted and the reflected signal is –π/2 and if it is less than host rods radii the phase difference is π/2 (Deyin Zhao et al., 2007).

PhC logic gate structure consists of four ports. Inputs and reference inputs are applied to port 1 and port 2 and the outputs are taken from the output ports 1 and 2. All incident signals including reference signal having the same wavelength of 1.55 μm, phase, and polarization. At the interfering point the path lengths of input signals are equal that is the path length from the AMS is equal to the path length BS which is set as 16 2*a* . The reflected input signal from the mirror interferes with another signal at the splitter. This interference is either constructive or destructive depending on their phase difference. The output taken from the output port 1 is destructive and port 2 is constructive.

Based on the relation between the transmitting and the reflecting signal t2+ r2=1, the transmission amplitude of the beam is e / 2 *<sup>i</sup>* and the reflection amplitude is ( ) <sup>2</sup> e / 2 *i* .The propagation of a wave in a periodic medium is governed by the Floquet-Bloch theorem which is given by ( ) ( )E *<sup>i</sup> Er ur e* , where E is a plane wave and *u(r)* has the periodicity of the PhC. The transmitted and reflected signals are expressed as

$$R\_{12} = \frac{\iota \mathbb{E}}{\sqrt{2}} e^{i\phi\_1} \tag{22}$$

$$T\_{22} = \frac{u\mathbb{E}}{\sqrt{2}}e^{i\phi\_2} \tag{23}$$

where R12 is reflected input signal 1 at splitter and T22 is the transmitted input signal 2 and 1 and 2 are the phase shifts of reflected and transmitted signals respectively. The resultant signal at the output port is a linear combination of reflected and transmitted beam, expressed as

$$\dot{\phi}O = R\_{12} + T\_{22} = \frac{\mu \mathbb{E}}{\sqrt{2}} \left( e^{i\phi\_1} + e^{i\phi\_2} \right) \tag{24}$$

and its corresponding intensity

$$I = \left| O \right|^2 = \left| \frac{u \to}{\sqrt{2}} \left( e^{i\phi \mathbf{1}} + e^{i\phi \mathbf{2}} \right) \right|^2 \tag{25}$$

Intensity of the reference signal is set at different levels according to the desired logic gates. In our simulations the mesh sizes in the *x*- and *z*- directions are set to be *a* /16. The time step for this mesh size is calculated from the Eq. 26

$$\nabla t = \frac{1}{c\sqrt{\frac{1}{\nabla x^\*} + \frac{1}{\nabla y^\*}}}\tag{26}$$

Optical Logic Devices Based on Photonic Crystal 75

To realize AND logic, inputs I1 , I2 and reference beam Iref are taken as P0 and 0.5P0 and combined inputs I1 and I2 are applied at input port 1 and Iref is applied at port 2. The destructive interfered signal at the output port 1 is considered as a AND output. In AND logic, when both the input signals are high the output is high otherwise it is zero. In simulation it is found that the output intensity is 0.24P0 for separate excitation of I1 and I2 and 0.751P0 for simultaneous excitation of both I1 and I2. If both the signals are not applied the output is 0.25P0.In the case of NOR gate, inputs I1 , I2 and reference beam Iref are considered as P0 and 1.5P0 respectively. The logic function of this gate is, if both the inputs are low the output is high or else it is zero. The simulation results show that when both the input signals are zero the output is 0.759P0 and if any one signal is applied the output is

> AND (Iref= 0.5P0) NOR ( Iref =1.5P0) O/P power Logic level O/P power Logic level

0.25P0. Truth table for AND logic and NOR logic gates is tabulated in Table 2.

0 0 0.25P0 0 0.759P0 1 0 1 0.24P0 0 0.25P0 0 1 0 0.24P0 0 0.25P0 0 1 1 0.751P0 1 0.25P0 0

Steady state electromagnetic field distributions of NOR gate and AND gate for various

0 0 0 0 0 0 0 1 0.5P0 1 0.5P0 1 1 0 0.5P0 1 0.5P0 1 1 1 0.001P0 0 1.00 P0 1

XOR OR O/P power Logic level O/P power Logic level

I1 I2

I1 I2

Table 1. Truth table for XOR and OR gate

Table 2. Truth table for AND logic and NOR gate

input combinations are shown in Figure 8 and Figure 9 respectively.

(a) (b) (c)

Fig. 8. Electromagnetic field distributions of NOR logic gates. (a) no input signal is applied (b) any one of the input signal is applied c) both input signals are applied simultaneously

**3.2.2 AND logic and NOR logic gates**

and it is found to 0.04 femtosecond. The calculated area is surrounded by a Perfectly Matched Layer (PML) boundary.
