**3.2.2 AND logic and NOR logic gates**

To realize AND logic, inputs I1 , I2 and reference beam Iref are taken as P0 and 0.5P0 and combined inputs I1 and I2 are applied at input port 1 and Iref is applied at port 2. The destructive interfered signal at the output port 1 is considered as a AND output. In AND logic, when both the input signals are high the output is high otherwise it is zero. In simulation it is found that the output intensity is 0.24P0 for separate excitation of I1 and I2 and 0.751P0 for simultaneous excitation of both I1 and I2. If both the signals are not applied the output is 0.25P0.In the case of NOR gate, inputs I1 , I2 and reference beam Iref are considered as P0 and 1.5P0 respectively. The logic function of this gate is, if both the inputs are low the output is high or else it is zero. The simulation results show that when both the input signals are zero the output is 0.759P0 and if any one signal is applied the output is 0.25P0. Truth table for AND logic and NOR logic gates is tabulated in Table 2.


Table 2. Truth table for AND logic and NOR gate

Steady state electromagnetic field distributions of NOR gate and AND gate for various input combinations are shown in Figure 8 and Figure 9 respectively.

Fig. 8. Electromagnetic field distributions of NOR logic gates. (a) no input signal is applied (b) any one of the input signal is applied c) both input signals are applied simultaneously

Optical Logic Devices Based on Photonic Crystal 77

Fig. 11. Field distribution of NAND logic gates a) no input is applied b) any one of the input

0 0 1.25P0 1 0.505P0 1 0 1 0.756P0 1 0.001P0 0 1 0 0.756P0 1 0.001P0 0 1 1 0.25P0 0 0.505P0 1

In a complete packaged system, photonic crystal based laser light sources, logic gates and detector are integrated within a single chip. Figure 12 illustrates the integrated photonic crystal based devices. Light source laser is based on a 2D photonic crystal slab patterned with a square lattice. Holes are drilled in GaAs dielectric material. The periodicity of the holes is fixed at 315 nm, and the hole radius is tuned from 105 to 130 nm to change the resonance frequency of the cavities (Hatice Altug et al., 2006). Lasers are driven by the given electrical signals and the corresponding optical output is applied to the all-optical logic gate. Laser 1 & 2 output signals are coupled using coupler and launched to the input port 1 of logic gate and the phase locked reference signal is applied to input port 2. All-optical logic

In the integrated photonic crystal based logic gates, output value of the logic gate will be standardized using a PhC amplifier. The gain of the amplifier is adjusted such that the output level is either "1" or "0". In Figure 12 AND logic gate output is standardized and given to one of the input of XOR gate and other input is getting from the output of another preceding logic gate. Thus the standardized output of one logic gate is given to the input port of the next in sequence logic gate and so on. Finally the output of the last logic gate is applied to the photodetector. The photodetector detects the optical signal. Photo detector is designed using triangular air-hole photonic crystal with lattice constant is 420nm and slab thickness is 204 nm (M Notomi and T Tanabe 2010). The detector converts the optical signal

NAND(Iref=2.5P0) XNOR ( Iref =P0) O/P power Logic level O/P power Logic level

(a) (b) (c)

**4. Photonic crystal optical logic devices for a packaged system** 

signal is excited c) both the signals are applied simultaneously

Table 3. Truth table for NAND logic and XNOR logic gate

gate performs the logical functions in optical domain.

I1 I2

into electrical output.

Fig. 9. Electromagnetic field distributions of AND logic gates. a) both the input signals are low b) any one of the input signal is high c) both input signals are high.

#### **3.2.3 NAND and XNOR logic gates**

For NAND logic realization, inputs I1 and I2 are set as P0 and reference beam Iref is set as 2.5P0. These are applied at input port 1 and 2 respectively. In NAND logic, when both the input signals are high the output is zero and any one of the input signal is low the output is high. It is evident from the simulation that when none of the signal is applied the output is 1.25P0 and if any one of the signal is applied the output is 0.756P0. If both the signals are excited the output is 0.25P0. The inputs I1 & I2 and Iref are considered as P0 for XNOR gate realization. Logic operation for XNOR gate is known that when both the inputs are same the output is high and if both the inputs are different the output is low. In simulation, it is found that the output is 0.505 P0 for simultaneous excitation of inputs and also for none of the input signal. When any one of the signal is applied the output is 0.001P0. The simulated field distributions of XNOR logic gate are illustrated in Figure 10 and NAND logic gate field distribution is shown in Figure 11. Table 3 explicates the truth table for NAND and XNOR logic gates.

Fig. 10. Electromagnetic field distributions of XNOR logic gates. (a) both the input signals are low b) any one of the input signal is applied (c) both the input signals are applied simultaneously.

(a) (b) (c)

low b) any one of the input signal is high c) both input signals are high.

(a) (b) (c)

Fig. 10. Electromagnetic field distributions of XNOR logic gates. (a) both the input signals are low b) any one of the input signal is applied (c) both the input signals are applied

**3.2.3 NAND and XNOR logic gates**

table for NAND and XNOR logic gates.

simultaneously.

Fig. 9. Electromagnetic field distributions of AND logic gates. a) both the input signals are

For NAND logic realization, inputs I1 and I2 are set as P0 and reference beam Iref is set as 2.5P0. These are applied at input port 1 and 2 respectively. In NAND logic, when both the input signals are high the output is zero and any one of the input signal is low the output is high. It is evident from the simulation that when none of the signal is applied the output is 1.25P0 and if any one of the signal is applied the output is 0.756P0. If both the signals are excited the output is 0.25P0. The inputs I1 & I2 and Iref are considered as P0 for XNOR gate realization. Logic operation for XNOR gate is known that when both the inputs are same the output is high and if both the inputs are different the output is low. In simulation, it is found that the output is 0.505 P0 for simultaneous excitation of inputs and also for none of the input signal. When any one of the signal is applied the output is 0.001P0. The simulated field distributions of XNOR logic gate are illustrated in Figure 10 and NAND logic gate field distribution is shown in Figure 11. Table 3 explicates the truth

Fig. 11. Field distribution of NAND logic gates a) no input is applied b) any one of the input signal is excited c) both the signals are applied simultaneously


Table 3. Truth table for NAND logic and XNOR logic gate
