**7.1 Hybrid STDP synapses**

**Figure 7a** shows a hybrid RRAM-CMOS synapse example with a 2T1R design that consists of one RRAM element and two transistors [ 228 ]. The top electrode of the RRAM device and the gate of one transistor known as the communication transistor are both driven by the pre-synaptic neuron. It displays the voltage VTE applied to the top electrode and VCG applied to the communication gate's gate, both of which are applied during a spike event by the pre-synaptic neuron. A synaptic current that spikes as a result of the applied voltage spikes in the figure, which is proportional to the conductance of the RRAM, acts as a storage component for synaptic weight. According to the schematic circuit of **Figure 7c** , synaptic current travels via the

*Neuromorphic Computing between Reality and Future Needs DOI: http://dx.doi.org/10.5772/intechopen.110097*

**Figure 7.**

*Hybrid RRAM-CMOS synapse with 2T1R configuration (a), voltage waveforms for VCG and VTE applied by the pre-synaptic neuron in the spike event (b), and overall circuit sketch including the synapse and the pre- and post-synaptic neurons [232].*

synaptic circuit and is fed into the input terminal of the post-synaptic neuron, where integration and firing occur. The input node of the post-synaptic neuron is a virtual ground, guaranteeing a zero voltage at the bottom electrode of the 2T1R synapse and acting as a summing input for a practically infinite number of synaptic channels. The post-synaptic neuron fires when the integrated current exceeds a predetermined threshold, sending spikes to the subsequent neurons in the network and applying a feedback spike to the fire gate.

#### **7.2 Learning with RRAM STDP synapses**

A conceptual demonstration of learning cannot be provided by definitively demonstrating STDP in individual synapses; instead, simulations and experiments at the higher level of synaptic/neural networks are needed. A straightforward example of a feed-forward neural network, known as a perceptron [233–235], is shown in **Figure 8**. The network is made up of two layers: a presynaptic layer where synaptic channels receive neural spikes, and a second layer with just a single postsynaptic neuron to integrate and fire current spikes. Each pre-synaptic neuron is coupled to a post-synaptic neuron via a hybrid CMOS-RRAM synapse, indicating that the network is fully connected. Depending on the time Δt between pre- and post-synaptic spikes, the post-synaptic neuron transmits a feedback spike to each synapse at each fire event to enable LTP/LTD. As a result, submitted patterns, such as images, sounds, or speech, tend to be learned by the network because the synapses corresponding to the pattern channels are potentiated while all other synapses, commonly known as the background synapses, tend to become depressed, thus enabling on-line learning of submitted patterns [226, 228, 229].

#### **Figure 8.**

*Schematic illustration of a perceptron-like neural network with a 4 × 4 first layer, and a single post-synaptic neuron in the second layer. Each neuron in the first layer is connected to the post-synaptic neuron by synapses [232].*

With the recent advancements in ferroelectric devices, nanowire networks, organic materials, and new memory hardware, duplicating the human neural network is now a more realistic possibility. The great ability of memory devices promise synaptic device that can handle massive amounts of data effectively while consuming extremely little power, which is necessary to develop artificial intelligence technologies. The detailed analysis of these memory devices, together with the present problems and future prospects, is covered in the following subsections.

#### *7.2.1 PRAM: phase-change synaptic devices*

Phase-change memory (PRAM), also called PCM, is a type of non-volatile randomaccess memory. A thesis on the viability of a phase-change memory device using chalcogenide film and a diode was published by Charles Sie in 1969 [236]. The phasechange memory process in chalcogenide glass involves electric-field-induced crystalline filament development, according to the following study from 1970 [237, 238].

PRAM uses the resistance difference between the crystalline phase's low resistivity and the high resistivity of the amorphous phase in phase change materials. A phase change material known as T-cell is typically used between two electrodes in PRAM structures. The phase of the material is changed after a high voltage/current is applied to the electrodes. A current pulse is used to anneal and quench the phase-change material to cause it to crystallise in order to set into the crystalline phase. The high resistance amorphous component can be steadily crystallised using a series of Set pulses to achieve the progressive Set function of PRAM devices. The programming region is first melted and then quickly quenched by using a strong current pulse for a brief period of time in order to reset into the amorphous phase.

The device has been investigated as a good candidate for artificial synapses in implementing the machine learning algorithm because of desirable properties as high speed, multi-level capability, and low energy consumption [239–241]. But issues with material quality and power consumption prohibited PRAM technology from being widely used. Resistance drift, which refers to how the resistance changes over time is a particular problem [242–244]. In phase-change materials, resistance drift is a common occurrence that severely hinders the development of PRAM and destroys stability. A structural relaxation, which is a locally rapid local rearrangement thermally induced at intervals the amorphous region, has been used to explain the drift

phenomenon in amorphous chalcogenide materials [243, 245–247]. This implies that the resistance can be modified with time and that a lost memory resembles almost human memory. In addition to the significant reliability problem with amorphous chalcogenide materials, a low power neuromorphic device must overcome the high power need for melting the phase-change material. These reliability and power problems must be solved for PRAM technology to function well as a synaptic device.

#### *7.2.2 Reram: filament type synaptic devices*

One of the leading candidates to replace current memory technology as the next generation is resistive random access memory (ReRAM). The non-volatile nature of ReRAM is the main justification, among many others. Researchers and manufacturers are currently paying close attention to every non-volatile memory. This results in a race between several technologies that practically all offer the same advantages while aiming for the same standard level of performance goals. Each non-volatile memory is competing fiercely to prove that it is a worthy rival in the memory field. Other non-volatile memories of current interest are PCRAM (Phase Change), FeRAM (Ferroelectric), and MRAM (Magnetoresistive). ReRAM is distinguished and enabled to compete with these technologies because of its quick read and write speeds. Additionally, ReRAM's manufacturing is not as difficult as other technologies.

Low dependability and performance variations, on the other hand, are the obstacles preventing its market penetration. Therefore, it still requires significant development in terms of material fabrication, construction, circuit difficulties, and handling unwanted disturbances from the outside environment. ReRAM technology appears to have more benefits than drawbacks, and this good promise for the future of the technology.

ReRAM has a metal-insulator-metal structure, with the insulator positioned between two layers of metal. Both metals form a low resistive state when touched, and a high resistive state when not touched. A conducting filament serves as the structure's central functional part. The rupture of the filament depends on the applied voltage across the metal terminals (**Figure 9**).

ReRAM's ability to store digital data, or 0 s and 1 s, is a result of its structural design. ReRAM typically operates in a High Resistive State [HRS], or logic low referred to as 0; a voltage is applied across ReRAM to switch its state from the High Resistive State to a Low Resistive State [LRS], or logic high referred to as 1. There is

#### **Figure 9.**

*(a) 2D structure of ReRam (b) 3D structure of ReRam [248].*

no suitable path for the current to pass since the filament is disconnected during the HRS. The filament contacts the bottom terminal and produces a low resistance route when an appropriate voltage is placed across the top electrode (TE) and bottom electrode (BE). This is known as coming into LRS, which is also known as logic high, or 1. HRS is the OFF state, and LRS is the ON state. The "Set" voltage is the voltage used to switch the ReRAM state from HRS to LRS. In a similar vein, the voltage used to switch a device from LRS to HRS is known as the "Reset" voltage. After a voltage that is greater than the Reset or Set voltage is applied, the filament either forms or ruptures. This state change is the write operation during putting ReRAM in the desired state to hold a logic. A voltage that is less than the Reset or Set voltage is applied to read the operation, and the output is monitored to determine the state of the ReRAM. In accordance with the polarity of the applied voltage, there are two forms of resistive switching. It could be bipolar or unipolar. In unipolar switching, the voltage's polarity has no dependence on the switching process. In contrast, switching in bipolar switching is dependent on the voltage's polarity, going from HRS to LRS in one case and from LRS to HRS in the other [249].
