**2. IMC architectures**

In the preceding section, we examined the hardware implications of modern DNNs, specifically the memory and computation complexity associated with von Neumann architectures. For instance, dense structures such as DenseNet require roughly 2*:*<sup>7</sup> <sup>10</sup><sup>7</sup> off-chip memory accesses to process an image frame [15]. This elevated number of off-chip memory access negatively impacts the energy efficiency of the overall system. IMC architectures provide a promising alternative to traditional von Neumann architectures. **Figure 3** depicts a generic block diagram of an IMC architecture with RRAM/SRAM memory cells. IMC uses analog- or digital-domain computation to carry out multiply-and-accumulate (MAC) operations. The crossbarbased IMC structure efficiently combines memory access and analog-domain computation into a single unit, resulting in faster execution of DNN workloads. The superior energy efficiency is primarily due to a full-custom design, higher density, and higher memory bandwidth [44, 45, 58]. Consequently, IMC-based systems are becoming increasingly popular for implementing compute- and memory-intensive AI applications. This section will examine various IMC architectures in depth using both SRAM and RRAM memory cells.
