**5. Conclusion**

In this chapter, we discussed benchmarking chiplet-based IMC-based AI accelerators. We discuss various IMC architectures proposed in the literature. CMOS- (e.g., SRAM) and memristor- (e.g., RRAM) based IMC architectures are discussed. Although IMC improves the energy efficiency of computing elements, it increases onchip communication volume. To address this, we discuss chiplet-based in-memory architectures. We also discuss different benchmarking simulators for monolithic and chiplet-based IMC architectures in detail. Finally, we dive deeply into SIAM, a chipletbased IMC benchmarking simulator. SIAM provides a unified framework for performance benchmarking of chiplet-based IMC architectures. SIAM supports both *homogeneous* (*generic*) and custom chiplet-based IMC architectures. Finally, SIAM interfaces with popular deep learning frameworks such as PyTorch and TensorFlow and can be integrated with modern NAS techniques.
