**3. Circuit implementations of the neural encoders**

To utilize the various encoding schemes in the application-specific integrated circuit (ASIC) of neural network systems, the circuit implementations of these neural encoders need to be investigated. This section will discuss the circuit implementations of these different encoders and their simulation results with analog sinusoidal current input.

#### **3.1 Rate encoder**

The schematic of the rate encoder is demonstrated in **Figure 3(a)**. After the clock signal CLK resets the voltage across the membrane capacitor C1 with the switch transistor M8, an encoding window begins. The voltage across the membrane capacitor C1 increases when the input current is injected. When the membrane voltage exceeds the reference voltage Vref, a spike will be fired through the buffer. The fired spike will also trigger the switch transistor M7 to bring the membrane voltage back to

**Figure 3.** *Circuit schematic and simulation result of rate encoder.*

the ground so that the integration process will start over. Thus, the relation between the input current and the spike numbers can be written as:

$$N = \frac{P}{T} = \frac{P}{\frac{C\_m V\_{ref}}{I\_{in}}} = \frac{P I\_{in}}{C\_m V\_{ref}},\tag{6}$$

where *N*, *P*, and *T* represent the spike number, encoding window period, and integration time of one spike. *Iin*, *Cm*, and *Vref* mean the input current, membrane capacitance, and the reference voltage. The formula shows that the number of spikes in the sampling window and the input current have a linear relationship. From **Figure 3(b)**, a similar relationship can be observed. When the input current is high, there are more spikes in the sampling window; when the input current is relatively smaller, there are fewer spikes in the sampling window.

#### **3.2 TTFS encoder**

The schematic of the TTFS encoder is depicted in **Figure 4(a)** [40]. The charge integration mechanism starts after the CLK signal resets the membrane voltage with switch transistor M11. Along with the voltage across the membrane capacitor C1 increasing, the voltage at the source of the transistor M1 will increase at a rate controlled by Vref. When the source voltage of M1 exceeds the threshold voltage of the inverter composing M3 and M4, the output will be digitally high. Almost immediately after the output becomes digital high, the four-transistor clock-controlled inverter also gives a digital high feedback signal to the switch M11 so that the membrane voltage goes back to the ground. Thus, at the output of the encoder, there will only be a spike instead of a square wave at digital high. Moreover, until the next CLK signal, the feedback signal will always be at the high voltage, so there will only be one spike in one sampling window. The time difference between the onset and the spike can be written as:

$$T = \frac{C\_m V\_{ref}}{I\_{in}}.\tag{7}$$

**Figure 4(b)** shows that the time difference is inversely proportional to the input current. The larger the input is, the closer the spike is to the CLK signal.

**Figure 4.** *Circuit schematic and simulation result of TTFS encoder.*

*Spiking Neural Encoding and Hardware Implementations for Neuromorphic Computing DOI: http://dx.doi.org/10.5772/intechopen.113050*

#### **3.3 ISI encoder**

As mentioned in Section 2, the ISI encoder has two different structures. In this section, we will talk in detail about the parallel structure. Although more neurons in the ISI encoder lead to more spikes in one encoding window, it also leads to higher power consumption and a larger design area. Thus, the two-neuron parallel structure ISI encoder circuit will be discussed in this section. The schematic of the encoder is demonstrated in **Figure 5(a)**. The two neurons utilize the same CLK signal and have the same encoding window. The input currents of the two neurons are the same, so the charge integration rates of the neurons are the same. The only difference between the neurons is that they have different reference voltages so that the neurons will fire spike at different times. Afterward, an OR gate is implemented to integrate the two spikes into a two-spike train. With that, the input information is converted to the time intervals of spikes, which can be expressed as:

$$D = T\_2 - T\_1 = \frac{C\_m \left(V\_{ref2} - V\_{ref1}\right)}{I\_{in}}.\tag{8}$$

The simulation result of the ISI encoder is illustrated in **Figure 5(b)**. It is noticeable that when the input is smaller, the time interval of the spike is larger and vice versa. Thus, this encoder has fulfilled the mathematical relation of the information conversion.

#### **3.4 TTFS-phase encoder**

As discussed in Section 2, the TTFS-phase encoding scheme shifts the TTFS-encoded spikes to the immediate local maximum of their corresponding SMOs. Since there is only one channel in our design, as shown in **Figure 6(a)**, the TTFS-phase encoder utilizes only one SMO [37]. To carry out the spike-shifting process, a gamma alignment block is implemented. Inside the gamma alignment block, a peak detector captures and holds the coming spike. The spike voltage will be held across the capacitor with a diode-connected transistor. After that, when the local maximum of the SMO arrives, a spike will be fired by the AND gate and outputted after being stabilized by a buffer. Meanwhile, the spike will trigger the switch transistor and bring the captured voltage back to the ground until the next spike comes.

**Figure 5.** *Circuit schematic and simulation result of ISI encoder*.

**Figure 6.** *Circuit schematic and simulation result of TTFS-phase encoder.*

The peak detector can only detect spikes that last longer than 10 nanoseconds (ns). However, the TTFS neuron can only output 1 ns spikes. Thus, a spike expander, as demonstrated in **Figure 6(a)**, is designed to extend the width of spikes. With Vbias controlling the charging rate on the capacitor, the width of spikes can be adjusted without changing the capacitor and thus save a lot of design area. **Figure 6(b)** illustrates the signal flows in the TTFS-phase encoder. The top panel of the figure represents the TTFS encoding function, while the bottom panel depicts the gamma alignment process. After being encoded by the TTFS neuron, the current signal is converted to spikes, and in the gamma alignment block, the TTFS spikes are moved to the next local maximum of the SMO.

**Figure 7.** *Circuit schematic and simulation result of ISI-phase encoder.*

*Spiking Neural Encoding and Hardware Implementations for Neuromorphic Computing DOI: http://dx.doi.org/10.5772/intechopen.113050*

#### **3.5 ISI-phase encoder**

Similar to the TTFS-phase encoder, the ISI-phase encoder is designed with an ISI encoder with one spike expander and one gamma alignment block, as shown in **Figure 7**. With the spike expander, the output spikes of the ISI encoder have a width of over 10 ns and thus can be captured by the peak detector. To shift the expanded spikes to the local maximum of the SMO, the gamma alignment block is implemented for the spike train in one sampling window. With the two neurons in the ISI encoder, there are two spikes in one encoding window, and thus the SMO frequency should be higher; otherwise, the two spikes in the same encoding window will possibly be moved to the same local maximum to leave only one spike in the sampling window.
