**2. Nanowires synthesis**

Nanowire can be synthesized through three approaches: i) top-down approaches, ii) bottom-up approaches, and iii) the combination of top-down and bottom-up approaches.

### **2.1 Top-down approach**

The top-down approach begins with a bulk material (microscopic materials), which will be by selection removed to create NWs through lithography patterning and wet/dry etching method [35]. From epitaxially grown-up thin films, they provide the advantage of fabricating NWs with exactly controlled doping profile and layer thickness [23]. If this NW structure has a p-n junction, it will be incorporated as an axial p-n junction after the NWs are formed. To create a radial p-n junction, ion implantation and molecular monolayer doping (MLD) can be used [31, 36, 37]. In the fabrication of nanowires, numerous lithographic styles are used with controllable exposure, size, and distance for dependable light-trapping and latterly high-effectiveness solar cells [38]. The traditional optical lithography can offer a high result, but its essential dimension is confined by the optical phenomenon restriction of the sun wavelength [38, 39]. On the other hand, traditional electronbeam lithography (EBL) has a veritably high resolution but suffers from high-cost and low throughput [40, 41]. Nanoimprint lithography (NIL) [42, 43] can be used in order to obtain both high throughput and resolution, and self-powered parallel electron lithography may be used [44, 45]. The NIL technology avoids light diffraction in optical lithography and can fabricate the nanowires with fabricating accuracy up to several nanometers [46]. The process includes lithography patterning, and then dry etching to obtain nanowires with vertical and smooth sidewalls [36, 47]. Subsequently, wet etching processes are also conducted to first etch the remaining etching masks followed by the removal of physically damaged and nonstoichiometric oxidized surface layers [48]. The top-down have disadvantages when compared with bottom-up approaches. It does not offer any material saving and also lack freedom in material design. Furthermore, the etching process could introduce surface defects that adversely affect the nanowire's optical and electrical properties, and thus lead to much-degraded device performance [49].

#### **2.2 Bottom-up approach**

Bottom-up approach NW synthesis is supported by gas-phase epitaxial growth technique to supply detached NW ensembles with or without order. There are many techniques employed under the bottom-up approach for nanowire growth, such as chemical vapor deposition (CVD) [46, 50, 51], chemical-beam epitaxy (CBE) [52, 53], *Solar Energy Conversion Efficiency, Growth Mechanism and Design of III–V Nanowire-Based… DOI: http://dx.doi.org/10.5772/intechopen.105985*

laser ablation [54], and hybrid vapor-phase epitaxy [55, 56]. Nevertheless, III–V semiconductor nanowires are mainly grown by either metal–organic vapor-phase epitaxy (MOVPE) [57–60] or molecular-beam epitaxy (MBE) technique [61, 62] with and without catalysis assistance. Catalyzed growth involves the use of metal nanoparticles, such as Au, Al, and other metals [34].

The catalysts that are used as an assist in the growth of NWs can be external or from the elements of materials used to grow NWs, which are called seed particles. In general, we can classify the NWs growth mechanisms into four as shown in **Figure 1**:

#### **Figure 1.**

*Schematic representation of four basic nanowire growth mechanisms: (a) selective area epitaxy, (b) oxide-assisted growth, (c) homoparticle growth, and (d) heteroparticle growth [63].*

(i) homoparticle growth, (ii) heteroparticle growth, (iii) non-catalyst growth, and (iv) oxide-assisted growth. The seed particles can be homoparticle growth (**Figure 1c**); in this case, a seed particle is formed consisting of one or all elements used for wire growth or it can be simply a self-assisted growth. As the seed particle size varies during growth both length and diameter increase. The seed particles can also be heteroparticle growth (**Figure 1d**) and in this case, a seed particle (typically Au) is deposited prior to growth, in simple words, it is a foreign metal-assisted growth technique. Throughout heating to increase temperature the seed particle alloys with the substrate and/or material forms the gas phase. In this case, particle size during growth is constant. Noncatalyzed growth includes selective area epitaxy (SAE) where growth occurs on a prepatterned substrate [64–66]. In selective area epitaxy, an epitaxial layer nucleates in openings of a mask layer and continuously grows in height; its lateral growth is restricted by low-energy facets (**Figure 1a**). [63, 67]. Oxide-assisted growth (OAG) is additionally a mechanism used in crystal growth with the aid of the semiconductor substance's oxides as a passivating shell to suppress the subsequent growth [68]. During OAG growth, the semiconductor and

#### **Figure 2.**

*Solar cell fabrication process and SEM images. (a) Fabrication steps of GaAs nanowire array solar cells with axial junction, (b) 30° tilted SEM image of as grown vertical GaAs nanowire array on GaAs (111) B substrate, (c) SEM image after nanowires are embedded in BCB and etched by RIE to expose short tips, and (d) SEM image after coating of ITO film by sputtering. A conformal dome-like cap is formed on the tips of nanowires [69].*

*Solar Energy Conversion Efficiency, Growth Mechanism and Design of III–V Nanowire-Based… DOI: http://dx.doi.org/10.5772/intechopen.105985*

its oxide are adsorbed on the substrate, where the semiconductor produces nucleation centers, which also create the semiconductor nanowires, while the oxide forms a passivating shell (**Figure 1b**).

For the non-catalyzed growth method, Maoqing Yao et al. [69] fabricated arrays of GaAs nanowires solar cell with an axial p-i-n junction, which are grown by selective area growth (SAG) method, using mass production compatible metal-organic chemical vapor deposition (MOCVD) technique. This growth method is free of the metal catalyst. The fabrication process of their axial junction GaAs nanowire solar cell is shown in **Figure 2a**. Their fabrication steps are (1) electron-beam lithography is applied to form hole array in silicon nitride mask, (2) SAG of p-i-n GaAs nanowire using MOCVD, (3) BCB infiltration, (4) reactive ion etching (RIE) to expose nanowire tips, and (5) transparent conductive indium tin oxide (ITO) deposition. The SEM images for as-grown vertical GaAs nanowire array (**Figure 2b**), after nanowires are embedded in BCB and etched by RIE to expose short tips (**Figure 2c**) and after coating of ITO film by sputtering (**Figure 2d**) is displayed.
