New Electronic Devices for Power Converters

*Moufu Kong*

#### **Abstract**

Power electronic devices are crucial components of power converter systems. The evolution of power devices drives the development of power converters, including improvements in performance, reliability, and power capacity. In this chapter, the author expounds the structure, working principle, and static and dynamic characteristics of the conventional PN junction diode. And the silicon carbide (SiC) Schottky barrier diode (SBD), junction barrier Schottky (JBS) diode, trench JBS (T-JBS) diode, and sidewall-enhanced trench JBS (SET-JBS) diode are also discussed and compared. Also, the structures and properties of the gallium oxide (Ga2O3) SBD and heterojunction diode are also summarized. Next, the author gives a detailed analysis and discussion of the silicon power metal-oxide-semiconductor field-effect transistor (MOSFET), superjunction MOSFET, and the SiC MOSFET and JFET, and the Ga2O3 MOSFET. Then, the device structure and operating principle, switching characteristics, and current tailing mechanism of the insulated gate bipolar transistor (IGBT) are also analyzed and summarized in detail. Finally, the energy band structure, working principle, and switching characteristic of the gallium nitride (GaN) high-electron mobility transistor (HEMT), one of the hot devices in the current market, are also described. Finally, the summary and prospect of power electronic devices are also presented in this chapter.

**Keywords:** electronic device, superjunction, IGBT, SiC diode, SiC MOSFET, GaN HEMT, Ga2O3 diode

#### **1. Introduction**

Power electronic devices are the core components of power converters and directly affect the performance and reliability of power converters. In recent years, in addition to conventional silicon-based devices, some new electronic devices have emerged, which are widely used in power conversion systems and play an important role in the performance improvement and development of power converters. This chapter explains the traditional silicon-based power diodes and power MOSFET and also describes the structures and working principles of superjunction power MOSFET devices and IGBT power devices. More importantly, with the development of the wide-bandgap semiconductor technology, SiC diodes, SiC MOSFETs, SiC JFETs, and GaN HEMTs are also widely used in various power

converters and power electronic systems, so this chapter also describes the widebandgap power semiconductor devices. At the same time, the ultra-wide bandgap power semiconductor devices represented by gallium oxide (Ga2O3) have also become a research hotspot, and this chapter also explains the Ga2O3 power diodes and Ga2O3 power MOSFETs. Finally, the development trend of new electronic devices is also summarized.

#### **2. Power diodes**

#### **2.1 Silicon PN junction diode**

Silicon power diodes are the most commonly used power electronic devices, and their basic principle is the unidirectional conductivity of the PN junction diode. When a P-type doping and a N-type doping are performed on a semiconductor material, a PN junction is formed at the interface. Due to the existence of the doping concentration gradient at the interface, the holes in the P-type region diffuse to the N-type region and recombine with the majority carrier electrons in the N-type region. Similarly, the electrons in the N-type region diffuse to the side of the P-type region and recombine with the majority carrier holes of the P-type region. And a space charge region is formed at the interface, in which the N-type side has only positive charges ionized by the donors, and the P-type region has only negative charges ionized by the acceptors. Therefore, an electric field directed from the N-type region to the P-type region is formed at the space charge region. And under the action of this electric field, the minority carrier holes in the N-type region drift toward the P-type region, and the minority carrier electrons in the Ptype region also drift toward the N-type region. The diffusion and drift motions of carriers will eventually reach a dynamic equilibrium, and the width of the space charge region (depletion region) remains constant, and the built-in electric field (*E*) is also maintained constant. **Figure 1** shows the equilibrium PN Junction and its space charge region.

The diode is formed when the PN junction chip is packaged and the anode (A) and cathode (K) electrodes are led out. When the PN junction (or diode) is forward biased, since the external electric field (*E*V) and the built-in electric field (*E*) are in

**Figure 1.** *Equilibrium PN junction and its space charge region.* opposite directions, the space charge region is narrowed, and the diffusion effect of the majority carriers is greatly enhanced at this time, forming a larger forward current (*I*F), the PN junction is turned on, which is shown in **Figure 2**.

On the contrary, when the PN junction (or diode) is reverse biased, since the external electric field (*E*V) and the built-in electric field (*E*) are in the same direction, the space charge region becomes wider, which greatly hinders the diffusion of majority carriers. And the PN junction is in the off state, and only a negligible reverse leakage current (*I*R) flows through the diode, as shown in **Figure 3**. **Figure 3** also shows the electric field distribution of the reverse-biased diode. When the applied reverse bias voltage (*V*) increases, the peak electric field (*E*max) also increases accordingly. When the *E*max is up to the critical breakdown electric field (*E*C) of the semiconductor, the diode breaks down, the applied voltage is the breakdown voltage (*U*BR), which is also equal to the area of the electric field distribution triangle. When the diode breaks down, the reverse current of the diode will increase sharply.

The I-V characteristic curve of the PN junction diode is shown in **Figure 4**. When the forward voltage drop (*V*AK) is higher than the turn-on (or knee) voltage drop (*V*ON) the diode is turned ON, and the current (*I*AK) is approximately exponential with respect to the voltage (*V*AK). When the diode is reverse biased, its reverse leakage current (*I*R) is very small and can be negligible, but when the reverse bias voltage crosses to *U*BR, the current increases sharply, so the *U*BR is the breakdown voltage of the diode. When designing a power converter, it is necessary to be reasonable in choosing the *U*BR and forward current capability of the diode. The I-V characteristic of the PN diode can be described as Eq. (1).

$$I\_{\mathbf{AK}} = I\_{\mathbf{S}} \cdot \left[ \mathbf{e}^{\left(q\mathbf{V}\_{\mathbf{AK}}/k\mathbf{T}\right)} - \mathbf{1} \right] \tag{1}$$

Where *I*<sup>S</sup> is the reverse state saturation current (leakage current) *I*R,*T* is the thermodynamic temperature, *k* is the Boltzmann constant, and *V*AK is the applied bias

**Figure 2.** *PN junction or diode in the forward bias conduction state.*

**Figure 3.** *PN junction diode in the reverse bias state.*

**Figure 4.** *The I-V characteristics of the PN junction diode.*

voltage between the anode and the cathode. At room temperature, the *kT*/*q* is about 26 mV.

Due to the charge storage effect in the diode, the switching of the diode from the ON state to the OFF state requires a transient process. **Figure 5** shows the reverse recovery transient of the diode. When the power supply voltage of the diode circuit changes from the forward state to the reverse state of the diode, the current of the diode decreases from the forward on-state current (*I*F) to the reverse saturation current *I*R, it does not maintain at *I*<sup>R</sup> immediately, but increases reversely to *I*RM, which is because although the voltage of the external circuit has been reversed, the inside of the diode is still full of carriers, and these carriers need a process to be extracted from the body of the diode. This period of time is called the reverse recovery time (*t*rr) of the diode, and the charge extracted during the *t*rr time is called the reverse *New Electronic Devices for Power Converters DOI: http://dx.doi.org/10.5772/intechopen.108467*

**Figure 5.** *The reverse recovery characteristics of the PN junction diode.*

recovery charge (*Q*rr). Generally speaking, the *t*rr and *Q*rr of PN junction diodes with the same rated voltage and rated current are larger than those of Schottky diodes.

#### **2.2 SiC power diodes**

The energy bandgap of 4H-silicon carbide (4H-SiC) is about 3 times that of Si (Silicon), the thermal conductivity is also 3 times that of Si, the critical breakdown electric field is about 8 to 10 times that of Si, and the saturation drift velocity of electrons is 2 times that of Si. These superior properties of SiC make it the preferred material for high-frequency, high-power, high-temperature, and radiation-resistant semiconductor devices.

**Figure 6** shows the specific on-resistance (*R*on,sp) of N-type drift region in 4H-SiC and Silicon at different breakdown voltages. And the *R*on,sp of the 4H-SiC drift region is about 2000 times smaller than that of the silicon devices for the same breakdown voltage [1].

Since the turn-on voltage (or knee voltage) of the SiC PN junction is as high as about 2.8 V, which is much higher than that of the SiC Schottky diode with a value of

**Figure 6.**

*Specific on-resistance of n-type drift region in 4H-SiC and silicon at at different breakdown voltages.*

lower than 1 V. So, the commercial SiC diodes with a breakdown voltage of less than 4500 V are almost Schottky diodes. For the SiC Schottky diodes, the much lower drift region resistance and much higher energy bandgap compared with silicon can boost the breakdown voltage to over 3000 V with reasonable on-state voltage drop (VF) and relatively low leakage current [1]. Although silicon-based Schottky diodes are also commonly used in power systems and power converters, they operate at low voltages (typically ≤200 V). They offer very low on-state voltage drops and losses despite high leakage current and low maximum operating temperature.

The SiC power diode structures are mainly Schottky barrier diodes (SBD) and junction barrier Schottky diodes (JBS), which are shown in **Figure 7a,b**, respectively. The main feature of the SiC SBD is the Schottky contact formed at the interface between the metal and 4H-SiC. While the SiC JBS introduces P-type regions at a certain distance in the SBD to shield the electric field at the Schottky contact interface and reduce the reverse leakage current. The energy band diagram for the metal– semiconductor (4H-SiC) contact is shown in **Figure 7c**.

In the typical normal operating state of the above two devices, the on-state current is dominated by majority carriers—electrons, and the storage effect of the minority carriers in the drift region is almost negligible. This causes the transition from the onstate to the reverse blocking state of the SiC SBD and JBS diode very fast with a much shorter reverse recovery time (*t*rr) and a much lower reverse recovery charge (*Q*rr) compared with those of the silicon PN diode. The high switching speed and the high current density compared with the silicon PN diodes make them suitable for high frequency, high power, and high-end applications.

For SiC Schottky power diodes, due to the low doping concentration in the N-type drift (N-drift) region to support high reverse blocking voltages, the current via thermionic emission current transport mechanism is dominant in Schottky barrier diodes. So the thermionic emission theory can be used to describe the current density *J*AK flows across the Schottky barrier interface [2], which is shown in Eq. (2):

$$J\_{\rm AK} = \mathbf{A}^{\ast} \mathbf{T}^2 \mathbf{e}^{-(q\Phi\_{\rm BN}/\mathbf{kT})} \left[ \mathbf{e}^{\left(qV\_{\rm AK}/\mathbf{kT}\right)} - \mathbf{1} \right] \tag{2}$$

where *A\** is the effective Richardson constant, *Φ*BN is the barrier height of the metal–semiconductor contact (shown in **Figure 7c**),*T* is the thermodynamic temperature, *k* is the Boltzmann constant, and *V*AK is the applied bias voltage between the

#### **Figure 7.**

*(a) SiC Schottky barrier diodes (SBD), (b) SiC junction barrier Schottky diodes (JBS) and (c) the band diagram for metal–semiconductor contact.*

anode and the cathode. Among them, the Richardson constant of N-type silicon carbide material is 146 A�cm�<sup>2</sup> �*K*�<sup>2</sup> .

The turn-on voltage drop (*V*ON) of the Schottky diode is mainly determined by the barrier height (*Φ*BNÞ. And the *Φ*BN mainly depends on the workfunction of metal materials, thus the on-state voltage drops of SiC Schottky diode can be selected by choosing different metal materials.

Based on the operation mechanism of SiC Schottky diode, the static I-V characteristic curves of SiC SBD and JBS diodes are shown in **Figure 8**. As can be seen from the figure, the SiC SBD exhibits a higher forward current density, but it also shows a larger leakage current and a lower breakdown voltage (*U*BR). Although the SiC JBS diode has a lower current density, the leakage current in the blocking state is much lower and the *U*BR is also higher than those of the SBD. This is because the P-type regions introduced in the JBS structure reduce the Schottky contact area, resulting in a certain reduction in current density, but the introduction of the P-type regions shields the electric field at the Schottky contact interface, thereby effectively reduces the reverse leakage current and improves the breakdown voltage. However, in SiC materials, the ion implantation depth of the P-type regions is relatively shallow (usually <1 μm), thus the electric field shielding effect is limited. Then, the trench JBS (T-JBS) diode has been proposed to achieve a low reverse leakage current [3, 4]. Unfortunately, the T-JBS structure introduces a severe JFET (junction field-effect transistor) effect, which greatly reduces the on-state current density. And the sidewall-enhanced JBS (SET-JBS) diode was proposed to alleviate the JFET effect and increase the Schottky contact area, resulting in an improvement in current density [5]. **Figure 9a,b** shows the device structures of the T-JBS diode and the SET-JBS diode, respectively. And the static I-V characteristic comparison result is also shown in **Figure 9c**.

#### **2.3 Ga2O3 power diodes**

Gallium oxide (Ga2O3) is a representative material of the ultra-wide bandgap semiconductor material and has attracted extensive research interest in recent years. There are five isomers of Ga2O3, and the beta-Ga2O3 (β-Ga2O3) is mostly used material for power devices. Due to its ultra-wideband gap (over 4 times of Si), high theoretical breakdown electric field (8MV/cm), large Baliga figure of merit (3400), and stable chemical properties, it has become an ideal choice for high-voltage and

**Figure 8.** *The static characteristic curves of SiC SBD and JBS diodes.*

#### **Figure 9.**

*(a) SiC trench JBS (T-JBS) diode, (b) SiC sidewall enhanced JBS diode (SET-JBS), and (c) static characteristic comparison of different Schottky diodes [5].*

high-power rectifiers and field-effect transistors [6, 7]. Nowadays, with the improvement of crystal growth technology, large-scale Ga2O3 single crystals have been produced, such as pulling method, guided mode method, and floating zone melting method [8]. There is also a method of heteroepitaxial growth of gallium oxide thin films on substrates such as quartz glass, sapphire, silicon, and gallium arsenide [9–11].

**Figure 10a** shows the cross-sectional structure view of the Ga2O3 Schottky barrier diode (SBD). As shown in the figure, the top metal layer (Pt/Ti/Au) is in contact with the Ga2O3 N-type drift region to form a Schottky contact. And the bottom metal (Ti/ Au) is in contact with a heavily doped N+ Ga2O3 substrate to form an ohmic contact. The operating mechanism of Ga2O3 SBD is similar to that of SiC SBD. However, compared with SiC materials, the effective P-type doping has not yet been achieved in Ga2O3 materials. Due to the lack of P-type doping in the Ga2O3 materials, **Figure 10b** shows a structure of a Ga2O3 heterojunction (HJ) PN diode [12]. The current density of the Ga2O3 heterojunction PN diode is higher than that of the Ga2O3 SBD due to the hole injection and conductance modulation effect in the N-type drift region. However, because the barrier height of the heterojunction PN junction is higher than that of Schottky contact, the turn-on voltage drop of the HJ PN diode is higher than that of the SBD, but the Ga2O3 heterojunction PN diode has great advantages in the field of ultra-high voltage (e.g., > 6500 V) applications with a lower voltage drop at the same current density compared with Ga2O3 SBD. At present, the Ga2O3 power heterojunction diode with a breakdown voltage exceeding 8000 V has been developed [12].

#### **Figure 10.**

*Device structures of (a) Ga2O3 SBD, (b) Ga2O3 heterojunction PN diode [9].*

*New Electronic Devices for Power Converters DOI: http://dx.doi.org/10.5772/intechopen.108467*

**Figure 11** shows the forward I-V characteristic curves of the Ga2O3 SBD and the Ga2O3 HJ PN diode. And it can be seen from the figure that the turn-on voltage drop of the Ga2O3 SBD (*V*ON1) is lower than that of the Ga2O3 HJ PN diode (*V*ON2), but the current *I*AK of the Ga2O3 HJ PN diode rises faster with the voltage *V*AK, which is mainly caused by the conductance modulation effect in the Ga2O3 HJ PN diode.

#### **2.4 Dynamic characteristic comparison of the diodes**

**Figure 12** presents an intuitive rough comparison result of the reverse recovery characteristics of Si, SiC, and Ga2O3 diodes at the same rated breakdown voltage and rated current. It can be seen from the figure that the Si PN junction diode has the largest reverse recovery current, the longest reverse recovery time, and the largest

**Figure 11.** *The Ga2O3 SBD and Ga2O3 HJ PN diode forward I-V characteristics.*

**Figure 12.**

*Comparison of reverse recovery characteristics of Si, SiC, and Ga2O3 diodes at the same rated breakdown voltage and rated current.*

reverse recovery charge. And the Ga2O3 SBD has the best reverse recovery performance. The reverse recovery performance of the SiC Schottky diodes is between that of Si and Ga2O3 diodes.

#### **3. Power MOSFET and JFET**

#### **3.1 Device structure and operating mechanism**

The power MOSFET (metal-oxide-semiconductor field-effect transistor) has many advantages: (a) it is a voltage-controlled device with high input impedance and low driving power consumption, (b) it is no secondary breakdown with wide safe operating area (SOA), and due to good thermal stability, the operating temperature can reach up to 200°C, which is 50°C higher than that of the bipolar transistor (BJT), (c) it is a majority carrier conduction device with the strong anti-irradiation ability and (d) it is no minority-carrier storage effect, and the switching frequency is high. Because the power MOSFET has those advantages mentioned above, it has always been a research hotspot in the industry and widely used in the power converters.

**Figure 13a,b** shows the device structure of the N-channel vertical power MOSFET and its electric field distribution in the blocking state, respectively. When the gate (G) to source (S) voltage (*V*GS) is higher than the threshold voltage (*V*TH) of the Nchannel MOSFET and the drain-to-source voltage (*V*DS) is positive, the MOSFET is turned ON, and the electrons flow from the source n + region through the channel and n-drift region to the n + drain region to form the drain current *I*DS. Conversely, if VGS < VTH and VDS is a positive high voltage, the channel is off and the MOSFET is in a forward blocking state (voltage sustaining state). At this time, the electric field distribution inside the device is roughly as shown in **Figure 13b**, and the voltage is mainly sustained by the n-drift region. **Figure 13c,d** demonstrates the symbols of the N-channel power MOSFET and P-channel power MOSFET, respectively.

#### *3.1.1 Static characteristic*

**Figure 14a,b** shows the transfer characteristic and the output characteristic of the N-channel power MOSFET, respectively. And when VGS > VTH, the MOSFET is

#### **Figure 13.**

*(a) Device structure of the N-channel power MOSFET, (b) the electric field distribution of the power MOSFET in the blocking state; the symbols of the (c) N-channel power MOSFET and (d) P-channel power MOSFET.*

**Figure 14.** *(a) The transfer characteristic curve and (b) output characteristic curve of the power MOSFET.*

turned ON, and the drain current *I*DS increases as the *V*GS increases. From the output characteristic curve, when the device is in the cut-off region, *I*DS is almost negligible; when the device is in the triode region, the current *I*DS increases sharply with *V*DS. While in the saturation region, *I*DS hardly increases with *V*DS. And when the device is in the breakdown region, the current *I*DS increases sharply, causing a dramatic increment in power consumption, which may cause a thermal runaway of the device. Therefore, the device should be avoided as much as possible to operate in the breakdown region.

#### *3.1.2 Dynamic characteristic*

**Figure 15a,b** shows the power MOSFET switching test circuit with an inductive load L and the typical characteristics of power MOSFET switching transients [13]. As the power MOSFET is a majority carrier device, there is no minority carrier storage effect, so the switching speed is fast, typically 20–50 ns. As shown in **Figure 15b**, the turning-on time of the device is *t*sw(on) (*t*sw(on) = *t*d1 + *t*on), and the turn-off time is *t*sw(off) (*t*sw(off) = *t*d2 + *t*off). Typically, most devices have a longer turn-off time than their turn-on time.

#### **Figure 15.**

*(a) MOSFET switching test circuit with inductive load, (b) typical characteristics of power MOSFET switching transients [13].*

#### **3.2 Superjunction power MOSFET**

The conventional power MOSFET devices have an inherent contradiction that the specific on-resistance (*R*on,sp) is proportional to the 2.5th power of the breakdown voltage (BV), that is *R*on,sp∝ BV2.5, which is dreaded as "silicon limit" theory. This means that even with a small increase in BV, *R*on,sp will increase substantially, thereby greatly increasing the conduction loss of the device.

In 1993, Chen invented the superjunction device, which greatly improved the contradiction between *R*on,sp and BV with a much better relationship as *R*on,sp∝ BV1.32 [14, 15]. And the superjunction MOSFET was commercialized in 1998 and hailed as a "milestone" in the field of power electronic devices [16].

**Figure 16a,b** illustrate the device structure of superjunction MOSFET and its approximate electric field distribution in the drift region. Due to the introduction of the charge compensation effect of the P-type pillars in the drift region, the doping concentration of the n-drift can be greatly increased, thereby greatly reducing the *R*on,sp. of the device. At the same time, the charge compensation effect makes the total net charge of the properly designed superjunction drift region to be zero in the blocking state, so that the electric field distribution is approximately rectangular. Therefore, at the same rated voltage, the drift region thickness of superjunction MOSFETs is thinner than that of conventional power MOSFETs with a triangular electric field distribution. The much higher n-drift doping concentration and thinner n-drift region thickness greatly reduce the *R*on,sp. of the device, enabling superjunction devices to break the "silicon limit" of conventional MOSFETs.

**Figure 17** shows the *R*on,sp. comparison result between the silicon conventional power MOSFET and superjunction MOSFET at different breakdown voltages [17]. As can be seen from the figure, the relationship between the *R*on,sp. and BV of the superjunction MOSFET is approximately linear. The comparison results show that the superjunction devices can be used for higher power density and higher-end applications.

**Figure 16.**

*(a) Structure of superjunction MOSFET and (b) the approximate electric field distribution in the drift region.*

**Figure 17.**

*Ron,sp comparison between the silicon conventional MOSFET and Superjunction MOSFET at different breakdown voltages [17].*

#### **3.3 SiC power MOSFET**

**Figure 18** presents the structural comparison of Si and SiC vertical power MOSFETs at the same rated breakdown voltage. It can be seen from the figure that under the same rated breakdown voltage, the thickness of the n-drift region of the SiC MOSFET is about 1/10 of that of the silicon MOSFET, so the drift region resistance is dramatically reduced and the current density of the SiC power MOSFET is greatly improved, the conduction loss is greatly reduced, the switching speed is also improved, and the chip size is greatly reduced. At the same time, due to the larger energy band gap and higher thermal conductivity of SiC materials, the SiC MOSFETs can be operated at temperatures over 200°C. However, compared with silicon

MOSFETs, the channel mobility of SiC MOSFETs is still very low, and its on-state resistance still has a large room for improvement. At the same time, the electric field of the gate oxide layer may be very high, which brings challenges to the reliability of the gate oxide layer.

Since the current capability of SiC devices is much larger than that of silicon devices, SiC lateral devices can also be used in power-integrated circuits to handle larger power conversions. And the SiC lateral device can easily achieve over 1200 V breakdown voltage while still obtaining a low on-resistance [18, 19]. **Figure 19** shows the cross-sectional view of a SiC lateral power MOSFET device [20]. Compared with the SiC vertical MOSFET, all electrodes of the SiC lateral power MOSFET are on the surface of the device, so that the SiC lateral MOSFET can be integrated with SiC lowvoltage integrated circuits on the same chip to realize monolithic SiC power integrated circuits. The operating principle of the SiC lateral power MOSFET is almost the same as the vertical power MOSFET. The only difference between the two kinds of devices is that the current of the lateral power MOSFET flows laterally, and the electron flow path is shown by the red dotted line in the figure. It is worth mentioning that the purpose of introducing the p-top region into the lateral power MOSFET of this device is to increase the doping concentration of n-drift through the principle of charge compensation, and greatly reduce the on-resistance while optimizing the surface electric field. So the device has the advantages of high breakdown voltage and low onresistance.

#### **3.4 SiC JFET**

Due to the extremely low channel mobility of SiC MOSFETs and the reliability issues of the SiO2 gate oxide layer, SiC JFET (junction field-effect transistor) devices were once favored by researchers and the industry, and have also been commercialized [21, 22]. **Figure 20a,b** show the structure and the symbol of the SiC power JFET device, respectively. Different from the MOSFET, the SiC JFET controls the turn-off of the device by applying a negative voltage through the p<sup>+</sup> gate with respect to the source to completely deplete the N-type channel region. Generally, the SiC JFET is a normally on device, and when the gate-to-source is zero biased (*V*GS = 0 V), the channel is not fully depleted, the device is in the on-state, and electrons flow from the n<sup>+</sup> source through the channel region to the n+ drain. Since the channel mobility of SiC JFETs is much greater than that of SiC MOSFETs, the SiC JFETs have lower onresistances. However, the gate control voltages of the two devices are different. The

**Figure 19.** *Cross-sectional view of a SiC lateral power MOSFET device [18].*

*New Electronic Devices for Power Converters DOI: http://dx.doi.org/10.5772/intechopen.108467*

**Figure 20.**

*(a) The cross-sectional view and (b) symbol of the SiC power JFET; (c) SiC JFET/Si MOSFET cascode configuration; (d) SiC SBD-JFET.*

*V*GS of the JFET cannot be higher than the turn-on voltage drop of the gate-source PN junction ( 2.8 V), while the *V*GS of the MOSFET can be as high as 20 V.

In order to take the performance advantages of SiC JFETs and make SiC JFETs as easy to control as MOSFETs at the same time, a cascode configuration consisting of a low-voltage high-current Si MOSFET and a high-voltage SiC JFET has emerged on the market and gained lots of applications, which is shown in **Figure 20c** [23]. In addition, in order to realize the self-reverse recovery of the SiC JFET device and improve its performance, a new SiC SBD-JFET has been proposed in **Figure 20d** [24].

#### **3.5 Ga2O3 power MOSFET**

**Figure 21a** shows the structure of the depletion-mode Ga2O3 MOSFET, which has a negative threshold voltage *V*TH [25]. The two heavily Si-doped N+ regions are connected with metals to form low-resistance ohmic contacts, respectively. The source-connected field plate above the gate can effectively reduce the surface electric field and improve the breakdown voltage of the device in the blocking state. And due to the existence of the Fe-doped semi-insulated β-Ga2O3 substrate, the leakage current through the substrate is obviously reduced. During forward conduction, the gate-to-source voltage *V*GS

**Figure 21.**

*(a) Depletion-mode Ga2O3 lateral MOSFET [25], (b) enhancement-mode Ga2O3 vertical transistor [26].*

**Figure 22.**

*(a) Transfer characteristic curve of the depletion-mode and enhancement-mode Ga2O3 MOSFETs (b) I-V output characteristic curve of Ga2O3 MOSFETs.*

is higher than *V*TH, the channel region under the gate is not fully depleted, and a positive drain voltage relative to the source *V*DS is applied, the electrons flow from the N+ source to the drain along the channel region and the N-type β-Ga2O3 drift region to form the on-state drain current *I*DS. When the gate-to-source voltage *V*GS < *V*TH, the channel region is fully depleted, and the device is changed to the blocking state with no electron flowing from the source to drain. And the maximum blocking voltage (breakdown voltage) is mainly determined by the distance from the gate to the drain, the doping concentration of N-type β-Ga2O3, and the parameters of the field plate. **Figure 21b** shows a vertical enhancement-mode Ga2O3 MOSFET with a breakdown voltage over 1 kV [26].

The transfer characteristic curve of the Ga2O3 MOSFET is shown in **Figure 22a**. It can be seen from the figure that the *V*TH of the depletion-mode device is negative, and the *V*TH of the enhancement-mode device is positive. Since there is no effective P-type doping in Ga2O3, therefore, the common devices are almost in depletion mode. The main way of realizing enhancement-mode Ga2O3 MOSFET is to make the channel region to be very thin (such as the recessed gate structure [27]) or to be very narrow (as shown in **Figure 21b**), so that when the *V*GS is zero biased, the channel region can also be completely depleted. Although the realization of enhancement-mode devices increases the complexity of the fabrication process, the enhancement-mode devices are easier to be controlled from the application point of view. **Figure 22b** plots the output I-V curves of the Ga2O3 MOSFET and both the depletion-mode and enhancement-mode Ga2O3 MOSFETs have similar I-V curves. Also, it can be seen that the transfer characteristics and I-V characteristics of the Ga2O3 MOSFET are similar to those of the Si and SiC power MOSFETs described above, but due to the different material parameters, the current capability of the Ga2O3 MOSFET device is higher. In addition, the switching characteristics of Ga2O3 MOSFETs are similar to those of Si and SiC MOSFETs.

#### **4. Insulated gate bipolar transistor (IGBT)**

Insulated gate bipolar transistor (IGBT) is a composite fully controlled voltagedriven power electronic device composed of BJT (bipolar junction transistor) and MOSFET, which has both the high input impedance and the low on-state voltage drop.

#### *New Electronic Devices for Power Converters DOI: http://dx.doi.org/10.5772/intechopen.108467*

It was once hailed as an almost ideal switching device in the field of power electronics, except for its higher turn-off loss and longer turn-off time compared with those of the power MOSFETs.

**Figure 23a,b** demonstrate cross-section view of the IGBT and the equivalent circuit of internal structure, respectively [28]. From the perspective of device structure, the n<sup>+</sup> region connected to the emitter (E) electrode, p-base, gate, and n-drift region constitute an N-channel MOSFET (N-MOSFET). At the same time, the p<sup>+</sup> /pbase, n-drift/n-buffer regions, and the p<sup>+</sup> collector (C) constitute a PNP BJT. Therefore, from the perspective of the internal device structure, the IGBT can be regarded as a combination of an N-MOSFET and a PNP BJT. Thus, the IGBT has the advantages of the high input resistance of N-MOSFET and the large current density of BJT. It is worth noting that many researchers also call the electrode collector (C) on the back of the device as anode (A), and the electrode emitter (E) on the surface as cathode (K). **Figure 23c** also shows the symbol of the IGBT.

In the blocking state, the gate voltage with respect to the emitter (*V*GE) is zero biased or negatively biased. At this time, the N-MOSFET controlled by the gate is in the off-state, and the IGBT is also in the off-state. And the applied positive voltage between the collector electrode and the emitter electrode (*V*CE) is sustained by the Pbase/N-drift junction. Since the doping concentration of the p-base region is much higher than that of the n-drift region, so the breakdown voltage of the IGBT is mainly determined by the thickness and doping concentration of the n-drift region.

In the on-state, *V*GE is applied to a positive voltage (usually +15 V). And an inversion layer electron channel connecting the n<sup>+</sup> region and the n-drift region is formed on the surface of the p-base region under the gate. The electrons flow from the n<sup>+</sup> region through the channel into the n-drift region and finally into the p+ collector region. The electron current acts as the base drive current of the PNP transistor, which facilitates the injection of holes from the p <sup>+</sup> collector region into the n-buffer and ndrift regions, and finally into the emitter electrode.

**Figure 24a,b** illustrate the transfer characteristic and output characteristic curves of the IGBT, respectively. As can be seen from the figure, the transfer characteristic curve of the IGBT is similar to that of power MOSFET. However, the forward output characteristic of the IGBTs is slightly different from that of MOSFETs. The main

**Figure 23.**

*(a) Cross-section view of the IGBT, (b) equivalent circuit of internal structure, (c) the symbol of the IGBT.*

#### **Figure 24.**

difference is that, in addition to *V*GE > *V*TH, the forward conduction of IGBTs requires *V*CE to be higher than the turn-on voltage *V*PN of the p<sup>+</sup> /n-buffer PN junction. After the turning-on of the device, a large number of holes are injected into the n-drift region from the p<sup>+</sup> collector, resulting in a conductance modulation effect, which greatly increases the current density and reduces the on-state voltage drop (*V*ON) of the device. **Figure 24b** also reveals the reverse breakdown characteristic of the IGBT, the reverse breakdown voltage is mainly determined by the breakdown voltage of the p+ /n-buffer junction, usually because the doping concentration of the n-buffer region is much higher than the n-drift region, the reverse breakdown voltage of the IGBT is very low. However, for an IGBT without an n-buffer region, the reverse breakdown voltage may also be close to the forward breakdown voltage.

The turning-on characteristic of the IGBT is similar to that of the power MOSFET, but its turning-off characteristic is different from that of the power MOSFET. **Figure 25** shows the typical switching-off characteristic of the IGBT [29]. Compared with the switching-off transient of the power MOSFET, the turning-off transient of the IGBT is much longer and a long tail current is appeared in the turning-off process [30]. The reason is that after the channel of the IGBT is turned off, a large number of nonequilibrium electrons in the drift region flow out to the p<sup>+</sup> collector region under the action of the electric field. During this transient, the bottom p<sup>+</sup> /n-buffer PN junction is still in the forward biased state, and holes are continuously injected into the

**Figure 25.** *Typical switching off characteristic of the IGBT [29].*

*New Electronic Devices for Power Converters DOI: http://dx.doi.org/10.5772/intechopen.108467*

n-drift region until almost all the electrons are extracted from the n-drift region. Thus, the holes injection during the turn-off process is the main reason for the current tailing. Although there are some design optimizations and structural improvements to increase the turn-off speed of IGBTs, most of them come at the expense of forward voltage drop (*V*ON) [31]. And the improvements in the trade-off relationship between the turn-on voltage drop and turn-off loss of the IGBT are still being pursued [32]. Nevertheless, the switching speed of IGBT is far inferior to that of MOSFET, which limits the high-frequency application of the IGBT.

#### **5. GaN high electron mobility transistor (HEMT)**

In 1992, the first Gallium nitride high electron mobility transistor (GaN HEMT) was developed by using metal organic chemical vapor deposition (MOCVD) [33]. Subsequently, GaN devices have attracted great attention and research. The GaN HEMT has the advantages of high current density, high breakdown voltage, high operating frequency, high reliability, and low switching loss. GaN HEMTs have great potential for application in high frequency, high efficiency, and high power density power electronic systems. Currently, the GaN HEMTs are commercialized with rated voltage up to 650 V and are widely used in power converters, power adapters, on-board charging, data centers, and other applications [34].

For nitride semiconductors, the thermodynamic stable phase is a hexagonal symmetric wurtzite structure, while the thermodynamic metastable phase is a cubic symmetric sphalerite structure [35]. The wurtzite GaN crystal structure does not show symmetry along the C-axis, besides the sum of the vector *P* of the polarization intensity of Ga-N covalent bond is not zero. There should be a deviation between positive and negative ions, so a strong spontaneous polarization effect generates inside the GaN. As for AlGaN/GaN heterojunctions, the lattice constants of the two materials do not match, leading to the existence of stress forces between atoms near the contact surface of the two materials. Under the action of this stress force, the lattice asymmetry is enhanced, meanwhile the lattice deformation deviates the center of positive and negative charges in the lattice, resulting in a strong piezoelectric polarization effect.

**Figure 26a,b** show the energy band diagram and the structure of the enhancement-mode GaN HEMT, respectively [36, 37]. The heterojunction energy is discontinuous due to the strong total polarized induced electric field generated by the

addition of piezoelectric polarization and spontaneous polarization in the heterostructure, as well as the conduction band shift Δ*E*<sup>c</sup> at the heterojunction interface. The energy band bends in the GaN layer to form a triangular electron potential well, which captures electrons ionized by donor impurities and then forms a large number of two-dimensional electron gas (2DEG). Due to the existence of a high potential barrier on the side of AlGaN, it is hard for electrons to cross the potential well, therefore, electrons are restricted to move laterally in the thin layer of the interface, instead of moving perpendicular to the interface. Different from the channel electrons in traditional MOSFET, 2DEG accumulates on one side of the intrinsic potential well layer, realizing the separation of carriers and the Coulomb scattering center. There is almost no electron impurity scattering in the potential well, which indicates that the 2DEG has a very high electron mobility. At the same time, the concentration of 2DEG obtained under the unintentional doping of GaN is quite considerable, thereby the GaN HEMT devices have high current density and unique application value.

#### 1.Static characteristic

**Figure 27a,b** show the transfer characteristics and output characteristics of the enhancement-mode GaN HEMT, respectively. The threshold voltage (*V*TH) of the GaN HEMT is the gate-to-source voltage (*V*GS) corresponding to the device from off state to on state, that is, the *V*TH is the voltage applied to the gate when the AlGaN and GaN interface forms the 2DEG. Currently, the threshold voltage (*V*TH) of the typical commercial AlGaN/GaN HEMT is positive—enhancement mode HEMT.

It is found that the 2DEG characteristics are very similar to the channel electrons of MOSFET, so the output characteristics of the enhanced GaN HEMT are very close to the characteristics of n-channel MOSFET. By varying the applied drainsource voltage when the device is turned on, GaN HEMT can be operated in the linear (unsaturated) and saturation regions. However, in the GaN HEMT, when *V*DS is high, the drain current *I*DS decreases with the increase of *V*DS, and the current collapse effect occurs. The main reason is that under the large *V*DS, a high electric field is generated between the gate and drain, and the channel hot electrons are excited to tunnel to the surface of AlGaN, and are trapped by the

**Figure 28.**

*Switching characteristics of the enhancement-mode GaN HEMT: (a) turn-on, (b) turn-off (redrawn from figure 1 in ref. [39]).*

surface states between the gate and drain, forming a virtual gate and a current collapse phenomenon [38].

2.Dynamic characteristics

High concentration of 2DEG with high mobility exists in the channel layer of the GaN HEMT, which on the one hand enables the device to form a maximum forward current, and on the other hand enables it to operate at high frequency and high power. Compared with traditional Si-based and SiC MOSFETs, the GaN HEMT has a faster switching time and smaller switching loss. **Figure 28** shows the typical switching waveforms of an enhancement-mode GaN HEMT in a double-pulse test circuit [39]. As can be seen from the figure, the turn-on and turn-off times of the GaN HEMT are very short, both around 10 ns. However, it is worth noting that different GaN HEMT devices and applications in different circuits have slightly different switching times.

#### **6. Prospects for new electronic devices**

For power electronic devices, we always pursue higher breakdown voltage, lower loss, higher reliability and thermal stability, and low cost. In recent years, with the increasing demand for electronic devices in power electronic systems and power converters, new electronic devices represented by SiC devices and GaN devices have also achieved rapid development. However, there is still much room for improvement in the performance of these devices, and these new devices will continue to achieve breakthroughs in performance and cost reductions in the future. At the same time, besides the Ga2O3 devices, new electronic devices based on ultra-wide bandgap materials (such as diamond, BN, and AlN) will also emerge one after another and will be gradually applied in the market for high voltage, high-power, and high-end

#### **Figure 29.**

*Relationship between specific on-resistance and breakdown voltage of power electronic devices based on various materials [40].*

applications. **Figure 29** shows the relationship between specific on-resistance and breakdown voltage of power electronic devices based on various materials [40], which also shows the development trend of power device materials from another perspective.

#### **7. Conclusions**

The emergence and development of new power electronic devices are critical to the development of power converters and power electronic systems. Understanding how electronic devices work is important for better design of power converters. This chapter describes in detail the power electronic devices commonly used in power converters. Starting from the structure and working principle of PN junction, this chapter describes the structure and main properties of SiC and Ga2O3 power diodes. And the structure and characteristics of power MOSFET, superjunction MOSFET, SiC MOSFET, SiC JFET, and Ga2O3 MOSFET are described. Then, the structure, principle, and characteristics of IGBT, an extremely important bipolar device in modern power electronic systems, are described. Finally, the structure, working principle and related characteristics of the emerging GaN HEMT devices are also described in detail. And looking ahead, new power electronic devices, such as diamond diodes and diamond MOSFETs, will continue to appear and develop to meet the more stringent requirements of power converters for lower loss, higher breakdown voltage, higher power density, higher switching frequency, and reliability.

*New Electronic Devices for Power Converters DOI: http://dx.doi.org/10.5772/intechopen.108467*

### **Author details**

Moufu Kong State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu, China

\*Address all correspondence to: kmf@uestc.edu.cn

© 2023 The Author(s). Licensee IntechOpen. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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#### **Chapter 3**

## Automatic Current Sharing Mechanism in Two-Phase Series Capacitor Buck DC-DC Converter (2-pscB)

*Salahaldein A. Rmila*

#### **Abstract**

In this chapter, we introduce the concept of the Inherited Automatic Current Sharing Mechanism (ACSM) in a two-phase series capacitor buck topology (2-pscB). This topology was introduced to power laptops as low-voltage and high-current Voltage Regulator Modules as well as non-isolated Point-of-Load converters (Vin < 12 V). To satisfy the converter stability, a state-space modeling technique of switching intervals coupled with parasitic component linearization is developed. Due to the series capacitor charging period miscalculation, the applicability of the ACSM of 2 pscB switching topology for high-power electronic applications is still very limited. Inserting a series capacitor between power switches of phase A increases loop parasitic inductance, introduces a time delay mismatch between the gate voltages of the two switches, and causes interference with the synchronization of the dead time between both phases of 2-pscB converters since the phase B has no series capacitor. This mismatch reduces the heat distribution efficiency and lifetime. As such, a complete model study delivered by the converter is required to design a robust controller. Driven to explore the series capacitor voltage feedback mechanism, frequency analysis of transfer functions, and filter behavior with experimental prototype examples (Vin < 120 V) have been presented for the first time to demonstrate the theoretical analysis. Obtained efficiency was up to 94.9% at full load.

**Keywords:** two-phase series-capacitor buck converter, state-space averaging, VRMs applications, current sharing mechanism, inductor currents derivation

#### **1. Introduction**

The current sharing mechanism concept for conventional multi-phase converters, which are designed based on sensing each phase current to deliver the current information to their controllers, is one of main issues of its implementation. In conventional buck converters, this mechanism may require a preset current sharing ratio at the expense of efficiency, which eventually requires a larger sensing circuit to achieve the sensing accuracy of each phase. Introducing the concept of automatic current

sharing in two-phase series capacitor buck topology (2-pscB) is one of the solutions to tackle this issue.

One of the main benefits of a 2-pscB converter is power management to obtain the highest performance of the regulator, automatic power management between phases is used, and the current is evenly distributed between the phases. If the current balance is not fully achieved, input and output ripple cancelation benefits are interrupted, resulting in stability problems. With complete current sharing, better thermal performance and efficiency at higher loads are guaranteed, because all output load is not concentrated in one group of Si MOSFETs/GaNs switches or in a single inductor; otherwise, the unmatched currents may cause a sharp drop in efficiency, instead of two or more phases sharing the thermal burden, the current will pass and cause failure in one phase. The typical topology and time intervals for 2-pscB are shown in **Figure 1**.

There are many advantages attached to this power conversion topology, such as:


**Figure 1.** *Two-phase series capacitor buck converter a) topology and b) time intervals.*

*Automatic Current Sharing Mechanism in Two-Phase Series Capacitor Buck DC-DC… DOI: http://dx.doi.org/10.5772/intechopen.107975*


#### **2. The 2-pscB regulator states equations**

The main objective of this section is to derive the transfer functions governing the operation of the 2-pscB converter. Since this converter is nonlinear and time-varying, it utilizes the switching function of the converter power device to achieve high efficiency. Due to the non-ideal characteristics of the switches and their conduction mode resistance during the switching transition, and because the voltage and current will not suddenly become zero during the switching time, this response brings a certain power loss to the system. In modeling, the load current is assumed to be unknown, as such assumed that this topology consists of non-ideal (transistors, inductor, and capacitor), and they have resistance in conduction conditions. The nonlinear—regulator active switches—circuit elements have other non-ideal effects like a voltage drop of conduction mode of active switches, which is neglected due to the complexity of modeling process. This state-space averaging model could be used to design a robust controller that can satisfy the stability and performance conditions of the converter. Small-signal model linearization of four switching intervals using a state-space average model is required. However, the non-idealistic nature of switches with their conduction mode resistance generates some power losses due to the finite voltage and current during switching transitions. Therefore, a complete model includes all the system parameters has to be generated, such as the turn-on resistance of the diode switch, the parasitic resistances of the inductor and capacitor, and the unidentified load current that can be delivered from the converter. The first step in modeling is to convert a complex circuit into a simplified circuit, in which circuit rules can be established. In a switching regulator, a component that stores energy in a circuit or system (such as capacitor voltage and inductor current) is of great significance. The linear and time-invariant system consists of four regions: the two on-regions of input source and series-capacitor energy storage source and two off-regions. The on-time is denoted by *D1T*, *D3T*, and the off-time is denoted by *D2T,* (1 � *D1-D2-D3) T.*

Thus.

$$\mathbf{d}\_1 \mathbf{T} = \mathbf{D}\_1 \mathbf{T}.$$

$$(d\_2 - d\_1) \ T = D\_2 \mathbf{T}.$$

$$(d\_3 - d\_2) \ T = D\_3 \mathbf{T}.$$

$$(\mathbf{1} - d\_3) \ T = (\mathbf{1} - D\_1 - D\_2 - D\_3) \ \mathbf{T}.\tag{1}$$

In which *T* is the period of the steady-state output voltage. **Figure 1** shows a twophase series capacitor buck switching regulator. The four switches are turned on (off) by a pulse with a period of *T,* and its duty cycle is *d* seconds. Therefore, we can represent the simple equivalent circuit of the system in four on and off modes. To look at the stages of operation of this converter in a steady state during the first mode, the high-side switch of phase A, switch *Q11*, is on, and the inductor current in inductor *L1* charges up the series capacitor a small amount. Using two series capacitors or more *Cs1*, *Cs2*, .., *Csn* in parallel will reduce the parasitic resistance *rCs* to half or less. This topology has a duty cycle as follows.

$$\frac{V\_o}{V\_{in}} = \frac{d\_1(d\_3 - d\_2)}{d\_1 + d\_3 - d\_2} = \frac{D\_1 D\_3}{D\_1 + D\_3} \tag{2}$$

Where *d*1, *d*2, *d*<sup>3</sup> represent intervals for capacitor series buck modes. When these intervals are equal *D*1= *D*<sup>2</sup> = *D*<sup>3</sup> = *D=ton/T.* Hence,

$$\frac{V\_o}{V\_{in}} = \frac{D}{2} = \frac{t\_{on}}{2T} \tag{3}$$

At current sharing balance between the two phases, switching voltage must be the same where,

$$d\_1(V\_{\rm in} - V\_{\rm Cs}) = V\_{\rm Cs}(d\_3 - d\_2) \tag{4}$$

or

$$\frac{V\_{Cs}}{V\_{in}} = \frac{d\_1}{d\_1 + d\_3 - d\_2} = \frac{D\_1}{D\_1 + D\_3} \tag{5}$$

From Eqs. (2, 5) at steady-state condition we conclude that

$$\frac{V\_o}{V\_{os}} = D\_3 \tag{6}$$

Consideration of *iL, vCs,* and *vCo* as our state variables of the continuous-time LTI system consists of a state equation and output equation. As a result, the multiphase controller maximizes the duty cycles of both phases during the transient period to the maximum of 25% of the period while maintaining 25% of the time between each duty cycle. All phase inductors that parallel each other are reduced by several phases where a smaller equivalent inductance can charge the output capacitor faster than bigger ones. This issue also reduces the overshooting when the excess charge stored in the inductor of each phase partially discharges at the phases turn-off state, and then the rest transfers to the output capacitor.

On the other hand, the first drawback of this topology is that it has a 50% duty cycle limit. This limitation means that the high-side switches *Q11* and *Q21* cannot be turned on at the same time, coupled with the fact that conventional buck gives the converter an inherent 2:1 step-down; therefore, the theoretical minimum input voltage rate is four times the output voltage. In other words, the minimum input voltage is going to be almost five times the output voltage when we take losses into account.

$$V\_{in} \ge 4 \ (V\_o + E\_{os}) \tag{7}$$

*Automatic Current Sharing Mechanism in Two-Phase Series Capacitor Buck DC-DC… DOI: http://dx.doi.org/10.5772/intechopen.107975*

#### **3. Small signal average switching model**

In literature, many approaches have been proposed for modeling DC-DC converters, e.g., averaged nonlinear formulation in which switching frequency is dependent. Another approach is large-signal presentations of the variable-structure system [1], where the state-space averaging approach is widely used, which yields an average and linearized model formulation [2] depending on the switching frequency, this model is non-linear and time-varying [3]. The sources of disturbance in power DC-DC systems are many [4, 5]. **Figure 2** shows a functional diagram representing some of these sources, where *vo* and *iL* are dependent on independent inputs.

$$v\_o(t) = f\_1\{v\_{in}(t), i\_{out}, D\_1(t), D\_3(t)\}\tag{8}$$

$$i\_L(t) = f\_2\{v\_{in}(t), i\_{out}, D\_1(t), D\_3(t)\}\tag{9}$$

The equivalent circuit model of the 2-pscB converter can be expressed as seen in **Figure 3**, which contains four independent inputs (input voltage, two control input

**Figure 2.** *Block diagram illustrated the dependence of vo on independent inputs.*

**Figure 3.** *The 2-pscB system ac small signal variations model.*

variation, and load current) and one output dependent variable. Therefore, the ideal transformer averaging model concept can be directly applied to represent the converter.

$$V\_{sw1} = D\_1(V\_{T1} - V\_{T2}) = D\_1(V\_{in} - V\_{Ci}) \tag{10}$$

$$V\_{sv2} = D\_3(V\_{T2} - V\_{T3}) = D\_3 V\_{G} \tag{11}$$

By realizing Eqs. (10) and (11), a large signal average switch model can be formed with transformers and similar average current equations, hence,

$$
\boldsymbol{\upsilon}\_{\mathcal{V}} = \boldsymbol{\upsilon}\_{\text{in}} - \boldsymbol{\upsilon}\_{\text{Cs}} \tag{12}
$$

$$i\_L(t) = i\_{P1}(t) + i\_{P2}(t) \tag{13}$$

$$\frac{\upsilon\_o}{\dot{\upsilon}\_L} = \mathcal{R} // \frac{\mathbf{1}}{\mathbf{S} \mathbf{C}\_o} \tag{14}$$

where *p1*, *p2* are phase current points, at complete current sharing conditions, ideal transformers for both phases will be symmetrical such as

$$D\_1 \hat{i} \ p\_1 = D\_3 \hat{i} \ p\_2 \tag{15}$$

Another way to illustrate 2-pscB converter system ac small signal variations model is seen in **Figure 4**, the output voltage variation can be expressed.

$$v\_o(\mathbf{s}) = G\_{vd}(\mathbf{s})\{D\_1(\mathbf{s}) + D\_3(\mathbf{s})\} + G\_{v-in}(\mathbf{s})v\_{in}(\mathbf{s}) - Z\_{out}(\mathbf{s})i\_{out}(\mathbf{s})\tag{16}$$

Where *Gv*�*in*ð Þ*s* and *Gvd*ð Þ*s* are the line-to-output and control-to-output transfer function expression, respectively. Manipulate block diagram to solve for *vo*ð Þ*s* . Hence

$$v\_o = V\_{ref} \frac{G\_c G\_r G\_{vd} / V\_M}{1 + H G\_c G\_r G\_{vd} / V\_M} + V\_{in} \frac{G\_{v-in}}{1 + H G\_c G\_r G\_{vd} / V\_M} \pm i\_{out} \frac{Z\_{out}}{1 + H G\_c G\_r G\_{vd} / V\_M} \tag{17}$$

which is of the form,

**Figure 4.** *Open loop impedance of 2-pscB converter.*

*Automatic Current Sharing Mechanism in Two-Phase Series Capacitor Buck DC-DC… DOI: http://dx.doi.org/10.5772/intechopen.107975*

$$v\_o = V\_{ref} \frac{1}{H} \frac{T}{\mathbf{1} + T} + V\_{in} \frac{G\_{v-in}}{\mathbf{1} + T} \pm i\_{out} \frac{Z\_{out}}{\mathbf{1} + T} \tag{18}$$

With T sð Þ¼ *H s*ð Þ*Gc*ð Þ*s Gr*ð Þ*s Gvd*ð Þ*s =VM*

*T s*ð Þ is the product of the small-signal gains in the foreword and feedback paths of the control loop, the modulator voltage is *VM,* and *H(s)* is the current sensor gain. *Zout* is converter output impedance formula. To find the output voltage at the equilibrium case and complete current sharing, writing the *KVL* for the simple loops of **Figure 5**, we get:

$$v\_o = i\_L \left( R // \frac{\mathbf{1}}{s\mathbf{C}\_o} \right) = (i\_{L1} + i\_{L2}) \left( R // \frac{\mathbf{1}}{s\mathbf{C}\_o} \right) \tag{19}$$

$$i\_{L1}(2sL) - i\_{L2}(sL) = \frac{1}{2}v\_{in}D\_1 + \frac{1}{2}v\_{in}D\_3 \tag{20}$$

$$i\_{L2}(sL) - i\_{L1}(sL) + i\_{L2}\left(R/ / \frac{1}{sC\_o}\right) = \frac{1}{2}v\_{in}D\_3\tag{21}$$

After calculating the previous equations, we conclude

$$v\_o = \frac{2\,R}{sL(sRC\_o + 1)} \left(\frac{1}{4}v\_{in}(D\_1 + D\_3) - v\_o\right) \tag{22}$$

In other words,

$$\frac{v\_o}{v\_{in}} = \frac{\frac{D\_1 + D\_3}{4}}{s^2 \frac{L\_1 C\_s}{2} + s \frac{L\_1}{2R} + 1} \tag{23}$$

This formula represents converter line-to-output transfer function.

$$G\_{v-in}(\mathbf{s}) = \frac{v\_o(\mathbf{s})}{v\_{in}(\mathbf{s})} \Big|\_{D\_1 = D\_3 = 0, i\_{\text{out}} = 0} = \frac{\frac{D\_1 + D\_3}{4}}{\frac{s^2}{o\rho\_o^2} + \frac{s}{Q\_o a\_o} + \mathbf{1}} \tag{24}$$

At *D*<sup>1</sup> ¼ *D*<sup>3</sup> ¼ *D*

**Figure 5.** *Complete block diagram of two-phase series capacitor voltage regulator.*

*Power Electronics, Radio Frequency and Microwave Engineering*

$$G\_{v-in}(\mathfrak{s}) = \frac{D}{2} = G\_{\mathfrak{g}\circ}$$

And

$$\mathbf{G}\_{\nu-in}(\mathbf{s}) = \mathbf{G}\_{\nu-in}(\mathbf{s})|\_{\text{phase }I} + \mathbf{G}\_{\nu-in}(\mathbf{s})|\_{\text{phase }II}$$

$$= \frac{\upsilon\_o(\mathbf{s})}{\upsilon\_{in}(\mathbf{s})}|\_{D\_1 = 0, i\_{\text{out}} = 0} + \frac{\upsilon\_o(\mathbf{s})}{\upsilon\_{in}(\mathbf{s})}|\_{D\_3 = 0, i\_{\text{out}} = 0} \tag{25}$$

$$\left.G\_{v-in}(s)\right|\_{phase\ I} = \left.G\_{v-in}(s)\right|\_{phase\ II} = \frac{\frac{D\_{1,3}}{4}}{\frac{s^2}{a\_\flat^2} + \frac{s}{Q\_\flat a\_\flat} + \mathbf{1}}\tag{26}$$

Where the angular frequency and quality factor are

$$a\_o = \sqrt{\frac{2}{C\_o L}}, \ Q\_O = R\sqrt{\frac{2}{L}}$$

To generate a Laplacian formula represents converter control-to-output transfer function *GvD*ð Þ*s* ,

$$G\_{vD}(s) = \frac{v\_o(s)}{D(s)}\Big|\_{v\_{\rm in} = 0, i\_{\rm out} = 0} = \frac{\frac{v\_{\rm in}}{2}}{\frac{s^2}{\alpha r\_o^2} + \frac{s}{Q\_o \alpha o\_{\rm s}} + 1} \tag{27}$$

$$\left.G\_{\rm vD}(s) = G\_{\rm vD}(s)\right|\_{\rm phase\ I} + G\_{\rm vD}(s)\Big|\_{\rm phase\ II} = \frac{v\_o(s)}{D\_1(s)}\Big|\_{v\_{\rm in} = 0, j\_{\rm out} = 0} + \frac{v\_o(s)}{D\_3(s)}\Big|\_{v\_{\rm in} = 0, j\_{\rm out} = 0} \tag{28}$$

At complete current sharing

$$\left.G\_{vD}(s)\right|\_{\text{phase }I} = \left.G\_{vD}(s)\right|\_{\text{phase }II} = \frac{\frac{v\_{\text{in}}}{\text{d}}}{\frac{s^2}{a\_\rho^2} + \frac{s}{Q\_\rho a\_\nu} + 1} \tag{29}$$

To derive converter output impedance formula

$$Z\_{out} = \frac{v\_o(s)}{i\_{out}(s)}\Big|\_{v\_{in} = 0, D\_1 = D\_3 = 0}$$

$$= \left(\mathcal{R} // \frac{sL}{2} // / \frac{1}{s\mathcal{C}\_o} \right) = \frac{2\,\text{s}L}{s^2\frac{L}{2}\frac{\mathcal{C}\_o}{2} + s\,\frac{L}{2R} + \mathbf{1}} = \frac{2\,\text{s}L}{\frac{s^2}{a\_s^2} + \frac{s}{Q\_o a\_s} + \mathbf{1}}\tag{30}$$

In some analyses, accurate models are needed; thus, these formulas represent the transfer functions with output filter parasitic components,

$$G\_{v-in}(s) = \frac{v\_o(s)}{v\_{in}(s)}\bigg|\_{D\_1 = D\_3 = 0, i\_{out} = 0}$$

$$= \frac{\frac{D}{2}\left(s\frac{2C\_o r\_{Ca}}{2R + r\_L} + \frac{2R}{2R + r\_L}\right)}{s^2\left(\frac{RLC\_o + LC\_o r\_{Ca}}{2R + r\_L}\right) + s\left(\frac{L + RC\_o r\_L + C\_o r\_L r\_{Cr} + 2RC\_o r\_{Ca}}{2R + r\_L}\right) + 1}\tag{31}$$

*Automatic Current Sharing Mechanism in Two-Phase Series Capacitor Buck DC-DC… DOI: http://dx.doi.org/10.5772/intechopen.107975*

$$\begin{split} G\_{vD}(s) &= \frac{v\_o(s)}{D(s)}\Big|\_{v\_{in}=0, i\_{out}=0} \\ &= \frac{v\_{in}\frac{R}{2R+r\_L}\left(s\frac{C\_vr\_O}{R}+\mathbf{1}\right)}{s^2\left(\frac{RLC\_a+LC\_vr\_L}{2R+r\_L}\right)+s\left(\frac{L+RC\_vr\_L+C\_vr\_{rI}r\_O+2RC\_vr\_{rL}}{2R+r\_L}\right)+\mathbf{1}} \\ &= \frac{R}{2R+r\_L}\frac{v\_{in}\left(\frac{s}{a\_x}+\mathbf{1}\right)}{\frac{s^2}{a\_{o\_x}^2}+\frac{s}{Q\_ox\_v}+\mathbf{1}}\tag{32} \end{split} \tag{32}$$

Where,

$$\rho\_{\rm x} = \frac{R}{C\_{\rm or\_{\rm Co}}}, \rho\_o = \sqrt{\frac{2R + r\_L}{LC\_o(R + r\_{\rm Co})}}, \\ Q\_o = \frac{\sqrt{LC\_o(2R + r\_L)(R + r\_{\rm Co})}}{(L + RC\_{\rm or\_L} + C\_{\rm or\_{\rm Co}}r\_L + 2RC\_{\rm or\_{\rm Co}})} \tag{33}$$

Therefore, the choice of components used in a switching regulator has a large impact on its performance. Critical components such as switching elements, magnetic components, and filter capacitors all affect both the switching frequency and the overall efficiency of the converter. In the previous sections, the power switch, inductances, and capacitances were all considered ideal components. But real components are not ideal and have parasitic properties, which will affect the overall performance of the DC-DC converter. A typical output capacitor always exhibits stray elements such as *rCo*. This parasitic element introduces a zero in the control-to-output transfer function see Eq. (32). The relationship between the output parasitic capacitor (*rCo* + Δ*rCo*) and converter control-to-output transfer function is illustrated in **Figure 6**.

When using the ceramic output capacitor, the output capacitor parasitic *rCo* effect is aggravated at relatively high frequencies, often above the switching frequency so it can be seen in the gain graph. The parameter *ω<sup>o</sup>* is the angular corner frequency, which is defined as follows.

**Figure 6.** *GvD and output capacitor ESR parasitic variation from 0 to 90 mΩ.*

*Power Electronics, Radio Frequency and Microwave Engineering*

$$f\_o = \frac{o\_o}{2\pi}$$

$$f\_o = \frac{1}{2\pi} \sqrt{\frac{2R + r\_L}{RLC\_o + LC\_o r\_{Co}}}\tag{34}$$

To get a well-regulated average output voltage signal, the switching frequency must be greater than 10 times of angular corner frequency (cutoff frequency) for small or invisible output voltage ripple.

$$f\_{w} > 10f\_{o}$$

Thus, *fsw*≈20*f <sup>o</sup>* is recommended. The converter output impedance transfer function formula, including output filter parasitic, is presented as follows.

$$Z\_{\rm out} = \frac{s^2 \left(\frac{RLC\_{\rm rCs}}{2R + r\_L}\right) + sR\left(\frac{L + C\_{\rm o}r\_{\rm O}r\_L}{2R + r\_L}\right) + \frac{R}{2R + r\_L}}{s^2LC\_o\left(\frac{R + r\_{\rm O}}{2R + r\_L}\right) + s\left(\frac{L + RC\_{\rm o}r\_L + C\_{\rm o}r\_Lr\_{\rm O} + 2RC\_{\rm o}r\_{\rm O}}{2R + r\_L}\right) + 1}}\tag{35}$$

For inequality conditions, we find

$$Z\_{out} = \frac{Z\_{\mathbb{S}} \left( \frac{\mathbb{S}^2}{a\_k^2} + \frac{\mathbb{S}}{Q\_k a\_k} + \mathbf{1} \right)}{\left( \frac{\mathbb{S}^2}{a\_\circ^2} + \frac{\mathbb{S}}{Q\_\circ a\_\circ} + \mathbf{1} \right)} \tag{36}$$

Where:

$$\mathbf{Z}\_{\mathbf{g}} = \frac{Rr\_{\mathrm{L}}}{2R + r\_{\mathrm{L}}}, \ a y\_{\mathrm{k}} = \sqrt{\frac{r\_{\mathrm{L}1} + r\_{\mathrm{L}2}}{(L\_{1} + L\_{2})\mathbf{C}\_{\boldsymbol{\theta}}r\_{\mathrm{G}}}}, \ \mathbf{Q}\_{\mathrm{k}} = \frac{\sqrt{(r\_{\mathrm{L}1} + r\_{\mathrm{L}2})(L\_{1} + L\_{2})\mathbf{C}\_{\boldsymbol{\theta}}r\_{\mathrm{G}}}}{(L\_{1} + L\_{2}) + (r\_{\mathrm{L}1} + r\_{\mathrm{L}2})\mathbf{C}\_{\boldsymbol{\theta}}r\_{\mathrm{G}}} \tag{37}$$

$$\alpha\_o = \sqrt{\frac{2R + r\_L}{LC\_o(R + r\_{Co})}}, \ Q\_o = \frac{\sqrt{LC\_o(2R + r\_L)(R + r\_{Co})}}{(L + RC\_o r\_L + C\_o r\_{Co} \ r\_L + 2RC\_o r\_{Co})} \tag{38}$$

From Eq. (35), inductance parasitic variation (*rL* + Δ*rL*) affects output impedance in lower frequencies, often below the switching frequency so the gain graph increases with the inductance parasitic increases, as can be seen in **Figure 7**.

Output capacitor ESR parasitic variation affects the output impedance in high frequencies, as can be seen in **Figure 8**. From the previous two figures, we can summarize the observations in another way, where the output impedance is represented by the contribution of the filter components, as shown in **Figure 9**. By the below graph's inspection of **Figure 9**, we can see that the inductor resistive path *rL* dominates the impedance in DC. As frequency increases, the inductor then enters the spectrum. The capacitor impedance starts to take over the inductive section at higher frequencies until it becomes a short circuit and leaves the output impedance value to its series loss *rCo*. To solve for the peak value of output impedance at resonance value of *fo*, since *rCo* contribution is small and neglected at low frequencies.

$$|Z\_{out-Max}|dB = R\sqrt{\frac{2}{\frac{2}{Z\_s^2} \left(Z\_o^2 + Rr\_L\right)^2 + r\_L^2}}\tag{39}$$

*Automatic Current Sharing Mechanism in Two-Phase Series Capacitor Buck DC-DC… DOI: http://dx.doi.org/10.5772/intechopen.107975*

**Figure 7.** *Zout and inductor parasitic rL variation from 0 to 90 mΩ..*

**Figure 8.** Zout *and output capacitor ESR parasitic variation from 0 to 90 mΩ..*

Where *Zo* ¼ ffiffiffiffi *L Co* q is the characteristic impedance of the filter.

The output filter size needs to be very carefully selected to minimize voltage drop and power loss, which can be achieved by minimizing the output impedance [6]. Therefore, to get rid of the resonance frequency and maintain a good gain value, it is necessary to select a natural frequency higher than the resonance frequency. The natural frequency should be in the output capacitor region, where the influence of inductance is minimal. Thus,

$$|Z\_{o-Min}| \cong \sqrt{\left(\frac{1}{2\text{ }\pi\text{f}\_{max}\text{C}\_o}\right)^2 + r\_{\text{Co}}^2} \tag{40}$$

**Figure 9.** *Output impedance bode diagram spectrum.*

#### **4. Inductor currents derivation**

Based on the concept of automatic current sharing, we need to study the inductor current of each phase. For steady-state conditions, as seen from **Figure 10**, during interval state one and state three, the current through the inductors increases in phase sequence because energy is being stored in the inductors from the input supply or series capacitors. During the off-time of each phase, the current through inductors decreases as both inductors are sourcing energy to the output. Note that the current increase at state one is equal to the decrease in current during state two and state three of the same phase. The average series capacitor voltage *vCs* maintains its value at exactly half of the input voltage with a small voltage ripple, thus it can be regarded as a constant voltage source*.* A large magnitude difference in the inductor currents with 180o out of phase can be seen during the initial transient. This magnitude difference decreases as the steady-state condition is attained. The duration of the transient time

**Figure 10.** *The main waveforms of* 2-pscB *topology.*

*Automatic Current Sharing Mechanism in Two-Phase Series Capacitor Buck DC-DC… DOI: http://dx.doi.org/10.5772/intechopen.107975*

depends on dead time matching between the two phases and can be reduced using a soft start scheme with a pre-charged series capacitor. However, this will introduce a delay time to the circuit. The output voltage ripple can be controlled by the size of the output filter. The average charging and discharging currents for the series capacitor are similar, this verifies the steady-state operation of the 2-pscB converter. From this figure, the current ripple *(*Δ*iL*<sup>1</sup> ) through the phase inductor is greater than the total output current ripple (Δ*iL*).

State four is a repeat of state two with both inductors connected to the ground and supplying energy to the output capacitor. In state one, when the average inductor current of phase A is larger than the average inductor current of phase B, the series capacitor voltage *vCs* would slowly increase. For VRMs applications, most processors recommend low-output voltage ripple where these applications demand keeping the output current ripple low. This implies the need for a large inductor, the relationship expressed as follows:

$$V\_{ripple} = I\_{ripple} \* r\_{Co}, I\_{ripple} \propto \frac{1}{L} \tag{41}$$

On the contrary, as mentioned before, the other requirement is the fast-transient response. This justifies the need for a small inductor to allow the current through the supply to change quickly, but at the same time, this assumption conflicts directly with the need for a larger inductor to minimize output voltage ripple.

A mathematical representation of the 2-pscB converter with its internal current sharing mechanism resulting from the *vCs.* **Figure 11** shows the average model of the 2-pscB converter, including the main parasitic components and the CSM using the internal series capacitor voltage feedback loop. This block diagram aims to generate a reference trajectory to be used by the controller model.

Where the two phases' currents are:

$$\dot{q}\_{L1}(t) = \frac{1}{L\_1} \int\_0^\infty (V\_{in}D\_1 - V\_{C3}D\_1 - V\_o(t))dt\tag{42}$$

**Figure 11.** *The* 2-pscB *converter average model diagram of inductor currents and current sharing mechanism.*

*Power Electronics, Radio Frequency and Microwave Engineering*

$$\dot{a}\_{L2}(t) = \frac{1}{L\_2} \int\_0^\infty (V\_{Gz} D\_3 - V\_o(t)) dt \tag{43}$$

From current (Eqs. 42, 43), the first derivative of two-phase currents is: At *D*<sup>1</sup> ¼ *D*<sup>3</sup> ¼ *D* and *L*<sup>1</sup> ¼ *L*<sup>2</sup> ¼ *L*

$$\frac{di\_L}{dt} = \frac{di\_{L1}}{dt} + \frac{di\_{L2}}{dt} \tag{44}$$

$$I = \frac{1}{L}V\_{in}D - \frac{2}{L\ Co} \int\_{0}^{T} \left(i\_L - \frac{V\_o(t)}{R}\right)dt\tag{45}$$

The second derivatives of two-phase inductor currents, where

$$\frac{di\_{L1}^{2}}{dt^{2}} = -i\_{L1}\frac{1}{L}\left(\frac{D}{Cs} + \frac{1}{Co}\right) + i\_{L2}\frac{1}{L}\left(\frac{D}{Cs} - \frac{1}{Co}\right) + \frac{V\_{o}}{L\text{ Co }R} = a\_{1}i\_{L1} + b\_{1}i\_{L2} + c\_{1} \tag{46}$$

$$\frac{d\dot{i}\_{L2}^{2}}{dt^{2}} = \dot{i}\_{L1}\frac{1}{L}\left(\frac{D}{\text{Cs}} + \frac{1}{\text{Co}}\right) - \dot{i}\_{L2}\frac{1}{L}\left(\frac{D}{\text{Cs}} - \frac{1}{\text{Co}}\right) + \frac{V\_{o}}{L\text{Co}\ R} = a\_{2}\dot{i}\_{L1} + b\_{2}\dot{i}\_{L2} + c\_{2}\tag{47}$$

Using Laplace transform, we can derive the current time domain formulas as

$$
\begin{bmatrix} \dot{i}\_{L1}''\\ \dot{i}\_{L2}'' \end{bmatrix} = \begin{bmatrix} a\_1 \ b\_1\\ a\_2 \ b\_2 \end{bmatrix} \begin{bmatrix} \dot{i}\_{L1} \\ \dot{i}\_{L2} \end{bmatrix} + \begin{bmatrix} c\_1\\ c\_2 \end{bmatrix} \tag{48}
$$

For initial conditions of  $i\_{L1}(0) = 0$ ,  $i\_{L2}(0) = 0$ , and.

 $\frac{di\_{L1}(0)}{dt} = \frac{v\_{in}}{L}$   $D$ ,  $\frac{di\_{L2}(0)}{dt} = 0$ 

$$\frac{d\dot{i}\_L^2}{dt^2} = \frac{2}{L\text{ Co}} \left(\frac{V\_o(t)}{R} - i\_L\right) = -\frac{2}{L\text{ Co}}i\_{Co} \tag{49}$$

Since *Vin* = 0 for the second derivatives, the average output capacitor current equals zero.

< *iCo* > = 0, Then

$$\frac{d\vec{i}\_L^2}{dt^2} = \mathbf{0}\_-$$

#### **5. Series capacitor damping behavior**

To examine the damping oscillation of the current sharing of the two phases regarding inductor resistive parasitic variation. Back to Eq. (42), we can express its formula as:

$$L\_1 \frac{di\_{L1}(t)}{dt} = V\_{in} D\_1 - i\_L r\_{on1} - V\_{C3} D\_1 - i\_{L1} r\_{Cs} - i\_{L1} r\_{L1} - V\_o(t) \tag{50}$$

$$L\_2 \frac{di\_{L2}(t)}{dt} = -i\_L r\_{on2} + V\_{\text{Cs}} D\_3 - i\_{L2} r\_{\text{Cs}} - i\_{L2} r\_{on3} - i\_{L2} r\_{L2} - V\_o(t) \tag{51}$$

*Automatic Current Sharing Mechanism in Two-Phase Series Capacitor Buck DC-DC… DOI: http://dx.doi.org/10.5772/intechopen.107975*

Where *ron*1, *ron*2, *ron*3, and *ron*<sup>4</sup> represent converter switches on-state resistances, and and *rCs* represents the total series capacitor resistive parasitic component.

Where

$$V\_{\rm Gz}(t) = \frac{1}{\rm Cs} \int\_0^\infty (i\_{L1} - i\_{L2}) \, dt \tag{52}$$

Plugging Eq. (52) and substituting Eq. (50) into Eq. (51), the results at full current sharing (*ron* = *ron*<sup>1</sup> = *ron*<sup>2</sup> = *ron*<sup>3</sup> = *ron*4, and *rL* = *rL*<sup>1</sup> = *rL*2) will be,

$$\frac{d^2 i\_{\rm Cs}(t)}{dt^2} + \frac{1}{L} \left( \frac{d i\_{\rm Cs}(t)}{dt} (r\_L + r\_{on} + r\_{\rm Cs}) + \frac{(D\_1 + D\_3)}{\rm Cs} i\_{\rm Cs} \right) = 0 \tag{53}$$

To analyze the effect of *rL*, assume that other parasitic parameters are very small or zero (ideal conditions) to simplify the results also for homogeneous second-order differential equation,

$$\frac{d^2 \dot{i}\_{\rm Cs}(t)}{dt^2} + \frac{1}{L} \left( \frac{d \dot{i}\_{\rm Cs}(t)}{dt} r\_L + \frac{(D\_1 + D\_3)}{\rm Cs} \dot{i}\_{\rm Cs} \right) = 0 \tag{54}$$

Eq. (54) can be rearranged to

$$\frac{d^2i\_{\rm Cs}(t)}{dt^2} + 2\zeta a\_{\rm Cs} \frac{di\_{\rm Cs}(t)}{dt} + a\_{\rm Cs}^2 i\_{\rm Cs} = 0\tag{55}$$

which is in the form of a second-order differential equation, representing the damped harmonic oscillator nature with attenuation (*ζωCs*) and the angular resonant frequency of (*ωCs*)

$$\zeta = \frac{r\_L}{2} \sqrt{\frac{\text{Cs}}{L \, (D\_1 + D\_3)}}, \text{ } \mu\_{\text{Cs}} = \sqrt{\frac{(D\_1 + D\_3)}{L \, \text{Cs}}}, \text{ Q}\_{\text{Cs}} = \frac{1}{r\_L} \sqrt{\frac{L \, (D\_1 + D\_3)}{\text{Cs}}} \tag{56}$$

Setting initial values *iCs* (0þ) *=* 0, From Eq. (50)

$$\frac{di\_{\rm Ca}(\mathbf{0})}{dt} = c\_s \frac{d^2 v\_{\rm Ca}(\mathbf{0})}{dt^2} = \frac{D}{L} \left(V\_{in} - 2v\_{\rm Ca}(\mathbf{0})\right) \tag{57}$$

thus,

$$v\_{\rm Gz}(\mathbf{0}^+) = V\_{\rm Gz} - \frac{\Delta V\_{\rm Gz}}{2} \tag{58}$$

The damped harmonic oscillator can be translated as current perturbation representing the difference in phases average inductor currents. The effect of series capacitor ESR and switches internal on-state resistance is similar to the inductor DCR effect. For different parameters settings, to find the solution of second-order, linear, homogeneous differential equations with constant coefficients, there is a need to figure out the characteristic equation as.

**Figure 12.**

*Series capacitor characteristic equation response of (a) the difference in average inductor currents due to current perturbation in inductor currents for varying values of lumped inductor resistance and (b) the difference in average series capacitor voltage.*

$$a^2 + P\_1 a + P\_0 = \mathbf{0} \tag{59}$$

To solve equations With real coefficients, the complex roots are always distinct if they are not purely real. So, for complex roots *s*1,2 ¼ *α*∓*jβ*

$$i\_{\rm Cr} = \lambda\_1 e^{\rm at} \cos \beta \mathbf{t} + \lambda\_2 e^{\beta \mathbf{t}} \sin \beta \mathbf{t} \tag{60}$$

Where *λ<sup>1</sup>* and *λ<sup>2</sup>* are arbitrary constants, **Figure 12** depicts this type of solution.

#### **6. Unbalanced series capacitor voltage**

The 2-pscB converter current sharing mechanism tolerance will be discussed here, for many reasons, as the case of unmatched duty cycles, this topology has the ability to maintain adequate current sharing balance for a certain limit. This limit depends on the charging time of the series capacitor, which in general is affected by the quality of series capacitor material.

Since

$$\frac{V\_{\text{G}}}{V\_{\text{in}}} = \frac{D\_1}{D\_1 + D\_3}$$

$$V\_{sw1} = V\_{\text{in}} - V\_{\text{G}}$$

$$V\_{sw2} = V\_{\text{G}}$$

$$\frac{V\_{sw1}}{V\_{sw2}} = \frac{D\_3}{D\_1} = \frac{d\_3 - d\_2}{d\_1} \tag{61}$$

It turns out that under phase unbalanced conditions (duty cycle mismatch, phase placement issues, etc.), the transient time is longer than the transient time under balanced conditions when *D1* = *D3*. For unbalanced conditions, the areas of the switching voltage node pulses for both phases remain the same for a certain tolerance or boundary.

$$V\_{sw1}{}^\* D\_1 = V\_{sw2}{}^\* D\_3 = V\_o \tag{62}$$

*Automatic Current Sharing Mechanism in Two-Phase Series Capacitor Buck DC-DC… DOI: http://dx.doi.org/10.5772/intechopen.107975*

**Figure 13.** *The 2-pscB converter current sharing mechanism tolerance at* D1 = 0.2, D3 = 0.35.

An example to present these conditions is, at *D*<sup>1</sup> = 0.2 and *D*<sup>3</sup> = 0.35 or opposite values, as shown in **Figure 13**,

$$\frac{V\_{sw1}}{V\_{sw2}} = \pm \mathbf{1.75} \text{ and } V\_{sw1} \neq V\_{sw2} \tag{63}$$

Therefore, phase A switching node voltage*Vsw*<sup>1</sup> increased to compensate for the reduction in the on-time of the phase. As shown in **Figure 13**, in both buck phases, when the high-side switch is turned off, the low-side (synchronous rectifier) switch is turned on, and the current is circulating through the lower switch. Since the inductor current cannot instantaneously stop, the "on-time" and "off-time" of the switch are unbalanced. Each phase inductance is large enough to ensure that it works in the continuous conduction mode (CCM). For certain limits, during steady-state operation, the series capacitor voltage can still manage to maintain the desired output voltage and stabilize current sharing among the two phases [7–12]. The 2-pscB topology has been fully investigated using different Si MOSFETs and GaN switches. The theoretical and experimental testing specifications for the eGaN-based 48 V/5Vdc 2-pscB converter are listed in **Table 1**.

**Figure 14** shows the main proposed prototypes and evaluation modules of GaN transistors and Si MOSFETs 2-pscB converters at different voltage rate (*Vin* < 120 V). Experimental results to examine the CSM for the phase-sensorless GaN-based 48 V/ 5 V 2-pscB converter with an efficiency of up to 94.9% are shown in **Figure 15**. To construct the converter GS61004B transistors with *Rds(on)* of 15 mΩ are used. Despite the two-phase parasitic components' layout unbalance, the waveform shows output voltage, series capacitor current, and the fully automatic current balancing (≈100%) between two phases.

The output current ripple (*IL*) is less than the phase ripple (*iL(rms)* = *iL1(rms)* + *iL2 (rms)*), which is one of the technical advantages of multi-phase that the combined output ripple (total ripple) is less than the ripple current in each phase. This occurs due to driving the phases out of phase. To achieve the complete current sharing


#### **Table 1.**

*2-pscB converter evaluation parameters.*

*The proposed* 2-pscB *converter EVM prototypes using different switches at (*Vin < 120 V*)*.

balance between two phases, the switching nodes voltage must be the same. Also, for the voltage equations of phase inductors *vL*<sup>1</sup> and *vL*<sup>2</sup> (see **Figure 1a**), these voltages must equal each other. This equivalency gives the expression of the series capacitor voltage in terms of the topology parasitic values as follows:

$$\upsilon\_{\rm Cs} = \upsilon\_{\rm in} \frac{D\_1}{D\_1 + D\_3} + \frac{i\_{L\_1} \boxleftarrow{i}\_1 + i\_{L\_2} \boxleftarrow{i}\_2}{D\_1 + D\_3} \tag{64}$$

Where parasitic coefficients are

$$\begin{aligned} \Xi\_1 &= r\_{on}(\mathbf{1} + D\_3 - 2D\_1) - D\_1 r\_{Cs} - r\_{L1} \\ \Xi\_2 &= 2D\_3 r\_{on} + D\_3 r\_{Cs} - r\_{on} + r\_{L2} \end{aligned}$$

*Automatic Current Sharing Mechanism in Two-Phase Series Capacitor Buck DC-DC… DOI: http://dx.doi.org/10.5772/intechopen.107975*

#### **Figure 15.**

*The* 2-pscB *converter typical waveforms of* iCs (above), iL1, iL2 (middle), and Vo *(below) at 48 V input and 250 kHz.*

For small variations in topology duty cycles, parasitic coefficients can be neglected. The complete current sharing conditions can be reached at∈<sup>1</sup> =∈<sup>2</sup> ffi (0)

Analytical and experimental comparisons between the traditional buck topology and the 2-pscB topology show that the 2-pscB topology can reduce power losses by up to 31% at full load. Analytical estimates show that the maximum converter inductor size reduces by 55%, and inductor current ripple reduces by 30% compared with conventional bucks at the same switching frequency and duty cycle. This study concludes that the 2-pscB topology requires only 34% of the conventional buck capacitor [13–16]. Please note that the efficiency of this topology increases with the size of the inductor, but at the cost of transient response performance.

#### **7. Conclusion**

The main purpose of this chapter is to provide a comprehensive overview of the 2-pscB topology current sharing mechanism starting from the model of the AC smallsignal variation of the system to the characteristic equations response of balanced and unbalanced series capacitor voltage. This would help in the enhancement of the overall performance. Theoretical analysis of damping behavior of series capacitor current is formulated, and series capacitor voltage compensation mechanism of the topology current was presented. Detailed studies of the mathematical representation modeling and Laplacian matrices of the 2-pscB converter with an internal voltage feedback loop were presented to help build an efficient converter controller. Based on the above, this topology needs an additional control circuit that can limit the inrush current caused by series capacitance and output capacitor charging period at the beginning of the transient time. The duration of the transient time depends on dead time matching between the two phases and can be reduced using a soft start scheme with a pre-charged series capacitor. Since phase B has no series capacitor, for traditional half-bridge gate driving circuits, inserting a series capacitor between power

switches of phase A increases loop parasitic inductance, introducing a time delay mismatch between the gate voltages of the phase switches. This mismatch can eventually cause interference with the synchronization of the dead time between phase A and B of 2-pscB converters. Using traditional half-bridge gate driving circuits in 2 pscB, the turn-off delay of phase A switches caused by its *CDS* discharging period appears and amplifies by parasitic effects and the phases'sinking path mismatch. Careful consideration has to be given to the specifications of the series capacitor to tackle parasitic and mismatch problems.

#### **Conflicts of interest**

The author declares that there are no conflicts of interest regarding the publication of this chapter.

### **Author details**

Salahaldein A. Rmila Department of Electrical Engineering, University of Arkansas, Fayetteville, USA

\*Address all correspondence to: saa016@uark.edu

© 2022 The Author(s). Licensee IntechOpen. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

*Automatic Current Sharing Mechanism in Two-Phase Series Capacitor Buck DC-DC… DOI: http://dx.doi.org/10.5772/intechopen.107975*

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Section 2
