**4. VHDL code generation and synthesize results**

The VHDL code generation and synthesis steps can be validated after verifying the functionality of the XSG architecture of the proposed SVM-DTC-IOFL. The obtained simulation results of the section confirm the good functionality of the designed XSG architecture, which offers the possibility to generate the VHDL and determine the synthesis results utilizing the Xilinx Vivado. During the hardware implementation of the classical DTC and the proposed SVM-DTC-IOFL approaches, the used resources from the FPGA are depicted in **Table 4**.


**Table 4.**

*Utilized resources from Xilinx Zynq FPGA.*
