**Abstract**

This chapter proposes a design of hardware architecture of an improved Direct Torque Control (DTC) for a real-time implementation on a Xilinx Field-Programmable Gate Array (FPGA). The first contribution in this chapter consists in combining the DTC with a Space Vector Modulation (SVM) technique and an Input-Output Feedback Linearization (IOFL) approach. In fact, the classical DTC has remarkable performance in terms of fast torque response and less dependence on the system parameters. Despite the cited advantages, the classical DTC is penalized by high torque ripples and inverter-switching-frequency variations. In this context, the SVM is added to the DTC structure in order to keep the switching frequency constant and to reduce ripples. Furthermore, the nonlinear IOFL is proposed to achieve a decoupled flux and torque control. The novel structure is named in this chapter as DTC-IOFL-SVM. Moreover, this chapter presents a hardware implementation of the suggested DTC-IOFL-SVM strategy utilization. The hardware implementation is chosen in order to reduce the sampling period of the system thanks to the parallel processing of the FPGA. In order to demonstrate the performance of the FPGA implementation of the proposed DTC-IOFL-SVM, numerous simulation results are presented using the Xilinx system generator under a Matlab/Simulink.

**Keywords:** induction motor, direct torque control, input–output feedback linearization, FPGA
