Low-Power CMOS/FinFETs Circuit Using Adiabatic Switching Principle

*Cancio Monteiro*

## **Abstract**

Power consumption has become a very serious concern with regard to the rapid technology of Internet of Things (IoT) devices. The IoT devices, such as sensor nodes, secure cryptographic devices, and medical implantable devices are general embedded systems that require low power and operate at low-frequency speed. Countless efforts have been done to reduce power consumption in complementary metal oxide semiconductors (CMOS) through supply voltage downscaling, reducing unnecessary clock activity, avoiding long path circuit topology, etc. Another circuit technique for lowpower purpose is by employing adiabatic switching principle. The adiabatic switching is commonly used in minimizing energy loss during charging/discharging period at all nodes of the circuit. In this paper, a low-power adiabatic CMOS/FinFETs circuit for low-power secure logic application is presented. The circuit speed, power consumption, and other evaluation metrics indicating the circuit performances will be compared among the proposed circuits and other circuit topologies that are available in the literature.

**Keywords:** CMOS, adiabatic, low-power, FinFETs, dual-rail, PUF, secure logic, LSI multiplier

## **1. Introduction**

In recent years, the emerging Internet of Things (IoT) technology has introduced challenges and opportunities for engineering-related fields. It is estimated that the number of active IoT devices will surpass 25.4 billion in 2030 [1], including wired and wireless sensor networks. Most researchers consider the security profile (authenticity, integrity, and confidentiality) [2–8] and power-saving crypto-devices [9, 10] as challenging efforts in IoT network design for resilient and sustainable infrastructure of Industry 4.0 [11]. With the rapid growth of portable and standalone IoT devices, the energy availability has to be well-managed to assure the sustainability of IoT connectivity. These IoT devices can be supplied either by utilizing abundant ambient energy sources [12] or by powering with rechargeable battery technology. In this context, the electronic circuit design technique that is able to consume low power has to be addressed. To contribute to the secure communication among IoT devices, the circuit designers are again demanded to produce secure cryptographic devices to withstand

side-channel-analysis (SCA) attract techniques [13–16]. In tackling both the lowpower and high-security demand, numerous efforts have been done at the circuit design level by employing the adiabatic switching principle [17]; such as secure adiabatic logic (SAL) [18], symmetric adiabatic logic (SyAL) [19], 2N-2N2P [20, 21], charge-sharing symmetric adiabatic logic (CSSAL) [22], 2-phase symmetric pass gate adiabatic logic (2-SPGAL) [23], and the secure quasi-adiabatic logic (SQAL) [24]. Moreover, to confirm the authenticity of any crypto-device, a physically unclonable function (PUF) circuit is utilized to verify the chip authenticity and for secure key generation [25, 26]. Definition of a PUF in [27] states that a PUF is a hardware security fundamental that translates an input challenge into an output response through a physical system in a manner that is specific to the exact hardware instance (unique) and cannot be replicated (unclonable). The PUF related SRAM-based circuit design in adiabatic operation was first reported in Quasi-Adiabatic Logic PUF (QUAL-PUF) [28]. Accordingly, the author of this paper then proposed the CMOS-based two-phase clocking adiabatic PUF (TPCA-PUF) [29], and the PUF circuit stability is further investigated under various temperature and process variations using FinFETS technology [30].

In this paper, the author further describes the adiabatic circuit design technique for low-power application, using single-rail and dual-rail circuit topologies. The proposed circuits' operation, the evaluation metrics utilized for secure logic verification, the frequency spectrum of the proposed circuits, and the LSI circuit design using proposed circuits in comparison with previous works to validate the effectiveness and the performances of the proposed works are presented.

The rest of this paper is structured as follows: Section 2 describes the fundamental low-power circuit design, which briefly describes the adiabatic switching principles in comparison with the conventional CMOS logic circuit. Section 3 presents the proposed CMOS logic circuit topologies in detail. Section 4 describes the proposed LSI circuits, their respective simulation conditions, and the security evaluation metrics. Simulation results and technical discussion of the proposed works in comparison with the convention-related circuits are discussed in section 5. Finally, Section 6 concludes the research findings of this work.

## **2. Low-power circuit design technique**

To ensure the long battery life for battery-powered embedded cryptographic devices, the CMOS power consumption needs to be highly considered. There have been several circuit design techniques reported to reduce dynamic power consumption, such as reducing supply voltage to near and subthreshold regions, reducing circuit switching activities, and avoiding long critical paths to diminish unnecessary glitch current, etc. From the circuit supply voltage point of view, adiabatic logic principle is a promising technique that can guarantee the efficiency of power usage. Therefore, in the following subsections, the author describes power consumption comparison among conventional and adiabatic CMOS logic styles.

### **2.1 Power consumption of CMOS circuit**

Total power in a CMOS circuit comes from dynamic power, short-circuit power, and static (or leakage) power, as indicated in **Figure 1**. The dynamic power consumption occurs when the output node's capacitor CL is switched (charging period). *Low-Power CMOS/FinFETs Circuit Using Adiabatic Switching Principle DOI: http://dx.doi.org/10.5772/intechopen.107151*

The short-circuit power happens when both PMOS (PM) and NMOS (NM) transistors operate simultaneously during a short period of time of different input signal transitions (such as *In(t)* signal changes from 0 ➔ 1 and 1 ➔ 0). The other contributing power is the static power, which is consumed at either PM or NM transistor that operate in the cutoff region (or any electronic device is in standby mode).

$$P\_{Total} = P\_{Dynamic} + P\_{\rm SC} + P\_{\rm Sattic} \tag{1}$$

## *2.1.1 Dynamic power*

Dynamic power consumption commonly depends on the switching frequency *f*, amplitude of power supply *Vdd***,** and the load capacitance *CL* of the output node. The operation of CMOS inverter logic in **Figure 1** is that when the state of input signal *In(t)* changes from 1 ➔ 0, the PM transistor is switched ON, and the current supply from *Vdd* is flowing down to charge the output node of *CL* from initial condition of Vy(0\_) = 0 ➔ Vy = *Vdd*. The internal equivalent RC model during this operation is called a pull-up network (PUN), as shown in **Figure 2a**. On the other hand, when the state of input signal *In(t)* charges from 0 ➔ 1, the NM transistor is switched ON and the output node of Vy is discharged from initial condition of Vy(0\_) = Vdd ➔ Vy = 0 level (grounded). The internal equivalent RC model during this operation is called a pull-down network (PDN), as shown in **Figure 2b**.

From **Figure 2**, the total power dissipation can be calculated using each network system. By considering the MOS resistance value of 1/gmn = 1/gmp = R, CL = C, we can calculate the current source that flows into the circuit, as shown in Eq. (2):

$$ip(t) = i(t) = \frac{V\_{dd}}{R}e^{\frac{1}{RC}t} \tag{2}$$

The power consumption is calculated as:

#### **Figure 2.**

*(a) A CMOS pull-up network (PUN) RC equivalent model for charging phase, (b) A CMOS pull-down network (PDN) RC equivalent model for discharging phase.*

$$p(t) = i(t)V\_R(t) = i(t)^2 R = \frac{V\_{dd}}{R}e^{-2\frac{1}{RC}}\tag{3}$$

Hence, the energy dissipated over the period of *t=0* to *t=τ* is calculated as follows:

$$E\_{\text{charge}} = \int\_0^\tau p(t)dt = \int\_0^\tau \frac{V\_{dd}}{R} e^{-2\frac{\mathbf{k}\cdot\mathbf{r}}{R}} dt = C\frac{V\_{dd}}{2} \left(e^{-2\frac{\mathbf{k}\cdot\mathbf{r}}{R}} + \mathbf{1}\right),\tag{4}$$

If, *τ* >> *RC*, then the energy charged in output load capacitance is:

$$E\_{charge} = \frac{1}{2} \text{CV}\_{dd}^2\tag{5}$$

From Eq. (5), half of the energy is dissipated as heat by the resistance 1/gmp in **Figure 2a**; therefore, the total energy dissipated from power supply during PUN operation is *Etotal = CVdd 2 .* Then, the average dynamic power *Pdynamic*=*Etotal/T,* which is consumed during a certain period of time *T* can be formulated as

$$P\_{dynamic} = a \text{fCV}\_{dd}^2,\tag{6}$$

where, the *f* denotes the clock frequency, and α is the switching activity factor, which corresponds to the average number of 0 ➔ 1 transitions that occur at the output cell in each clock cycle.

#### *2.1.2 Short-circuit power*

Short circuit power (*PSC*) usually occurs because there is no zero second exist during different data transitions in CMOS logic circuit. The detailed discussion of short-circuit power was reported in [31], with an expression shown in Eq. (7);

$$P\_{\rm SC} = \frac{1}{12} \beta \text{gf} \left( V\_{dd} - 2V\_T \right)^3 \tag{7}$$

where *β* is a gain factor of a MOS transistor, *τ* represents the rise and fall time, *f* denotes a clock frequency, and the *VT* is the MOS transistor threshold voltage.

#### *2.1.3 Static power*

Static power consumption is power loss when the transistor is not in the process of switching (cut-off state). It occurs when a small leakage current (*Ileak*) is flowing through the MOS transistor that is turned off. Static power is increasing significantly proportional to the shrinking of CMOS process technology.

There are several components that trigger the occurrence of leakage power [32, 33] as shown in **Figure 3**; such as (1) Reverse bias diode leakage current (*Irbdl*), which occurs due to the reverse bias current of p-n junction between diffusion region of the transistor and substrate; (2) Gate oxide tunneling current (*Iox*) is the leak current that flows from oxide insulation to substrate; (3) Gate induced drain leakage (*GIDL*) is another leakage current that increases exponentially due to the reduced gate oxide thickness; and (4) Subthreshold leakage current (*Isub*). Thereby, the total summation of all leakage current *Ileak* components aforementioned can be formulated as:

$$P\_{leak} = I\_{leak} V\_{dd} \tag{8}$$

### **2.2 Adiabatic switching principle**

The adiabatic switching technique enables the logic circuit to reuse energy stored in output load capacitance during the recovery phase, known as energy recycling [17]. For better understanding of the adiabatic switching principle, the author uses the same RC model circuit with a different power supply as depicted in **Figure 4**. **Figure 4a** represents conventional logic with constant step *Vdd* voltage, whereas **Figure 4b** explains the concept of adiabatic switching with ramped step voltage, which is defined by the length of time.

**Figure 3.** *Components of leakage power in CMOS [34].*

#### **Figure 4.**

*Equivalent RC model of CMOS logic versus adiabatic logic; (a) CMOS logic with step voltage and (b) Adiabatic logic with ramped step voltage. (c) The peak supply current of the adiabatic logic is significantly lower than that of the conventional CMOS logic under the same simulation parameters and conditions.*

Applying Kirchhoff Voltage Law (KVL) for the circuit in **Figure 1a** and **b**, the equation for charging network of the conventional CMOS is expressed in Eq. (9)

$$\mathbf{R}\_{\mathbf{i}(t)} + \frac{1}{\mathbf{C}} \int\_{0}^{\mathbf{T}} \mathbf{i}(\mathbf{t}) \mathbf{d}\mathbf{t} + \mathbf{v}(\mathbf{0}\_{-}) = \mathbf{V}\_{\mathbf{dd}} \tag{9}$$

and the charging network for adiabatic switching is similarly expressed in Eq. (10)

$$\mathbf{R}\_{\mathbf{i}(\mathbf{t})} + \frac{\mathbf{1}}{\mathbf{C}} \int\_{0}^{\mathbf{T}} \mathbf{i}(\mathbf{t}) \mathbf{d}\mathbf{t} + \mathbf{v}(\mathbf{0}\_{-}) = \frac{\mathbf{V} \mathbf{d} \mathbf{d}}{\pi}(\mathbf{t}) \tag{10}$$

where τ is the rising time of ramp voltage *Vdd.* Applying the Laplace transform and inverse Laplace transform, we obtain the charging current as expressed in equations (11, 12) for CMOS logic and adiabatic logic, respectively:

*Low-Power CMOS/FinFETs Circuit Using Adiabatic Switching Principle DOI: http://dx.doi.org/10.5772/intechopen.107151*

$$\mathbf{i}(\mathbf{t}) = \frac{\mathbf{V}\_{\text{dd}}}{\mathbf{R}} \mathbf{e}^{-\frac{1}{\mathbf{R}\cdot\mathbf{t}}} \tag{11}$$

$$\mathbf{i(t)} = \frac{\mathbf{V\_{dd}}\mathbf{C}}{\pi} \left(\mathbf{1} - \mathbf{e^{-\frac{1}{\mathbf{RC}}t}}\right) \tag{12}$$

The peak current difference of (Eqs. 11, 12) shows a large area and sudden flow of the current of the conventional CMOS, and gradual increase of supply current peak of the adiabatic switching in accordance with slow rising τ, which can be observed in **Figure 1c**.

Further analysis from an energy consumption perspective, the dissipated energy over the period *t* = 0 to *t* = τ is expressed as in Eq. (13)

$$\mathbf{E}\_{\rm diss} = \int\_0^\pi \mathbf{R}^2(\mathbf{t})d\mathbf{t} + \mathbf{E}(\mathbf{0}\_-) \tag{13}$$

Substituting current *i*(*t*) in Eqs. (11, 12) into Eq. (13), we have energy stored in capacitance for each conventional CMOS and adiabatic switching as expressed in Eqs. (14, 15), respectively.

$$\mathbf{E\_{CMOS}} = \frac{1}{2}\mathbf{C}\mathbf{V}\_{\mathrm{dd}}^2\tag{14}$$

$$\text{E}\_{\text{Adàbatic}} = \frac{\text{RC}}{\pi} \text{CV}\_{\text{dd}}^2 \tag{15}$$

Eq. (15) obviously shows that by increasing the time of τ, the energy dissipation of adiabatic logic is significantly lower compared to the one of the conventional CMOS logics in Eq. (14).

## **3. CMOS logic circuit topology**

The logic circuit available in the literature has two kinds of circuit topologies; the single-rail (SR) logic circuit composes of static CMOS (scCMOS: see **Figure 1**) and dynamic CMOS logics [35], and the dual-rail CMOS logic (DR-CMOS or differential logic) [20, 36], as depicted in **Figure 5a** and **b**. Regarding these circuits, uncountable research have been done from the viewpoint of low-power dissipation [20, 36–41], high speed, and further application into the secure cryptographic hardware design [18–24, 42, 43]. From the logic's security perspective, balancing supply current flows into the circuit is the main constraint, since the side-channel cryptanalysis targeting for the different peak current/power traces when crypto devices execute encryption and decryption processes [14]. Hence, **Figure 5** describes the supply current traces at different input data transitions for conventional static CMOS, dual-rail CMOS circuits (refers to **Figure 5a** and **b**, respectively), and our previously proposed charge-sharing symmetric adiabatic logic (CSSAL [22]). Effective side-channel analysis countermeasure is how the circuit is able to mask different input transitions with the same supply peak current despite any input�output data flipping. This can be solved by the charge-sharing technique of the proposed CSSAL circuit. In addition, the CSSAL adopted the adiabatic switching principle, which lower peak current compared with the conventional CMOS logic technique in scCMOS and DR-CMOS in **Figure 5**.

**Figure 5.** *Logic circuit topology and each of its supply current traces.*

## **4. Proposed LSI circuit**

The author of this paper has proposed three different circuit applications based on SR and DR CMOS circuit topologies for low-power and high-security profile, such as CSSAL [22], the source biased semi-adiabatic logic (SBSAL) [41], and the two-phase clocking adiabatic physical unclonable function (TPCA-PUF) [29]. In these following sub-sections, the author will present the fundamental circuit topology of each and their respective LSI block diagram.

## **4.1 The CSSAL circuit**

The fundamental inverter logic style of the CSSAL circuit is shown in **Figure 5c**. The CSSAL is designed using DR circuit topology with four phases of adiabatic switching operations (charge-sharing, evaluation, hold, and recovery phases) [22], in which, the same internal equivalent RC model of each phase occurs for all possible different input data transitions, which yielding the same peak current as depicted in the right side of **Figure 5c**. It is obviously shown in **Figure 5** that the CSSAL performs balanced low peak current in comparison with the other logic circuits along the four

different input transitions. This type of supply current trace is difficult to predict the position of its true input data, hence it is secure and applicable for cryptographic LSI design (**Figure 6**). To validate the security merit of the proposed CSSAL, the bit parallel cellular multiplier over finite field *GF*(2<sup>4</sup> ) has been designed and implemented using the 0.18 um CMOS process technology. Input-output signals of the bit parallel cellular multiplier over *GF* (24 ) are depicted in **Figure 7**.

### **4.2 The SBSAL circuit**

The proposed SBASL circuit is a type of SR static CMOS logic family in adiabatic switching operation with sinusoidal power clock supply, as depicted in **Figure 8d**. The SBSAL circuit is basically operated in charging and discharging periods, in which the equivalent RC model of PUN and PDN are depicted in **Figure 9a** and **b**. This figure illustrates the output voltages, the instantaneous power, and the energy dissipated during charging and discharging phases. The total energy loss in SBSAL logic circuit is formulated in Eq. (16) as follows:

$$\mathbf{E\_{SBSAL}} = \frac{\mathbf{RC}}{\tau} \mathbf{CV\_{PC}}^2 + \frac{\mathbf{1}}{2} \mathbf{CV\_{bias}}^2 + \frac{\mathbf{RC}}{\tau} \mathbf{C(V\_{out} - V\_{bias})}^2 \tag{16}$$

This Eq. (16) means the energy stored in the load capacitance *CL* is recycled to *Vbias* power supply. Although there is nonadiabatic energy loss of <sup>1</sup> <sup>2</sup>CVbias <sup>2</sup> in Eq. (8), the V*bias* is set to 0.23 V, which has very low contribution to the total energy loss in the circuit. The SBSAL circuit PDN network is connected to 0.23 Volt bias voltage instead of connecting to ground or another sinusoidal supply voltage. This connection technique will only require one circuit to produce *Vpc* power supply. This means that the proposed SBSAL has low complexity if compared to the other adiabatic logic family shown in **Figure 8b** and **c**.

To validate the effectiveness of the proposed logic as a low-power SBSAL circuit, we implemented a 4x4-bit array SBSAL LSI multiplier as depicted in **Figure 10**. It is verified that the SBSAL multiplier logic function is well operated as shown in **Figure 11**.

**Figure 6.** *The circuit block diagram of the bit parallel cellular multiplier over* GF *(2<sup>4</sup> ).*

**Figure 7.**

*Input-Output signals of the CSSAL bit parallel cellular multiplier over* GF *(24 ).*

## **4.3 The TCPA-PUF circuit**

The proposed adiabatic FinFETs based PUF circuit topology is depicted in **Figures 12** and **13a**. It was designed with cross-coupled latch circuit based on SRAM circuit topology. The challenge signal of the proposed PUF circuit is controlled by the static CMOS inverter aimed to conduct charging and discharging of the PUF cell semiadiabatically using a trapezoidal power clock signal of Vpc. Notable improvement from QUAL-PUF circuit topology, the TCPA-PUF controls the current flow from output nodes to slowly flow to the ground through N4 transistor by controlling its operation speed with a ramped Vpc- signal. Notably, in the proposed adiabatic PUF circuit, the author applies two phases of power clock signals Vpc and Vpc-, as depicted in **Figure 14b**. The circuit operation of the TCPA-PUF cell is shown in **Figure 15**. Detailed TCPA-PUF circuit operation in an adiabatic mode for CMOS-based design has been clearly explained in [29], and the FinFETs-based TCPA-PUF design can be accessed in [30].

To verify the effectiveness and the stability of the proposed SRAM based TCPA-PUF, the author designs a 4-bit cascaded adiabatic PUF as depicted in **Figure 14**. Each local PUF is supplied with four different power clocks with a phase difference of 90̊.

*Low-Power CMOS/FinFETs Circuit Using Adiabatic Switching Principle DOI: http://dx.doi.org/10.5772/intechopen.107151*

**Figure 8.**

*Inverter logic investigated; a) Conventional CMOS logic, b) Adiabatic 2PASCL logic [39], c) Adiabatic 2PC2AL logic [40], and d) Proposed SBSAL [41].*

**Figure 9.** *Proposed SBSAL logic operation; a) Discharging period and b) Charging Period.*

**Figure 10.** *Circuit diagram of a 4x4-bit array LSI multiplier.*

**Figure 11.** *Input-output signals of SBSAL multiplier at 25 MHz.*

*Low-Power CMOS/FinFETs Circuit Using Adiabatic Switching Principle DOI: http://dx.doi.org/10.5772/intechopen.107151*

**Figure 12.** *SRAM-based FinFET PUF circuit; (a) QUAL-PUF circuit, (b) TCPA-PUF circuit.*

**Figure 13.** *Input and output signals of the proposed CMOS TCPA-PUF cell with nominal 1.8 V of Vdd voltage.*

**Figure 14.** *Proposed 4-bit CMOS/FinFET TPCA-PUF architecture.*

Moreover, each challenge bit signal has ¼ delay time of one power clock cycle. This delay time allows the challenge bits to flip the response signals right at the middle point of the idle/wait phase of the *Vpc* signals, and the challenge bits are perfectly flipped adiabatically.

Monte-Carlo simulation results of the 4-bit TPCA-PUF and QUAL-PUF challengeresponse signals are depicted in **Figure 16**, where 100 times repetitions of the same 4-bit LSI PUF circuit are simulated. This result is performed with reference temperature of T = 27°C and CL = 10 fF, *fCb* = 10 MHz, and *fVpc* = 100 MHz with 10% of Vth variation. Simulation results of response signals (Rb1–Rb4) with a given challenge bit (Rb) performed correct and stable operations for both PUF circuit topologies.

**Figure 15.**

*Monte-Carlo simulation result of proposed 4-bit FinFET based TPCA-PUF LSI circuit with nominal 1 V of Vdd voltage.*

*Low-Power CMOS/FinFETs Circuit Using Adiabatic Switching Principle DOI: http://dx.doi.org/10.5772/intechopen.107151*

#### **Figure 16.**

*Energy dissipation of the LSI multiplier circuits; (a) bit parallel cellular multiplier over* GF *(24 ) with secure CSSAL circuit (refer to Figure 6), (b) 4x4-bit array multiplier (refer to Figure 10 with SBSAL circuit).*

## **5. Simulation results and discussion**

The simulation results presented in this section are all obtained from LTSpice simulation of both CMOS and FinFETs technologies, while the simulation conditions are described in **Table 1**.

The technical discussion in this paper will only focus on energy dissipation, which reflects the title of low-power of this paper. Energy dissipated by each LSI circuits is obtained from the following Eq. (17) formula:

$$E\_{\rm SRSAL} = \int\_0^T \left( V\_{pc(t)} I\_{pc(t)} + V\_{bias} I\_{bias(t)} \right) dt,\tag{17}$$

and energy dissipation for both CSSAL and TCPA-PUF are formulated in Eq. (18):

$$E\_{\rm diss.} = \int\_0^T \Sigma(Vpcs.Ipcs)dt. \tag{18}$$


**Table 1.** *Simulation conditions.* 1. In CSSAL design process, the author has employed several techniques, such as (1) adopting the adiabatic switching principle for energy recycling to achieve low power consumption and low peak current, (2) dual-rail logic circuit topology is utilized to establish uniform transitional supply peak current, and (3) symmetric pull-down network transistors with internal node charges are shared and discharged to ground simultaneously, which construct a constant internal equivalent RC model for all input condition to reduce current-to-data dependency. The evaluation metric in our proposed CSSAL circuit has two targets: the secure logic and low power. For secure logic verification, we evaluate the logic ability to balance current traces by calculating the normalized standard deviation as in following Eq. (19):

$$\text{NSD} = \sigma\_{\text{E}} / \text{\text{\textdegree E}},\tag{19}$$

where the Ē is the average of energy dissipation of every respective input transition, and the standard deviation of **σ**<sup>E</sup> = ffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi P*En <sup>i</sup>*¼*E***1**ð Þ *Ei* � **<sup>E</sup> <sup>2</sup>** *=n* q . The ideal value of NSD has to be 0%. The post-layout comparison of secure logic circuits in this paper is as labeled in **Figure 16a**, such as TDPL, SyAL, CSSAL, and the 2N-2N2P. The NSD result calculated at 1.25 MHz has shown that the CSSAL has 3.49%, SyAL: 4.69%, 2N-2N2P: 49.08%, and TDPL has 58.71%. Moreover, the energy dissipation per cycle of post-layout simulation is shown in **Figure 16a**, in which the proposed CSSAL consumes low energy at lower frequencies (1.25 MHz and below). Therefore, the proposed CSSAL cellular multiplier is suitable for low-power and high-security devices at 1.25 MHz and/or below this speed.


$$\text{Uniquures}\ (U(\%)) = \frac{2}{k(k-1)} \sum\_{i=1}^{k-1} \sum\_{j=i+1}^{k} \frac{HD\left(R\_i, R\_j\right)}{n} \times 100. \tag{20}$$

The *Reliability* measures how reproducibly the challenge-response pairs of a PUF instance with the varying environmental conditions such as temperature and CMOS process variations as shown in Eq. (21):

$$Reliability\left(R(\text{\textquotedbl})\right) = 100 - \frac{1}{k} \sum\_{i=1}^{k} \frac{HD\left(R\_{i,} R\_{i,j}\right)}{n} \tag{21}$$

*Low-Power CMOS/FinFETs Circuit Using Adiabatic Switching Principle DOI: http://dx.doi.org/10.5772/intechopen.107151*


#### **Table 2.**

*Comparison of conventional and proposed adiabatic PUFs (with T = 27°C and CL = 10 fF,* fCb *= 10 MHz, and* fVpc *= 100 MHz).*

The ideal values of *uniqueness* and *reliability* are 50% and 100%, respectively. The TCPA-PUF evaluation results have always been close to the ideal values.

It has been revealed that the FinFET device has several advantages, such as higher on-state current, lower off-state current (lower leakage current), faster-switching speed [44], and its double gates enabling three possible connection modes (shorted gate-SG, independent gate-IG, and low-power-LP) for low power and high-speed applications. In this work, the author has thoroughly investigated the proposed TPCA-PUF cell using bulked FinFET with a 45 nm process for all SG, IG, and LP modes. As a result, the author has revealed that SG mode is suitable for the proposed TPCA-PUF circuit topology. The gate connection type of LP and IG modes leads to higher energy and produces wrong response bits for larger cascaded bit-length (4-bit in this work). Therefore, the whole works of 4-bit LSI design and simulation, including the data presented in this paper are performed by utilizing the SG mode connection type. The TPCA-PUF cell was implemented using SRAM-based circuit topology, hence this study is claimed to be the first work in the literature that employs FinFETs-based SRAM type PUF. Numerical data in **Table 2** compare the QUAL-PUF and proposed TPCA-PUF for both CMOS and FinFETs process technologies. Overall data in **Table 2** have shown that the proposed TPCA-PUF consumes lower energy/bit/cycle and start-up power, which is suitable for low-power IoT application.

## **6. Conclusion**

This paper has presented a comparative study on energy dissipation and secure evaluation metrics of the proposed CSSAL, SBSAL, and QUAL-PUF with other conventional related circuit topologies.

1.Secure CSSAL: the NSD result calculated at 1.25 MHz has shown that the CSSAL has 3.49%, SyAL: 4.69%, 2N-2N2P: 49.08%, and TDPL has 58.71%. Moreover, the energy dissipation per cycle of post-layout simulation has shown that the

CSSAL consumes low energy at lower frequencies (1.25 MHz and below). Therefore, the proposed CSSAL cellular multiplier is suitable for low-power and high-security devices at 1.25 MHz and/or below this speed.


The uniqueness, reliability, and the BER of the proposed FinFETs-based TPCA-PUF are 50.13%, 99.57%, and 0.54%, which exhibits a superior security performance if compared with the FinFETs-based QUAL-PUF cell. The remarkable performances (ultra-low power and security profile) of the proposed FinFETs-based TPCA-PUF makes it an appropriate candidate for low-power and secure IoT device applications.

## **Author details**

Cancio Monteiro Faculty of Engineering Science and Technology, Department of Electronics and Electrical Engineering, National University of Timor Lorosa'e (UNTL), Dili, Timor-Leste

\*Address all correspondence to: cancio.monteiro@untl.edu.tl

© 2022 The Author(s). Licensee IntechOpen. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

*Low-Power CMOS/FinFETs Circuit Using Adiabatic Switching Principle DOI: http://dx.doi.org/10.5772/intechopen.107151*

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## **Chapter 7**

## Resistive Switching and Hysteresis Phenomena at Nanoscale

*Vithaldas Raja and Ramesh Mohan Thamankar*

## **Abstract**

Resistive switching at the nanoscale is at the heart of the memristor devices technology. These switching devices have emerged as alternative candidates for the existing memory and data storage technologies. Memristors are also considered to be the fourth pillar of classical electronics; extensive research has been carried out for over three decades to understand the physical processes in these devices. Due to their robust characteristics, resistive switching memory devices have been proposed for neuromorphic computation, in-memory computation, and on-chip data storage. In this chapter, the effects of various external stimuli on the characteristics of resistive switching devices are comprehensively reviewed. The emphasis will be given on 2 dimensional (2D) materials, which are exciting systems owing to superior electrical characteristics combined with their high stability at room temperature. These atomically thin 2D materials possess unique electrical, optical and mechanical properties in a broad spectrum, and open the opportunity for developing novel and more efficient electronic devices. Additionally, resistive switching due to light has also grabbed the attention of optoelectronic engineers and scientists for the advancement of optical switches and photo tuned memristors. The variety of material systems used in the fabrication of memristors is comprehensively discussed.

**Keywords:** resistive switching, nanoscale, neuromorphic devices, hysteresis, computation, low dimensional materials, h-BN, MoS2, graphene, Memristor, neuromorphic computation

## **1. Introduction**

Continuous miniaturization of electronic devices has forced researchers to find newer ways of designing novel materials for nanoscale devices. Among the various devices needed in the electronic circuitry, memory devices represent an important category, with an increasing market. These components save the information in terms of "0" and "1". These two states are attributed to the low resistance and high resistance states of the memristive devices. Resistive switching memory devices represent the simplest group among various types of memory devices. In the simplest design of a resistive switching device, an active material (normally an oxide or a large band gap material in general) is sandwiched between two metal electrodes to form a Metal– Insulator–Metal (M-I-M) junction. When an external stimulus like an electric field is applied across the two metal electrodes, electronic conduction kicks-in at a voltage

specific to the active material. This trilayer system without the external stimulus will be in the high resistance state and can be switched using very low applied voltages. As the applied field strength reaches the breakdown strength of the active material, an insulator-to-metal transition takes place, inducing a low resistance state. The transition is characterized by a rapid increase in the current of 2–5 orders of magnitude depending on the material system considered. This typically happens because of the formation of conducting filaments parallel to the current flow, which is either due to a local phase transition, Joule heating or field-induced carrier generation. When these devices reach a nanometer size scale, electrons can tunnel through the active material (tunnel barrier), giving rise to a leakage current. To overcome this issue, researchers have been trying to replace the existing oxide materials (Si-based oxides) by newly designed materials with higher dielectric constant.

Resistive switching (RS) phenomena are described using various characteristics that define performance and device stability. These characteristics include volatile/non-volatile type, operating voltage, switching speed, ON/OFF ratio, endurance, and retention. The RS process is also classified as unipolar or bipolar based on the polarity of the operating voltage. Various intrinsic and extrinsic factors play an important role in the resistive switching characteristics. Based on the requirements of future technologies, ideal values of important characteristics should be the following: i) operating voltages <1 V, ii) power consumption 10 pJ per transition, iii) switching time or transition speed from one state to another below 10 ns, to name a few. A stable resistive switching device is expected to have endurance greater than 10<sup>9</sup> cycles, with data retention for more than 10 years. For higher storage density, the cell size of a unit (M-I-M) structure should be 576 nm2 with an ON/OFF ratio of 10<sup>6</sup> . However, the main constraint for these devices to be ready for applications is the identification of a single system with characteristic values equal to or near to these ideal values [1].

The hysteresis in the resistance of the switching device has been studied over a few decades now. The hysteresis behavior in resistance was first proposed by Leon Chua who coined the term "memristor", which is considered to be the fourth element in the classical electronics [2, 3]. It took almost two decades to establish the memristive effect experimentally [4]. The coupled solid-state electronic and ionic transport under the external stimuli was measured and established as a memristor based on Pt/TiO2/Pt device. Meanwhile, there are enough studies on devices showing the resistive switching behavior. For example, resistance switching based on ion migration [5], organic materials based non-volatile memory elements [6] and solid-state electrolyte [7] and thin film based resistive switching devices [8].

In general, the resistance switching of the device is characterized by an increase in the current level of 2–5 orders of magnitude. The conducting filament created during this transition may or may not be stable at room temperature. If the room temperature thermal energy is sufficient to disrupt this conducting filament, the low resistance state is not stable. In this scenario, a consistent memory performance will not be attained. While, if the conducting filament created during switching is stable at room temperature, the low resistance state will be stable at room temperature. Typically, the metal oxide-based memory devices are expected to be stable beyond 80°C for a given duration. When cyclic external stimulus is applied to such a device, a repeatable switching between high resistance state (HRS) to low resistance state (LRS) would result in hysteric current – voltage characteristics.

For the usage of resistive switching devices in information processing architectures, a high resistance state (HRS or OFF state) and a low resistance state (LRS or ON state) should be clearly defined. This should be followed by fast switching. To achieve this goal, extensive research has been carried out to optimize the design of the device structure, the materials used for the devices and size scale of the devices. Over the past two decades, since the discovery of graphene, many 2D materials have been also proposed/used for the fabrication of resistive switching devices.

The present chapter is divided into three main sections. Section 1 gives an introduction to the resistive switching process and its characteristics. Section 2, discusses the hysteresis in the electric field-induced resistive switching devices and different material systems used in the M-I-M structures. In Section 3, light-induced resistive switching is described. Optically-induced resistive switching will enhance the usage of such M-I-M devices in the field of optoelectronics and optical sensing. The last section, Section 4, is focused on the resistive switching devices used in neuromorphic devices and computation. The action of synapse – neuron pair in brain-inspired information processing is mimicked in the laboratory by fabricating resistive switching memory devices and architecture. At the end, Section 5 gives the brief conclusion of the chapter highlighting some of the objectives to be achieved in future nano-electronic technologies.

## **2. Electric field-induced hysteresis in resistive switching devices**

#### **2.1 Resistive switching mechanisms**

One of the common external stimuli used in electronic devices is the electric field. **Figure 1** (Adapted from [9]) shows an overview of how a typical resistive switching device and a combination of devices can be used as a memory architecture. **Figure 1(a)** shows a schematic diagram of a metal – insulator – metal (M-I-M) device. These individual memory devices can also be integrated into an architecture to process information, as shown in **Figure 1(b)**. Here, the resistance of the individual memory element can be set at desired values by applying voltage pulses. Extensive research has been carried out to understand the underlying mechanism of hysteretic resistive switching in these simple devices. Two main proposals to explain the resistive switching process are represented by: i) the formation of conduction path due to metallic filament as shown in **Figure 1(c)**. This is generally referred to as conducting bridge memory (CB) or electrochemical memory (ECM) or even sometimes referred to as programmable metallization (PM) device. ii) the presence of oxygen ion vacancies, which will form a conduction path due to the applied electric field, as shown in **Figure 1(d)**. In this case, the migration of oxygen ion vacancies is considered to be the main reason for the low resistance state.

In the first model shown in **Figure 1(c)**, the formation of a metallic filament across the active material causing a short path for electron transport is considered. This is termed conductive–bridge random access memory (CBRAM) and there are a lot of reports available in literature to support this argument [10, 11]. This phenomenon is significantly affected by the type of electrode material used in the devices. In the second model, **Figure 1(d)**, charged oxygen ion vacancies form a conducting bridge between the top and bottom electrodes of the device, thus resulting in a switching. This model is based on ions migration, where field-driven migration of oxygen ion vacancies or metallic ions occurs through the active material. Both processes have been explained using analytical and numerical models [12, 13]. The analytical model explains the phenomena occurring at the device level considering the circuit design

#### **Figure 1.**

*(a) Schematic diagram of a resistive switching device (M-I-M) consisting of two metallic electrodes separated by the switching material [9] (b) Combination of the devices in the memory architecture. (c) A typical metallic filament formed between the two electrodes giving a low resistance state. (d) The process-induced oxygen vacancies randomly distributed in the oxide material is depicted. These oxygen vacancies form a chain when a suitable voltage is applied to the device and the chain will act as a conduction path. Typical current – Voltage characteristics showing the hysteresis behavior depicting the switching process are shown in (e) and (f). The unipolar switching is shown in (e). Here, a forming process, rupture of the filament during the RESET process and filament formation during the SET process is shown. In (f) a bipolar switching is shown [9]. In this case, the electrochemical migration of oxygen ions is responsible for the hysteric current–voltage behavior of the device. (g) Typical current – Voltage characteristics of Ag-AgGeSe-Ag switching device. The insets a to D depict the various stages of the switching cycle.*

parameters. The numerical models are based on the parameters affecting the operation of the device, such as the type and shape of the bias voltage, and compliance current. The compliance current is set to limit the current flowing through the device, such that the device can be operated successively for many cycles. Without current compliance, the applied voltage might create a complete dielectric breakdown and the device might not be able to get back to the high resistance state. As of now, the most widely-accepted model explains the switching process via trap-assisted tunneling mechanism (TAT) [14, 15]. In this case, the tunneling of electrons occurs via the traps generated or recombined with certain probabilities depending on the local electric field. **Figure 1(e)** and **(f)** show the typical hysteretic behavior of resistance switching in two types of devices. When the voltage is ramped across the device, the device switches from a high resistance state (HRS) to a low resistance state (LRS) at a welldefined voltage, with a clear distinction between the two resistance states. The critical voltage at which this transition occurs depends on the thickness and dielectric constant of the active material present in the device. The fact that the current – voltage characteristics show hysteresis implies that these structures can be used as memories devices to store information. The advantage of such devices is that the memory can be erased by applying a voltage in the opposite direction, which switches the device back to its original high resistance state.

Initially, when the applied voltage is zero, the device is in the high resistance state (OFF) and the switching material is in its pristine state (**Figure 1(g)**). When sufficiently large voltage is applied, the device turns ON (SET process). Here, a stable metallic filament grows through the switching layer by means of anodic dissolution of metal, as shown in the inset A of **Figure 1(g)**. Further application of higher voltages will strengthen this metallic filament and a stable ON state (low resistance) is retained. This is due to the migration of the metallic ions generated and the crystallization of the metallic filament. When a sufficiently large bias in the reverse direction is applied, the formed metallic filament dissolves (inset C) resulting in low current passing through the device (HRS), which results in the RESET state of the device. This forming and breaking of the metallic filament is considered as electrochemical metallization and is found to be the main cause of the memristive effect [16]. In general, the electrochemically active metals like Ag and Cu are used to study the electrochemical metallization phenomena in devices.

The Valence Change Mechanism (VCM Type) is attributed to the switching mechanism in devices based on binary oxides or even multinary oxides. In this case, the electrochemical dissolution of the metallic electrode does not occur. As early as in 1960's, studies were carried out on Nb-Nb2O5-B and Nb-Nb2O5-In trilayer structures [17], and later in 1990's, mostly manganates, titanates and zirconates have been studied. The trilayer structures based on these materials exhibited bipolar switching [8, 18]. Since the electrode metallization does not occur, a SET procedure is always needed before the device shows a bipolar switching. Several mechanisms have been put forward to explain the mechanism of resistive switching in this case. The most favored mechanism is the charge-trap model. Here, the injected charges are trapped at the site of defects within the insulating material of the device [16]. In the case of strongly correlated electron systems, which undergo insulator-to-metal transition (IMT), the charge injection acts as doping, resulting in the switching of the resistance state of the insulator. Further, there are extensive reports on the anion-assisted switching, mostly based on the oxygen ion vacancies, which are more mobile than the metal cations. The formation and dissolution of the conduction path due to oxygen vacancies have been proposed as a reason for the resistive switching. The created anion vacancies will affect the charge state of the metal cations, and thus, this generic phenomenon is normally referred to as valence change memory (VCM).

#### **2.2 Resistive switching characteristics**

The ability of resistive switching devices to retain a certain resistance state (HRS or LRS) even after the application of a voltage over a period of time makes them nonvolatile. Thus, a very low voltage (lower than the operating voltage) is required to read, leading to the low power consumption of such devices. Instead, for volatile devices, the write and read voltages are of equal weight and the device is brought back to its original state, upon removing the power supply. Thus, for random access memory technology, non-volatility is essential. These non-volatile resistive switching type devices are also proposed for neuromorphic computing architecture, as electronic synaptic devices. For such computing architectures, there are two types of rules to be implemented, short-term plasticity (STP) and long-term plasticity (LTP).

STP can be achieved either by using volatile devices or complex architectures based on non-volatile devices [2]. This has encouraged several research groups to develop resistive switching devices showcasing volatile behavior. Shi et al. [19] were the first to demonstrate the coexistence of volatile and non-volatile behavior in resistive switching devices based on hexagonal-Boron Nitride (h-BN). By means of modulating the compliance current, the coexistence of volatile and non-volatile characteristics is studied. It was also due to the inherent chemical stability of the material that it exhibited a controlled dielectric breakdown. The h-BN device was able to completely recover the resistance state upon removal of the voltage supply. The hysteresis curves for h-BN devices are shown in **Figure 2**. A schematic diagram of the Au/Ti/h-BN/Cu switching device is shown in **Figure 2(a)**. Resistive switching curves indicate volatile behavior as shown in **Figure 2(b)**. The volatile behavior can be seen on both sides of the voltage cycle. The device regains its high resistance state (HRS) when the voltage is cycled via 0 V - Vmax – 0 V. Because of the chemical and thermal stability of h-BN, the soft breakdown occurring can be completely recovered once the electrical bias is removed. The complete recovery of the high resistance state can be achieved on both bias polarities. **Figure 2(c)** and **(d)** show the volatile switching characteristics with the compliance current values of 1 μA and 10 μA respectively. Even though large scatter is observed in the switching voltages in the lower compliance regime, the hysteresis can be clearly seen, indicating that the device can be used as a memory device. It can also be observed that the voltage range at which the device can be operated as a memory element is also larger when a higher compliance current is used. This can be due to the unstable conductive filaments (CF) being formed when the device is operated with a lower current compliance value compared to more stable CF, and thus wider hysteresis, when higher current compliance is used [9]. Further, it is interesting to notice that non-volatility can be activated by setting a higher compliance current. This is clearly shown in **Figure 2(e)** and **(f)** for compliance currents of 500 μA and 3 mA, respectively. **Figure 2(e)** shows the non-volatile behavior when a positive SET voltage cycle is applied, and **Figure 2(f)** shows the non-volatile characteristics when a negative SET voltage cycle is applied. Here, also the area of the hysteresis is different for different SET voltage cycles applied. The switching characteristics with negative SET cycle seem to show a sharp transition from HRS to LRS state.

It is important to note that the complete recovery of the high resistance state in the case of volatile switching is shown in the top row. This is unlike in the case of transition metal oxide switching devices. Even though h-BN shows extreme chemical stability, together with a reliable device performance, there are still many "unknown" parameters that must be understood in detail when 2D materials are used in the devices. Some of the 'unknowns' are highlighted in the recent work by Pey et al. [20] as indicated in **Table 1**.

Most resistive switching devices are based on thin films of transition metal oxides (TMO) as active elements in M-I-M structures. A large number of systems exhibiting resistive switching characteristics have been reported in literature. As mentioned earlier, there is a variety of resistive switching characteristics for this simple structure of the device. For a decade or so, there has been a common consensus on the phenomenology of resistive switching in these devices. Switching phenomena can be classified into unipolar and bipolar memory effects. One can term this effect as "switching modes" in the devices. Extensive research in 2D materials has extended the horizon of unipolar and bipolar effects observed in a variety of 2D materials.

Both unipolar and bipolar resistive switching processes have been observed over the years. For unipolar resistive switching devices, a voltage with the same polarity is applied for both SET and RESET process. This means that the memory state of the

*Resistive Switching and Hysteresis Phenomena at Nanoscale DOI: http://dx.doi.org/10.5772/intechopen.101500*

#### **Figure 2.**

*The two types of resistive switching observed in Au/Ti/h-BN/Cu based resistive switching devices [19]. (a) Schematic diagram of Au/Ti/h-BN/Cu switching device (b) volatile resistive switching characteristics in both polarities. On both sides, the device goes back to its HRS state when the voltage is cycled through a full cycle. (c) the volatile resistive switching of the device with a compliance current set at 1 μA. Clear hysteresis of the current – Voltage characteristics can be observed. (d) Similar volatile resistive switching characteristics of the device with compliance current of 10 μA. Higher compliance current setting seems to stabilize the hysteresis with smaller deviation in switching voltage compared to the lower compliance. (e) the non-volatile switching characteristics of the same device. In this case, a negative voltage cycle is applied as a SET cycle for the device. (f) the nonvolatile switching characteristics with positive SET cycle. In both cases of positive and negative SET cycle applied, a clear switching characteristic is achieved.*

device can be switched by successive application of biases with same or opposite polarity. This is because the devices are primarily governed by thermochemical mechanisms, such as Joule heating effects in the formation and rupture of conductive

#### **Unknowns in breakdown phenomena in 2D materials** [20]

1. Type and charge state of vacancy defects causing breakdown.

2. Validity of percolation model for the area and thickness scaling

3. Origin of defect clustering – intrinsic or extrinsic or both?

4.What are the activation and relaxation energies of the defects?

5. Role and competition between charge trapping and SILC in h-BN.

6. Size and shape of percolation path

7. Role of metal – h-BN interface on the breakdown kinetics

8. Role of self-heating and its impact on the post-breakdown behavior

9. Role of covalent B-N bonds and Van der Waal forces on percolation

10.Which extrapolation model could be used for time dependent breakdown lifetime estimation?

11. Overall conduction path propagation in layered materials

#### **Table 1.**

*List of issues which are still to be understood in detail in the case of 2-D materials, as listed in ref. 20. The 'unknowns' listed in this table will be a key research topic for the next decade when large band gap 2-D materials will be considered.*

filaments. Meanwhile, the bipolar resistive switching process is associated with electrochemical mechanisms, which require voltage of opposite polarity to switch between the memory states. These distinct behaviors of polarity (unipolar/bipolar) and volatility (volatile/non-volatile), allow identifying suitable applications, where the efficiency of the devices can be exploited.

Interestingly, in some specific cases, the mode of resistive switching is interchangeable. In the case of a bilayer stack of Ga2O3/Cu2O grown on ITO substrates such interchangeable switching was observed. The bipolar switching was attributed to the existence of the traps in the interface and the unipolar switching was ascribed to the oxygen ion vacancies accumulating at the interface [21]. Specific systems have been designed to showcase the coexistence of unipolar and bipolar phenomena. Some of these devices exhibit irreversible transitions from one switching mode to the other (unipolar to bipolar), which are of less use compared to the reversible transition between these modes.

Also, the coexistence of two switching modes in a single device, gives more degrees of freedom in controlling the geometry/composition of conductive filaments, and eventually leads to development of multilevel resistive switching memories [21, 22]. Zhao et al. [22] demonstrated a reversible transition between the two switching modes in Ag/MoS2/Au resistive switching device, as shown in **Figure 3**. In this particular case, the devices were fabricated on a flexible polyethylene terephthalate (PET) substrate, as shown in **Figure 3(b)**. Bipolar (**Figure 3(c)**) and unipolar (**Figure 3(d)**) switching can be clearly seen in the device. Notice the polarity of the applied SET process. In the case of bipolar switching, the SET process is carried out by applying a positive voltage, and the switching can be observed on both sides of the applied bias. In the case of unipolar switching, the SET voltage cycle and the switching cycle is observed in the negative polarity. Further, these two modes of switching can be tuned by changing the voltage polarity (see **Figure 3(e)**). The bipolar resistance state mode was observed by the application of +3 V for the SET process in the positive direction. The unipolar-resistance state mode was observed by supplying a negative write voltage of -3 V, as shown in **Figure 3(g)** and **(h)**. In this case, the bipolar state was due to the migration of the silver ions (from the electrode) through MoS2. Meanwhile, in the case of the unipolar state, the conduction paths through the sulfur ions (S) were

*Resistive Switching and Hysteresis Phenomena at Nanoscale DOI: http://dx.doi.org/10.5772/intechopen.101500*

#### **Figure 3.**

*Flexible resistive switching device. (a) Schematic diagram of the Ag/MoS2/Au resistive switching device [22]. (b) The flexible PET substrate on which the Ag/MoS2/Au switching device is fabricated. (c) Bipolar switching characteristics (black) of MoS2 device with the positive forming voltage cycle (red). Voltage at which the transition to low resistance state (indicated by SET) is clearly defined. A gradual change into high resistance state can be seen in the negative bias region (RESET). (d) a unipolar switching characteristic of MoS2-based devices. Here, the forming voltage cycle in the switching cycle is in the same polarity of the applied bias voltage. The two switching modes can be altered by changing the voltage polarity as shown in (e). The low resistance state of bipolar (black) and unipolar (red) state has a completely different behavior for positive voltages as shown in (f). The multilevel operation of such device is shown in (g) and (h).*

causing the resistive switching. The memory capacity was controlled by modulating the compliance current in the device.

Such modulation of the memory capacity of resistive switching devices was also reported for resistive switching devices based on hafnium oxide [23] and assembled black phosphorus quantum dots (BPQD) [24]. The self-assembled BPQD sandwiched between two poly(methyl methacrylate) (PMMA) polymer layers, is used as a switching layer. This heterostructure is sandwiched between aluminum (Al) electrodes. The switching characteristics are shown in **Figure 4** in detail. In particular, in **Figure 4(a)**, one can notice that BPQD shows a wide memory window, undergoing a HRS to LRS transition at 2.9 V. For bias voltages lower than this critical voltage, the space charge limited conduction dominates the carrier transport. The hysteresis and the switching behavior are maintained for different BPQD film thickness, as shown in **Figure 4(b)**. These devices exhibit exquisite resistive switching curves. The switching voltage for these devices decreases with an increase in BPQD film thickness. This device structure also showed an extremely high ON/OFF ratio (in the order of 10<sup>7</sup> ) compared to MoS2-, Graphene-, and Black Phosphorus (BP) nanosheets-based

#### **Figure 4.**

*Resistive switching curves of black phosphorus quantum dot (BPQD) based switching devices [24]. (a) A clear bipolar switching can be seen with bistable resistance state. (b) The ON/OFF ratio can be controlled by modifying the compliance current. (c) The compliance current dependent switching characteristics is shown. (d) The statistics of ON/OFF ratio is seen to depend on the compliance current as shown.*

resistive switching devices. For achieving stable multilevel resistive switching, the compliance current in the BPQD device was varied in the range of 10 A<sup>1</sup> A to 10 A<sup>4</sup> A. This has in turn a direct effect on the LRS and HRS current values and the switching voltages, as noticeable in **Figure 4(c)**. The device also demonstrated tunable resistive switching properties; the ON/OFF ratio depended on the compliance current, as shown in **Figure 4(d)**.

On one hand, materials used for the memory devices form the heart of information processing; however, the device optimization is also an extremely important aspect of nanoelectronics. One of the important parameters in this sense is the switching speed of the memory device. There are reports that illustrate how to determine the switching speed of resistive switching devices. For example, a resistive switching device based on tantalum oxide (Ta2O5) switches with an ultrafast speed of around 10 ps at a bias voltage of 3 V [25]. By varying the voltage amplitude, multi-state resistive switching was achieved. The ultrafast performance of this device was demonstrated by using a coplanar waveguide structure of the device with pulsed voltage. The drawback of such device was that the amplitude of the pulsed voltage was extremely high (>3 V). However, at present, the switching speed at reliable voltages (<1 V) is limited by the experimental measurement setup [26].

One of the other important characteristics of resistive switching devices is the operating voltage at which the transition from the high resistance state (HRS) to low resistance state (LRS) takes place. This is expected to be as low as possible, for efficient low power synaptic application in neuromorphic computing architectures. The voltage threshold is dependent on several factors, including the active material between the two metal electrodes, the distance between the two metal electrodes, and the material of the two electrodes. The MoS2/MoOx heterostructure can be operated at voltages as low as 0.1 V [27]. The device exhibited symmetric bipolar resistive switching curves with an ON/OFF ratio of 106 . Such devices operating at exceptionally low voltages with a wide hysteresis can be particularly useful for high density storage systems. The resistive switching performance of a device solely based on solution processed non-oxidized MoS2, displayed linear current - voltage curves in disparity with the heterostructure-based devices. The heterostructure-based device also displayed moderate stability with an endurance of <sup>10</sup><sup>5</sup> cycles. Further, VO2 based nano resistive switches consuming only 4.2 fJ of energy per switching are fabricated by a novel approach [28], whereby VO2 nanocrystals are embedded in conductive Si tips with an effective lateral size of about 100 nm, after 30mins of synthesis. More importantly, at room temperature, the nanocrystal-based VO2 devices showed a switching from HRS to LRS at 0.1 V. Additionally, the device showed a high stability of cyclic switching process with endurance longer than 10<sup>11</sup> cycles. It was clear that such enhanced results were obtained only because of the device geometry, while the VO2 thin films of 300 nm size grown on silicon substrate had an operating voltage of nearly 6 V at room temperature.

As mentioned earlier, the stability of a resistive switching device is characterized by endurance and retention. Endurance is the measure of the maximum number of stable switching cycles the device can perform between two or more resistive states without progressive breakdown of the device. With the overgrowing demand of modern technologies with dynamic applications, it is necessary for such electronic devices to showcase performance stability over a period of time. Several factors such as (i) structural stability of the resistive switching device, (ii) undesired electrochemical reactions between the electrode and the resistive switching materials, (iii) progressive growth of conductive filament, can lead to higher number of endurance

cycles. For a reliable resistive switching device, the ideal endurance value should be >10<sup>9</sup> cycles. There have been few studies in literature that have reported such high endurance values. In a recent publication, Huang et al. [29] reported a bilayer aluminum oxide-based resistive switching devices (W/AlOx/Al2O3/Pt) with high endurance cycles from cryogenic to high temperatures (10<sup>7</sup> at 100 K, 10<sup>10</sup> at 298 K and 10<sup>8</sup> at 400 K). Here, an oxygen-deficient layer of AlOx was stacked upon a stoichiometric Al2O3 layer between tungsten (W) and platinum (Pt) as top and bottom electrodes respectively. This homogeneous bilayer stacking of oxygen poor/rich aluminum oxide layers resulted in controlled activity of oxygen vacancies for all resistive states. Accompanied with these high endurance values, this device exhibited ON/OFF ratio of 10<sup>3</sup> at low switching voltages, with fast switching speed of 28 ns. Engineering of endurance cycles for metal oxide-based RS devices was also projected by Wiefels et al. [30]. They showed that by utilizing ohmic electrodes it is possible to enhance endurance of the resistive switching device by an order of 1–2. Ohmic electrode metals act as a high potential barrier for generation of oxygen defects at metal electrode-switching material interface. This limits excessive formation/accumulation of oxygen defects and uncontrolled filament growth between the top and bottom electrodes.

Data stability is a key aspect for memory storage, synapses of neural network and RRAM applications of resistive switching devices. Data stability is checked by studying the ability of a switching device to retain its discrete resistance states (LRS and HRS) with appreciative ON/OFF ratio after SET and RESET transitions over a period of time. It is essential for the perseverance of the stored data and to avoid fluctuations in the persistent read and write processes of the device. Reliable non-volatile resistive switching devices must have retention value of >10 years at functioning temperature of 85°C. However, this retention value is underachieved by the majority of switching devices, primarily due to the thermodynamical instability of the material and inconsistent formation/rupture of conductive filaments formed during the SET/RESET processes. Nevertheless, a trilayer (Al2O3/HfO2/Al2O3) oxide-based device showed an excellent reliability with retention of >10 years at a temperature of 85°C [31].

### **2.3 Effect of external perturbations on RS characteristics**

The characteristic results discussed until now are all dependent on either the device structure or the materials used for the active layer and for the electrodes. However, environmental effects also play a role in the switching performance of these devices. Thus, to understand the robustness of resistive switching devices, it is important to test their performance under various extreme conditions. Several reports can be found in the literature till date, where resistive switching of different materials is observed to be influenced by variation of temperature [32], ambient pressure [33], humidity [34] and light illumination [35]. The possibility of remotely controlling a resistive switching device via an external magnetic field has been also reported in a recent study [36]. These external perturbations affect the course of hysteresis of the device, without causing a hindrance to the switching from HRS to LRS. This explicit dependence of the resistive switching characteristics on external stimuli can also pave way for novel integrated technologies. It is also important to note that this dependence on external environmental effects is reversible, i.e., the devices are observed to showcase the original characteristics when returned to normal conditions.

Another material which is extensively studied is HfO2. The oxides of hafnium and cerium are mostly studied from the point of view of replacing the silicon-based oxides in transistor technology. HfO2-based resistive switching devices at nanoscale have

## *Resistive Switching and Hysteresis Phenomena at Nanoscale DOI: http://dx.doi.org/10.5772/intechopen.101500*

been extensively studied. The resistive switching as a function of temperature for HfO2-based resistive switching devices was investigated in a wide range of temperature from 213 to 413 K [32]. A stable bipolar resistive switching was measured at all the temperatures considered. The OFF state current levels of the device increased gradually with increasing temperature. This behavior of the device in OFF state can be attributed to the semiconductor behavior (resistance decreases with increase in temperature). In contrast to that, the device was characterized by a metallic-type behavior in ON state, where the current levels decreased as temperature increased. Layered MoOx/MoS2 resistive switching devices showed temperature-dependent resistive switching with well-defined hysteresis in the current – voltage characteristics [27]. The threshold voltage of switching shows an exponential dependence on the voltage sweep rate. Here, the MoOx is oxygen-deficient and anionic motion results in the resistance switching. Resistive switching characteristics of MoOx-based devices were studied in the temperature range from 300 to 343 K with jumps of 10 K. Interestingly, both the HfO2- and MoOx-based devices showcased similar tuning of the resistive switching with respect to temperature variations. The SET and RESET voltages are observed to decrease with increasing temperature along with an increase in the OFFstate current levels. The hysteresis gradually narrows with increasing temperature, limiting the operating temperature range of such devices.

Importantly, these devices still exhibited stable bipolar non-volatile resistive switching at elevated temperatures. Researchers have been trying to understand the resistive switching devices with increasingly smaller sizes, ultimately reaching atomic scale. For example, an interesting work on atomic scale switching was recently reported in a device based on a solid polymer electrolyte (SPE) comprising a blend of polyethylene oxide (PEO) and AgClO4 [33]. The atomic switching, operating even at elevated temperature, originates from the mobile Ag ions. The report indicated that the operating voltage reduces with temperature and is independent of external conditions, such as air or vacuum. These atomic scale devices are based on electrochemical reactions and ion transport in the electrolyte. Fascinatingly, the devices exhibit reverse reliance when varying temperature in vacuum and air, i.e., the effect of temperature on resistive switching of these devices was inconsistent under air and vacuum. The magnitude of SET and RESET voltages reduced with temperature in the device containing SPE, while the PEO-based device showed an increase in the SET and RESET voltages with temperature. Also, the hysteresis curves appear smooth for measurements performed in vacuum, compared to the abrupt SET and RESET process of the devices tested in air. Additionally, in these devices the change in width of the hysteresis was quite distinct, as shown in **Figure 5(a)**. The hysteresis of the red curve obtained at lower temperature (i.e., 40°C) is quite large. As the temperature is increased, a reduction in the hysteresis can be seen, even though a clear resistance switching is observed. In this low temperature regime, the threshold voltage at which resistance switching occurs is higher than 1 V. By increasing temperature from room temperature, the threshold voltage drastically reduced (**Figure 5(b)**). As indicated in the schematic inset of **Figure 5(b)**, the switching behavior is attributed to the Ag ions dissolving in the SPE matrix, thus forming a conduction path leading to a low resistance state. As the temperature is increased up to 60°C, a clear resistance switching can be seen, with a reduction of the hysteresis width with increasing temperature. A similar temperature-dependent hysteresis can be seen in a simple, lateral metal-VO2 metal device, as shown in **Figure 5(d)**. The switching voltage reduced drastically with temperature and still shows a sharp transition into the low resistance state [37]. This reduction in the threshold voltage can be seen when the device is operated in ambient

#### **Figure 5.**

*Resistance switching in Ag/solid polymer electrolyte (SPE)/Pt -based atomic switches [33]. (a) A clear hysteric switching is observed at low temperatures with threshold voltages in the range 1 V–3 V for the temperature indicated. (b) The resistance switching at higher temperature with drastic reduction in the threshold voltages. Both (a) and (b) are measured in vacuum, while the switching characteristics depicted in (c) are measured in ambient conditions. Again, the threshold voltages are higher than 1 V, while the area of the hysteresis reduces with increasing temperature. (d) A similar temperature dependent resistance switching seen in VO2based device. The area of hysteresis reduces as the temperature is increased. The shape of the switching characteristics is typical for electric field-induced insulator-to-metal transition in VO2-based devices [37].*

conditions. Here, the threshold voltage is preceded by a gradual change in the resistance, differently from the case of vacuum measurements. Similar temperature dependence is also seen in the case of a Cu/Ta2O5/Pt atomic switch [38].

Inspired by these temperature-dependent studies, humidity-dependent resistive switching studies for multilayer VO2 devices [34], at room temperature, have been reported recently. Humidity is present everywhere and strongly affects the performance of electronic devices, especially at the nanoscale. In the VO2-based switching devices the operating voltage is exponentially reduced with increasing humidity. An increase in adsorption of water molecules at higher humidity levels, eventually assisting the material by increasing the conductivity, required relatively low voltage to switch from HRS to LRS. Once again, the devices exhibited bipolar resistive switching at all humidity levels (11–90% RH) with a decrease in the width of the hysteresis curve at ascending relative humidity. Such strong dependence of the resistive switching devices on relative humidity can be exploited in developing novel robust humidity sensors.

The dependence of resistive switching on the relative humidity levels has been observed in other ECM devices containing SrTiO3, CeO2, TiO2, BaTiO3, SnO2, ZrO2: Y2O3, especially when the oxide material is deposited using physical vapor deposition techniques [39–43]. This process will result in a porous oxide switching layer, which will enable the incorporation of hydroxyl ions. This is detrimental if the oxide material is used in transistor designs where a gate dielectric (an oxide material) is used. Due to the adsorption of water molecules, the operating parameters will be affected. The temperature variation in the operating conditions can affect the filament formation (SET process) and the dissolution of the filament (RESET process) [44, 45]. Various mechanisms have been proposed for oxidation of the copper electrodes used in the Cu/Ta2O5/Pt structures [44]. The device characteristics depend on how the Cu ion migrates in the Ta2O5 material. Several rate limiting mechanisms have been proposed. Firstly, the copper can get ionized at the oxide interface due to the reduction of the tantalum oxide or copper can get ionized via interaction with ambient gasses like O2. Further exposure to H2O molecules can result in the formation of CuO, Cu2O and also Cu3O2 at the oxide interface. These oxides of copper will form the sources of metal ions, which will then migrate through the oxide layer affecting the resistance state of the device. It should be further noted that during the initial stages adsorption of water molecules on VO2 and Ta2O5 surface results in a hydrogen bond network.

Another external stimulus used for manipulating the resistance states of a memristor device is optical light. First of its kind, a graphene oxide-based optical memristor device showed a repeatable resistive switching under ultraviolet (UV) light [35]. Two kinds of devices, lateral and transverse, were developed using graphene oxide (GO). The ON/ OFF ratio was found to increase with the graphene oxide thickness. In the transverse type device, GO sheets with effective thickness of 500 nm was sandwiched between Indium Tin Oxide (ITO) and thermally deposited Ag electrodes; in the lateral devices, the GO layer was drop-casted on interdigitated ITO electrodes with a large effective area. These devices exhibited solely reversible characteristic changes under illumination of long wavelengths of light, and both reversible and irreversible changes in the properties under shorter wavelength. Although narrow bipolar resistive switching was observed in the lateral devices, there was an increase in the current value when the device was illuminated by UV light. The transverse devices offered a wider hysteresis window compared to the lateral devices. However, the hysteresis narrowed under the illumination of UV light and returned to its original state in dark mode. The reversible changes were attributed to photo conductance, whereas irreversible effects are due to the reduction of GO sheets.

Another exciting report was focused on a remotely engineered TiO2-based resistive switching device using an external magnetic field [36]. The Ag/TiO2/FTO device showed stable, repeatable resistive switching characteristics, as shown in **Figure 6(b)**. The surprising effect is that the switching process can be controlled by using an external magnetic field. These effects were attributed to residual Lorentz forces, enabling the remote control of resistance states. An exponentially increasing relationship was defined between the SET voltage and the external magnetic field, as seen in the inset of **Figure 6(c)**. The device did not show any degradation, even after repeated resistive switching cycles in presence of magnetic field. It showed a multilevel character under the application of different voltage pulses of 50 μs width under a magnetic field in the range of 0 –2300 Oe, as shown in **Figure 6(d)**.

## **3. Optically-induced resistive switching devices**

One of the novel ways of making a device switch between stable resistance states is by irradiation of light of suitable wavelength. It has attracted considerable attention

#### **Figure 6.**

*The magnetic field effect on Ag/TiO2/FTO resistive switching device [36]. (a) A schematic diagram of the experimental set up to study the effect of magnetic field on the resistive switching. The electric field and magnetic field are perpendicular to each other. (b) A typical resistive switching characteristics measured. The device shows a reliable ON and OFF state. (c) The effect of external magnetic field on the switching voltage. The threshold voltage increases with the magnetic field due to residual Lorentz force on the charge carriers. (d) Multilevel resistance states of the device at various voltage pulses indicted.*

from the scientific community due to its additional functionalities over the traditional ways of resistive switching. Light of desirable wavelength is capable to induce photogenerated charge carriers in photo-sensitive materials, which can modulate the conductivity of the material. Further, the switching between distinct and stable resistance states or achieving desired programming modes can be controlled by attuning the energy of the photons, i.e., regulating the wavelength of the irradiated light, duration of the illumination, as well as the dark modes and the number of optical pulses for the write and erase process. Compared to the aggressiveness of the electric field-induced resistive switching process, where there is possibility for the devices to undergo an irreversible dielectric breakdown under high electric fields, the optical pulse approach is a much gentler programming procedure and would disregard the possibility of permanently damaging the memristive properties of the device by converting it to an Ohmic material during the switching process. The light-induced resistive switching phenomena would also diminish the occurrence of crosstalk in complex integrated technologies, especially the neuromorphic computing architectures inspired by human brain (**Figure 7**) [46].

#### **Figure 7.**

*Optically tunable resistive switching crossbar array. The input and output lines (yellow and blue strips) are separated by the switching material, which is tuned optically. Each trilayer structure is shown on the right. The two metal electrodes are separated by the active material which can absorb light. The absorption of light photons will generate charge carriers inside the material, forming a conductive bridge, thus changing the resistance state of the device. (Reproduced from [46].)*

Apart from that, the ability of the optically-induced resistive switching devices to store information when the device switches between stable resistance states with discriminate resistance values, mainly high resistance state (HRS) and the low resistance state (LRS), makes such devices an integral part of the ultra-modern memory technologies. For such photonic memories, the devices are often perceived to encounter a light-induced irreversible resistive switching. This irreversible resistive switching technique can be used as an advantage, permitting the device to function as a "write once read many times (WORM)" type of memory [47]. The irreversible resistive switching would also enhance the encryption of the stored data, as the stored memory/data can be erased solely by the application of suitable external stimulus. These, devices can be possibly switched back to the original HRS by applying suitable biased voltages of appropriate magnitude.

Multifunctionality of a nanodevice is one of the important aspects of the upcoming technologies. For this, hybrid resistive switching devices based on the combined effects of the voltage and optical pulse stimulation have been reported. These devices have displayed enhanced switching characteristics, such as ultra-low SET and RESET voltages, compliance free working devices, and multilevel resistive switching with stable intermediate resistive states. These advanced abilities pave the way for integrated optoelectronic devices, such as light emitting diodes, optical sensors, and photovoltaics.

The selection of wavelength of the optical pulse for inducing resistive switching in a particular material is selected depending upon the bandgap of the material. This is to allow the material to absorb the irradiating photons, which can excite or induce charge carriers in the material. The photogenerated charge carriers assist the material in modulating the active material's conductivity and can be attributed to changes in the resistive switching performance of the device. The choice of the top electrode material can also play a role in these conduction mechanisms, e.g., transparent electrode materials would allow transmission of the photons directly to the active material. Different device structures developed using different oxides, and other 2D materials [47, 48] with corresponding triggering wavelength are tabulated in **Table 2**.


#### **Table 2.**

*A list of 2D materials used in optically tunable resistive switching devices. Column 2 represents the corresponding wavelength or optical power required to induce resistive switching.*

### *Resistive Switching and Hysteresis Phenomena at Nanoscale DOI: http://dx.doi.org/10.5772/intechopen.101500*

Several photosensitive semiconducting materials such as oxides, two-dimensional materials, organic materials, and perovskites have been reported as active materials in optical resistive switching devices [48]. These materials have showed both pure optically-induced resistive switching and reconfigurability of the resistive states by both optical and electrical signals. A simple and straightforward ultraviolet (UV) induced resistive switching was reported for pristine metal oxide switching device treated with PEDOT:PSS [47]. The polymer treatment on the top electrode was known to increase the UV sensitivity of the device. The UV illumination and dark mode treatment cyclically switched the device between steady resistance states. The wavelength-dependent study revealed best results for UV light of 300 nm. The difference between the initial and final resistance state was 300 Ω. Though the device did not require an additional voltage stimulus for triggering the switching process, a negatively biased voltage signal was needed to bring back the device to the initial resistance state. Another important example of optoelectronic resistive switching devices was demonstrated based upon zinc oxide nanorods [52]. Relying on the desorption of oxygen defects present in the material due to optical illumination, the device showed good switching performance with a photosensitivity of 7.75. The device displays WORM-type memory behavior, retaining the ON state once the illumination is disrupted after forward scanning, as can be observed in **Figure 8(b)**. The switching performance of the device is persistent with optical stimulation, and when the light illumination is cut-off, the switching property also disappears. This behavior is attributed to the absence of photogenerated charge carriers and complete recovery of chemisorbed oxygen vacancies in dark mode.

The diverse electronic and optical properties of 2D materials allow tuning the resistive switching behavior of these devices by a broad spectrum of electromagnetic wavelengths. An important example of white light-induced optical memristor is based on MoS2 nanorods [50]. A clear bipolar resistive switching with a clearly defined resistance level can be seen in **Figure 9**. The schematic of MoS2 nanorods based memristor is shown in **Figure 9(a)**. Vertically aligned MoS2 nanorods are sandwiched between copper and platinum electrodes, where a white light is irradiated on the top electrodes (Copper electrodes) (**Figure 9(a)**). The switching device shows a reduction in the SET and RESET voltage due to the absorption of white light as shown in

#### **Figure 8.**

*Light-assisted resistive switching in solution-processed zinc oxide (ZnO) nanorods [52]. (a) Stable bipolar resistive switching is observed under optical illumination of (halogen lamp). Write once read many (WORM) type of behavior shown in (b). The cyclic switching behavior of the device being persistent with the light illumination.*

#### **Figure 9.**

*A typical MoS2 nanorod memristor device that is switchable using optical light [50] (a) The vertically aligned MoS2 nanorods are sandwiched between the platinum and copper electrodes. The MoS2 nanorods undergo resistive switching under the illumination of white light. (b) Resistive switching curves under dark state and white light illumination. The electroforming under the illumination also occurs at lower voltages as shown in the inset of (b). The typical hysteric resistive switching also shows a strong dependence of light illumination.*

**Figure 9(b)**. The absorbed white light introduces a conduction path in the MoS2 via sulfur vacancies. Further, the SET voltage reduces with the intensity of white light. This gives an added advantage to tune the SET voltage at a given light intensity and correspondingly the device can be used for information storage. The ON/OFF ratio of <sup>10</sup><sup>3</sup> was also maintained over 1500 cycles, implying an excellent stability of the device.

Interestingly, even though graphene displays a zero-band gap, the resistive switching property of graphene can be controlled with light, from noticeably short ultraviolet to long microwave wavelengths; however, due to its semi-metallic nature, graphene is more suitable for electrode materials. An example of tunable resistive switching device based on Rhenium di-Selenide where monolayer graphene (G) with gold (Au) contacts is used as bottom electrode was recently reported [51]. **Figure 10(a)** shows the switching characteristics with gate voltage. Without any gate voltage, the device undergoes a sharp transition from HRS to LRS at +2.3 V (shown in green curve). When the voltage polarity is switched, the device undergoes a transition from LRS to HRS at around 2 V. This switching is attributed to the formation and rupture of Cu filament. The resistive switching properties of the device are engineered using the gate voltage, which consequently varies the Schottky barrier height at the ReSe2/ Graphene junction. This variation in barrier height brings about changes in the ON/OFF ratio and operating voltages of the resistive switching device. Further considerable reduction in these values is observed when a deep UV light of wavelength 220 nm is irradiated on the device, as shown in **Figure 10(a)** and **(b)**.

Interesting results were observed when the superconducting Niobium (Nb) thin films were studied for light-assisted resistive switching [49]. At room temperature, Nb thin films showing metallic behavior under normal conditions, exhibited resistive switching behavior when exposed to light from visible to near infrared wavelengths. Unlike the conventional photosensitive devices, this device switched to high resistance state from the initial resistance state upon being exposed to light, as shown in **Figure 10(c)** and **(d)**. Further, a study of the interaction between superconductivity and photoconductivity was also reported in this work. The light-assisted switching

*Resistive Switching and Hysteresis Phenomena at Nanoscale DOI: http://dx.doi.org/10.5772/intechopen.101500*

#### **Figure 10.**

*Light induced resistive switching in Cu/ReSe2/graphene device. (a) Various resistive switching characteristics with gate voltage. Without any gate voltage, switching occurs at 2.3 V from HRS state to LRS (SET process shown in green). Similarly, when the voltage polarity is changed, the RESET process occurs where the device switches from LR to HRS [51]. (b) Result of the switching voltages in dark and under illumination. (c) the switching characteristics of Nb-based devices under illumination from UV to NIR region. The Nb-based devices goes to HRS under illumination by a halogen lamp, of 532, 1064 nm wavelength, shown in (c) and (d) [49].*

behavior of the device at room temperature was explained by photon stimulated electron–phonon scattering. However, at lower temperatures, energy is absorbed by the thin films from the irradiation of light-generated heat in the material. The generated heat increased the effective temperature of Nb thin films, eventually increasing the resistance of thin films. The critical temperature of 8.5 K for the transition of normal metallic Nb thin films to a superconducting state decreases to lower temperatures. The photo-sensing behavior of Nb thin films even in the superconducting state can be exploited for the development of superconducting photodetectors [49, 53, 54].

## **4. Resistance switching devices for neuromorphic computing**

Recently, resistive switching hysteresis has been adopted to mimic the operation of human brain in lab. Human brain can perform multiple operations simultaneously with a fast speed. The brain can process complex and comprehensive information, such as identification, memory, voice analysis and image processing simultaneously with extremely low power consumption (20 W) [55]. In this way, human brain

processes information with much higher efficiency compared to the classical computers based on von-Neuman computation [55–58].

The von-Neuman computation occurs in two different places (central processing unit and memory units) connected by huge number of wires, which becomes a considerable drawback for low power electronics. This necessary requirement of data transfer between the central processing unit (CPU) and the memory units limits the speed and results in increased power consumption in the von-Neuman computing and it is often called as von-Neuman bottleneck [55]. On the other hand, a design of human brain consisting of neurons and synapses offers a better option for fast processing and low power consumption. Efforts have been made to use machine learning software and complementary metal – oxide-based structures have been used to mimic the processing of the human brain. However, this also meets the bottleneck of high-power consumption and the speed of operation, just like the Complementary Metal Oxide Semiconductor (CMOS) architecture in nanoelectronics [56].

Human brain represents a unique architecture where memory and computing take place in the same unit, thereby increasing the data processing ability and reducing the time scale of the information processing. In this way, our brain overcomes the bottleneck of the power consumption compared to the von Neuman. An overview of the brain-inspired neuromorphic device architecture is shown in **Figure 11** - (Adapted from [56]). The independent memory and processing unit connected by physical metallic wires is depicted in **Figure 11(a)**. Since the information storage and processing are performed in separate locations, the processing speed is limited (see **Figure 11(b)**).

The fundamental units of brain computing are neurons and synapses. These are the basis of massive neural networks present inside the human brain. The pre-neuron and post-neuron parts are interconnected via synapses, which offer optimal processing in our brain. The connection strength between two neurons is known as synaptic weight. It is primararily attributed to the volume of neurotransmitter released or absorbed in the biological synaptic action. The action of biological synapses i.e., transmitting of information via electrochemical signal, can be replicated using a two-terminal electronic device, namely a memristor [59]. The two-terminal memristor device can be used to mimic the synapses and neuron combination, as shown in **Figure 11(c)** and **(d)**. Here, the top and bottom electrodes can act as pre and post neurons. The insulating material emulates the biological synapse and the artificial synaptic action is established by modulating the conductance/resistance of the insulating material between these two electrodes. The synaptic actions in neural networks are responsible for advanced activities of the human brain as learning, sensing and remembering. These neural activities are attributed to the synaptic plasticity, which is defined as the synaptic weight modulation ability.

The fundamental rule of synaptic action in the pre-neuron-synapse-post neuron complex is that when the neurons on either side of the synapse are activated simultaneously, then the synaptic weight should increase in the process. This postulate is often referred to as Hebb's rule or sometimes referred to as cell assembly theory [56]. In general, this rule suggests how much the synaptic weight should increase or decrease in proportion to their product when the two neurons are simultaneously activated. The synaptic weight modulation can enhance or depress the connection strength between the two next neurons. This is known as the potentiation or depression of the synapse. For artificial synapse, potentiation can be achieved by positive pulses, and negative pulses can induce depression. Potentiation and depression are the learning and forgetting aspects of artificial neurons [60].

#### **Figure 11.**

*A schematic diagram of the von-Neuman style of computing and the brain inspired computation [56]. (a) The typical memory and processing unit architecture in the classical computers, which has a bottleneck of processing. (b) A sequential computation in von-Neuman style where data are fetched processed and stored, limiting the processing speed and also the power consumption. (c) A neuron based computational procedure. Multiple input output connections via synapse – Neuron building block for neuromorphic computation. (d) A typical neuron – Synapse building block of a neuromorphic device. Here, from the multiple inputs via synapses, the neuron processes the information and gives an output indicated schematically. (e) A biological neuron and synapses connections in human brain.*

Depending on the modification of synaptic weight, synaptic plasticity is classified into short term plasticity (STP) & long-term plasticity (LTP). When the effects of plasticity last for a short period of time, from milliseconds to few minutes, it is known as STP. For LTP, the retention time of modification effects of the artificial synapse is more than several hours. In the biological brain, STP is accountable for the computational processes like learning, while LTP is responsible for learning and memorizing processes. These properties of STP and LTP can be exploited for artificial neural networks (ANN) using volatile and non-volatile memristive devices [57]. However, by continual stimulation of pulses during the computational processes, one can achieve alteration of synaptic plasticity from STP to LTP. STP is further inspected by

paired-pulse facilitation (PPF) and paired-pulse depression (PPD) learning rules. During the synaptic weight modulation process, when two consecutive pre-synaptic spikes stimulate in a short interval of time, the synaptic weight would temporarily increase or decrease. Thus, for PPF the second pre-synaptic spike would produce larger post-synaptic current than the first pre-synaptic spike. Meanwhile, opposite outcome is observed for PPD. Apart from this, synaptic plasticity can also be induced by utilizing the temporal relationship between pre and post synaptic spikes. This phenomenon is known as spike-timing dependent plasticity (STDP) [61].

Two-terminal switching devices include memristors, ferroelectric tunnel junctions (FTJ's) and devices containing phase change materials [62]. In the case of threeterminal devices, these are mainly represented by electrochemical transistors, transistors based on phase change materials and charge trapping transistors [63].

For the design of synapses, the most interesting devices are the memristors, which are trilayer structures with an active material inserted between two metallic electrodes. The dynamic range, multilevel switching and the retention of the memory will determine the quality of the synapse designed. Many materials have been tested for this purpose, as shown in **Table 3**. Although, a variety of active materials have been tested/used in memristive switching devices as indicated in **Table 3**, the research has extensively contributed to the understanding of the fundamental physical mechanisms of the switching process, the switching speed in the devices, as well as designing and fabricating the architecture for the synapse – neuron combination.

The important aspect of these devices is the consistent abrupt transition/switching between high resistance and low resistance states. For an optimal neuromorphic device, a low voltage operation, fast switching and clear distinction between a high resistance state and low resistance state are required. Even though a transistor configuration has been tested for various materials such as Li3POxSex, Li3POxSex, Nafion,


#### **Table 3.**

*Summary of various materials used with hysteretic switching characteristics proposed for neuromorphic computation. The materials are divided into various categories depending on the device fabrication and thickness of the materials used. All the materials are considered from the references listed.*

HfZrOx, Ta2O5/HfZrOx and Al NPs/Al2O3, the operation speed is fairly large compared to the two-terminal devices.

One common signature of a memristor device is the hysteresis of the current – voltage characteristics. The hysteretic behavior indicates that the device has a long saturation time. The long current saturation time helps to use this device as a neuromorphic device at various frequencies. A device which showed excellent hysteresis is based on Metal - Nb2O5-x – Metal junctions, displayed in **Figure 12(a)** and **(b)**. The oxygen vacancies are attributed to the conduction via Nb2O5-x, which are located at 0.2–1.2 eV below the conduction band edge [65]. In this case, the hysteric characteristics are attributed to the long saturation time, which allows a broad range of frequencies for neuromorphic operations that require hysteresis. This device exhibited extremely high capacitance in the low frequency range, where biological process occurs, as shown in **Figure 12(b)** [60]. This is an important feature of the device, which is useful for mimicking the biological process in the laboratory. A similar device performance was seen in a TiOx nanowire device, as shown in **Figure 12(c)** and **(d)** [60]. These devices could be controlled in the intermediate states of resistance, which is an essential part of the neuromorphic devices. The TiO2 and Nb2O5 based devices represent typical examples of memdiodes to be used in the brain-inspired computation.

#### **Figure 12.**

*(a) Typical current – Voltage characteristics of metal – Nb2O5 –metal memdiode [65]. Frequency-dependent capacitance indicates extremely high capacitance where the biological processes occur. (b) The capacitance remains almost constant until the threshold voltage is reached. Subsequently, the capacitance decreases, and conductance increases as expected. In the lower row, a device based on TiOx single nanowire is shown. (c) A small hysteresis can be seen in the low voltage regime indicating a possible operating voltage range for memristors. (d) The endurance performance is shown on the right.*

## **4.1 2D materials for neuromorphic computation**

While the heterostructures and epitaxial structures have been studied for their possible application in neuromorphic computations, the low-dimensional materials have attracted attention for this purpose [66].

Materials like graphene, chalcogenides, and hexagonal boron nitride have been tested for their functionality in brain-inspired computation architectures. Recently, neuromorphic systems based on organic polymers have also been tested [67, 68]. Their intrinsic low dimensionality gives an added advantage with respect to their mechanical stability and tunability of the electronic properties. The 2D materials can be integrated into the heterostructure and transistor-type design to get desirable neuromorphic characteristics. Among two-dimensional materials, graphene, and its derivatives with extremely high carrier mobilities are used as electrodes, while systems belonging to the hexagonal boron nitride family with large electronic energy band gap are promising candidates for neuromorphic architectures.

The large band gap of hexagonal boron nitride at the monolayer thickness limit is extremely important for reliable switching characteristics of the heterostructures. Transition metal-chalcogenides are another class of 2D materials that offer wide variety of properties such as semi-metallic and semiconducting behavior. All these 2D materials maintain crystallinity and consequently the electrical characteristics will be more reliable compared to their oxide counterparts in the heterostructures. The existence of crystallinity at low-dimensional scale is essential for faster switching and low energy operations. **Figure 13** displays an overview of the use of 2D materials for neuromorphic computation. Clearly, 2D materials have an advantage over the thin film counterparts since it is possible to intrinsically get materials with a variety of energy gap, as shown in **Figure 13**. With 2D materials, devices can be fabricated in the form of stacked layers, which will give exotic properties and low operating voltages.

### **Figure 13.**

*Overview of the low dimensional materials used for the resistive switching devices [66]. (a) The option of choosing 2-dimensional materials from graphene (no energy gap) to h-BN (6 eV) gives added advantage in various device structures. (b) Since the materials are in lower dimensions, they will have advantages compared to the bulk materials in terms of the flexibility, low power consumption and most importantly, atomically flat surfaces. (c) Various types of the switching processes attributed to the resistive switching memory devices using the low dimensional materials.*

## *Resistive Switching and Hysteresis Phenomena at Nanoscale DOI: http://dx.doi.org/10.5772/intechopen.101500*

One of the 2D materials commonly used for hysteric resistive switching is hexagonal boron nitride (h-BN), and extensive research is currently being carried out on this material. The h-BN offers a multitude of applications; for example, it can be used as an insulator for a classical transistor design using 2D materials, and a host material for qubits. Having an intrinsic large energy gap, h-BN can form an integral part of the nanoscale 2D transistor design replacing the traditional oxides needed for controlling the ON/OFF states of a transistor (for example, in graphene or MoS2 based transistors). Further, h-BN also finds importance in the design of quantum bits (QUBITS) for futuristic quantum computation. Nitrogen and Boron vacancies, as well as other defect complexes in h-BN [61, 69–71] have attracted attention due to the possibility of using them as qubits. Recent transmission electron microscopy studies reveal that at the breakdown electric field strength, the electrode metal ions diffuse through the layers creating a conduction path, giving rise to a low resistance state.

#### **Figure 14.**

*The mechanism of resistive switching in devices using 2-D materials is schematically shown. The switching can originate from various mechanisms like ionic migration, phase change and the spin flip as indicated as shown in (a). (b) A MoS2 based neuromorphic device. Transmission Electron micrograph shows clear few layer MoS2 sandwiched between Au electrodes. This device shows a clear SET-RESET process with well-defined ON and OFF states. (c) A switching device from MoS2/MoO3heterostructure. Even though, the hysteresis is small, the device clearly shows a resistive switching as shown in (d).*

Recently, MoS2 double-layer devices have shown spike-timing dependent plasticity (STDP), which is clearly dependent on the hysteretic resistive switching characteristics, as shown in Cu-MoS2-Au devices [72–74]. On the other hand, the memristor (hysteretic) behavior of monolayer MoS2/WO3 heterostructure has also been studied for neuromorphic devices [73]. The resistive switching characteristics of these heterostructures based on 2-dimensional materials can be explained using similar processes observed in the traditional devices, including ion migration and phase change. However, a new phenomenon of spin-flipping is found to be responsible for the resistive switching behavior [71]. **Figure 14(a)** shows the schematic representation of the ion migration, phase change and the spin flipping, which might cause a resistive switching in low dimensional materials and heterostructures. Again, the device configuration is similar to that of the normal trilayer structures containing the active material between the two metal electrodes. An example of such structure, which shows clear resistive switching with clear hysteresis, is represented by the Au/ MoS2/Au system, shown in **Figure 14(b)**. The layer of MoS2 is sandwiched between Au electrodes as shown in the transmission electron microscopy images, and a very sharp interface can be seen between Au-MoS2 on both sides. This device shows a clear bipolar switching as reported in **Figure 14(b)**. Even though the interfaces are separated by atomic distances, the threshold voltage is still about 1 V giving a huge promise for nanoscale, low power memory applications. Similarly, as shown in **Figure 14(c)** and **(d)**, the WSe2/Graphene heterostructure also shows promising switching properties with hysteresis. Further optimisation of device geometry and operating conditions will yield a better switching performance in these heterostructures.

## **5. Conclusion**

Overall, the future of nanoelectronics and neuromorphic computation revolves around two primary objectives. Firstly, newer materials, heterostructures, and multilayers should be designed to get optimum device performance. The materials used in lab-scale devices should be stable and robust, so that performance would remain acceptable even in the large-scale integration. This will enable not only saving information, but also processing information. The design of materials should address various issues, such as quantum mechanical tunneling of electrons, intrinsic and process-induced defects related to nanoscale and atomic scale devices. These parameters will affect the performance of the devices at the nanoscale. Secondly, the device architecture should be such that these new devices should be compatible to the already optimized device integration and manufacturing. Design aspects should also consider optimizing from the point of view of multiple applications. In this chapter, we have given an overview and discussed materials and devices related to memory applications displaying hysteresis in the current–voltage characteristics. These devices are proposed to be used in low-power nanoscale memory devices and possibly used in the case of neuromorphic computation.

## **Acknowledgements**

Authors thank Vellore Institute of Technology (VIT, VELLORE), India for providing 'VIT SEED GRANT' for carrying out this research work.

## **Conflict of interest**

The authors declare that they have no known competing financial interests or personal relationships that could have appeared to influence the work reported in this book chapter.

## **Author details**

Vithaldas Raja<sup>1</sup> and Ramesh Mohan Thamankar<sup>2</sup> \*

1 Department of Physics, School of Advanced Sciences, Vellore Institute of Technology, Vellore, India

2 Centre for Functional Materials, Vellore Institute of Technology, Vellore, India

\*Address all correspondence to: rameshm.thamankar@vit.ac.in

© 2022 The Author(s). Licensee IntechOpen. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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## *Edited by Hai-Zhi Song, Kim Ho Yeap and Magdalene Wan Ching Goh*

As a fundamental aspect of science and technology, the electromagnetic field has infiltrated most human activities. This book reviews recent achievements in electromagnetic field theory, in the scientific research driven by the electromagnetic field, and in the application of the electromagnetic field in advanced technology. Theoretical aspects of the electromagnetic field are examined in detail and new interpretations of the basic interactions related to magnetic fields are proposed. Among the scientific research topics reviewed, new understandings are achieved of longdistance wireless power transfer, nerve impulses, and electromagnetic diagnosis mechanisms. A new concept of the electric field at the verge of discharge is applied to the electric fields produced by any distribution or structure of electric charges in clouds. The detailed relationship between materials and microwave electromagnetic fields is described in order to achieve fine control of the chemical reaction field in materials under microwave irradiation. Electromagnetic power consumption in microelectronic devices is carefully analysed, enabling power saving in CMOS/FinFET circuits. The effective use of 2D materials in newly developed electronic, electromagnetic resistive switching devices is investigated.

Published in London, UK © 2023 IntechOpen © Cappan / iStock

Electromagnetic Field in Advancing Science and Technology

Electromagnetic Field

in Advancing Science

and Technology

*Edited by Hai-Zhi Song, Kim Ho Yeap* 

*and Magdalene Wan Ching Goh*