**3. Roles of reconfigurable platforms**

Over the past years, the semiconductor enterprise has consistently reduced the size of its devices while increasing their power and efficiency. Moore's Law drove down the cost per transistor dramatically each time the total number of transistors created was duplicated (approximately 45%) [36]. The pace with the fast demand for quicker and smaller goods has driven this technology to its limitations, making it increasingly hard to rise the density of transistors on a chip also its operating frequency, that appears to be nearly saturated [21]. This Moore's Law deceleration raises several

*Future Internet of Things: Connecting the Unconnected World and Things Based on 5/6G… DOI: http://dx.doi.org/10.5772/intechopen.104673*

challenges for system designers, who expected better performance-to-energy ratios from each new generation of devices. This technical deadlock has prepared the way for the introduction of reprogramed platforms (i.e., FPGA-based platforms) as a novel hardware method to addressing these difficulties across a wide range of on-board use areas [5, 15].

**Figure 2** illustrates the various software and hardware architectures that are now available on the market and commonly employed in the creation of embedded systems [21]. Microcontrollers (MCUs) provide the most flexibility, whereas ASICs (application-specific integrated circuits) offer the maximum performance. FPGA-based solutions, on the other hand, could offer the best of both worlds by providing high crippled processing abilities, leading in greater performance raise than MCUs and the ability to be reprogrammed at any moment. In comparison to ASICs, over time execution via partial or dynamic reconfiguration techniques provides greater flexibility. However, because MCUs are software devices, they offer best flexibility, making them useful in basic, low-cost embedded systems [38].

FPGA manufacturers have begun to integrate embedded processors (soft or hard) into their gadgets in recent years, leading to so-called Field Programmable Chip Systems (FPGA SoC), which have emerged as the world's greatest option for balancing flexibility with efficient computing power. FPGA SoCs have progressed from a single or dual-core processor-only platform to a far more powerful platform with graphics processing units (GPUs), real-time processors, multi-core processors, real-time processors and specialized hardware blocks such as digital signal processors (DSPs) and video compression components. With this varied array of resources ranging from systems that are efficient intended at high-end applications to a better resource-constrained platform, these heterogeneous reprogrammed technologies are better technical options for dealing with the ever-increasing diversity of Low-end IoT applications. Nevertheless, depending on the target context and uses situation, each IoT deployment may use a distinct network data and transmission architecture, technology and design processes that are widely used, based on the general requirements imposed by the environment's natural evolution the IoT ecosystem.

### **3.1 Connectivity and interoperability**

Hardware-assisted technologies that can speed widely recognized protocols and standards at the network edge are steadily resolving connectivity and interoperability problems in reconfigurable systems. For example, some data privacy-related

**Figure 2.** *Performance versus flexibility of different processing platforms.*

communication operations (e.g., authentication, data encryption/decryption) take quite a long time and cost a lot of power. Offloading such activities to hardware (e.g., cryptographic protocols and algorithms) can result in improved performance-topower tradeoffs. Gomes et al. [39] suggested a 6LoWPAN accelerator that can analyze and filter packets received by a radio transceiver. When compared to software filtering, the findings demonstrated a nearly 13.24% reduction in performance overhead. In addition to speeding up these computing operations, reconfigurable systems can help to reduce the obsolescence of cryptographic primitives through dynamic partial reconfiguration (DPR) [40]. Furthermore, some IoT-based applications have consistently employed FPGAs for networking reasons and obtained promising results in recent years, fostering the growth of different solutions in the industry. In [38], Andina et al. discussed many research that demonstrate the benefits of employing FPGAs to tackle connectivity challenges on IoT systems.

The growth of software-defined radio systems has coincided with the evolution of radio communications (SDR). An SDR is a radio communication system in which standard FPGA hardware components (e.g., mixers, filters, amplifiers, modulators/ demodulators, detectors) are integrated in software. Indeed, this method facilitates the generation of smart communication strategies with great usefulness in a variety of sectors (e.g., mobile phones or military applications), where protocols and radio settings (e.g., new modulation designs, filters) may be modified in real time. The benefits of reprogrammable platforms paired with the SDR paradigm give up a new pair of possibilities in which new hardware modules (specified in software but speeded in hardware) may be developed and dynamically installed on reconfigurable systems using DPR [41, 42].

#### **3.2 Intelligence**

The current trend to solve the problems of excess information created at the edge and latencies engendered by its transmission through the network has given rise to the concept of edge computing, in which the edge node uses AI, specifically deep learning methodologies, to properly accomplish data analysis at the source. Because of their inherent parallel compilation ability and performance per watt benefits, FPGA-based platforms are well suited to address AI needs in this situation. By offering hardwareaccelerated inference techniques, these systems can fulfill the strict effectiveness and power restrictions of edge devices.

The latest generation low density FPGAs, such as the Xilinx 7000 family, can speed neural networks in the 1 W to 1 mW region. Each FPGA series has a convolutional neural network (CNN) accelerator that may be configured for accuracy or power consumption [20]. In comparison to previous platforms, Intel's new FPGA SoC combine DSP blocks with unique floating point capabilities into the FPGA fabric, considerably reducing logic resources consumption and improving overall performance [9]. To be fair, the high computational storage and power capacities requirement of classic neural network designs continue to confront even the newest FPGA-based platforms.

While the market has recently lauded FPGAs' capabilities for AI acceleration, academia has as well thoroughly researched this subject, presenting many accelerators and demonstrating interesting results. In [43] the authors developed a low-precision CNN accelerator that delivered about the precision of a standard CNN while outperforming other tasks by up to 6 times. The authors of [43] developed a CNNbased image classifier accelerated on a high-end FPGA SoC that investigates both the integrated hardcore and the FPGA fabric holistically. When compared to standard

*Future Internet of Things: Connecting the Unconnected World and Things Based on 5/6G… DOI: http://dx.doi.org/10.5772/intechopen.104673*

hardware platforms, the solution achieves outstanding performance/power consumption ratios (e.g., CPU, GPU). Other similar papers offer techniques based on hardware accelerated AI as well. In the works cited in [44], the results presented make it possible to accelerate the performance of 4x compared to other solutions while reducing energy consumption. Although the Deep Learning Accelerator written in OpenCL is capable of accelerating AlexNet up to 10 times quicker than the different leading edge approaches. From another point of view, the authors of [45] have proposed a series of efficient design techniques (p. To meet the limitations of devices with limited resources. A common element in all these works is that solutions based on FPGA strike a true balance between compute performance and energy efficiency. Furthermore, these platforms are the only option capable of continuously adapting to the high speed of development in AI frameworks, both in terms of algorithm implementation and performance/power needs for future generation workloads.

#### **3.3 Security**

IoT system security is a critical necessity. The attack vector spectrum is expanding, and IoT system developers want solid and very secure countermeasures to efficiently protect the upcoming devices generation. Faced with today's security demands, new reconfigurable systems include a variety of security blocks ranging from core hardware encryption engines.

The basic functions include numerous techniques that support greater security standards, as aa example we mention data encryption/decryption before performing data transmission. The latest generation of FPGAs provide a diverse set of integrated, hardware-accelerated blocks and cryptographic resources (e.g., ECC, AES, SHA, and HMAC). Microsemi's SmartFusion, SmartFusion2, and IGLOO2 devices, for example, provide hardware accelerators for AES-128/256 and SHA-256, that may be utilized for performing design also data security (e.g., to validate the integrity and authenticity of a bit stream). In addition, the advantages of employing FPGA-based cryptographic accelerators have been extensively discussed in the literature; Piedra et al. [46] compared the performance and power consumption of cryptographic primitives in commercial IoT nodes to an FPGA-based cryptographic accelerator. The outcomes shown that the latter technique may significantly improve the execution time of sophisticated cryptographic algorithms, and hence power consumption. Another feature of FPGA-based cryptographic systems is their inherent reconfigurability, that may be used to simply upgrade limited or obsolete cryptographic algorithms and protocols.

A TRNG block is necessary to support cryptographic engines. It generates random cryptographic keys from a statistically independent source of random values. While exhibiting many physical sources of entropy (e.g., clock jitter, thermal noise, shot noise, etc), FPGA-based TRNGs may as well attain ideal high-speed ratios and function as a source of truly random numbers [47]. Newer FPGA-based applications, such as Microsemi's FPGA SoC, are also equipped with a non-deterministic TRNG that is certified to handle cryptographic applications. The protected root keys, which must be uniquely tied to the device, are another important feature of the basic function class [31]. Today's cutting-edge implementation depends on PUF technology, which, due to unavoidable differences in the nanoscale manufacturing process, makes PUFs a viable physical device attribute for generating a peculiar silicon fingerprint [48]. Root keys created from PUFs are fetched from the chip rather than kept on it. PUFs are now present in a wide range of devices, from small sensors and microcontrollers to FPGA-

based systems. PUF-based applications in [49] serve as a means for security software on an MCU as well as a basis for authenticating IoT devices in the cloud. On contrast [50], proposes a secure protocol based on PUF to secure a DPR compliant IoT design deployed in FPGA.

The wide system solutions that provide secure primitives at the CPU level provide platform security as well as access control to system components (e.g., FPGA blocks, peripherals, memory). Arm, the dominating architecture in the mobile and in-vehicle categories (with 50 billion devices deployed), launched the most powerful current platform security mechanism, Arm TrustZone, in 2014. Arm TrustZone is a hardware security system that covers both low and high-end Arm CPUs. The later provides a compartmentalized method to security by giving two hardware-reinforced regions of protection: secure and regular worlds. The different worlds are totally separated from hardware and have uneven privileges, preventing insecure software from immediately accessing secure global components. The Trust Zone bit is not contained within the CPU; it extends from the processor to the bus to the hardware's internal circuitry, Zynq-based FPGA SoC are a great example. This technology has been widely employed in academia and business as a significant enabler for the use of Trusted Execution Contexts (TEEs) and to offer strict isolation (security by separation) in critical environments.

#### **3.4 Energy**

Users would expect tinier, smarter, and longer-lasting IoT items offered by ultralow power IT-optimized solutions. FPGAs have lowered power consumption per operation by more than a factor of 1000 since their introduction [51]. These advancements have been driven mostly by process technology and the desire to reach new markets, particularly the consumer sector. Power concerns are now at the forefront of FPGA architecture considerations, and newly FPGA categories are all geared towards low-cost, high-volume applications. The majority of FPGAs are based on SRAM technology, which necessitates extra non-volatile memory to keep their configuration pattern, increasing power consumption. Nonetheless, these platforms have changed significantly over time, and newer devices are more energy effective. For example, Lattice's iCE40 family of FPGAs can operate at 10 mA in active mode and up to 35 μA in standby mode. Due to the uncertain initial state of the SRAM cells, Lattice systems are prone to spikes in starting current (inrush current) like SRAM-based FPGAs. iCE FPGAs, on the other hand, have a maximum inrush current of 1.2 mA, which is a very high efficient number for battery-powered uses.

Flash FPGAs have always fallen behind SRAM-based devices in regards of performance, density, and on-chip IP. Although, new developments in flash technology (e.g., flash memory cell reduction, flash memory integration into advanced logic operations) have dramatically increased these platforms. This technique has a very low static energy consumption as well as minimal inrush and setup power. Microsemi FPGAs investigate flash memory. The IGLOO series, specifically developed for today's portable and energy efficient devices, may deliver standby power consumption rates as low as 2 μW in their FPGA portfolio. Furthermore, Microsemi's FPGA SoC have Flash \* Freeze technology, that places the FPGA design in a low-power sleep mode while maintaining the prior state of memory, enabling for quick FPGA shutdown and restart. Sensor arrays, which are invariably turned on and off on a regular basis, might benefit immensely from this feature. Furthermore, a system designer may take use of the extra combination of such technology with other low power modes provided by

*Future Internet of Things: Connecting the Unconnected World and Things Based on 5/6G… DOI: http://dx.doi.org/10.5772/intechopen.104673*

the integrated hard-core MCU to fulfill the rigorous energy requirements of numerous IoT applications.

To improve energy efficiency, some solutions incorporate a dynamic power management (DPM) module in their reconfigurable hardware, that permits individual resources to be totally turn off in standby or low power mode, as well as a reset function. The voltage and frequency dynamic scales used to govern the digital processing component. The later function is a power management approach that allows the voltage and speed of the MCU to be altered and decreased to lower levels when not in use to reduce power consumption. Furthermore, reconfigurable solutions appear to be an excellent option for heterogeneous grains of low power by studying low consumption operating partners with extremely low static power consumption also employing a DPM system paired with DVFS approaches [52].

#### **3.5 Combination of reconfigurable platforms and IoT Motes**

The platforms based on FPGA are quite diverse, extending from compact form dimensions, ultra-low power consumption, and production-priced solutions to fully SoC-enabled platforms with considerable hardware resources to fulfill customer nominations this days. This technology, which has a high level of maturity, is a good option for designing personalized solutions for wireless detecting uses. The authors of [53] have published a complete survey addressing a wide range of hardware devices available for low-end IoT mobiles. By providing numerous solutions based on standalone FPGA platforms or heterogeneous designs that integrate an MCU and an FPGA, this paper focuses on the rising focus in researching reprogrammed architectures used in this industry. FPGA-based designs have permit the optimization of numerous components of wireless sensors in aspects of performance and power consumption, while some work has also boosted device security.

Several methods aimed at wireless sensor systems have previously been presented, including PowWow [54], CookiesWSN [37], HaLoMote, and CUTE mote [55]. In these references, the recent state of the art, are well highlighted, on low-end IoT motes which leverage reprogrammable technology on their design, describing their variations from previously recognized CGUs, in addition their most essential qualities and attributes: network accelerators available, radio device used, SoC adopted, MCU design, local security related hardware/software, application specific accelerators, and maturity level. PowWow and CookiesWSN are the first low-end motes implementations that integrate a low-power MCU (TIMSP430) with a tiny low-power Flash FPGA as well as a radio transceiver. The first solution looks into using the FPGA to build low-level network-bound accelerators such forward error correction (FEC) methods. PowWow investigates energy management approaches to manage the digital processing element in order to enhance energy efficiency. While both feature an Elliptical Curve Cryptography Accelerator (ECC), CookiesWSN adds an applicationspecific Sensor Data Processing Accelerator (SDP) as well as a reprogrammed Kalman filter to reduce noisy samples in the process of data acquisition processing. Despite the major accomplishments of PowWow and CookiesWSN, the utilization of discrete MCU and radio frequency (RF) components resulted in slower communications and worse power efficiency.

Recent alternatives, such as HaLoMote and CUTE mote, have solved some of the previous methods' limitations. HaLoMote, a hardware-accelerated low-power mote aimed at IoT, combines an RF-SoC transceiver (ATmega256RFR2) with a Microsemi IGLOO M1AGL1000 crawled to speed up massive computation tasks mentioning sensor data aggregation in an SDP. Furthermore, the system offers a DPM accelerator, which enables low power standby modes with extremely low static power consumption, resulting in decreased power consumption. The CUTE mote, on the opposite, is described as a programmable and dependable terminal device that is specifically built for low power IoT applications. The design is implemented on an FPGA SoC (Microsemi martFusion2) platform, which combines an Arm Cortex-M3 hardcore MCU closely linked with a Flash-based FPGA and an externally connected IEEE 802.15.4 radio transceiver. Offloaded hardware accelerators are provided as hardware devices to the MCU and are accessed using a standard on-chip communication protocol, which simplifies design and minimizes access time. The contribution in [55] used a micro-positioning measurement system to evaluate and install their platform. A specific application SDP, a root mean square (RMS) statistical procedure for information evaluation and analysis a Fast Fourier Transform (FFT) method for digital differential signal processing, a finite impulse response (FIR) filter for signal processing, and other signal and image compression techniques have been used. Other relevant contributions in this field [56], despite being at a low maturity level, analyze significant improvements in reprogrammed systems dedicated for FPGA-based wireless sensing uses and conforming to standards, Low-end IoT, where it is still suggested to deploy specific, network, and security related tasks in the FPGA. Although they contribute to a common vision, some contributions are still in the design phase.

Despite variations on multiple levels, all of the prior studies referenced have a common point of view, that we defend through the following chapter: Indeed, in the future of IoT-enabled devices reconfigurable platforms will make a crucial role, where essential problems like as connection and interoperability, cutting-edge AI, hardware and energy efficiency and data security, will surely keep being the top trends and difficulties for future low-end IoT Words.
