**4. Pipelined SMS4-BSK cryptosystem**

The pipelining is implemented in the encryption architecture of the SMS4-BSK cryptosystem. The pipelined encryption architecture of the SMS4-BSK cryptosystem is shown in **Figure 7**. A latch is introduced between every processing step. The processing delay of every step in the encryption architecture is different. So, the step with a higher processing delay may affect the encryption speed and throughput. By implementing a

**Figure 7.** *Pipelined SMS4-BSK encryption architecture.*

latch between every processing step, it will be possible to balance the data access rate at each step. The pipelined SMS4-BSK cryptosystem is developed in Xilinx Vivado 2017 Design Suite using Verification Logic Hardware Description Language (Verilog HDL) and implemented in Kintex-7 Field Programmable Gate Array (FPGA).

The Kintex-7 FPGA with the Device Name: XC7K410T and the Package: FBG676 is used to implement the cryptosystem. The number of Input and Output Buffers (IOB) available in the package are 400 and the requirement of the cryptosystem is 386. The synthesis report generated notes the timing summary and the area utilized by design. **Figure 8** shows the technology schematic of the pipelined SMS4-BSK obtained from the Xilinx Vivado 2017 Design Suite. The simulated timing diagram of the pipelined SMS4-BSK cryptosystem is shown in **Figure 9**.

*Perspective Chapter: The Importance of Pipeline in Modern Cryptosystem DOI: http://dx.doi.org/10.5772/intechopen.102983*


#### **Figure 9.**

*Simulated timing diagram of the pipelined SMS4-BSK encryption architecture.*


#### **Table 1.**

*Comparison of pipelined SMS4-BSK with other SMS4 cryptosystems.*

The throughput of the Pipelined SMS4-BSK algorithm is calculated using Eq. (10).

$$\text{Throughput} = \frac{B \, Xf}{N} \tag{10}$$

Where B is the message block size (128 bit), f is the clock frequency (464 MHz) and N is the effective number of clock cycles utilized (6 Clock cycles).

∴ Throughput ≈ 9.9 Gbps.

The performance of the Pipelined SMS4-BSK encryption architecture is compared with the other SMS4 architecture and tabulated in **Table 1**. It is evident from **Table 1** that the throughput of the Pipelined SMS4-BSK cryptosystem is far better than other cryptosystems.

## **5. Conclusion**

In this chapter, the implementation of the pipeline in the modern SMS4-BSK cryptosystem is discussed. The SMS4-BSK cryptosystem is more robust, has a large Keyspace, has optimum Key Sensitivity and Plaintext Sensitivity, is faster, has high throughput and can resist all the four major cryptanalysis attacks. The throughput of the SMS4-BSK cryptosystem is further improved to 9.9 Gbps by implementing a pipeline in the encryption architecture. The comparison of throughput of the various architectures of the SMS4 cryptosystem is shown in **Table 1**. It is evident from **Table 1** that the pipelined design of the SMS4-BSK cryptosystem has higher throughput. All the designs are implemented in Kintex-7 FPGA for comparison.

As a future enhancement, the pipeline implementation can be extended to the Key Scheduling architecture to improve the throughput further. A novel BM S-Box is being designed to replace the BSK processing block (Non-linear Transformation Block) of the SMS4-BSK cryptosystem to improve the speed and throughput.
