**5. Hardware implementation of the proposed hybrid cryptosystem**

The suggested hardware architecture is performed with reduced resources that the embedded system makes available. Al cryptographic functions are required to design the hybrid secure framework operated in 32 bits datapath. In our design, six essential blocks are performed with the Control Unit, AES block, the RSA block, keccak block, and I/O buffer for 32-bit data bus. The control unit controls all algorithms and the information exchanged from external devices. Buffer in and buffer out are necessary for communicating the data from and to the on-chip bus. The AES block is used for data encryption and decryption. The keccak block is designed for hashing the message and finally, the RSA block is performed for the signature generation and verification. The proposed hardware architecture is given in **Figure 6**.

The suggested hybrid cryptographic framework is implemented on the DE2–115 board featuring Cyclone IV.E FPGA. **Table 1** gives the utilization of resources when synthesized by the Quartus II tools. The system necessitates 80% of logic elements, 79% of combinational functions, 27% of logic registers, and 7% of memory and consumes 226.15 mW. Concluding the obtained results, the proposed cryptosystem hardware design occupies a small hardware area and consumes reduced power. Thus, the proposed cryptosystem meets the constraints of onboard systems.

**Figure 6.** *Hardware architecture of the proposed cryptosystem.*

*Hardware Implementation of an Improved Hybrid Cryptosystem for Numerical Image Encryption… DOI: http://dx.doi.org/10.5772/intechopen.105207*


#### **Table 1.**

*Hardware resources results.*
